if_bge.c revision 1.224
1 /* $NetBSD: if_bge.c,v 1.224 2013/03/23 19:40:43 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.224 2013/03/23 19:40:43 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int); 254 static void bge_miibus_writereg(device_t, int, int, int); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5724, 440 "Broadcom BCM5724 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5750, 444 "Broadcom BCM5750 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5750M, 448 "Broadcom BCM5750M Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751, 452 "Broadcom BCM5751 Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5751F, 456 "Broadcom BCM5751F Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5751M, 460 "Broadcom BCM5751M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5752, 464 "Broadcom BCM5752 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5752M, 468 "Broadcom BCM5752M Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753, 472 "Broadcom BCM5753 Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5753F, 476 "Broadcom BCM5753F Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5753M, 480 "Broadcom BCM5753M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5754, 484 "Broadcom BCM5754 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5754M, 488 "Broadcom BCM5754M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5755, 492 "Broadcom BCM5755 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5755M, 496 "Broadcom BCM5755M Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5756, 500 "Broadcom BCM5756 Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761, 504 "Broadcom BCM5761 Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761E, 508 "Broadcom BCM5761E Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5761S, 512 "Broadcom BCM5761S Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5761SE, 516 "Broadcom BCM5761SE Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5764, 520 "Broadcom BCM5764 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5780, 524 "Broadcom BCM5780 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5780S, 528 "Broadcom BCM5780S Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5781, 532 "Broadcom BCM5781 Gigabit Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5782, 536 "Broadcom BCM5782 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5784M, 540 "BCM5784M NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5785F, 544 "BCM5785F NetLink 10/100 Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5785G, 548 "BCM5785G NetLink 1000baseT Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5786, 552 "Broadcom BCM5786 Gigabit Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787, 556 "Broadcom BCM5787 Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5787F, 560 "Broadcom BCM5787F 10/100 Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5787M, 564 "Broadcom BCM5787M Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5788, 568 "Broadcom BCM5788 Gigabit Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5789, 572 "Broadcom BCM5789 Gigabit Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5901, 576 "Broadcom BCM5901 Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5901A2, 580 "Broadcom BCM5901A2 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5903M, 584 "Broadcom BCM5903M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM5906, 588 "Broadcom BCM5906 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM5906M, 592 "Broadcom BCM5906M Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57760, 596 "Broadcom BCM57760 Fast Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57761, 600 "Broadcom BCM57761 Fast Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57762, 604 "Broadcom BCM57762 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57765, 608 "Broadcom BCM57765 Fast Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57766, 612 "Broadcom BCM57766 Fast Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57780, 616 "Broadcom BCM57780 Fast Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57781, 620 "Broadcom BCM57781 Fast Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57782, 624 "Broadcom BCM57782 Fast Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57785, 628 "Broadcom BCM57785 Fast Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57786, 632 "Broadcom BCM57786 Fast Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57788, 636 "Broadcom BCM57788 Fast Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57790, 640 "Broadcom BCM57790 Fast Ethernet", 641 }, 642 { PCI_VENDOR_BROADCOM, 643 PCI_PRODUCT_BROADCOM_BCM57791, 644 "Broadcom BCM57791 Fast Ethernet", 645 }, 646 { PCI_VENDOR_BROADCOM, 647 PCI_PRODUCT_BROADCOM_BCM57795, 648 "Broadcom BCM57795 Fast Ethernet", 649 }, 650 { PCI_VENDOR_SCHNEIDERKOCH, 651 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 652 "SysKonnect SK-9Dx1 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_3COM, 655 PCI_PRODUCT_3COM_3C996, 656 "3Com 3c996 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PW008GE4, 660 "Fujitsu PW008GE4 Gigabit Ethernet", 661 }, 662 { PCI_VENDOR_FUJITSU4, 663 PCI_PRODUCT_FUJITSU4_PW008GE5, 664 "Fujitsu PW008GE5 Gigabit Ethernet", 665 }, 666 { PCI_VENDOR_FUJITSU4, 667 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 668 "Fujitsu Primepower 250/450 Gigabit Ethernet", 669 }, 670 { 0, 671 0, 672 NULL }, 673 }; 674 675 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 676 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 677 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 678 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 679 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 680 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 681 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 682 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 683 684 static const struct bge_revision { 685 uint32_t br_chipid; 686 const char *br_name; 687 } bge_revisions[] = { 688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 743 /* 5754 and 5787 share the same ASIC ID */ 744 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 745 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 746 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 747 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 748 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 749 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 750 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 751 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 752 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 753 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 754 755 { 0, NULL } 756 }; 757 758 /* 759 * Some defaults for major revisions, so that newer steppings 760 * that we don't know about have a shot at working. 761 */ 762 static const struct bge_revision bge_majorrevs[] = { 763 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 764 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 765 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 766 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 767 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 768 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 769 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 772 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 773 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 774 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 775 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 776 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 777 /* 5754 and 5787 share the same ASIC ID */ 778 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 779 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 780 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 781 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 782 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 783 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 784 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 785 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 786 787 { 0, NULL } 788 }; 789 790 static int bge_allow_asf = 1; 791 792 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 793 bge_probe, bge_attach, NULL, NULL); 794 795 static uint32_t 796 bge_readmem_ind(struct bge_softc *sc, int off) 797 { 798 pcireg_t val; 799 800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 801 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 802 return 0; 803 804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 805 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 806 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 807 return val; 808 } 809 810 static void 811 bge_writemem_ind(struct bge_softc *sc, int off, int val) 812 { 813 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 817 } 818 819 /* 820 * PCI Express only 821 */ 822 static void 823 bge_set_max_readrq(struct bge_softc *sc) 824 { 825 pcireg_t val; 826 827 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 828 + PCI_PCIE_DCSR); 829 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 830 switch (sc->bge_expmrq) { 831 case 2048: 832 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 833 break; 834 case 4096: 835 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 836 break; 837 default: 838 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 839 break; 840 } 841 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 842 + PCI_PCIE_DCSR, val); 843 } 844 845 #ifdef notdef 846 static uint32_t 847 bge_readreg_ind(struct bge_softc *sc, int off) 848 { 849 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 850 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 851 } 852 #endif 853 854 static void 855 bge_writereg_ind(struct bge_softc *sc, int off, int val) 856 { 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 859 } 860 861 static void 862 bge_writemem_direct(struct bge_softc *sc, int off, int val) 863 { 864 CSR_WRITE_4(sc, off, val); 865 } 866 867 static void 868 bge_writembx(struct bge_softc *sc, int off, int val) 869 { 870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 871 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 872 873 CSR_WRITE_4(sc, off, val); 874 } 875 876 static void 877 bge_writembx_flush(struct bge_softc *sc, int off, int val) 878 { 879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 880 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 881 882 CSR_WRITE_4_FLUSH(sc, off, val); 883 } 884 885 /* 886 * Clear all stale locks and select the lock for this driver instance. 887 */ 888 void 889 bge_ape_lock_init(struct bge_softc *sc) 890 { 891 struct pci_attach_args *pa = &(sc->bge_pa); 892 uint32_t bit, regbase; 893 int i; 894 895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 896 regbase = BGE_APE_LOCK_GRANT; 897 else 898 regbase = BGE_APE_PER_LOCK_GRANT; 899 900 /* Clear any stale locks. */ 901 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 902 switch (i) { 903 case BGE_APE_LOCK_PHY0: 904 case BGE_APE_LOCK_PHY1: 905 case BGE_APE_LOCK_PHY2: 906 case BGE_APE_LOCK_PHY3: 907 bit = BGE_APE_LOCK_GRANT_DRIVER0; 908 break; 909 default: 910 if (pa->pa_function != 0) 911 bit = BGE_APE_LOCK_GRANT_DRIVER0; 912 else 913 bit = (1 << pa->pa_function); 914 } 915 APE_WRITE_4(sc, regbase + 4 * i, bit); 916 } 917 918 /* Select the PHY lock based on the device's function number. */ 919 switch (pa->pa_function) { 920 case 0: 921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 922 break; 923 case 1: 924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 925 break; 926 case 2: 927 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 928 break; 929 case 3: 930 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 931 break; 932 default: 933 printf("%s: PHY lock not supported on function\n", 934 device_xname(sc->bge_dev)); 935 break; 936 } 937 } 938 939 /* 940 * Check for APE firmware, set flags, and print version info. 941 */ 942 void 943 bge_ape_read_fw_ver(struct bge_softc *sc) 944 { 945 const char *fwtype; 946 uint32_t apedata, features; 947 948 /* Check for a valid APE signature in shared memory. */ 949 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 950 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 951 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 952 return; 953 } 954 955 /* Check if APE firmware is running. */ 956 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 957 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 958 printf("%s: APE signature found but FW status not ready! " 959 "0x%08x\n", device_xname(sc->bge_dev), apedata); 960 return; 961 } 962 963 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 964 965 /* Fetch the APE firwmare type and version. */ 966 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 967 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 968 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 969 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 970 fwtype = "NCSI"; 971 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 972 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 973 fwtype = "DASH"; 974 } else 975 fwtype = "UNKN"; 976 977 /* Print the APE firmware version. */ 978 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 979 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 980 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 981 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 982 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 983 } 984 985 int 986 bge_ape_lock(struct bge_softc *sc, int locknum) 987 { 988 struct pci_attach_args *pa = &(sc->bge_pa); 989 uint32_t bit, gnt, req, status; 990 int i, off; 991 992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 993 return (0); 994 995 /* Lock request/grant registers have different bases. */ 996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 997 req = BGE_APE_LOCK_REQ; 998 gnt = BGE_APE_LOCK_GRANT; 999 } else { 1000 req = BGE_APE_PER_LOCK_REQ; 1001 gnt = BGE_APE_PER_LOCK_GRANT; 1002 } 1003 1004 off = 4 * locknum; 1005 1006 switch (locknum) { 1007 case BGE_APE_LOCK_GPIO: 1008 /* Lock required when using GPIO. */ 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1010 return (0); 1011 if (pa->pa_function == 0) 1012 bit = BGE_APE_LOCK_REQ_DRIVER0; 1013 else 1014 bit = (1 << pa->pa_function); 1015 break; 1016 case BGE_APE_LOCK_GRC: 1017 /* Lock required to reset the device. */ 1018 if (pa->pa_function == 0) 1019 bit = BGE_APE_LOCK_REQ_DRIVER0; 1020 else 1021 bit = (1 << pa->pa_function); 1022 break; 1023 case BGE_APE_LOCK_MEM: 1024 /* Lock required when accessing certain APE memory. */ 1025 if (pa->pa_function == 0) 1026 bit = BGE_APE_LOCK_REQ_DRIVER0; 1027 else 1028 bit = (1 << pa->pa_function); 1029 break; 1030 case BGE_APE_LOCK_PHY0: 1031 case BGE_APE_LOCK_PHY1: 1032 case BGE_APE_LOCK_PHY2: 1033 case BGE_APE_LOCK_PHY3: 1034 /* Lock required when accessing PHYs. */ 1035 bit = BGE_APE_LOCK_REQ_DRIVER0; 1036 break; 1037 default: 1038 return (EINVAL); 1039 } 1040 1041 /* Request a lock. */ 1042 APE_WRITE_4_FLUSH(sc, req + off, bit); 1043 1044 /* Wait up to 1 second to acquire lock. */ 1045 for (i = 0; i < 20000; i++) { 1046 status = APE_READ_4(sc, gnt + off); 1047 if (status == bit) 1048 break; 1049 DELAY(50); 1050 } 1051 1052 /* Handle any errors. */ 1053 if (status != bit) { 1054 printf("%s: APE lock %d request failed! " 1055 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1056 device_xname(sc->bge_dev), 1057 locknum, req + off, bit & 0xFFFF, gnt + off, 1058 status & 0xFFFF); 1059 /* Revoke the lock request. */ 1060 APE_WRITE_4(sc, gnt + off, bit); 1061 return (EBUSY); 1062 } 1063 1064 return (0); 1065 } 1066 1067 void 1068 bge_ape_unlock(struct bge_softc *sc, int locknum) 1069 { 1070 struct pci_attach_args *pa = &(sc->bge_pa); 1071 uint32_t bit, gnt; 1072 int off; 1073 1074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1075 return; 1076 1077 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1078 gnt = BGE_APE_LOCK_GRANT; 1079 else 1080 gnt = BGE_APE_PER_LOCK_GRANT; 1081 1082 off = 4 * locknum; 1083 1084 switch (locknum) { 1085 case BGE_APE_LOCK_GPIO: 1086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1087 return; 1088 if (pa->pa_function == 0) 1089 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1090 else 1091 bit = (1 << pa->pa_function); 1092 break; 1093 case BGE_APE_LOCK_GRC: 1094 if (pa->pa_function == 0) 1095 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1096 else 1097 bit = (1 << pa->pa_function); 1098 break; 1099 case BGE_APE_LOCK_MEM: 1100 if (pa->pa_function == 0) 1101 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1102 else 1103 bit = (1 << pa->pa_function); 1104 break; 1105 case BGE_APE_LOCK_PHY0: 1106 case BGE_APE_LOCK_PHY1: 1107 case BGE_APE_LOCK_PHY2: 1108 case BGE_APE_LOCK_PHY3: 1109 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1110 break; 1111 default: 1112 return; 1113 } 1114 1115 /* Write and flush for consecutive bge_ape_lock() */ 1116 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1117 } 1118 1119 /* 1120 * Send an event to the APE firmware. 1121 */ 1122 void 1123 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1124 { 1125 uint32_t apedata; 1126 int i; 1127 1128 /* NCSI does not support APE events. */ 1129 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1130 return; 1131 1132 /* Wait up to 1ms for APE to service previous event. */ 1133 for (i = 10; i > 0; i--) { 1134 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1135 break; 1136 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1137 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1138 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1139 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1141 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1142 break; 1143 } 1144 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1145 DELAY(100); 1146 } 1147 if (i == 0) { 1148 printf("%s: APE event 0x%08x send timed out\n", 1149 device_xname(sc->bge_dev), event); 1150 } 1151 } 1152 1153 void 1154 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1155 { 1156 uint32_t apedata, event; 1157 1158 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1159 return; 1160 1161 switch (kind) { 1162 case BGE_RESET_START: 1163 /* If this is the first load, clear the load counter. */ 1164 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1165 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1166 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1167 else { 1168 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1169 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1170 } 1171 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1172 BGE_APE_HOST_SEG_SIG_MAGIC); 1173 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1174 BGE_APE_HOST_SEG_LEN_MAGIC); 1175 1176 /* Add some version info if bge(4) supports it. */ 1177 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1178 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1179 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1180 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1181 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1182 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_START); 1185 event = BGE_APE_EVENT_STATUS_STATE_START; 1186 break; 1187 case BGE_RESET_SHUTDOWN: 1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1189 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1190 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1191 break; 1192 case BGE_RESET_SUSPEND: 1193 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1194 break; 1195 default: 1196 return; 1197 } 1198 1199 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1200 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1201 } 1202 1203 static uint8_t 1204 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1205 { 1206 uint32_t access, byte = 0; 1207 int i; 1208 1209 /* Lock. */ 1210 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1211 for (i = 0; i < 8000; i++) { 1212 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1213 break; 1214 DELAY(20); 1215 } 1216 if (i == 8000) 1217 return 1; 1218 1219 /* Enable access. */ 1220 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1221 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1222 1223 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1224 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1225 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1226 DELAY(10); 1227 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1228 DELAY(10); 1229 break; 1230 } 1231 } 1232 1233 if (i == BGE_TIMEOUT * 10) { 1234 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1235 return 1; 1236 } 1237 1238 /* Get result. */ 1239 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1240 1241 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1242 1243 /* Disable access. */ 1244 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1245 1246 /* Unlock. */ 1247 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Read a sequence of bytes from NVRAM. 1254 */ 1255 static int 1256 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1257 { 1258 int error = 0, i; 1259 uint8_t byte = 0; 1260 1261 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1262 return 1; 1263 1264 for (i = 0; i < cnt; i++) { 1265 error = bge_nvram_getbyte(sc, off + i, &byte); 1266 if (error) 1267 break; 1268 *(dest + i) = byte; 1269 } 1270 1271 return (error ? 1 : 0); 1272 } 1273 1274 /* 1275 * Read a byte of data stored in the EEPROM at address 'addr.' The 1276 * BCM570x supports both the traditional bitbang interface and an 1277 * auto access interface for reading the EEPROM. We use the auto 1278 * access method. 1279 */ 1280 static uint8_t 1281 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1282 { 1283 int i; 1284 uint32_t byte = 0; 1285 1286 /* 1287 * Enable use of auto EEPROM access so we can avoid 1288 * having to use the bitbang method. 1289 */ 1290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1291 1292 /* Reset the EEPROM, load the clock period. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, 1294 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1295 DELAY(20); 1296 1297 /* Issue the read EEPROM command. */ 1298 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1299 1300 /* Wait for completion */ 1301 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1302 DELAY(10); 1303 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1304 break; 1305 } 1306 1307 if (i == BGE_TIMEOUT * 10) { 1308 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1309 return 1; 1310 } 1311 1312 /* Get result. */ 1313 byte = CSR_READ_4(sc, BGE_EE_DATA); 1314 1315 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1316 1317 return 0; 1318 } 1319 1320 /* 1321 * Read a sequence of bytes from the EEPROM. 1322 */ 1323 static int 1324 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1325 { 1326 int error = 0, i; 1327 uint8_t byte = 0; 1328 char *dest = destv; 1329 1330 for (i = 0; i < cnt; i++) { 1331 error = bge_eeprom_getbyte(sc, off + i, &byte); 1332 if (error) 1333 break; 1334 *(dest + i) = byte; 1335 } 1336 1337 return (error ? 1 : 0); 1338 } 1339 1340 static int 1341 bge_miibus_readreg(device_t dev, int phy, int reg) 1342 { 1343 struct bge_softc *sc = device_private(dev); 1344 uint32_t val; 1345 uint32_t autopoll; 1346 int i; 1347 1348 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1349 return 0; 1350 1351 /* Reading with autopolling on may trigger PCI errors */ 1352 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1353 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1354 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1355 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1356 DELAY(80); 1357 } 1358 1359 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1360 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1361 1362 for (i = 0; i < BGE_TIMEOUT; i++) { 1363 delay(10); 1364 val = CSR_READ_4(sc, BGE_MI_COMM); 1365 if (!(val & BGE_MICOMM_BUSY)) { 1366 DELAY(5); 1367 val = CSR_READ_4(sc, BGE_MI_COMM); 1368 break; 1369 } 1370 } 1371 1372 if (i == BGE_TIMEOUT) { 1373 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1374 val = 0; 1375 goto done; 1376 } 1377 1378 done: 1379 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1380 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1381 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1382 DELAY(80); 1383 } 1384 1385 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1386 1387 if (val & BGE_MICOMM_READFAIL) 1388 return 0; 1389 1390 return (val & 0xFFFF); 1391 } 1392 1393 static void 1394 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1395 { 1396 struct bge_softc *sc = device_private(dev); 1397 uint32_t autopoll; 1398 int i; 1399 1400 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1401 return; 1402 1403 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1404 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1405 return; 1406 1407 /* Reading with autopolling on may trigger PCI errors */ 1408 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1409 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1410 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1411 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1412 DELAY(80); 1413 } 1414 1415 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1416 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1417 1418 for (i = 0; i < BGE_TIMEOUT; i++) { 1419 delay(10); 1420 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1421 delay(5); 1422 CSR_READ_4(sc, BGE_MI_COMM); 1423 break; 1424 } 1425 } 1426 1427 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1428 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1429 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1430 delay(80); 1431 } 1432 1433 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1434 1435 if (i == BGE_TIMEOUT) 1436 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1437 } 1438 1439 static void 1440 bge_miibus_statchg(struct ifnet *ifp) 1441 { 1442 struct bge_softc *sc = ifp->if_softc; 1443 struct mii_data *mii = &sc->bge_mii; 1444 uint32_t mac_mode, rx_mode, tx_mode; 1445 1446 /* 1447 * Get flow control negotiation result. 1448 */ 1449 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1450 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1451 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1452 mii->mii_media_active &= ~IFM_ETH_FMASK; 1453 } 1454 1455 /* Set the port mode (MII/GMII) to match the link speed. */ 1456 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1457 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1458 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1459 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1460 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1461 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1462 mac_mode |= BGE_PORTMODE_GMII; 1463 else 1464 mac_mode |= BGE_PORTMODE_MII; 1465 1466 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1467 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1468 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1469 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1470 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1471 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1472 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1473 } else 1474 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1475 1476 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1477 DELAY(40); 1478 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1479 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1480 } 1481 1482 /* 1483 * Update rx threshold levels to values in a particular slot 1484 * of the interrupt-mitigation table bge_rx_threshes. 1485 */ 1486 static void 1487 bge_set_thresh(struct ifnet *ifp, int lvl) 1488 { 1489 struct bge_softc *sc = ifp->if_softc; 1490 int s; 1491 1492 /* For now, just save the new Rx-intr thresholds and record 1493 * that a threshold update is pending. Updating the hardware 1494 * registers here (even at splhigh()) is observed to 1495 * occasionaly cause glitches where Rx-interrupts are not 1496 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1497 */ 1498 s = splnet(); 1499 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1500 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1501 sc->bge_pending_rxintr_change = 1; 1502 splx(s); 1503 } 1504 1505 1506 /* 1507 * Update Rx thresholds of all bge devices 1508 */ 1509 static void 1510 bge_update_all_threshes(int lvl) 1511 { 1512 struct ifnet *ifp; 1513 const char * const namebuf = "bge"; 1514 int namelen; 1515 1516 if (lvl < 0) 1517 lvl = 0; 1518 else if (lvl >= NBGE_RX_THRESH) 1519 lvl = NBGE_RX_THRESH - 1; 1520 1521 namelen = strlen(namebuf); 1522 /* 1523 * Now search all the interfaces for this name/number 1524 */ 1525 IFNET_FOREACH(ifp) { 1526 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1527 continue; 1528 /* We got a match: update if doing auto-threshold-tuning */ 1529 if (bge_auto_thresh) 1530 bge_set_thresh(ifp, lvl); 1531 } 1532 } 1533 1534 /* 1535 * Handle events that have triggered interrupts. 1536 */ 1537 static void 1538 bge_handle_events(struct bge_softc *sc) 1539 { 1540 1541 return; 1542 } 1543 1544 /* 1545 * Memory management for jumbo frames. 1546 */ 1547 1548 static int 1549 bge_alloc_jumbo_mem(struct bge_softc *sc) 1550 { 1551 char *ptr, *kva; 1552 bus_dma_segment_t seg; 1553 int i, rseg, state, error; 1554 struct bge_jpool_entry *entry; 1555 1556 state = error = 0; 1557 1558 /* Grab a big chunk o' storage. */ 1559 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1560 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1561 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1562 return ENOBUFS; 1563 } 1564 1565 state = 1; 1566 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1567 BUS_DMA_NOWAIT)) { 1568 aprint_error_dev(sc->bge_dev, 1569 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1570 error = ENOBUFS; 1571 goto out; 1572 } 1573 1574 state = 2; 1575 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1576 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1577 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1578 error = ENOBUFS; 1579 goto out; 1580 } 1581 1582 state = 3; 1583 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1584 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1585 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1586 error = ENOBUFS; 1587 goto out; 1588 } 1589 1590 state = 4; 1591 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1592 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1593 1594 SLIST_INIT(&sc->bge_jfree_listhead); 1595 SLIST_INIT(&sc->bge_jinuse_listhead); 1596 1597 /* 1598 * Now divide it up into 9K pieces and save the addresses 1599 * in an array. 1600 */ 1601 ptr = sc->bge_cdata.bge_jumbo_buf; 1602 for (i = 0; i < BGE_JSLOTS; i++) { 1603 sc->bge_cdata.bge_jslots[i] = ptr; 1604 ptr += BGE_JLEN; 1605 entry = malloc(sizeof(struct bge_jpool_entry), 1606 M_DEVBUF, M_NOWAIT); 1607 if (entry == NULL) { 1608 aprint_error_dev(sc->bge_dev, 1609 "no memory for jumbo buffer queue!\n"); 1610 error = ENOBUFS; 1611 goto out; 1612 } 1613 entry->slot = i; 1614 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1615 entry, jpool_entries); 1616 } 1617 out: 1618 if (error != 0) { 1619 switch (state) { 1620 case 4: 1621 bus_dmamap_unload(sc->bge_dmatag, 1622 sc->bge_cdata.bge_rx_jumbo_map); 1623 case 3: 1624 bus_dmamap_destroy(sc->bge_dmatag, 1625 sc->bge_cdata.bge_rx_jumbo_map); 1626 case 2: 1627 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1628 case 1: 1629 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1630 break; 1631 default: 1632 break; 1633 } 1634 } 1635 1636 return error; 1637 } 1638 1639 /* 1640 * Allocate a jumbo buffer. 1641 */ 1642 static void * 1643 bge_jalloc(struct bge_softc *sc) 1644 { 1645 struct bge_jpool_entry *entry; 1646 1647 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1648 1649 if (entry == NULL) { 1650 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1651 return NULL; 1652 } 1653 1654 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1655 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1656 return (sc->bge_cdata.bge_jslots[entry->slot]); 1657 } 1658 1659 /* 1660 * Release a jumbo buffer. 1661 */ 1662 static void 1663 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1664 { 1665 struct bge_jpool_entry *entry; 1666 struct bge_softc *sc; 1667 int i, s; 1668 1669 /* Extract the softc struct pointer. */ 1670 sc = (struct bge_softc *)arg; 1671 1672 if (sc == NULL) 1673 panic("bge_jfree: can't find softc pointer!"); 1674 1675 /* calculate the slot this buffer belongs to */ 1676 1677 i = ((char *)buf 1678 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1679 1680 if ((i < 0) || (i >= BGE_JSLOTS)) 1681 panic("bge_jfree: asked to free buffer that we don't manage!"); 1682 1683 s = splvm(); 1684 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1685 if (entry == NULL) 1686 panic("bge_jfree: buffer not in use!"); 1687 entry->slot = i; 1688 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1689 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1690 1691 if (__predict_true(m != NULL)) 1692 pool_cache_put(mb_cache, m); 1693 splx(s); 1694 } 1695 1696 1697 /* 1698 * Initialize a standard receive ring descriptor. 1699 */ 1700 static int 1701 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1702 bus_dmamap_t dmamap) 1703 { 1704 struct mbuf *m_new = NULL; 1705 struct bge_rx_bd *r; 1706 int error; 1707 1708 if (dmamap == NULL) { 1709 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1710 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1711 if (error != 0) 1712 return error; 1713 } 1714 1715 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1716 1717 if (m == NULL) { 1718 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1719 if (m_new == NULL) 1720 return ENOBUFS; 1721 1722 MCLGET(m_new, M_DONTWAIT); 1723 if (!(m_new->m_flags & M_EXT)) { 1724 m_freem(m_new); 1725 return ENOBUFS; 1726 } 1727 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1728 1729 } else { 1730 m_new = m; 1731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1732 m_new->m_data = m_new->m_ext.ext_buf; 1733 } 1734 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1735 m_adj(m_new, ETHER_ALIGN); 1736 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1737 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1738 return ENOBUFS; 1739 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1740 BUS_DMASYNC_PREREAD); 1741 1742 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1743 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1744 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1745 r->bge_flags = BGE_RXBDFLAG_END; 1746 r->bge_len = m_new->m_len; 1747 r->bge_idx = i; 1748 1749 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1750 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1751 i * sizeof (struct bge_rx_bd), 1752 sizeof (struct bge_rx_bd), 1753 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1754 1755 return 0; 1756 } 1757 1758 /* 1759 * Initialize a jumbo receive ring descriptor. This allocates 1760 * a jumbo buffer from the pool managed internally by the driver. 1761 */ 1762 static int 1763 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1764 { 1765 struct mbuf *m_new = NULL; 1766 struct bge_rx_bd *r; 1767 void *buf = NULL; 1768 1769 if (m == NULL) { 1770 1771 /* Allocate the mbuf. */ 1772 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1773 if (m_new == NULL) 1774 return ENOBUFS; 1775 1776 /* Allocate the jumbo buffer */ 1777 buf = bge_jalloc(sc); 1778 if (buf == NULL) { 1779 m_freem(m_new); 1780 aprint_error_dev(sc->bge_dev, 1781 "jumbo allocation failed -- packet dropped!\n"); 1782 return ENOBUFS; 1783 } 1784 1785 /* Attach the buffer to the mbuf. */ 1786 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1787 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1788 bge_jfree, sc); 1789 m_new->m_flags |= M_EXT_RW; 1790 } else { 1791 m_new = m; 1792 buf = m_new->m_data = m_new->m_ext.ext_buf; 1793 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1794 } 1795 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1796 m_adj(m_new, ETHER_ALIGN); 1797 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1798 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1799 BUS_DMASYNC_PREREAD); 1800 /* Set up the descriptor. */ 1801 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1802 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1803 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1804 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1805 r->bge_len = m_new->m_len; 1806 r->bge_idx = i; 1807 1808 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1809 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1810 i * sizeof (struct bge_rx_bd), 1811 sizeof (struct bge_rx_bd), 1812 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1813 1814 return 0; 1815 } 1816 1817 /* 1818 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1819 * that's 1MB or memory, which is a lot. For now, we fill only the first 1820 * 256 ring entries and hope that our CPU is fast enough to keep up with 1821 * the NIC. 1822 */ 1823 static int 1824 bge_init_rx_ring_std(struct bge_softc *sc) 1825 { 1826 int i; 1827 1828 if (sc->bge_flags & BGE_RXRING_VALID) 1829 return 0; 1830 1831 for (i = 0; i < BGE_SSLOTS; i++) { 1832 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1833 return ENOBUFS; 1834 } 1835 1836 sc->bge_std = i - 1; 1837 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1838 1839 sc->bge_flags |= BGE_RXRING_VALID; 1840 1841 return 0; 1842 } 1843 1844 static void 1845 bge_free_rx_ring_std(struct bge_softc *sc) 1846 { 1847 int i; 1848 1849 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1850 return; 1851 1852 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1853 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1854 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1855 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1856 bus_dmamap_destroy(sc->bge_dmatag, 1857 sc->bge_cdata.bge_rx_std_map[i]); 1858 } 1859 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1860 sizeof(struct bge_rx_bd)); 1861 } 1862 1863 sc->bge_flags &= ~BGE_RXRING_VALID; 1864 } 1865 1866 static int 1867 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1868 { 1869 int i; 1870 volatile struct bge_rcb *rcb; 1871 1872 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1873 return 0; 1874 1875 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1876 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1877 return ENOBUFS; 1878 } 1879 1880 sc->bge_jumbo = i - 1; 1881 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1882 1883 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1884 rcb->bge_maxlen_flags = 0; 1885 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1886 1887 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1888 1889 return 0; 1890 } 1891 1892 static void 1893 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1894 { 1895 int i; 1896 1897 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1898 return; 1899 1900 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1901 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1902 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1903 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1904 } 1905 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1906 sizeof(struct bge_rx_bd)); 1907 } 1908 1909 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1910 } 1911 1912 static void 1913 bge_free_tx_ring(struct bge_softc *sc) 1914 { 1915 int i; 1916 struct txdmamap_pool_entry *dma; 1917 1918 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1919 return; 1920 1921 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1922 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1923 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1924 sc->bge_cdata.bge_tx_chain[i] = NULL; 1925 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1926 link); 1927 sc->txdma[i] = 0; 1928 } 1929 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1930 sizeof(struct bge_tx_bd)); 1931 } 1932 1933 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1934 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1935 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1936 free(dma, M_DEVBUF); 1937 } 1938 1939 sc->bge_flags &= ~BGE_TXRING_VALID; 1940 } 1941 1942 static int 1943 bge_init_tx_ring(struct bge_softc *sc) 1944 { 1945 int i; 1946 bus_dmamap_t dmamap; 1947 struct txdmamap_pool_entry *dma; 1948 1949 if (sc->bge_flags & BGE_TXRING_VALID) 1950 return 0; 1951 1952 sc->bge_txcnt = 0; 1953 sc->bge_tx_saved_considx = 0; 1954 1955 /* Initialize transmit producer index for host-memory send ring. */ 1956 sc->bge_tx_prodidx = 0; 1957 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1958 /* 5700 b2 errata */ 1959 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1960 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1961 1962 /* NIC-memory send ring not used; initialize to zero. */ 1963 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1964 /* 5700 b2 errata */ 1965 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1966 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1967 1968 SLIST_INIT(&sc->txdma_list); 1969 for (i = 0; i < BGE_RSLOTS; i++) { 1970 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1971 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1972 &dmamap)) 1973 return ENOBUFS; 1974 if (dmamap == NULL) 1975 panic("dmamap NULL in bge_init_tx_ring"); 1976 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1977 if (dma == NULL) { 1978 aprint_error_dev(sc->bge_dev, 1979 "can't alloc txdmamap_pool_entry\n"); 1980 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1981 return ENOMEM; 1982 } 1983 dma->dmamap = dmamap; 1984 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1985 } 1986 1987 sc->bge_flags |= BGE_TXRING_VALID; 1988 1989 return 0; 1990 } 1991 1992 static void 1993 bge_setmulti(struct bge_softc *sc) 1994 { 1995 struct ethercom *ac = &sc->ethercom; 1996 struct ifnet *ifp = &ac->ec_if; 1997 struct ether_multi *enm; 1998 struct ether_multistep step; 1999 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2000 uint32_t h; 2001 int i; 2002 2003 if (ifp->if_flags & IFF_PROMISC) 2004 goto allmulti; 2005 2006 /* Now program new ones. */ 2007 ETHER_FIRST_MULTI(step, ac, enm); 2008 while (enm != NULL) { 2009 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2010 /* 2011 * We must listen to a range of multicast addresses. 2012 * For now, just accept all multicasts, rather than 2013 * trying to set only those filter bits needed to match 2014 * the range. (At this time, the only use of address 2015 * ranges is for IP multicast routing, for which the 2016 * range is big enough to require all bits set.) 2017 */ 2018 goto allmulti; 2019 } 2020 2021 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2022 2023 /* Just want the 7 least-significant bits. */ 2024 h &= 0x7f; 2025 2026 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2027 ETHER_NEXT_MULTI(step, enm); 2028 } 2029 2030 ifp->if_flags &= ~IFF_ALLMULTI; 2031 goto setit; 2032 2033 allmulti: 2034 ifp->if_flags |= IFF_ALLMULTI; 2035 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2036 2037 setit: 2038 for (i = 0; i < 4; i++) 2039 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2040 } 2041 2042 static void 2043 bge_sig_pre_reset(struct bge_softc *sc, int type) 2044 { 2045 2046 /* 2047 * Some chips don't like this so only do this if ASF is enabled 2048 */ 2049 if (sc->bge_asf_mode) 2050 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2051 2052 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2053 switch (type) { 2054 case BGE_RESET_START: 2055 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2056 BGE_FW_DRV_STATE_START); 2057 break; 2058 case BGE_RESET_SHUTDOWN: 2059 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2060 BGE_FW_DRV_STATE_UNLOAD); 2061 break; 2062 case BGE_RESET_SUSPEND: 2063 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2064 BGE_FW_DRV_STATE_SUSPEND); 2065 break; 2066 } 2067 } 2068 2069 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2070 bge_ape_driver_state_change(sc, type); 2071 } 2072 2073 static void 2074 bge_sig_post_reset(struct bge_softc *sc, int type) 2075 { 2076 2077 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2078 switch (type) { 2079 case BGE_RESET_START: 2080 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2081 BGE_FW_DRV_STATE_START_DONE); 2082 /* START DONE */ 2083 break; 2084 case BGE_RESET_SHUTDOWN: 2085 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2086 BGE_FW_DRV_STATE_UNLOAD_DONE); 2087 break; 2088 } 2089 } 2090 2091 if (type == BGE_RESET_SHUTDOWN) 2092 bge_ape_driver_state_change(sc, type); 2093 } 2094 2095 static void 2096 bge_sig_legacy(struct bge_softc *sc, int type) 2097 { 2098 2099 if (sc->bge_asf_mode) { 2100 switch (type) { 2101 case BGE_RESET_START: 2102 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2103 BGE_FW_DRV_STATE_START); 2104 break; 2105 case BGE_RESET_SHUTDOWN: 2106 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2107 BGE_FW_DRV_STATE_UNLOAD); 2108 break; 2109 } 2110 } 2111 } 2112 2113 static void 2114 bge_wait_for_event_ack(struct bge_softc *sc) 2115 { 2116 int i; 2117 2118 /* wait up to 2500usec */ 2119 for (i = 0; i < 250; i++) { 2120 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2121 BGE_RX_CPU_DRV_EVENT)) 2122 break; 2123 DELAY(10); 2124 } 2125 } 2126 2127 static void 2128 bge_stop_fw(struct bge_softc *sc) 2129 { 2130 2131 if (sc->bge_asf_mode) { 2132 bge_wait_for_event_ack(sc); 2133 2134 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2135 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2136 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2137 2138 bge_wait_for_event_ack(sc); 2139 } 2140 } 2141 2142 static int 2143 bge_poll_fw(struct bge_softc *sc) 2144 { 2145 uint32_t val; 2146 int i; 2147 2148 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2149 for (i = 0; i < BGE_TIMEOUT; i++) { 2150 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2151 if (val & BGE_VCPU_STATUS_INIT_DONE) 2152 break; 2153 DELAY(100); 2154 } 2155 if (i >= BGE_TIMEOUT) { 2156 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2157 return -1; 2158 } 2159 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2160 /* 2161 * Poll the value location we just wrote until 2162 * we see the 1's complement of the magic number. 2163 * This indicates that the firmware initialization 2164 * is complete. 2165 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2166 */ 2167 for (i = 0; i < BGE_TIMEOUT; i++) { 2168 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2169 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2170 break; 2171 DELAY(10); 2172 } 2173 2174 if (i >= BGE_TIMEOUT) { 2175 aprint_error_dev(sc->bge_dev, 2176 "firmware handshake timed out, val = %x\n", val); 2177 return -1; 2178 } 2179 } 2180 2181 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2182 /* tg3 says we have to wait extra time */ 2183 delay(10 * 1000); 2184 } 2185 2186 return 0; 2187 } 2188 2189 int 2190 bge_phy_addr(struct bge_softc *sc) 2191 { 2192 struct pci_attach_args *pa = &(sc->bge_pa); 2193 int phy_addr = 1; 2194 2195 /* 2196 * PHY address mapping for various devices. 2197 * 2198 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2199 * ---------+-------+-------+-------+-------+ 2200 * BCM57XX | 1 | X | X | X | 2201 * BCM5704 | 1 | X | 1 | X | 2202 * BCM5717 | 1 | 8 | 2 | 9 | 2203 * BCM5719 | 1 | 8 | 2 | 9 | 2204 * BCM5720 | 1 | 8 | 2 | 9 | 2205 * 2206 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2207 * ---------+-------+-------+-------+-------+ 2208 * BCM57XX | X | X | X | X | 2209 * BCM5704 | X | X | X | X | 2210 * BCM5717 | X | X | X | X | 2211 * BCM5719 | 3 | 10 | 4 | 11 | 2212 * BCM5720 | X | X | X | X | 2213 * 2214 * Other addresses may respond but they are not 2215 * IEEE compliant PHYs and should be ignored. 2216 */ 2217 switch (BGE_ASICREV(sc->bge_chipid)) { 2218 case BGE_ASICREV_BCM5717: 2219 case BGE_ASICREV_BCM5719: 2220 case BGE_ASICREV_BCM5720: 2221 phy_addr = pa->pa_function; 2222 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2223 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2224 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2225 } else { 2226 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2227 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2228 } 2229 } 2230 2231 return phy_addr; 2232 } 2233 2234 /* 2235 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2236 * self-test results. 2237 */ 2238 static int 2239 bge_chipinit(struct bge_softc *sc) 2240 { 2241 uint32_t dma_rw_ctl, mode_ctl, reg; 2242 int i; 2243 2244 /* Set endianness before we access any non-PCI registers. */ 2245 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2246 BGE_INIT); 2247 2248 /* 2249 * Clear the MAC statistics block in the NIC's 2250 * internal memory. 2251 */ 2252 for (i = BGE_STATS_BLOCK; 2253 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2254 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2255 2256 for (i = BGE_STATUS_BLOCK; 2257 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2258 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2259 2260 /* 5717 workaround from tg3 */ 2261 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2262 /* Save */ 2263 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2264 2265 /* Temporary modify MODE_CTL to control TLP */ 2266 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2267 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2268 2269 /* Control TLP */ 2270 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2271 BGE_TLP_PHYCTL1); 2272 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2273 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2274 2275 /* Restore */ 2276 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2277 } 2278 2279 /* XXX Should we use 57765_FAMILY? */ 2280 if (BGE_IS_57765_PLUS(sc)) { 2281 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2282 /* Save */ 2283 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2284 2285 /* Temporary modify MODE_CTL to control TLP */ 2286 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2287 CSR_WRITE_4(sc, BGE_MODE_CTL, 2288 reg | BGE_MODECTL_PCIE_TLPADDR1); 2289 2290 /* Control TLP */ 2291 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2292 BGE_TLP_PHYCTL5); 2293 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2294 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2295 2296 /* Restore */ 2297 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2298 } 2299 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2300 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2301 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2302 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2303 2304 /* Save */ 2305 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2306 2307 /* Temporary modify MODE_CTL to control TLP */ 2308 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2309 CSR_WRITE_4(sc, BGE_MODE_CTL, 2310 reg | BGE_MODECTL_PCIE_TLPADDR0); 2311 2312 /* Control TLP */ 2313 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2314 BGE_TLP_FTSMAX); 2315 reg &= ~BGE_TLP_FTSMAX_MSK; 2316 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2317 reg | BGE_TLP_FTSMAX_VAL); 2318 2319 /* Restore */ 2320 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2321 } 2322 2323 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2324 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2325 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2326 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2327 } 2328 2329 /* Set up the PCI DMA control register. */ 2330 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2331 if (sc->bge_flags & BGE_PCIE) { 2332 /* Read watermark not used, 128 bytes for write. */ 2333 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2334 device_xname(sc->bge_dev))); 2335 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2336 } else if (sc->bge_flags & BGE_PCIX) { 2337 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2338 device_xname(sc->bge_dev))); 2339 /* PCI-X bus */ 2340 if (BGE_IS_5714_FAMILY(sc)) { 2341 /* 256 bytes for read and write. */ 2342 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2343 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2344 2345 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2346 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2347 else 2348 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2349 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2350 /* 1536 bytes for read, 384 bytes for write. */ 2351 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2352 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2353 } else { 2354 /* 384 bytes for read and write. */ 2355 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2356 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2357 (0x0F); 2358 } 2359 2360 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2361 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2362 uint32_t tmp; 2363 2364 /* Set ONEDMA_ATONCE for hardware workaround. */ 2365 tmp = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2366 BGE_PCI_CLKCTL) & 0x1f; 2367 if (tmp == 6 || tmp == 7) 2368 dma_rw_ctl |= 2369 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2370 2371 /* Set PCI-X DMA write workaround. */ 2372 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2373 } 2374 } else { 2375 /* Conventional PCI bus: 256 bytes for read and write. */ 2376 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2377 device_xname(sc->bge_dev))); 2378 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2379 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2380 2381 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2382 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2383 dma_rw_ctl |= 0x0F; 2384 } 2385 2386 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2387 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2388 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2389 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2390 2391 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2392 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2393 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2394 2395 if (BGE_IS_5717_PLUS(sc)) { 2396 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2397 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2398 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2399 2400 /* 2401 * Enable HW workaround for controllers that misinterpret 2402 * a status tag update and leave interrupts permanently 2403 * disabled. 2404 */ 2405 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2406 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2407 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2408 } 2409 2410 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2411 dma_rw_ctl); 2412 2413 /* 2414 * Set up general mode register. 2415 */ 2416 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2417 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2418 /* Retain Host-2-BMC settings written by APE firmware. */ 2419 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2420 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2421 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2422 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2423 } 2424 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2425 BGE_MODECTL_TX_NO_PHDR_CSUM; 2426 2427 /* 2428 * BCM5701 B5 have a bug causing data corruption when using 2429 * 64-bit DMA reads, which can be terminated early and then 2430 * completed later as 32-bit accesses, in combination with 2431 * certain bridges. 2432 */ 2433 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2434 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2435 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2436 2437 /* 2438 * Tell the firmware the driver is running 2439 */ 2440 if (sc->bge_asf_mode & ASF_STACKUP) 2441 mode_ctl |= BGE_MODECTL_STACKUP; 2442 2443 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2444 2445 /* 2446 * Disable memory write invalidate. Apparently it is not supported 2447 * properly by these devices. 2448 */ 2449 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2450 PCI_COMMAND_INVALIDATE_ENABLE); 2451 2452 #ifdef __brokenalpha__ 2453 /* 2454 * Must insure that we do not cross an 8K (bytes) boundary 2455 * for DMA reads. Our highest limit is 1K bytes. This is a 2456 * restriction on some ALPHA platforms with early revision 2457 * 21174 PCI chipsets, such as the AlphaPC 164lx 2458 */ 2459 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2460 #endif 2461 2462 /* Set the timer prescaler (always 66MHz) */ 2463 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2464 2465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2466 DELAY(40); /* XXX */ 2467 2468 /* Put PHY into ready state */ 2469 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2470 DELAY(40); 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int 2477 bge_blockinit(struct bge_softc *sc) 2478 { 2479 volatile struct bge_rcb *rcb; 2480 bus_size_t rcb_addr; 2481 struct ifnet *ifp = &sc->ethercom.ec_if; 2482 bge_hostaddr taddr; 2483 uint32_t dmactl, val; 2484 int i, limit; 2485 2486 /* 2487 * Initialize the memory window pointer register so that 2488 * we can access the first 32K of internal NIC RAM. This will 2489 * allow us to set up the TX send ring RCBs and the RX return 2490 * ring RCBs, plus other things which live in NIC memory. 2491 */ 2492 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2493 2494 /* Step 33: Configure mbuf memory pool */ 2495 if (!BGE_IS_5705_PLUS(sc)) { 2496 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2497 BGE_BUFFPOOL_1); 2498 2499 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2501 else 2502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2503 2504 /* Configure DMA resource pool */ 2505 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2506 BGE_DMA_DESCRIPTORS); 2507 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2508 } 2509 2510 /* Step 35: Configure mbuf pool watermarks */ 2511 /* new broadcom docs strongly recommend these: */ 2512 if (BGE_IS_5717_PLUS(sc)) { 2513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2514 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2515 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2516 } else if (BGE_IS_5705_PLUS(sc)) { 2517 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2518 2519 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2521 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2522 } else { 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2524 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2525 } 2526 } else { 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2530 } 2531 2532 /* Step 36: Configure DMA resource watermarks */ 2533 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2534 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2535 2536 /* Step 38: Enable buffer manager */ 2537 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2538 /* 2539 * Change the arbitration algorithm of TXMBUF read request to 2540 * round-robin instead of priority based for BCM5719. When 2541 * TXFIFO is almost empty, RDMA will hold its request until 2542 * TXFIFO is not almost empty. 2543 */ 2544 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2545 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2546 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2547 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2548 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2549 val |= BGE_BMANMODE_LOMBUF_ATTN; 2550 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2551 2552 /* Step 39: Poll for buffer manager start indication */ 2553 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2554 DELAY(10); 2555 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2556 break; 2557 } 2558 2559 if (i == BGE_TIMEOUT * 2) { 2560 aprint_error_dev(sc->bge_dev, 2561 "buffer manager failed to start\n"); 2562 return ENXIO; 2563 } 2564 2565 /* Step 40: Enable flow-through queues */ 2566 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2567 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2568 2569 /* Wait until queue initialization is complete */ 2570 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2571 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2572 break; 2573 DELAY(10); 2574 } 2575 2576 if (i == BGE_TIMEOUT * 2) { 2577 aprint_error_dev(sc->bge_dev, 2578 "flow-through queue init failed\n"); 2579 return ENXIO; 2580 } 2581 2582 /* 2583 * Summary of rings supported by the controller: 2584 * 2585 * Standard Receive Producer Ring 2586 * - This ring is used to feed receive buffers for "standard" 2587 * sized frames (typically 1536 bytes) to the controller. 2588 * 2589 * Jumbo Receive Producer Ring 2590 * - This ring is used to feed receive buffers for jumbo sized 2591 * frames (i.e. anything bigger than the "standard" frames) 2592 * to the controller. 2593 * 2594 * Mini Receive Producer Ring 2595 * - This ring is used to feed receive buffers for "mini" 2596 * sized frames to the controller. 2597 * - This feature required external memory for the controller 2598 * but was never used in a production system. Should always 2599 * be disabled. 2600 * 2601 * Receive Return Ring 2602 * - After the controller has placed an incoming frame into a 2603 * receive buffer that buffer is moved into a receive return 2604 * ring. The driver is then responsible to passing the 2605 * buffer up to the stack. Many versions of the controller 2606 * support multiple RR rings. 2607 * 2608 * Send Ring 2609 * - This ring is used for outgoing frames. Many versions of 2610 * the controller support multiple send rings. 2611 */ 2612 2613 /* Step 41: Initialize the standard RX ring control block */ 2614 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2615 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2616 if (BGE_IS_5717_PLUS(sc)) { 2617 /* 2618 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2619 * Bits 15-2 : Maximum RX frame size 2620 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2621 * Bit 0 : Reserved 2622 */ 2623 rcb->bge_maxlen_flags = 2624 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2625 } else if (BGE_IS_5705_PLUS(sc)) { 2626 /* 2627 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2628 * Bits 15-2 : Reserved (should be 0) 2629 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2630 * Bit 0 : Reserved 2631 */ 2632 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2633 } else { 2634 /* 2635 * Ring size is always XXX entries 2636 * Bits 31-16: Maximum RX frame size 2637 * Bits 15-2 : Reserved (should be 0) 2638 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2639 * Bit 0 : Reserved 2640 */ 2641 rcb->bge_maxlen_flags = 2642 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2643 } 2644 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2646 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2647 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2648 else 2649 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2650 /* Write the standard receive producer ring control block. */ 2651 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2652 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2653 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2654 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2655 2656 /* Reset the standard receive producer ring producer index. */ 2657 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2658 2659 /* 2660 * Step 42: Initialize the jumbo RX ring control block 2661 * We set the 'ring disabled' bit in the flags 2662 * field until we're actually ready to start 2663 * using this ring (i.e. once we set the MTU 2664 * high enough to require it). 2665 */ 2666 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2667 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2668 BGE_HOSTADDR(rcb->bge_hostaddr, 2669 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2670 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2671 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2672 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2674 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2675 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2676 else 2677 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2678 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2679 rcb->bge_hostaddr.bge_addr_hi); 2680 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2681 rcb->bge_hostaddr.bge_addr_lo); 2682 /* Program the jumbo receive producer ring RCB parameters. */ 2683 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2684 rcb->bge_maxlen_flags); 2685 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2686 /* Reset the jumbo receive producer ring producer index. */ 2687 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2688 } 2689 2690 /* Disable the mini receive producer ring RCB. */ 2691 if (BGE_IS_5700_FAMILY(sc)) { 2692 /* Set up dummy disabled mini ring RCB */ 2693 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2694 rcb->bge_maxlen_flags = 2695 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2696 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2697 rcb->bge_maxlen_flags); 2698 /* Reset the mini receive producer ring producer index. */ 2699 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2700 2701 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2702 offsetof(struct bge_ring_data, bge_info), 2703 sizeof (struct bge_gib), 2704 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2705 } 2706 2707 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2708 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2709 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2710 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2711 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2712 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2713 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2714 } 2715 /* 2716 * The BD ring replenish thresholds control how often the 2717 * hardware fetches new BD's from the producer rings in host 2718 * memory. Setting the value too low on a busy system can 2719 * starve the hardware and recue the throughpout. 2720 * 2721 * Set the BD ring replenish thresholds. The recommended 2722 * values are 1/8th the number of descriptors allocated to 2723 * each ring, but since we try to avoid filling the entire 2724 * ring we set these to the minimal value of 8. This needs to 2725 * be done on several of the supported chip revisions anyway, 2726 * to work around HW bugs. 2727 */ 2728 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2729 if (BGE_IS_JUMBO_CAPABLE(sc)) 2730 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2731 2732 if (BGE_IS_5717_PLUS(sc)) { 2733 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2734 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2735 } 2736 2737 /* 2738 * Disable all send rings by setting the 'ring disabled' bit 2739 * in the flags field of all the TX send ring control blocks, 2740 * located in NIC memory. 2741 */ 2742 if (BGE_IS_5700_FAMILY(sc)) { 2743 /* 5700 to 5704 had 16 send rings. */ 2744 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2745 } else 2746 limit = 1; 2747 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2748 for (i = 0; i < limit; i++) { 2749 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2750 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2751 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2752 rcb_addr += sizeof(struct bge_rcb); 2753 } 2754 2755 /* Configure send ring RCB 0 (we use only the first ring) */ 2756 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2757 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2758 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2759 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2760 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2761 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2762 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2763 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2764 else 2765 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2766 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2767 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2768 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2769 2770 /* 2771 * Disable all receive return rings by setting the 2772 * 'ring diabled' bit in the flags field of all the receive 2773 * return ring control blocks, located in NIC memory. 2774 */ 2775 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2776 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2777 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2778 /* Should be 17, use 16 until we get an SRAM map. */ 2779 limit = 16; 2780 } else if (BGE_IS_5700_FAMILY(sc)) 2781 limit = BGE_RX_RINGS_MAX; 2782 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2783 BGE_IS_57765_PLUS(sc)) 2784 limit = 4; 2785 else 2786 limit = 1; 2787 /* Disable all receive return rings */ 2788 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2789 for (i = 0; i < limit; i++) { 2790 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2791 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2792 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2793 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2794 BGE_RCB_FLAG_RING_DISABLED)); 2795 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2796 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2797 (i * (sizeof(uint64_t))), 0); 2798 rcb_addr += sizeof(struct bge_rcb); 2799 } 2800 2801 /* 2802 * Set up receive return ring 0. Note that the NIC address 2803 * for RX return rings is 0x0. The return rings live entirely 2804 * within the host, so the nicaddr field in the RCB isn't used. 2805 */ 2806 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2807 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2808 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2809 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2810 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2811 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2812 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2813 2814 /* Set random backoff seed for TX */ 2815 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2816 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2817 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2818 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2819 BGE_TX_BACKOFF_SEED_MASK); 2820 2821 /* Set inter-packet gap */ 2822 val = 0x2620; 2823 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2824 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2825 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2826 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2827 2828 /* 2829 * Specify which ring to use for packets that don't match 2830 * any RX rules. 2831 */ 2832 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2833 2834 /* 2835 * Configure number of RX lists. One interrupt distribution 2836 * list, sixteen active lists, one bad frames class. 2837 */ 2838 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2839 2840 /* Inialize RX list placement stats mask. */ 2841 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2842 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2843 2844 /* Disable host coalescing until we get it set up */ 2845 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2846 2847 /* Poll to make sure it's shut down. */ 2848 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2849 DELAY(10); 2850 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2851 break; 2852 } 2853 2854 if (i == BGE_TIMEOUT * 2) { 2855 aprint_error_dev(sc->bge_dev, 2856 "host coalescing engine failed to idle\n"); 2857 return ENXIO; 2858 } 2859 2860 /* Set up host coalescing defaults */ 2861 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2862 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2863 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2864 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2865 if (!(BGE_IS_5705_PLUS(sc))) { 2866 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2867 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2868 } 2869 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2870 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2871 2872 /* Set up address of statistics block */ 2873 if (BGE_IS_5700_FAMILY(sc)) { 2874 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2875 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2876 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2877 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2878 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2879 } 2880 2881 /* Set up address of status block */ 2882 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2883 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2884 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2885 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2886 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2887 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2888 2889 /* Set up status block size. */ 2890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2891 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2892 val = BGE_STATBLKSZ_FULL; 2893 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2894 } else { 2895 val = BGE_STATBLKSZ_32BYTE; 2896 bzero(&sc->bge_rdata->bge_status_block, 32); 2897 } 2898 2899 /* Turn on host coalescing state machine */ 2900 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2901 2902 /* Turn on RX BD completion state machine and enable attentions */ 2903 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2904 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2905 2906 /* Turn on RX list placement state machine */ 2907 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2908 2909 /* Turn on RX list selector state machine. */ 2910 if (!(BGE_IS_5705_PLUS(sc))) 2911 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2912 2913 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2914 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2915 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2916 BGE_MACMODE_FRMHDR_DMA_ENB; 2917 2918 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2919 val |= BGE_PORTMODE_TBI; 2920 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2921 val |= BGE_PORTMODE_GMII; 2922 else 2923 val |= BGE_PORTMODE_MII; 2924 2925 /* Allow APE to send/receive frames. */ 2926 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2927 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2928 2929 /* Turn on DMA, clear stats */ 2930 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2931 DELAY(40); 2932 2933 /* Set misc. local control, enable interrupts on attentions */ 2934 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2935 if (BGE_IS_5717_PLUS(sc)) { 2936 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2937 DELAY(100); 2938 } 2939 2940 /* Turn on DMA completion state machine */ 2941 if (!(BGE_IS_5705_PLUS(sc))) 2942 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2943 2944 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2945 2946 /* Enable host coalescing bug fix. */ 2947 if (BGE_IS_5755_PLUS(sc)) 2948 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2949 2950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2951 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2952 2953 /* Turn on write DMA state machine */ 2954 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2955 DELAY(40); 2956 2957 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2958 2959 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2960 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2961 2962 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2963 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2964 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2965 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2966 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2967 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2968 2969 if (sc->bge_flags & BGE_PCIE) 2970 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2971 if (sc->bge_flags & BGE_TSO) 2972 val |= BGE_RDMAMODE_TSO4_ENABLE; 2973 2974 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2975 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2976 BGE_RDMAMODE_H2BNC_VLAN_DET; 2977 /* 2978 * Allow multiple outstanding read requests from 2979 * non-LSO read DMA engine. 2980 */ 2981 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2982 } 2983 2984 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2985 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2986 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2987 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2988 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2989 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2990 /* 2991 * Adjust tx margin to prevent TX data corruption and 2992 * fix internal FIFO overflow. 2993 */ 2994 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2995 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2996 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2997 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2998 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2999 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3000 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3001 } 3002 /* 3003 * Enable fix for read DMA FIFO overruns. 3004 * The fix is to limit the number of RX BDs 3005 * the hardware would fetch at a fime. 3006 */ 3007 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3008 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3009 } 3010 3011 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3012 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3013 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3014 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3015 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3016 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3017 /* 3018 * Allow 4KB burst length reads for non-LSO frames. 3019 * Enable 512B burst length reads for buffer descriptors. 3020 */ 3021 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3022 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3023 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3024 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3025 } 3026 3027 /* Turn on read DMA state machine */ 3028 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3029 delay(40); 3030 3031 /* Turn on RX data completion state machine */ 3032 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3033 3034 /* Turn on RX BD initiator state machine */ 3035 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3036 3037 /* Turn on RX data and RX BD initiator state machine */ 3038 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3039 3040 /* Turn on Mbuf cluster free state machine */ 3041 if (!BGE_IS_5705_PLUS(sc)) 3042 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3043 3044 /* Turn on send BD completion state machine */ 3045 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3046 3047 /* Turn on send data completion state machine */ 3048 val = BGE_SDCMODE_ENABLE; 3049 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3050 val |= BGE_SDCMODE_CDELAY; 3051 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3052 3053 /* Turn on send data initiator state machine */ 3054 if (sc->bge_flags & BGE_TSO) { 3055 /* XXX: magic value from Linux driver */ 3056 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3057 BGE_SDIMODE_HW_LSO_PRE_DMA); 3058 } else 3059 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3060 3061 /* Turn on send BD initiator state machine */ 3062 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3063 3064 /* Turn on send BD selector state machine */ 3065 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3066 3067 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3068 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3069 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3070 3071 /* ack/clear link change events */ 3072 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3073 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3074 BGE_MACSTAT_LINK_CHANGED); 3075 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3076 3077 /* 3078 * Enable attention when the link has changed state for 3079 * devices that use auto polling. 3080 */ 3081 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3082 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3083 } else { 3084 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3085 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3087 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3088 BGE_EVTENB_MI_INTERRUPT); 3089 } 3090 3091 /* 3092 * Clear any pending link state attention. 3093 * Otherwise some link state change events may be lost until attention 3094 * is cleared by bge_intr() -> bge_link_upd() sequence. 3095 * It's not necessary on newer BCM chips - perhaps enabling link 3096 * state change attentions implies clearing pending attention. 3097 */ 3098 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3099 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3100 BGE_MACSTAT_LINK_CHANGED); 3101 3102 /* Enable link state change attentions. */ 3103 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3104 3105 return 0; 3106 } 3107 3108 static const struct bge_revision * 3109 bge_lookup_rev(uint32_t chipid) 3110 { 3111 const struct bge_revision *br; 3112 3113 for (br = bge_revisions; br->br_name != NULL; br++) { 3114 if (br->br_chipid == chipid) 3115 return br; 3116 } 3117 3118 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3119 if (br->br_chipid == BGE_ASICREV(chipid)) 3120 return br; 3121 } 3122 3123 return NULL; 3124 } 3125 3126 static const struct bge_product * 3127 bge_lookup(const struct pci_attach_args *pa) 3128 { 3129 const struct bge_product *bp; 3130 3131 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3132 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3133 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3134 return bp; 3135 } 3136 3137 return NULL; 3138 } 3139 3140 static uint32_t 3141 bge_chipid(const struct pci_attach_args *pa) 3142 { 3143 uint32_t id; 3144 3145 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3146 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3147 3148 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3149 switch (PCI_PRODUCT(pa->pa_id)) { 3150 case PCI_PRODUCT_BROADCOM_BCM5717: 3151 case PCI_PRODUCT_BROADCOM_BCM5718: 3152 case PCI_PRODUCT_BROADCOM_BCM5719: 3153 case PCI_PRODUCT_BROADCOM_BCM5720: 3154 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3155 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3156 BGE_PCI_GEN2_PRODID_ASICREV); 3157 break; 3158 case PCI_PRODUCT_BROADCOM_BCM57761: 3159 case PCI_PRODUCT_BROADCOM_BCM57762: 3160 case PCI_PRODUCT_BROADCOM_BCM57765: 3161 case PCI_PRODUCT_BROADCOM_BCM57766: 3162 case PCI_PRODUCT_BROADCOM_BCM57781: 3163 case PCI_PRODUCT_BROADCOM_BCM57785: 3164 case PCI_PRODUCT_BROADCOM_BCM57791: 3165 case PCI_PRODUCT_BROADCOM_BCM57795: 3166 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3167 BGE_PCI_GEN15_PRODID_ASICREV); 3168 break; 3169 default: 3170 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3171 BGE_PCI_PRODID_ASICREV); 3172 break; 3173 } 3174 } 3175 3176 return id; 3177 } 3178 3179 /* 3180 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3181 * against our list and return its name if we find a match. Note 3182 * that since the Broadcom controller contains VPD support, we 3183 * can get the device name string from the controller itself instead 3184 * of the compiled-in string. This is a little slow, but it guarantees 3185 * we'll always announce the right product name. 3186 */ 3187 static int 3188 bge_probe(device_t parent, cfdata_t match, void *aux) 3189 { 3190 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3191 3192 if (bge_lookup(pa) != NULL) 3193 return 1; 3194 3195 return 0; 3196 } 3197 3198 static void 3199 bge_attach(device_t parent, device_t self, void *aux) 3200 { 3201 struct bge_softc *sc = device_private(self); 3202 struct pci_attach_args *pa = aux; 3203 prop_dictionary_t dict; 3204 const struct bge_product *bp; 3205 const struct bge_revision *br; 3206 pci_chipset_tag_t pc; 3207 pci_intr_handle_t ih; 3208 const char *intrstr = NULL; 3209 bus_dma_segment_t seg; 3210 int rseg; 3211 uint32_t hwcfg = 0; 3212 uint32_t command; 3213 struct ifnet *ifp; 3214 uint32_t misccfg; 3215 void * kva; 3216 u_char eaddr[ETHER_ADDR_LEN]; 3217 pcireg_t memtype, subid, reg; 3218 bus_addr_t memaddr; 3219 bus_size_t memsize, apesize; 3220 uint32_t pm_ctl; 3221 bool no_seeprom; 3222 int capmask; 3223 3224 bp = bge_lookup(pa); 3225 KASSERT(bp != NULL); 3226 3227 sc->sc_pc = pa->pa_pc; 3228 sc->sc_pcitag = pa->pa_tag; 3229 sc->bge_dev = self; 3230 3231 sc->bge_pa = *pa; 3232 pc = sc->sc_pc; 3233 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3234 3235 aprint_naive(": Ethernet controller\n"); 3236 aprint_normal(": %s\n", bp->bp_name); 3237 3238 /* 3239 * Map control/status registers. 3240 */ 3241 DPRINTFN(5, ("Map control/status regs\n")); 3242 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3243 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3244 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3245 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3246 3247 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3248 aprint_error_dev(sc->bge_dev, 3249 "failed to enable memory mapping!\n"); 3250 return; 3251 } 3252 3253 DPRINTFN(5, ("pci_mem_find\n")); 3254 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3255 switch (memtype) { 3256 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3257 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3258 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3259 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3260 &memaddr, &memsize) == 0) 3261 break; 3262 default: 3263 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3264 return; 3265 } 3266 3267 DPRINTFN(5, ("pci_intr_map\n")); 3268 if (pci_intr_map(pa, &ih)) { 3269 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3270 return; 3271 } 3272 3273 DPRINTFN(5, ("pci_intr_string\n")); 3274 intrstr = pci_intr_string(pc, ih); 3275 3276 DPRINTFN(5, ("pci_intr_establish\n")); 3277 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3278 3279 if (sc->bge_intrhand == NULL) { 3280 aprint_error_dev(sc->bge_dev, 3281 "couldn't establish interrupt%s%s\n", 3282 intrstr ? " at " : "", intrstr ? intrstr : ""); 3283 return; 3284 } 3285 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3286 3287 /* Save various chip information. */ 3288 sc->bge_chipid = bge_chipid(pa); 3289 sc->bge_phy_addr = bge_phy_addr(sc); 3290 3291 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3292 &sc->bge_pciecap, NULL) != 0) 3293 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3294 /* PCIe */ 3295 sc->bge_flags |= BGE_PCIE; 3296 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3297 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3298 sc->bge_expmrq = 2048; 3299 else 3300 sc->bge_expmrq = 4096; 3301 bge_set_max_readrq(sc); 3302 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3303 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3304 /* PCI-X */ 3305 sc->bge_flags |= BGE_PCIX; 3306 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3307 &sc->bge_pcixcap, NULL) == 0) 3308 aprint_error_dev(sc->bge_dev, 3309 "unable to find PCIX capability\n"); 3310 } 3311 3312 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3313 /* 3314 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3315 * can clobber the chip's PCI config-space power control 3316 * registers, leaving the card in D3 powersave state. We do 3317 * not have memory-mapped registers in this state, so force 3318 * device into D0 state before starting initialization. 3319 */ 3320 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3321 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3322 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3323 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3324 DELAY(1000); /* 27 usec is allegedly sufficent */ 3325 } 3326 3327 /* Save chipset family. */ 3328 switch (BGE_ASICREV(sc->bge_chipid)) { 3329 case BGE_ASICREV_BCM57765: 3330 case BGE_ASICREV_BCM57766: 3331 sc->bge_flags |= BGE_57765_PLUS; 3332 /* FALLTHROUGH */ 3333 case BGE_ASICREV_BCM5717: 3334 case BGE_ASICREV_BCM5719: 3335 case BGE_ASICREV_BCM5720: 3336 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3337 BGE_5705_PLUS; 3338 break; 3339 case BGE_ASICREV_BCM5755: 3340 case BGE_ASICREV_BCM5761: 3341 case BGE_ASICREV_BCM5784: 3342 case BGE_ASICREV_BCM5785: 3343 case BGE_ASICREV_BCM5787: 3344 case BGE_ASICREV_BCM57780: 3345 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3346 break; 3347 case BGE_ASICREV_BCM5700: 3348 case BGE_ASICREV_BCM5701: 3349 case BGE_ASICREV_BCM5703: 3350 case BGE_ASICREV_BCM5704: 3351 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3352 break; 3353 case BGE_ASICREV_BCM5714_A0: 3354 case BGE_ASICREV_BCM5780: 3355 case BGE_ASICREV_BCM5714: 3356 sc->bge_flags |= BGE_5714_FAMILY; 3357 /* FALLTHROUGH */ 3358 case BGE_ASICREV_BCM5750: 3359 case BGE_ASICREV_BCM5752: 3360 case BGE_ASICREV_BCM5906: 3361 sc->bge_flags |= BGE_575X_PLUS; 3362 /* FALLTHROUGH */ 3363 case BGE_ASICREV_BCM5705: 3364 sc->bge_flags |= BGE_5705_PLUS; 3365 break; 3366 } 3367 3368 /* Identify chips with APE processor. */ 3369 switch (BGE_ASICREV(sc->bge_chipid)) { 3370 case BGE_ASICREV_BCM5717: 3371 case BGE_ASICREV_BCM5719: 3372 case BGE_ASICREV_BCM5720: 3373 case BGE_ASICREV_BCM5761: 3374 sc->bge_flags |= BGE_APE; 3375 break; 3376 } 3377 3378 /* Chips with APE need BAR2 access for APE registers/memory. */ 3379 if ((sc->bge_flags & BGE_APE) != 0) { 3380 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3381 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3382 &sc->bge_apetag, &sc->bge_apehandle, NULL, &apesize)) { 3383 aprint_error_dev(sc->bge_dev, 3384 "couldn't map BAR2 memory\n"); 3385 return; 3386 } 3387 3388 /* Enable APE register/memory access by host driver. */ 3389 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3390 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3391 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3392 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3393 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3394 3395 bge_ape_lock_init(sc); 3396 bge_ape_read_fw_ver(sc); 3397 } 3398 3399 /* Identify the chips that use an CPMU. */ 3400 if (BGE_IS_5717_PLUS(sc) || 3401 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3402 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3403 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3404 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3405 sc->bge_flags |= BGE_CPMU_PRESENT; 3406 3407 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3408 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3409 else 3410 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3411 3412 /* 3413 * When using the BCM5701 in PCI-X mode, data corruption has 3414 * been observed in the first few bytes of some received packets. 3415 * Aligning the packet buffer in memory eliminates the corruption. 3416 * Unfortunately, this misaligns the packet payloads. On platforms 3417 * which do not support unaligned accesses, we will realign the 3418 * payloads by copying the received packets. 3419 */ 3420 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3421 sc->bge_flags & BGE_PCIX) 3422 sc->bge_flags |= BGE_RX_ALIGNBUG; 3423 3424 if (BGE_IS_5700_FAMILY(sc)) 3425 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3426 3427 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3428 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3429 3430 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3431 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3432 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3433 sc->bge_flags |= BGE_IS_5788; 3434 3435 /* 3436 * Some controllers seem to require a special firmware to use 3437 * TSO. But the firmware is not available to FreeBSD and Linux 3438 * claims that the TSO performed by the firmware is slower than 3439 * hardware based TSO. Moreover the firmware based TSO has one 3440 * known bug which can't handle TSO if ethernet header + IP/TCP 3441 * header is greater than 80 bytes. The workaround for the TSO 3442 * bug exist but it seems it's too expensive than not using 3443 * TSO at all. Some hardwares also have the TSO bug so limit 3444 * the TSO to the controllers that are not affected TSO issues 3445 * (e.g. 5755 or higher). 3446 */ 3447 if (BGE_IS_5755_PLUS(sc)) { 3448 /* 3449 * BCM5754 and BCM5787 shares the same ASIC id so 3450 * explicit device id check is required. 3451 */ 3452 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3453 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3454 sc->bge_flags |= BGE_TSO; 3455 } 3456 3457 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3458 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3459 (misccfg == 0x4000 || misccfg == 0x8000)) || 3460 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3461 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3462 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3463 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3464 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3465 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3466 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3467 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3468 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3469 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3470 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3471 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3472 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3473 capmask &= ~BMSR_EXTSTAT; 3474 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3475 } 3476 3477 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3478 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3479 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3480 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3481 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3482 3483 /* Set various PHY bug flags. */ 3484 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3485 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3486 sc->bge_flags |= BGE_PHY_CRC_BUG; 3487 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3488 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3489 sc->bge_flags |= BGE_PHY_ADC_BUG; 3490 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3491 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3492 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3493 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3494 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3495 sc->bge_flags |= BGE_PHY_NO_3LED; 3496 if (BGE_IS_5705_PLUS(sc) && 3497 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3498 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3499 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3500 !BGE_IS_5717_PLUS(sc)) { 3501 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3503 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3504 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3505 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3506 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3507 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3508 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3509 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3510 } else 3511 sc->bge_flags |= BGE_PHY_BER_BUG; 3512 } 3513 3514 /* 3515 * SEEPROM check. 3516 * First check if firmware knows we do not have SEEPROM. 3517 */ 3518 if (prop_dictionary_get_bool(device_properties(self), 3519 "without-seeprom", &no_seeprom) && no_seeprom) 3520 sc->bge_flags |= BGE_NO_EEPROM; 3521 3522 /* Now check the 'ROM failed' bit on the RX CPU */ 3523 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3524 sc->bge_flags |= BGE_NO_EEPROM; 3525 3526 sc->bge_asf_mode = 0; 3527 /* No ASF if APE present. */ 3528 if ((sc->bge_flags & BGE_APE) == 0) { 3529 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3530 BGE_SRAM_DATA_SIG_MAGIC)) { 3531 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3532 BGE_HWCFG_ASF) { 3533 sc->bge_asf_mode |= ASF_ENABLE; 3534 sc->bge_asf_mode |= ASF_STACKUP; 3535 if (BGE_IS_575X_PLUS(sc)) 3536 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3537 } 3538 } 3539 } 3540 3541 bge_stop_fw(sc); 3542 bge_sig_pre_reset(sc, BGE_RESET_START); 3543 if (bge_reset(sc)) 3544 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3545 3546 bge_sig_legacy(sc, BGE_RESET_START); 3547 bge_sig_post_reset(sc, BGE_RESET_START); 3548 3549 if (bge_chipinit(sc)) { 3550 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3551 bge_release_resources(sc); 3552 return; 3553 } 3554 3555 /* 3556 * Get station address from the EEPROM. 3557 */ 3558 if (bge_get_eaddr(sc, eaddr)) { 3559 aprint_error_dev(sc->bge_dev, 3560 "failed to read station address\n"); 3561 bge_release_resources(sc); 3562 return; 3563 } 3564 3565 br = bge_lookup_rev(sc->bge_chipid); 3566 3567 if (br == NULL) { 3568 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3569 sc->bge_chipid); 3570 } else { 3571 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3572 br->br_name, sc->bge_chipid); 3573 } 3574 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3575 3576 /* Allocate the general information block and ring buffers. */ 3577 if (pci_dma64_available(pa)) 3578 sc->bge_dmatag = pa->pa_dmat64; 3579 else 3580 sc->bge_dmatag = pa->pa_dmat; 3581 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3582 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3583 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 3584 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3585 return; 3586 } 3587 DPRINTFN(5, ("bus_dmamem_map\n")); 3588 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 3589 sizeof(struct bge_ring_data), &kva, 3590 BUS_DMA_NOWAIT)) { 3591 aprint_error_dev(sc->bge_dev, 3592 "can't map DMA buffers (%zu bytes)\n", 3593 sizeof(struct bge_ring_data)); 3594 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3595 return; 3596 } 3597 DPRINTFN(5, ("bus_dmamem_create\n")); 3598 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3599 sizeof(struct bge_ring_data), 0, 3600 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3601 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3602 bus_dmamem_unmap(sc->bge_dmatag, kva, 3603 sizeof(struct bge_ring_data)); 3604 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3605 return; 3606 } 3607 DPRINTFN(5, ("bus_dmamem_load\n")); 3608 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3609 sizeof(struct bge_ring_data), NULL, 3610 BUS_DMA_NOWAIT)) { 3611 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3612 bus_dmamem_unmap(sc->bge_dmatag, kva, 3613 sizeof(struct bge_ring_data)); 3614 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3615 return; 3616 } 3617 3618 DPRINTFN(5, ("bzero\n")); 3619 sc->bge_rdata = (struct bge_ring_data *)kva; 3620 3621 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3622 3623 /* Try to allocate memory for jumbo buffers. */ 3624 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3625 if (bge_alloc_jumbo_mem(sc)) { 3626 aprint_error_dev(sc->bge_dev, 3627 "jumbo buffer allocation failed\n"); 3628 } else 3629 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3630 } 3631 3632 /* Set default tuneable values. */ 3633 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3634 sc->bge_rx_coal_ticks = 150; 3635 sc->bge_rx_max_coal_bds = 64; 3636 sc->bge_tx_coal_ticks = 300; 3637 sc->bge_tx_max_coal_bds = 400; 3638 if (BGE_IS_5705_PLUS(sc)) { 3639 sc->bge_tx_coal_ticks = (12 * 5); 3640 sc->bge_tx_max_coal_bds = (12 * 5); 3641 aprint_verbose_dev(sc->bge_dev, 3642 "setting short Tx thresholds\n"); 3643 } 3644 3645 if (BGE_IS_5717_PLUS(sc)) 3646 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3647 else if (BGE_IS_5705_PLUS(sc)) 3648 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3649 else 3650 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3651 3652 /* Set up ifnet structure */ 3653 ifp = &sc->ethercom.ec_if; 3654 ifp->if_softc = sc; 3655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3656 ifp->if_ioctl = bge_ioctl; 3657 ifp->if_stop = bge_stop; 3658 ifp->if_start = bge_start; 3659 ifp->if_init = bge_init; 3660 ifp->if_watchdog = bge_watchdog; 3661 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3662 IFQ_SET_READY(&ifp->if_snd); 3663 DPRINTFN(5, ("strcpy if_xname\n")); 3664 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3665 3666 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3667 sc->ethercom.ec_if.if_capabilities |= 3668 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3669 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3670 sc->ethercom.ec_if.if_capabilities |= 3671 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3672 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3673 #endif 3674 sc->ethercom.ec_capabilities |= 3675 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3676 3677 if (sc->bge_flags & BGE_TSO) 3678 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3679 3680 /* 3681 * Do MII setup. 3682 */ 3683 DPRINTFN(5, ("mii setup\n")); 3684 sc->bge_mii.mii_ifp = ifp; 3685 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3686 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3687 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3688 3689 /* 3690 * Figure out what sort of media we have by checking the hardware 3691 * config word in the first 32k of NIC internal memory, or fall back to 3692 * the config word in the EEPROM. Note: on some BCM5700 cards, 3693 * this value appears to be unset. If that's the case, we have to rely 3694 * on identifying the NIC by its PCI subsystem ID, as we do below for 3695 * the SysKonnect SK-9D41. 3696 */ 3697 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3698 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3699 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3700 bge_read_eeprom(sc, (void *)&hwcfg, 3701 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3702 hwcfg = be32toh(hwcfg); 3703 } 3704 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3705 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3706 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3707 if (BGE_IS_5714_FAMILY(sc)) 3708 sc->bge_flags |= BGE_PHY_FIBER_MII; 3709 else 3710 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3711 } 3712 3713 /* set phyflags and chipid before mii_attach() */ 3714 dict = device_properties(self); 3715 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3716 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3717 3718 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3719 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3720 bge_ifmedia_sts); 3721 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3722 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3723 0, NULL); 3724 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3725 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3726 /* Pretend the user requested this setting */ 3727 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3728 } else { 3729 /* 3730 * Do transceiver setup and tell the firmware the 3731 * driver is down so we can try to get access the 3732 * probe if ASF is running. Retry a couple of times 3733 * if we get a conflict with the ASF firmware accessing 3734 * the PHY. 3735 */ 3736 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3737 bge_asf_driver_up(sc); 3738 3739 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3740 bge_ifmedia_sts); 3741 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3742 sc->bge_phy_addr, MII_OFFSET_ANY, 3743 MIIF_DOPAUSE); 3744 3745 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3746 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3747 ifmedia_add(&sc->bge_mii.mii_media, 3748 IFM_ETHER|IFM_MANUAL, 0, NULL); 3749 ifmedia_set(&sc->bge_mii.mii_media, 3750 IFM_ETHER|IFM_MANUAL); 3751 } else 3752 ifmedia_set(&sc->bge_mii.mii_media, 3753 IFM_ETHER|IFM_AUTO); 3754 3755 /* 3756 * Now tell the firmware we are going up after probing the PHY 3757 */ 3758 if (sc->bge_asf_mode & ASF_STACKUP) 3759 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3760 } 3761 3762 /* 3763 * Call MI attach routine. 3764 */ 3765 DPRINTFN(5, ("if_attach\n")); 3766 if_attach(ifp); 3767 DPRINTFN(5, ("ether_ifattach\n")); 3768 ether_ifattach(ifp, eaddr); 3769 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3770 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3771 RND_TYPE_NET, 0); 3772 #ifdef BGE_EVENT_COUNTERS 3773 /* 3774 * Attach event counters. 3775 */ 3776 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3777 NULL, device_xname(sc->bge_dev), "intr"); 3778 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3779 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3780 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3781 NULL, device_xname(sc->bge_dev), "tx_xon"); 3782 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3783 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3784 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3785 NULL, device_xname(sc->bge_dev), "rx_xon"); 3786 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3787 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3788 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3789 NULL, device_xname(sc->bge_dev), "xoffentered"); 3790 #endif /* BGE_EVENT_COUNTERS */ 3791 DPRINTFN(5, ("callout_init\n")); 3792 callout_init(&sc->bge_timeout, 0); 3793 3794 if (pmf_device_register(self, NULL, NULL)) 3795 pmf_class_network_register(self, ifp); 3796 else 3797 aprint_error_dev(self, "couldn't establish power handler\n"); 3798 3799 bge_sysctl_init(sc); 3800 3801 #ifdef BGE_DEBUG 3802 bge_debug_info(sc); 3803 #endif 3804 } 3805 3806 static void 3807 bge_release_resources(struct bge_softc *sc) 3808 { 3809 if (sc->bge_vpd_prodname != NULL) 3810 free(sc->bge_vpd_prodname, M_DEVBUF); 3811 3812 if (sc->bge_vpd_readonly != NULL) 3813 free(sc->bge_vpd_readonly, M_DEVBUF); 3814 } 3815 3816 static int 3817 bge_reset(struct bge_softc *sc) 3818 { 3819 uint32_t cachesize, command; 3820 uint32_t reset, mac_mode, mac_mode_mask; 3821 pcireg_t devctl, reg; 3822 int i, val; 3823 void (*write_op)(struct bge_softc *, int, int); 3824 3825 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3826 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3827 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3828 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3829 3830 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3831 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3832 if (sc->bge_flags & BGE_PCIE) 3833 write_op = bge_writemem_direct; 3834 else 3835 write_op = bge_writemem_ind; 3836 } else 3837 write_op = bge_writereg_ind; 3838 3839 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3840 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3841 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3842 for (i = 0; i < 8000; i++) { 3843 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3844 BGE_NVRAMSWARB_GNT1) 3845 break; 3846 DELAY(20); 3847 } 3848 if (i == 8000) { 3849 printf("%s: NVRAM lock timedout!\n", 3850 device_xname(sc->bge_dev)); 3851 } 3852 } 3853 /* Take APE lock when performing reset. */ 3854 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3855 3856 /* Save some important PCI state. */ 3857 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3858 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3859 3860 /* Step 5b-5d: */ 3861 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3862 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3863 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3864 3865 /* XXX ???: Disable fastboot on controllers that support it. */ 3866 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3867 BGE_IS_5755_PLUS(sc)) 3868 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3869 3870 /* 3871 * Step 6: Write the magic number to SRAM at offset 0xB50. 3872 * When firmware finishes its initialization it will 3873 * write ~BGE_MAGIC_NUMBER to the same location. 3874 */ 3875 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3876 3877 /* Step 7: */ 3878 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3879 /* 3880 * XXX: from FreeBSD/Linux; no documentation 3881 */ 3882 if (sc->bge_flags & BGE_PCIE) { 3883 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3884 !BGE_IS_57765_PLUS(sc) && 3885 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3886 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3887 /* PCI Express 1.0 system */ 3888 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3889 BGE_PHY_PCIE_SCRAM_MODE); 3890 } 3891 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3892 /* 3893 * Prevent PCI Express link training 3894 * during global reset. 3895 */ 3896 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3897 reset |= (1 << 29); 3898 } 3899 } 3900 3901 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3902 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3903 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3904 i | BGE_VCPU_STATUS_DRV_RESET); 3905 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3906 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3907 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3908 } 3909 3910 /* 3911 * Set GPHY Power Down Override to leave GPHY 3912 * powered up in D0 uninitialized. 3913 */ 3914 if (BGE_IS_5705_PLUS(sc) && 3915 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3916 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3917 3918 /* Issue global reset */ 3919 write_op(sc, BGE_MISC_CFG, reset); 3920 3921 /* Step 8: wait for complete */ 3922 if (sc->bge_flags & BGE_PCIE) 3923 delay(100*1000); /* too big */ 3924 else 3925 delay(1000); 3926 3927 if (sc->bge_flags & BGE_PCIE) { 3928 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3929 DELAY(500000); 3930 /* XXX: Magic Numbers */ 3931 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3932 BGE_PCI_UNKNOWN0); 3933 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3934 BGE_PCI_UNKNOWN0, 3935 reg | (1 << 15)); 3936 } 3937 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3938 sc->bge_pciecap + PCI_PCIE_DCSR); 3939 /* Clear enable no snoop and disable relaxed ordering. */ 3940 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3941 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3942 3943 /* Set PCIE max payload size to 128 for older PCIe devices */ 3944 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3945 devctl &= ~(0x00e0); 3946 /* Clear device status register. Write 1b to clear */ 3947 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3948 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3949 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3950 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3951 bge_set_max_readrq(sc); 3952 } 3953 3954 /* From Linux: dummy read to flush PCI posted writes */ 3955 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3956 3957 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3958 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3959 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3960 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3961 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 3962 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 3963 (sc->bge_flags & BGE_PCIX) != 0) 3964 val |= BGE_PCISTATE_RETRY_SAME_DMA; 3965 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3966 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3967 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3968 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3969 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 3970 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3971 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3972 3973 /* Step 11: disable PCI-X Relaxed Ordering. */ 3974 if (sc->bge_flags & BGE_PCIX) { 3975 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3976 + PCI_PCIX_CMD); 3977 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3978 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3979 } 3980 3981 /* Step 12: Enable memory arbiter. */ 3982 if (BGE_IS_5714_FAMILY(sc)) { 3983 val = CSR_READ_4(sc, BGE_MARB_MODE); 3984 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3985 } else 3986 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3987 3988 /* XXX 5721, 5751 and 5752 */ 3989 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3990 /* Step 19: */ 3991 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3992 /* Step 20: */ 3993 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3994 } 3995 3996 /* Step 28: Fix up byte swapping */ 3997 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3998 3999 /* 4000 * Wait for the bootcode to complete initialization. 4001 * See BCM5718 programmer's guide's "step 13, Device reset Procedure, 4002 * Section 7". 4003 */ 4004 if (BGE_IS_5717_PLUS(sc)) { 4005 for (i = 0; i < 1000*1000; i++) { 4006 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4007 if (val == BGE_SRAM_FW_MB_RESET_MAGIC) 4008 break; 4009 DELAY(10); 4010 } 4011 } 4012 4013 /* Step 21: 5822 B0 errata */ 4014 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4015 pcireg_t msidata; 4016 4017 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4018 BGE_PCI_MSI_DATA); 4019 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4020 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4021 msidata); 4022 } 4023 4024 /* 4025 * Step 18: wirte mac mode 4026 * XXX Write 0x0c for 5703S and 5704S 4027 */ 4028 val = CSR_READ_4(sc, BGE_MAC_MODE); 4029 val = (val & ~mac_mode_mask) | mac_mode; 4030 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4031 DELAY(40); 4032 4033 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4034 4035 /* Step 17: Poll until the firmware initialization is complete */ 4036 bge_poll_fw(sc); 4037 4038 /* 4039 * The 5704 in TBI mode apparently needs some special 4040 * adjustment to insure the SERDES drive level is set 4041 * to 1.2V. 4042 */ 4043 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4044 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4045 uint32_t serdescfg; 4046 4047 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4048 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4049 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4050 } 4051 4052 if (sc->bge_flags & BGE_PCIE && 4053 !BGE_IS_57765_PLUS(sc) && 4054 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4055 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4056 uint32_t v; 4057 4058 /* Enable PCI Express bug fix */ 4059 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4060 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4061 v | BGE_TLP_DATA_FIFO_PROTECT); 4062 } 4063 4064 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4065 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4066 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4067 4068 return 0; 4069 } 4070 4071 /* 4072 * Frame reception handling. This is called if there's a frame 4073 * on the receive return list. 4074 * 4075 * Note: we have to be able to handle two possibilities here: 4076 * 1) the frame is from the jumbo receive ring 4077 * 2) the frame is from the standard receive ring 4078 */ 4079 4080 static void 4081 bge_rxeof(struct bge_softc *sc) 4082 { 4083 struct ifnet *ifp; 4084 uint16_t rx_prod, rx_cons; 4085 int stdcnt = 0, jumbocnt = 0; 4086 bus_dmamap_t dmamap; 4087 bus_addr_t offset, toff; 4088 bus_size_t tlen; 4089 int tosync; 4090 4091 rx_cons = sc->bge_rx_saved_considx; 4092 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4093 4094 /* Nothing to do */ 4095 if (rx_cons == rx_prod) 4096 return; 4097 4098 ifp = &sc->ethercom.ec_if; 4099 4100 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4101 offsetof(struct bge_ring_data, bge_status_block), 4102 sizeof (struct bge_status_block), 4103 BUS_DMASYNC_POSTREAD); 4104 4105 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4106 tosync = rx_prod - rx_cons; 4107 4108 if (tosync != 0) 4109 rnd_add_uint32(&sc->rnd_source, tosync); 4110 4111 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4112 4113 if (tosync < 0) { 4114 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4115 sizeof (struct bge_rx_bd); 4116 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4117 toff, tlen, BUS_DMASYNC_POSTREAD); 4118 tosync = -tosync; 4119 } 4120 4121 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4122 offset, tosync * sizeof (struct bge_rx_bd), 4123 BUS_DMASYNC_POSTREAD); 4124 4125 while (rx_cons != rx_prod) { 4126 struct bge_rx_bd *cur_rx; 4127 uint32_t rxidx; 4128 struct mbuf *m = NULL; 4129 4130 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4131 4132 rxidx = cur_rx->bge_idx; 4133 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4134 4135 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4136 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4137 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4138 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4139 jumbocnt++; 4140 bus_dmamap_sync(sc->bge_dmatag, 4141 sc->bge_cdata.bge_rx_jumbo_map, 4142 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4143 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4144 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4145 ifp->if_ierrors++; 4146 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4147 continue; 4148 } 4149 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4150 NULL)== ENOBUFS) { 4151 ifp->if_ierrors++; 4152 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4153 continue; 4154 } 4155 } else { 4156 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4157 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4158 4159 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4160 stdcnt++; 4161 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4162 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4163 if (dmamap == NULL) { 4164 ifp->if_ierrors++; 4165 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4166 continue; 4167 } 4168 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4169 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4170 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4171 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4172 ifp->if_ierrors++; 4173 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4174 continue; 4175 } 4176 if (bge_newbuf_std(sc, sc->bge_std, 4177 NULL, dmamap) == ENOBUFS) { 4178 ifp->if_ierrors++; 4179 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4180 continue; 4181 } 4182 } 4183 4184 ifp->if_ipackets++; 4185 #ifndef __NO_STRICT_ALIGNMENT 4186 /* 4187 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4188 * the Rx buffer has the layer-2 header unaligned. 4189 * If our CPU requires alignment, re-align by copying. 4190 */ 4191 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4192 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4193 cur_rx->bge_len); 4194 m->m_data += ETHER_ALIGN; 4195 } 4196 #endif 4197 4198 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4199 m->m_pkthdr.rcvif = ifp; 4200 4201 /* 4202 * Handle BPF listeners. Let the BPF user see the packet. 4203 */ 4204 bpf_mtap(ifp, m); 4205 4206 bge_rxcsum(sc, cur_rx, m); 4207 4208 /* 4209 * If we received a packet with a vlan tag, pass it 4210 * to vlan_input() instead of ether_input(). 4211 */ 4212 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4213 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4214 } 4215 4216 (*ifp->if_input)(ifp, m); 4217 } 4218 4219 sc->bge_rx_saved_considx = rx_cons; 4220 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4221 if (stdcnt) 4222 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4223 if (jumbocnt) 4224 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4225 } 4226 4227 static void 4228 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4229 { 4230 4231 if (BGE_IS_5717_PLUS(sc)) { 4232 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4233 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4234 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4235 if ((cur_rx->bge_error_flag & 4236 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4237 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4238 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4239 m->m_pkthdr.csum_data = 4240 cur_rx->bge_tcp_udp_csum; 4241 m->m_pkthdr.csum_flags |= 4242 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4243 M_CSUM_DATA); 4244 } 4245 } 4246 } else { 4247 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4248 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4249 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4250 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4251 /* 4252 * Rx transport checksum-offload may also 4253 * have bugs with packets which, when transmitted, 4254 * were `runts' requiring padding. 4255 */ 4256 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4257 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4258 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4259 m->m_pkthdr.csum_data = 4260 cur_rx->bge_tcp_udp_csum; 4261 m->m_pkthdr.csum_flags |= 4262 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4263 M_CSUM_DATA); 4264 } 4265 } 4266 } 4267 4268 static void 4269 bge_txeof(struct bge_softc *sc) 4270 { 4271 struct bge_tx_bd *cur_tx = NULL; 4272 struct ifnet *ifp; 4273 struct txdmamap_pool_entry *dma; 4274 bus_addr_t offset, toff; 4275 bus_size_t tlen; 4276 int tosync; 4277 struct mbuf *m; 4278 4279 ifp = &sc->ethercom.ec_if; 4280 4281 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4282 offsetof(struct bge_ring_data, bge_status_block), 4283 sizeof (struct bge_status_block), 4284 BUS_DMASYNC_POSTREAD); 4285 4286 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4287 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4288 sc->bge_tx_saved_considx; 4289 4290 if (tosync != 0) 4291 rnd_add_uint32(&sc->rnd_source, tosync); 4292 4293 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4294 4295 if (tosync < 0) { 4296 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4297 sizeof (struct bge_tx_bd); 4298 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4299 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4300 tosync = -tosync; 4301 } 4302 4303 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4304 offset, tosync * sizeof (struct bge_tx_bd), 4305 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4306 4307 /* 4308 * Go through our tx ring and free mbufs for those 4309 * frames that have been sent. 4310 */ 4311 while (sc->bge_tx_saved_considx != 4312 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4313 uint32_t idx = 0; 4314 4315 idx = sc->bge_tx_saved_considx; 4316 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4317 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4318 ifp->if_opackets++; 4319 m = sc->bge_cdata.bge_tx_chain[idx]; 4320 if (m != NULL) { 4321 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4322 dma = sc->txdma[idx]; 4323 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4324 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4325 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4326 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4327 sc->txdma[idx] = NULL; 4328 4329 m_freem(m); 4330 } 4331 sc->bge_txcnt--; 4332 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4333 ifp->if_timer = 0; 4334 } 4335 4336 if (cur_tx != NULL) 4337 ifp->if_flags &= ~IFF_OACTIVE; 4338 } 4339 4340 static int 4341 bge_intr(void *xsc) 4342 { 4343 struct bge_softc *sc; 4344 struct ifnet *ifp; 4345 uint32_t statusword; 4346 4347 sc = xsc; 4348 ifp = &sc->ethercom.ec_if; 4349 4350 /* It is possible for the interrupt to arrive before 4351 * the status block is updated prior to the interrupt. 4352 * Reading the PCI State register will confirm whether the 4353 * interrupt is ours and will flush the status block. 4354 */ 4355 4356 /* read status word from status block */ 4357 statusword = sc->bge_rdata->bge_status_block.bge_status; 4358 4359 if ((statusword & BGE_STATFLAG_UPDATED) || 4360 (!(pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 4361 BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4362 /* Ack interrupt and stop others from occuring. */ 4363 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4364 4365 BGE_EVCNT_INCR(sc->bge_ev_intr); 4366 4367 /* clear status word */ 4368 sc->bge_rdata->bge_status_block.bge_status = 0; 4369 4370 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4371 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4372 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4373 bge_link_upd(sc); 4374 4375 if (ifp->if_flags & IFF_RUNNING) { 4376 /* Check RX return ring producer/consumer */ 4377 bge_rxeof(sc); 4378 4379 /* Check TX ring producer/consumer */ 4380 bge_txeof(sc); 4381 } 4382 4383 if (sc->bge_pending_rxintr_change) { 4384 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4385 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4386 uint32_t junk; 4387 4388 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4389 DELAY(10); 4390 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4391 4392 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4393 DELAY(10); 4394 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4395 4396 sc->bge_pending_rxintr_change = 0; 4397 } 4398 bge_handle_events(sc); 4399 4400 /* Re-enable interrupts. */ 4401 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4402 4403 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4404 bge_start(ifp); 4405 4406 return 1; 4407 } else 4408 return 0; 4409 } 4410 4411 static void 4412 bge_asf_driver_up(struct bge_softc *sc) 4413 { 4414 if (sc->bge_asf_mode & ASF_STACKUP) { 4415 /* Send ASF heartbeat aprox. every 2s */ 4416 if (sc->bge_asf_count) 4417 sc->bge_asf_count --; 4418 else { 4419 sc->bge_asf_count = 2; 4420 4421 bge_wait_for_event_ack(sc); 4422 4423 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4424 BGE_FW_CMD_DRV_ALIVE); 4425 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4426 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4427 BGE_FW_HB_TIMEOUT_SEC); 4428 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4429 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4430 BGE_RX_CPU_DRV_EVENT); 4431 } 4432 } 4433 } 4434 4435 static void 4436 bge_tick(void *xsc) 4437 { 4438 struct bge_softc *sc = xsc; 4439 struct mii_data *mii = &sc->bge_mii; 4440 int s; 4441 4442 s = splnet(); 4443 4444 if (BGE_IS_5705_PLUS(sc)) 4445 bge_stats_update_regs(sc); 4446 else 4447 bge_stats_update(sc); 4448 4449 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4450 /* 4451 * Since in TBI mode auto-polling can't be used we should poll 4452 * link status manually. Here we register pending link event 4453 * and trigger interrupt. 4454 */ 4455 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4456 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4457 } else { 4458 /* 4459 * Do not touch PHY if we have link up. This could break 4460 * IPMI/ASF mode or produce extra input errors. 4461 * (extra input errors was reported for bcm5701 & bcm5704). 4462 */ 4463 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4464 mii_tick(mii); 4465 } 4466 4467 bge_asf_driver_up(sc); 4468 4469 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4470 4471 splx(s); 4472 } 4473 4474 static void 4475 bge_stats_update_regs(struct bge_softc *sc) 4476 { 4477 struct ifnet *ifp = &sc->ethercom.ec_if; 4478 4479 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4480 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4481 4482 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4483 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4484 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4485 } 4486 4487 static void 4488 bge_stats_update(struct bge_softc *sc) 4489 { 4490 struct ifnet *ifp = &sc->ethercom.ec_if; 4491 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4492 4493 #define READ_STAT(sc, stats, stat) \ 4494 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4495 4496 ifp->if_collisions += 4497 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4498 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4499 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4500 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4501 ifp->if_collisions; 4502 4503 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4504 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4505 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4506 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4507 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4508 READ_STAT(sc, stats, 4509 xoffPauseFramesReceived.bge_addr_lo)); 4510 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4511 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4512 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4513 READ_STAT(sc, stats, 4514 macControlFramesReceived.bge_addr_lo)); 4515 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4516 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4517 4518 #undef READ_STAT 4519 4520 #ifdef notdef 4521 ifp->if_collisions += 4522 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4523 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4524 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4525 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4526 ifp->if_collisions; 4527 #endif 4528 } 4529 4530 /* 4531 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4532 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4533 * but when such padded frames employ the bge IP/TCP checksum offload, 4534 * the hardware checksum assist gives incorrect results (possibly 4535 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4536 * If we pad such runts with zeros, the onboard checksum comes out correct. 4537 */ 4538 static inline int 4539 bge_cksum_pad(struct mbuf *pkt) 4540 { 4541 struct mbuf *last = NULL; 4542 int padlen; 4543 4544 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4545 4546 /* if there's only the packet-header and we can pad there, use it. */ 4547 if (pkt->m_pkthdr.len == pkt->m_len && 4548 M_TRAILINGSPACE(pkt) >= padlen) { 4549 last = pkt; 4550 } else { 4551 /* 4552 * Walk packet chain to find last mbuf. We will either 4553 * pad there, or append a new mbuf and pad it 4554 * (thus perhaps avoiding the bcm5700 dma-min bug). 4555 */ 4556 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4557 continue; /* do nothing */ 4558 } 4559 4560 /* `last' now points to last in chain. */ 4561 if (M_TRAILINGSPACE(last) < padlen) { 4562 /* Allocate new empty mbuf, pad it. Compact later. */ 4563 struct mbuf *n; 4564 MGET(n, M_DONTWAIT, MT_DATA); 4565 if (n == NULL) 4566 return ENOBUFS; 4567 n->m_len = 0; 4568 last->m_next = n; 4569 last = n; 4570 } 4571 } 4572 4573 KDASSERT(!M_READONLY(last)); 4574 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4575 4576 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4577 memset(mtod(last, char *) + last->m_len, 0, padlen); 4578 last->m_len += padlen; 4579 pkt->m_pkthdr.len += padlen; 4580 return 0; 4581 } 4582 4583 /* 4584 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4585 */ 4586 static inline int 4587 bge_compact_dma_runt(struct mbuf *pkt) 4588 { 4589 struct mbuf *m, *prev; 4590 int totlen, prevlen; 4591 4592 prev = NULL; 4593 totlen = 0; 4594 prevlen = -1; 4595 4596 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4597 int mlen = m->m_len; 4598 int shortfall = 8 - mlen ; 4599 4600 totlen += mlen; 4601 if (mlen == 0) 4602 continue; 4603 if (mlen >= 8) 4604 continue; 4605 4606 /* If we get here, mbuf data is too small for DMA engine. 4607 * Try to fix by shuffling data to prev or next in chain. 4608 * If that fails, do a compacting deep-copy of the whole chain. 4609 */ 4610 4611 /* Internal frag. If fits in prev, copy it there. */ 4612 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4613 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4614 prev->m_len += mlen; 4615 m->m_len = 0; 4616 /* XXX stitch chain */ 4617 prev->m_next = m_free(m); 4618 m = prev; 4619 continue; 4620 } 4621 else if (m->m_next != NULL && 4622 M_TRAILINGSPACE(m) >= shortfall && 4623 m->m_next->m_len >= (8 + shortfall)) { 4624 /* m is writable and have enough data in next, pull up. */ 4625 4626 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4627 shortfall); 4628 m->m_len += shortfall; 4629 m->m_next->m_len -= shortfall; 4630 m->m_next->m_data += shortfall; 4631 } 4632 else if (m->m_next == NULL || 1) { 4633 /* Got a runt at the very end of the packet. 4634 * borrow data from the tail of the preceding mbuf and 4635 * update its length in-place. (The original data is still 4636 * valid, so we can do this even if prev is not writable.) 4637 */ 4638 4639 /* if we'd make prev a runt, just move all of its data. */ 4640 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4641 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4642 4643 if ((prev->m_len - shortfall) < 8) 4644 shortfall = prev->m_len; 4645 4646 #ifdef notyet /* just do the safe slow thing for now */ 4647 if (!M_READONLY(m)) { 4648 if (M_LEADINGSPACE(m) < shorfall) { 4649 void *m_dat; 4650 m_dat = (m->m_flags & M_PKTHDR) ? 4651 m->m_pktdat : m->dat; 4652 memmove(m_dat, mtod(m, void*), m->m_len); 4653 m->m_data = m_dat; 4654 } 4655 } else 4656 #endif /* just do the safe slow thing */ 4657 { 4658 struct mbuf * n = NULL; 4659 int newprevlen = prev->m_len - shortfall; 4660 4661 MGET(n, M_NOWAIT, MT_DATA); 4662 if (n == NULL) 4663 return ENOBUFS; 4664 KASSERT(m->m_len + shortfall < MLEN 4665 /*, 4666 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4667 4668 /* first copy the data we're stealing from prev */ 4669 memcpy(n->m_data, prev->m_data + newprevlen, 4670 shortfall); 4671 4672 /* update prev->m_len accordingly */ 4673 prev->m_len -= shortfall; 4674 4675 /* copy data from runt m */ 4676 memcpy(n->m_data + shortfall, m->m_data, 4677 m->m_len); 4678 4679 /* n holds what we stole from prev, plus m */ 4680 n->m_len = shortfall + m->m_len; 4681 4682 /* stitch n into chain and free m */ 4683 n->m_next = m->m_next; 4684 prev->m_next = n; 4685 /* KASSERT(m->m_next == NULL); */ 4686 m->m_next = NULL; 4687 m_free(m); 4688 m = n; /* for continuing loop */ 4689 } 4690 } 4691 prevlen = m->m_len; 4692 } 4693 return 0; 4694 } 4695 4696 /* 4697 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4698 * pointers to descriptors. 4699 */ 4700 static int 4701 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4702 { 4703 struct bge_tx_bd *f = NULL; 4704 uint32_t frag, cur; 4705 uint16_t csum_flags = 0; 4706 uint16_t txbd_tso_flags = 0; 4707 struct txdmamap_pool_entry *dma; 4708 bus_dmamap_t dmamap; 4709 int i = 0; 4710 struct m_tag *mtag; 4711 int use_tso, maxsegsize, error; 4712 4713 cur = frag = *txidx; 4714 4715 if (m_head->m_pkthdr.csum_flags) { 4716 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4717 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4718 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4719 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4720 } 4721 4722 /* 4723 * If we were asked to do an outboard checksum, and the NIC 4724 * has the bug where it sometimes adds in the Ethernet padding, 4725 * explicitly pad with zeros so the cksum will be correct either way. 4726 * (For now, do this for all chip versions, until newer 4727 * are confirmed to not require the workaround.) 4728 */ 4729 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4730 #ifdef notyet 4731 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4732 #endif 4733 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4734 goto check_dma_bug; 4735 4736 if (bge_cksum_pad(m_head) != 0) 4737 return ENOBUFS; 4738 4739 check_dma_bug: 4740 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4741 goto doit; 4742 4743 /* 4744 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4745 * less than eight bytes. If we encounter a teeny mbuf 4746 * at the end of a chain, we can pad. Otherwise, copy. 4747 */ 4748 if (bge_compact_dma_runt(m_head) != 0) 4749 return ENOBUFS; 4750 4751 doit: 4752 dma = SLIST_FIRST(&sc->txdma_list); 4753 if (dma == NULL) 4754 return ENOBUFS; 4755 dmamap = dma->dmamap; 4756 4757 /* 4758 * Set up any necessary TSO state before we start packing... 4759 */ 4760 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4761 if (!use_tso) { 4762 maxsegsize = 0; 4763 } else { /* TSO setup */ 4764 unsigned mss; 4765 struct ether_header *eh; 4766 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4767 struct mbuf * m0 = m_head; 4768 struct ip *ip; 4769 struct tcphdr *th; 4770 int iphl, hlen; 4771 4772 /* 4773 * XXX It would be nice if the mbuf pkthdr had offset 4774 * fields for the protocol headers. 4775 */ 4776 4777 eh = mtod(m0, struct ether_header *); 4778 switch (htons(eh->ether_type)) { 4779 case ETHERTYPE_IP: 4780 offset = ETHER_HDR_LEN; 4781 break; 4782 4783 case ETHERTYPE_VLAN: 4784 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4785 break; 4786 4787 default: 4788 /* 4789 * Don't support this protocol or encapsulation. 4790 */ 4791 return ENOBUFS; 4792 } 4793 4794 /* 4795 * TCP/IP headers are in the first mbuf; we can do 4796 * this the easy way. 4797 */ 4798 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4799 hlen = iphl + offset; 4800 if (__predict_false(m0->m_len < 4801 (hlen + sizeof(struct tcphdr)))) { 4802 4803 aprint_debug_dev(sc->bge_dev, 4804 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4805 "not handled yet\n", 4806 m0->m_len, hlen+ sizeof(struct tcphdr)); 4807 #ifdef NOTYET 4808 /* 4809 * XXX jonathan (at) NetBSD.org: untested. 4810 * how to force this branch to be taken? 4811 */ 4812 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4813 4814 m_copydata(m0, offset, sizeof(ip), &ip); 4815 m_copydata(m0, hlen, sizeof(th), &th); 4816 4817 ip.ip_len = 0; 4818 4819 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4820 sizeof(ip.ip_len), &ip.ip_len); 4821 4822 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4823 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4824 4825 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4826 sizeof(th.th_sum), &th.th_sum); 4827 4828 hlen += th.th_off << 2; 4829 iptcp_opt_words = hlen; 4830 #else 4831 /* 4832 * if_wm "hard" case not yet supported, can we not 4833 * mandate it out of existence? 4834 */ 4835 (void) ip; (void)th; (void) ip_tcp_hlen; 4836 4837 return ENOBUFS; 4838 #endif 4839 } else { 4840 ip = (struct ip *) (mtod(m0, char *) + offset); 4841 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4842 ip_tcp_hlen = iphl + (th->th_off << 2); 4843 4844 /* Total IP/TCP options, in 32-bit words */ 4845 iptcp_opt_words = (ip_tcp_hlen 4846 - sizeof(struct tcphdr) 4847 - sizeof(struct ip)) >> 2; 4848 } 4849 if (BGE_IS_575X_PLUS(sc)) { 4850 th->th_sum = 0; 4851 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4852 } else { 4853 /* 4854 * XXX jonathan (at) NetBSD.org: 5705 untested. 4855 * Requires TSO firmware patch for 5701/5703/5704. 4856 */ 4857 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4858 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4859 } 4860 4861 mss = m_head->m_pkthdr.segsz; 4862 txbd_tso_flags |= 4863 BGE_TXBDFLAG_CPU_PRE_DMA | 4864 BGE_TXBDFLAG_CPU_POST_DMA; 4865 4866 /* 4867 * Our NIC TSO-assist assumes TSO has standard, optionless 4868 * IPv4 and TCP headers, which total 40 bytes. By default, 4869 * the NIC copies 40 bytes of IP/TCP header from the 4870 * supplied header into the IP/TCP header portion of 4871 * each post-TSO-segment. If the supplied packet has IP or 4872 * TCP options, we need to tell the NIC to copy those extra 4873 * bytes into each post-TSO header, in addition to the normal 4874 * 40-byte IP/TCP header (and to leave space accordingly). 4875 * Unfortunately, the driver encoding of option length 4876 * varies across different ASIC families. 4877 */ 4878 tcp_seg_flags = 0; 4879 if (iptcp_opt_words) { 4880 if (BGE_IS_5705_PLUS(sc)) { 4881 tcp_seg_flags = 4882 iptcp_opt_words << 11; 4883 } else { 4884 txbd_tso_flags |= 4885 iptcp_opt_words << 12; 4886 } 4887 } 4888 maxsegsize = mss | tcp_seg_flags; 4889 ip->ip_len = htons(mss + ip_tcp_hlen); 4890 4891 } /* TSO setup */ 4892 4893 /* 4894 * Start packing the mbufs in this chain into 4895 * the fragment pointers. Stop when we run out 4896 * of fragments or hit the end of the mbuf chain. 4897 */ 4898 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4899 BUS_DMA_NOWAIT); 4900 if (error) 4901 return ENOBUFS; 4902 /* 4903 * Sanity check: avoid coming within 16 descriptors 4904 * of the end of the ring. 4905 */ 4906 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4907 BGE_TSO_PRINTF(("%s: " 4908 " dmamap_load_mbuf too close to ring wrap\n", 4909 device_xname(sc->bge_dev))); 4910 goto fail_unload; 4911 } 4912 4913 mtag = sc->ethercom.ec_nvlans ? 4914 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4915 4916 4917 /* Iterate over dmap-map fragments. */ 4918 for (i = 0; i < dmamap->dm_nsegs; i++) { 4919 f = &sc->bge_rdata->bge_tx_ring[frag]; 4920 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4921 break; 4922 4923 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4924 f->bge_len = dmamap->dm_segs[i].ds_len; 4925 4926 /* 4927 * For 5751 and follow-ons, for TSO we must turn 4928 * off checksum-assist flag in the tx-descr, and 4929 * supply the ASIC-revision-specific encoding 4930 * of TSO flags and segsize. 4931 */ 4932 if (use_tso) { 4933 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4934 f->bge_rsvd = maxsegsize; 4935 f->bge_flags = csum_flags | txbd_tso_flags; 4936 } else { 4937 f->bge_rsvd = 0; 4938 f->bge_flags = 4939 (csum_flags | txbd_tso_flags) & 0x0fff; 4940 } 4941 } else { 4942 f->bge_rsvd = 0; 4943 f->bge_flags = csum_flags; 4944 } 4945 4946 if (mtag != NULL) { 4947 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4948 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4949 } else { 4950 f->bge_vlan_tag = 0; 4951 } 4952 cur = frag; 4953 BGE_INC(frag, BGE_TX_RING_CNT); 4954 } 4955 4956 if (i < dmamap->dm_nsegs) { 4957 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4958 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4959 goto fail_unload; 4960 } 4961 4962 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4963 BUS_DMASYNC_PREWRITE); 4964 4965 if (frag == sc->bge_tx_saved_considx) { 4966 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4967 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4968 4969 goto fail_unload; 4970 } 4971 4972 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4973 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4974 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4975 sc->txdma[cur] = dma; 4976 sc->bge_txcnt += dmamap->dm_nsegs; 4977 4978 *txidx = frag; 4979 4980 return 0; 4981 4982 fail_unload: 4983 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4984 4985 return ENOBUFS; 4986 } 4987 4988 /* 4989 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4990 * to the mbuf data regions directly in the transmit descriptors. 4991 */ 4992 static void 4993 bge_start(struct ifnet *ifp) 4994 { 4995 struct bge_softc *sc; 4996 struct mbuf *m_head = NULL; 4997 uint32_t prodidx; 4998 int pkts = 0; 4999 5000 sc = ifp->if_softc; 5001 5002 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5003 return; 5004 5005 prodidx = sc->bge_tx_prodidx; 5006 5007 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5008 IFQ_POLL(&ifp->if_snd, m_head); 5009 if (m_head == NULL) 5010 break; 5011 5012 #if 0 5013 /* 5014 * XXX 5015 * safety overkill. If this is a fragmented packet chain 5016 * with delayed TCP/UDP checksums, then only encapsulate 5017 * it if we have enough descriptors to handle the entire 5018 * chain at once. 5019 * (paranoia -- may not actually be needed) 5020 */ 5021 if (m_head->m_flags & M_FIRSTFRAG && 5022 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5023 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5024 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5025 ifp->if_flags |= IFF_OACTIVE; 5026 break; 5027 } 5028 } 5029 #endif 5030 5031 /* 5032 * Pack the data into the transmit ring. If we 5033 * don't have room, set the OACTIVE flag and wait 5034 * for the NIC to drain the ring. 5035 */ 5036 if (bge_encap(sc, m_head, &prodidx)) { 5037 ifp->if_flags |= IFF_OACTIVE; 5038 break; 5039 } 5040 5041 /* now we are committed to transmit the packet */ 5042 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5043 pkts++; 5044 5045 /* 5046 * If there's a BPF listener, bounce a copy of this frame 5047 * to him. 5048 */ 5049 bpf_mtap(ifp, m_head); 5050 } 5051 if (pkts == 0) 5052 return; 5053 5054 /* Transmit */ 5055 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5056 /* 5700 b2 errata */ 5057 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5058 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5059 5060 sc->bge_tx_prodidx = prodidx; 5061 5062 /* 5063 * Set a timeout in case the chip goes out to lunch. 5064 */ 5065 ifp->if_timer = 5; 5066 } 5067 5068 static int 5069 bge_init(struct ifnet *ifp) 5070 { 5071 struct bge_softc *sc = ifp->if_softc; 5072 const uint16_t *m; 5073 uint32_t mode; 5074 int s, error = 0; 5075 5076 s = splnet(); 5077 5078 ifp = &sc->ethercom.ec_if; 5079 5080 /* Cancel pending I/O and flush buffers. */ 5081 bge_stop(ifp, 0); 5082 5083 bge_stop_fw(sc); 5084 bge_sig_pre_reset(sc, BGE_RESET_START); 5085 bge_reset(sc); 5086 bge_sig_legacy(sc, BGE_RESET_START); 5087 bge_sig_post_reset(sc, BGE_RESET_START); 5088 5089 bge_chipinit(sc); 5090 5091 /* 5092 * Init the various state machines, ring 5093 * control blocks and firmware. 5094 */ 5095 error = bge_blockinit(sc); 5096 if (error != 0) { 5097 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5098 error); 5099 splx(s); 5100 return error; 5101 } 5102 5103 ifp = &sc->ethercom.ec_if; 5104 5105 /* Specify MTU. */ 5106 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5107 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5108 5109 /* Load our MAC address. */ 5110 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5111 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5112 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5113 5114 /* Enable or disable promiscuous mode as needed. */ 5115 if (ifp->if_flags & IFF_PROMISC) 5116 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5117 else 5118 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5119 5120 /* Program multicast filter. */ 5121 bge_setmulti(sc); 5122 5123 /* Init RX ring. */ 5124 bge_init_rx_ring_std(sc); 5125 5126 /* 5127 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5128 * memory to insure that the chip has in fact read the first 5129 * entry of the ring. 5130 */ 5131 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5132 uint32_t v, i; 5133 for (i = 0; i < 10; i++) { 5134 DELAY(20); 5135 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5136 if (v == (MCLBYTES - ETHER_ALIGN)) 5137 break; 5138 } 5139 if (i == 10) 5140 aprint_error_dev(sc->bge_dev, 5141 "5705 A0 chip failed to load RX ring\n"); 5142 } 5143 5144 /* Init jumbo RX ring. */ 5145 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5146 bge_init_rx_ring_jumbo(sc); 5147 5148 /* Init our RX return ring index */ 5149 sc->bge_rx_saved_considx = 0; 5150 5151 /* Init TX ring. */ 5152 bge_init_tx_ring(sc); 5153 5154 /* Enable TX MAC state machine lockup fix. */ 5155 mode = CSR_READ_4(sc, BGE_TX_MODE); 5156 if (BGE_IS_5755_PLUS(sc) || 5157 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5158 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5159 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5160 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5161 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5162 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5163 } 5164 5165 /* Turn on transmitter */ 5166 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5167 DELAY(100); 5168 5169 /* Turn on receiver */ 5170 mode = CSR_READ_4(sc, BGE_RX_MODE); 5171 if (BGE_IS_5755_PLUS(sc)) 5172 mode |= BGE_RXMODE_IPV6_ENABLE; 5173 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5174 DELAY(10); 5175 5176 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5177 5178 /* Tell firmware we're alive. */ 5179 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5180 5181 /* Enable host interrupts. */ 5182 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5183 BGE_PCIMISCCTL_CLEAR_INTA); 5184 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5185 BGE_PCIMISCCTL_MASK_PCI_INTR); 5186 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5187 5188 if ((error = bge_ifmedia_upd(ifp)) != 0) 5189 goto out; 5190 5191 ifp->if_flags |= IFF_RUNNING; 5192 ifp->if_flags &= ~IFF_OACTIVE; 5193 5194 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5195 5196 out: 5197 sc->bge_if_flags = ifp->if_flags; 5198 splx(s); 5199 5200 return error; 5201 } 5202 5203 /* 5204 * Set media options. 5205 */ 5206 static int 5207 bge_ifmedia_upd(struct ifnet *ifp) 5208 { 5209 struct bge_softc *sc = ifp->if_softc; 5210 struct mii_data *mii = &sc->bge_mii; 5211 struct ifmedia *ifm = &sc->bge_ifmedia; 5212 int rc; 5213 5214 /* If this is a 1000baseX NIC, enable the TBI port. */ 5215 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5216 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5217 return EINVAL; 5218 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5219 case IFM_AUTO: 5220 /* 5221 * The BCM5704 ASIC appears to have a special 5222 * mechanism for programming the autoneg 5223 * advertisement registers in TBI mode. 5224 */ 5225 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5226 uint32_t sgdig; 5227 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5228 if (sgdig & BGE_SGDIGSTS_DONE) { 5229 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5230 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5231 sgdig |= BGE_SGDIGCFG_AUTO | 5232 BGE_SGDIGCFG_PAUSE_CAP | 5233 BGE_SGDIGCFG_ASYM_PAUSE; 5234 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5235 sgdig | BGE_SGDIGCFG_SEND); 5236 DELAY(5); 5237 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5238 sgdig); 5239 } 5240 } 5241 break; 5242 case IFM_1000_SX: 5243 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5244 BGE_CLRBIT(sc, BGE_MAC_MODE, 5245 BGE_MACMODE_HALF_DUPLEX); 5246 } else { 5247 BGE_SETBIT(sc, BGE_MAC_MODE, 5248 BGE_MACMODE_HALF_DUPLEX); 5249 } 5250 DELAY(40); 5251 break; 5252 default: 5253 return EINVAL; 5254 } 5255 /* XXX 802.3x flow control for 1000BASE-SX */ 5256 return 0; 5257 } 5258 5259 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5260 if ((rc = mii_mediachg(mii)) == ENXIO) 5261 return 0; 5262 5263 /* 5264 * Force an interrupt so that we will call bge_link_upd 5265 * if needed and clear any pending link state attention. 5266 * Without this we are not getting any further interrupts 5267 * for link state changes and thus will not UP the link and 5268 * not be able to send in bge_start. The only way to get 5269 * things working was to receive a packet and get a RX intr. 5270 */ 5271 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5272 sc->bge_flags & BGE_IS_5788) 5273 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5274 else 5275 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5276 5277 return rc; 5278 } 5279 5280 /* 5281 * Report current media status. 5282 */ 5283 static void 5284 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5285 { 5286 struct bge_softc *sc = ifp->if_softc; 5287 struct mii_data *mii = &sc->bge_mii; 5288 5289 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5290 ifmr->ifm_status = IFM_AVALID; 5291 ifmr->ifm_active = IFM_ETHER; 5292 if (CSR_READ_4(sc, BGE_MAC_STS) & 5293 BGE_MACSTAT_TBI_PCS_SYNCHED) 5294 ifmr->ifm_status |= IFM_ACTIVE; 5295 ifmr->ifm_active |= IFM_1000_SX; 5296 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5297 ifmr->ifm_active |= IFM_HDX; 5298 else 5299 ifmr->ifm_active |= IFM_FDX; 5300 return; 5301 } 5302 5303 mii_pollstat(mii); 5304 ifmr->ifm_status = mii->mii_media_status; 5305 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5306 sc->bge_flowflags; 5307 } 5308 5309 static int 5310 bge_ifflags_cb(struct ethercom *ec) 5311 { 5312 struct ifnet *ifp = &ec->ec_if; 5313 struct bge_softc *sc = ifp->if_softc; 5314 int change = ifp->if_flags ^ sc->bge_if_flags; 5315 5316 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5317 return ENETRESET; 5318 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5319 return 0; 5320 5321 if ((ifp->if_flags & IFF_PROMISC) == 0) 5322 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5323 else 5324 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5325 5326 bge_setmulti(sc); 5327 5328 sc->bge_if_flags = ifp->if_flags; 5329 return 0; 5330 } 5331 5332 static int 5333 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5334 { 5335 struct bge_softc *sc = ifp->if_softc; 5336 struct ifreq *ifr = (struct ifreq *) data; 5337 int s, error = 0; 5338 struct mii_data *mii; 5339 5340 s = splnet(); 5341 5342 switch (command) { 5343 case SIOCSIFMEDIA: 5344 /* XXX Flow control is not supported for 1000BASE-SX */ 5345 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5346 ifr->ifr_media &= ~IFM_ETH_FMASK; 5347 sc->bge_flowflags = 0; 5348 } 5349 5350 /* Flow control requires full-duplex mode. */ 5351 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5352 (ifr->ifr_media & IFM_FDX) == 0) { 5353 ifr->ifr_media &= ~IFM_ETH_FMASK; 5354 } 5355 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5356 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5357 /* We can do both TXPAUSE and RXPAUSE. */ 5358 ifr->ifr_media |= 5359 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5360 } 5361 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5362 } 5363 /* FALLTHROUGH */ 5364 case SIOCGIFMEDIA: 5365 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5366 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5367 command); 5368 } else { 5369 mii = &sc->bge_mii; 5370 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5371 command); 5372 } 5373 break; 5374 default: 5375 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5376 break; 5377 5378 error = 0; 5379 5380 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5381 ; 5382 else if (ifp->if_flags & IFF_RUNNING) 5383 bge_setmulti(sc); 5384 break; 5385 } 5386 5387 splx(s); 5388 5389 return error; 5390 } 5391 5392 static void 5393 bge_watchdog(struct ifnet *ifp) 5394 { 5395 struct bge_softc *sc; 5396 5397 sc = ifp->if_softc; 5398 5399 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5400 5401 ifp->if_flags &= ~IFF_RUNNING; 5402 bge_init(ifp); 5403 5404 ifp->if_oerrors++; 5405 } 5406 5407 static void 5408 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5409 { 5410 int i; 5411 5412 BGE_CLRBIT_FLUSH(sc, reg, bit); 5413 5414 for (i = 0; i < 1000; i++) { 5415 delay(100); 5416 if ((CSR_READ_4(sc, reg) & bit) == 0) 5417 return; 5418 } 5419 5420 /* 5421 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5422 * on some environment (and once after boot?) 5423 */ 5424 if (reg != BGE_SRS_MODE) 5425 aprint_error_dev(sc->bge_dev, 5426 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5427 (u_long)reg, bit); 5428 } 5429 5430 /* 5431 * Stop the adapter and free any mbufs allocated to the 5432 * RX and TX lists. 5433 */ 5434 static void 5435 bge_stop(struct ifnet *ifp, int disable) 5436 { 5437 struct bge_softc *sc = ifp->if_softc; 5438 5439 callout_stop(&sc->bge_timeout); 5440 5441 /* Disable host interrupts. */ 5442 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 5443 BGE_PCIMISCCTL_MASK_PCI_INTR); 5444 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5445 5446 /* 5447 * Tell firmware we're shutting down. 5448 */ 5449 bge_stop_fw(sc); 5450 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5451 5452 /* 5453 * Disable all of the receiver blocks. 5454 */ 5455 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5456 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5457 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5458 if (BGE_IS_5700_FAMILY(sc)) 5459 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5460 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5461 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5462 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5463 5464 /* 5465 * Disable all of the transmit blocks. 5466 */ 5467 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5468 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5469 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5470 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5471 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5472 if (BGE_IS_5700_FAMILY(sc)) 5473 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5474 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5475 5476 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5477 delay(40); 5478 5479 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5480 5481 /* 5482 * Shut down all of the memory managers and related 5483 * state machines. 5484 */ 5485 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5486 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5487 if (BGE_IS_5700_FAMILY(sc)) 5488 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5489 5490 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5491 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5492 5493 if (BGE_IS_5700_FAMILY(sc)) { 5494 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5495 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5496 } 5497 5498 bge_reset(sc); 5499 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5500 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5501 5502 /* 5503 * Keep the ASF firmware running if up. 5504 */ 5505 if (sc->bge_asf_mode & ASF_STACKUP) 5506 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5507 else 5508 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5509 5510 /* Free the RX lists. */ 5511 bge_free_rx_ring_std(sc); 5512 5513 /* Free jumbo RX list. */ 5514 if (BGE_IS_JUMBO_CAPABLE(sc)) 5515 bge_free_rx_ring_jumbo(sc); 5516 5517 /* Free TX buffers. */ 5518 bge_free_tx_ring(sc); 5519 5520 /* 5521 * Isolate/power down the PHY. 5522 */ 5523 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5524 mii_down(&sc->bge_mii); 5525 5526 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5527 5528 /* Clear MAC's link state (PHY may still have link UP). */ 5529 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5530 5531 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5532 } 5533 5534 static void 5535 bge_link_upd(struct bge_softc *sc) 5536 { 5537 struct ifnet *ifp = &sc->ethercom.ec_if; 5538 struct mii_data *mii = &sc->bge_mii; 5539 uint32_t status; 5540 int link; 5541 5542 /* Clear 'pending link event' flag */ 5543 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5544 5545 /* 5546 * Process link state changes. 5547 * Grrr. The link status word in the status block does 5548 * not work correctly on the BCM5700 rev AX and BX chips, 5549 * according to all available information. Hence, we have 5550 * to enable MII interrupts in order to properly obtain 5551 * async link changes. Unfortunately, this also means that 5552 * we have to read the MAC status register to detect link 5553 * changes, thereby adding an additional register access to 5554 * the interrupt handler. 5555 */ 5556 5557 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5558 status = CSR_READ_4(sc, BGE_MAC_STS); 5559 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5560 mii_pollstat(mii); 5561 5562 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5563 mii->mii_media_status & IFM_ACTIVE && 5564 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5565 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5566 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5567 (!(mii->mii_media_status & IFM_ACTIVE) || 5568 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5569 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5570 5571 /* Clear the interrupt */ 5572 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5573 BGE_EVTENB_MI_INTERRUPT); 5574 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5575 BRGPHY_MII_ISR); 5576 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5577 BRGPHY_MII_IMR, BRGPHY_INTRS); 5578 } 5579 return; 5580 } 5581 5582 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5583 status = CSR_READ_4(sc, BGE_MAC_STS); 5584 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5585 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5586 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5587 if (BGE_ASICREV(sc->bge_chipid) 5588 == BGE_ASICREV_BCM5704) { 5589 BGE_CLRBIT(sc, BGE_MAC_MODE, 5590 BGE_MACMODE_TBI_SEND_CFGS); 5591 DELAY(40); 5592 } 5593 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5594 if_link_state_change(ifp, LINK_STATE_UP); 5595 } 5596 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5597 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5598 if_link_state_change(ifp, LINK_STATE_DOWN); 5599 } 5600 /* 5601 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5602 * This should not happen since mii callouts are locked now, but 5603 * we keep this check for debug. 5604 */ 5605 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5606 /* 5607 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5608 * bit in status word always set. Workaround this bug by 5609 * reading PHY link status directly. 5610 */ 5611 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5612 BGE_STS_LINK : 0; 5613 5614 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5615 mii_pollstat(mii); 5616 5617 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5618 mii->mii_media_status & IFM_ACTIVE && 5619 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5620 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5621 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5622 (!(mii->mii_media_status & IFM_ACTIVE) || 5623 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5624 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5625 } 5626 } 5627 5628 /* Clear the attention */ 5629 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5630 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5631 BGE_MACSTAT_LINK_CHANGED); 5632 } 5633 5634 static int 5635 bge_sysctl_verify(SYSCTLFN_ARGS) 5636 { 5637 int error, t; 5638 struct sysctlnode node; 5639 5640 node = *rnode; 5641 t = *(int*)rnode->sysctl_data; 5642 node.sysctl_data = &t; 5643 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5644 if (error || newp == NULL) 5645 return error; 5646 5647 #if 0 5648 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5649 node.sysctl_num, rnode->sysctl_num)); 5650 #endif 5651 5652 if (node.sysctl_num == bge_rxthresh_nodenum) { 5653 if (t < 0 || t >= NBGE_RX_THRESH) 5654 return EINVAL; 5655 bge_update_all_threshes(t); 5656 } else 5657 return EINVAL; 5658 5659 *(int*)rnode->sysctl_data = t; 5660 5661 return 0; 5662 } 5663 5664 /* 5665 * Set up sysctl(3) MIB, hw.bge.*. 5666 */ 5667 static void 5668 bge_sysctl_init(struct bge_softc *sc) 5669 { 5670 int rc, bge_root_num; 5671 const struct sysctlnode *node; 5672 5673 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5674 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5675 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5676 goto out; 5677 } 5678 5679 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5680 0, CTLTYPE_NODE, "bge", 5681 SYSCTL_DESCR("BGE interface controls"), 5682 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5683 goto out; 5684 } 5685 5686 bge_root_num = node->sysctl_num; 5687 5688 /* BGE Rx interrupt mitigation level */ 5689 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5690 CTLFLAG_READWRITE, 5691 CTLTYPE_INT, "rx_lvl", 5692 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5693 bge_sysctl_verify, 0, 5694 &bge_rx_thresh_lvl, 5695 0, CTL_HW, bge_root_num, CTL_CREATE, 5696 CTL_EOL)) != 0) { 5697 goto out; 5698 } 5699 5700 bge_rxthresh_nodenum = node->sysctl_num; 5701 5702 return; 5703 5704 out: 5705 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5706 } 5707 5708 #ifdef BGE_DEBUG 5709 void 5710 bge_debug_info(struct bge_softc *sc) 5711 { 5712 5713 printf("Hardware Flags:\n"); 5714 if (BGE_IS_57765_PLUS(sc)) 5715 printf(" - 57765 Plus\n"); 5716 if (BGE_IS_5717_PLUS(sc)) 5717 printf(" - 5717 Plus\n"); 5718 if (BGE_IS_5755_PLUS(sc)) 5719 printf(" - 5755 Plus\n"); 5720 if (BGE_IS_575X_PLUS(sc)) 5721 printf(" - 575X Plus\n"); 5722 if (BGE_IS_5705_PLUS(sc)) 5723 printf(" - 5705 Plus\n"); 5724 if (BGE_IS_5714_FAMILY(sc)) 5725 printf(" - 5714 Family\n"); 5726 if (BGE_IS_5700_FAMILY(sc)) 5727 printf(" - 5700 Family\n"); 5728 if (sc->bge_flags & BGE_IS_5788) 5729 printf(" - 5788\n"); 5730 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5731 printf(" - Supports Jumbo Frames\n"); 5732 if (sc->bge_flags & BGE_NO_EEPROM) 5733 printf(" - No EEPROM\n"); 5734 if (sc->bge_flags & BGE_PCIX) 5735 printf(" - PCI-X Bus\n"); 5736 if (sc->bge_flags & BGE_PCIE) 5737 printf(" - PCI Express Bus\n"); 5738 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5739 printf(" - RX Alignment Bug\n"); 5740 if (sc->bge_flags & BGE_APE) 5741 printf(" - APE\n"); 5742 if (sc->bge_flags & BGE_CPMU_PRESENT) 5743 printf(" - CPMU\n"); 5744 if (sc->bge_flags & BGE_TSO) 5745 printf(" - TSO\n"); 5746 5747 if (sc->bge_flags & BGE_PHY_NO_3LED) 5748 printf(" - No 3 LEDs\n"); 5749 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5750 printf(" - CRC bug\n"); 5751 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5752 printf(" - ADC bug\n"); 5753 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5754 printf(" - 5704 A0 bug\n"); 5755 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5756 printf(" - jitter bug\n"); 5757 if (sc->bge_flags & BGE_PHY_BER_BUG) 5758 printf(" - BER bug\n"); 5759 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5760 printf(" - adjust trim\n"); 5761 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5762 printf(" - no wirespeed\n"); 5763 } 5764 #endif /* BGE_DEBUG */ 5765 5766 static int 5767 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5768 { 5769 prop_dictionary_t dict; 5770 prop_data_t ea; 5771 5772 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5773 return 1; 5774 5775 dict = device_properties(sc->bge_dev); 5776 ea = prop_dictionary_get(dict, "mac-address"); 5777 if (ea != NULL) { 5778 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5779 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5780 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5781 return 0; 5782 } 5783 5784 return 1; 5785 } 5786 5787 static int 5788 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5789 { 5790 uint32_t mac_addr; 5791 5792 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5793 if ((mac_addr >> 16) == 0x484b) { 5794 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5795 ether_addr[1] = (uint8_t)mac_addr; 5796 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5797 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5798 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5799 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5800 ether_addr[5] = (uint8_t)mac_addr; 5801 return 0; 5802 } 5803 return 1; 5804 } 5805 5806 static int 5807 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5808 { 5809 int mac_offset = BGE_EE_MAC_OFFSET; 5810 5811 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5812 mac_offset = BGE_EE_MAC_OFFSET_5906; 5813 5814 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5815 ETHER_ADDR_LEN)); 5816 } 5817 5818 static int 5819 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5820 { 5821 5822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5823 return 1; 5824 5825 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5826 ETHER_ADDR_LEN)); 5827 } 5828 5829 static int 5830 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5831 { 5832 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5833 /* NOTE: Order is critical */ 5834 bge_get_eaddr_fw, 5835 bge_get_eaddr_mem, 5836 bge_get_eaddr_nvram, 5837 bge_get_eaddr_eeprom, 5838 NULL 5839 }; 5840 const bge_eaddr_fcn_t *func; 5841 5842 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5843 if ((*func)(sc, eaddr) == 0) 5844 break; 5845 } 5846 return (*func == NULL ? ENXIO : 0); 5847 } 5848
Indexes created Sun Sep 28 07:09:56 GMT 2025