if_bge.c revision 1.226
1 /* $NetBSD: if_bge.c,v 1.226 2013/03/24 19:16:10 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.226 2013/03/24 19:16:10 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int); 254 static void bge_miibus_writereg(device_t, int, int, int); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5724, 440 "Broadcom BCM5724 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5750, 444 "Broadcom BCM5750 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5750M, 448 "Broadcom BCM5750M Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751, 452 "Broadcom BCM5751 Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5751F, 456 "Broadcom BCM5751F Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5751M, 460 "Broadcom BCM5751M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5752, 464 "Broadcom BCM5752 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5752M, 468 "Broadcom BCM5752M Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753, 472 "Broadcom BCM5753 Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5753F, 476 "Broadcom BCM5753F Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5753M, 480 "Broadcom BCM5753M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5754, 484 "Broadcom BCM5754 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5754M, 488 "Broadcom BCM5754M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5755, 492 "Broadcom BCM5755 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5755M, 496 "Broadcom BCM5755M Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5756, 500 "Broadcom BCM5756 Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761, 504 "Broadcom BCM5761 Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761E, 508 "Broadcom BCM5761E Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5761S, 512 "Broadcom BCM5761S Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5761SE, 516 "Broadcom BCM5761SE Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5764, 520 "Broadcom BCM5764 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5780, 524 "Broadcom BCM5780 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5780S, 528 "Broadcom BCM5780S Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5781, 532 "Broadcom BCM5781 Gigabit Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5782, 536 "Broadcom BCM5782 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5784M, 540 "BCM5784M NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5785F, 544 "BCM5785F NetLink 10/100 Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5785G, 548 "BCM5785G NetLink 1000baseT Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5786, 552 "Broadcom BCM5786 Gigabit Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787, 556 "Broadcom BCM5787 Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5787F, 560 "Broadcom BCM5787F 10/100 Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5787M, 564 "Broadcom BCM5787M Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5788, 568 "Broadcom BCM5788 Gigabit Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5789, 572 "Broadcom BCM5789 Gigabit Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5901, 576 "Broadcom BCM5901 Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5901A2, 580 "Broadcom BCM5901A2 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5903M, 584 "Broadcom BCM5903M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM5906, 588 "Broadcom BCM5906 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM5906M, 592 "Broadcom BCM5906M Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57760, 596 "Broadcom BCM57760 Fast Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57761, 600 "Broadcom BCM57761 Fast Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57762, 604 "Broadcom BCM57762 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57765, 608 "Broadcom BCM57765 Fast Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57766, 612 "Broadcom BCM57766 Fast Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57780, 616 "Broadcom BCM57780 Fast Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57781, 620 "Broadcom BCM57781 Fast Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57782, 624 "Broadcom BCM57782 Fast Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57785, 628 "Broadcom BCM57785 Fast Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57786, 632 "Broadcom BCM57786 Fast Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57788, 636 "Broadcom BCM57788 Fast Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57790, 640 "Broadcom BCM57790 Fast Ethernet", 641 }, 642 { PCI_VENDOR_BROADCOM, 643 PCI_PRODUCT_BROADCOM_BCM57791, 644 "Broadcom BCM57791 Fast Ethernet", 645 }, 646 { PCI_VENDOR_BROADCOM, 647 PCI_PRODUCT_BROADCOM_BCM57795, 648 "Broadcom BCM57795 Fast Ethernet", 649 }, 650 { PCI_VENDOR_SCHNEIDERKOCH, 651 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 652 "SysKonnect SK-9Dx1 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_3COM, 655 PCI_PRODUCT_3COM_3C996, 656 "3Com 3c996 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PW008GE4, 660 "Fujitsu PW008GE4 Gigabit Ethernet", 661 }, 662 { PCI_VENDOR_FUJITSU4, 663 PCI_PRODUCT_FUJITSU4_PW008GE5, 664 "Fujitsu PW008GE5 Gigabit Ethernet", 665 }, 666 { PCI_VENDOR_FUJITSU4, 667 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 668 "Fujitsu Primepower 250/450 Gigabit Ethernet", 669 }, 670 { 0, 671 0, 672 NULL }, 673 }; 674 675 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 676 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 677 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 678 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 679 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 680 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 681 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 682 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 683 684 static const struct bge_revision { 685 uint32_t br_chipid; 686 const char *br_name; 687 } bge_revisions[] = { 688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 743 /* 5754 and 5787 share the same ASIC ID */ 744 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 745 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 746 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 747 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 748 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 749 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 750 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 751 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 752 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 753 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 754 755 { 0, NULL } 756 }; 757 758 /* 759 * Some defaults for major revisions, so that newer steppings 760 * that we don't know about have a shot at working. 761 */ 762 static const struct bge_revision bge_majorrevs[] = { 763 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 764 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 765 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 766 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 767 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 768 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 769 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 772 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 773 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 774 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 775 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 776 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 777 /* 5754 and 5787 share the same ASIC ID */ 778 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 779 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 780 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 781 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 782 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 783 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 784 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 785 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 786 787 { 0, NULL } 788 }; 789 790 static int bge_allow_asf = 1; 791 792 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 793 bge_probe, bge_attach, NULL, NULL); 794 795 static uint32_t 796 bge_readmem_ind(struct bge_softc *sc, int off) 797 { 798 pcireg_t val; 799 800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 801 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 802 return 0; 803 804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 805 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 806 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 807 return val; 808 } 809 810 static void 811 bge_writemem_ind(struct bge_softc *sc, int off, int val) 812 { 813 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 817 } 818 819 /* 820 * PCI Express only 821 */ 822 static void 823 bge_set_max_readrq(struct bge_softc *sc) 824 { 825 pcireg_t val; 826 827 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 828 + PCI_PCIE_DCSR); 829 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 830 switch (sc->bge_expmrq) { 831 case 2048: 832 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 833 break; 834 case 4096: 835 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 836 break; 837 default: 838 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 839 break; 840 } 841 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 842 + PCI_PCIE_DCSR, val); 843 } 844 845 #ifdef notdef 846 static uint32_t 847 bge_readreg_ind(struct bge_softc *sc, int off) 848 { 849 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 850 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 851 } 852 #endif 853 854 static void 855 bge_writereg_ind(struct bge_softc *sc, int off, int val) 856 { 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 859 } 860 861 static void 862 bge_writemem_direct(struct bge_softc *sc, int off, int val) 863 { 864 CSR_WRITE_4(sc, off, val); 865 } 866 867 static void 868 bge_writembx(struct bge_softc *sc, int off, int val) 869 { 870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 871 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 872 873 CSR_WRITE_4(sc, off, val); 874 } 875 876 static void 877 bge_writembx_flush(struct bge_softc *sc, int off, int val) 878 { 879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 880 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 881 882 CSR_WRITE_4_FLUSH(sc, off, val); 883 } 884 885 /* 886 * Clear all stale locks and select the lock for this driver instance. 887 */ 888 void 889 bge_ape_lock_init(struct bge_softc *sc) 890 { 891 struct pci_attach_args *pa = &(sc->bge_pa); 892 uint32_t bit, regbase; 893 int i; 894 895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 896 regbase = BGE_APE_LOCK_GRANT; 897 else 898 regbase = BGE_APE_PER_LOCK_GRANT; 899 900 /* Clear any stale locks. */ 901 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 902 switch (i) { 903 case BGE_APE_LOCK_PHY0: 904 case BGE_APE_LOCK_PHY1: 905 case BGE_APE_LOCK_PHY2: 906 case BGE_APE_LOCK_PHY3: 907 bit = BGE_APE_LOCK_GRANT_DRIVER0; 908 break; 909 default: 910 if (pa->pa_function != 0) 911 bit = BGE_APE_LOCK_GRANT_DRIVER0; 912 else 913 bit = (1 << pa->pa_function); 914 } 915 APE_WRITE_4(sc, regbase + 4 * i, bit); 916 } 917 918 /* Select the PHY lock based on the device's function number. */ 919 switch (pa->pa_function) { 920 case 0: 921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 922 break; 923 case 1: 924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 925 break; 926 case 2: 927 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 928 break; 929 case 3: 930 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 931 break; 932 default: 933 printf("%s: PHY lock not supported on function\n", 934 device_xname(sc->bge_dev)); 935 break; 936 } 937 } 938 939 /* 940 * Check for APE firmware, set flags, and print version info. 941 */ 942 void 943 bge_ape_read_fw_ver(struct bge_softc *sc) 944 { 945 const char *fwtype; 946 uint32_t apedata, features; 947 948 /* Check for a valid APE signature in shared memory. */ 949 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 950 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 951 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 952 return; 953 } 954 955 /* Check if APE firmware is running. */ 956 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 957 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 958 printf("%s: APE signature found but FW status not ready! " 959 "0x%08x\n", device_xname(sc->bge_dev), apedata); 960 return; 961 } 962 963 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 964 965 /* Fetch the APE firwmare type and version. */ 966 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 967 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 968 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 969 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 970 fwtype = "NCSI"; 971 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 972 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 973 fwtype = "DASH"; 974 } else 975 fwtype = "UNKN"; 976 977 /* Print the APE firmware version. */ 978 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 979 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 980 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 981 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 982 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 983 } 984 985 int 986 bge_ape_lock(struct bge_softc *sc, int locknum) 987 { 988 struct pci_attach_args *pa = &(sc->bge_pa); 989 uint32_t bit, gnt, req, status; 990 int i, off; 991 992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 993 return (0); 994 995 /* Lock request/grant registers have different bases. */ 996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 997 req = BGE_APE_LOCK_REQ; 998 gnt = BGE_APE_LOCK_GRANT; 999 } else { 1000 req = BGE_APE_PER_LOCK_REQ; 1001 gnt = BGE_APE_PER_LOCK_GRANT; 1002 } 1003 1004 off = 4 * locknum; 1005 1006 switch (locknum) { 1007 case BGE_APE_LOCK_GPIO: 1008 /* Lock required when using GPIO. */ 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1010 return (0); 1011 if (pa->pa_function == 0) 1012 bit = BGE_APE_LOCK_REQ_DRIVER0; 1013 else 1014 bit = (1 << pa->pa_function); 1015 break; 1016 case BGE_APE_LOCK_GRC: 1017 /* Lock required to reset the device. */ 1018 if (pa->pa_function == 0) 1019 bit = BGE_APE_LOCK_REQ_DRIVER0; 1020 else 1021 bit = (1 << pa->pa_function); 1022 break; 1023 case BGE_APE_LOCK_MEM: 1024 /* Lock required when accessing certain APE memory. */ 1025 if (pa->pa_function == 0) 1026 bit = BGE_APE_LOCK_REQ_DRIVER0; 1027 else 1028 bit = (1 << pa->pa_function); 1029 break; 1030 case BGE_APE_LOCK_PHY0: 1031 case BGE_APE_LOCK_PHY1: 1032 case BGE_APE_LOCK_PHY2: 1033 case BGE_APE_LOCK_PHY3: 1034 /* Lock required when accessing PHYs. */ 1035 bit = BGE_APE_LOCK_REQ_DRIVER0; 1036 break; 1037 default: 1038 return (EINVAL); 1039 } 1040 1041 /* Request a lock. */ 1042 APE_WRITE_4_FLUSH(sc, req + off, bit); 1043 1044 /* Wait up to 1 second to acquire lock. */ 1045 for (i = 0; i < 20000; i++) { 1046 status = APE_READ_4(sc, gnt + off); 1047 if (status == bit) 1048 break; 1049 DELAY(50); 1050 } 1051 1052 /* Handle any errors. */ 1053 if (status != bit) { 1054 printf("%s: APE lock %d request failed! " 1055 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1056 device_xname(sc->bge_dev), 1057 locknum, req + off, bit & 0xFFFF, gnt + off, 1058 status & 0xFFFF); 1059 /* Revoke the lock request. */ 1060 APE_WRITE_4(sc, gnt + off, bit); 1061 return (EBUSY); 1062 } 1063 1064 return (0); 1065 } 1066 1067 void 1068 bge_ape_unlock(struct bge_softc *sc, int locknum) 1069 { 1070 struct pci_attach_args *pa = &(sc->bge_pa); 1071 uint32_t bit, gnt; 1072 int off; 1073 1074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1075 return; 1076 1077 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1078 gnt = BGE_APE_LOCK_GRANT; 1079 else 1080 gnt = BGE_APE_PER_LOCK_GRANT; 1081 1082 off = 4 * locknum; 1083 1084 switch (locknum) { 1085 case BGE_APE_LOCK_GPIO: 1086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1087 return; 1088 if (pa->pa_function == 0) 1089 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1090 else 1091 bit = (1 << pa->pa_function); 1092 break; 1093 case BGE_APE_LOCK_GRC: 1094 if (pa->pa_function == 0) 1095 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1096 else 1097 bit = (1 << pa->pa_function); 1098 break; 1099 case BGE_APE_LOCK_MEM: 1100 if (pa->pa_function == 0) 1101 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1102 else 1103 bit = (1 << pa->pa_function); 1104 break; 1105 case BGE_APE_LOCK_PHY0: 1106 case BGE_APE_LOCK_PHY1: 1107 case BGE_APE_LOCK_PHY2: 1108 case BGE_APE_LOCK_PHY3: 1109 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1110 break; 1111 default: 1112 return; 1113 } 1114 1115 /* Write and flush for consecutive bge_ape_lock() */ 1116 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1117 } 1118 1119 /* 1120 * Send an event to the APE firmware. 1121 */ 1122 void 1123 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1124 { 1125 uint32_t apedata; 1126 int i; 1127 1128 /* NCSI does not support APE events. */ 1129 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1130 return; 1131 1132 /* Wait up to 1ms for APE to service previous event. */ 1133 for (i = 10; i > 0; i--) { 1134 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1135 break; 1136 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1137 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1138 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1139 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1141 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1142 break; 1143 } 1144 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1145 DELAY(100); 1146 } 1147 if (i == 0) { 1148 printf("%s: APE event 0x%08x send timed out\n", 1149 device_xname(sc->bge_dev), event); 1150 } 1151 } 1152 1153 void 1154 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1155 { 1156 uint32_t apedata, event; 1157 1158 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1159 return; 1160 1161 switch (kind) { 1162 case BGE_RESET_START: 1163 /* If this is the first load, clear the load counter. */ 1164 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1165 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1166 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1167 else { 1168 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1169 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1170 } 1171 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1172 BGE_APE_HOST_SEG_SIG_MAGIC); 1173 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1174 BGE_APE_HOST_SEG_LEN_MAGIC); 1175 1176 /* Add some version info if bge(4) supports it. */ 1177 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1178 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1179 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1180 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1181 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1182 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_START); 1185 event = BGE_APE_EVENT_STATUS_STATE_START; 1186 break; 1187 case BGE_RESET_SHUTDOWN: 1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1189 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1190 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1191 break; 1192 case BGE_RESET_SUSPEND: 1193 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1194 break; 1195 default: 1196 return; 1197 } 1198 1199 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1200 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1201 } 1202 1203 static uint8_t 1204 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1205 { 1206 uint32_t access, byte = 0; 1207 int i; 1208 1209 /* Lock. */ 1210 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1211 for (i = 0; i < 8000; i++) { 1212 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1213 break; 1214 DELAY(20); 1215 } 1216 if (i == 8000) 1217 return 1; 1218 1219 /* Enable access. */ 1220 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1221 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1222 1223 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1224 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1225 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1226 DELAY(10); 1227 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1228 DELAY(10); 1229 break; 1230 } 1231 } 1232 1233 if (i == BGE_TIMEOUT * 10) { 1234 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1235 return 1; 1236 } 1237 1238 /* Get result. */ 1239 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1240 1241 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1242 1243 /* Disable access. */ 1244 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1245 1246 /* Unlock. */ 1247 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Read a sequence of bytes from NVRAM. 1254 */ 1255 static int 1256 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1257 { 1258 int error = 0, i; 1259 uint8_t byte = 0; 1260 1261 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1262 return 1; 1263 1264 for (i = 0; i < cnt; i++) { 1265 error = bge_nvram_getbyte(sc, off + i, &byte); 1266 if (error) 1267 break; 1268 *(dest + i) = byte; 1269 } 1270 1271 return (error ? 1 : 0); 1272 } 1273 1274 /* 1275 * Read a byte of data stored in the EEPROM at address 'addr.' The 1276 * BCM570x supports both the traditional bitbang interface and an 1277 * auto access interface for reading the EEPROM. We use the auto 1278 * access method. 1279 */ 1280 static uint8_t 1281 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1282 { 1283 int i; 1284 uint32_t byte = 0; 1285 1286 /* 1287 * Enable use of auto EEPROM access so we can avoid 1288 * having to use the bitbang method. 1289 */ 1290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1291 1292 /* Reset the EEPROM, load the clock period. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, 1294 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1295 DELAY(20); 1296 1297 /* Issue the read EEPROM command. */ 1298 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1299 1300 /* Wait for completion */ 1301 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1302 DELAY(10); 1303 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1304 break; 1305 } 1306 1307 if (i == BGE_TIMEOUT * 10) { 1308 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1309 return 1; 1310 } 1311 1312 /* Get result. */ 1313 byte = CSR_READ_4(sc, BGE_EE_DATA); 1314 1315 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1316 1317 return 0; 1318 } 1319 1320 /* 1321 * Read a sequence of bytes from the EEPROM. 1322 */ 1323 static int 1324 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1325 { 1326 int error = 0, i; 1327 uint8_t byte = 0; 1328 char *dest = destv; 1329 1330 for (i = 0; i < cnt; i++) { 1331 error = bge_eeprom_getbyte(sc, off + i, &byte); 1332 if (error) 1333 break; 1334 *(dest + i) = byte; 1335 } 1336 1337 return (error ? 1 : 0); 1338 } 1339 1340 static int 1341 bge_miibus_readreg(device_t dev, int phy, int reg) 1342 { 1343 struct bge_softc *sc = device_private(dev); 1344 uint32_t val; 1345 uint32_t autopoll; 1346 int i; 1347 1348 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1349 return 0; 1350 1351 /* Reading with autopolling on may trigger PCI errors */ 1352 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1353 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1354 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1355 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1356 DELAY(80); 1357 } 1358 1359 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1360 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1361 1362 for (i = 0; i < BGE_TIMEOUT; i++) { 1363 delay(10); 1364 val = CSR_READ_4(sc, BGE_MI_COMM); 1365 if (!(val & BGE_MICOMM_BUSY)) { 1366 DELAY(5); 1367 val = CSR_READ_4(sc, BGE_MI_COMM); 1368 break; 1369 } 1370 } 1371 1372 if (i == BGE_TIMEOUT) { 1373 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1374 val = 0; 1375 goto done; 1376 } 1377 1378 done: 1379 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1380 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1381 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1382 DELAY(80); 1383 } 1384 1385 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1386 1387 if (val & BGE_MICOMM_READFAIL) 1388 return 0; 1389 1390 return (val & 0xFFFF); 1391 } 1392 1393 static void 1394 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1395 { 1396 struct bge_softc *sc = device_private(dev); 1397 uint32_t autopoll; 1398 int i; 1399 1400 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1401 return; 1402 1403 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1404 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1405 return; 1406 1407 /* Reading with autopolling on may trigger PCI errors */ 1408 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1409 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1410 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1411 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1412 DELAY(80); 1413 } 1414 1415 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1416 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1417 1418 for (i = 0; i < BGE_TIMEOUT; i++) { 1419 delay(10); 1420 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1421 delay(5); 1422 CSR_READ_4(sc, BGE_MI_COMM); 1423 break; 1424 } 1425 } 1426 1427 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1428 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1429 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1430 delay(80); 1431 } 1432 1433 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1434 1435 if (i == BGE_TIMEOUT) 1436 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1437 } 1438 1439 static void 1440 bge_miibus_statchg(struct ifnet *ifp) 1441 { 1442 struct bge_softc *sc = ifp->if_softc; 1443 struct mii_data *mii = &sc->bge_mii; 1444 uint32_t mac_mode, rx_mode, tx_mode; 1445 1446 /* 1447 * Get flow control negotiation result. 1448 */ 1449 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1450 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1451 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1452 mii->mii_media_active &= ~IFM_ETH_FMASK; 1453 } 1454 1455 /* Set the port mode (MII/GMII) to match the link speed. */ 1456 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1457 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1458 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1459 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1460 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1461 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1462 mac_mode |= BGE_PORTMODE_GMII; 1463 else 1464 mac_mode |= BGE_PORTMODE_MII; 1465 1466 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1467 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1468 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1469 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1470 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1471 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1472 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1473 } else 1474 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1475 1476 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1477 DELAY(40); 1478 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1479 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1480 } 1481 1482 /* 1483 * Update rx threshold levels to values in a particular slot 1484 * of the interrupt-mitigation table bge_rx_threshes. 1485 */ 1486 static void 1487 bge_set_thresh(struct ifnet *ifp, int lvl) 1488 { 1489 struct bge_softc *sc = ifp->if_softc; 1490 int s; 1491 1492 /* For now, just save the new Rx-intr thresholds and record 1493 * that a threshold update is pending. Updating the hardware 1494 * registers here (even at splhigh()) is observed to 1495 * occasionaly cause glitches where Rx-interrupts are not 1496 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1497 */ 1498 s = splnet(); 1499 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1500 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1501 sc->bge_pending_rxintr_change = 1; 1502 splx(s); 1503 } 1504 1505 1506 /* 1507 * Update Rx thresholds of all bge devices 1508 */ 1509 static void 1510 bge_update_all_threshes(int lvl) 1511 { 1512 struct ifnet *ifp; 1513 const char * const namebuf = "bge"; 1514 int namelen; 1515 1516 if (lvl < 0) 1517 lvl = 0; 1518 else if (lvl >= NBGE_RX_THRESH) 1519 lvl = NBGE_RX_THRESH - 1; 1520 1521 namelen = strlen(namebuf); 1522 /* 1523 * Now search all the interfaces for this name/number 1524 */ 1525 IFNET_FOREACH(ifp) { 1526 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1527 continue; 1528 /* We got a match: update if doing auto-threshold-tuning */ 1529 if (bge_auto_thresh) 1530 bge_set_thresh(ifp, lvl); 1531 } 1532 } 1533 1534 /* 1535 * Handle events that have triggered interrupts. 1536 */ 1537 static void 1538 bge_handle_events(struct bge_softc *sc) 1539 { 1540 1541 return; 1542 } 1543 1544 /* 1545 * Memory management for jumbo frames. 1546 */ 1547 1548 static int 1549 bge_alloc_jumbo_mem(struct bge_softc *sc) 1550 { 1551 char *ptr, *kva; 1552 bus_dma_segment_t seg; 1553 int i, rseg, state, error; 1554 struct bge_jpool_entry *entry; 1555 1556 state = error = 0; 1557 1558 /* Grab a big chunk o' storage. */ 1559 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1560 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1561 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1562 return ENOBUFS; 1563 } 1564 1565 state = 1; 1566 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1567 BUS_DMA_NOWAIT)) { 1568 aprint_error_dev(sc->bge_dev, 1569 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1570 error = ENOBUFS; 1571 goto out; 1572 } 1573 1574 state = 2; 1575 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1576 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1577 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1578 error = ENOBUFS; 1579 goto out; 1580 } 1581 1582 state = 3; 1583 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1584 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1585 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1586 error = ENOBUFS; 1587 goto out; 1588 } 1589 1590 state = 4; 1591 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1592 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1593 1594 SLIST_INIT(&sc->bge_jfree_listhead); 1595 SLIST_INIT(&sc->bge_jinuse_listhead); 1596 1597 /* 1598 * Now divide it up into 9K pieces and save the addresses 1599 * in an array. 1600 */ 1601 ptr = sc->bge_cdata.bge_jumbo_buf; 1602 for (i = 0; i < BGE_JSLOTS; i++) { 1603 sc->bge_cdata.bge_jslots[i] = ptr; 1604 ptr += BGE_JLEN; 1605 entry = malloc(sizeof(struct bge_jpool_entry), 1606 M_DEVBUF, M_NOWAIT); 1607 if (entry == NULL) { 1608 aprint_error_dev(sc->bge_dev, 1609 "no memory for jumbo buffer queue!\n"); 1610 error = ENOBUFS; 1611 goto out; 1612 } 1613 entry->slot = i; 1614 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1615 entry, jpool_entries); 1616 } 1617 out: 1618 if (error != 0) { 1619 switch (state) { 1620 case 4: 1621 bus_dmamap_unload(sc->bge_dmatag, 1622 sc->bge_cdata.bge_rx_jumbo_map); 1623 case 3: 1624 bus_dmamap_destroy(sc->bge_dmatag, 1625 sc->bge_cdata.bge_rx_jumbo_map); 1626 case 2: 1627 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1628 case 1: 1629 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1630 break; 1631 default: 1632 break; 1633 } 1634 } 1635 1636 return error; 1637 } 1638 1639 /* 1640 * Allocate a jumbo buffer. 1641 */ 1642 static void * 1643 bge_jalloc(struct bge_softc *sc) 1644 { 1645 struct bge_jpool_entry *entry; 1646 1647 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1648 1649 if (entry == NULL) { 1650 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1651 return NULL; 1652 } 1653 1654 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1655 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1656 return (sc->bge_cdata.bge_jslots[entry->slot]); 1657 } 1658 1659 /* 1660 * Release a jumbo buffer. 1661 */ 1662 static void 1663 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1664 { 1665 struct bge_jpool_entry *entry; 1666 struct bge_softc *sc; 1667 int i, s; 1668 1669 /* Extract the softc struct pointer. */ 1670 sc = (struct bge_softc *)arg; 1671 1672 if (sc == NULL) 1673 panic("bge_jfree: can't find softc pointer!"); 1674 1675 /* calculate the slot this buffer belongs to */ 1676 1677 i = ((char *)buf 1678 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1679 1680 if ((i < 0) || (i >= BGE_JSLOTS)) 1681 panic("bge_jfree: asked to free buffer that we don't manage!"); 1682 1683 s = splvm(); 1684 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1685 if (entry == NULL) 1686 panic("bge_jfree: buffer not in use!"); 1687 entry->slot = i; 1688 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1689 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1690 1691 if (__predict_true(m != NULL)) 1692 pool_cache_put(mb_cache, m); 1693 splx(s); 1694 } 1695 1696 1697 /* 1698 * Initialize a standard receive ring descriptor. 1699 */ 1700 static int 1701 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1702 bus_dmamap_t dmamap) 1703 { 1704 struct mbuf *m_new = NULL; 1705 struct bge_rx_bd *r; 1706 int error; 1707 1708 if (dmamap == NULL) { 1709 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1710 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1711 if (error != 0) 1712 return error; 1713 } 1714 1715 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1716 1717 if (m == NULL) { 1718 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1719 if (m_new == NULL) 1720 return ENOBUFS; 1721 1722 MCLGET(m_new, M_DONTWAIT); 1723 if (!(m_new->m_flags & M_EXT)) { 1724 m_freem(m_new); 1725 return ENOBUFS; 1726 } 1727 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1728 1729 } else { 1730 m_new = m; 1731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1732 m_new->m_data = m_new->m_ext.ext_buf; 1733 } 1734 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1735 m_adj(m_new, ETHER_ALIGN); 1736 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1737 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1738 return ENOBUFS; 1739 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1740 BUS_DMASYNC_PREREAD); 1741 1742 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1743 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1744 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1745 r->bge_flags = BGE_RXBDFLAG_END; 1746 r->bge_len = m_new->m_len; 1747 r->bge_idx = i; 1748 1749 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1750 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1751 i * sizeof (struct bge_rx_bd), 1752 sizeof (struct bge_rx_bd), 1753 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1754 1755 return 0; 1756 } 1757 1758 /* 1759 * Initialize a jumbo receive ring descriptor. This allocates 1760 * a jumbo buffer from the pool managed internally by the driver. 1761 */ 1762 static int 1763 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1764 { 1765 struct mbuf *m_new = NULL; 1766 struct bge_rx_bd *r; 1767 void *buf = NULL; 1768 1769 if (m == NULL) { 1770 1771 /* Allocate the mbuf. */ 1772 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1773 if (m_new == NULL) 1774 return ENOBUFS; 1775 1776 /* Allocate the jumbo buffer */ 1777 buf = bge_jalloc(sc); 1778 if (buf == NULL) { 1779 m_freem(m_new); 1780 aprint_error_dev(sc->bge_dev, 1781 "jumbo allocation failed -- packet dropped!\n"); 1782 return ENOBUFS; 1783 } 1784 1785 /* Attach the buffer to the mbuf. */ 1786 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1787 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1788 bge_jfree, sc); 1789 m_new->m_flags |= M_EXT_RW; 1790 } else { 1791 m_new = m; 1792 buf = m_new->m_data = m_new->m_ext.ext_buf; 1793 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1794 } 1795 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1796 m_adj(m_new, ETHER_ALIGN); 1797 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1798 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1799 BUS_DMASYNC_PREREAD); 1800 /* Set up the descriptor. */ 1801 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1802 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1803 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1804 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1805 r->bge_len = m_new->m_len; 1806 r->bge_idx = i; 1807 1808 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1809 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1810 i * sizeof (struct bge_rx_bd), 1811 sizeof (struct bge_rx_bd), 1812 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1813 1814 return 0; 1815 } 1816 1817 /* 1818 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1819 * that's 1MB or memory, which is a lot. For now, we fill only the first 1820 * 256 ring entries and hope that our CPU is fast enough to keep up with 1821 * the NIC. 1822 */ 1823 static int 1824 bge_init_rx_ring_std(struct bge_softc *sc) 1825 { 1826 int i; 1827 1828 if (sc->bge_flags & BGE_RXRING_VALID) 1829 return 0; 1830 1831 for (i = 0; i < BGE_SSLOTS; i++) { 1832 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1833 return ENOBUFS; 1834 } 1835 1836 sc->bge_std = i - 1; 1837 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1838 1839 sc->bge_flags |= BGE_RXRING_VALID; 1840 1841 return 0; 1842 } 1843 1844 static void 1845 bge_free_rx_ring_std(struct bge_softc *sc) 1846 { 1847 int i; 1848 1849 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1850 return; 1851 1852 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1853 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1854 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1855 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1856 bus_dmamap_destroy(sc->bge_dmatag, 1857 sc->bge_cdata.bge_rx_std_map[i]); 1858 } 1859 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1860 sizeof(struct bge_rx_bd)); 1861 } 1862 1863 sc->bge_flags &= ~BGE_RXRING_VALID; 1864 } 1865 1866 static int 1867 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1868 { 1869 int i; 1870 volatile struct bge_rcb *rcb; 1871 1872 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1873 return 0; 1874 1875 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1876 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1877 return ENOBUFS; 1878 } 1879 1880 sc->bge_jumbo = i - 1; 1881 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1882 1883 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1884 rcb->bge_maxlen_flags = 0; 1885 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1886 1887 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1888 1889 return 0; 1890 } 1891 1892 static void 1893 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1894 { 1895 int i; 1896 1897 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1898 return; 1899 1900 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1901 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1902 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1903 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1904 } 1905 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1906 sizeof(struct bge_rx_bd)); 1907 } 1908 1909 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1910 } 1911 1912 static void 1913 bge_free_tx_ring(struct bge_softc *sc) 1914 { 1915 int i; 1916 struct txdmamap_pool_entry *dma; 1917 1918 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1919 return; 1920 1921 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1922 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1923 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1924 sc->bge_cdata.bge_tx_chain[i] = NULL; 1925 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1926 link); 1927 sc->txdma[i] = 0; 1928 } 1929 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1930 sizeof(struct bge_tx_bd)); 1931 } 1932 1933 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1934 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1935 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1936 free(dma, M_DEVBUF); 1937 } 1938 1939 sc->bge_flags &= ~BGE_TXRING_VALID; 1940 } 1941 1942 static int 1943 bge_init_tx_ring(struct bge_softc *sc) 1944 { 1945 int i; 1946 bus_dmamap_t dmamap; 1947 struct txdmamap_pool_entry *dma; 1948 1949 if (sc->bge_flags & BGE_TXRING_VALID) 1950 return 0; 1951 1952 sc->bge_txcnt = 0; 1953 sc->bge_tx_saved_considx = 0; 1954 1955 /* Initialize transmit producer index for host-memory send ring. */ 1956 sc->bge_tx_prodidx = 0; 1957 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1958 /* 5700 b2 errata */ 1959 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1960 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1961 1962 /* NIC-memory send ring not used; initialize to zero. */ 1963 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1964 /* 5700 b2 errata */ 1965 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1966 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1967 1968 SLIST_INIT(&sc->txdma_list); 1969 for (i = 0; i < BGE_RSLOTS; i++) { 1970 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1971 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1972 &dmamap)) 1973 return ENOBUFS; 1974 if (dmamap == NULL) 1975 panic("dmamap NULL in bge_init_tx_ring"); 1976 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1977 if (dma == NULL) { 1978 aprint_error_dev(sc->bge_dev, 1979 "can't alloc txdmamap_pool_entry\n"); 1980 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1981 return ENOMEM; 1982 } 1983 dma->dmamap = dmamap; 1984 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1985 } 1986 1987 sc->bge_flags |= BGE_TXRING_VALID; 1988 1989 return 0; 1990 } 1991 1992 static void 1993 bge_setmulti(struct bge_softc *sc) 1994 { 1995 struct ethercom *ac = &sc->ethercom; 1996 struct ifnet *ifp = &ac->ec_if; 1997 struct ether_multi *enm; 1998 struct ether_multistep step; 1999 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2000 uint32_t h; 2001 int i; 2002 2003 if (ifp->if_flags & IFF_PROMISC) 2004 goto allmulti; 2005 2006 /* Now program new ones. */ 2007 ETHER_FIRST_MULTI(step, ac, enm); 2008 while (enm != NULL) { 2009 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2010 /* 2011 * We must listen to a range of multicast addresses. 2012 * For now, just accept all multicasts, rather than 2013 * trying to set only those filter bits needed to match 2014 * the range. (At this time, the only use of address 2015 * ranges is for IP multicast routing, for which the 2016 * range is big enough to require all bits set.) 2017 */ 2018 goto allmulti; 2019 } 2020 2021 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2022 2023 /* Just want the 7 least-significant bits. */ 2024 h &= 0x7f; 2025 2026 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2027 ETHER_NEXT_MULTI(step, enm); 2028 } 2029 2030 ifp->if_flags &= ~IFF_ALLMULTI; 2031 goto setit; 2032 2033 allmulti: 2034 ifp->if_flags |= IFF_ALLMULTI; 2035 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2036 2037 setit: 2038 for (i = 0; i < 4; i++) 2039 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2040 } 2041 2042 static void 2043 bge_sig_pre_reset(struct bge_softc *sc, int type) 2044 { 2045 2046 /* 2047 * Some chips don't like this so only do this if ASF is enabled 2048 */ 2049 if (sc->bge_asf_mode) 2050 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2051 2052 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2053 switch (type) { 2054 case BGE_RESET_START: 2055 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2056 BGE_FW_DRV_STATE_START); 2057 break; 2058 case BGE_RESET_SHUTDOWN: 2059 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2060 BGE_FW_DRV_STATE_UNLOAD); 2061 break; 2062 case BGE_RESET_SUSPEND: 2063 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2064 BGE_FW_DRV_STATE_SUSPEND); 2065 break; 2066 } 2067 } 2068 2069 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2070 bge_ape_driver_state_change(sc, type); 2071 } 2072 2073 static void 2074 bge_sig_post_reset(struct bge_softc *sc, int type) 2075 { 2076 2077 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2078 switch (type) { 2079 case BGE_RESET_START: 2080 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2081 BGE_FW_DRV_STATE_START_DONE); 2082 /* START DONE */ 2083 break; 2084 case BGE_RESET_SHUTDOWN: 2085 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2086 BGE_FW_DRV_STATE_UNLOAD_DONE); 2087 break; 2088 } 2089 } 2090 2091 if (type == BGE_RESET_SHUTDOWN) 2092 bge_ape_driver_state_change(sc, type); 2093 } 2094 2095 static void 2096 bge_sig_legacy(struct bge_softc *sc, int type) 2097 { 2098 2099 if (sc->bge_asf_mode) { 2100 switch (type) { 2101 case BGE_RESET_START: 2102 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2103 BGE_FW_DRV_STATE_START); 2104 break; 2105 case BGE_RESET_SHUTDOWN: 2106 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2107 BGE_FW_DRV_STATE_UNLOAD); 2108 break; 2109 } 2110 } 2111 } 2112 2113 static void 2114 bge_wait_for_event_ack(struct bge_softc *sc) 2115 { 2116 int i; 2117 2118 /* wait up to 2500usec */ 2119 for (i = 0; i < 250; i++) { 2120 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2121 BGE_RX_CPU_DRV_EVENT)) 2122 break; 2123 DELAY(10); 2124 } 2125 } 2126 2127 static void 2128 bge_stop_fw(struct bge_softc *sc) 2129 { 2130 2131 if (sc->bge_asf_mode) { 2132 bge_wait_for_event_ack(sc); 2133 2134 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2135 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2136 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2137 2138 bge_wait_for_event_ack(sc); 2139 } 2140 } 2141 2142 static int 2143 bge_poll_fw(struct bge_softc *sc) 2144 { 2145 uint32_t val; 2146 int i; 2147 2148 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2149 for (i = 0; i < BGE_TIMEOUT; i++) { 2150 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2151 if (val & BGE_VCPU_STATUS_INIT_DONE) 2152 break; 2153 DELAY(100); 2154 } 2155 if (i >= BGE_TIMEOUT) { 2156 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2157 return -1; 2158 } 2159 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2160 /* 2161 * Poll the value location we just wrote until 2162 * we see the 1's complement of the magic number. 2163 * This indicates that the firmware initialization 2164 * is complete. 2165 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2166 */ 2167 for (i = 0; i < BGE_TIMEOUT; i++) { 2168 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2169 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2170 break; 2171 DELAY(10); 2172 } 2173 2174 if (i >= BGE_TIMEOUT) { 2175 aprint_error_dev(sc->bge_dev, 2176 "firmware handshake timed out, val = %x\n", val); 2177 return -1; 2178 } 2179 } 2180 2181 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2182 /* tg3 says we have to wait extra time */ 2183 delay(10 * 1000); 2184 } 2185 2186 return 0; 2187 } 2188 2189 int 2190 bge_phy_addr(struct bge_softc *sc) 2191 { 2192 struct pci_attach_args *pa = &(sc->bge_pa); 2193 int phy_addr = 1; 2194 2195 /* 2196 * PHY address mapping for various devices. 2197 * 2198 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2199 * ---------+-------+-------+-------+-------+ 2200 * BCM57XX | 1 | X | X | X | 2201 * BCM5704 | 1 | X | 1 | X | 2202 * BCM5717 | 1 | 8 | 2 | 9 | 2203 * BCM5719 | 1 | 8 | 2 | 9 | 2204 * BCM5720 | 1 | 8 | 2 | 9 | 2205 * 2206 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2207 * ---------+-------+-------+-------+-------+ 2208 * BCM57XX | X | X | X | X | 2209 * BCM5704 | X | X | X | X | 2210 * BCM5717 | X | X | X | X | 2211 * BCM5719 | 3 | 10 | 4 | 11 | 2212 * BCM5720 | X | X | X | X | 2213 * 2214 * Other addresses may respond but they are not 2215 * IEEE compliant PHYs and should be ignored. 2216 */ 2217 switch (BGE_ASICREV(sc->bge_chipid)) { 2218 case BGE_ASICREV_BCM5717: 2219 case BGE_ASICREV_BCM5719: 2220 case BGE_ASICREV_BCM5720: 2221 phy_addr = pa->pa_function; 2222 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2223 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2224 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2225 } else { 2226 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2227 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2228 } 2229 } 2230 2231 return phy_addr; 2232 } 2233 2234 /* 2235 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2236 * self-test results. 2237 */ 2238 static int 2239 bge_chipinit(struct bge_softc *sc) 2240 { 2241 uint32_t dma_rw_ctl, mode_ctl, reg; 2242 int i; 2243 2244 /* Set endianness before we access any non-PCI registers. */ 2245 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2246 BGE_INIT); 2247 2248 /* 2249 * Clear the MAC statistics block in the NIC's 2250 * internal memory. 2251 */ 2252 for (i = BGE_STATS_BLOCK; 2253 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2254 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2255 2256 for (i = BGE_STATUS_BLOCK; 2257 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2258 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2259 2260 /* 5717 workaround from tg3 */ 2261 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2262 /* Save */ 2263 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2264 2265 /* Temporary modify MODE_CTL to control TLP */ 2266 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2267 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2268 2269 /* Control TLP */ 2270 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2271 BGE_TLP_PHYCTL1); 2272 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2273 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2274 2275 /* Restore */ 2276 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2277 } 2278 2279 /* XXX Should we use 57765_FAMILY? */ 2280 if (BGE_IS_57765_PLUS(sc)) { 2281 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2282 /* Save */ 2283 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2284 2285 /* Temporary modify MODE_CTL to control TLP */ 2286 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2287 CSR_WRITE_4(sc, BGE_MODE_CTL, 2288 reg | BGE_MODECTL_PCIE_TLPADDR1); 2289 2290 /* Control TLP */ 2291 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2292 BGE_TLP_PHYCTL5); 2293 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2294 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2295 2296 /* Restore */ 2297 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2298 } 2299 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2300 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2301 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2302 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2303 2304 /* Save */ 2305 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2306 2307 /* Temporary modify MODE_CTL to control TLP */ 2308 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2309 CSR_WRITE_4(sc, BGE_MODE_CTL, 2310 reg | BGE_MODECTL_PCIE_TLPADDR0); 2311 2312 /* Control TLP */ 2313 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2314 BGE_TLP_FTSMAX); 2315 reg &= ~BGE_TLP_FTSMAX_MSK; 2316 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2317 reg | BGE_TLP_FTSMAX_VAL); 2318 2319 /* Restore */ 2320 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2321 } 2322 2323 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2324 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2325 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2326 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2327 } 2328 2329 /* Set up the PCI DMA control register. */ 2330 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2331 if (sc->bge_flags & BGE_PCIE) { 2332 /* Read watermark not used, 128 bytes for write. */ 2333 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2334 device_xname(sc->bge_dev))); 2335 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2336 } else if (sc->bge_flags & BGE_PCIX) { 2337 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2338 device_xname(sc->bge_dev))); 2339 /* PCI-X bus */ 2340 if (BGE_IS_5714_FAMILY(sc)) { 2341 /* 256 bytes for read and write. */ 2342 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2343 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2344 2345 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2346 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2347 else 2348 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2349 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2350 /* 1536 bytes for read, 384 bytes for write. */ 2351 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2352 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2353 } else { 2354 /* 384 bytes for read and write. */ 2355 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2356 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2357 (0x0F); 2358 } 2359 2360 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2361 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2362 uint32_t tmp; 2363 2364 /* Set ONEDMA_ATONCE for hardware workaround. */ 2365 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2366 if (tmp == 6 || tmp == 7) 2367 dma_rw_ctl |= 2368 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2369 2370 /* Set PCI-X DMA write workaround. */ 2371 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2372 } 2373 } else { 2374 /* Conventional PCI bus: 256 bytes for read and write. */ 2375 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2376 device_xname(sc->bge_dev))); 2377 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2378 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2379 2380 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2381 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2382 dma_rw_ctl |= 0x0F; 2383 } 2384 2385 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2386 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2387 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2388 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2389 2390 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2391 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2392 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2393 2394 if (BGE_IS_5717_PLUS(sc)) { 2395 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2396 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2397 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2398 2399 /* 2400 * Enable HW workaround for controllers that misinterpret 2401 * a status tag update and leave interrupts permanently 2402 * disabled. 2403 */ 2404 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2405 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2406 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2407 } 2408 2409 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2410 dma_rw_ctl); 2411 2412 /* 2413 * Set up general mode register. 2414 */ 2415 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2416 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2417 /* Retain Host-2-BMC settings written by APE firmware. */ 2418 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2419 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2420 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2421 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2422 } 2423 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2424 BGE_MODECTL_TX_NO_PHDR_CSUM; 2425 2426 /* 2427 * BCM5701 B5 have a bug causing data corruption when using 2428 * 64-bit DMA reads, which can be terminated early and then 2429 * completed later as 32-bit accesses, in combination with 2430 * certain bridges. 2431 */ 2432 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2433 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2434 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2435 2436 /* 2437 * Tell the firmware the driver is running 2438 */ 2439 if (sc->bge_asf_mode & ASF_STACKUP) 2440 mode_ctl |= BGE_MODECTL_STACKUP; 2441 2442 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2443 2444 /* 2445 * Disable memory write invalidate. Apparently it is not supported 2446 * properly by these devices. 2447 */ 2448 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2449 PCI_COMMAND_INVALIDATE_ENABLE); 2450 2451 #ifdef __brokenalpha__ 2452 /* 2453 * Must insure that we do not cross an 8K (bytes) boundary 2454 * for DMA reads. Our highest limit is 1K bytes. This is a 2455 * restriction on some ALPHA platforms with early revision 2456 * 21174 PCI chipsets, such as the AlphaPC 164lx 2457 */ 2458 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2459 #endif 2460 2461 /* Set the timer prescaler (always 66MHz) */ 2462 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2463 2464 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2465 DELAY(40); /* XXX */ 2466 2467 /* Put PHY into ready state */ 2468 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2469 DELAY(40); 2470 } 2471 2472 return 0; 2473 } 2474 2475 static int 2476 bge_blockinit(struct bge_softc *sc) 2477 { 2478 volatile struct bge_rcb *rcb; 2479 bus_size_t rcb_addr; 2480 struct ifnet *ifp = &sc->ethercom.ec_if; 2481 bge_hostaddr taddr; 2482 uint32_t dmactl, val; 2483 int i, limit; 2484 2485 /* 2486 * Initialize the memory window pointer register so that 2487 * we can access the first 32K of internal NIC RAM. This will 2488 * allow us to set up the TX send ring RCBs and the RX return 2489 * ring RCBs, plus other things which live in NIC memory. 2490 */ 2491 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2492 2493 /* Step 33: Configure mbuf memory pool */ 2494 if (!BGE_IS_5705_PLUS(sc)) { 2495 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2496 BGE_BUFFPOOL_1); 2497 2498 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2499 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2500 else 2501 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2502 2503 /* Configure DMA resource pool */ 2504 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2505 BGE_DMA_DESCRIPTORS); 2506 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2507 } 2508 2509 /* Step 35: Configure mbuf pool watermarks */ 2510 /* new broadcom docs strongly recommend these: */ 2511 if (BGE_IS_5717_PLUS(sc)) { 2512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2514 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2515 } else if (BGE_IS_5705_PLUS(sc)) { 2516 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2517 2518 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2521 } else { 2522 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2524 } 2525 } else { 2526 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2529 } 2530 2531 /* Step 36: Configure DMA resource watermarks */ 2532 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2533 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2534 2535 /* Step 38: Enable buffer manager */ 2536 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2537 /* 2538 * Change the arbitration algorithm of TXMBUF read request to 2539 * round-robin instead of priority based for BCM5719. When 2540 * TXFIFO is almost empty, RDMA will hold its request until 2541 * TXFIFO is not almost empty. 2542 */ 2543 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2544 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2546 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2547 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2548 val |= BGE_BMANMODE_LOMBUF_ATTN; 2549 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2550 2551 /* Step 39: Poll for buffer manager start indication */ 2552 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2553 DELAY(10); 2554 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2555 break; 2556 } 2557 2558 if (i == BGE_TIMEOUT * 2) { 2559 aprint_error_dev(sc->bge_dev, 2560 "buffer manager failed to start\n"); 2561 return ENXIO; 2562 } 2563 2564 /* Step 40: Enable flow-through queues */ 2565 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2566 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2567 2568 /* Wait until queue initialization is complete */ 2569 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2570 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2571 break; 2572 DELAY(10); 2573 } 2574 2575 if (i == BGE_TIMEOUT * 2) { 2576 aprint_error_dev(sc->bge_dev, 2577 "flow-through queue init failed\n"); 2578 return ENXIO; 2579 } 2580 2581 /* 2582 * Summary of rings supported by the controller: 2583 * 2584 * Standard Receive Producer Ring 2585 * - This ring is used to feed receive buffers for "standard" 2586 * sized frames (typically 1536 bytes) to the controller. 2587 * 2588 * Jumbo Receive Producer Ring 2589 * - This ring is used to feed receive buffers for jumbo sized 2590 * frames (i.e. anything bigger than the "standard" frames) 2591 * to the controller. 2592 * 2593 * Mini Receive Producer Ring 2594 * - This ring is used to feed receive buffers for "mini" 2595 * sized frames to the controller. 2596 * - This feature required external memory for the controller 2597 * but was never used in a production system. Should always 2598 * be disabled. 2599 * 2600 * Receive Return Ring 2601 * - After the controller has placed an incoming frame into a 2602 * receive buffer that buffer is moved into a receive return 2603 * ring. The driver is then responsible to passing the 2604 * buffer up to the stack. Many versions of the controller 2605 * support multiple RR rings. 2606 * 2607 * Send Ring 2608 * - This ring is used for outgoing frames. Many versions of 2609 * the controller support multiple send rings. 2610 */ 2611 2612 /* Step 41: Initialize the standard RX ring control block */ 2613 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2614 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2615 if (BGE_IS_5717_PLUS(sc)) { 2616 /* 2617 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2618 * Bits 15-2 : Maximum RX frame size 2619 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2620 * Bit 0 : Reserved 2621 */ 2622 rcb->bge_maxlen_flags = 2623 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2624 } else if (BGE_IS_5705_PLUS(sc)) { 2625 /* 2626 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2627 * Bits 15-2 : Reserved (should be 0) 2628 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2629 * Bit 0 : Reserved 2630 */ 2631 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2632 } else { 2633 /* 2634 * Ring size is always XXX entries 2635 * Bits 31-16: Maximum RX frame size 2636 * Bits 15-2 : Reserved (should be 0) 2637 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2638 * Bit 0 : Reserved 2639 */ 2640 rcb->bge_maxlen_flags = 2641 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2642 } 2643 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2644 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2646 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2647 else 2648 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2649 /* Write the standard receive producer ring control block. */ 2650 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2651 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2652 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2653 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2654 2655 /* Reset the standard receive producer ring producer index. */ 2656 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2657 2658 /* 2659 * Step 42: Initialize the jumbo RX ring control block 2660 * We set the 'ring disabled' bit in the flags 2661 * field until we're actually ready to start 2662 * using this ring (i.e. once we set the MTU 2663 * high enough to require it). 2664 */ 2665 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2666 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2667 BGE_HOSTADDR(rcb->bge_hostaddr, 2668 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2669 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2670 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2671 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2672 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2674 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2675 else 2676 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2677 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2678 rcb->bge_hostaddr.bge_addr_hi); 2679 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2680 rcb->bge_hostaddr.bge_addr_lo); 2681 /* Program the jumbo receive producer ring RCB parameters. */ 2682 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2683 rcb->bge_maxlen_flags); 2684 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2685 /* Reset the jumbo receive producer ring producer index. */ 2686 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2687 } 2688 2689 /* Disable the mini receive producer ring RCB. */ 2690 if (BGE_IS_5700_FAMILY(sc)) { 2691 /* Set up dummy disabled mini ring RCB */ 2692 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2693 rcb->bge_maxlen_flags = 2694 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2695 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2696 rcb->bge_maxlen_flags); 2697 /* Reset the mini receive producer ring producer index. */ 2698 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2699 2700 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2701 offsetof(struct bge_ring_data, bge_info), 2702 sizeof (struct bge_gib), 2703 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2704 } 2705 2706 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2707 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2708 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2709 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2710 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2711 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2712 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2713 } 2714 /* 2715 * The BD ring replenish thresholds control how often the 2716 * hardware fetches new BD's from the producer rings in host 2717 * memory. Setting the value too low on a busy system can 2718 * starve the hardware and recue the throughpout. 2719 * 2720 * Set the BD ring replenish thresholds. The recommended 2721 * values are 1/8th the number of descriptors allocated to 2722 * each ring, but since we try to avoid filling the entire 2723 * ring we set these to the minimal value of 8. This needs to 2724 * be done on several of the supported chip revisions anyway, 2725 * to work around HW bugs. 2726 */ 2727 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2728 if (BGE_IS_JUMBO_CAPABLE(sc)) 2729 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2730 2731 if (BGE_IS_5717_PLUS(sc)) { 2732 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2733 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2734 } 2735 2736 /* 2737 * Disable all send rings by setting the 'ring disabled' bit 2738 * in the flags field of all the TX send ring control blocks, 2739 * located in NIC memory. 2740 */ 2741 if (BGE_IS_5700_FAMILY(sc)) { 2742 /* 5700 to 5704 had 16 send rings. */ 2743 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2744 } else 2745 limit = 1; 2746 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2747 for (i = 0; i < limit; i++) { 2748 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2749 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2750 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2751 rcb_addr += sizeof(struct bge_rcb); 2752 } 2753 2754 /* Configure send ring RCB 0 (we use only the first ring) */ 2755 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2756 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2757 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2758 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2759 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2760 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2761 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2762 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2763 else 2764 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2765 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2766 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2767 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2768 2769 /* 2770 * Disable all receive return rings by setting the 2771 * 'ring diabled' bit in the flags field of all the receive 2772 * return ring control blocks, located in NIC memory. 2773 */ 2774 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2775 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2776 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2777 /* Should be 17, use 16 until we get an SRAM map. */ 2778 limit = 16; 2779 } else if (BGE_IS_5700_FAMILY(sc)) 2780 limit = BGE_RX_RINGS_MAX; 2781 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2782 BGE_IS_57765_PLUS(sc)) 2783 limit = 4; 2784 else 2785 limit = 1; 2786 /* Disable all receive return rings */ 2787 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2788 for (i = 0; i < limit; i++) { 2789 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2790 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2791 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2792 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2793 BGE_RCB_FLAG_RING_DISABLED)); 2794 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2795 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2796 (i * (sizeof(uint64_t))), 0); 2797 rcb_addr += sizeof(struct bge_rcb); 2798 } 2799 2800 /* 2801 * Set up receive return ring 0. Note that the NIC address 2802 * for RX return rings is 0x0. The return rings live entirely 2803 * within the host, so the nicaddr field in the RCB isn't used. 2804 */ 2805 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2806 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2807 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2808 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2809 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2810 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2811 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2812 2813 /* Set random backoff seed for TX */ 2814 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2815 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2816 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2817 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2818 BGE_TX_BACKOFF_SEED_MASK); 2819 2820 /* Set inter-packet gap */ 2821 val = 0x2620; 2822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2823 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2824 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2825 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2826 2827 /* 2828 * Specify which ring to use for packets that don't match 2829 * any RX rules. 2830 */ 2831 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2832 2833 /* 2834 * Configure number of RX lists. One interrupt distribution 2835 * list, sixteen active lists, one bad frames class. 2836 */ 2837 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2838 2839 /* Inialize RX list placement stats mask. */ 2840 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2841 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2842 2843 /* Disable host coalescing until we get it set up */ 2844 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2845 2846 /* Poll to make sure it's shut down. */ 2847 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2848 DELAY(10); 2849 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2850 break; 2851 } 2852 2853 if (i == BGE_TIMEOUT * 2) { 2854 aprint_error_dev(sc->bge_dev, 2855 "host coalescing engine failed to idle\n"); 2856 return ENXIO; 2857 } 2858 2859 /* Set up host coalescing defaults */ 2860 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2861 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2862 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2863 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2864 if (!(BGE_IS_5705_PLUS(sc))) { 2865 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2866 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2867 } 2868 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2869 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2870 2871 /* Set up address of statistics block */ 2872 if (BGE_IS_5700_FAMILY(sc)) { 2873 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2874 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2875 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2876 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2877 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2878 } 2879 2880 /* Set up address of status block */ 2881 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2882 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2883 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2884 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2885 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2886 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2887 2888 /* Set up status block size. */ 2889 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2890 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2891 val = BGE_STATBLKSZ_FULL; 2892 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2893 } else { 2894 val = BGE_STATBLKSZ_32BYTE; 2895 bzero(&sc->bge_rdata->bge_status_block, 32); 2896 } 2897 2898 /* Turn on host coalescing state machine */ 2899 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2900 2901 /* Turn on RX BD completion state machine and enable attentions */ 2902 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2903 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2904 2905 /* Turn on RX list placement state machine */ 2906 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2907 2908 /* Turn on RX list selector state machine. */ 2909 if (!(BGE_IS_5705_PLUS(sc))) 2910 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2911 2912 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2913 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2914 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2915 BGE_MACMODE_FRMHDR_DMA_ENB; 2916 2917 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2918 val |= BGE_PORTMODE_TBI; 2919 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2920 val |= BGE_PORTMODE_GMII; 2921 else 2922 val |= BGE_PORTMODE_MII; 2923 2924 /* Allow APE to send/receive frames. */ 2925 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2926 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2927 2928 /* Turn on DMA, clear stats */ 2929 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2930 DELAY(40); 2931 2932 /* Set misc. local control, enable interrupts on attentions */ 2933 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2934 if (BGE_IS_5717_PLUS(sc)) { 2935 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2936 DELAY(100); 2937 } 2938 2939 /* Turn on DMA completion state machine */ 2940 if (!(BGE_IS_5705_PLUS(sc))) 2941 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2942 2943 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2944 2945 /* Enable host coalescing bug fix. */ 2946 if (BGE_IS_5755_PLUS(sc)) 2947 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2948 2949 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2950 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2951 2952 /* Turn on write DMA state machine */ 2953 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2954 DELAY(40); 2955 2956 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2957 2958 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2959 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2960 2961 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2962 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2963 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2964 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2965 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2966 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2967 2968 if (sc->bge_flags & BGE_PCIE) 2969 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2970 if (sc->bge_flags & BGE_TSO) 2971 val |= BGE_RDMAMODE_TSO4_ENABLE; 2972 2973 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2974 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2975 BGE_RDMAMODE_H2BNC_VLAN_DET; 2976 /* 2977 * Allow multiple outstanding read requests from 2978 * non-LSO read DMA engine. 2979 */ 2980 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2981 } 2982 2983 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2984 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2985 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2986 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2987 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2988 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2989 /* 2990 * Adjust tx margin to prevent TX data corruption and 2991 * fix internal FIFO overflow. 2992 */ 2993 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2994 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2995 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2996 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2997 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2998 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2999 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3000 } 3001 /* 3002 * Enable fix for read DMA FIFO overruns. 3003 * The fix is to limit the number of RX BDs 3004 * the hardware would fetch at a fime. 3005 */ 3006 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3007 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3008 } 3009 3010 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3011 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3012 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3013 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3014 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3015 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3016 /* 3017 * Allow 4KB burst length reads for non-LSO frames. 3018 * Enable 512B burst length reads for buffer descriptors. 3019 */ 3020 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3021 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3022 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3023 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3024 } 3025 3026 /* Turn on read DMA state machine */ 3027 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3028 delay(40); 3029 3030 /* Turn on RX data completion state machine */ 3031 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3032 3033 /* Turn on RX data and RX BD initiator state machine */ 3034 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3035 3036 /* Turn on Mbuf cluster free state machine */ 3037 if (!BGE_IS_5705_PLUS(sc)) 3038 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3039 3040 /* Turn on send data completion state machine */ 3041 val = BGE_SDCMODE_ENABLE; 3042 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3043 val |= BGE_SDCMODE_CDELAY; 3044 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3045 3046 /* Turn on send BD completion state machine */ 3047 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3048 3049 /* Turn on RX BD initiator state machine */ 3050 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3051 3052 /* Turn on send data initiator state machine */ 3053 if (sc->bge_flags & BGE_TSO) { 3054 /* XXX: magic value from Linux driver */ 3055 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3056 BGE_SDIMODE_HW_LSO_PRE_DMA); 3057 } else 3058 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3059 3060 /* Turn on send BD initiator state machine */ 3061 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3062 3063 /* Turn on send BD selector state machine */ 3064 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3065 3066 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3067 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3068 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3069 3070 /* ack/clear link change events */ 3071 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3072 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3073 BGE_MACSTAT_LINK_CHANGED); 3074 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3075 3076 /* 3077 * Enable attention when the link has changed state for 3078 * devices that use auto polling. 3079 */ 3080 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3081 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3082 } else { 3083 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3084 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3086 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3087 BGE_EVTENB_MI_INTERRUPT); 3088 } 3089 3090 /* 3091 * Clear any pending link state attention. 3092 * Otherwise some link state change events may be lost until attention 3093 * is cleared by bge_intr() -> bge_link_upd() sequence. 3094 * It's not necessary on newer BCM chips - perhaps enabling link 3095 * state change attentions implies clearing pending attention. 3096 */ 3097 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3098 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3099 BGE_MACSTAT_LINK_CHANGED); 3100 3101 /* Enable link state change attentions. */ 3102 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3103 3104 return 0; 3105 } 3106 3107 static const struct bge_revision * 3108 bge_lookup_rev(uint32_t chipid) 3109 { 3110 const struct bge_revision *br; 3111 3112 for (br = bge_revisions; br->br_name != NULL; br++) { 3113 if (br->br_chipid == chipid) 3114 return br; 3115 } 3116 3117 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3118 if (br->br_chipid == BGE_ASICREV(chipid)) 3119 return br; 3120 } 3121 3122 return NULL; 3123 } 3124 3125 static const struct bge_product * 3126 bge_lookup(const struct pci_attach_args *pa) 3127 { 3128 const struct bge_product *bp; 3129 3130 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3131 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3132 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3133 return bp; 3134 } 3135 3136 return NULL; 3137 } 3138 3139 static uint32_t 3140 bge_chipid(const struct pci_attach_args *pa) 3141 { 3142 uint32_t id; 3143 3144 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3145 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3146 3147 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3148 switch (PCI_PRODUCT(pa->pa_id)) { 3149 case PCI_PRODUCT_BROADCOM_BCM5717: 3150 case PCI_PRODUCT_BROADCOM_BCM5718: 3151 case PCI_PRODUCT_BROADCOM_BCM5719: 3152 case PCI_PRODUCT_BROADCOM_BCM5720: 3153 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3154 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3155 BGE_PCI_GEN2_PRODID_ASICREV); 3156 break; 3157 case PCI_PRODUCT_BROADCOM_BCM57761: 3158 case PCI_PRODUCT_BROADCOM_BCM57762: 3159 case PCI_PRODUCT_BROADCOM_BCM57765: 3160 case PCI_PRODUCT_BROADCOM_BCM57766: 3161 case PCI_PRODUCT_BROADCOM_BCM57781: 3162 case PCI_PRODUCT_BROADCOM_BCM57785: 3163 case PCI_PRODUCT_BROADCOM_BCM57791: 3164 case PCI_PRODUCT_BROADCOM_BCM57795: 3165 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3166 BGE_PCI_GEN15_PRODID_ASICREV); 3167 break; 3168 default: 3169 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3170 BGE_PCI_PRODID_ASICREV); 3171 break; 3172 } 3173 } 3174 3175 return id; 3176 } 3177 3178 /* 3179 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3180 * against our list and return its name if we find a match. Note 3181 * that since the Broadcom controller contains VPD support, we 3182 * can get the device name string from the controller itself instead 3183 * of the compiled-in string. This is a little slow, but it guarantees 3184 * we'll always announce the right product name. 3185 */ 3186 static int 3187 bge_probe(device_t parent, cfdata_t match, void *aux) 3188 { 3189 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3190 3191 if (bge_lookup(pa) != NULL) 3192 return 1; 3193 3194 return 0; 3195 } 3196 3197 static void 3198 bge_attach(device_t parent, device_t self, void *aux) 3199 { 3200 struct bge_softc *sc = device_private(self); 3201 struct pci_attach_args *pa = aux; 3202 prop_dictionary_t dict; 3203 const struct bge_product *bp; 3204 const struct bge_revision *br; 3205 pci_chipset_tag_t pc; 3206 pci_intr_handle_t ih; 3207 const char *intrstr = NULL; 3208 bus_dma_segment_t seg; 3209 int rseg; 3210 uint32_t hwcfg = 0; 3211 uint32_t command; 3212 struct ifnet *ifp; 3213 uint32_t misccfg; 3214 void * kva; 3215 u_char eaddr[ETHER_ADDR_LEN]; 3216 pcireg_t memtype, subid, reg; 3217 bus_addr_t memaddr; 3218 bus_size_t memsize, apesize; 3219 uint32_t pm_ctl; 3220 bool no_seeprom; 3221 int capmask; 3222 3223 bp = bge_lookup(pa); 3224 KASSERT(bp != NULL); 3225 3226 sc->sc_pc = pa->pa_pc; 3227 sc->sc_pcitag = pa->pa_tag; 3228 sc->bge_dev = self; 3229 3230 sc->bge_pa = *pa; 3231 pc = sc->sc_pc; 3232 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3233 3234 aprint_naive(": Ethernet controller\n"); 3235 aprint_normal(": %s\n", bp->bp_name); 3236 3237 /* 3238 * Map control/status registers. 3239 */ 3240 DPRINTFN(5, ("Map control/status regs\n")); 3241 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3242 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3243 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3244 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3245 3246 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3247 aprint_error_dev(sc->bge_dev, 3248 "failed to enable memory mapping!\n"); 3249 return; 3250 } 3251 3252 DPRINTFN(5, ("pci_mem_find\n")); 3253 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3254 switch (memtype) { 3255 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3256 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3257 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3258 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3259 &memaddr, &memsize) == 0) 3260 break; 3261 default: 3262 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3263 return; 3264 } 3265 3266 DPRINTFN(5, ("pci_intr_map\n")); 3267 if (pci_intr_map(pa, &ih)) { 3268 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3269 return; 3270 } 3271 3272 DPRINTFN(5, ("pci_intr_string\n")); 3273 intrstr = pci_intr_string(pc, ih); 3274 3275 DPRINTFN(5, ("pci_intr_establish\n")); 3276 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3277 3278 if (sc->bge_intrhand == NULL) { 3279 aprint_error_dev(sc->bge_dev, 3280 "couldn't establish interrupt%s%s\n", 3281 intrstr ? " at " : "", intrstr ? intrstr : ""); 3282 return; 3283 } 3284 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3285 3286 /* Save various chip information. */ 3287 sc->bge_chipid = bge_chipid(pa); 3288 sc->bge_phy_addr = bge_phy_addr(sc); 3289 3290 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3291 &sc->bge_pciecap, NULL) != 0) 3292 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3293 /* PCIe */ 3294 sc->bge_flags |= BGE_PCIE; 3295 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3296 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3297 sc->bge_expmrq = 2048; 3298 else 3299 sc->bge_expmrq = 4096; 3300 bge_set_max_readrq(sc); 3301 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3302 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3303 /* PCI-X */ 3304 sc->bge_flags |= BGE_PCIX; 3305 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3306 &sc->bge_pcixcap, NULL) == 0) 3307 aprint_error_dev(sc->bge_dev, 3308 "unable to find PCIX capability\n"); 3309 } 3310 3311 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3312 /* 3313 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3314 * can clobber the chip's PCI config-space power control 3315 * registers, leaving the card in D3 powersave state. We do 3316 * not have memory-mapped registers in this state, so force 3317 * device into D0 state before starting initialization. 3318 */ 3319 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3320 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3321 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3322 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3323 DELAY(1000); /* 27 usec is allegedly sufficent */ 3324 } 3325 3326 /* Save chipset family. */ 3327 switch (BGE_ASICREV(sc->bge_chipid)) { 3328 case BGE_ASICREV_BCM57765: 3329 case BGE_ASICREV_BCM57766: 3330 sc->bge_flags |= BGE_57765_PLUS; 3331 /* FALLTHROUGH */ 3332 case BGE_ASICREV_BCM5717: 3333 case BGE_ASICREV_BCM5719: 3334 case BGE_ASICREV_BCM5720: 3335 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3336 BGE_5705_PLUS; 3337 break; 3338 case BGE_ASICREV_BCM5755: 3339 case BGE_ASICREV_BCM5761: 3340 case BGE_ASICREV_BCM5784: 3341 case BGE_ASICREV_BCM5785: 3342 case BGE_ASICREV_BCM5787: 3343 case BGE_ASICREV_BCM57780: 3344 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3345 break; 3346 case BGE_ASICREV_BCM5700: 3347 case BGE_ASICREV_BCM5701: 3348 case BGE_ASICREV_BCM5703: 3349 case BGE_ASICREV_BCM5704: 3350 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3351 break; 3352 case BGE_ASICREV_BCM5714_A0: 3353 case BGE_ASICREV_BCM5780: 3354 case BGE_ASICREV_BCM5714: 3355 sc->bge_flags |= BGE_5714_FAMILY; 3356 /* FALLTHROUGH */ 3357 case BGE_ASICREV_BCM5750: 3358 case BGE_ASICREV_BCM5752: 3359 case BGE_ASICREV_BCM5906: 3360 sc->bge_flags |= BGE_575X_PLUS; 3361 /* FALLTHROUGH */ 3362 case BGE_ASICREV_BCM5705: 3363 sc->bge_flags |= BGE_5705_PLUS; 3364 break; 3365 } 3366 3367 /* Identify chips with APE processor. */ 3368 switch (BGE_ASICREV(sc->bge_chipid)) { 3369 case BGE_ASICREV_BCM5717: 3370 case BGE_ASICREV_BCM5719: 3371 case BGE_ASICREV_BCM5720: 3372 case BGE_ASICREV_BCM5761: 3373 sc->bge_flags |= BGE_APE; 3374 break; 3375 } 3376 3377 /* Chips with APE need BAR2 access for APE registers/memory. */ 3378 if ((sc->bge_flags & BGE_APE) != 0) { 3379 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3380 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3381 &sc->bge_apetag, &sc->bge_apehandle, NULL, &apesize)) { 3382 aprint_error_dev(sc->bge_dev, 3383 "couldn't map BAR2 memory\n"); 3384 return; 3385 } 3386 3387 /* Enable APE register/memory access by host driver. */ 3388 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3389 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3390 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3391 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3392 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3393 3394 bge_ape_lock_init(sc); 3395 bge_ape_read_fw_ver(sc); 3396 } 3397 3398 /* Identify the chips that use an CPMU. */ 3399 if (BGE_IS_5717_PLUS(sc) || 3400 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3401 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3402 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3403 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3404 sc->bge_flags |= BGE_CPMU_PRESENT; 3405 3406 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3407 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3408 else 3409 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3410 3411 /* 3412 * When using the BCM5701 in PCI-X mode, data corruption has 3413 * been observed in the first few bytes of some received packets. 3414 * Aligning the packet buffer in memory eliminates the corruption. 3415 * Unfortunately, this misaligns the packet payloads. On platforms 3416 * which do not support unaligned accesses, we will realign the 3417 * payloads by copying the received packets. 3418 */ 3419 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3420 sc->bge_flags & BGE_PCIX) 3421 sc->bge_flags |= BGE_RX_ALIGNBUG; 3422 3423 if (BGE_IS_5700_FAMILY(sc)) 3424 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3425 3426 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3427 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3428 3429 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3430 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3431 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3432 sc->bge_flags |= BGE_IS_5788; 3433 3434 /* 3435 * Some controllers seem to require a special firmware to use 3436 * TSO. But the firmware is not available to FreeBSD and Linux 3437 * claims that the TSO performed by the firmware is slower than 3438 * hardware based TSO. Moreover the firmware based TSO has one 3439 * known bug which can't handle TSO if ethernet header + IP/TCP 3440 * header is greater than 80 bytes. The workaround for the TSO 3441 * bug exist but it seems it's too expensive than not using 3442 * TSO at all. Some hardwares also have the TSO bug so limit 3443 * the TSO to the controllers that are not affected TSO issues 3444 * (e.g. 5755 or higher). 3445 */ 3446 if (BGE_IS_5755_PLUS(sc)) { 3447 /* 3448 * BCM5754 and BCM5787 shares the same ASIC id so 3449 * explicit device id check is required. 3450 */ 3451 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3452 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3453 sc->bge_flags |= BGE_TSO; 3454 } 3455 3456 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3457 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3458 (misccfg == 0x4000 || misccfg == 0x8000)) || 3459 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3460 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3461 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3463 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3464 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3465 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3466 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3467 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3468 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3469 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3470 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3471 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3472 capmask &= ~BMSR_EXTSTAT; 3473 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3474 } 3475 3476 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3477 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3478 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3479 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3480 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3481 3482 /* Set various PHY bug flags. */ 3483 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3484 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3485 sc->bge_flags |= BGE_PHY_CRC_BUG; 3486 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3487 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3488 sc->bge_flags |= BGE_PHY_ADC_BUG; 3489 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3490 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3491 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3493 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3494 sc->bge_flags |= BGE_PHY_NO_3LED; 3495 if (BGE_IS_5705_PLUS(sc) && 3496 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3497 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3498 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3499 !BGE_IS_5717_PLUS(sc)) { 3500 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3503 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3504 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3505 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3506 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3507 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3508 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3509 } else 3510 sc->bge_flags |= BGE_PHY_BER_BUG; 3511 } 3512 3513 /* 3514 * SEEPROM check. 3515 * First check if firmware knows we do not have SEEPROM. 3516 */ 3517 if (prop_dictionary_get_bool(device_properties(self), 3518 "without-seeprom", &no_seeprom) && no_seeprom) 3519 sc->bge_flags |= BGE_NO_EEPROM; 3520 3521 /* Now check the 'ROM failed' bit on the RX CPU */ 3522 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3523 sc->bge_flags |= BGE_NO_EEPROM; 3524 3525 sc->bge_asf_mode = 0; 3526 /* No ASF if APE present. */ 3527 if ((sc->bge_flags & BGE_APE) == 0) { 3528 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3529 BGE_SRAM_DATA_SIG_MAGIC)) { 3530 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3531 BGE_HWCFG_ASF) { 3532 sc->bge_asf_mode |= ASF_ENABLE; 3533 sc->bge_asf_mode |= ASF_STACKUP; 3534 if (BGE_IS_575X_PLUS(sc)) 3535 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3536 } 3537 } 3538 } 3539 3540 bge_stop_fw(sc); 3541 bge_sig_pre_reset(sc, BGE_RESET_START); 3542 if (bge_reset(sc)) 3543 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3544 3545 bge_sig_legacy(sc, BGE_RESET_START); 3546 bge_sig_post_reset(sc, BGE_RESET_START); 3547 3548 if (bge_chipinit(sc)) { 3549 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3550 bge_release_resources(sc); 3551 return; 3552 } 3553 3554 /* 3555 * Get station address from the EEPROM. 3556 */ 3557 if (bge_get_eaddr(sc, eaddr)) { 3558 aprint_error_dev(sc->bge_dev, 3559 "failed to read station address\n"); 3560 bge_release_resources(sc); 3561 return; 3562 } 3563 3564 br = bge_lookup_rev(sc->bge_chipid); 3565 3566 if (br == NULL) { 3567 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3568 sc->bge_chipid); 3569 } else { 3570 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3571 br->br_name, sc->bge_chipid); 3572 } 3573 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3574 3575 /* Allocate the general information block and ring buffers. */ 3576 if (pci_dma64_available(pa)) 3577 sc->bge_dmatag = pa->pa_dmat64; 3578 else 3579 sc->bge_dmatag = pa->pa_dmat; 3580 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3581 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3582 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 3583 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3584 return; 3585 } 3586 DPRINTFN(5, ("bus_dmamem_map\n")); 3587 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 3588 sizeof(struct bge_ring_data), &kva, 3589 BUS_DMA_NOWAIT)) { 3590 aprint_error_dev(sc->bge_dev, 3591 "can't map DMA buffers (%zu bytes)\n", 3592 sizeof(struct bge_ring_data)); 3593 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3594 return; 3595 } 3596 DPRINTFN(5, ("bus_dmamem_create\n")); 3597 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3598 sizeof(struct bge_ring_data), 0, 3599 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3600 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3601 bus_dmamem_unmap(sc->bge_dmatag, kva, 3602 sizeof(struct bge_ring_data)); 3603 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3604 return; 3605 } 3606 DPRINTFN(5, ("bus_dmamem_load\n")); 3607 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3608 sizeof(struct bge_ring_data), NULL, 3609 BUS_DMA_NOWAIT)) { 3610 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3611 bus_dmamem_unmap(sc->bge_dmatag, kva, 3612 sizeof(struct bge_ring_data)); 3613 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 3614 return; 3615 } 3616 3617 DPRINTFN(5, ("bzero\n")); 3618 sc->bge_rdata = (struct bge_ring_data *)kva; 3619 3620 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3621 3622 /* Try to allocate memory for jumbo buffers. */ 3623 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3624 if (bge_alloc_jumbo_mem(sc)) { 3625 aprint_error_dev(sc->bge_dev, 3626 "jumbo buffer allocation failed\n"); 3627 } else 3628 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3629 } 3630 3631 /* Set default tuneable values. */ 3632 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3633 sc->bge_rx_coal_ticks = 150; 3634 sc->bge_rx_max_coal_bds = 64; 3635 sc->bge_tx_coal_ticks = 300; 3636 sc->bge_tx_max_coal_bds = 400; 3637 if (BGE_IS_5705_PLUS(sc)) { 3638 sc->bge_tx_coal_ticks = (12 * 5); 3639 sc->bge_tx_max_coal_bds = (12 * 5); 3640 aprint_verbose_dev(sc->bge_dev, 3641 "setting short Tx thresholds\n"); 3642 } 3643 3644 if (BGE_IS_5717_PLUS(sc)) 3645 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3646 else if (BGE_IS_5705_PLUS(sc)) 3647 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3648 else 3649 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3650 3651 /* Set up ifnet structure */ 3652 ifp = &sc->ethercom.ec_if; 3653 ifp->if_softc = sc; 3654 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3655 ifp->if_ioctl = bge_ioctl; 3656 ifp->if_stop = bge_stop; 3657 ifp->if_start = bge_start; 3658 ifp->if_init = bge_init; 3659 ifp->if_watchdog = bge_watchdog; 3660 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3661 IFQ_SET_READY(&ifp->if_snd); 3662 DPRINTFN(5, ("strcpy if_xname\n")); 3663 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3664 3665 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3666 sc->ethercom.ec_if.if_capabilities |= 3667 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3668 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3669 sc->ethercom.ec_if.if_capabilities |= 3670 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3671 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3672 #endif 3673 sc->ethercom.ec_capabilities |= 3674 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3675 3676 if (sc->bge_flags & BGE_TSO) 3677 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3678 3679 /* 3680 * Do MII setup. 3681 */ 3682 DPRINTFN(5, ("mii setup\n")); 3683 sc->bge_mii.mii_ifp = ifp; 3684 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3685 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3686 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3687 3688 /* 3689 * Figure out what sort of media we have by checking the hardware 3690 * config word in the first 32k of NIC internal memory, or fall back to 3691 * the config word in the EEPROM. Note: on some BCM5700 cards, 3692 * this value appears to be unset. If that's the case, we have to rely 3693 * on identifying the NIC by its PCI subsystem ID, as we do below for 3694 * the SysKonnect SK-9D41. 3695 */ 3696 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3697 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3698 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3699 bge_read_eeprom(sc, (void *)&hwcfg, 3700 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3701 hwcfg = be32toh(hwcfg); 3702 } 3703 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3704 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3705 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3706 if (BGE_IS_5714_FAMILY(sc)) 3707 sc->bge_flags |= BGE_PHY_FIBER_MII; 3708 else 3709 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3710 } 3711 3712 /* set phyflags and chipid before mii_attach() */ 3713 dict = device_properties(self); 3714 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3715 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3716 3717 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3718 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3719 bge_ifmedia_sts); 3720 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3721 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3722 0, NULL); 3723 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3724 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3725 /* Pretend the user requested this setting */ 3726 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3727 } else { 3728 /* 3729 * Do transceiver setup and tell the firmware the 3730 * driver is down so we can try to get access the 3731 * probe if ASF is running. Retry a couple of times 3732 * if we get a conflict with the ASF firmware accessing 3733 * the PHY. 3734 */ 3735 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3736 bge_asf_driver_up(sc); 3737 3738 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3739 bge_ifmedia_sts); 3740 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3741 sc->bge_phy_addr, MII_OFFSET_ANY, 3742 MIIF_DOPAUSE); 3743 3744 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3745 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3746 ifmedia_add(&sc->bge_mii.mii_media, 3747 IFM_ETHER|IFM_MANUAL, 0, NULL); 3748 ifmedia_set(&sc->bge_mii.mii_media, 3749 IFM_ETHER|IFM_MANUAL); 3750 } else 3751 ifmedia_set(&sc->bge_mii.mii_media, 3752 IFM_ETHER|IFM_AUTO); 3753 3754 /* 3755 * Now tell the firmware we are going up after probing the PHY 3756 */ 3757 if (sc->bge_asf_mode & ASF_STACKUP) 3758 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3759 } 3760 3761 /* 3762 * Call MI attach routine. 3763 */ 3764 DPRINTFN(5, ("if_attach\n")); 3765 if_attach(ifp); 3766 DPRINTFN(5, ("ether_ifattach\n")); 3767 ether_ifattach(ifp, eaddr); 3768 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3769 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3770 RND_TYPE_NET, 0); 3771 #ifdef BGE_EVENT_COUNTERS 3772 /* 3773 * Attach event counters. 3774 */ 3775 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3776 NULL, device_xname(sc->bge_dev), "intr"); 3777 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3778 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3779 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3780 NULL, device_xname(sc->bge_dev), "tx_xon"); 3781 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3782 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3783 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3784 NULL, device_xname(sc->bge_dev), "rx_xon"); 3785 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3786 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3787 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3788 NULL, device_xname(sc->bge_dev), "xoffentered"); 3789 #endif /* BGE_EVENT_COUNTERS */ 3790 DPRINTFN(5, ("callout_init\n")); 3791 callout_init(&sc->bge_timeout, 0); 3792 3793 if (pmf_device_register(self, NULL, NULL)) 3794 pmf_class_network_register(self, ifp); 3795 else 3796 aprint_error_dev(self, "couldn't establish power handler\n"); 3797 3798 bge_sysctl_init(sc); 3799 3800 #ifdef BGE_DEBUG 3801 bge_debug_info(sc); 3802 #endif 3803 } 3804 3805 static void 3806 bge_release_resources(struct bge_softc *sc) 3807 { 3808 if (sc->bge_vpd_prodname != NULL) 3809 free(sc->bge_vpd_prodname, M_DEVBUF); 3810 3811 if (sc->bge_vpd_readonly != NULL) 3812 free(sc->bge_vpd_readonly, M_DEVBUF); 3813 } 3814 3815 static int 3816 bge_reset(struct bge_softc *sc) 3817 { 3818 uint32_t cachesize, command; 3819 uint32_t reset, mac_mode, mac_mode_mask; 3820 pcireg_t devctl, reg; 3821 int i, val; 3822 void (*write_op)(struct bge_softc *, int, int); 3823 3824 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3825 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3826 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3827 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3828 3829 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3830 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3831 if (sc->bge_flags & BGE_PCIE) 3832 write_op = bge_writemem_direct; 3833 else 3834 write_op = bge_writemem_ind; 3835 } else 3836 write_op = bge_writereg_ind; 3837 3838 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3839 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3840 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3841 for (i = 0; i < 8000; i++) { 3842 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3843 BGE_NVRAMSWARB_GNT1) 3844 break; 3845 DELAY(20); 3846 } 3847 if (i == 8000) { 3848 printf("%s: NVRAM lock timedout!\n", 3849 device_xname(sc->bge_dev)); 3850 } 3851 } 3852 /* Take APE lock when performing reset. */ 3853 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3854 3855 /* Save some important PCI state. */ 3856 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3857 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3858 3859 /* Step 5b-5d: */ 3860 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3861 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3862 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3863 3864 /* XXX ???: Disable fastboot on controllers that support it. */ 3865 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3866 BGE_IS_5755_PLUS(sc)) 3867 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3868 3869 /* 3870 * Step 6: Write the magic number to SRAM at offset 0xB50. 3871 * When firmware finishes its initialization it will 3872 * write ~BGE_MAGIC_NUMBER to the same location. 3873 */ 3874 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3875 3876 /* Step 7: */ 3877 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3878 /* 3879 * XXX: from FreeBSD/Linux; no documentation 3880 */ 3881 if (sc->bge_flags & BGE_PCIE) { 3882 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3883 !BGE_IS_57765_PLUS(sc) && 3884 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3885 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3886 /* PCI Express 1.0 system */ 3887 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3888 BGE_PHY_PCIE_SCRAM_MODE); 3889 } 3890 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3891 /* 3892 * Prevent PCI Express link training 3893 * during global reset. 3894 */ 3895 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3896 reset |= (1 << 29); 3897 } 3898 } 3899 3900 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3901 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3902 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3903 i | BGE_VCPU_STATUS_DRV_RESET); 3904 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3905 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3906 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3907 } 3908 3909 /* 3910 * Set GPHY Power Down Override to leave GPHY 3911 * powered up in D0 uninitialized. 3912 */ 3913 if (BGE_IS_5705_PLUS(sc) && 3914 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3915 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3916 3917 /* Issue global reset */ 3918 write_op(sc, BGE_MISC_CFG, reset); 3919 3920 /* Step 8: wait for complete */ 3921 if (sc->bge_flags & BGE_PCIE) 3922 delay(100*1000); /* too big */ 3923 else 3924 delay(1000); 3925 3926 if (sc->bge_flags & BGE_PCIE) { 3927 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3928 DELAY(500000); 3929 /* XXX: Magic Numbers */ 3930 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3931 BGE_PCI_UNKNOWN0); 3932 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3933 BGE_PCI_UNKNOWN0, 3934 reg | (1 << 15)); 3935 } 3936 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3937 sc->bge_pciecap + PCI_PCIE_DCSR); 3938 /* Clear enable no snoop and disable relaxed ordering. */ 3939 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3940 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3941 3942 /* Set PCIE max payload size to 128 for older PCIe devices */ 3943 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3944 devctl &= ~(0x00e0); 3945 /* Clear device status register. Write 1b to clear */ 3946 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3947 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3948 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3949 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3950 bge_set_max_readrq(sc); 3951 } 3952 3953 /* From Linux: dummy read to flush PCI posted writes */ 3954 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3955 3956 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3957 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3958 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3959 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3960 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 3961 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 3962 (sc->bge_flags & BGE_PCIX) != 0) 3963 val |= BGE_PCISTATE_RETRY_SAME_DMA; 3964 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3965 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3966 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3967 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3968 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 3969 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3970 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3971 3972 /* Step 11: disable PCI-X Relaxed Ordering. */ 3973 if (sc->bge_flags & BGE_PCIX) { 3974 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3975 + PCI_PCIX_CMD); 3976 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3977 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3978 } 3979 3980 /* Step 12: Enable memory arbiter. */ 3981 if (BGE_IS_5714_FAMILY(sc)) { 3982 val = CSR_READ_4(sc, BGE_MARB_MODE); 3983 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3984 } else 3985 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3986 3987 /* XXX 5721, 5751 and 5752 */ 3988 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3989 /* Step 19: */ 3990 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3991 /* Step 20: */ 3992 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3993 } 3994 3995 /* Step 28: Fix up byte swapping */ 3996 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3997 3998 /* 3999 * Wait for the bootcode to complete initialization. 4000 * See BCM5718 programmer's guide's "step 13, Device reset Procedure, 4001 * Section 7". 4002 */ 4003 if (BGE_IS_5717_PLUS(sc)) { 4004 for (i = 0; i < 1000*1000; i++) { 4005 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4006 if (val == BGE_SRAM_FW_MB_RESET_MAGIC) 4007 break; 4008 DELAY(10); 4009 } 4010 } 4011 4012 /* Step 21: 5822 B0 errata */ 4013 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4014 pcireg_t msidata; 4015 4016 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4017 BGE_PCI_MSI_DATA); 4018 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4019 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4020 msidata); 4021 } 4022 4023 /* 4024 * Step 18: wirte mac mode 4025 * XXX Write 0x0c for 5703S and 5704S 4026 */ 4027 val = CSR_READ_4(sc, BGE_MAC_MODE); 4028 val = (val & ~mac_mode_mask) | mac_mode; 4029 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4030 DELAY(40); 4031 4032 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4033 4034 /* Step 17: Poll until the firmware initialization is complete */ 4035 bge_poll_fw(sc); 4036 4037 /* 4038 * The 5704 in TBI mode apparently needs some special 4039 * adjustment to insure the SERDES drive level is set 4040 * to 1.2V. 4041 */ 4042 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4043 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4044 uint32_t serdescfg; 4045 4046 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4047 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4048 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4049 } 4050 4051 if (sc->bge_flags & BGE_PCIE && 4052 !BGE_IS_57765_PLUS(sc) && 4053 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4054 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4055 uint32_t v; 4056 4057 /* Enable PCI Express bug fix */ 4058 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4059 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4060 v | BGE_TLP_DATA_FIFO_PROTECT); 4061 } 4062 4063 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4064 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4065 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4066 4067 return 0; 4068 } 4069 4070 /* 4071 * Frame reception handling. This is called if there's a frame 4072 * on the receive return list. 4073 * 4074 * Note: we have to be able to handle two possibilities here: 4075 * 1) the frame is from the jumbo receive ring 4076 * 2) the frame is from the standard receive ring 4077 */ 4078 4079 static void 4080 bge_rxeof(struct bge_softc *sc) 4081 { 4082 struct ifnet *ifp; 4083 uint16_t rx_prod, rx_cons; 4084 int stdcnt = 0, jumbocnt = 0; 4085 bus_dmamap_t dmamap; 4086 bus_addr_t offset, toff; 4087 bus_size_t tlen; 4088 int tosync; 4089 4090 rx_cons = sc->bge_rx_saved_considx; 4091 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4092 4093 /* Nothing to do */ 4094 if (rx_cons == rx_prod) 4095 return; 4096 4097 ifp = &sc->ethercom.ec_if; 4098 4099 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4100 offsetof(struct bge_ring_data, bge_status_block), 4101 sizeof (struct bge_status_block), 4102 BUS_DMASYNC_POSTREAD); 4103 4104 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4105 tosync = rx_prod - rx_cons; 4106 4107 if (tosync != 0) 4108 rnd_add_uint32(&sc->rnd_source, tosync); 4109 4110 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4111 4112 if (tosync < 0) { 4113 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4114 sizeof (struct bge_rx_bd); 4115 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4116 toff, tlen, BUS_DMASYNC_POSTREAD); 4117 tosync = -tosync; 4118 } 4119 4120 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4121 offset, tosync * sizeof (struct bge_rx_bd), 4122 BUS_DMASYNC_POSTREAD); 4123 4124 while (rx_cons != rx_prod) { 4125 struct bge_rx_bd *cur_rx; 4126 uint32_t rxidx; 4127 struct mbuf *m = NULL; 4128 4129 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4130 4131 rxidx = cur_rx->bge_idx; 4132 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4133 4134 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4135 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4136 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4137 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4138 jumbocnt++; 4139 bus_dmamap_sync(sc->bge_dmatag, 4140 sc->bge_cdata.bge_rx_jumbo_map, 4141 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4142 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4143 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4144 ifp->if_ierrors++; 4145 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4146 continue; 4147 } 4148 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4149 NULL)== ENOBUFS) { 4150 ifp->if_ierrors++; 4151 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4152 continue; 4153 } 4154 } else { 4155 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4156 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4157 4158 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4159 stdcnt++; 4160 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4161 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4162 if (dmamap == NULL) { 4163 ifp->if_ierrors++; 4164 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4165 continue; 4166 } 4167 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4168 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4169 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4170 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4171 ifp->if_ierrors++; 4172 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4173 continue; 4174 } 4175 if (bge_newbuf_std(sc, sc->bge_std, 4176 NULL, dmamap) == ENOBUFS) { 4177 ifp->if_ierrors++; 4178 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4179 continue; 4180 } 4181 } 4182 4183 ifp->if_ipackets++; 4184 #ifndef __NO_STRICT_ALIGNMENT 4185 /* 4186 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4187 * the Rx buffer has the layer-2 header unaligned. 4188 * If our CPU requires alignment, re-align by copying. 4189 */ 4190 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4191 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4192 cur_rx->bge_len); 4193 m->m_data += ETHER_ALIGN; 4194 } 4195 #endif 4196 4197 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4198 m->m_pkthdr.rcvif = ifp; 4199 4200 /* 4201 * Handle BPF listeners. Let the BPF user see the packet. 4202 */ 4203 bpf_mtap(ifp, m); 4204 4205 bge_rxcsum(sc, cur_rx, m); 4206 4207 /* 4208 * If we received a packet with a vlan tag, pass it 4209 * to vlan_input() instead of ether_input(). 4210 */ 4211 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4212 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4213 } 4214 4215 (*ifp->if_input)(ifp, m); 4216 } 4217 4218 sc->bge_rx_saved_considx = rx_cons; 4219 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4220 if (stdcnt) 4221 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4222 if (jumbocnt) 4223 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4224 } 4225 4226 static void 4227 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4228 { 4229 4230 if (BGE_IS_5717_PLUS(sc)) { 4231 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4232 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4233 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4234 if ((cur_rx->bge_error_flag & 4235 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4236 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4237 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4238 m->m_pkthdr.csum_data = 4239 cur_rx->bge_tcp_udp_csum; 4240 m->m_pkthdr.csum_flags |= 4241 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4242 M_CSUM_DATA); 4243 } 4244 } 4245 } else { 4246 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4247 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4248 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4249 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4250 /* 4251 * Rx transport checksum-offload may also 4252 * have bugs with packets which, when transmitted, 4253 * were `runts' requiring padding. 4254 */ 4255 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4256 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4257 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4258 m->m_pkthdr.csum_data = 4259 cur_rx->bge_tcp_udp_csum; 4260 m->m_pkthdr.csum_flags |= 4261 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4262 M_CSUM_DATA); 4263 } 4264 } 4265 } 4266 4267 static void 4268 bge_txeof(struct bge_softc *sc) 4269 { 4270 struct bge_tx_bd *cur_tx = NULL; 4271 struct ifnet *ifp; 4272 struct txdmamap_pool_entry *dma; 4273 bus_addr_t offset, toff; 4274 bus_size_t tlen; 4275 int tosync; 4276 struct mbuf *m; 4277 4278 ifp = &sc->ethercom.ec_if; 4279 4280 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4281 offsetof(struct bge_ring_data, bge_status_block), 4282 sizeof (struct bge_status_block), 4283 BUS_DMASYNC_POSTREAD); 4284 4285 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4286 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4287 sc->bge_tx_saved_considx; 4288 4289 if (tosync != 0) 4290 rnd_add_uint32(&sc->rnd_source, tosync); 4291 4292 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4293 4294 if (tosync < 0) { 4295 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4296 sizeof (struct bge_tx_bd); 4297 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4298 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4299 tosync = -tosync; 4300 } 4301 4302 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4303 offset, tosync * sizeof (struct bge_tx_bd), 4304 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4305 4306 /* 4307 * Go through our tx ring and free mbufs for those 4308 * frames that have been sent. 4309 */ 4310 while (sc->bge_tx_saved_considx != 4311 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4312 uint32_t idx = 0; 4313 4314 idx = sc->bge_tx_saved_considx; 4315 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4316 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4317 ifp->if_opackets++; 4318 m = sc->bge_cdata.bge_tx_chain[idx]; 4319 if (m != NULL) { 4320 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4321 dma = sc->txdma[idx]; 4322 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4323 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4324 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4325 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4326 sc->txdma[idx] = NULL; 4327 4328 m_freem(m); 4329 } 4330 sc->bge_txcnt--; 4331 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4332 ifp->if_timer = 0; 4333 } 4334 4335 if (cur_tx != NULL) 4336 ifp->if_flags &= ~IFF_OACTIVE; 4337 } 4338 4339 static int 4340 bge_intr(void *xsc) 4341 { 4342 struct bge_softc *sc; 4343 struct ifnet *ifp; 4344 uint32_t statusword; 4345 4346 sc = xsc; 4347 ifp = &sc->ethercom.ec_if; 4348 4349 /* It is possible for the interrupt to arrive before 4350 * the status block is updated prior to the interrupt. 4351 * Reading the PCI State register will confirm whether the 4352 * interrupt is ours and will flush the status block. 4353 */ 4354 4355 /* read status word from status block */ 4356 statusword = sc->bge_rdata->bge_status_block.bge_status; 4357 4358 if ((statusword & BGE_STATFLAG_UPDATED) || 4359 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4360 /* Ack interrupt and stop others from occuring. */ 4361 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4362 4363 BGE_EVCNT_INCR(sc->bge_ev_intr); 4364 4365 /* clear status word */ 4366 sc->bge_rdata->bge_status_block.bge_status = 0; 4367 4368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4369 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4370 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4371 bge_link_upd(sc); 4372 4373 if (ifp->if_flags & IFF_RUNNING) { 4374 /* Check RX return ring producer/consumer */ 4375 bge_rxeof(sc); 4376 4377 /* Check TX ring producer/consumer */ 4378 bge_txeof(sc); 4379 } 4380 4381 if (sc->bge_pending_rxintr_change) { 4382 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4383 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4384 uint32_t junk; 4385 4386 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4387 DELAY(10); 4388 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4389 4390 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4391 DELAY(10); 4392 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4393 4394 sc->bge_pending_rxintr_change = 0; 4395 } 4396 bge_handle_events(sc); 4397 4398 /* Re-enable interrupts. */ 4399 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4400 4401 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4402 bge_start(ifp); 4403 4404 return 1; 4405 } else 4406 return 0; 4407 } 4408 4409 static void 4410 bge_asf_driver_up(struct bge_softc *sc) 4411 { 4412 if (sc->bge_asf_mode & ASF_STACKUP) { 4413 /* Send ASF heartbeat aprox. every 2s */ 4414 if (sc->bge_asf_count) 4415 sc->bge_asf_count --; 4416 else { 4417 sc->bge_asf_count = 2; 4418 4419 bge_wait_for_event_ack(sc); 4420 4421 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4422 BGE_FW_CMD_DRV_ALIVE); 4423 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4424 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4425 BGE_FW_HB_TIMEOUT_SEC); 4426 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4427 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4428 BGE_RX_CPU_DRV_EVENT); 4429 } 4430 } 4431 } 4432 4433 static void 4434 bge_tick(void *xsc) 4435 { 4436 struct bge_softc *sc = xsc; 4437 struct mii_data *mii = &sc->bge_mii; 4438 int s; 4439 4440 s = splnet(); 4441 4442 if (BGE_IS_5705_PLUS(sc)) 4443 bge_stats_update_regs(sc); 4444 else 4445 bge_stats_update(sc); 4446 4447 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4448 /* 4449 * Since in TBI mode auto-polling can't be used we should poll 4450 * link status manually. Here we register pending link event 4451 * and trigger interrupt. 4452 */ 4453 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4454 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4455 } else { 4456 /* 4457 * Do not touch PHY if we have link up. This could break 4458 * IPMI/ASF mode or produce extra input errors. 4459 * (extra input errors was reported for bcm5701 & bcm5704). 4460 */ 4461 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4462 mii_tick(mii); 4463 } 4464 4465 bge_asf_driver_up(sc); 4466 4467 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4468 4469 splx(s); 4470 } 4471 4472 static void 4473 bge_stats_update_regs(struct bge_softc *sc) 4474 { 4475 struct ifnet *ifp = &sc->ethercom.ec_if; 4476 4477 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4478 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4479 4480 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4481 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4482 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4483 } 4484 4485 static void 4486 bge_stats_update(struct bge_softc *sc) 4487 { 4488 struct ifnet *ifp = &sc->ethercom.ec_if; 4489 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4490 4491 #define READ_STAT(sc, stats, stat) \ 4492 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4493 4494 ifp->if_collisions += 4495 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4496 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4497 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4498 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4499 ifp->if_collisions; 4500 4501 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4502 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4503 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4504 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4505 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4506 READ_STAT(sc, stats, 4507 xoffPauseFramesReceived.bge_addr_lo)); 4508 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4509 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4510 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4511 READ_STAT(sc, stats, 4512 macControlFramesReceived.bge_addr_lo)); 4513 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4514 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4515 4516 #undef READ_STAT 4517 4518 #ifdef notdef 4519 ifp->if_collisions += 4520 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4521 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4522 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4523 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4524 ifp->if_collisions; 4525 #endif 4526 } 4527 4528 /* 4529 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4530 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4531 * but when such padded frames employ the bge IP/TCP checksum offload, 4532 * the hardware checksum assist gives incorrect results (possibly 4533 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4534 * If we pad such runts with zeros, the onboard checksum comes out correct. 4535 */ 4536 static inline int 4537 bge_cksum_pad(struct mbuf *pkt) 4538 { 4539 struct mbuf *last = NULL; 4540 int padlen; 4541 4542 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4543 4544 /* if there's only the packet-header and we can pad there, use it. */ 4545 if (pkt->m_pkthdr.len == pkt->m_len && 4546 M_TRAILINGSPACE(pkt) >= padlen) { 4547 last = pkt; 4548 } else { 4549 /* 4550 * Walk packet chain to find last mbuf. We will either 4551 * pad there, or append a new mbuf and pad it 4552 * (thus perhaps avoiding the bcm5700 dma-min bug). 4553 */ 4554 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4555 continue; /* do nothing */ 4556 } 4557 4558 /* `last' now points to last in chain. */ 4559 if (M_TRAILINGSPACE(last) < padlen) { 4560 /* Allocate new empty mbuf, pad it. Compact later. */ 4561 struct mbuf *n; 4562 MGET(n, M_DONTWAIT, MT_DATA); 4563 if (n == NULL) 4564 return ENOBUFS; 4565 n->m_len = 0; 4566 last->m_next = n; 4567 last = n; 4568 } 4569 } 4570 4571 KDASSERT(!M_READONLY(last)); 4572 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4573 4574 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4575 memset(mtod(last, char *) + last->m_len, 0, padlen); 4576 last->m_len += padlen; 4577 pkt->m_pkthdr.len += padlen; 4578 return 0; 4579 } 4580 4581 /* 4582 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4583 */ 4584 static inline int 4585 bge_compact_dma_runt(struct mbuf *pkt) 4586 { 4587 struct mbuf *m, *prev; 4588 int totlen, prevlen; 4589 4590 prev = NULL; 4591 totlen = 0; 4592 prevlen = -1; 4593 4594 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4595 int mlen = m->m_len; 4596 int shortfall = 8 - mlen ; 4597 4598 totlen += mlen; 4599 if (mlen == 0) 4600 continue; 4601 if (mlen >= 8) 4602 continue; 4603 4604 /* If we get here, mbuf data is too small for DMA engine. 4605 * Try to fix by shuffling data to prev or next in chain. 4606 * If that fails, do a compacting deep-copy of the whole chain. 4607 */ 4608 4609 /* Internal frag. If fits in prev, copy it there. */ 4610 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4611 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4612 prev->m_len += mlen; 4613 m->m_len = 0; 4614 /* XXX stitch chain */ 4615 prev->m_next = m_free(m); 4616 m = prev; 4617 continue; 4618 } 4619 else if (m->m_next != NULL && 4620 M_TRAILINGSPACE(m) >= shortfall && 4621 m->m_next->m_len >= (8 + shortfall)) { 4622 /* m is writable and have enough data in next, pull up. */ 4623 4624 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4625 shortfall); 4626 m->m_len += shortfall; 4627 m->m_next->m_len -= shortfall; 4628 m->m_next->m_data += shortfall; 4629 } 4630 else if (m->m_next == NULL || 1) { 4631 /* Got a runt at the very end of the packet. 4632 * borrow data from the tail of the preceding mbuf and 4633 * update its length in-place. (The original data is still 4634 * valid, so we can do this even if prev is not writable.) 4635 */ 4636 4637 /* if we'd make prev a runt, just move all of its data. */ 4638 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4639 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4640 4641 if ((prev->m_len - shortfall) < 8) 4642 shortfall = prev->m_len; 4643 4644 #ifdef notyet /* just do the safe slow thing for now */ 4645 if (!M_READONLY(m)) { 4646 if (M_LEADINGSPACE(m) < shorfall) { 4647 void *m_dat; 4648 m_dat = (m->m_flags & M_PKTHDR) ? 4649 m->m_pktdat : m->dat; 4650 memmove(m_dat, mtod(m, void*), m->m_len); 4651 m->m_data = m_dat; 4652 } 4653 } else 4654 #endif /* just do the safe slow thing */ 4655 { 4656 struct mbuf * n = NULL; 4657 int newprevlen = prev->m_len - shortfall; 4658 4659 MGET(n, M_NOWAIT, MT_DATA); 4660 if (n == NULL) 4661 return ENOBUFS; 4662 KASSERT(m->m_len + shortfall < MLEN 4663 /*, 4664 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4665 4666 /* first copy the data we're stealing from prev */ 4667 memcpy(n->m_data, prev->m_data + newprevlen, 4668 shortfall); 4669 4670 /* update prev->m_len accordingly */ 4671 prev->m_len -= shortfall; 4672 4673 /* copy data from runt m */ 4674 memcpy(n->m_data + shortfall, m->m_data, 4675 m->m_len); 4676 4677 /* n holds what we stole from prev, plus m */ 4678 n->m_len = shortfall + m->m_len; 4679 4680 /* stitch n into chain and free m */ 4681 n->m_next = m->m_next; 4682 prev->m_next = n; 4683 /* KASSERT(m->m_next == NULL); */ 4684 m->m_next = NULL; 4685 m_free(m); 4686 m = n; /* for continuing loop */ 4687 } 4688 } 4689 prevlen = m->m_len; 4690 } 4691 return 0; 4692 } 4693 4694 /* 4695 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4696 * pointers to descriptors. 4697 */ 4698 static int 4699 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4700 { 4701 struct bge_tx_bd *f = NULL; 4702 uint32_t frag, cur; 4703 uint16_t csum_flags = 0; 4704 uint16_t txbd_tso_flags = 0; 4705 struct txdmamap_pool_entry *dma; 4706 bus_dmamap_t dmamap; 4707 int i = 0; 4708 struct m_tag *mtag; 4709 int use_tso, maxsegsize, error; 4710 4711 cur = frag = *txidx; 4712 4713 if (m_head->m_pkthdr.csum_flags) { 4714 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4715 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4716 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4717 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4718 } 4719 4720 /* 4721 * If we were asked to do an outboard checksum, and the NIC 4722 * has the bug where it sometimes adds in the Ethernet padding, 4723 * explicitly pad with zeros so the cksum will be correct either way. 4724 * (For now, do this for all chip versions, until newer 4725 * are confirmed to not require the workaround.) 4726 */ 4727 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4728 #ifdef notyet 4729 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4730 #endif 4731 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4732 goto check_dma_bug; 4733 4734 if (bge_cksum_pad(m_head) != 0) 4735 return ENOBUFS; 4736 4737 check_dma_bug: 4738 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4739 goto doit; 4740 4741 /* 4742 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4743 * less than eight bytes. If we encounter a teeny mbuf 4744 * at the end of a chain, we can pad. Otherwise, copy. 4745 */ 4746 if (bge_compact_dma_runt(m_head) != 0) 4747 return ENOBUFS; 4748 4749 doit: 4750 dma = SLIST_FIRST(&sc->txdma_list); 4751 if (dma == NULL) 4752 return ENOBUFS; 4753 dmamap = dma->dmamap; 4754 4755 /* 4756 * Set up any necessary TSO state before we start packing... 4757 */ 4758 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4759 if (!use_tso) { 4760 maxsegsize = 0; 4761 } else { /* TSO setup */ 4762 unsigned mss; 4763 struct ether_header *eh; 4764 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4765 struct mbuf * m0 = m_head; 4766 struct ip *ip; 4767 struct tcphdr *th; 4768 int iphl, hlen; 4769 4770 /* 4771 * XXX It would be nice if the mbuf pkthdr had offset 4772 * fields for the protocol headers. 4773 */ 4774 4775 eh = mtod(m0, struct ether_header *); 4776 switch (htons(eh->ether_type)) { 4777 case ETHERTYPE_IP: 4778 offset = ETHER_HDR_LEN; 4779 break; 4780 4781 case ETHERTYPE_VLAN: 4782 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4783 break; 4784 4785 default: 4786 /* 4787 * Don't support this protocol or encapsulation. 4788 */ 4789 return ENOBUFS; 4790 } 4791 4792 /* 4793 * TCP/IP headers are in the first mbuf; we can do 4794 * this the easy way. 4795 */ 4796 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4797 hlen = iphl + offset; 4798 if (__predict_false(m0->m_len < 4799 (hlen + sizeof(struct tcphdr)))) { 4800 4801 aprint_debug_dev(sc->bge_dev, 4802 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4803 "not handled yet\n", 4804 m0->m_len, hlen+ sizeof(struct tcphdr)); 4805 #ifdef NOTYET 4806 /* 4807 * XXX jonathan (at) NetBSD.org: untested. 4808 * how to force this branch to be taken? 4809 */ 4810 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4811 4812 m_copydata(m0, offset, sizeof(ip), &ip); 4813 m_copydata(m0, hlen, sizeof(th), &th); 4814 4815 ip.ip_len = 0; 4816 4817 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4818 sizeof(ip.ip_len), &ip.ip_len); 4819 4820 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4821 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4822 4823 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4824 sizeof(th.th_sum), &th.th_sum); 4825 4826 hlen += th.th_off << 2; 4827 iptcp_opt_words = hlen; 4828 #else 4829 /* 4830 * if_wm "hard" case not yet supported, can we not 4831 * mandate it out of existence? 4832 */ 4833 (void) ip; (void)th; (void) ip_tcp_hlen; 4834 4835 return ENOBUFS; 4836 #endif 4837 } else { 4838 ip = (struct ip *) (mtod(m0, char *) + offset); 4839 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4840 ip_tcp_hlen = iphl + (th->th_off << 2); 4841 4842 /* Total IP/TCP options, in 32-bit words */ 4843 iptcp_opt_words = (ip_tcp_hlen 4844 - sizeof(struct tcphdr) 4845 - sizeof(struct ip)) >> 2; 4846 } 4847 if (BGE_IS_575X_PLUS(sc)) { 4848 th->th_sum = 0; 4849 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4850 } else { 4851 /* 4852 * XXX jonathan (at) NetBSD.org: 5705 untested. 4853 * Requires TSO firmware patch for 5701/5703/5704. 4854 */ 4855 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4856 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4857 } 4858 4859 mss = m_head->m_pkthdr.segsz; 4860 txbd_tso_flags |= 4861 BGE_TXBDFLAG_CPU_PRE_DMA | 4862 BGE_TXBDFLAG_CPU_POST_DMA; 4863 4864 /* 4865 * Our NIC TSO-assist assumes TSO has standard, optionless 4866 * IPv4 and TCP headers, which total 40 bytes. By default, 4867 * the NIC copies 40 bytes of IP/TCP header from the 4868 * supplied header into the IP/TCP header portion of 4869 * each post-TSO-segment. If the supplied packet has IP or 4870 * TCP options, we need to tell the NIC to copy those extra 4871 * bytes into each post-TSO header, in addition to the normal 4872 * 40-byte IP/TCP header (and to leave space accordingly). 4873 * Unfortunately, the driver encoding of option length 4874 * varies across different ASIC families. 4875 */ 4876 tcp_seg_flags = 0; 4877 if (iptcp_opt_words) { 4878 if (BGE_IS_5705_PLUS(sc)) { 4879 tcp_seg_flags = 4880 iptcp_opt_words << 11; 4881 } else { 4882 txbd_tso_flags |= 4883 iptcp_opt_words << 12; 4884 } 4885 } 4886 maxsegsize = mss | tcp_seg_flags; 4887 ip->ip_len = htons(mss + ip_tcp_hlen); 4888 4889 } /* TSO setup */ 4890 4891 /* 4892 * Start packing the mbufs in this chain into 4893 * the fragment pointers. Stop when we run out 4894 * of fragments or hit the end of the mbuf chain. 4895 */ 4896 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4897 BUS_DMA_NOWAIT); 4898 if (error) 4899 return ENOBUFS; 4900 /* 4901 * Sanity check: avoid coming within 16 descriptors 4902 * of the end of the ring. 4903 */ 4904 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4905 BGE_TSO_PRINTF(("%s: " 4906 " dmamap_load_mbuf too close to ring wrap\n", 4907 device_xname(sc->bge_dev))); 4908 goto fail_unload; 4909 } 4910 4911 mtag = sc->ethercom.ec_nvlans ? 4912 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4913 4914 4915 /* Iterate over dmap-map fragments. */ 4916 for (i = 0; i < dmamap->dm_nsegs; i++) { 4917 f = &sc->bge_rdata->bge_tx_ring[frag]; 4918 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4919 break; 4920 4921 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4922 f->bge_len = dmamap->dm_segs[i].ds_len; 4923 4924 /* 4925 * For 5751 and follow-ons, for TSO we must turn 4926 * off checksum-assist flag in the tx-descr, and 4927 * supply the ASIC-revision-specific encoding 4928 * of TSO flags and segsize. 4929 */ 4930 if (use_tso) { 4931 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4932 f->bge_rsvd = maxsegsize; 4933 f->bge_flags = csum_flags | txbd_tso_flags; 4934 } else { 4935 f->bge_rsvd = 0; 4936 f->bge_flags = 4937 (csum_flags | txbd_tso_flags) & 0x0fff; 4938 } 4939 } else { 4940 f->bge_rsvd = 0; 4941 f->bge_flags = csum_flags; 4942 } 4943 4944 if (mtag != NULL) { 4945 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4946 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4947 } else { 4948 f->bge_vlan_tag = 0; 4949 } 4950 cur = frag; 4951 BGE_INC(frag, BGE_TX_RING_CNT); 4952 } 4953 4954 if (i < dmamap->dm_nsegs) { 4955 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4956 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4957 goto fail_unload; 4958 } 4959 4960 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4961 BUS_DMASYNC_PREWRITE); 4962 4963 if (frag == sc->bge_tx_saved_considx) { 4964 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4965 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4966 4967 goto fail_unload; 4968 } 4969 4970 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4971 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4972 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4973 sc->txdma[cur] = dma; 4974 sc->bge_txcnt += dmamap->dm_nsegs; 4975 4976 *txidx = frag; 4977 4978 return 0; 4979 4980 fail_unload: 4981 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4982 4983 return ENOBUFS; 4984 } 4985 4986 /* 4987 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4988 * to the mbuf data regions directly in the transmit descriptors. 4989 */ 4990 static void 4991 bge_start(struct ifnet *ifp) 4992 { 4993 struct bge_softc *sc; 4994 struct mbuf *m_head = NULL; 4995 uint32_t prodidx; 4996 int pkts = 0; 4997 4998 sc = ifp->if_softc; 4999 5000 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5001 return; 5002 5003 prodidx = sc->bge_tx_prodidx; 5004 5005 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5006 IFQ_POLL(&ifp->if_snd, m_head); 5007 if (m_head == NULL) 5008 break; 5009 5010 #if 0 5011 /* 5012 * XXX 5013 * safety overkill. If this is a fragmented packet chain 5014 * with delayed TCP/UDP checksums, then only encapsulate 5015 * it if we have enough descriptors to handle the entire 5016 * chain at once. 5017 * (paranoia -- may not actually be needed) 5018 */ 5019 if (m_head->m_flags & M_FIRSTFRAG && 5020 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5021 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5022 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5023 ifp->if_flags |= IFF_OACTIVE; 5024 break; 5025 } 5026 } 5027 #endif 5028 5029 /* 5030 * Pack the data into the transmit ring. If we 5031 * don't have room, set the OACTIVE flag and wait 5032 * for the NIC to drain the ring. 5033 */ 5034 if (bge_encap(sc, m_head, &prodidx)) { 5035 ifp->if_flags |= IFF_OACTIVE; 5036 break; 5037 } 5038 5039 /* now we are committed to transmit the packet */ 5040 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5041 pkts++; 5042 5043 /* 5044 * If there's a BPF listener, bounce a copy of this frame 5045 * to him. 5046 */ 5047 bpf_mtap(ifp, m_head); 5048 } 5049 if (pkts == 0) 5050 return; 5051 5052 /* Transmit */ 5053 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5054 /* 5700 b2 errata */ 5055 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5056 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5057 5058 sc->bge_tx_prodidx = prodidx; 5059 5060 /* 5061 * Set a timeout in case the chip goes out to lunch. 5062 */ 5063 ifp->if_timer = 5; 5064 } 5065 5066 static int 5067 bge_init(struct ifnet *ifp) 5068 { 5069 struct bge_softc *sc = ifp->if_softc; 5070 const uint16_t *m; 5071 uint32_t mode; 5072 int s, error = 0; 5073 5074 s = splnet(); 5075 5076 ifp = &sc->ethercom.ec_if; 5077 5078 /* Cancel pending I/O and flush buffers. */ 5079 bge_stop(ifp, 0); 5080 5081 bge_stop_fw(sc); 5082 bge_sig_pre_reset(sc, BGE_RESET_START); 5083 bge_reset(sc); 5084 bge_sig_legacy(sc, BGE_RESET_START); 5085 bge_sig_post_reset(sc, BGE_RESET_START); 5086 5087 bge_chipinit(sc); 5088 5089 /* 5090 * Init the various state machines, ring 5091 * control blocks and firmware. 5092 */ 5093 error = bge_blockinit(sc); 5094 if (error != 0) { 5095 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5096 error); 5097 splx(s); 5098 return error; 5099 } 5100 5101 ifp = &sc->ethercom.ec_if; 5102 5103 /* Specify MTU. */ 5104 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5105 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5106 5107 /* Load our MAC address. */ 5108 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5109 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5110 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5111 5112 /* Enable or disable promiscuous mode as needed. */ 5113 if (ifp->if_flags & IFF_PROMISC) 5114 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5115 else 5116 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5117 5118 /* Program multicast filter. */ 5119 bge_setmulti(sc); 5120 5121 /* Init RX ring. */ 5122 bge_init_rx_ring_std(sc); 5123 5124 /* 5125 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5126 * memory to insure that the chip has in fact read the first 5127 * entry of the ring. 5128 */ 5129 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5130 uint32_t v, i; 5131 for (i = 0; i < 10; i++) { 5132 DELAY(20); 5133 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5134 if (v == (MCLBYTES - ETHER_ALIGN)) 5135 break; 5136 } 5137 if (i == 10) 5138 aprint_error_dev(sc->bge_dev, 5139 "5705 A0 chip failed to load RX ring\n"); 5140 } 5141 5142 /* Init jumbo RX ring. */ 5143 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5144 bge_init_rx_ring_jumbo(sc); 5145 5146 /* Init our RX return ring index */ 5147 sc->bge_rx_saved_considx = 0; 5148 5149 /* Init TX ring. */ 5150 bge_init_tx_ring(sc); 5151 5152 /* Enable TX MAC state machine lockup fix. */ 5153 mode = CSR_READ_4(sc, BGE_TX_MODE); 5154 if (BGE_IS_5755_PLUS(sc) || 5155 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5156 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5157 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5158 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5159 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5160 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5161 } 5162 5163 /* Turn on transmitter */ 5164 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5165 DELAY(100); 5166 5167 /* Turn on receiver */ 5168 mode = CSR_READ_4(sc, BGE_RX_MODE); 5169 if (BGE_IS_5755_PLUS(sc)) 5170 mode |= BGE_RXMODE_IPV6_ENABLE; 5171 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5172 DELAY(10); 5173 5174 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5175 5176 /* Tell firmware we're alive. */ 5177 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5178 5179 /* Enable host interrupts. */ 5180 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5181 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5182 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5183 5184 if ((error = bge_ifmedia_upd(ifp)) != 0) 5185 goto out; 5186 5187 ifp->if_flags |= IFF_RUNNING; 5188 ifp->if_flags &= ~IFF_OACTIVE; 5189 5190 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5191 5192 out: 5193 sc->bge_if_flags = ifp->if_flags; 5194 splx(s); 5195 5196 return error; 5197 } 5198 5199 /* 5200 * Set media options. 5201 */ 5202 static int 5203 bge_ifmedia_upd(struct ifnet *ifp) 5204 { 5205 struct bge_softc *sc = ifp->if_softc; 5206 struct mii_data *mii = &sc->bge_mii; 5207 struct ifmedia *ifm = &sc->bge_ifmedia; 5208 int rc; 5209 5210 /* If this is a 1000baseX NIC, enable the TBI port. */ 5211 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5212 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5213 return EINVAL; 5214 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5215 case IFM_AUTO: 5216 /* 5217 * The BCM5704 ASIC appears to have a special 5218 * mechanism for programming the autoneg 5219 * advertisement registers in TBI mode. 5220 */ 5221 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5222 uint32_t sgdig; 5223 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5224 if (sgdig & BGE_SGDIGSTS_DONE) { 5225 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5226 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5227 sgdig |= BGE_SGDIGCFG_AUTO | 5228 BGE_SGDIGCFG_PAUSE_CAP | 5229 BGE_SGDIGCFG_ASYM_PAUSE; 5230 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5231 sgdig | BGE_SGDIGCFG_SEND); 5232 DELAY(5); 5233 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5234 sgdig); 5235 } 5236 } 5237 break; 5238 case IFM_1000_SX: 5239 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5240 BGE_CLRBIT(sc, BGE_MAC_MODE, 5241 BGE_MACMODE_HALF_DUPLEX); 5242 } else { 5243 BGE_SETBIT(sc, BGE_MAC_MODE, 5244 BGE_MACMODE_HALF_DUPLEX); 5245 } 5246 DELAY(40); 5247 break; 5248 default: 5249 return EINVAL; 5250 } 5251 /* XXX 802.3x flow control for 1000BASE-SX */ 5252 return 0; 5253 } 5254 5255 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5256 if ((rc = mii_mediachg(mii)) == ENXIO) 5257 return 0; 5258 5259 /* 5260 * Force an interrupt so that we will call bge_link_upd 5261 * if needed and clear any pending link state attention. 5262 * Without this we are not getting any further interrupts 5263 * for link state changes and thus will not UP the link and 5264 * not be able to send in bge_start. The only way to get 5265 * things working was to receive a packet and get a RX intr. 5266 */ 5267 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5268 sc->bge_flags & BGE_IS_5788) 5269 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5270 else 5271 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5272 5273 return rc; 5274 } 5275 5276 /* 5277 * Report current media status. 5278 */ 5279 static void 5280 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5281 { 5282 struct bge_softc *sc = ifp->if_softc; 5283 struct mii_data *mii = &sc->bge_mii; 5284 5285 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5286 ifmr->ifm_status = IFM_AVALID; 5287 ifmr->ifm_active = IFM_ETHER; 5288 if (CSR_READ_4(sc, BGE_MAC_STS) & 5289 BGE_MACSTAT_TBI_PCS_SYNCHED) 5290 ifmr->ifm_status |= IFM_ACTIVE; 5291 ifmr->ifm_active |= IFM_1000_SX; 5292 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5293 ifmr->ifm_active |= IFM_HDX; 5294 else 5295 ifmr->ifm_active |= IFM_FDX; 5296 return; 5297 } 5298 5299 mii_pollstat(mii); 5300 ifmr->ifm_status = mii->mii_media_status; 5301 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5302 sc->bge_flowflags; 5303 } 5304 5305 static int 5306 bge_ifflags_cb(struct ethercom *ec) 5307 { 5308 struct ifnet *ifp = &ec->ec_if; 5309 struct bge_softc *sc = ifp->if_softc; 5310 int change = ifp->if_flags ^ sc->bge_if_flags; 5311 5312 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5313 return ENETRESET; 5314 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5315 return 0; 5316 5317 if ((ifp->if_flags & IFF_PROMISC) == 0) 5318 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5319 else 5320 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5321 5322 bge_setmulti(sc); 5323 5324 sc->bge_if_flags = ifp->if_flags; 5325 return 0; 5326 } 5327 5328 static int 5329 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5330 { 5331 struct bge_softc *sc = ifp->if_softc; 5332 struct ifreq *ifr = (struct ifreq *) data; 5333 int s, error = 0; 5334 struct mii_data *mii; 5335 5336 s = splnet(); 5337 5338 switch (command) { 5339 case SIOCSIFMEDIA: 5340 /* XXX Flow control is not supported for 1000BASE-SX */ 5341 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5342 ifr->ifr_media &= ~IFM_ETH_FMASK; 5343 sc->bge_flowflags = 0; 5344 } 5345 5346 /* Flow control requires full-duplex mode. */ 5347 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5348 (ifr->ifr_media & IFM_FDX) == 0) { 5349 ifr->ifr_media &= ~IFM_ETH_FMASK; 5350 } 5351 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5352 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5353 /* We can do both TXPAUSE and RXPAUSE. */ 5354 ifr->ifr_media |= 5355 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5356 } 5357 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5358 } 5359 /* FALLTHROUGH */ 5360 case SIOCGIFMEDIA: 5361 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5362 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5363 command); 5364 } else { 5365 mii = &sc->bge_mii; 5366 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5367 command); 5368 } 5369 break; 5370 default: 5371 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5372 break; 5373 5374 error = 0; 5375 5376 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5377 ; 5378 else if (ifp->if_flags & IFF_RUNNING) 5379 bge_setmulti(sc); 5380 break; 5381 } 5382 5383 splx(s); 5384 5385 return error; 5386 } 5387 5388 static void 5389 bge_watchdog(struct ifnet *ifp) 5390 { 5391 struct bge_softc *sc; 5392 5393 sc = ifp->if_softc; 5394 5395 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5396 5397 ifp->if_flags &= ~IFF_RUNNING; 5398 bge_init(ifp); 5399 5400 ifp->if_oerrors++; 5401 } 5402 5403 static void 5404 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5405 { 5406 int i; 5407 5408 BGE_CLRBIT_FLUSH(sc, reg, bit); 5409 5410 for (i = 0; i < 1000; i++) { 5411 delay(100); 5412 if ((CSR_READ_4(sc, reg) & bit) == 0) 5413 return; 5414 } 5415 5416 /* 5417 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5418 * on some environment (and once after boot?) 5419 */ 5420 if (reg != BGE_SRS_MODE) 5421 aprint_error_dev(sc->bge_dev, 5422 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5423 (u_long)reg, bit); 5424 } 5425 5426 /* 5427 * Stop the adapter and free any mbufs allocated to the 5428 * RX and TX lists. 5429 */ 5430 static void 5431 bge_stop(struct ifnet *ifp, int disable) 5432 { 5433 struct bge_softc *sc = ifp->if_softc; 5434 5435 callout_stop(&sc->bge_timeout); 5436 5437 /* Disable host interrupts. */ 5438 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5439 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5440 5441 /* 5442 * Tell firmware we're shutting down. 5443 */ 5444 bge_stop_fw(sc); 5445 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5446 5447 /* 5448 * Disable all of the receiver blocks. 5449 */ 5450 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5451 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5452 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5453 if (BGE_IS_5700_FAMILY(sc)) 5454 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5455 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5456 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5457 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5458 5459 /* 5460 * Disable all of the transmit blocks. 5461 */ 5462 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5463 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5464 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5465 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5466 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5467 if (BGE_IS_5700_FAMILY(sc)) 5468 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5469 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5470 5471 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5472 delay(40); 5473 5474 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5475 5476 /* 5477 * Shut down all of the memory managers and related 5478 * state machines. 5479 */ 5480 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5481 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5482 if (BGE_IS_5700_FAMILY(sc)) 5483 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5484 5485 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5486 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5487 5488 if (BGE_IS_5700_FAMILY(sc)) { 5489 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5490 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5491 } 5492 5493 bge_reset(sc); 5494 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5495 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5496 5497 /* 5498 * Keep the ASF firmware running if up. 5499 */ 5500 if (sc->bge_asf_mode & ASF_STACKUP) 5501 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5502 else 5503 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5504 5505 /* Free the RX lists. */ 5506 bge_free_rx_ring_std(sc); 5507 5508 /* Free jumbo RX list. */ 5509 if (BGE_IS_JUMBO_CAPABLE(sc)) 5510 bge_free_rx_ring_jumbo(sc); 5511 5512 /* Free TX buffers. */ 5513 bge_free_tx_ring(sc); 5514 5515 /* 5516 * Isolate/power down the PHY. 5517 */ 5518 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5519 mii_down(&sc->bge_mii); 5520 5521 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5522 5523 /* Clear MAC's link state (PHY may still have link UP). */ 5524 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5525 5526 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5527 } 5528 5529 static void 5530 bge_link_upd(struct bge_softc *sc) 5531 { 5532 struct ifnet *ifp = &sc->ethercom.ec_if; 5533 struct mii_data *mii = &sc->bge_mii; 5534 uint32_t status; 5535 int link; 5536 5537 /* Clear 'pending link event' flag */ 5538 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5539 5540 /* 5541 * Process link state changes. 5542 * Grrr. The link status word in the status block does 5543 * not work correctly on the BCM5700 rev AX and BX chips, 5544 * according to all available information. Hence, we have 5545 * to enable MII interrupts in order to properly obtain 5546 * async link changes. Unfortunately, this also means that 5547 * we have to read the MAC status register to detect link 5548 * changes, thereby adding an additional register access to 5549 * the interrupt handler. 5550 */ 5551 5552 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5553 status = CSR_READ_4(sc, BGE_MAC_STS); 5554 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5555 mii_pollstat(mii); 5556 5557 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5558 mii->mii_media_status & IFM_ACTIVE && 5559 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5560 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5561 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5562 (!(mii->mii_media_status & IFM_ACTIVE) || 5563 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5564 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5565 5566 /* Clear the interrupt */ 5567 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5568 BGE_EVTENB_MI_INTERRUPT); 5569 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5570 BRGPHY_MII_ISR); 5571 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5572 BRGPHY_MII_IMR, BRGPHY_INTRS); 5573 } 5574 return; 5575 } 5576 5577 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5578 status = CSR_READ_4(sc, BGE_MAC_STS); 5579 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5580 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5581 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5582 if (BGE_ASICREV(sc->bge_chipid) 5583 == BGE_ASICREV_BCM5704) { 5584 BGE_CLRBIT(sc, BGE_MAC_MODE, 5585 BGE_MACMODE_TBI_SEND_CFGS); 5586 DELAY(40); 5587 } 5588 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5589 if_link_state_change(ifp, LINK_STATE_UP); 5590 } 5591 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5592 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5593 if_link_state_change(ifp, LINK_STATE_DOWN); 5594 } 5595 /* 5596 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5597 * This should not happen since mii callouts are locked now, but 5598 * we keep this check for debug. 5599 */ 5600 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5601 /* 5602 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5603 * bit in status word always set. Workaround this bug by 5604 * reading PHY link status directly. 5605 */ 5606 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5607 BGE_STS_LINK : 0; 5608 5609 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5610 mii_pollstat(mii); 5611 5612 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5613 mii->mii_media_status & IFM_ACTIVE && 5614 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5615 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5616 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5617 (!(mii->mii_media_status & IFM_ACTIVE) || 5618 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5619 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5620 } 5621 } 5622 5623 /* Clear the attention */ 5624 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5625 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5626 BGE_MACSTAT_LINK_CHANGED); 5627 } 5628 5629 static int 5630 bge_sysctl_verify(SYSCTLFN_ARGS) 5631 { 5632 int error, t; 5633 struct sysctlnode node; 5634 5635 node = *rnode; 5636 t = *(int*)rnode->sysctl_data; 5637 node.sysctl_data = &t; 5638 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5639 if (error || newp == NULL) 5640 return error; 5641 5642 #if 0 5643 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5644 node.sysctl_num, rnode->sysctl_num)); 5645 #endif 5646 5647 if (node.sysctl_num == bge_rxthresh_nodenum) { 5648 if (t < 0 || t >= NBGE_RX_THRESH) 5649 return EINVAL; 5650 bge_update_all_threshes(t); 5651 } else 5652 return EINVAL; 5653 5654 *(int*)rnode->sysctl_data = t; 5655 5656 return 0; 5657 } 5658 5659 /* 5660 * Set up sysctl(3) MIB, hw.bge.*. 5661 */ 5662 static void 5663 bge_sysctl_init(struct bge_softc *sc) 5664 { 5665 int rc, bge_root_num; 5666 const struct sysctlnode *node; 5667 5668 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5669 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5670 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5671 goto out; 5672 } 5673 5674 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5675 0, CTLTYPE_NODE, "bge", 5676 SYSCTL_DESCR("BGE interface controls"), 5677 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5678 goto out; 5679 } 5680 5681 bge_root_num = node->sysctl_num; 5682 5683 /* BGE Rx interrupt mitigation level */ 5684 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5685 CTLFLAG_READWRITE, 5686 CTLTYPE_INT, "rx_lvl", 5687 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5688 bge_sysctl_verify, 0, 5689 &bge_rx_thresh_lvl, 5690 0, CTL_HW, bge_root_num, CTL_CREATE, 5691 CTL_EOL)) != 0) { 5692 goto out; 5693 } 5694 5695 bge_rxthresh_nodenum = node->sysctl_num; 5696 5697 return; 5698 5699 out: 5700 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5701 } 5702 5703 #ifdef BGE_DEBUG 5704 void 5705 bge_debug_info(struct bge_softc *sc) 5706 { 5707 5708 printf("Hardware Flags:\n"); 5709 if (BGE_IS_57765_PLUS(sc)) 5710 printf(" - 57765 Plus\n"); 5711 if (BGE_IS_5717_PLUS(sc)) 5712 printf(" - 5717 Plus\n"); 5713 if (BGE_IS_5755_PLUS(sc)) 5714 printf(" - 5755 Plus\n"); 5715 if (BGE_IS_575X_PLUS(sc)) 5716 printf(" - 575X Plus\n"); 5717 if (BGE_IS_5705_PLUS(sc)) 5718 printf(" - 5705 Plus\n"); 5719 if (BGE_IS_5714_FAMILY(sc)) 5720 printf(" - 5714 Family\n"); 5721 if (BGE_IS_5700_FAMILY(sc)) 5722 printf(" - 5700 Family\n"); 5723 if (sc->bge_flags & BGE_IS_5788) 5724 printf(" - 5788\n"); 5725 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5726 printf(" - Supports Jumbo Frames\n"); 5727 if (sc->bge_flags & BGE_NO_EEPROM) 5728 printf(" - No EEPROM\n"); 5729 if (sc->bge_flags & BGE_PCIX) 5730 printf(" - PCI-X Bus\n"); 5731 if (sc->bge_flags & BGE_PCIE) 5732 printf(" - PCI Express Bus\n"); 5733 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5734 printf(" - RX Alignment Bug\n"); 5735 if (sc->bge_flags & BGE_APE) 5736 printf(" - APE\n"); 5737 if (sc->bge_flags & BGE_CPMU_PRESENT) 5738 printf(" - CPMU\n"); 5739 if (sc->bge_flags & BGE_TSO) 5740 printf(" - TSO\n"); 5741 5742 if (sc->bge_flags & BGE_PHY_NO_3LED) 5743 printf(" - No 3 LEDs\n"); 5744 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5745 printf(" - CRC bug\n"); 5746 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5747 printf(" - ADC bug\n"); 5748 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5749 printf(" - 5704 A0 bug\n"); 5750 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5751 printf(" - jitter bug\n"); 5752 if (sc->bge_flags & BGE_PHY_BER_BUG) 5753 printf(" - BER bug\n"); 5754 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5755 printf(" - adjust trim\n"); 5756 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5757 printf(" - no wirespeed\n"); 5758 } 5759 #endif /* BGE_DEBUG */ 5760 5761 static int 5762 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5763 { 5764 prop_dictionary_t dict; 5765 prop_data_t ea; 5766 5767 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5768 return 1; 5769 5770 dict = device_properties(sc->bge_dev); 5771 ea = prop_dictionary_get(dict, "mac-address"); 5772 if (ea != NULL) { 5773 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5774 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5775 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5776 return 0; 5777 } 5778 5779 return 1; 5780 } 5781 5782 static int 5783 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5784 { 5785 uint32_t mac_addr; 5786 5787 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5788 if ((mac_addr >> 16) == 0x484b) { 5789 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5790 ether_addr[1] = (uint8_t)mac_addr; 5791 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5792 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5793 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5794 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5795 ether_addr[5] = (uint8_t)mac_addr; 5796 return 0; 5797 } 5798 return 1; 5799 } 5800 5801 static int 5802 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5803 { 5804 int mac_offset = BGE_EE_MAC_OFFSET; 5805 5806 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5807 mac_offset = BGE_EE_MAC_OFFSET_5906; 5808 5809 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5810 ETHER_ADDR_LEN)); 5811 } 5812 5813 static int 5814 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5815 { 5816 5817 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5818 return 1; 5819 5820 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5821 ETHER_ADDR_LEN)); 5822 } 5823 5824 static int 5825 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5826 { 5827 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5828 /* NOTE: Order is critical */ 5829 bge_get_eaddr_fw, 5830 bge_get_eaddr_mem, 5831 bge_get_eaddr_nvram, 5832 bge_get_eaddr_eeprom, 5833 NULL 5834 }; 5835 const bge_eaddr_fcn_t *func; 5836 5837 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5838 if ((*func)(sc, eaddr) == 0) 5839 break; 5840 } 5841 return (*func == NULL ? ENXIO : 0); 5842 } 5843
Indexes created Tue Sep 23 21:09:50 GMT 2025