if_bge.c revision 1.227
1 /* $NetBSD: if_bge.c,v 1.227 2013/03/24 22:33:59 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.227 2013/03/24 22:33:59 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static int bge_detach(device_t, int); 191 static void bge_release_resources(struct bge_softc *); 192 193 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 198 199 static void bge_txeof(struct bge_softc *); 200 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 201 static void bge_rxeof(struct bge_softc *); 202 203 static void bge_asf_driver_up (struct bge_softc *); 204 static void bge_tick(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static void bge_stats_update_regs(struct bge_softc *); 207 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 208 209 static int bge_intr(void *); 210 static void bge_start(struct ifnet *); 211 static int bge_ifflags_cb(struct ethercom *); 212 static int bge_ioctl(struct ifnet *, u_long, void *); 213 static int bge_init(struct ifnet *); 214 static void bge_stop(struct ifnet *, int); 215 static void bge_watchdog(struct ifnet *); 216 static int bge_ifmedia_upd(struct ifnet *); 217 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 219 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 221 222 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 223 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 224 static void bge_setmulti(struct bge_softc *); 225 226 static void bge_handle_events(struct bge_softc *); 227 static int bge_alloc_jumbo_mem(struct bge_softc *); 228 #if 0 /* XXX */ 229 static void bge_free_jumbo_mem(struct bge_softc *); 230 #endif 231 static void *bge_jalloc(struct bge_softc *); 232 static void bge_jfree(struct mbuf *, void *, size_t, void *); 233 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 234 bus_dmamap_t); 235 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 236 static int bge_init_rx_ring_std(struct bge_softc *); 237 static void bge_free_rx_ring_std(struct bge_softc *); 238 static int bge_init_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_rx_ring_jumbo(struct bge_softc *); 240 static void bge_free_tx_ring(struct bge_softc *); 241 static int bge_init_tx_ring(struct bge_softc *); 242 243 static int bge_chipinit(struct bge_softc *); 244 static int bge_blockinit(struct bge_softc *); 245 static int bge_phy_addr(struct bge_softc *); 246 static uint32_t bge_readmem_ind(struct bge_softc *, int); 247 static void bge_writemem_ind(struct bge_softc *, int, int); 248 static void bge_writembx(struct bge_softc *, int, int); 249 static void bge_writembx_flush(struct bge_softc *, int, int); 250 static void bge_writemem_direct(struct bge_softc *, int, int); 251 static void bge_writereg_ind(struct bge_softc *, int, int); 252 static void bge_set_max_readrq(struct bge_softc *); 253 254 static int bge_miibus_readreg(device_t, int, int); 255 static void bge_miibus_writereg(device_t, int, int, int); 256 static void bge_miibus_statchg(struct ifnet *); 257 258 #define BGE_RESET_SHUTDOWN 0 259 #define BGE_RESET_START 1 260 #define BGE_RESET_SUSPEND 2 261 static void bge_sig_post_reset(struct bge_softc *, int); 262 static void bge_sig_legacy(struct bge_softc *, int); 263 static void bge_sig_pre_reset(struct bge_softc *, int); 264 static void bge_wait_for_event_ack(struct bge_softc *); 265 static void bge_stop_fw(struct bge_softc *); 266 static int bge_reset(struct bge_softc *); 267 static void bge_link_upd(struct bge_softc *); 268 static void bge_sysctl_init(struct bge_softc *); 269 static int bge_sysctl_verify(SYSCTLFN_PROTO); 270 271 static void bge_ape_lock_init(struct bge_softc *); 272 static void bge_ape_read_fw_ver(struct bge_softc *); 273 static int bge_ape_lock(struct bge_softc *, int); 274 static void bge_ape_unlock(struct bge_softc *, int); 275 static void bge_ape_send_event(struct bge_softc *, uint32_t); 276 static void bge_ape_driver_state_change(struct bge_softc *, int); 277 278 #ifdef BGE_DEBUG 279 #define DPRINTF(x) if (bgedebug) printf x 280 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 281 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 282 int bgedebug = 0; 283 int bge_tso_debug = 0; 284 void bge_debug_info(struct bge_softc *); 285 #else 286 #define DPRINTF(x) 287 #define DPRINTFN(n,x) 288 #define BGE_TSO_PRINTF(x) 289 #endif 290 291 #ifdef BGE_EVENT_COUNTERS 292 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 293 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 294 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 295 #else 296 #define BGE_EVCNT_INCR(ev) /* nothing */ 297 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 298 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 299 #endif 300 301 static const struct bge_product { 302 pci_vendor_id_t bp_vendor; 303 pci_product_id_t bp_product; 304 const char *bp_name; 305 } bge_products[] = { 306 /* 307 * The BCM5700 documentation seems to indicate that the hardware 308 * still has the Alteon vendor ID burned into it, though it 309 * should always be overridden by the value in the EEPROM. We'll 310 * check for it anyway. 311 */ 312 { PCI_VENDOR_ALTEON, 313 PCI_PRODUCT_ALTEON_BCM5700, 314 "Broadcom BCM5700 Gigabit Ethernet", 315 }, 316 { PCI_VENDOR_ALTEON, 317 PCI_PRODUCT_ALTEON_BCM5701, 318 "Broadcom BCM5701 Gigabit Ethernet", 319 }, 320 { PCI_VENDOR_ALTIMA, 321 PCI_PRODUCT_ALTIMA_AC1000, 322 "Altima AC1000 Gigabit Ethernet", 323 }, 324 { PCI_VENDOR_ALTIMA, 325 PCI_PRODUCT_ALTIMA_AC1001, 326 "Altima AC1001 Gigabit Ethernet", 327 }, 328 { PCI_VENDOR_ALTIMA, 329 PCI_PRODUCT_ALTIMA_AC1003, 330 "Altima AC1003 Gigabit Ethernet", 331 }, 332 { PCI_VENDOR_ALTIMA, 333 PCI_PRODUCT_ALTIMA_AC9100, 334 "Altima AC9100 Gigabit Ethernet", 335 }, 336 { PCI_VENDOR_APPLE, 337 PCI_PRODUCT_APPLE_BCM5701, 338 "APPLE BCM5701 Gigabit Ethernet", 339 }, 340 { PCI_VENDOR_BROADCOM, 341 PCI_PRODUCT_BROADCOM_BCM5700, 342 "Broadcom BCM5700 Gigabit Ethernet", 343 }, 344 { PCI_VENDOR_BROADCOM, 345 PCI_PRODUCT_BROADCOM_BCM5701, 346 "Broadcom BCM5701 Gigabit Ethernet", 347 }, 348 { PCI_VENDOR_BROADCOM, 349 PCI_PRODUCT_BROADCOM_BCM5702, 350 "Broadcom BCM5702 Gigabit Ethernet", 351 }, 352 { PCI_VENDOR_BROADCOM, 353 PCI_PRODUCT_BROADCOM_BCM5702X, 354 "Broadcom BCM5702X Gigabit Ethernet" }, 355 { PCI_VENDOR_BROADCOM, 356 PCI_PRODUCT_BROADCOM_BCM5703, 357 "Broadcom BCM5703 Gigabit Ethernet", 358 }, 359 { PCI_VENDOR_BROADCOM, 360 PCI_PRODUCT_BROADCOM_BCM5703X, 361 "Broadcom BCM5703X Gigabit Ethernet", 362 }, 363 { PCI_VENDOR_BROADCOM, 364 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 365 "Broadcom BCM5703 Gigabit Ethernet", 366 }, 367 { PCI_VENDOR_BROADCOM, 368 PCI_PRODUCT_BROADCOM_BCM5704C, 369 "Broadcom BCM5704C Dual Gigabit Ethernet", 370 }, 371 { PCI_VENDOR_BROADCOM, 372 PCI_PRODUCT_BROADCOM_BCM5704S, 373 "Broadcom BCM5704S Dual Gigabit Ethernet", 374 }, 375 { PCI_VENDOR_BROADCOM, 376 PCI_PRODUCT_BROADCOM_BCM5705, 377 "Broadcom BCM5705 Gigabit Ethernet", 378 }, 379 { PCI_VENDOR_BROADCOM, 380 PCI_PRODUCT_BROADCOM_BCM5705F, 381 "Broadcom BCM5705F Gigabit Ethernet", 382 }, 383 { PCI_VENDOR_BROADCOM, 384 PCI_PRODUCT_BROADCOM_BCM5705K, 385 "Broadcom BCM5705K Gigabit Ethernet", 386 }, 387 { PCI_VENDOR_BROADCOM, 388 PCI_PRODUCT_BROADCOM_BCM5705M, 389 "Broadcom BCM5705M Gigabit Ethernet", 390 }, 391 { PCI_VENDOR_BROADCOM, 392 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 393 "Broadcom BCM5705M Gigabit Ethernet", 394 }, 395 { PCI_VENDOR_BROADCOM, 396 PCI_PRODUCT_BROADCOM_BCM5714, 397 "Broadcom BCM5714 Gigabit Ethernet", 398 }, 399 { PCI_VENDOR_BROADCOM, 400 PCI_PRODUCT_BROADCOM_BCM5714S, 401 "Broadcom BCM5714S Gigabit Ethernet", 402 }, 403 { PCI_VENDOR_BROADCOM, 404 PCI_PRODUCT_BROADCOM_BCM5715, 405 "Broadcom BCM5715 Gigabit Ethernet", 406 }, 407 { PCI_VENDOR_BROADCOM, 408 PCI_PRODUCT_BROADCOM_BCM5715S, 409 "Broadcom BCM5715S Gigabit Ethernet", 410 }, 411 { PCI_VENDOR_BROADCOM, 412 PCI_PRODUCT_BROADCOM_BCM5717, 413 "Broadcom BCM5717 Gigabit Ethernet", 414 }, 415 { PCI_VENDOR_BROADCOM, 416 PCI_PRODUCT_BROADCOM_BCM5718, 417 "Broadcom BCM5718 Gigabit Ethernet", 418 }, 419 { PCI_VENDOR_BROADCOM, 420 PCI_PRODUCT_BROADCOM_BCM5719, 421 "Broadcom BCM5719 Gigabit Ethernet", 422 }, 423 { PCI_VENDOR_BROADCOM, 424 PCI_PRODUCT_BROADCOM_BCM5720, 425 "Broadcom BCM5720 Gigabit Ethernet", 426 }, 427 { PCI_VENDOR_BROADCOM, 428 PCI_PRODUCT_BROADCOM_BCM5721, 429 "Broadcom BCM5721 Gigabit Ethernet", 430 }, 431 { PCI_VENDOR_BROADCOM, 432 PCI_PRODUCT_BROADCOM_BCM5722, 433 "Broadcom BCM5722 Gigabit Ethernet", 434 }, 435 { PCI_VENDOR_BROADCOM, 436 PCI_PRODUCT_BROADCOM_BCM5723, 437 "Broadcom BCM5723 Gigabit Ethernet", 438 }, 439 { PCI_VENDOR_BROADCOM, 440 PCI_PRODUCT_BROADCOM_BCM5724, 441 "Broadcom BCM5724 Gigabit Ethernet", 442 }, 443 { PCI_VENDOR_BROADCOM, 444 PCI_PRODUCT_BROADCOM_BCM5750, 445 "Broadcom BCM5750 Gigabit Ethernet", 446 }, 447 { PCI_VENDOR_BROADCOM, 448 PCI_PRODUCT_BROADCOM_BCM5750M, 449 "Broadcom BCM5750M Gigabit Ethernet", 450 }, 451 { PCI_VENDOR_BROADCOM, 452 PCI_PRODUCT_BROADCOM_BCM5751, 453 "Broadcom BCM5751 Gigabit Ethernet", 454 }, 455 { PCI_VENDOR_BROADCOM, 456 PCI_PRODUCT_BROADCOM_BCM5751F, 457 "Broadcom BCM5751F Gigabit Ethernet", 458 }, 459 { PCI_VENDOR_BROADCOM, 460 PCI_PRODUCT_BROADCOM_BCM5751M, 461 "Broadcom BCM5751M Gigabit Ethernet", 462 }, 463 { PCI_VENDOR_BROADCOM, 464 PCI_PRODUCT_BROADCOM_BCM5752, 465 "Broadcom BCM5752 Gigabit Ethernet", 466 }, 467 { PCI_VENDOR_BROADCOM, 468 PCI_PRODUCT_BROADCOM_BCM5752M, 469 "Broadcom BCM5752M Gigabit Ethernet", 470 }, 471 { PCI_VENDOR_BROADCOM, 472 PCI_PRODUCT_BROADCOM_BCM5753, 473 "Broadcom BCM5753 Gigabit Ethernet", 474 }, 475 { PCI_VENDOR_BROADCOM, 476 PCI_PRODUCT_BROADCOM_BCM5753F, 477 "Broadcom BCM5753F Gigabit Ethernet", 478 }, 479 { PCI_VENDOR_BROADCOM, 480 PCI_PRODUCT_BROADCOM_BCM5753M, 481 "Broadcom BCM5753M Gigabit Ethernet", 482 }, 483 { PCI_VENDOR_BROADCOM, 484 PCI_PRODUCT_BROADCOM_BCM5754, 485 "Broadcom BCM5754 Gigabit Ethernet", 486 }, 487 { PCI_VENDOR_BROADCOM, 488 PCI_PRODUCT_BROADCOM_BCM5754M, 489 "Broadcom BCM5754M Gigabit Ethernet", 490 }, 491 { PCI_VENDOR_BROADCOM, 492 PCI_PRODUCT_BROADCOM_BCM5755, 493 "Broadcom BCM5755 Gigabit Ethernet", 494 }, 495 { PCI_VENDOR_BROADCOM, 496 PCI_PRODUCT_BROADCOM_BCM5755M, 497 "Broadcom BCM5755M Gigabit Ethernet", 498 }, 499 { PCI_VENDOR_BROADCOM, 500 PCI_PRODUCT_BROADCOM_BCM5756, 501 "Broadcom BCM5756 Gigabit Ethernet", 502 }, 503 { PCI_VENDOR_BROADCOM, 504 PCI_PRODUCT_BROADCOM_BCM5761, 505 "Broadcom BCM5761 Gigabit Ethernet", 506 }, 507 { PCI_VENDOR_BROADCOM, 508 PCI_PRODUCT_BROADCOM_BCM5761E, 509 "Broadcom BCM5761E Gigabit Ethernet", 510 }, 511 { PCI_VENDOR_BROADCOM, 512 PCI_PRODUCT_BROADCOM_BCM5761S, 513 "Broadcom BCM5761S Gigabit Ethernet", 514 }, 515 { PCI_VENDOR_BROADCOM, 516 PCI_PRODUCT_BROADCOM_BCM5761SE, 517 "Broadcom BCM5761SE Gigabit Ethernet", 518 }, 519 { PCI_VENDOR_BROADCOM, 520 PCI_PRODUCT_BROADCOM_BCM5764, 521 "Broadcom BCM5764 Gigabit Ethernet", 522 }, 523 { PCI_VENDOR_BROADCOM, 524 PCI_PRODUCT_BROADCOM_BCM5780, 525 "Broadcom BCM5780 Gigabit Ethernet", 526 }, 527 { PCI_VENDOR_BROADCOM, 528 PCI_PRODUCT_BROADCOM_BCM5780S, 529 "Broadcom BCM5780S Gigabit Ethernet", 530 }, 531 { PCI_VENDOR_BROADCOM, 532 PCI_PRODUCT_BROADCOM_BCM5781, 533 "Broadcom BCM5781 Gigabit Ethernet", 534 }, 535 { PCI_VENDOR_BROADCOM, 536 PCI_PRODUCT_BROADCOM_BCM5782, 537 "Broadcom BCM5782 Gigabit Ethernet", 538 }, 539 { PCI_VENDOR_BROADCOM, 540 PCI_PRODUCT_BROADCOM_BCM5784M, 541 "BCM5784M NetLink 1000baseT Ethernet", 542 }, 543 { PCI_VENDOR_BROADCOM, 544 PCI_PRODUCT_BROADCOM_BCM5785F, 545 "BCM5785F NetLink 10/100 Ethernet", 546 }, 547 { PCI_VENDOR_BROADCOM, 548 PCI_PRODUCT_BROADCOM_BCM5785G, 549 "BCM5785G NetLink 1000baseT Ethernet", 550 }, 551 { PCI_VENDOR_BROADCOM, 552 PCI_PRODUCT_BROADCOM_BCM5786, 553 "Broadcom BCM5786 Gigabit Ethernet", 554 }, 555 { PCI_VENDOR_BROADCOM, 556 PCI_PRODUCT_BROADCOM_BCM5787, 557 "Broadcom BCM5787 Gigabit Ethernet", 558 }, 559 { PCI_VENDOR_BROADCOM, 560 PCI_PRODUCT_BROADCOM_BCM5787F, 561 "Broadcom BCM5787F 10/100 Ethernet", 562 }, 563 { PCI_VENDOR_BROADCOM, 564 PCI_PRODUCT_BROADCOM_BCM5787M, 565 "Broadcom BCM5787M Gigabit Ethernet", 566 }, 567 { PCI_VENDOR_BROADCOM, 568 PCI_PRODUCT_BROADCOM_BCM5788, 569 "Broadcom BCM5788 Gigabit Ethernet", 570 }, 571 { PCI_VENDOR_BROADCOM, 572 PCI_PRODUCT_BROADCOM_BCM5789, 573 "Broadcom BCM5789 Gigabit Ethernet", 574 }, 575 { PCI_VENDOR_BROADCOM, 576 PCI_PRODUCT_BROADCOM_BCM5901, 577 "Broadcom BCM5901 Fast Ethernet", 578 }, 579 { PCI_VENDOR_BROADCOM, 580 PCI_PRODUCT_BROADCOM_BCM5901A2, 581 "Broadcom BCM5901A2 Fast Ethernet", 582 }, 583 { PCI_VENDOR_BROADCOM, 584 PCI_PRODUCT_BROADCOM_BCM5903M, 585 "Broadcom BCM5903M Fast Ethernet", 586 }, 587 { PCI_VENDOR_BROADCOM, 588 PCI_PRODUCT_BROADCOM_BCM5906, 589 "Broadcom BCM5906 Fast Ethernet", 590 }, 591 { PCI_VENDOR_BROADCOM, 592 PCI_PRODUCT_BROADCOM_BCM5906M, 593 "Broadcom BCM5906M Fast Ethernet", 594 }, 595 { PCI_VENDOR_BROADCOM, 596 PCI_PRODUCT_BROADCOM_BCM57760, 597 "Broadcom BCM57760 Fast Ethernet", 598 }, 599 { PCI_VENDOR_BROADCOM, 600 PCI_PRODUCT_BROADCOM_BCM57761, 601 "Broadcom BCM57761 Fast Ethernet", 602 }, 603 { PCI_VENDOR_BROADCOM, 604 PCI_PRODUCT_BROADCOM_BCM57762, 605 "Broadcom BCM57762 Gigabit Ethernet", 606 }, 607 { PCI_VENDOR_BROADCOM, 608 PCI_PRODUCT_BROADCOM_BCM57765, 609 "Broadcom BCM57765 Fast Ethernet", 610 }, 611 { PCI_VENDOR_BROADCOM, 612 PCI_PRODUCT_BROADCOM_BCM57766, 613 "Broadcom BCM57766 Fast Ethernet", 614 }, 615 { PCI_VENDOR_BROADCOM, 616 PCI_PRODUCT_BROADCOM_BCM57780, 617 "Broadcom BCM57780 Fast Ethernet", 618 }, 619 { PCI_VENDOR_BROADCOM, 620 PCI_PRODUCT_BROADCOM_BCM57781, 621 "Broadcom BCM57781 Fast Ethernet", 622 }, 623 { PCI_VENDOR_BROADCOM, 624 PCI_PRODUCT_BROADCOM_BCM57782, 625 "Broadcom BCM57782 Fast Ethernet", 626 }, 627 { PCI_VENDOR_BROADCOM, 628 PCI_PRODUCT_BROADCOM_BCM57785, 629 "Broadcom BCM57785 Fast Ethernet", 630 }, 631 { PCI_VENDOR_BROADCOM, 632 PCI_PRODUCT_BROADCOM_BCM57786, 633 "Broadcom BCM57786 Fast Ethernet", 634 }, 635 { PCI_VENDOR_BROADCOM, 636 PCI_PRODUCT_BROADCOM_BCM57788, 637 "Broadcom BCM57788 Fast Ethernet", 638 }, 639 { PCI_VENDOR_BROADCOM, 640 PCI_PRODUCT_BROADCOM_BCM57790, 641 "Broadcom BCM57790 Fast Ethernet", 642 }, 643 { PCI_VENDOR_BROADCOM, 644 PCI_PRODUCT_BROADCOM_BCM57791, 645 "Broadcom BCM57791 Fast Ethernet", 646 }, 647 { PCI_VENDOR_BROADCOM, 648 PCI_PRODUCT_BROADCOM_BCM57795, 649 "Broadcom BCM57795 Fast Ethernet", 650 }, 651 { PCI_VENDOR_SCHNEIDERKOCH, 652 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 653 "SysKonnect SK-9Dx1 Gigabit Ethernet", 654 }, 655 { PCI_VENDOR_3COM, 656 PCI_PRODUCT_3COM_3C996, 657 "3Com 3c996 Gigabit Ethernet", 658 }, 659 { PCI_VENDOR_FUJITSU4, 660 PCI_PRODUCT_FUJITSU4_PW008GE4, 661 "Fujitsu PW008GE4 Gigabit Ethernet", 662 }, 663 { PCI_VENDOR_FUJITSU4, 664 PCI_PRODUCT_FUJITSU4_PW008GE5, 665 "Fujitsu PW008GE5 Gigabit Ethernet", 666 }, 667 { PCI_VENDOR_FUJITSU4, 668 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 669 "Fujitsu Primepower 250/450 Gigabit Ethernet", 670 }, 671 { 0, 672 0, 673 NULL }, 674 }; 675 676 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 677 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 678 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 679 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 680 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 681 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 683 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 684 685 static const struct bge_revision { 686 uint32_t br_chipid; 687 const char *br_name; 688 } bge_revisions[] = { 689 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 690 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 691 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 692 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 693 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 694 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 695 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 696 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 697 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 698 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 699 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 700 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 701 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 702 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 703 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 704 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 705 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 706 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 707 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 708 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 709 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 710 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 711 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 712 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 713 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 714 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 715 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 716 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 717 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 718 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 719 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 720 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 721 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 722 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 723 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 724 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 725 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 726 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 727 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 728 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 729 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 730 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 731 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 732 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 733 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 734 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 735 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 736 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 737 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 738 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 739 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 740 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 741 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 742 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 743 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 744 /* 5754 and 5787 share the same ASIC ID */ 745 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 746 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 747 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 748 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 749 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 750 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 751 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 752 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 753 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 754 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 755 756 { 0, NULL } 757 }; 758 759 /* 760 * Some defaults for major revisions, so that newer steppings 761 * that we don't know about have a shot at working. 762 */ 763 static const struct bge_revision bge_majorrevs[] = { 764 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 765 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 766 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 767 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 768 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 769 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 770 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 772 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 773 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 774 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 775 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 776 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 777 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 778 /* 5754 and 5787 share the same ASIC ID */ 779 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 780 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 781 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 782 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 783 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 784 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 785 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 786 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 787 788 { 0, NULL } 789 }; 790 791 static int bge_allow_asf = 1; 792 793 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 794 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 795 796 static uint32_t 797 bge_readmem_ind(struct bge_softc *sc, int off) 798 { 799 pcireg_t val; 800 801 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 802 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 803 return 0; 804 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 806 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 807 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 808 return val; 809 } 810 811 static void 812 bge_writemem_ind(struct bge_softc *sc, int off, int val) 813 { 814 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 817 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 818 } 819 820 /* 821 * PCI Express only 822 */ 823 static void 824 bge_set_max_readrq(struct bge_softc *sc) 825 { 826 pcireg_t val; 827 828 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 829 + PCI_PCIE_DCSR); 830 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 831 switch (sc->bge_expmrq) { 832 case 2048: 833 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 834 break; 835 case 4096: 836 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 837 break; 838 default: 839 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 840 break; 841 } 842 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 843 + PCI_PCIE_DCSR, val); 844 } 845 846 #ifdef notdef 847 static uint32_t 848 bge_readreg_ind(struct bge_softc *sc, int off) 849 { 850 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 851 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 852 } 853 #endif 854 855 static void 856 bge_writereg_ind(struct bge_softc *sc, int off, int val) 857 { 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 859 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 860 } 861 862 static void 863 bge_writemem_direct(struct bge_softc *sc, int off, int val) 864 { 865 CSR_WRITE_4(sc, off, val); 866 } 867 868 static void 869 bge_writembx(struct bge_softc *sc, int off, int val) 870 { 871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 872 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 873 874 CSR_WRITE_4(sc, off, val); 875 } 876 877 static void 878 bge_writembx_flush(struct bge_softc *sc, int off, int val) 879 { 880 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 881 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 882 883 CSR_WRITE_4_FLUSH(sc, off, val); 884 } 885 886 /* 887 * Clear all stale locks and select the lock for this driver instance. 888 */ 889 void 890 bge_ape_lock_init(struct bge_softc *sc) 891 { 892 struct pci_attach_args *pa = &(sc->bge_pa); 893 uint32_t bit, regbase; 894 int i; 895 896 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 897 regbase = BGE_APE_LOCK_GRANT; 898 else 899 regbase = BGE_APE_PER_LOCK_GRANT; 900 901 /* Clear any stale locks. */ 902 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 903 switch (i) { 904 case BGE_APE_LOCK_PHY0: 905 case BGE_APE_LOCK_PHY1: 906 case BGE_APE_LOCK_PHY2: 907 case BGE_APE_LOCK_PHY3: 908 bit = BGE_APE_LOCK_GRANT_DRIVER0; 909 break; 910 default: 911 if (pa->pa_function != 0) 912 bit = BGE_APE_LOCK_GRANT_DRIVER0; 913 else 914 bit = (1 << pa->pa_function); 915 } 916 APE_WRITE_4(sc, regbase + 4 * i, bit); 917 } 918 919 /* Select the PHY lock based on the device's function number. */ 920 switch (pa->pa_function) { 921 case 0: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 923 break; 924 case 1: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 926 break; 927 case 2: 928 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 929 break; 930 case 3: 931 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 932 break; 933 default: 934 printf("%s: PHY lock not supported on function\n", 935 device_xname(sc->bge_dev)); 936 break; 937 } 938 } 939 940 /* 941 * Check for APE firmware, set flags, and print version info. 942 */ 943 void 944 bge_ape_read_fw_ver(struct bge_softc *sc) 945 { 946 const char *fwtype; 947 uint32_t apedata, features; 948 949 /* Check for a valid APE signature in shared memory. */ 950 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 951 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 952 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 953 return; 954 } 955 956 /* Check if APE firmware is running. */ 957 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 958 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 959 printf("%s: APE signature found but FW status not ready! " 960 "0x%08x\n", device_xname(sc->bge_dev), apedata); 961 return; 962 } 963 964 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 965 966 /* Fetch the APE firwmare type and version. */ 967 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 968 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 969 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 970 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 971 fwtype = "NCSI"; 972 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 973 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 974 fwtype = "DASH"; 975 } else 976 fwtype = "UNKN"; 977 978 /* Print the APE firmware version. */ 979 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 980 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 981 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 982 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 983 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 984 } 985 986 int 987 bge_ape_lock(struct bge_softc *sc, int locknum) 988 { 989 struct pci_attach_args *pa = &(sc->bge_pa); 990 uint32_t bit, gnt, req, status; 991 int i, off; 992 993 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 994 return (0); 995 996 /* Lock request/grant registers have different bases. */ 997 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 998 req = BGE_APE_LOCK_REQ; 999 gnt = BGE_APE_LOCK_GRANT; 1000 } else { 1001 req = BGE_APE_PER_LOCK_REQ; 1002 gnt = BGE_APE_PER_LOCK_GRANT; 1003 } 1004 1005 off = 4 * locknum; 1006 1007 switch (locknum) { 1008 case BGE_APE_LOCK_GPIO: 1009 /* Lock required when using GPIO. */ 1010 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1011 return (0); 1012 if (pa->pa_function == 0) 1013 bit = BGE_APE_LOCK_REQ_DRIVER0; 1014 else 1015 bit = (1 << pa->pa_function); 1016 break; 1017 case BGE_APE_LOCK_GRC: 1018 /* Lock required to reset the device. */ 1019 if (pa->pa_function == 0) 1020 bit = BGE_APE_LOCK_REQ_DRIVER0; 1021 else 1022 bit = (1 << pa->pa_function); 1023 break; 1024 case BGE_APE_LOCK_MEM: 1025 /* Lock required when accessing certain APE memory. */ 1026 if (pa->pa_function == 0) 1027 bit = BGE_APE_LOCK_REQ_DRIVER0; 1028 else 1029 bit = (1 << pa->pa_function); 1030 break; 1031 case BGE_APE_LOCK_PHY0: 1032 case BGE_APE_LOCK_PHY1: 1033 case BGE_APE_LOCK_PHY2: 1034 case BGE_APE_LOCK_PHY3: 1035 /* Lock required when accessing PHYs. */ 1036 bit = BGE_APE_LOCK_REQ_DRIVER0; 1037 break; 1038 default: 1039 return (EINVAL); 1040 } 1041 1042 /* Request a lock. */ 1043 APE_WRITE_4_FLUSH(sc, req + off, bit); 1044 1045 /* Wait up to 1 second to acquire lock. */ 1046 for (i = 0; i < 20000; i++) { 1047 status = APE_READ_4(sc, gnt + off); 1048 if (status == bit) 1049 break; 1050 DELAY(50); 1051 } 1052 1053 /* Handle any errors. */ 1054 if (status != bit) { 1055 printf("%s: APE lock %d request failed! " 1056 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1057 device_xname(sc->bge_dev), 1058 locknum, req + off, bit & 0xFFFF, gnt + off, 1059 status & 0xFFFF); 1060 /* Revoke the lock request. */ 1061 APE_WRITE_4(sc, gnt + off, bit); 1062 return (EBUSY); 1063 } 1064 1065 return (0); 1066 } 1067 1068 void 1069 bge_ape_unlock(struct bge_softc *sc, int locknum) 1070 { 1071 struct pci_attach_args *pa = &(sc->bge_pa); 1072 uint32_t bit, gnt; 1073 int off; 1074 1075 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1076 return; 1077 1078 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1079 gnt = BGE_APE_LOCK_GRANT; 1080 else 1081 gnt = BGE_APE_PER_LOCK_GRANT; 1082 1083 off = 4 * locknum; 1084 1085 switch (locknum) { 1086 case BGE_APE_LOCK_GPIO: 1087 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1088 return; 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_GRC: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_MEM: 1101 if (pa->pa_function == 0) 1102 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1103 else 1104 bit = (1 << pa->pa_function); 1105 break; 1106 case BGE_APE_LOCK_PHY0: 1107 case BGE_APE_LOCK_PHY1: 1108 case BGE_APE_LOCK_PHY2: 1109 case BGE_APE_LOCK_PHY3: 1110 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1111 break; 1112 default: 1113 return; 1114 } 1115 1116 /* Write and flush for consecutive bge_ape_lock() */ 1117 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1118 } 1119 1120 /* 1121 * Send an event to the APE firmware. 1122 */ 1123 void 1124 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1125 { 1126 uint32_t apedata; 1127 int i; 1128 1129 /* NCSI does not support APE events. */ 1130 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1131 return; 1132 1133 /* Wait up to 1ms for APE to service previous event. */ 1134 for (i = 10; i > 0; i--) { 1135 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1136 break; 1137 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1138 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1139 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1140 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1141 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1142 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1143 break; 1144 } 1145 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1146 DELAY(100); 1147 } 1148 if (i == 0) { 1149 printf("%s: APE event 0x%08x send timed out\n", 1150 device_xname(sc->bge_dev), event); 1151 } 1152 } 1153 1154 void 1155 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1156 { 1157 uint32_t apedata, event; 1158 1159 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1160 return; 1161 1162 switch (kind) { 1163 case BGE_RESET_START: 1164 /* If this is the first load, clear the load counter. */ 1165 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1166 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1167 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1168 else { 1169 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1170 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1171 } 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1173 BGE_APE_HOST_SEG_SIG_MAGIC); 1174 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1175 BGE_APE_HOST_SEG_LEN_MAGIC); 1176 1177 /* Add some version info if bge(4) supports it. */ 1178 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1179 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1180 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1181 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1182 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1183 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1184 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1185 BGE_APE_HOST_DRVR_STATE_START); 1186 event = BGE_APE_EVENT_STATUS_STATE_START; 1187 break; 1188 case BGE_RESET_SHUTDOWN: 1189 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1190 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1191 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1192 break; 1193 case BGE_RESET_SUSPEND: 1194 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1195 break; 1196 default: 1197 return; 1198 } 1199 1200 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1201 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1202 } 1203 1204 static uint8_t 1205 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1206 { 1207 uint32_t access, byte = 0; 1208 int i; 1209 1210 /* Lock. */ 1211 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1212 for (i = 0; i < 8000; i++) { 1213 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1214 break; 1215 DELAY(20); 1216 } 1217 if (i == 8000) 1218 return 1; 1219 1220 /* Enable access. */ 1221 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1222 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1223 1224 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1225 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1226 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1227 DELAY(10); 1228 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1229 DELAY(10); 1230 break; 1231 } 1232 } 1233 1234 if (i == BGE_TIMEOUT * 10) { 1235 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1236 return 1; 1237 } 1238 1239 /* Get result. */ 1240 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1241 1242 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1243 1244 /* Disable access. */ 1245 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1246 1247 /* Unlock. */ 1248 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1249 1250 return 0; 1251 } 1252 1253 /* 1254 * Read a sequence of bytes from NVRAM. 1255 */ 1256 static int 1257 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1258 { 1259 int error = 0, i; 1260 uint8_t byte = 0; 1261 1262 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1263 return 1; 1264 1265 for (i = 0; i < cnt; i++) { 1266 error = bge_nvram_getbyte(sc, off + i, &byte); 1267 if (error) 1268 break; 1269 *(dest + i) = byte; 1270 } 1271 1272 return (error ? 1 : 0); 1273 } 1274 1275 /* 1276 * Read a byte of data stored in the EEPROM at address 'addr.' The 1277 * BCM570x supports both the traditional bitbang interface and an 1278 * auto access interface for reading the EEPROM. We use the auto 1279 * access method. 1280 */ 1281 static uint8_t 1282 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1283 { 1284 int i; 1285 uint32_t byte = 0; 1286 1287 /* 1288 * Enable use of auto EEPROM access so we can avoid 1289 * having to use the bitbang method. 1290 */ 1291 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1292 1293 /* Reset the EEPROM, load the clock period. */ 1294 CSR_WRITE_4(sc, BGE_EE_ADDR, 1295 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1296 DELAY(20); 1297 1298 /* Issue the read EEPROM command. */ 1299 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1300 1301 /* Wait for completion */ 1302 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1303 DELAY(10); 1304 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1305 break; 1306 } 1307 1308 if (i == BGE_TIMEOUT * 10) { 1309 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1310 return 1; 1311 } 1312 1313 /* Get result. */ 1314 byte = CSR_READ_4(sc, BGE_EE_DATA); 1315 1316 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1317 1318 return 0; 1319 } 1320 1321 /* 1322 * Read a sequence of bytes from the EEPROM. 1323 */ 1324 static int 1325 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1326 { 1327 int error = 0, i; 1328 uint8_t byte = 0; 1329 char *dest = destv; 1330 1331 for (i = 0; i < cnt; i++) { 1332 error = bge_eeprom_getbyte(sc, off + i, &byte); 1333 if (error) 1334 break; 1335 *(dest + i) = byte; 1336 } 1337 1338 return (error ? 1 : 0); 1339 } 1340 1341 static int 1342 bge_miibus_readreg(device_t dev, int phy, int reg) 1343 { 1344 struct bge_softc *sc = device_private(dev); 1345 uint32_t val; 1346 uint32_t autopoll; 1347 int i; 1348 1349 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1350 return 0; 1351 1352 /* Reading with autopolling on may trigger PCI errors */ 1353 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1354 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1355 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1356 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1357 DELAY(80); 1358 } 1359 1360 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1361 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1362 1363 for (i = 0; i < BGE_TIMEOUT; i++) { 1364 delay(10); 1365 val = CSR_READ_4(sc, BGE_MI_COMM); 1366 if (!(val & BGE_MICOMM_BUSY)) { 1367 DELAY(5); 1368 val = CSR_READ_4(sc, BGE_MI_COMM); 1369 break; 1370 } 1371 } 1372 1373 if (i == BGE_TIMEOUT) { 1374 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1375 val = 0; 1376 goto done; 1377 } 1378 1379 done: 1380 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1381 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1382 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1383 DELAY(80); 1384 } 1385 1386 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1387 1388 if (val & BGE_MICOMM_READFAIL) 1389 return 0; 1390 1391 return (val & 0xFFFF); 1392 } 1393 1394 static void 1395 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1396 { 1397 struct bge_softc *sc = device_private(dev); 1398 uint32_t autopoll; 1399 int i; 1400 1401 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1402 return; 1403 1404 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1405 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1406 return; 1407 1408 /* Reading with autopolling on may trigger PCI errors */ 1409 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1410 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1411 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1412 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1413 DELAY(80); 1414 } 1415 1416 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1417 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1418 1419 for (i = 0; i < BGE_TIMEOUT; i++) { 1420 delay(10); 1421 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1422 delay(5); 1423 CSR_READ_4(sc, BGE_MI_COMM); 1424 break; 1425 } 1426 } 1427 1428 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1429 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1430 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1431 delay(80); 1432 } 1433 1434 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1435 1436 if (i == BGE_TIMEOUT) 1437 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1438 } 1439 1440 static void 1441 bge_miibus_statchg(struct ifnet *ifp) 1442 { 1443 struct bge_softc *sc = ifp->if_softc; 1444 struct mii_data *mii = &sc->bge_mii; 1445 uint32_t mac_mode, rx_mode, tx_mode; 1446 1447 /* 1448 * Get flow control negotiation result. 1449 */ 1450 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1451 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1452 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1453 mii->mii_media_active &= ~IFM_ETH_FMASK; 1454 } 1455 1456 /* Set the port mode (MII/GMII) to match the link speed. */ 1457 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1458 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1459 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1460 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1461 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1462 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1463 mac_mode |= BGE_PORTMODE_GMII; 1464 else 1465 mac_mode |= BGE_PORTMODE_MII; 1466 1467 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1468 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1469 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1470 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1471 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1472 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1473 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1474 } else 1475 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1476 1477 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1478 DELAY(40); 1479 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1480 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1481 } 1482 1483 /* 1484 * Update rx threshold levels to values in a particular slot 1485 * of the interrupt-mitigation table bge_rx_threshes. 1486 */ 1487 static void 1488 bge_set_thresh(struct ifnet *ifp, int lvl) 1489 { 1490 struct bge_softc *sc = ifp->if_softc; 1491 int s; 1492 1493 /* For now, just save the new Rx-intr thresholds and record 1494 * that a threshold update is pending. Updating the hardware 1495 * registers here (even at splhigh()) is observed to 1496 * occasionaly cause glitches where Rx-interrupts are not 1497 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1498 */ 1499 s = splnet(); 1500 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1501 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1502 sc->bge_pending_rxintr_change = 1; 1503 splx(s); 1504 } 1505 1506 1507 /* 1508 * Update Rx thresholds of all bge devices 1509 */ 1510 static void 1511 bge_update_all_threshes(int lvl) 1512 { 1513 struct ifnet *ifp; 1514 const char * const namebuf = "bge"; 1515 int namelen; 1516 1517 if (lvl < 0) 1518 lvl = 0; 1519 else if (lvl >= NBGE_RX_THRESH) 1520 lvl = NBGE_RX_THRESH - 1; 1521 1522 namelen = strlen(namebuf); 1523 /* 1524 * Now search all the interfaces for this name/number 1525 */ 1526 IFNET_FOREACH(ifp) { 1527 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1528 continue; 1529 /* We got a match: update if doing auto-threshold-tuning */ 1530 if (bge_auto_thresh) 1531 bge_set_thresh(ifp, lvl); 1532 } 1533 } 1534 1535 /* 1536 * Handle events that have triggered interrupts. 1537 */ 1538 static void 1539 bge_handle_events(struct bge_softc *sc) 1540 { 1541 1542 return; 1543 } 1544 1545 /* 1546 * Memory management for jumbo frames. 1547 */ 1548 1549 static int 1550 bge_alloc_jumbo_mem(struct bge_softc *sc) 1551 { 1552 char *ptr, *kva; 1553 bus_dma_segment_t seg; 1554 int i, rseg, state, error; 1555 struct bge_jpool_entry *entry; 1556 1557 state = error = 0; 1558 1559 /* Grab a big chunk o' storage. */ 1560 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1561 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1562 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1563 return ENOBUFS; 1564 } 1565 1566 state = 1; 1567 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1568 BUS_DMA_NOWAIT)) { 1569 aprint_error_dev(sc->bge_dev, 1570 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1571 error = ENOBUFS; 1572 goto out; 1573 } 1574 1575 state = 2; 1576 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1577 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1578 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1579 error = ENOBUFS; 1580 goto out; 1581 } 1582 1583 state = 3; 1584 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1585 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1586 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1587 error = ENOBUFS; 1588 goto out; 1589 } 1590 1591 state = 4; 1592 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1593 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1594 1595 SLIST_INIT(&sc->bge_jfree_listhead); 1596 SLIST_INIT(&sc->bge_jinuse_listhead); 1597 1598 /* 1599 * Now divide it up into 9K pieces and save the addresses 1600 * in an array. 1601 */ 1602 ptr = sc->bge_cdata.bge_jumbo_buf; 1603 for (i = 0; i < BGE_JSLOTS; i++) { 1604 sc->bge_cdata.bge_jslots[i] = ptr; 1605 ptr += BGE_JLEN; 1606 entry = malloc(sizeof(struct bge_jpool_entry), 1607 M_DEVBUF, M_NOWAIT); 1608 if (entry == NULL) { 1609 aprint_error_dev(sc->bge_dev, 1610 "no memory for jumbo buffer queue!\n"); 1611 error = ENOBUFS; 1612 goto out; 1613 } 1614 entry->slot = i; 1615 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1616 entry, jpool_entries); 1617 } 1618 out: 1619 if (error != 0) { 1620 switch (state) { 1621 case 4: 1622 bus_dmamap_unload(sc->bge_dmatag, 1623 sc->bge_cdata.bge_rx_jumbo_map); 1624 case 3: 1625 bus_dmamap_destroy(sc->bge_dmatag, 1626 sc->bge_cdata.bge_rx_jumbo_map); 1627 case 2: 1628 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1629 case 1: 1630 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1631 break; 1632 default: 1633 break; 1634 } 1635 } 1636 1637 return error; 1638 } 1639 1640 /* 1641 * Allocate a jumbo buffer. 1642 */ 1643 static void * 1644 bge_jalloc(struct bge_softc *sc) 1645 { 1646 struct bge_jpool_entry *entry; 1647 1648 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1649 1650 if (entry == NULL) { 1651 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1652 return NULL; 1653 } 1654 1655 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1656 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1657 return (sc->bge_cdata.bge_jslots[entry->slot]); 1658 } 1659 1660 /* 1661 * Release a jumbo buffer. 1662 */ 1663 static void 1664 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1665 { 1666 struct bge_jpool_entry *entry; 1667 struct bge_softc *sc; 1668 int i, s; 1669 1670 /* Extract the softc struct pointer. */ 1671 sc = (struct bge_softc *)arg; 1672 1673 if (sc == NULL) 1674 panic("bge_jfree: can't find softc pointer!"); 1675 1676 /* calculate the slot this buffer belongs to */ 1677 1678 i = ((char *)buf 1679 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1680 1681 if ((i < 0) || (i >= BGE_JSLOTS)) 1682 panic("bge_jfree: asked to free buffer that we don't manage!"); 1683 1684 s = splvm(); 1685 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1686 if (entry == NULL) 1687 panic("bge_jfree: buffer not in use!"); 1688 entry->slot = i; 1689 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1690 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1691 1692 if (__predict_true(m != NULL)) 1693 pool_cache_put(mb_cache, m); 1694 splx(s); 1695 } 1696 1697 1698 /* 1699 * Initialize a standard receive ring descriptor. 1700 */ 1701 static int 1702 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1703 bus_dmamap_t dmamap) 1704 { 1705 struct mbuf *m_new = NULL; 1706 struct bge_rx_bd *r; 1707 int error; 1708 1709 if (dmamap == NULL) { 1710 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1711 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1712 if (error != 0) 1713 return error; 1714 } 1715 1716 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1717 1718 if (m == NULL) { 1719 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1720 if (m_new == NULL) 1721 return ENOBUFS; 1722 1723 MCLGET(m_new, M_DONTWAIT); 1724 if (!(m_new->m_flags & M_EXT)) { 1725 m_freem(m_new); 1726 return ENOBUFS; 1727 } 1728 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1729 1730 } else { 1731 m_new = m; 1732 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1733 m_new->m_data = m_new->m_ext.ext_buf; 1734 } 1735 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1736 m_adj(m_new, ETHER_ALIGN); 1737 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1738 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1739 return ENOBUFS; 1740 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1741 BUS_DMASYNC_PREREAD); 1742 1743 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1744 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1745 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1746 r->bge_flags = BGE_RXBDFLAG_END; 1747 r->bge_len = m_new->m_len; 1748 r->bge_idx = i; 1749 1750 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1751 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1752 i * sizeof (struct bge_rx_bd), 1753 sizeof (struct bge_rx_bd), 1754 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1755 1756 return 0; 1757 } 1758 1759 /* 1760 * Initialize a jumbo receive ring descriptor. This allocates 1761 * a jumbo buffer from the pool managed internally by the driver. 1762 */ 1763 static int 1764 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1765 { 1766 struct mbuf *m_new = NULL; 1767 struct bge_rx_bd *r; 1768 void *buf = NULL; 1769 1770 if (m == NULL) { 1771 1772 /* Allocate the mbuf. */ 1773 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1774 if (m_new == NULL) 1775 return ENOBUFS; 1776 1777 /* Allocate the jumbo buffer */ 1778 buf = bge_jalloc(sc); 1779 if (buf == NULL) { 1780 m_freem(m_new); 1781 aprint_error_dev(sc->bge_dev, 1782 "jumbo allocation failed -- packet dropped!\n"); 1783 return ENOBUFS; 1784 } 1785 1786 /* Attach the buffer to the mbuf. */ 1787 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1788 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1789 bge_jfree, sc); 1790 m_new->m_flags |= M_EXT_RW; 1791 } else { 1792 m_new = m; 1793 buf = m_new->m_data = m_new->m_ext.ext_buf; 1794 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1795 } 1796 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1797 m_adj(m_new, ETHER_ALIGN); 1798 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1799 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1800 BUS_DMASYNC_PREREAD); 1801 /* Set up the descriptor. */ 1802 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1803 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1804 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1805 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1806 r->bge_len = m_new->m_len; 1807 r->bge_idx = i; 1808 1809 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1810 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1811 i * sizeof (struct bge_rx_bd), 1812 sizeof (struct bge_rx_bd), 1813 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1814 1815 return 0; 1816 } 1817 1818 /* 1819 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1820 * that's 1MB or memory, which is a lot. For now, we fill only the first 1821 * 256 ring entries and hope that our CPU is fast enough to keep up with 1822 * the NIC. 1823 */ 1824 static int 1825 bge_init_rx_ring_std(struct bge_softc *sc) 1826 { 1827 int i; 1828 1829 if (sc->bge_flags & BGE_RXRING_VALID) 1830 return 0; 1831 1832 for (i = 0; i < BGE_SSLOTS; i++) { 1833 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1834 return ENOBUFS; 1835 } 1836 1837 sc->bge_std = i - 1; 1838 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1839 1840 sc->bge_flags |= BGE_RXRING_VALID; 1841 1842 return 0; 1843 } 1844 1845 static void 1846 bge_free_rx_ring_std(struct bge_softc *sc) 1847 { 1848 int i; 1849 1850 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1851 return; 1852 1853 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1854 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1855 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1856 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1857 bus_dmamap_destroy(sc->bge_dmatag, 1858 sc->bge_cdata.bge_rx_std_map[i]); 1859 } 1860 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1861 sizeof(struct bge_rx_bd)); 1862 } 1863 1864 sc->bge_flags &= ~BGE_RXRING_VALID; 1865 } 1866 1867 static int 1868 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1869 { 1870 int i; 1871 volatile struct bge_rcb *rcb; 1872 1873 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1874 return 0; 1875 1876 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1877 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1878 return ENOBUFS; 1879 } 1880 1881 sc->bge_jumbo = i - 1; 1882 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1883 1884 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1885 rcb->bge_maxlen_flags = 0; 1886 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1887 1888 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1889 1890 return 0; 1891 } 1892 1893 static void 1894 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1895 { 1896 int i; 1897 1898 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1899 return; 1900 1901 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1902 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1903 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1904 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1905 } 1906 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1907 sizeof(struct bge_rx_bd)); 1908 } 1909 1910 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1911 } 1912 1913 static void 1914 bge_free_tx_ring(struct bge_softc *sc) 1915 { 1916 int i; 1917 struct txdmamap_pool_entry *dma; 1918 1919 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1920 return; 1921 1922 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1923 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1924 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1925 sc->bge_cdata.bge_tx_chain[i] = NULL; 1926 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1927 link); 1928 sc->txdma[i] = 0; 1929 } 1930 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1931 sizeof(struct bge_tx_bd)); 1932 } 1933 1934 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1935 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1936 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1937 free(dma, M_DEVBUF); 1938 } 1939 1940 sc->bge_flags &= ~BGE_TXRING_VALID; 1941 } 1942 1943 static int 1944 bge_init_tx_ring(struct bge_softc *sc) 1945 { 1946 int i; 1947 bus_dmamap_t dmamap; 1948 struct txdmamap_pool_entry *dma; 1949 1950 if (sc->bge_flags & BGE_TXRING_VALID) 1951 return 0; 1952 1953 sc->bge_txcnt = 0; 1954 sc->bge_tx_saved_considx = 0; 1955 1956 /* Initialize transmit producer index for host-memory send ring. */ 1957 sc->bge_tx_prodidx = 0; 1958 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1959 /* 5700 b2 errata */ 1960 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1961 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1962 1963 /* NIC-memory send ring not used; initialize to zero. */ 1964 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1965 /* 5700 b2 errata */ 1966 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1967 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1968 1969 SLIST_INIT(&sc->txdma_list); 1970 for (i = 0; i < BGE_RSLOTS; i++) { 1971 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1972 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1973 &dmamap)) 1974 return ENOBUFS; 1975 if (dmamap == NULL) 1976 panic("dmamap NULL in bge_init_tx_ring"); 1977 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1978 if (dma == NULL) { 1979 aprint_error_dev(sc->bge_dev, 1980 "can't alloc txdmamap_pool_entry\n"); 1981 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1982 return ENOMEM; 1983 } 1984 dma->dmamap = dmamap; 1985 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1986 } 1987 1988 sc->bge_flags |= BGE_TXRING_VALID; 1989 1990 return 0; 1991 } 1992 1993 static void 1994 bge_setmulti(struct bge_softc *sc) 1995 { 1996 struct ethercom *ac = &sc->ethercom; 1997 struct ifnet *ifp = &ac->ec_if; 1998 struct ether_multi *enm; 1999 struct ether_multistep step; 2000 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2001 uint32_t h; 2002 int i; 2003 2004 if (ifp->if_flags & IFF_PROMISC) 2005 goto allmulti; 2006 2007 /* Now program new ones. */ 2008 ETHER_FIRST_MULTI(step, ac, enm); 2009 while (enm != NULL) { 2010 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2011 /* 2012 * We must listen to a range of multicast addresses. 2013 * For now, just accept all multicasts, rather than 2014 * trying to set only those filter bits needed to match 2015 * the range. (At this time, the only use of address 2016 * ranges is for IP multicast routing, for which the 2017 * range is big enough to require all bits set.) 2018 */ 2019 goto allmulti; 2020 } 2021 2022 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2023 2024 /* Just want the 7 least-significant bits. */ 2025 h &= 0x7f; 2026 2027 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2028 ETHER_NEXT_MULTI(step, enm); 2029 } 2030 2031 ifp->if_flags &= ~IFF_ALLMULTI; 2032 goto setit; 2033 2034 allmulti: 2035 ifp->if_flags |= IFF_ALLMULTI; 2036 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2037 2038 setit: 2039 for (i = 0; i < 4; i++) 2040 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2041 } 2042 2043 static void 2044 bge_sig_pre_reset(struct bge_softc *sc, int type) 2045 { 2046 2047 /* 2048 * Some chips don't like this so only do this if ASF is enabled 2049 */ 2050 if (sc->bge_asf_mode) 2051 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2052 2053 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2054 switch (type) { 2055 case BGE_RESET_START: 2056 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2057 BGE_FW_DRV_STATE_START); 2058 break; 2059 case BGE_RESET_SHUTDOWN: 2060 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2061 BGE_FW_DRV_STATE_UNLOAD); 2062 break; 2063 case BGE_RESET_SUSPEND: 2064 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2065 BGE_FW_DRV_STATE_SUSPEND); 2066 break; 2067 } 2068 } 2069 2070 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2071 bge_ape_driver_state_change(sc, type); 2072 } 2073 2074 static void 2075 bge_sig_post_reset(struct bge_softc *sc, int type) 2076 { 2077 2078 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2079 switch (type) { 2080 case BGE_RESET_START: 2081 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2082 BGE_FW_DRV_STATE_START_DONE); 2083 /* START DONE */ 2084 break; 2085 case BGE_RESET_SHUTDOWN: 2086 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2087 BGE_FW_DRV_STATE_UNLOAD_DONE); 2088 break; 2089 } 2090 } 2091 2092 if (type == BGE_RESET_SHUTDOWN) 2093 bge_ape_driver_state_change(sc, type); 2094 } 2095 2096 static void 2097 bge_sig_legacy(struct bge_softc *sc, int type) 2098 { 2099 2100 if (sc->bge_asf_mode) { 2101 switch (type) { 2102 case BGE_RESET_START: 2103 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2104 BGE_FW_DRV_STATE_START); 2105 break; 2106 case BGE_RESET_SHUTDOWN: 2107 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2108 BGE_FW_DRV_STATE_UNLOAD); 2109 break; 2110 } 2111 } 2112 } 2113 2114 static void 2115 bge_wait_for_event_ack(struct bge_softc *sc) 2116 { 2117 int i; 2118 2119 /* wait up to 2500usec */ 2120 for (i = 0; i < 250; i++) { 2121 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2122 BGE_RX_CPU_DRV_EVENT)) 2123 break; 2124 DELAY(10); 2125 } 2126 } 2127 2128 static void 2129 bge_stop_fw(struct bge_softc *sc) 2130 { 2131 2132 if (sc->bge_asf_mode) { 2133 bge_wait_for_event_ack(sc); 2134 2135 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2136 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2137 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2138 2139 bge_wait_for_event_ack(sc); 2140 } 2141 } 2142 2143 static int 2144 bge_poll_fw(struct bge_softc *sc) 2145 { 2146 uint32_t val; 2147 int i; 2148 2149 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2150 for (i = 0; i < BGE_TIMEOUT; i++) { 2151 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2152 if (val & BGE_VCPU_STATUS_INIT_DONE) 2153 break; 2154 DELAY(100); 2155 } 2156 if (i >= BGE_TIMEOUT) { 2157 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2158 return -1; 2159 } 2160 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2161 /* 2162 * Poll the value location we just wrote until 2163 * we see the 1's complement of the magic number. 2164 * This indicates that the firmware initialization 2165 * is complete. 2166 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2167 */ 2168 for (i = 0; i < BGE_TIMEOUT; i++) { 2169 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2170 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2171 break; 2172 DELAY(10); 2173 } 2174 2175 if (i >= BGE_TIMEOUT) { 2176 aprint_error_dev(sc->bge_dev, 2177 "firmware handshake timed out, val = %x\n", val); 2178 return -1; 2179 } 2180 } 2181 2182 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2183 /* tg3 says we have to wait extra time */ 2184 delay(10 * 1000); 2185 } 2186 2187 return 0; 2188 } 2189 2190 int 2191 bge_phy_addr(struct bge_softc *sc) 2192 { 2193 struct pci_attach_args *pa = &(sc->bge_pa); 2194 int phy_addr = 1; 2195 2196 /* 2197 * PHY address mapping for various devices. 2198 * 2199 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2200 * ---------+-------+-------+-------+-------+ 2201 * BCM57XX | 1 | X | X | X | 2202 * BCM5704 | 1 | X | 1 | X | 2203 * BCM5717 | 1 | 8 | 2 | 9 | 2204 * BCM5719 | 1 | 8 | 2 | 9 | 2205 * BCM5720 | 1 | 8 | 2 | 9 | 2206 * 2207 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2208 * ---------+-------+-------+-------+-------+ 2209 * BCM57XX | X | X | X | X | 2210 * BCM5704 | X | X | X | X | 2211 * BCM5717 | X | X | X | X | 2212 * BCM5719 | 3 | 10 | 4 | 11 | 2213 * BCM5720 | X | X | X | X | 2214 * 2215 * Other addresses may respond but they are not 2216 * IEEE compliant PHYs and should be ignored. 2217 */ 2218 switch (BGE_ASICREV(sc->bge_chipid)) { 2219 case BGE_ASICREV_BCM5717: 2220 case BGE_ASICREV_BCM5719: 2221 case BGE_ASICREV_BCM5720: 2222 phy_addr = pa->pa_function; 2223 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2224 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2225 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2226 } else { 2227 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2228 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2229 } 2230 } 2231 2232 return phy_addr; 2233 } 2234 2235 /* 2236 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2237 * self-test results. 2238 */ 2239 static int 2240 bge_chipinit(struct bge_softc *sc) 2241 { 2242 uint32_t dma_rw_ctl, mode_ctl, reg; 2243 int i; 2244 2245 /* Set endianness before we access any non-PCI registers. */ 2246 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2247 BGE_INIT); 2248 2249 /* 2250 * Clear the MAC statistics block in the NIC's 2251 * internal memory. 2252 */ 2253 for (i = BGE_STATS_BLOCK; 2254 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2255 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2256 2257 for (i = BGE_STATUS_BLOCK; 2258 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2259 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2260 2261 /* 5717 workaround from tg3 */ 2262 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2263 /* Save */ 2264 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2265 2266 /* Temporary modify MODE_CTL to control TLP */ 2267 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2268 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2269 2270 /* Control TLP */ 2271 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2272 BGE_TLP_PHYCTL1); 2273 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2274 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2275 2276 /* Restore */ 2277 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2278 } 2279 2280 /* XXX Should we use 57765_FAMILY? */ 2281 if (BGE_IS_57765_PLUS(sc)) { 2282 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2283 /* Save */ 2284 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2285 2286 /* Temporary modify MODE_CTL to control TLP */ 2287 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2288 CSR_WRITE_4(sc, BGE_MODE_CTL, 2289 reg | BGE_MODECTL_PCIE_TLPADDR1); 2290 2291 /* Control TLP */ 2292 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2293 BGE_TLP_PHYCTL5); 2294 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2295 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2296 2297 /* Restore */ 2298 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2299 } 2300 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2301 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2302 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2303 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2304 2305 /* Save */ 2306 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2307 2308 /* Temporary modify MODE_CTL to control TLP */ 2309 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2310 CSR_WRITE_4(sc, BGE_MODE_CTL, 2311 reg | BGE_MODECTL_PCIE_TLPADDR0); 2312 2313 /* Control TLP */ 2314 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2315 BGE_TLP_FTSMAX); 2316 reg &= ~BGE_TLP_FTSMAX_MSK; 2317 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2318 reg | BGE_TLP_FTSMAX_VAL); 2319 2320 /* Restore */ 2321 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2322 } 2323 2324 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2325 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2326 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2327 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2328 } 2329 2330 /* Set up the PCI DMA control register. */ 2331 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2332 if (sc->bge_flags & BGE_PCIE) { 2333 /* Read watermark not used, 128 bytes for write. */ 2334 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2335 device_xname(sc->bge_dev))); 2336 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2337 } else if (sc->bge_flags & BGE_PCIX) { 2338 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2339 device_xname(sc->bge_dev))); 2340 /* PCI-X bus */ 2341 if (BGE_IS_5714_FAMILY(sc)) { 2342 /* 256 bytes for read and write. */ 2343 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2344 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2345 2346 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2347 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2348 else 2349 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2350 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2351 /* 1536 bytes for read, 384 bytes for write. */ 2352 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2353 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2354 } else { 2355 /* 384 bytes for read and write. */ 2356 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2357 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2358 (0x0F); 2359 } 2360 2361 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2362 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2363 uint32_t tmp; 2364 2365 /* Set ONEDMA_ATONCE for hardware workaround. */ 2366 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2367 if (tmp == 6 || tmp == 7) 2368 dma_rw_ctl |= 2369 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2370 2371 /* Set PCI-X DMA write workaround. */ 2372 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2373 } 2374 } else { 2375 /* Conventional PCI bus: 256 bytes for read and write. */ 2376 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2377 device_xname(sc->bge_dev))); 2378 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2379 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2380 2381 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2382 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2383 dma_rw_ctl |= 0x0F; 2384 } 2385 2386 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2387 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2388 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2389 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2390 2391 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2392 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2393 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2394 2395 if (BGE_IS_5717_PLUS(sc)) { 2396 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2397 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2398 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2399 2400 /* 2401 * Enable HW workaround for controllers that misinterpret 2402 * a status tag update and leave interrupts permanently 2403 * disabled. 2404 */ 2405 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2406 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2407 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2408 } 2409 2410 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2411 dma_rw_ctl); 2412 2413 /* 2414 * Set up general mode register. 2415 */ 2416 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2417 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2418 /* Retain Host-2-BMC settings written by APE firmware. */ 2419 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2420 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2421 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2422 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2423 } 2424 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2425 BGE_MODECTL_TX_NO_PHDR_CSUM; 2426 2427 /* 2428 * BCM5701 B5 have a bug causing data corruption when using 2429 * 64-bit DMA reads, which can be terminated early and then 2430 * completed later as 32-bit accesses, in combination with 2431 * certain bridges. 2432 */ 2433 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2434 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2435 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2436 2437 /* 2438 * Tell the firmware the driver is running 2439 */ 2440 if (sc->bge_asf_mode & ASF_STACKUP) 2441 mode_ctl |= BGE_MODECTL_STACKUP; 2442 2443 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2444 2445 /* 2446 * Disable memory write invalidate. Apparently it is not supported 2447 * properly by these devices. 2448 */ 2449 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2450 PCI_COMMAND_INVALIDATE_ENABLE); 2451 2452 #ifdef __brokenalpha__ 2453 /* 2454 * Must insure that we do not cross an 8K (bytes) boundary 2455 * for DMA reads. Our highest limit is 1K bytes. This is a 2456 * restriction on some ALPHA platforms with early revision 2457 * 21174 PCI chipsets, such as the AlphaPC 164lx 2458 */ 2459 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2460 #endif 2461 2462 /* Set the timer prescaler (always 66MHz) */ 2463 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2464 2465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2466 DELAY(40); /* XXX */ 2467 2468 /* Put PHY into ready state */ 2469 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2470 DELAY(40); 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int 2477 bge_blockinit(struct bge_softc *sc) 2478 { 2479 volatile struct bge_rcb *rcb; 2480 bus_size_t rcb_addr; 2481 struct ifnet *ifp = &sc->ethercom.ec_if; 2482 bge_hostaddr taddr; 2483 uint32_t dmactl, val; 2484 int i, limit; 2485 2486 /* 2487 * Initialize the memory window pointer register so that 2488 * we can access the first 32K of internal NIC RAM. This will 2489 * allow us to set up the TX send ring RCBs and the RX return 2490 * ring RCBs, plus other things which live in NIC memory. 2491 */ 2492 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2493 2494 /* Step 33: Configure mbuf memory pool */ 2495 if (!BGE_IS_5705_PLUS(sc)) { 2496 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2497 BGE_BUFFPOOL_1); 2498 2499 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2501 else 2502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2503 2504 /* Configure DMA resource pool */ 2505 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2506 BGE_DMA_DESCRIPTORS); 2507 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2508 } 2509 2510 /* Step 35: Configure mbuf pool watermarks */ 2511 /* new broadcom docs strongly recommend these: */ 2512 if (BGE_IS_5717_PLUS(sc)) { 2513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2514 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2515 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2516 } else if (BGE_IS_5705_PLUS(sc)) { 2517 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2518 2519 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2521 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2522 } else { 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2524 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2525 } 2526 } else { 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2530 } 2531 2532 /* Step 36: Configure DMA resource watermarks */ 2533 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2534 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2535 2536 /* Step 38: Enable buffer manager */ 2537 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2538 /* 2539 * Change the arbitration algorithm of TXMBUF read request to 2540 * round-robin instead of priority based for BCM5719. When 2541 * TXFIFO is almost empty, RDMA will hold its request until 2542 * TXFIFO is not almost empty. 2543 */ 2544 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2545 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2546 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2547 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2548 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2549 val |= BGE_BMANMODE_LOMBUF_ATTN; 2550 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2551 2552 /* Step 39: Poll for buffer manager start indication */ 2553 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2554 DELAY(10); 2555 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2556 break; 2557 } 2558 2559 if (i == BGE_TIMEOUT * 2) { 2560 aprint_error_dev(sc->bge_dev, 2561 "buffer manager failed to start\n"); 2562 return ENXIO; 2563 } 2564 2565 /* Step 40: Enable flow-through queues */ 2566 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2567 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2568 2569 /* Wait until queue initialization is complete */ 2570 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2571 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2572 break; 2573 DELAY(10); 2574 } 2575 2576 if (i == BGE_TIMEOUT * 2) { 2577 aprint_error_dev(sc->bge_dev, 2578 "flow-through queue init failed\n"); 2579 return ENXIO; 2580 } 2581 2582 /* 2583 * Summary of rings supported by the controller: 2584 * 2585 * Standard Receive Producer Ring 2586 * - This ring is used to feed receive buffers for "standard" 2587 * sized frames (typically 1536 bytes) to the controller. 2588 * 2589 * Jumbo Receive Producer Ring 2590 * - This ring is used to feed receive buffers for jumbo sized 2591 * frames (i.e. anything bigger than the "standard" frames) 2592 * to the controller. 2593 * 2594 * Mini Receive Producer Ring 2595 * - This ring is used to feed receive buffers for "mini" 2596 * sized frames to the controller. 2597 * - This feature required external memory for the controller 2598 * but was never used in a production system. Should always 2599 * be disabled. 2600 * 2601 * Receive Return Ring 2602 * - After the controller has placed an incoming frame into a 2603 * receive buffer that buffer is moved into a receive return 2604 * ring. The driver is then responsible to passing the 2605 * buffer up to the stack. Many versions of the controller 2606 * support multiple RR rings. 2607 * 2608 * Send Ring 2609 * - This ring is used for outgoing frames. Many versions of 2610 * the controller support multiple send rings. 2611 */ 2612 2613 /* Step 41: Initialize the standard RX ring control block */ 2614 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2615 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2616 if (BGE_IS_5717_PLUS(sc)) { 2617 /* 2618 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2619 * Bits 15-2 : Maximum RX frame size 2620 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2621 * Bit 0 : Reserved 2622 */ 2623 rcb->bge_maxlen_flags = 2624 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2625 } else if (BGE_IS_5705_PLUS(sc)) { 2626 /* 2627 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2628 * Bits 15-2 : Reserved (should be 0) 2629 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2630 * Bit 0 : Reserved 2631 */ 2632 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2633 } else { 2634 /* 2635 * Ring size is always XXX entries 2636 * Bits 31-16: Maximum RX frame size 2637 * Bits 15-2 : Reserved (should be 0) 2638 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2639 * Bit 0 : Reserved 2640 */ 2641 rcb->bge_maxlen_flags = 2642 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2643 } 2644 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2646 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2647 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2648 else 2649 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2650 /* Write the standard receive producer ring control block. */ 2651 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2652 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2653 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2654 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2655 2656 /* Reset the standard receive producer ring producer index. */ 2657 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2658 2659 /* 2660 * Step 42: Initialize the jumbo RX ring control block 2661 * We set the 'ring disabled' bit in the flags 2662 * field until we're actually ready to start 2663 * using this ring (i.e. once we set the MTU 2664 * high enough to require it). 2665 */ 2666 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2667 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2668 BGE_HOSTADDR(rcb->bge_hostaddr, 2669 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2670 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2671 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2672 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2674 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2675 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2676 else 2677 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2678 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2679 rcb->bge_hostaddr.bge_addr_hi); 2680 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2681 rcb->bge_hostaddr.bge_addr_lo); 2682 /* Program the jumbo receive producer ring RCB parameters. */ 2683 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2684 rcb->bge_maxlen_flags); 2685 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2686 /* Reset the jumbo receive producer ring producer index. */ 2687 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2688 } 2689 2690 /* Disable the mini receive producer ring RCB. */ 2691 if (BGE_IS_5700_FAMILY(sc)) { 2692 /* Set up dummy disabled mini ring RCB */ 2693 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2694 rcb->bge_maxlen_flags = 2695 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2696 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2697 rcb->bge_maxlen_flags); 2698 /* Reset the mini receive producer ring producer index. */ 2699 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2700 2701 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2702 offsetof(struct bge_ring_data, bge_info), 2703 sizeof (struct bge_gib), 2704 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2705 } 2706 2707 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2708 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2709 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2710 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2711 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2712 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2713 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2714 } 2715 /* 2716 * The BD ring replenish thresholds control how often the 2717 * hardware fetches new BD's from the producer rings in host 2718 * memory. Setting the value too low on a busy system can 2719 * starve the hardware and recue the throughpout. 2720 * 2721 * Set the BD ring replenish thresholds. The recommended 2722 * values are 1/8th the number of descriptors allocated to 2723 * each ring, but since we try to avoid filling the entire 2724 * ring we set these to the minimal value of 8. This needs to 2725 * be done on several of the supported chip revisions anyway, 2726 * to work around HW bugs. 2727 */ 2728 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2729 if (BGE_IS_JUMBO_CAPABLE(sc)) 2730 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2731 2732 if (BGE_IS_5717_PLUS(sc)) { 2733 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2734 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2735 } 2736 2737 /* 2738 * Disable all send rings by setting the 'ring disabled' bit 2739 * in the flags field of all the TX send ring control blocks, 2740 * located in NIC memory. 2741 */ 2742 if (BGE_IS_5700_FAMILY(sc)) { 2743 /* 5700 to 5704 had 16 send rings. */ 2744 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2745 } else 2746 limit = 1; 2747 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2748 for (i = 0; i < limit; i++) { 2749 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2750 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2751 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2752 rcb_addr += sizeof(struct bge_rcb); 2753 } 2754 2755 /* Configure send ring RCB 0 (we use only the first ring) */ 2756 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2757 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2758 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2759 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2760 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2761 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2762 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2763 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2764 else 2765 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2766 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2767 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2768 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2769 2770 /* 2771 * Disable all receive return rings by setting the 2772 * 'ring diabled' bit in the flags field of all the receive 2773 * return ring control blocks, located in NIC memory. 2774 */ 2775 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2776 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2777 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2778 /* Should be 17, use 16 until we get an SRAM map. */ 2779 limit = 16; 2780 } else if (BGE_IS_5700_FAMILY(sc)) 2781 limit = BGE_RX_RINGS_MAX; 2782 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2783 BGE_IS_57765_PLUS(sc)) 2784 limit = 4; 2785 else 2786 limit = 1; 2787 /* Disable all receive return rings */ 2788 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2789 for (i = 0; i < limit; i++) { 2790 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2791 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2792 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2793 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2794 BGE_RCB_FLAG_RING_DISABLED)); 2795 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2796 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2797 (i * (sizeof(uint64_t))), 0); 2798 rcb_addr += sizeof(struct bge_rcb); 2799 } 2800 2801 /* 2802 * Set up receive return ring 0. Note that the NIC address 2803 * for RX return rings is 0x0. The return rings live entirely 2804 * within the host, so the nicaddr field in the RCB isn't used. 2805 */ 2806 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2807 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2808 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2809 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2810 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2811 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2812 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2813 2814 /* Set random backoff seed for TX */ 2815 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2816 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2817 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2818 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2819 BGE_TX_BACKOFF_SEED_MASK); 2820 2821 /* Set inter-packet gap */ 2822 val = 0x2620; 2823 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2824 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2825 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2826 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2827 2828 /* 2829 * Specify which ring to use for packets that don't match 2830 * any RX rules. 2831 */ 2832 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2833 2834 /* 2835 * Configure number of RX lists. One interrupt distribution 2836 * list, sixteen active lists, one bad frames class. 2837 */ 2838 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2839 2840 /* Inialize RX list placement stats mask. */ 2841 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2842 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2843 2844 /* Disable host coalescing until we get it set up */ 2845 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2846 2847 /* Poll to make sure it's shut down. */ 2848 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2849 DELAY(10); 2850 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2851 break; 2852 } 2853 2854 if (i == BGE_TIMEOUT * 2) { 2855 aprint_error_dev(sc->bge_dev, 2856 "host coalescing engine failed to idle\n"); 2857 return ENXIO; 2858 } 2859 2860 /* Set up host coalescing defaults */ 2861 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2862 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2863 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2864 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2865 if (!(BGE_IS_5705_PLUS(sc))) { 2866 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2867 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2868 } 2869 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2870 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2871 2872 /* Set up address of statistics block */ 2873 if (BGE_IS_5700_FAMILY(sc)) { 2874 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2875 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2876 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2877 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2878 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2879 } 2880 2881 /* Set up address of status block */ 2882 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2883 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2884 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2885 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2886 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2887 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2888 2889 /* Set up status block size. */ 2890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2891 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2892 val = BGE_STATBLKSZ_FULL; 2893 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2894 } else { 2895 val = BGE_STATBLKSZ_32BYTE; 2896 bzero(&sc->bge_rdata->bge_status_block, 32); 2897 } 2898 2899 /* Turn on host coalescing state machine */ 2900 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2901 2902 /* Turn on RX BD completion state machine and enable attentions */ 2903 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2904 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2905 2906 /* Turn on RX list placement state machine */ 2907 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2908 2909 /* Turn on RX list selector state machine. */ 2910 if (!(BGE_IS_5705_PLUS(sc))) 2911 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2912 2913 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2914 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2915 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2916 BGE_MACMODE_FRMHDR_DMA_ENB; 2917 2918 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2919 val |= BGE_PORTMODE_TBI; 2920 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2921 val |= BGE_PORTMODE_GMII; 2922 else 2923 val |= BGE_PORTMODE_MII; 2924 2925 /* Allow APE to send/receive frames. */ 2926 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2927 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2928 2929 /* Turn on DMA, clear stats */ 2930 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2931 DELAY(40); 2932 2933 /* Set misc. local control, enable interrupts on attentions */ 2934 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2935 if (BGE_IS_5717_PLUS(sc)) { 2936 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2937 DELAY(100); 2938 } 2939 2940 /* Turn on DMA completion state machine */ 2941 if (!(BGE_IS_5705_PLUS(sc))) 2942 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2943 2944 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2945 2946 /* Enable host coalescing bug fix. */ 2947 if (BGE_IS_5755_PLUS(sc)) 2948 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2949 2950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2951 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2952 2953 /* Turn on write DMA state machine */ 2954 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2955 DELAY(40); 2956 2957 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2958 2959 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2960 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2961 2962 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2963 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2964 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2965 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2966 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2967 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2968 2969 if (sc->bge_flags & BGE_PCIE) 2970 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2971 if (sc->bge_flags & BGE_TSO) 2972 val |= BGE_RDMAMODE_TSO4_ENABLE; 2973 2974 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2975 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2976 BGE_RDMAMODE_H2BNC_VLAN_DET; 2977 /* 2978 * Allow multiple outstanding read requests from 2979 * non-LSO read DMA engine. 2980 */ 2981 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2982 } 2983 2984 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2985 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2986 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2987 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2988 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2989 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2990 /* 2991 * Adjust tx margin to prevent TX data corruption and 2992 * fix internal FIFO overflow. 2993 */ 2994 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2995 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2996 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2997 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2998 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2999 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3000 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3001 } 3002 /* 3003 * Enable fix for read DMA FIFO overruns. 3004 * The fix is to limit the number of RX BDs 3005 * the hardware would fetch at a fime. 3006 */ 3007 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3008 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3009 } 3010 3011 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3012 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3013 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3014 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3015 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3016 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3017 /* 3018 * Allow 4KB burst length reads for non-LSO frames. 3019 * Enable 512B burst length reads for buffer descriptors. 3020 */ 3021 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3022 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3023 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3024 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3025 } 3026 3027 /* Turn on read DMA state machine */ 3028 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3029 delay(40); 3030 3031 /* Turn on RX data completion state machine */ 3032 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3033 3034 /* Turn on RX data and RX BD initiator state machine */ 3035 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3036 3037 /* Turn on Mbuf cluster free state machine */ 3038 if (!BGE_IS_5705_PLUS(sc)) 3039 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3040 3041 /* Turn on send data completion state machine */ 3042 val = BGE_SDCMODE_ENABLE; 3043 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3044 val |= BGE_SDCMODE_CDELAY; 3045 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3046 3047 /* Turn on send BD completion state machine */ 3048 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3049 3050 /* Turn on RX BD initiator state machine */ 3051 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3052 3053 /* Turn on send data initiator state machine */ 3054 if (sc->bge_flags & BGE_TSO) { 3055 /* XXX: magic value from Linux driver */ 3056 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3057 BGE_SDIMODE_HW_LSO_PRE_DMA); 3058 } else 3059 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3060 3061 /* Turn on send BD initiator state machine */ 3062 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3063 3064 /* Turn on send BD selector state machine */ 3065 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3066 3067 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3068 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3069 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3070 3071 /* ack/clear link change events */ 3072 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3073 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3074 BGE_MACSTAT_LINK_CHANGED); 3075 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3076 3077 /* 3078 * Enable attention when the link has changed state for 3079 * devices that use auto polling. 3080 */ 3081 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3082 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3083 } else { 3084 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3085 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3087 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3088 BGE_EVTENB_MI_INTERRUPT); 3089 } 3090 3091 /* 3092 * Clear any pending link state attention. 3093 * Otherwise some link state change events may be lost until attention 3094 * is cleared by bge_intr() -> bge_link_upd() sequence. 3095 * It's not necessary on newer BCM chips - perhaps enabling link 3096 * state change attentions implies clearing pending attention. 3097 */ 3098 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3099 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3100 BGE_MACSTAT_LINK_CHANGED); 3101 3102 /* Enable link state change attentions. */ 3103 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3104 3105 return 0; 3106 } 3107 3108 static const struct bge_revision * 3109 bge_lookup_rev(uint32_t chipid) 3110 { 3111 const struct bge_revision *br; 3112 3113 for (br = bge_revisions; br->br_name != NULL; br++) { 3114 if (br->br_chipid == chipid) 3115 return br; 3116 } 3117 3118 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3119 if (br->br_chipid == BGE_ASICREV(chipid)) 3120 return br; 3121 } 3122 3123 return NULL; 3124 } 3125 3126 static const struct bge_product * 3127 bge_lookup(const struct pci_attach_args *pa) 3128 { 3129 const struct bge_product *bp; 3130 3131 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3132 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3133 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3134 return bp; 3135 } 3136 3137 return NULL; 3138 } 3139 3140 static uint32_t 3141 bge_chipid(const struct pci_attach_args *pa) 3142 { 3143 uint32_t id; 3144 3145 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3146 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3147 3148 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3149 switch (PCI_PRODUCT(pa->pa_id)) { 3150 case PCI_PRODUCT_BROADCOM_BCM5717: 3151 case PCI_PRODUCT_BROADCOM_BCM5718: 3152 case PCI_PRODUCT_BROADCOM_BCM5719: 3153 case PCI_PRODUCT_BROADCOM_BCM5720: 3154 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3155 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3156 BGE_PCI_GEN2_PRODID_ASICREV); 3157 break; 3158 case PCI_PRODUCT_BROADCOM_BCM57761: 3159 case PCI_PRODUCT_BROADCOM_BCM57762: 3160 case PCI_PRODUCT_BROADCOM_BCM57765: 3161 case PCI_PRODUCT_BROADCOM_BCM57766: 3162 case PCI_PRODUCT_BROADCOM_BCM57781: 3163 case PCI_PRODUCT_BROADCOM_BCM57785: 3164 case PCI_PRODUCT_BROADCOM_BCM57791: 3165 case PCI_PRODUCT_BROADCOM_BCM57795: 3166 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3167 BGE_PCI_GEN15_PRODID_ASICREV); 3168 break; 3169 default: 3170 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3171 BGE_PCI_PRODID_ASICREV); 3172 break; 3173 } 3174 } 3175 3176 return id; 3177 } 3178 3179 /* 3180 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3181 * against our list and return its name if we find a match. Note 3182 * that since the Broadcom controller contains VPD support, we 3183 * can get the device name string from the controller itself instead 3184 * of the compiled-in string. This is a little slow, but it guarantees 3185 * we'll always announce the right product name. 3186 */ 3187 static int 3188 bge_probe(device_t parent, cfdata_t match, void *aux) 3189 { 3190 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3191 3192 if (bge_lookup(pa) != NULL) 3193 return 1; 3194 3195 return 0; 3196 } 3197 3198 static void 3199 bge_attach(device_t parent, device_t self, void *aux) 3200 { 3201 struct bge_softc *sc = device_private(self); 3202 struct pci_attach_args *pa = aux; 3203 prop_dictionary_t dict; 3204 const struct bge_product *bp; 3205 const struct bge_revision *br; 3206 pci_chipset_tag_t pc; 3207 pci_intr_handle_t ih; 3208 const char *intrstr = NULL; 3209 uint32_t hwcfg = 0; 3210 uint32_t command; 3211 struct ifnet *ifp; 3212 uint32_t misccfg; 3213 void * kva; 3214 u_char eaddr[ETHER_ADDR_LEN]; 3215 pcireg_t memtype, subid, reg; 3216 bus_addr_t memaddr; 3217 uint32_t pm_ctl; 3218 bool no_seeprom; 3219 int capmask; 3220 3221 bp = bge_lookup(pa); 3222 KASSERT(bp != NULL); 3223 3224 sc->sc_pc = pa->pa_pc; 3225 sc->sc_pcitag = pa->pa_tag; 3226 sc->bge_dev = self; 3227 3228 sc->bge_pa = *pa; 3229 pc = sc->sc_pc; 3230 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3231 3232 aprint_naive(": Ethernet controller\n"); 3233 aprint_normal(": %s\n", bp->bp_name); 3234 3235 /* 3236 * Map control/status registers. 3237 */ 3238 DPRINTFN(5, ("Map control/status regs\n")); 3239 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3240 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3241 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3242 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3243 3244 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3245 aprint_error_dev(sc->bge_dev, 3246 "failed to enable memory mapping!\n"); 3247 return; 3248 } 3249 3250 DPRINTFN(5, ("pci_mem_find\n")); 3251 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3252 switch (memtype) { 3253 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3254 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3255 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3256 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3257 &memaddr, &sc->bge_bsize) == 0) 3258 break; 3259 default: 3260 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3261 return; 3262 } 3263 3264 DPRINTFN(5, ("pci_intr_map\n")); 3265 if (pci_intr_map(pa, &ih)) { 3266 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3267 return; 3268 } 3269 3270 DPRINTFN(5, ("pci_intr_string\n")); 3271 intrstr = pci_intr_string(pc, ih); 3272 3273 DPRINTFN(5, ("pci_intr_establish\n")); 3274 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3275 3276 if (sc->bge_intrhand == NULL) { 3277 aprint_error_dev(sc->bge_dev, 3278 "couldn't establish interrupt%s%s\n", 3279 intrstr ? " at " : "", intrstr ? intrstr : ""); 3280 return; 3281 } 3282 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3283 3284 /* Save various chip information. */ 3285 sc->bge_chipid = bge_chipid(pa); 3286 sc->bge_phy_addr = bge_phy_addr(sc); 3287 3288 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3289 &sc->bge_pciecap, NULL) != 0) 3290 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3291 /* PCIe */ 3292 sc->bge_flags |= BGE_PCIE; 3293 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3294 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3295 sc->bge_expmrq = 2048; 3296 else 3297 sc->bge_expmrq = 4096; 3298 bge_set_max_readrq(sc); 3299 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3300 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3301 /* PCI-X */ 3302 sc->bge_flags |= BGE_PCIX; 3303 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3304 &sc->bge_pcixcap, NULL) == 0) 3305 aprint_error_dev(sc->bge_dev, 3306 "unable to find PCIX capability\n"); 3307 } 3308 3309 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3310 /* 3311 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3312 * can clobber the chip's PCI config-space power control 3313 * registers, leaving the card in D3 powersave state. We do 3314 * not have memory-mapped registers in this state, so force 3315 * device into D0 state before starting initialization. 3316 */ 3317 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3318 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3319 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3320 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3321 DELAY(1000); /* 27 usec is allegedly sufficent */ 3322 } 3323 3324 /* Save chipset family. */ 3325 switch (BGE_ASICREV(sc->bge_chipid)) { 3326 case BGE_ASICREV_BCM57765: 3327 case BGE_ASICREV_BCM57766: 3328 sc->bge_flags |= BGE_57765_PLUS; 3329 /* FALLTHROUGH */ 3330 case BGE_ASICREV_BCM5717: 3331 case BGE_ASICREV_BCM5719: 3332 case BGE_ASICREV_BCM5720: 3333 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3334 BGE_5705_PLUS; 3335 break; 3336 case BGE_ASICREV_BCM5755: 3337 case BGE_ASICREV_BCM5761: 3338 case BGE_ASICREV_BCM5784: 3339 case BGE_ASICREV_BCM5785: 3340 case BGE_ASICREV_BCM5787: 3341 case BGE_ASICREV_BCM57780: 3342 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3343 break; 3344 case BGE_ASICREV_BCM5700: 3345 case BGE_ASICREV_BCM5701: 3346 case BGE_ASICREV_BCM5703: 3347 case BGE_ASICREV_BCM5704: 3348 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3349 break; 3350 case BGE_ASICREV_BCM5714_A0: 3351 case BGE_ASICREV_BCM5780: 3352 case BGE_ASICREV_BCM5714: 3353 sc->bge_flags |= BGE_5714_FAMILY; 3354 /* FALLTHROUGH */ 3355 case BGE_ASICREV_BCM5750: 3356 case BGE_ASICREV_BCM5752: 3357 case BGE_ASICREV_BCM5906: 3358 sc->bge_flags |= BGE_575X_PLUS; 3359 /* FALLTHROUGH */ 3360 case BGE_ASICREV_BCM5705: 3361 sc->bge_flags |= BGE_5705_PLUS; 3362 break; 3363 } 3364 3365 /* Identify chips with APE processor. */ 3366 switch (BGE_ASICREV(sc->bge_chipid)) { 3367 case BGE_ASICREV_BCM5717: 3368 case BGE_ASICREV_BCM5719: 3369 case BGE_ASICREV_BCM5720: 3370 case BGE_ASICREV_BCM5761: 3371 sc->bge_flags |= BGE_APE; 3372 break; 3373 } 3374 3375 /* Chips with APE need BAR2 access for APE registers/memory. */ 3376 if ((sc->bge_flags & BGE_APE) != 0) { 3377 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3378 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3379 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3380 &sc->bge_apesize)) { 3381 aprint_error_dev(sc->bge_dev, 3382 "couldn't map BAR2 memory\n"); 3383 return; 3384 } 3385 3386 /* Enable APE register/memory access by host driver. */ 3387 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3388 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3389 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3390 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3391 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3392 3393 bge_ape_lock_init(sc); 3394 bge_ape_read_fw_ver(sc); 3395 } 3396 3397 /* Identify the chips that use an CPMU. */ 3398 if (BGE_IS_5717_PLUS(sc) || 3399 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3400 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3401 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3402 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3403 sc->bge_flags |= BGE_CPMU_PRESENT; 3404 3405 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3406 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3407 else 3408 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3409 3410 /* 3411 * When using the BCM5701 in PCI-X mode, data corruption has 3412 * been observed in the first few bytes of some received packets. 3413 * Aligning the packet buffer in memory eliminates the corruption. 3414 * Unfortunately, this misaligns the packet payloads. On platforms 3415 * which do not support unaligned accesses, we will realign the 3416 * payloads by copying the received packets. 3417 */ 3418 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3419 sc->bge_flags & BGE_PCIX) 3420 sc->bge_flags |= BGE_RX_ALIGNBUG; 3421 3422 if (BGE_IS_5700_FAMILY(sc)) 3423 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3424 3425 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3426 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3427 3428 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3429 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3430 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3431 sc->bge_flags |= BGE_IS_5788; 3432 3433 /* 3434 * Some controllers seem to require a special firmware to use 3435 * TSO. But the firmware is not available to FreeBSD and Linux 3436 * claims that the TSO performed by the firmware is slower than 3437 * hardware based TSO. Moreover the firmware based TSO has one 3438 * known bug which can't handle TSO if ethernet header + IP/TCP 3439 * header is greater than 80 bytes. The workaround for the TSO 3440 * bug exist but it seems it's too expensive than not using 3441 * TSO at all. Some hardwares also have the TSO bug so limit 3442 * the TSO to the controllers that are not affected TSO issues 3443 * (e.g. 5755 or higher). 3444 */ 3445 if (BGE_IS_5755_PLUS(sc)) { 3446 /* 3447 * BCM5754 and BCM5787 shares the same ASIC id so 3448 * explicit device id check is required. 3449 */ 3450 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3451 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3452 sc->bge_flags |= BGE_TSO; 3453 } 3454 3455 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3456 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3457 (misccfg == 0x4000 || misccfg == 0x8000)) || 3458 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3459 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3460 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3461 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3463 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3464 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3465 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3466 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3467 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3468 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3469 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3470 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3471 capmask &= ~BMSR_EXTSTAT; 3472 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3473 } 3474 3475 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3476 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3477 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3478 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3479 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3480 3481 /* Set various PHY bug flags. */ 3482 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3483 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3484 sc->bge_flags |= BGE_PHY_CRC_BUG; 3485 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3486 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3487 sc->bge_flags |= BGE_PHY_ADC_BUG; 3488 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3489 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3490 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3492 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3493 sc->bge_flags |= BGE_PHY_NO_3LED; 3494 if (BGE_IS_5705_PLUS(sc) && 3495 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3496 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3497 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3498 !BGE_IS_5717_PLUS(sc)) { 3499 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3500 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3503 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3504 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3505 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3506 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3507 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3508 } else 3509 sc->bge_flags |= BGE_PHY_BER_BUG; 3510 } 3511 3512 /* 3513 * SEEPROM check. 3514 * First check if firmware knows we do not have SEEPROM. 3515 */ 3516 if (prop_dictionary_get_bool(device_properties(self), 3517 "without-seeprom", &no_seeprom) && no_seeprom) 3518 sc->bge_flags |= BGE_NO_EEPROM; 3519 3520 /* Now check the 'ROM failed' bit on the RX CPU */ 3521 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3522 sc->bge_flags |= BGE_NO_EEPROM; 3523 3524 sc->bge_asf_mode = 0; 3525 /* No ASF if APE present. */ 3526 if ((sc->bge_flags & BGE_APE) == 0) { 3527 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3528 BGE_SRAM_DATA_SIG_MAGIC)) { 3529 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3530 BGE_HWCFG_ASF) { 3531 sc->bge_asf_mode |= ASF_ENABLE; 3532 sc->bge_asf_mode |= ASF_STACKUP; 3533 if (BGE_IS_575X_PLUS(sc)) 3534 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3535 } 3536 } 3537 } 3538 3539 bge_stop_fw(sc); 3540 bge_sig_pre_reset(sc, BGE_RESET_START); 3541 if (bge_reset(sc)) 3542 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3543 3544 bge_sig_legacy(sc, BGE_RESET_START); 3545 bge_sig_post_reset(sc, BGE_RESET_START); 3546 3547 if (bge_chipinit(sc)) { 3548 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3549 bge_release_resources(sc); 3550 return; 3551 } 3552 3553 /* 3554 * Get station address from the EEPROM. 3555 */ 3556 if (bge_get_eaddr(sc, eaddr)) { 3557 aprint_error_dev(sc->bge_dev, 3558 "failed to read station address\n"); 3559 bge_release_resources(sc); 3560 return; 3561 } 3562 3563 br = bge_lookup_rev(sc->bge_chipid); 3564 3565 if (br == NULL) { 3566 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3567 sc->bge_chipid); 3568 } else { 3569 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3570 br->br_name, sc->bge_chipid); 3571 } 3572 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3573 3574 /* Allocate the general information block and ring buffers. */ 3575 if (pci_dma64_available(pa)) 3576 sc->bge_dmatag = pa->pa_dmat64; 3577 else 3578 sc->bge_dmatag = pa->pa_dmat; 3579 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3580 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3581 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3582 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3583 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3584 return; 3585 } 3586 DPRINTFN(5, ("bus_dmamem_map\n")); 3587 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3588 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3589 BUS_DMA_NOWAIT)) { 3590 aprint_error_dev(sc->bge_dev, 3591 "can't map DMA buffers (%zu bytes)\n", 3592 sizeof(struct bge_ring_data)); 3593 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3594 sc->bge_ring_rseg); 3595 return; 3596 } 3597 DPRINTFN(5, ("bus_dmamem_create\n")); 3598 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3599 sizeof(struct bge_ring_data), 0, 3600 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3601 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3602 bus_dmamem_unmap(sc->bge_dmatag, kva, 3603 sizeof(struct bge_ring_data)); 3604 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3605 sc->bge_ring_rseg); 3606 return; 3607 } 3608 DPRINTFN(5, ("bus_dmamem_load\n")); 3609 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3610 sizeof(struct bge_ring_data), NULL, 3611 BUS_DMA_NOWAIT)) { 3612 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3613 bus_dmamem_unmap(sc->bge_dmatag, kva, 3614 sizeof(struct bge_ring_data)); 3615 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3616 sc->bge_ring_rseg); 3617 return; 3618 } 3619 3620 DPRINTFN(5, ("bzero\n")); 3621 sc->bge_rdata = (struct bge_ring_data *)kva; 3622 3623 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3624 3625 /* Try to allocate memory for jumbo buffers. */ 3626 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3627 if (bge_alloc_jumbo_mem(sc)) { 3628 aprint_error_dev(sc->bge_dev, 3629 "jumbo buffer allocation failed\n"); 3630 } else 3631 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3632 } 3633 3634 /* Set default tuneable values. */ 3635 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3636 sc->bge_rx_coal_ticks = 150; 3637 sc->bge_rx_max_coal_bds = 64; 3638 sc->bge_tx_coal_ticks = 300; 3639 sc->bge_tx_max_coal_bds = 400; 3640 if (BGE_IS_5705_PLUS(sc)) { 3641 sc->bge_tx_coal_ticks = (12 * 5); 3642 sc->bge_tx_max_coal_bds = (12 * 5); 3643 aprint_verbose_dev(sc->bge_dev, 3644 "setting short Tx thresholds\n"); 3645 } 3646 3647 if (BGE_IS_5717_PLUS(sc)) 3648 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3649 else if (BGE_IS_5705_PLUS(sc)) 3650 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3651 else 3652 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3653 3654 /* Set up ifnet structure */ 3655 ifp = &sc->ethercom.ec_if; 3656 ifp->if_softc = sc; 3657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3658 ifp->if_ioctl = bge_ioctl; 3659 ifp->if_stop = bge_stop; 3660 ifp->if_start = bge_start; 3661 ifp->if_init = bge_init; 3662 ifp->if_watchdog = bge_watchdog; 3663 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3664 IFQ_SET_READY(&ifp->if_snd); 3665 DPRINTFN(5, ("strcpy if_xname\n")); 3666 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3667 3668 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3669 sc->ethercom.ec_if.if_capabilities |= 3670 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3671 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3672 sc->ethercom.ec_if.if_capabilities |= 3673 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3674 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3675 #endif 3676 sc->ethercom.ec_capabilities |= 3677 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3678 3679 if (sc->bge_flags & BGE_TSO) 3680 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3681 3682 /* 3683 * Do MII setup. 3684 */ 3685 DPRINTFN(5, ("mii setup\n")); 3686 sc->bge_mii.mii_ifp = ifp; 3687 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3688 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3689 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3690 3691 /* 3692 * Figure out what sort of media we have by checking the hardware 3693 * config word in the first 32k of NIC internal memory, or fall back to 3694 * the config word in the EEPROM. Note: on some BCM5700 cards, 3695 * this value appears to be unset. If that's the case, we have to rely 3696 * on identifying the NIC by its PCI subsystem ID, as we do below for 3697 * the SysKonnect SK-9D41. 3698 */ 3699 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3700 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3701 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3702 bge_read_eeprom(sc, (void *)&hwcfg, 3703 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3704 hwcfg = be32toh(hwcfg); 3705 } 3706 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3707 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3708 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3709 if (BGE_IS_5714_FAMILY(sc)) 3710 sc->bge_flags |= BGE_PHY_FIBER_MII; 3711 else 3712 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3713 } 3714 3715 /* set phyflags and chipid before mii_attach() */ 3716 dict = device_properties(self); 3717 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3718 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3719 3720 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3721 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3722 bge_ifmedia_sts); 3723 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3724 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3725 0, NULL); 3726 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3727 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3728 /* Pretend the user requested this setting */ 3729 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3730 } else { 3731 /* 3732 * Do transceiver setup and tell the firmware the 3733 * driver is down so we can try to get access the 3734 * probe if ASF is running. Retry a couple of times 3735 * if we get a conflict with the ASF firmware accessing 3736 * the PHY. 3737 */ 3738 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3739 bge_asf_driver_up(sc); 3740 3741 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3742 bge_ifmedia_sts); 3743 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3744 sc->bge_phy_addr, MII_OFFSET_ANY, 3745 MIIF_DOPAUSE); 3746 3747 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3748 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3749 ifmedia_add(&sc->bge_mii.mii_media, 3750 IFM_ETHER|IFM_MANUAL, 0, NULL); 3751 ifmedia_set(&sc->bge_mii.mii_media, 3752 IFM_ETHER|IFM_MANUAL); 3753 } else 3754 ifmedia_set(&sc->bge_mii.mii_media, 3755 IFM_ETHER|IFM_AUTO); 3756 3757 /* 3758 * Now tell the firmware we are going up after probing the PHY 3759 */ 3760 if (sc->bge_asf_mode & ASF_STACKUP) 3761 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3762 } 3763 3764 /* 3765 * Call MI attach routine. 3766 */ 3767 DPRINTFN(5, ("if_attach\n")); 3768 if_attach(ifp); 3769 DPRINTFN(5, ("ether_ifattach\n")); 3770 ether_ifattach(ifp, eaddr); 3771 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3772 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3773 RND_TYPE_NET, 0); 3774 #ifdef BGE_EVENT_COUNTERS 3775 /* 3776 * Attach event counters. 3777 */ 3778 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3779 NULL, device_xname(sc->bge_dev), "intr"); 3780 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3781 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3782 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3783 NULL, device_xname(sc->bge_dev), "tx_xon"); 3784 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3785 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3786 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3787 NULL, device_xname(sc->bge_dev), "rx_xon"); 3788 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3789 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3790 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3791 NULL, device_xname(sc->bge_dev), "xoffentered"); 3792 #endif /* BGE_EVENT_COUNTERS */ 3793 DPRINTFN(5, ("callout_init\n")); 3794 callout_init(&sc->bge_timeout, 0); 3795 3796 if (pmf_device_register(self, NULL, NULL)) 3797 pmf_class_network_register(self, ifp); 3798 else 3799 aprint_error_dev(self, "couldn't establish power handler\n"); 3800 3801 bge_sysctl_init(sc); 3802 3803 #ifdef BGE_DEBUG 3804 bge_debug_info(sc); 3805 #endif 3806 } 3807 3808 /* 3809 * Stop all chip I/O so that the kernel's probe routines don't 3810 * get confused by errant DMAs when rebooting. 3811 */ 3812 static int 3813 bge_detach(device_t self, int flags __unused) 3814 { 3815 struct bge_softc *sc = device_private(self); 3816 struct ifnet *ifp = &sc->ethercom.ec_if; 3817 int s; 3818 3819 s = splnet(); 3820 /* Stop the interface. Callouts are stopped in it. */ 3821 bge_stop(ifp, 1); 3822 splx(s); 3823 3824 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3825 3826 /* Delete all remaining media. */ 3827 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3828 3829 ether_ifdetach(ifp); 3830 if_detach(ifp); 3831 3832 bge_release_resources(sc); 3833 3834 return 0; 3835 } 3836 3837 static void 3838 bge_release_resources(struct bge_softc *sc) 3839 { 3840 3841 /* Disestablish the interrupt handler */ 3842 if (sc->bge_intrhand != NULL) { 3843 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3844 sc->bge_intrhand = NULL; 3845 } 3846 3847 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3848 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3849 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3850 sizeof(struct bge_ring_data)); 3851 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3852 3853 /* Unmap the device registers */ 3854 if (sc->bge_bsize != 0) { 3855 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3856 sc->bge_bsize = 0; 3857 } 3858 3859 /* Unmap the APE registers */ 3860 if (sc->bge_apesize != 0) { 3861 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3862 sc->bge_apesize); 3863 sc->bge_apesize = 0; 3864 } 3865 } 3866 3867 static int 3868 bge_reset(struct bge_softc *sc) 3869 { 3870 uint32_t cachesize, command; 3871 uint32_t reset, mac_mode, mac_mode_mask; 3872 pcireg_t devctl, reg; 3873 int i, val; 3874 void (*write_op)(struct bge_softc *, int, int); 3875 3876 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3877 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3878 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3879 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3880 3881 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3882 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3883 if (sc->bge_flags & BGE_PCIE) 3884 write_op = bge_writemem_direct; 3885 else 3886 write_op = bge_writemem_ind; 3887 } else 3888 write_op = bge_writereg_ind; 3889 3890 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3891 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3892 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3893 for (i = 0; i < 8000; i++) { 3894 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3895 BGE_NVRAMSWARB_GNT1) 3896 break; 3897 DELAY(20); 3898 } 3899 if (i == 8000) { 3900 printf("%s: NVRAM lock timedout!\n", 3901 device_xname(sc->bge_dev)); 3902 } 3903 } 3904 /* Take APE lock when performing reset. */ 3905 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3906 3907 /* Save some important PCI state. */ 3908 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3909 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3910 3911 /* Step 5b-5d: */ 3912 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3913 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3914 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3915 3916 /* XXX ???: Disable fastboot on controllers that support it. */ 3917 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3918 BGE_IS_5755_PLUS(sc)) 3919 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3920 3921 /* 3922 * Step 6: Write the magic number to SRAM at offset 0xB50. 3923 * When firmware finishes its initialization it will 3924 * write ~BGE_MAGIC_NUMBER to the same location. 3925 */ 3926 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3927 3928 /* Step 7: */ 3929 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3930 /* 3931 * XXX: from FreeBSD/Linux; no documentation 3932 */ 3933 if (sc->bge_flags & BGE_PCIE) { 3934 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3935 !BGE_IS_57765_PLUS(sc) && 3936 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3937 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3938 /* PCI Express 1.0 system */ 3939 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3940 BGE_PHY_PCIE_SCRAM_MODE); 3941 } 3942 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3943 /* 3944 * Prevent PCI Express link training 3945 * during global reset. 3946 */ 3947 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3948 reset |= (1 << 29); 3949 } 3950 } 3951 3952 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3953 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3954 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3955 i | BGE_VCPU_STATUS_DRV_RESET); 3956 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3957 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3958 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3959 } 3960 3961 /* 3962 * Set GPHY Power Down Override to leave GPHY 3963 * powered up in D0 uninitialized. 3964 */ 3965 if (BGE_IS_5705_PLUS(sc) && 3966 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3967 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3968 3969 /* Issue global reset */ 3970 write_op(sc, BGE_MISC_CFG, reset); 3971 3972 /* Step 8: wait for complete */ 3973 if (sc->bge_flags & BGE_PCIE) 3974 delay(100*1000); /* too big */ 3975 else 3976 delay(1000); 3977 3978 if (sc->bge_flags & BGE_PCIE) { 3979 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3980 DELAY(500000); 3981 /* XXX: Magic Numbers */ 3982 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3983 BGE_PCI_UNKNOWN0); 3984 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3985 BGE_PCI_UNKNOWN0, 3986 reg | (1 << 15)); 3987 } 3988 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3989 sc->bge_pciecap + PCI_PCIE_DCSR); 3990 /* Clear enable no snoop and disable relaxed ordering. */ 3991 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 3992 PCI_PCIE_DCSR_ENA_NO_SNOOP); 3993 3994 /* Set PCIE max payload size to 128 for older PCIe devices */ 3995 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3996 devctl &= ~(0x00e0); 3997 /* Clear device status register. Write 1b to clear */ 3998 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3999 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 4000 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4001 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 4002 bge_set_max_readrq(sc); 4003 } 4004 4005 /* From Linux: dummy read to flush PCI posted writes */ 4006 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4007 4008 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 4009 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4010 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4011 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4012 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4013 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4014 (sc->bge_flags & BGE_PCIX) != 0) 4015 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4016 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4017 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4018 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4019 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4020 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4021 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4022 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4023 4024 /* Step 11: disable PCI-X Relaxed Ordering. */ 4025 if (sc->bge_flags & BGE_PCIX) { 4026 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4027 + PCI_PCIX_CMD); 4028 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4029 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 4030 } 4031 4032 /* Step 12: Enable memory arbiter. */ 4033 if (BGE_IS_5714_FAMILY(sc)) { 4034 val = CSR_READ_4(sc, BGE_MARB_MODE); 4035 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4036 } else 4037 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4038 4039 /* XXX 5721, 5751 and 5752 */ 4040 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4041 /* Step 19: */ 4042 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4043 /* Step 20: */ 4044 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4045 } 4046 4047 /* Step 28: Fix up byte swapping */ 4048 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4049 4050 /* 4051 * Wait for the bootcode to complete initialization. 4052 * See BCM5718 programmer's guide's "step 13, Device reset Procedure, 4053 * Section 7". 4054 */ 4055 if (BGE_IS_5717_PLUS(sc)) { 4056 for (i = 0; i < 1000*1000; i++) { 4057 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4058 if (val == BGE_SRAM_FW_MB_RESET_MAGIC) 4059 break; 4060 DELAY(10); 4061 } 4062 } 4063 4064 /* Step 21: 5822 B0 errata */ 4065 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4066 pcireg_t msidata; 4067 4068 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4069 BGE_PCI_MSI_DATA); 4070 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4071 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4072 msidata); 4073 } 4074 4075 /* 4076 * Step 18: wirte mac mode 4077 * XXX Write 0x0c for 5703S and 5704S 4078 */ 4079 val = CSR_READ_4(sc, BGE_MAC_MODE); 4080 val = (val & ~mac_mode_mask) | mac_mode; 4081 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4082 DELAY(40); 4083 4084 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4085 4086 /* Step 17: Poll until the firmware initialization is complete */ 4087 bge_poll_fw(sc); 4088 4089 /* 4090 * The 5704 in TBI mode apparently needs some special 4091 * adjustment to insure the SERDES drive level is set 4092 * to 1.2V. 4093 */ 4094 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4095 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4096 uint32_t serdescfg; 4097 4098 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4099 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4100 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4101 } 4102 4103 if (sc->bge_flags & BGE_PCIE && 4104 !BGE_IS_57765_PLUS(sc) && 4105 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4106 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4107 uint32_t v; 4108 4109 /* Enable PCI Express bug fix */ 4110 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4111 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4112 v | BGE_TLP_DATA_FIFO_PROTECT); 4113 } 4114 4115 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4116 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4117 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4118 4119 return 0; 4120 } 4121 4122 /* 4123 * Frame reception handling. This is called if there's a frame 4124 * on the receive return list. 4125 * 4126 * Note: we have to be able to handle two possibilities here: 4127 * 1) the frame is from the jumbo receive ring 4128 * 2) the frame is from the standard receive ring 4129 */ 4130 4131 static void 4132 bge_rxeof(struct bge_softc *sc) 4133 { 4134 struct ifnet *ifp; 4135 uint16_t rx_prod, rx_cons; 4136 int stdcnt = 0, jumbocnt = 0; 4137 bus_dmamap_t dmamap; 4138 bus_addr_t offset, toff; 4139 bus_size_t tlen; 4140 int tosync; 4141 4142 rx_cons = sc->bge_rx_saved_considx; 4143 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4144 4145 /* Nothing to do */ 4146 if (rx_cons == rx_prod) 4147 return; 4148 4149 ifp = &sc->ethercom.ec_if; 4150 4151 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4152 offsetof(struct bge_ring_data, bge_status_block), 4153 sizeof (struct bge_status_block), 4154 BUS_DMASYNC_POSTREAD); 4155 4156 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4157 tosync = rx_prod - rx_cons; 4158 4159 if (tosync != 0) 4160 rnd_add_uint32(&sc->rnd_source, tosync); 4161 4162 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4163 4164 if (tosync < 0) { 4165 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4166 sizeof (struct bge_rx_bd); 4167 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4168 toff, tlen, BUS_DMASYNC_POSTREAD); 4169 tosync = -tosync; 4170 } 4171 4172 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4173 offset, tosync * sizeof (struct bge_rx_bd), 4174 BUS_DMASYNC_POSTREAD); 4175 4176 while (rx_cons != rx_prod) { 4177 struct bge_rx_bd *cur_rx; 4178 uint32_t rxidx; 4179 struct mbuf *m = NULL; 4180 4181 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4182 4183 rxidx = cur_rx->bge_idx; 4184 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4185 4186 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4187 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4188 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4189 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4190 jumbocnt++; 4191 bus_dmamap_sync(sc->bge_dmatag, 4192 sc->bge_cdata.bge_rx_jumbo_map, 4193 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4194 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4195 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4196 ifp->if_ierrors++; 4197 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4198 continue; 4199 } 4200 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4201 NULL)== ENOBUFS) { 4202 ifp->if_ierrors++; 4203 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4204 continue; 4205 } 4206 } else { 4207 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4208 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4209 4210 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4211 stdcnt++; 4212 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4213 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4214 if (dmamap == NULL) { 4215 ifp->if_ierrors++; 4216 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4217 continue; 4218 } 4219 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4220 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4221 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4222 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4223 ifp->if_ierrors++; 4224 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4225 continue; 4226 } 4227 if (bge_newbuf_std(sc, sc->bge_std, 4228 NULL, dmamap) == ENOBUFS) { 4229 ifp->if_ierrors++; 4230 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4231 continue; 4232 } 4233 } 4234 4235 ifp->if_ipackets++; 4236 #ifndef __NO_STRICT_ALIGNMENT 4237 /* 4238 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4239 * the Rx buffer has the layer-2 header unaligned. 4240 * If our CPU requires alignment, re-align by copying. 4241 */ 4242 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4243 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4244 cur_rx->bge_len); 4245 m->m_data += ETHER_ALIGN; 4246 } 4247 #endif 4248 4249 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4250 m->m_pkthdr.rcvif = ifp; 4251 4252 /* 4253 * Handle BPF listeners. Let the BPF user see the packet. 4254 */ 4255 bpf_mtap(ifp, m); 4256 4257 bge_rxcsum(sc, cur_rx, m); 4258 4259 /* 4260 * If we received a packet with a vlan tag, pass it 4261 * to vlan_input() instead of ether_input(). 4262 */ 4263 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4264 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4265 } 4266 4267 (*ifp->if_input)(ifp, m); 4268 } 4269 4270 sc->bge_rx_saved_considx = rx_cons; 4271 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4272 if (stdcnt) 4273 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4274 if (jumbocnt) 4275 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4276 } 4277 4278 static void 4279 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4280 { 4281 4282 if (BGE_IS_5717_PLUS(sc)) { 4283 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4284 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4285 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4286 if ((cur_rx->bge_error_flag & 4287 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4288 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4289 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4290 m->m_pkthdr.csum_data = 4291 cur_rx->bge_tcp_udp_csum; 4292 m->m_pkthdr.csum_flags |= 4293 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4294 M_CSUM_DATA); 4295 } 4296 } 4297 } else { 4298 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4299 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4300 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4301 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4302 /* 4303 * Rx transport checksum-offload may also 4304 * have bugs with packets which, when transmitted, 4305 * were `runts' requiring padding. 4306 */ 4307 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4308 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4309 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4310 m->m_pkthdr.csum_data = 4311 cur_rx->bge_tcp_udp_csum; 4312 m->m_pkthdr.csum_flags |= 4313 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4314 M_CSUM_DATA); 4315 } 4316 } 4317 } 4318 4319 static void 4320 bge_txeof(struct bge_softc *sc) 4321 { 4322 struct bge_tx_bd *cur_tx = NULL; 4323 struct ifnet *ifp; 4324 struct txdmamap_pool_entry *dma; 4325 bus_addr_t offset, toff; 4326 bus_size_t tlen; 4327 int tosync; 4328 struct mbuf *m; 4329 4330 ifp = &sc->ethercom.ec_if; 4331 4332 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4333 offsetof(struct bge_ring_data, bge_status_block), 4334 sizeof (struct bge_status_block), 4335 BUS_DMASYNC_POSTREAD); 4336 4337 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4338 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4339 sc->bge_tx_saved_considx; 4340 4341 if (tosync != 0) 4342 rnd_add_uint32(&sc->rnd_source, tosync); 4343 4344 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4345 4346 if (tosync < 0) { 4347 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4348 sizeof (struct bge_tx_bd); 4349 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4350 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4351 tosync = -tosync; 4352 } 4353 4354 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4355 offset, tosync * sizeof (struct bge_tx_bd), 4356 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4357 4358 /* 4359 * Go through our tx ring and free mbufs for those 4360 * frames that have been sent. 4361 */ 4362 while (sc->bge_tx_saved_considx != 4363 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4364 uint32_t idx = 0; 4365 4366 idx = sc->bge_tx_saved_considx; 4367 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4368 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4369 ifp->if_opackets++; 4370 m = sc->bge_cdata.bge_tx_chain[idx]; 4371 if (m != NULL) { 4372 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4373 dma = sc->txdma[idx]; 4374 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4375 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4376 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4377 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4378 sc->txdma[idx] = NULL; 4379 4380 m_freem(m); 4381 } 4382 sc->bge_txcnt--; 4383 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4384 ifp->if_timer = 0; 4385 } 4386 4387 if (cur_tx != NULL) 4388 ifp->if_flags &= ~IFF_OACTIVE; 4389 } 4390 4391 static int 4392 bge_intr(void *xsc) 4393 { 4394 struct bge_softc *sc; 4395 struct ifnet *ifp; 4396 uint32_t statusword; 4397 4398 sc = xsc; 4399 ifp = &sc->ethercom.ec_if; 4400 4401 /* It is possible for the interrupt to arrive before 4402 * the status block is updated prior to the interrupt. 4403 * Reading the PCI State register will confirm whether the 4404 * interrupt is ours and will flush the status block. 4405 */ 4406 4407 /* read status word from status block */ 4408 statusword = sc->bge_rdata->bge_status_block.bge_status; 4409 4410 if ((statusword & BGE_STATFLAG_UPDATED) || 4411 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4412 /* Ack interrupt and stop others from occuring. */ 4413 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4414 4415 BGE_EVCNT_INCR(sc->bge_ev_intr); 4416 4417 /* clear status word */ 4418 sc->bge_rdata->bge_status_block.bge_status = 0; 4419 4420 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4421 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4422 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4423 bge_link_upd(sc); 4424 4425 if (ifp->if_flags & IFF_RUNNING) { 4426 /* Check RX return ring producer/consumer */ 4427 bge_rxeof(sc); 4428 4429 /* Check TX ring producer/consumer */ 4430 bge_txeof(sc); 4431 } 4432 4433 if (sc->bge_pending_rxintr_change) { 4434 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4435 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4436 uint32_t junk; 4437 4438 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4439 DELAY(10); 4440 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4441 4442 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4443 DELAY(10); 4444 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4445 4446 sc->bge_pending_rxintr_change = 0; 4447 } 4448 bge_handle_events(sc); 4449 4450 /* Re-enable interrupts. */ 4451 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4452 4453 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4454 bge_start(ifp); 4455 4456 return 1; 4457 } else 4458 return 0; 4459 } 4460 4461 static void 4462 bge_asf_driver_up(struct bge_softc *sc) 4463 { 4464 if (sc->bge_asf_mode & ASF_STACKUP) { 4465 /* Send ASF heartbeat aprox. every 2s */ 4466 if (sc->bge_asf_count) 4467 sc->bge_asf_count --; 4468 else { 4469 sc->bge_asf_count = 2; 4470 4471 bge_wait_for_event_ack(sc); 4472 4473 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4474 BGE_FW_CMD_DRV_ALIVE); 4475 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4476 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4477 BGE_FW_HB_TIMEOUT_SEC); 4478 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4479 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4480 BGE_RX_CPU_DRV_EVENT); 4481 } 4482 } 4483 } 4484 4485 static void 4486 bge_tick(void *xsc) 4487 { 4488 struct bge_softc *sc = xsc; 4489 struct mii_data *mii = &sc->bge_mii; 4490 int s; 4491 4492 s = splnet(); 4493 4494 if (BGE_IS_5705_PLUS(sc)) 4495 bge_stats_update_regs(sc); 4496 else 4497 bge_stats_update(sc); 4498 4499 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4500 /* 4501 * Since in TBI mode auto-polling can't be used we should poll 4502 * link status manually. Here we register pending link event 4503 * and trigger interrupt. 4504 */ 4505 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4506 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4507 } else { 4508 /* 4509 * Do not touch PHY if we have link up. This could break 4510 * IPMI/ASF mode or produce extra input errors. 4511 * (extra input errors was reported for bcm5701 & bcm5704). 4512 */ 4513 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4514 mii_tick(mii); 4515 } 4516 4517 bge_asf_driver_up(sc); 4518 4519 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4520 4521 splx(s); 4522 } 4523 4524 static void 4525 bge_stats_update_regs(struct bge_softc *sc) 4526 { 4527 struct ifnet *ifp = &sc->ethercom.ec_if; 4528 4529 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4530 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4531 4532 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4533 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4534 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4535 } 4536 4537 static void 4538 bge_stats_update(struct bge_softc *sc) 4539 { 4540 struct ifnet *ifp = &sc->ethercom.ec_if; 4541 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4542 4543 #define READ_STAT(sc, stats, stat) \ 4544 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4545 4546 ifp->if_collisions += 4547 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4548 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4549 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4550 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4551 ifp->if_collisions; 4552 4553 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4554 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4555 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4556 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4557 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4558 READ_STAT(sc, stats, 4559 xoffPauseFramesReceived.bge_addr_lo)); 4560 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4561 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4562 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4563 READ_STAT(sc, stats, 4564 macControlFramesReceived.bge_addr_lo)); 4565 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4566 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4567 4568 #undef READ_STAT 4569 4570 #ifdef notdef 4571 ifp->if_collisions += 4572 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4573 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4574 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4575 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4576 ifp->if_collisions; 4577 #endif 4578 } 4579 4580 /* 4581 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4582 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4583 * but when such padded frames employ the bge IP/TCP checksum offload, 4584 * the hardware checksum assist gives incorrect results (possibly 4585 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4586 * If we pad such runts with zeros, the onboard checksum comes out correct. 4587 */ 4588 static inline int 4589 bge_cksum_pad(struct mbuf *pkt) 4590 { 4591 struct mbuf *last = NULL; 4592 int padlen; 4593 4594 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4595 4596 /* if there's only the packet-header and we can pad there, use it. */ 4597 if (pkt->m_pkthdr.len == pkt->m_len && 4598 M_TRAILINGSPACE(pkt) >= padlen) { 4599 last = pkt; 4600 } else { 4601 /* 4602 * Walk packet chain to find last mbuf. We will either 4603 * pad there, or append a new mbuf and pad it 4604 * (thus perhaps avoiding the bcm5700 dma-min bug). 4605 */ 4606 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4607 continue; /* do nothing */ 4608 } 4609 4610 /* `last' now points to last in chain. */ 4611 if (M_TRAILINGSPACE(last) < padlen) { 4612 /* Allocate new empty mbuf, pad it. Compact later. */ 4613 struct mbuf *n; 4614 MGET(n, M_DONTWAIT, MT_DATA); 4615 if (n == NULL) 4616 return ENOBUFS; 4617 n->m_len = 0; 4618 last->m_next = n; 4619 last = n; 4620 } 4621 } 4622 4623 KDASSERT(!M_READONLY(last)); 4624 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4625 4626 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4627 memset(mtod(last, char *) + last->m_len, 0, padlen); 4628 last->m_len += padlen; 4629 pkt->m_pkthdr.len += padlen; 4630 return 0; 4631 } 4632 4633 /* 4634 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4635 */ 4636 static inline int 4637 bge_compact_dma_runt(struct mbuf *pkt) 4638 { 4639 struct mbuf *m, *prev; 4640 int totlen, prevlen; 4641 4642 prev = NULL; 4643 totlen = 0; 4644 prevlen = -1; 4645 4646 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4647 int mlen = m->m_len; 4648 int shortfall = 8 - mlen ; 4649 4650 totlen += mlen; 4651 if (mlen == 0) 4652 continue; 4653 if (mlen >= 8) 4654 continue; 4655 4656 /* If we get here, mbuf data is too small for DMA engine. 4657 * Try to fix by shuffling data to prev or next in chain. 4658 * If that fails, do a compacting deep-copy of the whole chain. 4659 */ 4660 4661 /* Internal frag. If fits in prev, copy it there. */ 4662 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4663 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4664 prev->m_len += mlen; 4665 m->m_len = 0; 4666 /* XXX stitch chain */ 4667 prev->m_next = m_free(m); 4668 m = prev; 4669 continue; 4670 } 4671 else if (m->m_next != NULL && 4672 M_TRAILINGSPACE(m) >= shortfall && 4673 m->m_next->m_len >= (8 + shortfall)) { 4674 /* m is writable and have enough data in next, pull up. */ 4675 4676 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4677 shortfall); 4678 m->m_len += shortfall; 4679 m->m_next->m_len -= shortfall; 4680 m->m_next->m_data += shortfall; 4681 } 4682 else if (m->m_next == NULL || 1) { 4683 /* Got a runt at the very end of the packet. 4684 * borrow data from the tail of the preceding mbuf and 4685 * update its length in-place. (The original data is still 4686 * valid, so we can do this even if prev is not writable.) 4687 */ 4688 4689 /* if we'd make prev a runt, just move all of its data. */ 4690 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4691 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4692 4693 if ((prev->m_len - shortfall) < 8) 4694 shortfall = prev->m_len; 4695 4696 #ifdef notyet /* just do the safe slow thing for now */ 4697 if (!M_READONLY(m)) { 4698 if (M_LEADINGSPACE(m) < shorfall) { 4699 void *m_dat; 4700 m_dat = (m->m_flags & M_PKTHDR) ? 4701 m->m_pktdat : m->dat; 4702 memmove(m_dat, mtod(m, void*), m->m_len); 4703 m->m_data = m_dat; 4704 } 4705 } else 4706 #endif /* just do the safe slow thing */ 4707 { 4708 struct mbuf * n = NULL; 4709 int newprevlen = prev->m_len - shortfall; 4710 4711 MGET(n, M_NOWAIT, MT_DATA); 4712 if (n == NULL) 4713 return ENOBUFS; 4714 KASSERT(m->m_len + shortfall < MLEN 4715 /*, 4716 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4717 4718 /* first copy the data we're stealing from prev */ 4719 memcpy(n->m_data, prev->m_data + newprevlen, 4720 shortfall); 4721 4722 /* update prev->m_len accordingly */ 4723 prev->m_len -= shortfall; 4724 4725 /* copy data from runt m */ 4726 memcpy(n->m_data + shortfall, m->m_data, 4727 m->m_len); 4728 4729 /* n holds what we stole from prev, plus m */ 4730 n->m_len = shortfall + m->m_len; 4731 4732 /* stitch n into chain and free m */ 4733 n->m_next = m->m_next; 4734 prev->m_next = n; 4735 /* KASSERT(m->m_next == NULL); */ 4736 m->m_next = NULL; 4737 m_free(m); 4738 m = n; /* for continuing loop */ 4739 } 4740 } 4741 prevlen = m->m_len; 4742 } 4743 return 0; 4744 } 4745 4746 /* 4747 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4748 * pointers to descriptors. 4749 */ 4750 static int 4751 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4752 { 4753 struct bge_tx_bd *f = NULL; 4754 uint32_t frag, cur; 4755 uint16_t csum_flags = 0; 4756 uint16_t txbd_tso_flags = 0; 4757 struct txdmamap_pool_entry *dma; 4758 bus_dmamap_t dmamap; 4759 int i = 0; 4760 struct m_tag *mtag; 4761 int use_tso, maxsegsize, error; 4762 4763 cur = frag = *txidx; 4764 4765 if (m_head->m_pkthdr.csum_flags) { 4766 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4767 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4768 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4769 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4770 } 4771 4772 /* 4773 * If we were asked to do an outboard checksum, and the NIC 4774 * has the bug where it sometimes adds in the Ethernet padding, 4775 * explicitly pad with zeros so the cksum will be correct either way. 4776 * (For now, do this for all chip versions, until newer 4777 * are confirmed to not require the workaround.) 4778 */ 4779 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4780 #ifdef notyet 4781 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4782 #endif 4783 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4784 goto check_dma_bug; 4785 4786 if (bge_cksum_pad(m_head) != 0) 4787 return ENOBUFS; 4788 4789 check_dma_bug: 4790 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4791 goto doit; 4792 4793 /* 4794 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4795 * less than eight bytes. If we encounter a teeny mbuf 4796 * at the end of a chain, we can pad. Otherwise, copy. 4797 */ 4798 if (bge_compact_dma_runt(m_head) != 0) 4799 return ENOBUFS; 4800 4801 doit: 4802 dma = SLIST_FIRST(&sc->txdma_list); 4803 if (dma == NULL) 4804 return ENOBUFS; 4805 dmamap = dma->dmamap; 4806 4807 /* 4808 * Set up any necessary TSO state before we start packing... 4809 */ 4810 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4811 if (!use_tso) { 4812 maxsegsize = 0; 4813 } else { /* TSO setup */ 4814 unsigned mss; 4815 struct ether_header *eh; 4816 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4817 struct mbuf * m0 = m_head; 4818 struct ip *ip; 4819 struct tcphdr *th; 4820 int iphl, hlen; 4821 4822 /* 4823 * XXX It would be nice if the mbuf pkthdr had offset 4824 * fields for the protocol headers. 4825 */ 4826 4827 eh = mtod(m0, struct ether_header *); 4828 switch (htons(eh->ether_type)) { 4829 case ETHERTYPE_IP: 4830 offset = ETHER_HDR_LEN; 4831 break; 4832 4833 case ETHERTYPE_VLAN: 4834 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4835 break; 4836 4837 default: 4838 /* 4839 * Don't support this protocol or encapsulation. 4840 */ 4841 return ENOBUFS; 4842 } 4843 4844 /* 4845 * TCP/IP headers are in the first mbuf; we can do 4846 * this the easy way. 4847 */ 4848 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4849 hlen = iphl + offset; 4850 if (__predict_false(m0->m_len < 4851 (hlen + sizeof(struct tcphdr)))) { 4852 4853 aprint_debug_dev(sc->bge_dev, 4854 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4855 "not handled yet\n", 4856 m0->m_len, hlen+ sizeof(struct tcphdr)); 4857 #ifdef NOTYET 4858 /* 4859 * XXX jonathan (at) NetBSD.org: untested. 4860 * how to force this branch to be taken? 4861 */ 4862 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4863 4864 m_copydata(m0, offset, sizeof(ip), &ip); 4865 m_copydata(m0, hlen, sizeof(th), &th); 4866 4867 ip.ip_len = 0; 4868 4869 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4870 sizeof(ip.ip_len), &ip.ip_len); 4871 4872 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4873 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4874 4875 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4876 sizeof(th.th_sum), &th.th_sum); 4877 4878 hlen += th.th_off << 2; 4879 iptcp_opt_words = hlen; 4880 #else 4881 /* 4882 * if_wm "hard" case not yet supported, can we not 4883 * mandate it out of existence? 4884 */ 4885 (void) ip; (void)th; (void) ip_tcp_hlen; 4886 4887 return ENOBUFS; 4888 #endif 4889 } else { 4890 ip = (struct ip *) (mtod(m0, char *) + offset); 4891 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4892 ip_tcp_hlen = iphl + (th->th_off << 2); 4893 4894 /* Total IP/TCP options, in 32-bit words */ 4895 iptcp_opt_words = (ip_tcp_hlen 4896 - sizeof(struct tcphdr) 4897 - sizeof(struct ip)) >> 2; 4898 } 4899 if (BGE_IS_575X_PLUS(sc)) { 4900 th->th_sum = 0; 4901 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4902 } else { 4903 /* 4904 * XXX jonathan (at) NetBSD.org: 5705 untested. 4905 * Requires TSO firmware patch for 5701/5703/5704. 4906 */ 4907 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4908 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4909 } 4910 4911 mss = m_head->m_pkthdr.segsz; 4912 txbd_tso_flags |= 4913 BGE_TXBDFLAG_CPU_PRE_DMA | 4914 BGE_TXBDFLAG_CPU_POST_DMA; 4915 4916 /* 4917 * Our NIC TSO-assist assumes TSO has standard, optionless 4918 * IPv4 and TCP headers, which total 40 bytes. By default, 4919 * the NIC copies 40 bytes of IP/TCP header from the 4920 * supplied header into the IP/TCP header portion of 4921 * each post-TSO-segment. If the supplied packet has IP or 4922 * TCP options, we need to tell the NIC to copy those extra 4923 * bytes into each post-TSO header, in addition to the normal 4924 * 40-byte IP/TCP header (and to leave space accordingly). 4925 * Unfortunately, the driver encoding of option length 4926 * varies across different ASIC families. 4927 */ 4928 tcp_seg_flags = 0; 4929 if (iptcp_opt_words) { 4930 if (BGE_IS_5705_PLUS(sc)) { 4931 tcp_seg_flags = 4932 iptcp_opt_words << 11; 4933 } else { 4934 txbd_tso_flags |= 4935 iptcp_opt_words << 12; 4936 } 4937 } 4938 maxsegsize = mss | tcp_seg_flags; 4939 ip->ip_len = htons(mss + ip_tcp_hlen); 4940 4941 } /* TSO setup */ 4942 4943 /* 4944 * Start packing the mbufs in this chain into 4945 * the fragment pointers. Stop when we run out 4946 * of fragments or hit the end of the mbuf chain. 4947 */ 4948 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4949 BUS_DMA_NOWAIT); 4950 if (error) 4951 return ENOBUFS; 4952 /* 4953 * Sanity check: avoid coming within 16 descriptors 4954 * of the end of the ring. 4955 */ 4956 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4957 BGE_TSO_PRINTF(("%s: " 4958 " dmamap_load_mbuf too close to ring wrap\n", 4959 device_xname(sc->bge_dev))); 4960 goto fail_unload; 4961 } 4962 4963 mtag = sc->ethercom.ec_nvlans ? 4964 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4965 4966 4967 /* Iterate over dmap-map fragments. */ 4968 for (i = 0; i < dmamap->dm_nsegs; i++) { 4969 f = &sc->bge_rdata->bge_tx_ring[frag]; 4970 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4971 break; 4972 4973 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4974 f->bge_len = dmamap->dm_segs[i].ds_len; 4975 4976 /* 4977 * For 5751 and follow-ons, for TSO we must turn 4978 * off checksum-assist flag in the tx-descr, and 4979 * supply the ASIC-revision-specific encoding 4980 * of TSO flags and segsize. 4981 */ 4982 if (use_tso) { 4983 if (BGE_IS_575X_PLUS(sc) || i == 0) { 4984 f->bge_rsvd = maxsegsize; 4985 f->bge_flags = csum_flags | txbd_tso_flags; 4986 } else { 4987 f->bge_rsvd = 0; 4988 f->bge_flags = 4989 (csum_flags | txbd_tso_flags) & 0x0fff; 4990 } 4991 } else { 4992 f->bge_rsvd = 0; 4993 f->bge_flags = csum_flags; 4994 } 4995 4996 if (mtag != NULL) { 4997 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4998 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4999 } else { 5000 f->bge_vlan_tag = 0; 5001 } 5002 cur = frag; 5003 BGE_INC(frag, BGE_TX_RING_CNT); 5004 } 5005 5006 if (i < dmamap->dm_nsegs) { 5007 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5008 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5009 goto fail_unload; 5010 } 5011 5012 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5013 BUS_DMASYNC_PREWRITE); 5014 5015 if (frag == sc->bge_tx_saved_considx) { 5016 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5017 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5018 5019 goto fail_unload; 5020 } 5021 5022 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5023 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5024 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5025 sc->txdma[cur] = dma; 5026 sc->bge_txcnt += dmamap->dm_nsegs; 5027 5028 *txidx = frag; 5029 5030 return 0; 5031 5032 fail_unload: 5033 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5034 5035 return ENOBUFS; 5036 } 5037 5038 /* 5039 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5040 * to the mbuf data regions directly in the transmit descriptors. 5041 */ 5042 static void 5043 bge_start(struct ifnet *ifp) 5044 { 5045 struct bge_softc *sc; 5046 struct mbuf *m_head = NULL; 5047 uint32_t prodidx; 5048 int pkts = 0; 5049 5050 sc = ifp->if_softc; 5051 5052 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5053 return; 5054 5055 prodidx = sc->bge_tx_prodidx; 5056 5057 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5058 IFQ_POLL(&ifp->if_snd, m_head); 5059 if (m_head == NULL) 5060 break; 5061 5062 #if 0 5063 /* 5064 * XXX 5065 * safety overkill. If this is a fragmented packet chain 5066 * with delayed TCP/UDP checksums, then only encapsulate 5067 * it if we have enough descriptors to handle the entire 5068 * chain at once. 5069 * (paranoia -- may not actually be needed) 5070 */ 5071 if (m_head->m_flags & M_FIRSTFRAG && 5072 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5073 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5074 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5075 ifp->if_flags |= IFF_OACTIVE; 5076 break; 5077 } 5078 } 5079 #endif 5080 5081 /* 5082 * Pack the data into the transmit ring. If we 5083 * don't have room, set the OACTIVE flag and wait 5084 * for the NIC to drain the ring. 5085 */ 5086 if (bge_encap(sc, m_head, &prodidx)) { 5087 ifp->if_flags |= IFF_OACTIVE; 5088 break; 5089 } 5090 5091 /* now we are committed to transmit the packet */ 5092 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5093 pkts++; 5094 5095 /* 5096 * If there's a BPF listener, bounce a copy of this frame 5097 * to him. 5098 */ 5099 bpf_mtap(ifp, m_head); 5100 } 5101 if (pkts == 0) 5102 return; 5103 5104 /* Transmit */ 5105 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5106 /* 5700 b2 errata */ 5107 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5108 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5109 5110 sc->bge_tx_prodidx = prodidx; 5111 5112 /* 5113 * Set a timeout in case the chip goes out to lunch. 5114 */ 5115 ifp->if_timer = 5; 5116 } 5117 5118 static int 5119 bge_init(struct ifnet *ifp) 5120 { 5121 struct bge_softc *sc = ifp->if_softc; 5122 const uint16_t *m; 5123 uint32_t mode; 5124 int s, error = 0; 5125 5126 s = splnet(); 5127 5128 ifp = &sc->ethercom.ec_if; 5129 5130 /* Cancel pending I/O and flush buffers. */ 5131 bge_stop(ifp, 0); 5132 5133 bge_stop_fw(sc); 5134 bge_sig_pre_reset(sc, BGE_RESET_START); 5135 bge_reset(sc); 5136 bge_sig_legacy(sc, BGE_RESET_START); 5137 bge_sig_post_reset(sc, BGE_RESET_START); 5138 5139 bge_chipinit(sc); 5140 5141 /* 5142 * Init the various state machines, ring 5143 * control blocks and firmware. 5144 */ 5145 error = bge_blockinit(sc); 5146 if (error != 0) { 5147 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5148 error); 5149 splx(s); 5150 return error; 5151 } 5152 5153 ifp = &sc->ethercom.ec_if; 5154 5155 /* Specify MTU. */ 5156 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5157 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5158 5159 /* Load our MAC address. */ 5160 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5161 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5162 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5163 5164 /* Enable or disable promiscuous mode as needed. */ 5165 if (ifp->if_flags & IFF_PROMISC) 5166 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5167 else 5168 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5169 5170 /* Program multicast filter. */ 5171 bge_setmulti(sc); 5172 5173 /* Init RX ring. */ 5174 bge_init_rx_ring_std(sc); 5175 5176 /* 5177 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5178 * memory to insure that the chip has in fact read the first 5179 * entry of the ring. 5180 */ 5181 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5182 uint32_t v, i; 5183 for (i = 0; i < 10; i++) { 5184 DELAY(20); 5185 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5186 if (v == (MCLBYTES - ETHER_ALIGN)) 5187 break; 5188 } 5189 if (i == 10) 5190 aprint_error_dev(sc->bge_dev, 5191 "5705 A0 chip failed to load RX ring\n"); 5192 } 5193 5194 /* Init jumbo RX ring. */ 5195 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5196 bge_init_rx_ring_jumbo(sc); 5197 5198 /* Init our RX return ring index */ 5199 sc->bge_rx_saved_considx = 0; 5200 5201 /* Init TX ring. */ 5202 bge_init_tx_ring(sc); 5203 5204 /* Enable TX MAC state machine lockup fix. */ 5205 mode = CSR_READ_4(sc, BGE_TX_MODE); 5206 if (BGE_IS_5755_PLUS(sc) || 5207 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5208 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5209 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5210 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5211 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5212 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5213 } 5214 5215 /* Turn on transmitter */ 5216 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5217 DELAY(100); 5218 5219 /* Turn on receiver */ 5220 mode = CSR_READ_4(sc, BGE_RX_MODE); 5221 if (BGE_IS_5755_PLUS(sc)) 5222 mode |= BGE_RXMODE_IPV6_ENABLE; 5223 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5224 DELAY(10); 5225 5226 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5227 5228 /* Tell firmware we're alive. */ 5229 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5230 5231 /* Enable host interrupts. */ 5232 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5233 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5234 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5235 5236 if ((error = bge_ifmedia_upd(ifp)) != 0) 5237 goto out; 5238 5239 ifp->if_flags |= IFF_RUNNING; 5240 ifp->if_flags &= ~IFF_OACTIVE; 5241 5242 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5243 5244 out: 5245 sc->bge_if_flags = ifp->if_flags; 5246 splx(s); 5247 5248 return error; 5249 } 5250 5251 /* 5252 * Set media options. 5253 */ 5254 static int 5255 bge_ifmedia_upd(struct ifnet *ifp) 5256 { 5257 struct bge_softc *sc = ifp->if_softc; 5258 struct mii_data *mii = &sc->bge_mii; 5259 struct ifmedia *ifm = &sc->bge_ifmedia; 5260 int rc; 5261 5262 /* If this is a 1000baseX NIC, enable the TBI port. */ 5263 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5264 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5265 return EINVAL; 5266 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5267 case IFM_AUTO: 5268 /* 5269 * The BCM5704 ASIC appears to have a special 5270 * mechanism for programming the autoneg 5271 * advertisement registers in TBI mode. 5272 */ 5273 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5274 uint32_t sgdig; 5275 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5276 if (sgdig & BGE_SGDIGSTS_DONE) { 5277 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5278 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5279 sgdig |= BGE_SGDIGCFG_AUTO | 5280 BGE_SGDIGCFG_PAUSE_CAP | 5281 BGE_SGDIGCFG_ASYM_PAUSE; 5282 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5283 sgdig | BGE_SGDIGCFG_SEND); 5284 DELAY(5); 5285 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5286 sgdig); 5287 } 5288 } 5289 break; 5290 case IFM_1000_SX: 5291 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5292 BGE_CLRBIT(sc, BGE_MAC_MODE, 5293 BGE_MACMODE_HALF_DUPLEX); 5294 } else { 5295 BGE_SETBIT(sc, BGE_MAC_MODE, 5296 BGE_MACMODE_HALF_DUPLEX); 5297 } 5298 DELAY(40); 5299 break; 5300 default: 5301 return EINVAL; 5302 } 5303 /* XXX 802.3x flow control for 1000BASE-SX */ 5304 return 0; 5305 } 5306 5307 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5308 if ((rc = mii_mediachg(mii)) == ENXIO) 5309 return 0; 5310 5311 /* 5312 * Force an interrupt so that we will call bge_link_upd 5313 * if needed and clear any pending link state attention. 5314 * Without this we are not getting any further interrupts 5315 * for link state changes and thus will not UP the link and 5316 * not be able to send in bge_start. The only way to get 5317 * things working was to receive a packet and get a RX intr. 5318 */ 5319 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5320 sc->bge_flags & BGE_IS_5788) 5321 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5322 else 5323 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5324 5325 return rc; 5326 } 5327 5328 /* 5329 * Report current media status. 5330 */ 5331 static void 5332 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5333 { 5334 struct bge_softc *sc = ifp->if_softc; 5335 struct mii_data *mii = &sc->bge_mii; 5336 5337 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5338 ifmr->ifm_status = IFM_AVALID; 5339 ifmr->ifm_active = IFM_ETHER; 5340 if (CSR_READ_4(sc, BGE_MAC_STS) & 5341 BGE_MACSTAT_TBI_PCS_SYNCHED) 5342 ifmr->ifm_status |= IFM_ACTIVE; 5343 ifmr->ifm_active |= IFM_1000_SX; 5344 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5345 ifmr->ifm_active |= IFM_HDX; 5346 else 5347 ifmr->ifm_active |= IFM_FDX; 5348 return; 5349 } 5350 5351 mii_pollstat(mii); 5352 ifmr->ifm_status = mii->mii_media_status; 5353 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5354 sc->bge_flowflags; 5355 } 5356 5357 static int 5358 bge_ifflags_cb(struct ethercom *ec) 5359 { 5360 struct ifnet *ifp = &ec->ec_if; 5361 struct bge_softc *sc = ifp->if_softc; 5362 int change = ifp->if_flags ^ sc->bge_if_flags; 5363 5364 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5365 return ENETRESET; 5366 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5367 return 0; 5368 5369 if ((ifp->if_flags & IFF_PROMISC) == 0) 5370 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5371 else 5372 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5373 5374 bge_setmulti(sc); 5375 5376 sc->bge_if_flags = ifp->if_flags; 5377 return 0; 5378 } 5379 5380 static int 5381 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5382 { 5383 struct bge_softc *sc = ifp->if_softc; 5384 struct ifreq *ifr = (struct ifreq *) data; 5385 int s, error = 0; 5386 struct mii_data *mii; 5387 5388 s = splnet(); 5389 5390 switch (command) { 5391 case SIOCSIFMEDIA: 5392 /* XXX Flow control is not supported for 1000BASE-SX */ 5393 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5394 ifr->ifr_media &= ~IFM_ETH_FMASK; 5395 sc->bge_flowflags = 0; 5396 } 5397 5398 /* Flow control requires full-duplex mode. */ 5399 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5400 (ifr->ifr_media & IFM_FDX) == 0) { 5401 ifr->ifr_media &= ~IFM_ETH_FMASK; 5402 } 5403 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5404 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5405 /* We can do both TXPAUSE and RXPAUSE. */ 5406 ifr->ifr_media |= 5407 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5408 } 5409 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5410 } 5411 /* FALLTHROUGH */ 5412 case SIOCGIFMEDIA: 5413 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5414 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5415 command); 5416 } else { 5417 mii = &sc->bge_mii; 5418 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5419 command); 5420 } 5421 break; 5422 default: 5423 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5424 break; 5425 5426 error = 0; 5427 5428 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5429 ; 5430 else if (ifp->if_flags & IFF_RUNNING) 5431 bge_setmulti(sc); 5432 break; 5433 } 5434 5435 splx(s); 5436 5437 return error; 5438 } 5439 5440 static void 5441 bge_watchdog(struct ifnet *ifp) 5442 { 5443 struct bge_softc *sc; 5444 5445 sc = ifp->if_softc; 5446 5447 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5448 5449 ifp->if_flags &= ~IFF_RUNNING; 5450 bge_init(ifp); 5451 5452 ifp->if_oerrors++; 5453 } 5454 5455 static void 5456 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5457 { 5458 int i; 5459 5460 BGE_CLRBIT_FLUSH(sc, reg, bit); 5461 5462 for (i = 0; i < 1000; i++) { 5463 delay(100); 5464 if ((CSR_READ_4(sc, reg) & bit) == 0) 5465 return; 5466 } 5467 5468 /* 5469 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5470 * on some environment (and once after boot?) 5471 */ 5472 if (reg != BGE_SRS_MODE) 5473 aprint_error_dev(sc->bge_dev, 5474 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5475 (u_long)reg, bit); 5476 } 5477 5478 /* 5479 * Stop the adapter and free any mbufs allocated to the 5480 * RX and TX lists. 5481 */ 5482 static void 5483 bge_stop(struct ifnet *ifp, int disable) 5484 { 5485 struct bge_softc *sc = ifp->if_softc; 5486 5487 callout_stop(&sc->bge_timeout); 5488 5489 /* Disable host interrupts. */ 5490 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5491 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5492 5493 /* 5494 * Tell firmware we're shutting down. 5495 */ 5496 bge_stop_fw(sc); 5497 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5498 5499 /* 5500 * Disable all of the receiver blocks. 5501 */ 5502 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5503 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5504 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5505 if (BGE_IS_5700_FAMILY(sc)) 5506 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5507 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5508 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5509 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5510 5511 /* 5512 * Disable all of the transmit blocks. 5513 */ 5514 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5515 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5516 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5517 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5518 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5519 if (BGE_IS_5700_FAMILY(sc)) 5520 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5521 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5522 5523 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5524 delay(40); 5525 5526 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5527 5528 /* 5529 * Shut down all of the memory managers and related 5530 * state machines. 5531 */ 5532 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5533 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5534 if (BGE_IS_5700_FAMILY(sc)) 5535 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5536 5537 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5538 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5539 5540 if (BGE_IS_5700_FAMILY(sc)) { 5541 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5542 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5543 } 5544 5545 bge_reset(sc); 5546 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5547 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5548 5549 /* 5550 * Keep the ASF firmware running if up. 5551 */ 5552 if (sc->bge_asf_mode & ASF_STACKUP) 5553 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5554 else 5555 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5556 5557 /* Free the RX lists. */ 5558 bge_free_rx_ring_std(sc); 5559 5560 /* Free jumbo RX list. */ 5561 if (BGE_IS_JUMBO_CAPABLE(sc)) 5562 bge_free_rx_ring_jumbo(sc); 5563 5564 /* Free TX buffers. */ 5565 bge_free_tx_ring(sc); 5566 5567 /* 5568 * Isolate/power down the PHY. 5569 */ 5570 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5571 mii_down(&sc->bge_mii); 5572 5573 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5574 5575 /* Clear MAC's link state (PHY may still have link UP). */ 5576 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5577 5578 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5579 } 5580 5581 static void 5582 bge_link_upd(struct bge_softc *sc) 5583 { 5584 struct ifnet *ifp = &sc->ethercom.ec_if; 5585 struct mii_data *mii = &sc->bge_mii; 5586 uint32_t status; 5587 int link; 5588 5589 /* Clear 'pending link event' flag */ 5590 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5591 5592 /* 5593 * Process link state changes. 5594 * Grrr. The link status word in the status block does 5595 * not work correctly on the BCM5700 rev AX and BX chips, 5596 * according to all available information. Hence, we have 5597 * to enable MII interrupts in order to properly obtain 5598 * async link changes. Unfortunately, this also means that 5599 * we have to read the MAC status register to detect link 5600 * changes, thereby adding an additional register access to 5601 * the interrupt handler. 5602 */ 5603 5604 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5605 status = CSR_READ_4(sc, BGE_MAC_STS); 5606 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5607 mii_pollstat(mii); 5608 5609 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5610 mii->mii_media_status & IFM_ACTIVE && 5611 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5612 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5613 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5614 (!(mii->mii_media_status & IFM_ACTIVE) || 5615 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5616 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5617 5618 /* Clear the interrupt */ 5619 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5620 BGE_EVTENB_MI_INTERRUPT); 5621 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5622 BRGPHY_MII_ISR); 5623 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5624 BRGPHY_MII_IMR, BRGPHY_INTRS); 5625 } 5626 return; 5627 } 5628 5629 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5630 status = CSR_READ_4(sc, BGE_MAC_STS); 5631 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5632 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5633 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5634 if (BGE_ASICREV(sc->bge_chipid) 5635 == BGE_ASICREV_BCM5704) { 5636 BGE_CLRBIT(sc, BGE_MAC_MODE, 5637 BGE_MACMODE_TBI_SEND_CFGS); 5638 DELAY(40); 5639 } 5640 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5641 if_link_state_change(ifp, LINK_STATE_UP); 5642 } 5643 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5644 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5645 if_link_state_change(ifp, LINK_STATE_DOWN); 5646 } 5647 /* 5648 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5649 * This should not happen since mii callouts are locked now, but 5650 * we keep this check for debug. 5651 */ 5652 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5653 /* 5654 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5655 * bit in status word always set. Workaround this bug by 5656 * reading PHY link status directly. 5657 */ 5658 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5659 BGE_STS_LINK : 0; 5660 5661 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5662 mii_pollstat(mii); 5663 5664 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5665 mii->mii_media_status & IFM_ACTIVE && 5666 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5667 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5668 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5669 (!(mii->mii_media_status & IFM_ACTIVE) || 5670 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5671 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5672 } 5673 } 5674 5675 /* Clear the attention */ 5676 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5677 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5678 BGE_MACSTAT_LINK_CHANGED); 5679 } 5680 5681 static int 5682 bge_sysctl_verify(SYSCTLFN_ARGS) 5683 { 5684 int error, t; 5685 struct sysctlnode node; 5686 5687 node = *rnode; 5688 t = *(int*)rnode->sysctl_data; 5689 node.sysctl_data = &t; 5690 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5691 if (error || newp == NULL) 5692 return error; 5693 5694 #if 0 5695 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5696 node.sysctl_num, rnode->sysctl_num)); 5697 #endif 5698 5699 if (node.sysctl_num == bge_rxthresh_nodenum) { 5700 if (t < 0 || t >= NBGE_RX_THRESH) 5701 return EINVAL; 5702 bge_update_all_threshes(t); 5703 } else 5704 return EINVAL; 5705 5706 *(int*)rnode->sysctl_data = t; 5707 5708 return 0; 5709 } 5710 5711 /* 5712 * Set up sysctl(3) MIB, hw.bge.*. 5713 */ 5714 static void 5715 bge_sysctl_init(struct bge_softc *sc) 5716 { 5717 int rc, bge_root_num; 5718 const struct sysctlnode *node; 5719 5720 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5721 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5722 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5723 goto out; 5724 } 5725 5726 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5727 0, CTLTYPE_NODE, "bge", 5728 SYSCTL_DESCR("BGE interface controls"), 5729 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5730 goto out; 5731 } 5732 5733 bge_root_num = node->sysctl_num; 5734 5735 /* BGE Rx interrupt mitigation level */ 5736 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5737 CTLFLAG_READWRITE, 5738 CTLTYPE_INT, "rx_lvl", 5739 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5740 bge_sysctl_verify, 0, 5741 &bge_rx_thresh_lvl, 5742 0, CTL_HW, bge_root_num, CTL_CREATE, 5743 CTL_EOL)) != 0) { 5744 goto out; 5745 } 5746 5747 bge_rxthresh_nodenum = node->sysctl_num; 5748 5749 return; 5750 5751 out: 5752 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5753 } 5754 5755 #ifdef BGE_DEBUG 5756 void 5757 bge_debug_info(struct bge_softc *sc) 5758 { 5759 5760 printf("Hardware Flags:\n"); 5761 if (BGE_IS_57765_PLUS(sc)) 5762 printf(" - 57765 Plus\n"); 5763 if (BGE_IS_5717_PLUS(sc)) 5764 printf(" - 5717 Plus\n"); 5765 if (BGE_IS_5755_PLUS(sc)) 5766 printf(" - 5755 Plus\n"); 5767 if (BGE_IS_575X_PLUS(sc)) 5768 printf(" - 575X Plus\n"); 5769 if (BGE_IS_5705_PLUS(sc)) 5770 printf(" - 5705 Plus\n"); 5771 if (BGE_IS_5714_FAMILY(sc)) 5772 printf(" - 5714 Family\n"); 5773 if (BGE_IS_5700_FAMILY(sc)) 5774 printf(" - 5700 Family\n"); 5775 if (sc->bge_flags & BGE_IS_5788) 5776 printf(" - 5788\n"); 5777 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5778 printf(" - Supports Jumbo Frames\n"); 5779 if (sc->bge_flags & BGE_NO_EEPROM) 5780 printf(" - No EEPROM\n"); 5781 if (sc->bge_flags & BGE_PCIX) 5782 printf(" - PCI-X Bus\n"); 5783 if (sc->bge_flags & BGE_PCIE) 5784 printf(" - PCI Express Bus\n"); 5785 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5786 printf(" - RX Alignment Bug\n"); 5787 if (sc->bge_flags & BGE_APE) 5788 printf(" - APE\n"); 5789 if (sc->bge_flags & BGE_CPMU_PRESENT) 5790 printf(" - CPMU\n"); 5791 if (sc->bge_flags & BGE_TSO) 5792 printf(" - TSO\n"); 5793 5794 if (sc->bge_flags & BGE_PHY_NO_3LED) 5795 printf(" - No 3 LEDs\n"); 5796 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5797 printf(" - CRC bug\n"); 5798 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5799 printf(" - ADC bug\n"); 5800 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5801 printf(" - 5704 A0 bug\n"); 5802 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5803 printf(" - jitter bug\n"); 5804 if (sc->bge_flags & BGE_PHY_BER_BUG) 5805 printf(" - BER bug\n"); 5806 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5807 printf(" - adjust trim\n"); 5808 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5809 printf(" - no wirespeed\n"); 5810 } 5811 #endif /* BGE_DEBUG */ 5812 5813 static int 5814 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5815 { 5816 prop_dictionary_t dict; 5817 prop_data_t ea; 5818 5819 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5820 return 1; 5821 5822 dict = device_properties(sc->bge_dev); 5823 ea = prop_dictionary_get(dict, "mac-address"); 5824 if (ea != NULL) { 5825 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5826 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5827 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5828 return 0; 5829 } 5830 5831 return 1; 5832 } 5833 5834 static int 5835 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5836 { 5837 uint32_t mac_addr; 5838 5839 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5840 if ((mac_addr >> 16) == 0x484b) { 5841 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5842 ether_addr[1] = (uint8_t)mac_addr; 5843 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5844 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5845 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5846 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5847 ether_addr[5] = (uint8_t)mac_addr; 5848 return 0; 5849 } 5850 return 1; 5851 } 5852 5853 static int 5854 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5855 { 5856 int mac_offset = BGE_EE_MAC_OFFSET; 5857 5858 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5859 mac_offset = BGE_EE_MAC_OFFSET_5906; 5860 5861 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5862 ETHER_ADDR_LEN)); 5863 } 5864 5865 static int 5866 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5867 { 5868 5869 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5870 return 1; 5871 5872 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5873 ETHER_ADDR_LEN)); 5874 } 5875 5876 static int 5877 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5878 { 5879 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5880 /* NOTE: Order is critical */ 5881 bge_get_eaddr_fw, 5882 bge_get_eaddr_mem, 5883 bge_get_eaddr_nvram, 5884 bge_get_eaddr_eeprom, 5885 NULL 5886 }; 5887 const bge_eaddr_fcn_t *func; 5888 5889 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5890 if ((*func)(sc, eaddr) == 0) 5891 break; 5892 } 5893 return (*func == NULL ? ENXIO : 0); 5894 } 5895
Indexes created Wed Sep 24 02:09:48 GMT 2025