if_bge.c revision 1.228
1 /* $NetBSD: if_bge.c,v 1.228 2013/03/27 10:26:05 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.228 2013/03/27 10:26:05 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static int bge_detach(device_t, int); 191 static void bge_release_resources(struct bge_softc *); 192 193 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 198 199 static void bge_txeof(struct bge_softc *); 200 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 201 static void bge_rxeof(struct bge_softc *); 202 203 static void bge_asf_driver_up (struct bge_softc *); 204 static void bge_tick(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static void bge_stats_update_regs(struct bge_softc *); 207 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 208 209 static int bge_intr(void *); 210 static void bge_start(struct ifnet *); 211 static int bge_ifflags_cb(struct ethercom *); 212 static int bge_ioctl(struct ifnet *, u_long, void *); 213 static int bge_init(struct ifnet *); 214 static void bge_stop(struct ifnet *, int); 215 static void bge_watchdog(struct ifnet *); 216 static int bge_ifmedia_upd(struct ifnet *); 217 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 219 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 221 222 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 223 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 224 static void bge_setmulti(struct bge_softc *); 225 226 static void bge_handle_events(struct bge_softc *); 227 static int bge_alloc_jumbo_mem(struct bge_softc *); 228 #if 0 /* XXX */ 229 static void bge_free_jumbo_mem(struct bge_softc *); 230 #endif 231 static void *bge_jalloc(struct bge_softc *); 232 static void bge_jfree(struct mbuf *, void *, size_t, void *); 233 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 234 bus_dmamap_t); 235 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 236 static int bge_init_rx_ring_std(struct bge_softc *); 237 static void bge_free_rx_ring_std(struct bge_softc *); 238 static int bge_init_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_rx_ring_jumbo(struct bge_softc *); 240 static void bge_free_tx_ring(struct bge_softc *); 241 static int bge_init_tx_ring(struct bge_softc *); 242 243 static int bge_chipinit(struct bge_softc *); 244 static int bge_blockinit(struct bge_softc *); 245 static int bge_phy_addr(struct bge_softc *); 246 static uint32_t bge_readmem_ind(struct bge_softc *, int); 247 static void bge_writemem_ind(struct bge_softc *, int, int); 248 static void bge_writembx(struct bge_softc *, int, int); 249 static void bge_writembx_flush(struct bge_softc *, int, int); 250 static void bge_writemem_direct(struct bge_softc *, int, int); 251 static void bge_writereg_ind(struct bge_softc *, int, int); 252 static void bge_set_max_readrq(struct bge_softc *); 253 254 static int bge_miibus_readreg(device_t, int, int); 255 static void bge_miibus_writereg(device_t, int, int, int); 256 static void bge_miibus_statchg(struct ifnet *); 257 258 #define BGE_RESET_SHUTDOWN 0 259 #define BGE_RESET_START 1 260 #define BGE_RESET_SUSPEND 2 261 static void bge_sig_post_reset(struct bge_softc *, int); 262 static void bge_sig_legacy(struct bge_softc *, int); 263 static void bge_sig_pre_reset(struct bge_softc *, int); 264 static void bge_wait_for_event_ack(struct bge_softc *); 265 static void bge_stop_fw(struct bge_softc *); 266 static int bge_reset(struct bge_softc *); 267 static void bge_link_upd(struct bge_softc *); 268 static void bge_sysctl_init(struct bge_softc *); 269 static int bge_sysctl_verify(SYSCTLFN_PROTO); 270 271 static void bge_ape_lock_init(struct bge_softc *); 272 static void bge_ape_read_fw_ver(struct bge_softc *); 273 static int bge_ape_lock(struct bge_softc *, int); 274 static void bge_ape_unlock(struct bge_softc *, int); 275 static void bge_ape_send_event(struct bge_softc *, uint32_t); 276 static void bge_ape_driver_state_change(struct bge_softc *, int); 277 278 #ifdef BGE_DEBUG 279 #define DPRINTF(x) if (bgedebug) printf x 280 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 281 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 282 int bgedebug = 0; 283 int bge_tso_debug = 0; 284 void bge_debug_info(struct bge_softc *); 285 #else 286 #define DPRINTF(x) 287 #define DPRINTFN(n,x) 288 #define BGE_TSO_PRINTF(x) 289 #endif 290 291 #ifdef BGE_EVENT_COUNTERS 292 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 293 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 294 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 295 #else 296 #define BGE_EVCNT_INCR(ev) /* nothing */ 297 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 298 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 299 #endif 300 301 static const struct bge_product { 302 pci_vendor_id_t bp_vendor; 303 pci_product_id_t bp_product; 304 const char *bp_name; 305 } bge_products[] = { 306 /* 307 * The BCM5700 documentation seems to indicate that the hardware 308 * still has the Alteon vendor ID burned into it, though it 309 * should always be overridden by the value in the EEPROM. We'll 310 * check for it anyway. 311 */ 312 { PCI_VENDOR_ALTEON, 313 PCI_PRODUCT_ALTEON_BCM5700, 314 "Broadcom BCM5700 Gigabit Ethernet", 315 }, 316 { PCI_VENDOR_ALTEON, 317 PCI_PRODUCT_ALTEON_BCM5701, 318 "Broadcom BCM5701 Gigabit Ethernet", 319 }, 320 { PCI_VENDOR_ALTIMA, 321 PCI_PRODUCT_ALTIMA_AC1000, 322 "Altima AC1000 Gigabit Ethernet", 323 }, 324 { PCI_VENDOR_ALTIMA, 325 PCI_PRODUCT_ALTIMA_AC1001, 326 "Altima AC1001 Gigabit Ethernet", 327 }, 328 { PCI_VENDOR_ALTIMA, 329 PCI_PRODUCT_ALTIMA_AC1003, 330 "Altima AC1003 Gigabit Ethernet", 331 }, 332 { PCI_VENDOR_ALTIMA, 333 PCI_PRODUCT_ALTIMA_AC9100, 334 "Altima AC9100 Gigabit Ethernet", 335 }, 336 { PCI_VENDOR_APPLE, 337 PCI_PRODUCT_APPLE_BCM5701, 338 "APPLE BCM5701 Gigabit Ethernet", 339 }, 340 { PCI_VENDOR_BROADCOM, 341 PCI_PRODUCT_BROADCOM_BCM5700, 342 "Broadcom BCM5700 Gigabit Ethernet", 343 }, 344 { PCI_VENDOR_BROADCOM, 345 PCI_PRODUCT_BROADCOM_BCM5701, 346 "Broadcom BCM5701 Gigabit Ethernet", 347 }, 348 { PCI_VENDOR_BROADCOM, 349 PCI_PRODUCT_BROADCOM_BCM5702, 350 "Broadcom BCM5702 Gigabit Ethernet", 351 }, 352 { PCI_VENDOR_BROADCOM, 353 PCI_PRODUCT_BROADCOM_BCM5702X, 354 "Broadcom BCM5702X Gigabit Ethernet" }, 355 { PCI_VENDOR_BROADCOM, 356 PCI_PRODUCT_BROADCOM_BCM5703, 357 "Broadcom BCM5703 Gigabit Ethernet", 358 }, 359 { PCI_VENDOR_BROADCOM, 360 PCI_PRODUCT_BROADCOM_BCM5703X, 361 "Broadcom BCM5703X Gigabit Ethernet", 362 }, 363 { PCI_VENDOR_BROADCOM, 364 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 365 "Broadcom BCM5703 Gigabit Ethernet", 366 }, 367 { PCI_VENDOR_BROADCOM, 368 PCI_PRODUCT_BROADCOM_BCM5704C, 369 "Broadcom BCM5704C Dual Gigabit Ethernet", 370 }, 371 { PCI_VENDOR_BROADCOM, 372 PCI_PRODUCT_BROADCOM_BCM5704S, 373 "Broadcom BCM5704S Dual Gigabit Ethernet", 374 }, 375 { PCI_VENDOR_BROADCOM, 376 PCI_PRODUCT_BROADCOM_BCM5705, 377 "Broadcom BCM5705 Gigabit Ethernet", 378 }, 379 { PCI_VENDOR_BROADCOM, 380 PCI_PRODUCT_BROADCOM_BCM5705F, 381 "Broadcom BCM5705F Gigabit Ethernet", 382 }, 383 { PCI_VENDOR_BROADCOM, 384 PCI_PRODUCT_BROADCOM_BCM5705K, 385 "Broadcom BCM5705K Gigabit Ethernet", 386 }, 387 { PCI_VENDOR_BROADCOM, 388 PCI_PRODUCT_BROADCOM_BCM5705M, 389 "Broadcom BCM5705M Gigabit Ethernet", 390 }, 391 { PCI_VENDOR_BROADCOM, 392 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 393 "Broadcom BCM5705M Gigabit Ethernet", 394 }, 395 { PCI_VENDOR_BROADCOM, 396 PCI_PRODUCT_BROADCOM_BCM5714, 397 "Broadcom BCM5714 Gigabit Ethernet", 398 }, 399 { PCI_VENDOR_BROADCOM, 400 PCI_PRODUCT_BROADCOM_BCM5714S, 401 "Broadcom BCM5714S Gigabit Ethernet", 402 }, 403 { PCI_VENDOR_BROADCOM, 404 PCI_PRODUCT_BROADCOM_BCM5715, 405 "Broadcom BCM5715 Gigabit Ethernet", 406 }, 407 { PCI_VENDOR_BROADCOM, 408 PCI_PRODUCT_BROADCOM_BCM5715S, 409 "Broadcom BCM5715S Gigabit Ethernet", 410 }, 411 { PCI_VENDOR_BROADCOM, 412 PCI_PRODUCT_BROADCOM_BCM5717, 413 "Broadcom BCM5717 Gigabit Ethernet", 414 }, 415 { PCI_VENDOR_BROADCOM, 416 PCI_PRODUCT_BROADCOM_BCM5718, 417 "Broadcom BCM5718 Gigabit Ethernet", 418 }, 419 { PCI_VENDOR_BROADCOM, 420 PCI_PRODUCT_BROADCOM_BCM5719, 421 "Broadcom BCM5719 Gigabit Ethernet", 422 }, 423 { PCI_VENDOR_BROADCOM, 424 PCI_PRODUCT_BROADCOM_BCM5720, 425 "Broadcom BCM5720 Gigabit Ethernet", 426 }, 427 { PCI_VENDOR_BROADCOM, 428 PCI_PRODUCT_BROADCOM_BCM5721, 429 "Broadcom BCM5721 Gigabit Ethernet", 430 }, 431 { PCI_VENDOR_BROADCOM, 432 PCI_PRODUCT_BROADCOM_BCM5722, 433 "Broadcom BCM5722 Gigabit Ethernet", 434 }, 435 { PCI_VENDOR_BROADCOM, 436 PCI_PRODUCT_BROADCOM_BCM5723, 437 "Broadcom BCM5723 Gigabit Ethernet", 438 }, 439 { PCI_VENDOR_BROADCOM, 440 PCI_PRODUCT_BROADCOM_BCM5724, 441 "Broadcom BCM5724 Gigabit Ethernet", 442 }, 443 { PCI_VENDOR_BROADCOM, 444 PCI_PRODUCT_BROADCOM_BCM5750, 445 "Broadcom BCM5750 Gigabit Ethernet", 446 }, 447 { PCI_VENDOR_BROADCOM, 448 PCI_PRODUCT_BROADCOM_BCM5750M, 449 "Broadcom BCM5750M Gigabit Ethernet", 450 }, 451 { PCI_VENDOR_BROADCOM, 452 PCI_PRODUCT_BROADCOM_BCM5751, 453 "Broadcom BCM5751 Gigabit Ethernet", 454 }, 455 { PCI_VENDOR_BROADCOM, 456 PCI_PRODUCT_BROADCOM_BCM5751F, 457 "Broadcom BCM5751F Gigabit Ethernet", 458 }, 459 { PCI_VENDOR_BROADCOM, 460 PCI_PRODUCT_BROADCOM_BCM5751M, 461 "Broadcom BCM5751M Gigabit Ethernet", 462 }, 463 { PCI_VENDOR_BROADCOM, 464 PCI_PRODUCT_BROADCOM_BCM5752, 465 "Broadcom BCM5752 Gigabit Ethernet", 466 }, 467 { PCI_VENDOR_BROADCOM, 468 PCI_PRODUCT_BROADCOM_BCM5752M, 469 "Broadcom BCM5752M Gigabit Ethernet", 470 }, 471 { PCI_VENDOR_BROADCOM, 472 PCI_PRODUCT_BROADCOM_BCM5753, 473 "Broadcom BCM5753 Gigabit Ethernet", 474 }, 475 { PCI_VENDOR_BROADCOM, 476 PCI_PRODUCT_BROADCOM_BCM5753F, 477 "Broadcom BCM5753F Gigabit Ethernet", 478 }, 479 { PCI_VENDOR_BROADCOM, 480 PCI_PRODUCT_BROADCOM_BCM5753M, 481 "Broadcom BCM5753M Gigabit Ethernet", 482 }, 483 { PCI_VENDOR_BROADCOM, 484 PCI_PRODUCT_BROADCOM_BCM5754, 485 "Broadcom BCM5754 Gigabit Ethernet", 486 }, 487 { PCI_VENDOR_BROADCOM, 488 PCI_PRODUCT_BROADCOM_BCM5754M, 489 "Broadcom BCM5754M Gigabit Ethernet", 490 }, 491 { PCI_VENDOR_BROADCOM, 492 PCI_PRODUCT_BROADCOM_BCM5755, 493 "Broadcom BCM5755 Gigabit Ethernet", 494 }, 495 { PCI_VENDOR_BROADCOM, 496 PCI_PRODUCT_BROADCOM_BCM5755M, 497 "Broadcom BCM5755M Gigabit Ethernet", 498 }, 499 { PCI_VENDOR_BROADCOM, 500 PCI_PRODUCT_BROADCOM_BCM5756, 501 "Broadcom BCM5756 Gigabit Ethernet", 502 }, 503 { PCI_VENDOR_BROADCOM, 504 PCI_PRODUCT_BROADCOM_BCM5761, 505 "Broadcom BCM5761 Gigabit Ethernet", 506 }, 507 { PCI_VENDOR_BROADCOM, 508 PCI_PRODUCT_BROADCOM_BCM5761E, 509 "Broadcom BCM5761E Gigabit Ethernet", 510 }, 511 { PCI_VENDOR_BROADCOM, 512 PCI_PRODUCT_BROADCOM_BCM5761S, 513 "Broadcom BCM5761S Gigabit Ethernet", 514 }, 515 { PCI_VENDOR_BROADCOM, 516 PCI_PRODUCT_BROADCOM_BCM5761SE, 517 "Broadcom BCM5761SE Gigabit Ethernet", 518 }, 519 { PCI_VENDOR_BROADCOM, 520 PCI_PRODUCT_BROADCOM_BCM5764, 521 "Broadcom BCM5764 Gigabit Ethernet", 522 }, 523 { PCI_VENDOR_BROADCOM, 524 PCI_PRODUCT_BROADCOM_BCM5780, 525 "Broadcom BCM5780 Gigabit Ethernet", 526 }, 527 { PCI_VENDOR_BROADCOM, 528 PCI_PRODUCT_BROADCOM_BCM5780S, 529 "Broadcom BCM5780S Gigabit Ethernet", 530 }, 531 { PCI_VENDOR_BROADCOM, 532 PCI_PRODUCT_BROADCOM_BCM5781, 533 "Broadcom BCM5781 Gigabit Ethernet", 534 }, 535 { PCI_VENDOR_BROADCOM, 536 PCI_PRODUCT_BROADCOM_BCM5782, 537 "Broadcom BCM5782 Gigabit Ethernet", 538 }, 539 { PCI_VENDOR_BROADCOM, 540 PCI_PRODUCT_BROADCOM_BCM5784M, 541 "BCM5784M NetLink 1000baseT Ethernet", 542 }, 543 { PCI_VENDOR_BROADCOM, 544 PCI_PRODUCT_BROADCOM_BCM5785F, 545 "BCM5785F NetLink 10/100 Ethernet", 546 }, 547 { PCI_VENDOR_BROADCOM, 548 PCI_PRODUCT_BROADCOM_BCM5785G, 549 "BCM5785G NetLink 1000baseT Ethernet", 550 }, 551 { PCI_VENDOR_BROADCOM, 552 PCI_PRODUCT_BROADCOM_BCM5786, 553 "Broadcom BCM5786 Gigabit Ethernet", 554 }, 555 { PCI_VENDOR_BROADCOM, 556 PCI_PRODUCT_BROADCOM_BCM5787, 557 "Broadcom BCM5787 Gigabit Ethernet", 558 }, 559 { PCI_VENDOR_BROADCOM, 560 PCI_PRODUCT_BROADCOM_BCM5787F, 561 "Broadcom BCM5787F 10/100 Ethernet", 562 }, 563 { PCI_VENDOR_BROADCOM, 564 PCI_PRODUCT_BROADCOM_BCM5787M, 565 "Broadcom BCM5787M Gigabit Ethernet", 566 }, 567 { PCI_VENDOR_BROADCOM, 568 PCI_PRODUCT_BROADCOM_BCM5788, 569 "Broadcom BCM5788 Gigabit Ethernet", 570 }, 571 { PCI_VENDOR_BROADCOM, 572 PCI_PRODUCT_BROADCOM_BCM5789, 573 "Broadcom BCM5789 Gigabit Ethernet", 574 }, 575 { PCI_VENDOR_BROADCOM, 576 PCI_PRODUCT_BROADCOM_BCM5901, 577 "Broadcom BCM5901 Fast Ethernet", 578 }, 579 { PCI_VENDOR_BROADCOM, 580 PCI_PRODUCT_BROADCOM_BCM5901A2, 581 "Broadcom BCM5901A2 Fast Ethernet", 582 }, 583 { PCI_VENDOR_BROADCOM, 584 PCI_PRODUCT_BROADCOM_BCM5903M, 585 "Broadcom BCM5903M Fast Ethernet", 586 }, 587 { PCI_VENDOR_BROADCOM, 588 PCI_PRODUCT_BROADCOM_BCM5906, 589 "Broadcom BCM5906 Fast Ethernet", 590 }, 591 { PCI_VENDOR_BROADCOM, 592 PCI_PRODUCT_BROADCOM_BCM5906M, 593 "Broadcom BCM5906M Fast Ethernet", 594 }, 595 { PCI_VENDOR_BROADCOM, 596 PCI_PRODUCT_BROADCOM_BCM57760, 597 "Broadcom BCM57760 Fast Ethernet", 598 }, 599 { PCI_VENDOR_BROADCOM, 600 PCI_PRODUCT_BROADCOM_BCM57761, 601 "Broadcom BCM57761 Fast Ethernet", 602 }, 603 { PCI_VENDOR_BROADCOM, 604 PCI_PRODUCT_BROADCOM_BCM57762, 605 "Broadcom BCM57762 Gigabit Ethernet", 606 }, 607 { PCI_VENDOR_BROADCOM, 608 PCI_PRODUCT_BROADCOM_BCM57765, 609 "Broadcom BCM57765 Fast Ethernet", 610 }, 611 { PCI_VENDOR_BROADCOM, 612 PCI_PRODUCT_BROADCOM_BCM57766, 613 "Broadcom BCM57766 Fast Ethernet", 614 }, 615 { PCI_VENDOR_BROADCOM, 616 PCI_PRODUCT_BROADCOM_BCM57780, 617 "Broadcom BCM57780 Fast Ethernet", 618 }, 619 { PCI_VENDOR_BROADCOM, 620 PCI_PRODUCT_BROADCOM_BCM57781, 621 "Broadcom BCM57781 Fast Ethernet", 622 }, 623 { PCI_VENDOR_BROADCOM, 624 PCI_PRODUCT_BROADCOM_BCM57782, 625 "Broadcom BCM57782 Fast Ethernet", 626 }, 627 { PCI_VENDOR_BROADCOM, 628 PCI_PRODUCT_BROADCOM_BCM57785, 629 "Broadcom BCM57785 Fast Ethernet", 630 }, 631 { PCI_VENDOR_BROADCOM, 632 PCI_PRODUCT_BROADCOM_BCM57786, 633 "Broadcom BCM57786 Fast Ethernet", 634 }, 635 { PCI_VENDOR_BROADCOM, 636 PCI_PRODUCT_BROADCOM_BCM57788, 637 "Broadcom BCM57788 Fast Ethernet", 638 }, 639 { PCI_VENDOR_BROADCOM, 640 PCI_PRODUCT_BROADCOM_BCM57790, 641 "Broadcom BCM57790 Fast Ethernet", 642 }, 643 { PCI_VENDOR_BROADCOM, 644 PCI_PRODUCT_BROADCOM_BCM57791, 645 "Broadcom BCM57791 Fast Ethernet", 646 }, 647 { PCI_VENDOR_BROADCOM, 648 PCI_PRODUCT_BROADCOM_BCM57795, 649 "Broadcom BCM57795 Fast Ethernet", 650 }, 651 { PCI_VENDOR_SCHNEIDERKOCH, 652 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 653 "SysKonnect SK-9Dx1 Gigabit Ethernet", 654 }, 655 { PCI_VENDOR_3COM, 656 PCI_PRODUCT_3COM_3C996, 657 "3Com 3c996 Gigabit Ethernet", 658 }, 659 { PCI_VENDOR_FUJITSU4, 660 PCI_PRODUCT_FUJITSU4_PW008GE4, 661 "Fujitsu PW008GE4 Gigabit Ethernet", 662 }, 663 { PCI_VENDOR_FUJITSU4, 664 PCI_PRODUCT_FUJITSU4_PW008GE5, 665 "Fujitsu PW008GE5 Gigabit Ethernet", 666 }, 667 { PCI_VENDOR_FUJITSU4, 668 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 669 "Fujitsu Primepower 250/450 Gigabit Ethernet", 670 }, 671 { 0, 672 0, 673 NULL }, 674 }; 675 676 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 677 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 678 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 679 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 680 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 681 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 683 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 684 685 static const struct bge_revision { 686 uint32_t br_chipid; 687 const char *br_name; 688 } bge_revisions[] = { 689 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 690 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 691 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 692 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 693 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 694 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 695 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 696 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 697 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 698 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 699 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 700 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 701 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 702 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 703 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 704 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 705 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 706 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 707 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 708 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 709 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 710 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 711 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 712 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 713 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 714 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 715 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 716 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 717 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 718 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 719 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 720 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 721 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 722 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 723 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 724 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 725 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 726 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 727 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 728 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 729 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 730 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 731 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 732 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 733 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 734 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 735 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 736 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 737 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 738 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 739 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 740 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 741 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 742 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 743 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 744 /* 5754 and 5787 share the same ASIC ID */ 745 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 746 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 747 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 748 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 749 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 750 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 751 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 752 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 753 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 754 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 755 756 { 0, NULL } 757 }; 758 759 /* 760 * Some defaults for major revisions, so that newer steppings 761 * that we don't know about have a shot at working. 762 */ 763 static const struct bge_revision bge_majorrevs[] = { 764 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 765 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 766 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 767 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 768 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 769 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 770 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 772 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 773 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 774 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 775 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 776 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 777 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 778 /* 5754 and 5787 share the same ASIC ID */ 779 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 780 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 781 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 782 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 783 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 784 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 785 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 786 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 787 788 { 0, NULL } 789 }; 790 791 static int bge_allow_asf = 1; 792 793 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 794 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 795 796 static uint32_t 797 bge_readmem_ind(struct bge_softc *sc, int off) 798 { 799 pcireg_t val; 800 801 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 802 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 803 return 0; 804 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 806 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 807 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 808 return val; 809 } 810 811 static void 812 bge_writemem_ind(struct bge_softc *sc, int off, int val) 813 { 814 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 817 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 818 } 819 820 /* 821 * PCI Express only 822 */ 823 static void 824 bge_set_max_readrq(struct bge_softc *sc) 825 { 826 pcireg_t val; 827 828 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 829 + PCI_PCIE_DCSR); 830 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 831 switch (sc->bge_expmrq) { 832 case 2048: 833 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 834 break; 835 case 4096: 836 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 837 break; 838 default: 839 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 840 break; 841 } 842 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 843 + PCI_PCIE_DCSR, val); 844 } 845 846 #ifdef notdef 847 static uint32_t 848 bge_readreg_ind(struct bge_softc *sc, int off) 849 { 850 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 851 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 852 } 853 #endif 854 855 static void 856 bge_writereg_ind(struct bge_softc *sc, int off, int val) 857 { 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 859 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 860 } 861 862 static void 863 bge_writemem_direct(struct bge_softc *sc, int off, int val) 864 { 865 CSR_WRITE_4(sc, off, val); 866 } 867 868 static void 869 bge_writembx(struct bge_softc *sc, int off, int val) 870 { 871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 872 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 873 874 CSR_WRITE_4(sc, off, val); 875 } 876 877 static void 878 bge_writembx_flush(struct bge_softc *sc, int off, int val) 879 { 880 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 881 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 882 883 CSR_WRITE_4_FLUSH(sc, off, val); 884 } 885 886 /* 887 * Clear all stale locks and select the lock for this driver instance. 888 */ 889 void 890 bge_ape_lock_init(struct bge_softc *sc) 891 { 892 struct pci_attach_args *pa = &(sc->bge_pa); 893 uint32_t bit, regbase; 894 int i; 895 896 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 897 regbase = BGE_APE_LOCK_GRANT; 898 else 899 regbase = BGE_APE_PER_LOCK_GRANT; 900 901 /* Clear any stale locks. */ 902 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 903 switch (i) { 904 case BGE_APE_LOCK_PHY0: 905 case BGE_APE_LOCK_PHY1: 906 case BGE_APE_LOCK_PHY2: 907 case BGE_APE_LOCK_PHY3: 908 bit = BGE_APE_LOCK_GRANT_DRIVER0; 909 break; 910 default: 911 if (pa->pa_function != 0) 912 bit = BGE_APE_LOCK_GRANT_DRIVER0; 913 else 914 bit = (1 << pa->pa_function); 915 } 916 APE_WRITE_4(sc, regbase + 4 * i, bit); 917 } 918 919 /* Select the PHY lock based on the device's function number. */ 920 switch (pa->pa_function) { 921 case 0: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 923 break; 924 case 1: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 926 break; 927 case 2: 928 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 929 break; 930 case 3: 931 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 932 break; 933 default: 934 printf("%s: PHY lock not supported on function\n", 935 device_xname(sc->bge_dev)); 936 break; 937 } 938 } 939 940 /* 941 * Check for APE firmware, set flags, and print version info. 942 */ 943 void 944 bge_ape_read_fw_ver(struct bge_softc *sc) 945 { 946 const char *fwtype; 947 uint32_t apedata, features; 948 949 /* Check for a valid APE signature in shared memory. */ 950 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 951 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 952 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 953 return; 954 } 955 956 /* Check if APE firmware is running. */ 957 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 958 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 959 printf("%s: APE signature found but FW status not ready! " 960 "0x%08x\n", device_xname(sc->bge_dev), apedata); 961 return; 962 } 963 964 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 965 966 /* Fetch the APE firwmare type and version. */ 967 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 968 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 969 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 970 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 971 fwtype = "NCSI"; 972 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 973 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 974 fwtype = "DASH"; 975 } else 976 fwtype = "UNKN"; 977 978 /* Print the APE firmware version. */ 979 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 980 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 981 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 982 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 983 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 984 } 985 986 int 987 bge_ape_lock(struct bge_softc *sc, int locknum) 988 { 989 struct pci_attach_args *pa = &(sc->bge_pa); 990 uint32_t bit, gnt, req, status; 991 int i, off; 992 993 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 994 return (0); 995 996 /* Lock request/grant registers have different bases. */ 997 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 998 req = BGE_APE_LOCK_REQ; 999 gnt = BGE_APE_LOCK_GRANT; 1000 } else { 1001 req = BGE_APE_PER_LOCK_REQ; 1002 gnt = BGE_APE_PER_LOCK_GRANT; 1003 } 1004 1005 off = 4 * locknum; 1006 1007 switch (locknum) { 1008 case BGE_APE_LOCK_GPIO: 1009 /* Lock required when using GPIO. */ 1010 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1011 return (0); 1012 if (pa->pa_function == 0) 1013 bit = BGE_APE_LOCK_REQ_DRIVER0; 1014 else 1015 bit = (1 << pa->pa_function); 1016 break; 1017 case BGE_APE_LOCK_GRC: 1018 /* Lock required to reset the device. */ 1019 if (pa->pa_function == 0) 1020 bit = BGE_APE_LOCK_REQ_DRIVER0; 1021 else 1022 bit = (1 << pa->pa_function); 1023 break; 1024 case BGE_APE_LOCK_MEM: 1025 /* Lock required when accessing certain APE memory. */ 1026 if (pa->pa_function == 0) 1027 bit = BGE_APE_LOCK_REQ_DRIVER0; 1028 else 1029 bit = (1 << pa->pa_function); 1030 break; 1031 case BGE_APE_LOCK_PHY0: 1032 case BGE_APE_LOCK_PHY1: 1033 case BGE_APE_LOCK_PHY2: 1034 case BGE_APE_LOCK_PHY3: 1035 /* Lock required when accessing PHYs. */ 1036 bit = BGE_APE_LOCK_REQ_DRIVER0; 1037 break; 1038 default: 1039 return (EINVAL); 1040 } 1041 1042 /* Request a lock. */ 1043 APE_WRITE_4_FLUSH(sc, req + off, bit); 1044 1045 /* Wait up to 1 second to acquire lock. */ 1046 for (i = 0; i < 20000; i++) { 1047 status = APE_READ_4(sc, gnt + off); 1048 if (status == bit) 1049 break; 1050 DELAY(50); 1051 } 1052 1053 /* Handle any errors. */ 1054 if (status != bit) { 1055 printf("%s: APE lock %d request failed! " 1056 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1057 device_xname(sc->bge_dev), 1058 locknum, req + off, bit & 0xFFFF, gnt + off, 1059 status & 0xFFFF); 1060 /* Revoke the lock request. */ 1061 APE_WRITE_4(sc, gnt + off, bit); 1062 return (EBUSY); 1063 } 1064 1065 return (0); 1066 } 1067 1068 void 1069 bge_ape_unlock(struct bge_softc *sc, int locknum) 1070 { 1071 struct pci_attach_args *pa = &(sc->bge_pa); 1072 uint32_t bit, gnt; 1073 int off; 1074 1075 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1076 return; 1077 1078 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1079 gnt = BGE_APE_LOCK_GRANT; 1080 else 1081 gnt = BGE_APE_PER_LOCK_GRANT; 1082 1083 off = 4 * locknum; 1084 1085 switch (locknum) { 1086 case BGE_APE_LOCK_GPIO: 1087 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1088 return; 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_GRC: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_MEM: 1101 if (pa->pa_function == 0) 1102 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1103 else 1104 bit = (1 << pa->pa_function); 1105 break; 1106 case BGE_APE_LOCK_PHY0: 1107 case BGE_APE_LOCK_PHY1: 1108 case BGE_APE_LOCK_PHY2: 1109 case BGE_APE_LOCK_PHY3: 1110 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1111 break; 1112 default: 1113 return; 1114 } 1115 1116 /* Write and flush for consecutive bge_ape_lock() */ 1117 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1118 } 1119 1120 /* 1121 * Send an event to the APE firmware. 1122 */ 1123 void 1124 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1125 { 1126 uint32_t apedata; 1127 int i; 1128 1129 /* NCSI does not support APE events. */ 1130 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1131 return; 1132 1133 printf("%s: APE event 0x%08x send\n", device_xname(sc->bge_dev), event); 1134 1135 /* Wait up to 1ms for APE to service previous event. */ 1136 for (i = 10; i > 0; i--) { 1137 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1138 break; 1139 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1140 printf("%s: APE data 0x%08x -> 0x%08x\n", 1141 device_xname(sc->bge_dev), apedata, event); 1142 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1143 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1144 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1145 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1146 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1147 break; 1148 } 1149 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1150 DELAY(100); 1151 } 1152 if (i == 0) { 1153 printf("%s: APE event 0x%08x send timed out\n", 1154 device_xname(sc->bge_dev), event); 1155 } 1156 } 1157 1158 void 1159 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1160 { 1161 uint32_t apedata, event; 1162 1163 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1164 return; 1165 1166 switch (kind) { 1167 case BGE_RESET_START: 1168 /* If this is the first load, clear the load counter. */ 1169 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1170 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1171 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1172 else { 1173 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1174 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1175 } 1176 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1177 BGE_APE_HOST_SEG_SIG_MAGIC); 1178 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1179 BGE_APE_HOST_SEG_LEN_MAGIC); 1180 1181 /* Add some version info if bge(4) supports it. */ 1182 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1183 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1184 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1185 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1186 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1187 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1189 BGE_APE_HOST_DRVR_STATE_START); 1190 event = BGE_APE_EVENT_STATUS_STATE_START; 1191 break; 1192 case BGE_RESET_SHUTDOWN: 1193 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1194 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1195 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1196 break; 1197 case BGE_RESET_SUSPEND: 1198 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1199 break; 1200 default: 1201 return; 1202 } 1203 1204 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1205 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1206 } 1207 1208 static uint8_t 1209 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1210 { 1211 uint32_t access, byte = 0; 1212 int i; 1213 1214 /* Lock. */ 1215 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1216 for (i = 0; i < 8000; i++) { 1217 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1218 break; 1219 DELAY(20); 1220 } 1221 if (i == 8000) 1222 return 1; 1223 1224 /* Enable access. */ 1225 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1226 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1227 1228 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1229 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1230 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1231 DELAY(10); 1232 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1233 DELAY(10); 1234 break; 1235 } 1236 } 1237 1238 if (i == BGE_TIMEOUT * 10) { 1239 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1240 return 1; 1241 } 1242 1243 /* Get result. */ 1244 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1245 1246 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1247 1248 /* Disable access. */ 1249 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1250 1251 /* Unlock. */ 1252 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1253 1254 return 0; 1255 } 1256 1257 /* 1258 * Read a sequence of bytes from NVRAM. 1259 */ 1260 static int 1261 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1262 { 1263 int error = 0, i; 1264 uint8_t byte = 0; 1265 1266 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1267 return 1; 1268 1269 for (i = 0; i < cnt; i++) { 1270 error = bge_nvram_getbyte(sc, off + i, &byte); 1271 if (error) 1272 break; 1273 *(dest + i) = byte; 1274 } 1275 1276 return (error ? 1 : 0); 1277 } 1278 1279 /* 1280 * Read a byte of data stored in the EEPROM at address 'addr.' The 1281 * BCM570x supports both the traditional bitbang interface and an 1282 * auto access interface for reading the EEPROM. We use the auto 1283 * access method. 1284 */ 1285 static uint8_t 1286 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1287 { 1288 int i; 1289 uint32_t byte = 0; 1290 1291 /* 1292 * Enable use of auto EEPROM access so we can avoid 1293 * having to use the bitbang method. 1294 */ 1295 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1296 1297 /* Reset the EEPROM, load the clock period. */ 1298 CSR_WRITE_4(sc, BGE_EE_ADDR, 1299 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1300 DELAY(20); 1301 1302 /* Issue the read EEPROM command. */ 1303 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1304 1305 /* Wait for completion */ 1306 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1307 DELAY(10); 1308 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1309 break; 1310 } 1311 1312 if (i == BGE_TIMEOUT * 10) { 1313 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1314 return 1; 1315 } 1316 1317 /* Get result. */ 1318 byte = CSR_READ_4(sc, BGE_EE_DATA); 1319 1320 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1321 1322 return 0; 1323 } 1324 1325 /* 1326 * Read a sequence of bytes from the EEPROM. 1327 */ 1328 static int 1329 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1330 { 1331 int error = 0, i; 1332 uint8_t byte = 0; 1333 char *dest = destv; 1334 1335 for (i = 0; i < cnt; i++) { 1336 error = bge_eeprom_getbyte(sc, off + i, &byte); 1337 if (error) 1338 break; 1339 *(dest + i) = byte; 1340 } 1341 1342 return (error ? 1 : 0); 1343 } 1344 1345 static int 1346 bge_miibus_readreg(device_t dev, int phy, int reg) 1347 { 1348 struct bge_softc *sc = device_private(dev); 1349 uint32_t val; 1350 uint32_t autopoll; 1351 int i; 1352 1353 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1354 return 0; 1355 1356 /* Reading with autopolling on may trigger PCI errors */ 1357 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1358 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1359 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1360 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1361 DELAY(80); 1362 } 1363 1364 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1365 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1366 1367 for (i = 0; i < BGE_TIMEOUT; i++) { 1368 delay(10); 1369 val = CSR_READ_4(sc, BGE_MI_COMM); 1370 if (!(val & BGE_MICOMM_BUSY)) { 1371 DELAY(5); 1372 val = CSR_READ_4(sc, BGE_MI_COMM); 1373 break; 1374 } 1375 } 1376 1377 if (i == BGE_TIMEOUT) { 1378 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1379 val = 0; 1380 goto done; 1381 } 1382 1383 done: 1384 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1385 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1386 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1387 DELAY(80); 1388 } 1389 1390 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1391 1392 if (val & BGE_MICOMM_READFAIL) 1393 return 0; 1394 1395 return (val & 0xFFFF); 1396 } 1397 1398 static void 1399 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1400 { 1401 struct bge_softc *sc = device_private(dev); 1402 uint32_t autopoll; 1403 int i; 1404 1405 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1406 return; 1407 1408 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1409 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1410 return; 1411 1412 /* Reading with autopolling on may trigger PCI errors */ 1413 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1414 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1415 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1416 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1417 DELAY(80); 1418 } 1419 1420 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1421 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1422 1423 for (i = 0; i < BGE_TIMEOUT; i++) { 1424 delay(10); 1425 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1426 delay(5); 1427 CSR_READ_4(sc, BGE_MI_COMM); 1428 break; 1429 } 1430 } 1431 1432 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1433 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1434 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1435 delay(80); 1436 } 1437 1438 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1439 1440 if (i == BGE_TIMEOUT) 1441 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1442 } 1443 1444 static void 1445 bge_miibus_statchg(struct ifnet *ifp) 1446 { 1447 struct bge_softc *sc = ifp->if_softc; 1448 struct mii_data *mii = &sc->bge_mii; 1449 uint32_t mac_mode, rx_mode, tx_mode; 1450 1451 /* 1452 * Get flow control negotiation result. 1453 */ 1454 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1455 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1456 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1457 mii->mii_media_active &= ~IFM_ETH_FMASK; 1458 } 1459 1460 /* Set the port mode (MII/GMII) to match the link speed. */ 1461 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1462 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1463 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1464 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1465 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1466 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1467 mac_mode |= BGE_PORTMODE_GMII; 1468 else 1469 mac_mode |= BGE_PORTMODE_MII; 1470 1471 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1472 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1473 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1474 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1475 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1476 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1477 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1478 } else 1479 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1480 1481 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1482 DELAY(40); 1483 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1484 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1485 } 1486 1487 /* 1488 * Update rx threshold levels to values in a particular slot 1489 * of the interrupt-mitigation table bge_rx_threshes. 1490 */ 1491 static void 1492 bge_set_thresh(struct ifnet *ifp, int lvl) 1493 { 1494 struct bge_softc *sc = ifp->if_softc; 1495 int s; 1496 1497 /* For now, just save the new Rx-intr thresholds and record 1498 * that a threshold update is pending. Updating the hardware 1499 * registers here (even at splhigh()) is observed to 1500 * occasionaly cause glitches where Rx-interrupts are not 1501 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1502 */ 1503 s = splnet(); 1504 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1505 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1506 sc->bge_pending_rxintr_change = 1; 1507 splx(s); 1508 } 1509 1510 1511 /* 1512 * Update Rx thresholds of all bge devices 1513 */ 1514 static void 1515 bge_update_all_threshes(int lvl) 1516 { 1517 struct ifnet *ifp; 1518 const char * const namebuf = "bge"; 1519 int namelen; 1520 1521 if (lvl < 0) 1522 lvl = 0; 1523 else if (lvl >= NBGE_RX_THRESH) 1524 lvl = NBGE_RX_THRESH - 1; 1525 1526 namelen = strlen(namebuf); 1527 /* 1528 * Now search all the interfaces for this name/number 1529 */ 1530 IFNET_FOREACH(ifp) { 1531 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1532 continue; 1533 /* We got a match: update if doing auto-threshold-tuning */ 1534 if (bge_auto_thresh) 1535 bge_set_thresh(ifp, lvl); 1536 } 1537 } 1538 1539 /* 1540 * Handle events that have triggered interrupts. 1541 */ 1542 static void 1543 bge_handle_events(struct bge_softc *sc) 1544 { 1545 1546 return; 1547 } 1548 1549 /* 1550 * Memory management for jumbo frames. 1551 */ 1552 1553 static int 1554 bge_alloc_jumbo_mem(struct bge_softc *sc) 1555 { 1556 char *ptr, *kva; 1557 bus_dma_segment_t seg; 1558 int i, rseg, state, error; 1559 struct bge_jpool_entry *entry; 1560 1561 state = error = 0; 1562 1563 /* Grab a big chunk o' storage. */ 1564 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1565 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1566 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1567 return ENOBUFS; 1568 } 1569 1570 state = 1; 1571 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1572 BUS_DMA_NOWAIT)) { 1573 aprint_error_dev(sc->bge_dev, 1574 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1575 error = ENOBUFS; 1576 goto out; 1577 } 1578 1579 state = 2; 1580 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1581 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1582 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1583 error = ENOBUFS; 1584 goto out; 1585 } 1586 1587 state = 3; 1588 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1589 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1590 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1591 error = ENOBUFS; 1592 goto out; 1593 } 1594 1595 state = 4; 1596 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1597 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1598 1599 SLIST_INIT(&sc->bge_jfree_listhead); 1600 SLIST_INIT(&sc->bge_jinuse_listhead); 1601 1602 /* 1603 * Now divide it up into 9K pieces and save the addresses 1604 * in an array. 1605 */ 1606 ptr = sc->bge_cdata.bge_jumbo_buf; 1607 for (i = 0; i < BGE_JSLOTS; i++) { 1608 sc->bge_cdata.bge_jslots[i] = ptr; 1609 ptr += BGE_JLEN; 1610 entry = malloc(sizeof(struct bge_jpool_entry), 1611 M_DEVBUF, M_NOWAIT); 1612 if (entry == NULL) { 1613 aprint_error_dev(sc->bge_dev, 1614 "no memory for jumbo buffer queue!\n"); 1615 error = ENOBUFS; 1616 goto out; 1617 } 1618 entry->slot = i; 1619 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1620 entry, jpool_entries); 1621 } 1622 out: 1623 if (error != 0) { 1624 switch (state) { 1625 case 4: 1626 bus_dmamap_unload(sc->bge_dmatag, 1627 sc->bge_cdata.bge_rx_jumbo_map); 1628 case 3: 1629 bus_dmamap_destroy(sc->bge_dmatag, 1630 sc->bge_cdata.bge_rx_jumbo_map); 1631 case 2: 1632 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1633 case 1: 1634 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1635 break; 1636 default: 1637 break; 1638 } 1639 } 1640 1641 return error; 1642 } 1643 1644 /* 1645 * Allocate a jumbo buffer. 1646 */ 1647 static void * 1648 bge_jalloc(struct bge_softc *sc) 1649 { 1650 struct bge_jpool_entry *entry; 1651 1652 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1653 1654 if (entry == NULL) { 1655 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1656 return NULL; 1657 } 1658 1659 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1660 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1661 return (sc->bge_cdata.bge_jslots[entry->slot]); 1662 } 1663 1664 /* 1665 * Release a jumbo buffer. 1666 */ 1667 static void 1668 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1669 { 1670 struct bge_jpool_entry *entry; 1671 struct bge_softc *sc; 1672 int i, s; 1673 1674 /* Extract the softc struct pointer. */ 1675 sc = (struct bge_softc *)arg; 1676 1677 if (sc == NULL) 1678 panic("bge_jfree: can't find softc pointer!"); 1679 1680 /* calculate the slot this buffer belongs to */ 1681 1682 i = ((char *)buf 1683 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1684 1685 if ((i < 0) || (i >= BGE_JSLOTS)) 1686 panic("bge_jfree: asked to free buffer that we don't manage!"); 1687 1688 s = splvm(); 1689 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1690 if (entry == NULL) 1691 panic("bge_jfree: buffer not in use!"); 1692 entry->slot = i; 1693 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1694 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1695 1696 if (__predict_true(m != NULL)) 1697 pool_cache_put(mb_cache, m); 1698 splx(s); 1699 } 1700 1701 1702 /* 1703 * Initialize a standard receive ring descriptor. 1704 */ 1705 static int 1706 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1707 bus_dmamap_t dmamap) 1708 { 1709 struct mbuf *m_new = NULL; 1710 struct bge_rx_bd *r; 1711 int error; 1712 1713 if (dmamap == NULL) { 1714 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1715 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1716 if (error != 0) 1717 return error; 1718 } 1719 1720 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1721 1722 if (m == NULL) { 1723 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1724 if (m_new == NULL) 1725 return ENOBUFS; 1726 1727 MCLGET(m_new, M_DONTWAIT); 1728 if (!(m_new->m_flags & M_EXT)) { 1729 m_freem(m_new); 1730 return ENOBUFS; 1731 } 1732 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1733 1734 } else { 1735 m_new = m; 1736 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1737 m_new->m_data = m_new->m_ext.ext_buf; 1738 } 1739 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1740 m_adj(m_new, ETHER_ALIGN); 1741 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1742 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1743 return ENOBUFS; 1744 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1745 BUS_DMASYNC_PREREAD); 1746 1747 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1748 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1749 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1750 r->bge_flags = BGE_RXBDFLAG_END; 1751 r->bge_len = m_new->m_len; 1752 r->bge_idx = i; 1753 1754 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1755 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1756 i * sizeof (struct bge_rx_bd), 1757 sizeof (struct bge_rx_bd), 1758 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1759 1760 return 0; 1761 } 1762 1763 /* 1764 * Initialize a jumbo receive ring descriptor. This allocates 1765 * a jumbo buffer from the pool managed internally by the driver. 1766 */ 1767 static int 1768 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1769 { 1770 struct mbuf *m_new = NULL; 1771 struct bge_rx_bd *r; 1772 void *buf = NULL; 1773 1774 if (m == NULL) { 1775 1776 /* Allocate the mbuf. */ 1777 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1778 if (m_new == NULL) 1779 return ENOBUFS; 1780 1781 /* Allocate the jumbo buffer */ 1782 buf = bge_jalloc(sc); 1783 if (buf == NULL) { 1784 m_freem(m_new); 1785 aprint_error_dev(sc->bge_dev, 1786 "jumbo allocation failed -- packet dropped!\n"); 1787 return ENOBUFS; 1788 } 1789 1790 /* Attach the buffer to the mbuf. */ 1791 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1792 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1793 bge_jfree, sc); 1794 m_new->m_flags |= M_EXT_RW; 1795 } else { 1796 m_new = m; 1797 buf = m_new->m_data = m_new->m_ext.ext_buf; 1798 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1799 } 1800 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1801 m_adj(m_new, ETHER_ALIGN); 1802 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1803 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1804 BUS_DMASYNC_PREREAD); 1805 /* Set up the descriptor. */ 1806 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1807 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1808 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1809 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1810 r->bge_len = m_new->m_len; 1811 r->bge_idx = i; 1812 1813 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1814 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1815 i * sizeof (struct bge_rx_bd), 1816 sizeof (struct bge_rx_bd), 1817 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1818 1819 return 0; 1820 } 1821 1822 /* 1823 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1824 * that's 1MB or memory, which is a lot. For now, we fill only the first 1825 * 256 ring entries and hope that our CPU is fast enough to keep up with 1826 * the NIC. 1827 */ 1828 static int 1829 bge_init_rx_ring_std(struct bge_softc *sc) 1830 { 1831 int i; 1832 1833 if (sc->bge_flags & BGE_RXRING_VALID) 1834 return 0; 1835 1836 for (i = 0; i < BGE_SSLOTS; i++) { 1837 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1838 return ENOBUFS; 1839 } 1840 1841 sc->bge_std = i - 1; 1842 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1843 1844 sc->bge_flags |= BGE_RXRING_VALID; 1845 1846 return 0; 1847 } 1848 1849 static void 1850 bge_free_rx_ring_std(struct bge_softc *sc) 1851 { 1852 int i; 1853 1854 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1855 return; 1856 1857 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1858 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1859 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1860 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1861 bus_dmamap_destroy(sc->bge_dmatag, 1862 sc->bge_cdata.bge_rx_std_map[i]); 1863 } 1864 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1865 sizeof(struct bge_rx_bd)); 1866 } 1867 1868 sc->bge_flags &= ~BGE_RXRING_VALID; 1869 } 1870 1871 static int 1872 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1873 { 1874 int i; 1875 volatile struct bge_rcb *rcb; 1876 1877 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1878 return 0; 1879 1880 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1881 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1882 return ENOBUFS; 1883 } 1884 1885 sc->bge_jumbo = i - 1; 1886 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1887 1888 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1889 rcb->bge_maxlen_flags = 0; 1890 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1891 1892 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1893 1894 return 0; 1895 } 1896 1897 static void 1898 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1899 { 1900 int i; 1901 1902 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1903 return; 1904 1905 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1906 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1907 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1908 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1909 } 1910 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1911 sizeof(struct bge_rx_bd)); 1912 } 1913 1914 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1915 } 1916 1917 static void 1918 bge_free_tx_ring(struct bge_softc *sc) 1919 { 1920 int i; 1921 struct txdmamap_pool_entry *dma; 1922 1923 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1924 return; 1925 1926 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1927 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1928 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1929 sc->bge_cdata.bge_tx_chain[i] = NULL; 1930 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1931 link); 1932 sc->txdma[i] = 0; 1933 } 1934 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1935 sizeof(struct bge_tx_bd)); 1936 } 1937 1938 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1939 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1940 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1941 free(dma, M_DEVBUF); 1942 } 1943 1944 sc->bge_flags &= ~BGE_TXRING_VALID; 1945 } 1946 1947 static int 1948 bge_init_tx_ring(struct bge_softc *sc) 1949 { 1950 int i; 1951 bus_dmamap_t dmamap; 1952 struct txdmamap_pool_entry *dma; 1953 1954 if (sc->bge_flags & BGE_TXRING_VALID) 1955 return 0; 1956 1957 sc->bge_txcnt = 0; 1958 sc->bge_tx_saved_considx = 0; 1959 1960 /* Initialize transmit producer index for host-memory send ring. */ 1961 sc->bge_tx_prodidx = 0; 1962 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1963 /* 5700 b2 errata */ 1964 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1965 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1966 1967 /* NIC-memory send ring not used; initialize to zero. */ 1968 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1969 /* 5700 b2 errata */ 1970 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1971 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1972 1973 SLIST_INIT(&sc->txdma_list); 1974 for (i = 0; i < BGE_RSLOTS; i++) { 1975 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1976 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1977 &dmamap)) 1978 return ENOBUFS; 1979 if (dmamap == NULL) 1980 panic("dmamap NULL in bge_init_tx_ring"); 1981 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1982 if (dma == NULL) { 1983 aprint_error_dev(sc->bge_dev, 1984 "can't alloc txdmamap_pool_entry\n"); 1985 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1986 return ENOMEM; 1987 } 1988 dma->dmamap = dmamap; 1989 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1990 } 1991 1992 sc->bge_flags |= BGE_TXRING_VALID; 1993 1994 return 0; 1995 } 1996 1997 static void 1998 bge_setmulti(struct bge_softc *sc) 1999 { 2000 struct ethercom *ac = &sc->ethercom; 2001 struct ifnet *ifp = &ac->ec_if; 2002 struct ether_multi *enm; 2003 struct ether_multistep step; 2004 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2005 uint32_t h; 2006 int i; 2007 2008 if (ifp->if_flags & IFF_PROMISC) 2009 goto allmulti; 2010 2011 /* Now program new ones. */ 2012 ETHER_FIRST_MULTI(step, ac, enm); 2013 while (enm != NULL) { 2014 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2015 /* 2016 * We must listen to a range of multicast addresses. 2017 * For now, just accept all multicasts, rather than 2018 * trying to set only those filter bits needed to match 2019 * the range. (At this time, the only use of address 2020 * ranges is for IP multicast routing, for which the 2021 * range is big enough to require all bits set.) 2022 */ 2023 goto allmulti; 2024 } 2025 2026 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2027 2028 /* Just want the 7 least-significant bits. */ 2029 h &= 0x7f; 2030 2031 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2032 ETHER_NEXT_MULTI(step, enm); 2033 } 2034 2035 ifp->if_flags &= ~IFF_ALLMULTI; 2036 goto setit; 2037 2038 allmulti: 2039 ifp->if_flags |= IFF_ALLMULTI; 2040 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2041 2042 setit: 2043 for (i = 0; i < 4; i++) 2044 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2045 } 2046 2047 static void 2048 bge_sig_pre_reset(struct bge_softc *sc, int type) 2049 { 2050 2051 /* 2052 * Some chips don't like this so only do this if ASF is enabled 2053 */ 2054 if (sc->bge_asf_mode) 2055 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2056 2057 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2058 switch (type) { 2059 case BGE_RESET_START: 2060 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2061 BGE_FW_DRV_STATE_START); 2062 break; 2063 case BGE_RESET_SHUTDOWN: 2064 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2065 BGE_FW_DRV_STATE_UNLOAD); 2066 break; 2067 case BGE_RESET_SUSPEND: 2068 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2069 BGE_FW_DRV_STATE_SUSPEND); 2070 break; 2071 } 2072 } 2073 2074 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2075 bge_ape_driver_state_change(sc, type); 2076 } 2077 2078 static void 2079 bge_sig_post_reset(struct bge_softc *sc, int type) 2080 { 2081 2082 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2083 switch (type) { 2084 case BGE_RESET_START: 2085 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2086 BGE_FW_DRV_STATE_START_DONE); 2087 /* START DONE */ 2088 break; 2089 case BGE_RESET_SHUTDOWN: 2090 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2091 BGE_FW_DRV_STATE_UNLOAD_DONE); 2092 break; 2093 } 2094 } 2095 2096 if (type == BGE_RESET_SHUTDOWN) 2097 bge_ape_driver_state_change(sc, type); 2098 } 2099 2100 static void 2101 bge_sig_legacy(struct bge_softc *sc, int type) 2102 { 2103 2104 if (sc->bge_asf_mode) { 2105 switch (type) { 2106 case BGE_RESET_START: 2107 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2108 BGE_FW_DRV_STATE_START); 2109 break; 2110 case BGE_RESET_SHUTDOWN: 2111 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2112 BGE_FW_DRV_STATE_UNLOAD); 2113 break; 2114 } 2115 } 2116 } 2117 2118 static void 2119 bge_wait_for_event_ack(struct bge_softc *sc) 2120 { 2121 int i; 2122 2123 /* wait up to 2500usec */ 2124 for (i = 0; i < 250; i++) { 2125 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2126 BGE_RX_CPU_DRV_EVENT)) 2127 break; 2128 DELAY(10); 2129 } 2130 } 2131 2132 static void 2133 bge_stop_fw(struct bge_softc *sc) 2134 { 2135 2136 if (sc->bge_asf_mode) { 2137 bge_wait_for_event_ack(sc); 2138 2139 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2140 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2141 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2142 2143 bge_wait_for_event_ack(sc); 2144 } 2145 } 2146 2147 static int 2148 bge_poll_fw(struct bge_softc *sc) 2149 { 2150 uint32_t val; 2151 int i; 2152 2153 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2154 for (i = 0; i < BGE_TIMEOUT; i++) { 2155 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2156 if (val & BGE_VCPU_STATUS_INIT_DONE) 2157 break; 2158 DELAY(100); 2159 } 2160 if (i >= BGE_TIMEOUT) { 2161 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2162 return -1; 2163 } 2164 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2165 /* 2166 * Poll the value location we just wrote until 2167 * we see the 1's complement of the magic number. 2168 * This indicates that the firmware initialization 2169 * is complete. 2170 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2171 */ 2172 for (i = 0; i < BGE_TIMEOUT; i++) { 2173 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2174 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2175 break; 2176 DELAY(10); 2177 } 2178 2179 if (i >= BGE_TIMEOUT) { 2180 aprint_error_dev(sc->bge_dev, 2181 "firmware handshake timed out, val = %x\n", val); 2182 return -1; 2183 } 2184 } 2185 2186 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2187 /* tg3 says we have to wait extra time */ 2188 delay(10 * 1000); 2189 } 2190 2191 return 0; 2192 } 2193 2194 int 2195 bge_phy_addr(struct bge_softc *sc) 2196 { 2197 struct pci_attach_args *pa = &(sc->bge_pa); 2198 int phy_addr = 1; 2199 2200 /* 2201 * PHY address mapping for various devices. 2202 * 2203 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2204 * ---------+-------+-------+-------+-------+ 2205 * BCM57XX | 1 | X | X | X | 2206 * BCM5704 | 1 | X | 1 | X | 2207 * BCM5717 | 1 | 8 | 2 | 9 | 2208 * BCM5719 | 1 | 8 | 2 | 9 | 2209 * BCM5720 | 1 | 8 | 2 | 9 | 2210 * 2211 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2212 * ---------+-------+-------+-------+-------+ 2213 * BCM57XX | X | X | X | X | 2214 * BCM5704 | X | X | X | X | 2215 * BCM5717 | X | X | X | X | 2216 * BCM5719 | 3 | 10 | 4 | 11 | 2217 * BCM5720 | X | X | X | X | 2218 * 2219 * Other addresses may respond but they are not 2220 * IEEE compliant PHYs and should be ignored. 2221 */ 2222 switch (BGE_ASICREV(sc->bge_chipid)) { 2223 case BGE_ASICREV_BCM5717: 2224 case BGE_ASICREV_BCM5719: 2225 case BGE_ASICREV_BCM5720: 2226 phy_addr = pa->pa_function; 2227 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2228 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2229 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2230 } else { 2231 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2232 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2233 } 2234 } 2235 2236 return phy_addr; 2237 } 2238 2239 /* 2240 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2241 * self-test results. 2242 */ 2243 static int 2244 bge_chipinit(struct bge_softc *sc) 2245 { 2246 uint32_t dma_rw_ctl, mode_ctl, reg; 2247 int i; 2248 2249 /* Set endianness before we access any non-PCI registers. */ 2250 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2251 BGE_INIT); 2252 2253 /* 2254 * Clear the MAC statistics block in the NIC's 2255 * internal memory. 2256 */ 2257 for (i = BGE_STATS_BLOCK; 2258 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2259 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2260 2261 for (i = BGE_STATUS_BLOCK; 2262 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2263 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2264 2265 /* 5717 workaround from tg3 */ 2266 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2267 /* Save */ 2268 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2269 2270 /* Temporary modify MODE_CTL to control TLP */ 2271 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2272 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2273 2274 /* Control TLP */ 2275 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2276 BGE_TLP_PHYCTL1); 2277 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2278 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2279 2280 /* Restore */ 2281 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2282 } 2283 2284 /* XXX Should we use 57765_FAMILY? */ 2285 if (BGE_IS_57765_PLUS(sc)) { 2286 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2287 /* Save */ 2288 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2289 2290 /* Temporary modify MODE_CTL to control TLP */ 2291 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2292 CSR_WRITE_4(sc, BGE_MODE_CTL, 2293 reg | BGE_MODECTL_PCIE_TLPADDR1); 2294 2295 /* Control TLP */ 2296 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2297 BGE_TLP_PHYCTL5); 2298 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2299 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2300 2301 /* Restore */ 2302 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2303 } 2304 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2305 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2306 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2307 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2308 2309 /* Save */ 2310 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2311 2312 /* Temporary modify MODE_CTL to control TLP */ 2313 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2314 CSR_WRITE_4(sc, BGE_MODE_CTL, 2315 reg | BGE_MODECTL_PCIE_TLPADDR0); 2316 2317 /* Control TLP */ 2318 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2319 BGE_TLP_FTSMAX); 2320 reg &= ~BGE_TLP_FTSMAX_MSK; 2321 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2322 reg | BGE_TLP_FTSMAX_VAL); 2323 2324 /* Restore */ 2325 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2326 } 2327 2328 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2329 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2330 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2331 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2332 } 2333 2334 /* Set up the PCI DMA control register. */ 2335 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2336 if (sc->bge_flags & BGE_PCIE) { 2337 /* Read watermark not used, 128 bytes for write. */ 2338 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2339 device_xname(sc->bge_dev))); 2340 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2341 } else if (sc->bge_flags & BGE_PCIX) { 2342 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2343 device_xname(sc->bge_dev))); 2344 /* PCI-X bus */ 2345 if (BGE_IS_5714_FAMILY(sc)) { 2346 /* 256 bytes for read and write. */ 2347 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2348 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2349 2350 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2351 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2352 else 2353 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2354 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2355 /* 1536 bytes for read, 384 bytes for write. */ 2356 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2357 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2358 } else { 2359 /* 384 bytes for read and write. */ 2360 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2361 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2362 (0x0F); 2363 } 2364 2365 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2366 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2367 uint32_t tmp; 2368 2369 /* Set ONEDMA_ATONCE for hardware workaround. */ 2370 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2371 if (tmp == 6 || tmp == 7) 2372 dma_rw_ctl |= 2373 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2374 2375 /* Set PCI-X DMA write workaround. */ 2376 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2377 } 2378 } else { 2379 /* Conventional PCI bus: 256 bytes for read and write. */ 2380 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2381 device_xname(sc->bge_dev))); 2382 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2383 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2384 2385 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2386 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2387 dma_rw_ctl |= 0x0F; 2388 } 2389 2390 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2391 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2392 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2393 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2394 2395 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2396 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2397 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2398 2399 if (BGE_IS_5717_PLUS(sc)) { 2400 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2401 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2402 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2403 2404 /* 2405 * Enable HW workaround for controllers that misinterpret 2406 * a status tag update and leave interrupts permanently 2407 * disabled. 2408 */ 2409 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2410 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2411 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2412 } 2413 2414 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2415 dma_rw_ctl); 2416 2417 /* 2418 * Set up general mode register. 2419 */ 2420 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2421 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2422 /* Retain Host-2-BMC settings written by APE firmware. */ 2423 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2424 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2425 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2426 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2427 } 2428 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2429 BGE_MODECTL_TX_NO_PHDR_CSUM; 2430 2431 /* 2432 * BCM5701 B5 have a bug causing data corruption when using 2433 * 64-bit DMA reads, which can be terminated early and then 2434 * completed later as 32-bit accesses, in combination with 2435 * certain bridges. 2436 */ 2437 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2438 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2439 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2440 2441 /* 2442 * Tell the firmware the driver is running 2443 */ 2444 if (sc->bge_asf_mode & ASF_STACKUP) 2445 mode_ctl |= BGE_MODECTL_STACKUP; 2446 2447 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2448 2449 /* 2450 * Disable memory write invalidate. Apparently it is not supported 2451 * properly by these devices. 2452 */ 2453 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2454 PCI_COMMAND_INVALIDATE_ENABLE); 2455 2456 #ifdef __brokenalpha__ 2457 /* 2458 * Must insure that we do not cross an 8K (bytes) boundary 2459 * for DMA reads. Our highest limit is 1K bytes. This is a 2460 * restriction on some ALPHA platforms with early revision 2461 * 21174 PCI chipsets, such as the AlphaPC 164lx 2462 */ 2463 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2464 #endif 2465 2466 /* Set the timer prescaler (always 66MHz) */ 2467 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2468 2469 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2470 DELAY(40); /* XXX */ 2471 2472 /* Put PHY into ready state */ 2473 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2474 DELAY(40); 2475 } 2476 2477 return 0; 2478 } 2479 2480 static int 2481 bge_blockinit(struct bge_softc *sc) 2482 { 2483 volatile struct bge_rcb *rcb; 2484 bus_size_t rcb_addr; 2485 struct ifnet *ifp = &sc->ethercom.ec_if; 2486 bge_hostaddr taddr; 2487 uint32_t dmactl, val; 2488 int i, limit; 2489 2490 /* 2491 * Initialize the memory window pointer register so that 2492 * we can access the first 32K of internal NIC RAM. This will 2493 * allow us to set up the TX send ring RCBs and the RX return 2494 * ring RCBs, plus other things which live in NIC memory. 2495 */ 2496 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2497 2498 /* Step 33: Configure mbuf memory pool */ 2499 if (!BGE_IS_5705_PLUS(sc)) { 2500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2501 BGE_BUFFPOOL_1); 2502 2503 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2505 else 2506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2507 2508 /* Configure DMA resource pool */ 2509 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2510 BGE_DMA_DESCRIPTORS); 2511 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2512 } 2513 2514 /* Step 35: Configure mbuf pool watermarks */ 2515 /* new broadcom docs strongly recommend these: */ 2516 if (BGE_IS_5717_PLUS(sc)) { 2517 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2518 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2520 } else if (BGE_IS_5705_PLUS(sc)) { 2521 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2522 2523 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2524 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2525 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2526 } else { 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2529 } 2530 } else { 2531 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2532 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2534 } 2535 2536 /* Step 36: Configure DMA resource watermarks */ 2537 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2538 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2539 2540 /* Step 38: Enable buffer manager */ 2541 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2542 /* 2543 * Change the arbitration algorithm of TXMBUF read request to 2544 * round-robin instead of priority based for BCM5719. When 2545 * TXFIFO is almost empty, RDMA will hold its request until 2546 * TXFIFO is not almost empty. 2547 */ 2548 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2549 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2550 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2551 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2552 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2553 val |= BGE_BMANMODE_LOMBUF_ATTN; 2554 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2555 2556 /* Step 39: Poll for buffer manager start indication */ 2557 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2558 DELAY(10); 2559 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2560 break; 2561 } 2562 2563 if (i == BGE_TIMEOUT * 2) { 2564 aprint_error_dev(sc->bge_dev, 2565 "buffer manager failed to start\n"); 2566 return ENXIO; 2567 } 2568 2569 /* Step 40: Enable flow-through queues */ 2570 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2571 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2572 2573 /* Wait until queue initialization is complete */ 2574 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2575 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2576 break; 2577 DELAY(10); 2578 } 2579 2580 if (i == BGE_TIMEOUT * 2) { 2581 aprint_error_dev(sc->bge_dev, 2582 "flow-through queue init failed\n"); 2583 return ENXIO; 2584 } 2585 2586 /* 2587 * Summary of rings supported by the controller: 2588 * 2589 * Standard Receive Producer Ring 2590 * - This ring is used to feed receive buffers for "standard" 2591 * sized frames (typically 1536 bytes) to the controller. 2592 * 2593 * Jumbo Receive Producer Ring 2594 * - This ring is used to feed receive buffers for jumbo sized 2595 * frames (i.e. anything bigger than the "standard" frames) 2596 * to the controller. 2597 * 2598 * Mini Receive Producer Ring 2599 * - This ring is used to feed receive buffers for "mini" 2600 * sized frames to the controller. 2601 * - This feature required external memory for the controller 2602 * but was never used in a production system. Should always 2603 * be disabled. 2604 * 2605 * Receive Return Ring 2606 * - After the controller has placed an incoming frame into a 2607 * receive buffer that buffer is moved into a receive return 2608 * ring. The driver is then responsible to passing the 2609 * buffer up to the stack. Many versions of the controller 2610 * support multiple RR rings. 2611 * 2612 * Send Ring 2613 * - This ring is used for outgoing frames. Many versions of 2614 * the controller support multiple send rings. 2615 */ 2616 2617 /* Step 41: Initialize the standard RX ring control block */ 2618 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2619 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2620 if (BGE_IS_5717_PLUS(sc)) { 2621 /* 2622 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2623 * Bits 15-2 : Maximum RX frame size 2624 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2625 * Bit 0 : Reserved 2626 */ 2627 rcb->bge_maxlen_flags = 2628 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2629 } else if (BGE_IS_5705_PLUS(sc)) { 2630 /* 2631 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2632 * Bits 15-2 : Reserved (should be 0) 2633 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2634 * Bit 0 : Reserved 2635 */ 2636 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2637 } else { 2638 /* 2639 * Ring size is always XXX entries 2640 * Bits 31-16: Maximum RX frame size 2641 * Bits 15-2 : Reserved (should be 0) 2642 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2643 * Bit 0 : Reserved 2644 */ 2645 rcb->bge_maxlen_flags = 2646 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2647 } 2648 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2649 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2650 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2651 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2652 else 2653 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2654 /* Write the standard receive producer ring control block. */ 2655 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2656 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2657 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2658 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2659 2660 /* Reset the standard receive producer ring producer index. */ 2661 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2662 2663 /* 2664 * Step 42: Initialize the jumbo RX ring control block 2665 * We set the 'ring disabled' bit in the flags 2666 * field until we're actually ready to start 2667 * using this ring (i.e. once we set the MTU 2668 * high enough to require it). 2669 */ 2670 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2671 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2672 BGE_HOSTADDR(rcb->bge_hostaddr, 2673 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2674 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2675 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2676 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2677 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2678 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2679 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2680 else 2681 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2682 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2683 rcb->bge_hostaddr.bge_addr_hi); 2684 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2685 rcb->bge_hostaddr.bge_addr_lo); 2686 /* Program the jumbo receive producer ring RCB parameters. */ 2687 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2688 rcb->bge_maxlen_flags); 2689 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2690 /* Reset the jumbo receive producer ring producer index. */ 2691 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2692 } 2693 2694 /* Disable the mini receive producer ring RCB. */ 2695 if (BGE_IS_5700_FAMILY(sc)) { 2696 /* Set up dummy disabled mini ring RCB */ 2697 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2698 rcb->bge_maxlen_flags = 2699 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2700 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2701 rcb->bge_maxlen_flags); 2702 /* Reset the mini receive producer ring producer index. */ 2703 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2704 2705 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2706 offsetof(struct bge_ring_data, bge_info), 2707 sizeof (struct bge_gib), 2708 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2709 } 2710 2711 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2712 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2713 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2714 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2715 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2716 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2717 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2718 } 2719 /* 2720 * The BD ring replenish thresholds control how often the 2721 * hardware fetches new BD's from the producer rings in host 2722 * memory. Setting the value too low on a busy system can 2723 * starve the hardware and recue the throughpout. 2724 * 2725 * Set the BD ring replenish thresholds. The recommended 2726 * values are 1/8th the number of descriptors allocated to 2727 * each ring, but since we try to avoid filling the entire 2728 * ring we set these to the minimal value of 8. This needs to 2729 * be done on several of the supported chip revisions anyway, 2730 * to work around HW bugs. 2731 */ 2732 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2733 if (BGE_IS_JUMBO_CAPABLE(sc)) 2734 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2735 2736 if (BGE_IS_5717_PLUS(sc)) { 2737 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2738 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2739 } 2740 2741 /* 2742 * Disable all send rings by setting the 'ring disabled' bit 2743 * in the flags field of all the TX send ring control blocks, 2744 * located in NIC memory. 2745 */ 2746 if (BGE_IS_5700_FAMILY(sc)) { 2747 /* 5700 to 5704 had 16 send rings. */ 2748 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2749 } else 2750 limit = 1; 2751 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2752 for (i = 0; i < limit; i++) { 2753 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2754 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2755 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2756 rcb_addr += sizeof(struct bge_rcb); 2757 } 2758 2759 /* Configure send ring RCB 0 (we use only the first ring) */ 2760 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2761 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2762 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2763 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2764 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2765 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2766 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2767 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2768 else 2769 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2770 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2771 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2772 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2773 2774 /* 2775 * Disable all receive return rings by setting the 2776 * 'ring diabled' bit in the flags field of all the receive 2777 * return ring control blocks, located in NIC memory. 2778 */ 2779 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2780 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2781 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2782 /* Should be 17, use 16 until we get an SRAM map. */ 2783 limit = 16; 2784 } else if (BGE_IS_5700_FAMILY(sc)) 2785 limit = BGE_RX_RINGS_MAX; 2786 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2787 BGE_IS_57765_PLUS(sc)) 2788 limit = 4; 2789 else 2790 limit = 1; 2791 /* Disable all receive return rings */ 2792 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2793 for (i = 0; i < limit; i++) { 2794 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2795 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2796 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2797 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2798 BGE_RCB_FLAG_RING_DISABLED)); 2799 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2800 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2801 (i * (sizeof(uint64_t))), 0); 2802 rcb_addr += sizeof(struct bge_rcb); 2803 } 2804 2805 /* 2806 * Set up receive return ring 0. Note that the NIC address 2807 * for RX return rings is 0x0. The return rings live entirely 2808 * within the host, so the nicaddr field in the RCB isn't used. 2809 */ 2810 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2811 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2812 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2813 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2814 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2815 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2816 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2817 2818 /* Set random backoff seed for TX */ 2819 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2820 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2821 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2822 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2823 BGE_TX_BACKOFF_SEED_MASK); 2824 2825 /* Set inter-packet gap */ 2826 val = 0x2620; 2827 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2828 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2829 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2830 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2831 2832 /* 2833 * Specify which ring to use for packets that don't match 2834 * any RX rules. 2835 */ 2836 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2837 2838 /* 2839 * Configure number of RX lists. One interrupt distribution 2840 * list, sixteen active lists, one bad frames class. 2841 */ 2842 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2843 2844 /* Inialize RX list placement stats mask. */ 2845 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2846 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2847 2848 /* Disable host coalescing until we get it set up */ 2849 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2850 2851 /* Poll to make sure it's shut down. */ 2852 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2853 DELAY(10); 2854 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2855 break; 2856 } 2857 2858 if (i == BGE_TIMEOUT * 2) { 2859 aprint_error_dev(sc->bge_dev, 2860 "host coalescing engine failed to idle\n"); 2861 return ENXIO; 2862 } 2863 2864 /* Set up host coalescing defaults */ 2865 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2866 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2867 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2868 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2869 if (!(BGE_IS_5705_PLUS(sc))) { 2870 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2871 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2872 } 2873 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2874 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2875 2876 /* Set up address of statistics block */ 2877 if (BGE_IS_5700_FAMILY(sc)) { 2878 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2879 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2880 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2881 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2882 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2883 } 2884 2885 /* Set up address of status block */ 2886 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2887 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2888 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2889 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2890 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2891 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2892 2893 /* Set up status block size. */ 2894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2895 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2896 val = BGE_STATBLKSZ_FULL; 2897 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2898 } else { 2899 val = BGE_STATBLKSZ_32BYTE; 2900 bzero(&sc->bge_rdata->bge_status_block, 32); 2901 } 2902 2903 /* Turn on host coalescing state machine */ 2904 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2905 2906 /* Turn on RX BD completion state machine and enable attentions */ 2907 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2908 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2909 2910 /* Turn on RX list placement state machine */ 2911 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2912 2913 /* Turn on RX list selector state machine. */ 2914 if (!(BGE_IS_5705_PLUS(sc))) 2915 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2916 2917 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2918 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2919 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2920 BGE_MACMODE_FRMHDR_DMA_ENB; 2921 2922 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2923 val |= BGE_PORTMODE_TBI; 2924 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2925 val |= BGE_PORTMODE_GMII; 2926 else 2927 val |= BGE_PORTMODE_MII; 2928 2929 /* Allow APE to send/receive frames. */ 2930 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2931 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2932 2933 /* Turn on DMA, clear stats */ 2934 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2935 DELAY(40); 2936 2937 /* Set misc. local control, enable interrupts on attentions */ 2938 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2939 if (BGE_IS_5717_PLUS(sc)) { 2940 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2941 DELAY(100); 2942 } 2943 2944 /* Turn on DMA completion state machine */ 2945 if (!(BGE_IS_5705_PLUS(sc))) 2946 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2947 2948 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2949 2950 /* Enable host coalescing bug fix. */ 2951 if (BGE_IS_5755_PLUS(sc)) 2952 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2953 2954 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2955 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2956 2957 /* Turn on write DMA state machine */ 2958 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2959 DELAY(40); 2960 2961 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2962 2963 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2964 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2965 2966 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2967 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2968 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2969 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2970 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2971 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2972 2973 if (sc->bge_flags & BGE_PCIE) 2974 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2975 if (sc->bge_flags & BGE_TSO) 2976 val |= BGE_RDMAMODE_TSO4_ENABLE; 2977 2978 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2979 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2980 BGE_RDMAMODE_H2BNC_VLAN_DET; 2981 /* 2982 * Allow multiple outstanding read requests from 2983 * non-LSO read DMA engine. 2984 */ 2985 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2986 } 2987 2988 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2989 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2990 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2991 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2992 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2993 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2994 /* 2995 * Adjust tx margin to prevent TX data corruption and 2996 * fix internal FIFO overflow. 2997 */ 2998 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2999 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3000 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3001 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3002 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3003 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3004 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3005 } 3006 /* 3007 * Enable fix for read DMA FIFO overruns. 3008 * The fix is to limit the number of RX BDs 3009 * the hardware would fetch at a fime. 3010 */ 3011 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3012 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3013 } 3014 3015 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3016 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3017 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3018 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3019 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3020 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3021 /* 3022 * Allow 4KB burst length reads for non-LSO frames. 3023 * Enable 512B burst length reads for buffer descriptors. 3024 */ 3025 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3026 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3027 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3028 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3029 } 3030 3031 /* Turn on read DMA state machine */ 3032 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3033 delay(40); 3034 3035 /* Turn on RX data completion state machine */ 3036 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3037 3038 /* Turn on RX data and RX BD initiator state machine */ 3039 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3040 3041 /* Turn on Mbuf cluster free state machine */ 3042 if (!BGE_IS_5705_PLUS(sc)) 3043 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3044 3045 /* Turn on send data completion state machine */ 3046 val = BGE_SDCMODE_ENABLE; 3047 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3048 val |= BGE_SDCMODE_CDELAY; 3049 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3050 3051 /* Turn on send BD completion state machine */ 3052 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3053 3054 /* Turn on RX BD initiator state machine */ 3055 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3056 3057 /* Turn on send data initiator state machine */ 3058 if (sc->bge_flags & BGE_TSO) { 3059 /* XXX: magic value from Linux driver */ 3060 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3061 BGE_SDIMODE_HW_LSO_PRE_DMA); 3062 } else 3063 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3064 3065 /* Turn on send BD initiator state machine */ 3066 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3067 3068 /* Turn on send BD selector state machine */ 3069 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3070 3071 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3072 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3073 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3074 3075 /* ack/clear link change events */ 3076 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3077 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3078 BGE_MACSTAT_LINK_CHANGED); 3079 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3080 3081 /* 3082 * Enable attention when the link has changed state for 3083 * devices that use auto polling. 3084 */ 3085 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3086 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3087 } else { 3088 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3089 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3090 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3091 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3092 BGE_EVTENB_MI_INTERRUPT); 3093 } 3094 3095 /* 3096 * Clear any pending link state attention. 3097 * Otherwise some link state change events may be lost until attention 3098 * is cleared by bge_intr() -> bge_link_upd() sequence. 3099 * It's not necessary on newer BCM chips - perhaps enabling link 3100 * state change attentions implies clearing pending attention. 3101 */ 3102 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3103 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3104 BGE_MACSTAT_LINK_CHANGED); 3105 3106 /* Enable link state change attentions. */ 3107 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3108 3109 return 0; 3110 } 3111 3112 static const struct bge_revision * 3113 bge_lookup_rev(uint32_t chipid) 3114 { 3115 const struct bge_revision *br; 3116 3117 for (br = bge_revisions; br->br_name != NULL; br++) { 3118 if (br->br_chipid == chipid) 3119 return br; 3120 } 3121 3122 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3123 if (br->br_chipid == BGE_ASICREV(chipid)) 3124 return br; 3125 } 3126 3127 return NULL; 3128 } 3129 3130 static const struct bge_product * 3131 bge_lookup(const struct pci_attach_args *pa) 3132 { 3133 const struct bge_product *bp; 3134 3135 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3136 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3137 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3138 return bp; 3139 } 3140 3141 return NULL; 3142 } 3143 3144 static uint32_t 3145 bge_chipid(const struct pci_attach_args *pa) 3146 { 3147 uint32_t id; 3148 3149 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3150 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3151 3152 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3153 switch (PCI_PRODUCT(pa->pa_id)) { 3154 case PCI_PRODUCT_BROADCOM_BCM5717: 3155 case PCI_PRODUCT_BROADCOM_BCM5718: 3156 case PCI_PRODUCT_BROADCOM_BCM5719: 3157 case PCI_PRODUCT_BROADCOM_BCM5720: 3158 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3159 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3160 BGE_PCI_GEN2_PRODID_ASICREV); 3161 break; 3162 case PCI_PRODUCT_BROADCOM_BCM57761: 3163 case PCI_PRODUCT_BROADCOM_BCM57762: 3164 case PCI_PRODUCT_BROADCOM_BCM57765: 3165 case PCI_PRODUCT_BROADCOM_BCM57766: 3166 case PCI_PRODUCT_BROADCOM_BCM57781: 3167 case PCI_PRODUCT_BROADCOM_BCM57785: 3168 case PCI_PRODUCT_BROADCOM_BCM57791: 3169 case PCI_PRODUCT_BROADCOM_BCM57795: 3170 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3171 BGE_PCI_GEN15_PRODID_ASICREV); 3172 break; 3173 default: 3174 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3175 BGE_PCI_PRODID_ASICREV); 3176 break; 3177 } 3178 } 3179 3180 return id; 3181 } 3182 3183 /* 3184 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3185 * against our list and return its name if we find a match. Note 3186 * that since the Broadcom controller contains VPD support, we 3187 * can get the device name string from the controller itself instead 3188 * of the compiled-in string. This is a little slow, but it guarantees 3189 * we'll always announce the right product name. 3190 */ 3191 static int 3192 bge_probe(device_t parent, cfdata_t match, void *aux) 3193 { 3194 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3195 3196 if (bge_lookup(pa) != NULL) 3197 return 1; 3198 3199 return 0; 3200 } 3201 3202 static void 3203 bge_attach(device_t parent, device_t self, void *aux) 3204 { 3205 struct bge_softc *sc = device_private(self); 3206 struct pci_attach_args *pa = aux; 3207 prop_dictionary_t dict; 3208 const struct bge_product *bp; 3209 const struct bge_revision *br; 3210 pci_chipset_tag_t pc; 3211 pci_intr_handle_t ih; 3212 const char *intrstr = NULL; 3213 uint32_t hwcfg = 0; 3214 uint32_t command; 3215 struct ifnet *ifp; 3216 uint32_t misccfg; 3217 void * kva; 3218 u_char eaddr[ETHER_ADDR_LEN]; 3219 pcireg_t memtype, subid, reg; 3220 bus_addr_t memaddr; 3221 uint32_t pm_ctl; 3222 bool no_seeprom; 3223 int capmask; 3224 3225 bp = bge_lookup(pa); 3226 KASSERT(bp != NULL); 3227 3228 sc->sc_pc = pa->pa_pc; 3229 sc->sc_pcitag = pa->pa_tag; 3230 sc->bge_dev = self; 3231 3232 sc->bge_pa = *pa; 3233 pc = sc->sc_pc; 3234 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3235 3236 aprint_naive(": Ethernet controller\n"); 3237 aprint_normal(": %s\n", bp->bp_name); 3238 3239 /* 3240 * Map control/status registers. 3241 */ 3242 DPRINTFN(5, ("Map control/status regs\n")); 3243 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3244 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3245 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3246 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3247 3248 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3249 aprint_error_dev(sc->bge_dev, 3250 "failed to enable memory mapping!\n"); 3251 return; 3252 } 3253 3254 DPRINTFN(5, ("pci_mem_find\n")); 3255 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3256 switch (memtype) { 3257 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3258 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3259 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3260 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3261 &memaddr, &sc->bge_bsize) == 0) 3262 break; 3263 default: 3264 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3265 return; 3266 } 3267 3268 DPRINTFN(5, ("pci_intr_map\n")); 3269 if (pci_intr_map(pa, &ih)) { 3270 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3271 return; 3272 } 3273 3274 DPRINTFN(5, ("pci_intr_string\n")); 3275 intrstr = pci_intr_string(pc, ih); 3276 3277 DPRINTFN(5, ("pci_intr_establish\n")); 3278 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3279 3280 if (sc->bge_intrhand == NULL) { 3281 aprint_error_dev(sc->bge_dev, 3282 "couldn't establish interrupt%s%s\n", 3283 intrstr ? " at " : "", intrstr ? intrstr : ""); 3284 return; 3285 } 3286 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3287 3288 /* Save various chip information. */ 3289 sc->bge_chipid = bge_chipid(pa); 3290 sc->bge_phy_addr = bge_phy_addr(sc); 3291 3292 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3293 &sc->bge_pciecap, NULL) != 0) 3294 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3295 /* PCIe */ 3296 sc->bge_flags |= BGE_PCIE; 3297 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3298 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3299 sc->bge_expmrq = 2048; 3300 else 3301 sc->bge_expmrq = 4096; 3302 bge_set_max_readrq(sc); 3303 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3304 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3305 /* PCI-X */ 3306 sc->bge_flags |= BGE_PCIX; 3307 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3308 &sc->bge_pcixcap, NULL) == 0) 3309 aprint_error_dev(sc->bge_dev, 3310 "unable to find PCIX capability\n"); 3311 } 3312 3313 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3314 /* 3315 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3316 * can clobber the chip's PCI config-space power control 3317 * registers, leaving the card in D3 powersave state. We do 3318 * not have memory-mapped registers in this state, so force 3319 * device into D0 state before starting initialization. 3320 */ 3321 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3322 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3323 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3324 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3325 DELAY(1000); /* 27 usec is allegedly sufficent */ 3326 } 3327 3328 /* Save chipset family. */ 3329 switch (BGE_ASICREV(sc->bge_chipid)) { 3330 case BGE_ASICREV_BCM57765: 3331 case BGE_ASICREV_BCM57766: 3332 sc->bge_flags |= BGE_57765_PLUS; 3333 /* FALLTHROUGH */ 3334 case BGE_ASICREV_BCM5717: 3335 case BGE_ASICREV_BCM5719: 3336 case BGE_ASICREV_BCM5720: 3337 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3338 BGE_5705_PLUS; 3339 break; 3340 case BGE_ASICREV_BCM5755: 3341 case BGE_ASICREV_BCM5761: 3342 case BGE_ASICREV_BCM5784: 3343 case BGE_ASICREV_BCM5785: 3344 case BGE_ASICREV_BCM5787: 3345 case BGE_ASICREV_BCM57780: 3346 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3347 break; 3348 case BGE_ASICREV_BCM5700: 3349 case BGE_ASICREV_BCM5701: 3350 case BGE_ASICREV_BCM5703: 3351 case BGE_ASICREV_BCM5704: 3352 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3353 break; 3354 case BGE_ASICREV_BCM5714_A0: 3355 case BGE_ASICREV_BCM5780: 3356 case BGE_ASICREV_BCM5714: 3357 sc->bge_flags |= BGE_5714_FAMILY; 3358 /* FALLTHROUGH */ 3359 case BGE_ASICREV_BCM5750: 3360 case BGE_ASICREV_BCM5752: 3361 case BGE_ASICREV_BCM5906: 3362 sc->bge_flags |= BGE_575X_PLUS; 3363 /* FALLTHROUGH */ 3364 case BGE_ASICREV_BCM5705: 3365 sc->bge_flags |= BGE_5705_PLUS; 3366 break; 3367 } 3368 3369 /* Identify chips with APE processor. */ 3370 switch (BGE_ASICREV(sc->bge_chipid)) { 3371 case BGE_ASICREV_BCM5717: 3372 case BGE_ASICREV_BCM5719: 3373 case BGE_ASICREV_BCM5720: 3374 case BGE_ASICREV_BCM5761: 3375 sc->bge_flags |= BGE_APE; 3376 break; 3377 } 3378 3379 /* Chips with APE need BAR2 access for APE registers/memory. */ 3380 if ((sc->bge_flags & BGE_APE) != 0) { 3381 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3382 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3383 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3384 &sc->bge_apesize)) { 3385 aprint_error_dev(sc->bge_dev, 3386 "couldn't map BAR2 memory\n"); 3387 return; 3388 } 3389 3390 /* Enable APE register/memory access by host driver. */ 3391 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3392 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3393 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3394 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3395 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3396 3397 bge_ape_lock_init(sc); 3398 bge_ape_read_fw_ver(sc); 3399 } 3400 3401 /* Identify the chips that use an CPMU. */ 3402 if (BGE_IS_5717_PLUS(sc) || 3403 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3404 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3405 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3406 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3407 sc->bge_flags |= BGE_CPMU_PRESENT; 3408 3409 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3410 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3411 else 3412 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3413 3414 /* 3415 * When using the BCM5701 in PCI-X mode, data corruption has 3416 * been observed in the first few bytes of some received packets. 3417 * Aligning the packet buffer in memory eliminates the corruption. 3418 * Unfortunately, this misaligns the packet payloads. On platforms 3419 * which do not support unaligned accesses, we will realign the 3420 * payloads by copying the received packets. 3421 */ 3422 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3423 sc->bge_flags & BGE_PCIX) 3424 sc->bge_flags |= BGE_RX_ALIGNBUG; 3425 3426 if (BGE_IS_5700_FAMILY(sc)) 3427 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3428 3429 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3430 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3431 3432 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3433 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3434 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3435 sc->bge_flags |= BGE_IS_5788; 3436 3437 /* 3438 * Some controllers seem to require a special firmware to use 3439 * TSO. But the firmware is not available to FreeBSD and Linux 3440 * claims that the TSO performed by the firmware is slower than 3441 * hardware based TSO. Moreover the firmware based TSO has one 3442 * known bug which can't handle TSO if ethernet header + IP/TCP 3443 * header is greater than 80 bytes. The workaround for the TSO 3444 * bug exist but it seems it's too expensive than not using 3445 * TSO at all. Some hardwares also have the TSO bug so limit 3446 * the TSO to the controllers that are not affected TSO issues 3447 * (e.g. 5755 or higher). 3448 */ 3449 if (BGE_IS_5755_PLUS(sc)) { 3450 /* 3451 * BCM5754 and BCM5787 shares the same ASIC id so 3452 * explicit device id check is required. 3453 */ 3454 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3455 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3456 sc->bge_flags |= BGE_TSO; 3457 } 3458 3459 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3460 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3461 (misccfg == 0x4000 || misccfg == 0x8000)) || 3462 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3463 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3464 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3465 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3466 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3467 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3468 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3469 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3470 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3471 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3472 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3473 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3474 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3475 capmask &= ~BMSR_EXTSTAT; 3476 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3477 } 3478 3479 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3480 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3481 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3482 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3483 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3484 3485 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3486 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 3487 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766 || 3488 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 && 3489 sc->bge_chipid != BGE_CHIPID_BCM5717_A0) || 3490 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 && 3491 sc->bge_chipid != BGE_CHIPID_BCM57765_A0)) 3492 sc->bge_flags |= BGE_PHY_EEE; 3493 3494 /* Set various PHY bug flags. */ 3495 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3496 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3497 sc->bge_flags |= BGE_PHY_CRC_BUG; 3498 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3499 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3500 sc->bge_flags |= BGE_PHY_ADC_BUG; 3501 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3502 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3503 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3504 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3505 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3506 sc->bge_flags |= BGE_PHY_NO_3LED; 3507 if (BGE_IS_5705_PLUS(sc) && 3508 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3509 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3510 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3511 !BGE_IS_5717_PLUS(sc)) { 3512 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3513 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3514 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3515 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3516 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3517 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3518 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3519 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3520 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3521 } else 3522 sc->bge_flags |= BGE_PHY_BER_BUG; 3523 } 3524 3525 /* 3526 * SEEPROM check. 3527 * First check if firmware knows we do not have SEEPROM. 3528 */ 3529 if (prop_dictionary_get_bool(device_properties(self), 3530 "without-seeprom", &no_seeprom) && no_seeprom) 3531 sc->bge_flags |= BGE_NO_EEPROM; 3532 3533 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3534 sc->bge_flags |= BGE_NO_EEPROM; 3535 3536 /* Now check the 'ROM failed' bit on the RX CPU */ 3537 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3538 sc->bge_flags |= BGE_NO_EEPROM; 3539 3540 sc->bge_asf_mode = 0; 3541 /* No ASF if APE present. */ 3542 if ((sc->bge_flags & BGE_APE) == 0) { 3543 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3544 BGE_SRAM_DATA_SIG_MAGIC)) { 3545 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3546 BGE_HWCFG_ASF) { 3547 sc->bge_asf_mode |= ASF_ENABLE; 3548 sc->bge_asf_mode |= ASF_STACKUP; 3549 if (BGE_IS_575X_PLUS(sc)) 3550 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3551 } 3552 } 3553 } 3554 3555 bge_stop_fw(sc); 3556 bge_sig_pre_reset(sc, BGE_RESET_START); 3557 if (bge_reset(sc)) 3558 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3559 3560 bge_sig_legacy(sc, BGE_RESET_START); 3561 bge_sig_post_reset(sc, BGE_RESET_START); 3562 3563 if (bge_chipinit(sc)) { 3564 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3565 bge_release_resources(sc); 3566 return; 3567 } 3568 3569 /* 3570 * Get station address from the EEPROM. 3571 */ 3572 if (bge_get_eaddr(sc, eaddr)) { 3573 aprint_error_dev(sc->bge_dev, 3574 "failed to read station address\n"); 3575 bge_release_resources(sc); 3576 return; 3577 } 3578 3579 br = bge_lookup_rev(sc->bge_chipid); 3580 3581 if (br == NULL) { 3582 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3583 sc->bge_chipid); 3584 } else { 3585 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3586 br->br_name, sc->bge_chipid); 3587 } 3588 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3589 3590 /* Allocate the general information block and ring buffers. */ 3591 if (pci_dma64_available(pa)) 3592 sc->bge_dmatag = pa->pa_dmat64; 3593 else 3594 sc->bge_dmatag = pa->pa_dmat; 3595 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3596 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3597 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3598 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3599 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3600 return; 3601 } 3602 DPRINTFN(5, ("bus_dmamem_map\n")); 3603 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3604 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3605 BUS_DMA_NOWAIT)) { 3606 aprint_error_dev(sc->bge_dev, 3607 "can't map DMA buffers (%zu bytes)\n", 3608 sizeof(struct bge_ring_data)); 3609 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3610 sc->bge_ring_rseg); 3611 return; 3612 } 3613 DPRINTFN(5, ("bus_dmamem_create\n")); 3614 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3615 sizeof(struct bge_ring_data), 0, 3616 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3617 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3618 bus_dmamem_unmap(sc->bge_dmatag, kva, 3619 sizeof(struct bge_ring_data)); 3620 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3621 sc->bge_ring_rseg); 3622 return; 3623 } 3624 DPRINTFN(5, ("bus_dmamem_load\n")); 3625 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3626 sizeof(struct bge_ring_data), NULL, 3627 BUS_DMA_NOWAIT)) { 3628 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3629 bus_dmamem_unmap(sc->bge_dmatag, kva, 3630 sizeof(struct bge_ring_data)); 3631 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3632 sc->bge_ring_rseg); 3633 return; 3634 } 3635 3636 DPRINTFN(5, ("bzero\n")); 3637 sc->bge_rdata = (struct bge_ring_data *)kva; 3638 3639 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3640 3641 /* Try to allocate memory for jumbo buffers. */ 3642 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3643 if (bge_alloc_jumbo_mem(sc)) { 3644 aprint_error_dev(sc->bge_dev, 3645 "jumbo buffer allocation failed\n"); 3646 } else 3647 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3648 } 3649 3650 /* Set default tuneable values. */ 3651 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3652 sc->bge_rx_coal_ticks = 150; 3653 sc->bge_rx_max_coal_bds = 64; 3654 sc->bge_tx_coal_ticks = 300; 3655 sc->bge_tx_max_coal_bds = 400; 3656 if (BGE_IS_5705_PLUS(sc)) { 3657 sc->bge_tx_coal_ticks = (12 * 5); 3658 sc->bge_tx_max_coal_bds = (12 * 5); 3659 aprint_verbose_dev(sc->bge_dev, 3660 "setting short Tx thresholds\n"); 3661 } 3662 3663 if (BGE_IS_5717_PLUS(sc)) 3664 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3665 else if (BGE_IS_5705_PLUS(sc)) 3666 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3667 else 3668 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3669 3670 /* Set up ifnet structure */ 3671 ifp = &sc->ethercom.ec_if; 3672 ifp->if_softc = sc; 3673 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3674 ifp->if_ioctl = bge_ioctl; 3675 ifp->if_stop = bge_stop; 3676 ifp->if_start = bge_start; 3677 ifp->if_init = bge_init; 3678 ifp->if_watchdog = bge_watchdog; 3679 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3680 IFQ_SET_READY(&ifp->if_snd); 3681 DPRINTFN(5, ("strcpy if_xname\n")); 3682 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3683 3684 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3685 sc->ethercom.ec_if.if_capabilities |= 3686 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3687 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3688 sc->ethercom.ec_if.if_capabilities |= 3689 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3690 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3691 #endif 3692 sc->ethercom.ec_capabilities |= 3693 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3694 3695 if (sc->bge_flags & BGE_TSO) 3696 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3697 3698 /* 3699 * Do MII setup. 3700 */ 3701 DPRINTFN(5, ("mii setup\n")); 3702 sc->bge_mii.mii_ifp = ifp; 3703 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3704 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3705 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3706 3707 /* 3708 * Figure out what sort of media we have by checking the hardware 3709 * config word in the first 32k of NIC internal memory, or fall back to 3710 * the config word in the EEPROM. Note: on some BCM5700 cards, 3711 * this value appears to be unset. If that's the case, we have to rely 3712 * on identifying the NIC by its PCI subsystem ID, as we do below for 3713 * the SysKonnect SK-9D41. 3714 */ 3715 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3716 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3717 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3718 bge_read_eeprom(sc, (void *)&hwcfg, 3719 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3720 hwcfg = be32toh(hwcfg); 3721 } 3722 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3723 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3724 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3725 if (BGE_IS_5714_FAMILY(sc)) 3726 sc->bge_flags |= BGE_PHY_FIBER_MII; 3727 else 3728 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3729 } 3730 3731 /* set phyflags and chipid before mii_attach() */ 3732 dict = device_properties(self); 3733 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3734 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3735 3736 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3737 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3738 bge_ifmedia_sts); 3739 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3740 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3741 0, NULL); 3742 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3743 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3744 /* Pretend the user requested this setting */ 3745 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3746 } else { 3747 /* 3748 * Do transceiver setup and tell the firmware the 3749 * driver is down so we can try to get access the 3750 * probe if ASF is running. Retry a couple of times 3751 * if we get a conflict with the ASF firmware accessing 3752 * the PHY. 3753 */ 3754 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3755 bge_asf_driver_up(sc); 3756 3757 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3758 bge_ifmedia_sts); 3759 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3760 sc->bge_phy_addr, MII_OFFSET_ANY, 3761 MIIF_DOPAUSE); 3762 3763 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3764 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3765 ifmedia_add(&sc->bge_mii.mii_media, 3766 IFM_ETHER|IFM_MANUAL, 0, NULL); 3767 ifmedia_set(&sc->bge_mii.mii_media, 3768 IFM_ETHER|IFM_MANUAL); 3769 } else 3770 ifmedia_set(&sc->bge_mii.mii_media, 3771 IFM_ETHER|IFM_AUTO); 3772 3773 /* 3774 * Now tell the firmware we are going up after probing the PHY 3775 */ 3776 if (sc->bge_asf_mode & ASF_STACKUP) 3777 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3778 } 3779 3780 /* 3781 * Call MI attach routine. 3782 */ 3783 DPRINTFN(5, ("if_attach\n")); 3784 if_attach(ifp); 3785 DPRINTFN(5, ("ether_ifattach\n")); 3786 ether_ifattach(ifp, eaddr); 3787 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3788 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3789 RND_TYPE_NET, 0); 3790 #ifdef BGE_EVENT_COUNTERS 3791 /* 3792 * Attach event counters. 3793 */ 3794 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3795 NULL, device_xname(sc->bge_dev), "intr"); 3796 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3797 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3798 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3799 NULL, device_xname(sc->bge_dev), "tx_xon"); 3800 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3801 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3802 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3803 NULL, device_xname(sc->bge_dev), "rx_xon"); 3804 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3805 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3806 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3807 NULL, device_xname(sc->bge_dev), "xoffentered"); 3808 #endif /* BGE_EVENT_COUNTERS */ 3809 DPRINTFN(5, ("callout_init\n")); 3810 callout_init(&sc->bge_timeout, 0); 3811 3812 if (pmf_device_register(self, NULL, NULL)) 3813 pmf_class_network_register(self, ifp); 3814 else 3815 aprint_error_dev(self, "couldn't establish power handler\n"); 3816 3817 bge_sysctl_init(sc); 3818 3819 #ifdef BGE_DEBUG 3820 bge_debug_info(sc); 3821 #endif 3822 } 3823 3824 /* 3825 * Stop all chip I/O so that the kernel's probe routines don't 3826 * get confused by errant DMAs when rebooting. 3827 */ 3828 static int 3829 bge_detach(device_t self, int flags __unused) 3830 { 3831 struct bge_softc *sc = device_private(self); 3832 struct ifnet *ifp = &sc->ethercom.ec_if; 3833 int s; 3834 3835 s = splnet(); 3836 /* Stop the interface. Callouts are stopped in it. */ 3837 bge_stop(ifp, 1); 3838 splx(s); 3839 3840 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3841 3842 /* Delete all remaining media. */ 3843 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3844 3845 ether_ifdetach(ifp); 3846 if_detach(ifp); 3847 3848 bge_release_resources(sc); 3849 3850 return 0; 3851 } 3852 3853 static void 3854 bge_release_resources(struct bge_softc *sc) 3855 { 3856 3857 /* Disestablish the interrupt handler */ 3858 if (sc->bge_intrhand != NULL) { 3859 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3860 sc->bge_intrhand = NULL; 3861 } 3862 3863 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3864 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3865 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3866 sizeof(struct bge_ring_data)); 3867 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3868 3869 /* Unmap the device registers */ 3870 if (sc->bge_bsize != 0) { 3871 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3872 sc->bge_bsize = 0; 3873 } 3874 3875 /* Unmap the APE registers */ 3876 if (sc->bge_apesize != 0) { 3877 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3878 sc->bge_apesize); 3879 sc->bge_apesize = 0; 3880 } 3881 } 3882 3883 static int 3884 bge_reset(struct bge_softc *sc) 3885 { 3886 uint32_t cachesize, command; 3887 uint32_t reset, mac_mode, mac_mode_mask; 3888 pcireg_t devctl, reg; 3889 int i, val; 3890 void (*write_op)(struct bge_softc *, int, int); 3891 3892 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3893 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3894 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3895 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3896 3897 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3898 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3899 if (sc->bge_flags & BGE_PCIE) 3900 write_op = bge_writemem_direct; 3901 else 3902 write_op = bge_writemem_ind; 3903 } else 3904 write_op = bge_writereg_ind; 3905 3906 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3907 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3908 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3909 for (i = 0; i < 8000; i++) { 3910 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3911 BGE_NVRAMSWARB_GNT1) 3912 break; 3913 DELAY(20); 3914 } 3915 if (i == 8000) { 3916 printf("%s: NVRAM lock timedout!\n", 3917 device_xname(sc->bge_dev)); 3918 } 3919 } 3920 /* Take APE lock when performing reset. */ 3921 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3922 3923 /* Save some important PCI state. */ 3924 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3925 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3926 3927 /* Step 5b-5d: */ 3928 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3929 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3930 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3931 3932 /* XXX ???: Disable fastboot on controllers that support it. */ 3933 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3934 BGE_IS_5755_PLUS(sc)) 3935 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3936 3937 /* 3938 * Step 6: Write the magic number to SRAM at offset 0xB50. 3939 * When firmware finishes its initialization it will 3940 * write ~BGE_MAGIC_NUMBER to the same location. 3941 */ 3942 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3943 3944 /* Step 7: */ 3945 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3946 /* 3947 * XXX: from FreeBSD/Linux; no documentation 3948 */ 3949 if (sc->bge_flags & BGE_PCIE) { 3950 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3951 !BGE_IS_57765_PLUS(sc) && 3952 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3953 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3954 /* PCI Express 1.0 system */ 3955 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3956 BGE_PHY_PCIE_SCRAM_MODE); 3957 } 3958 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3959 /* 3960 * Prevent PCI Express link training 3961 * during global reset. 3962 */ 3963 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3964 reset |= (1 << 29); 3965 } 3966 } 3967 3968 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3969 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3970 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3971 i | BGE_VCPU_STATUS_DRV_RESET); 3972 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3973 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3974 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3975 } 3976 3977 /* 3978 * Set GPHY Power Down Override to leave GPHY 3979 * powered up in D0 uninitialized. 3980 */ 3981 if (BGE_IS_5705_PLUS(sc) && 3982 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3983 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3984 3985 /* Issue global reset */ 3986 write_op(sc, BGE_MISC_CFG, reset); 3987 3988 /* Step 8: wait for complete */ 3989 if (sc->bge_flags & BGE_PCIE) 3990 delay(100*1000); /* too big */ 3991 else 3992 delay(1000); 3993 3994 if (sc->bge_flags & BGE_PCIE) { 3995 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3996 DELAY(500000); 3997 /* XXX: Magic Numbers */ 3998 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3999 BGE_PCI_UNKNOWN0); 4000 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4001 BGE_PCI_UNKNOWN0, 4002 reg | (1 << 15)); 4003 } 4004 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4005 sc->bge_pciecap + PCI_PCIE_DCSR); 4006 /* Clear enable no snoop and disable relaxed ordering. */ 4007 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 4008 PCI_PCIE_DCSR_ENA_NO_SNOOP); 4009 4010 /* Set PCIE max payload size to 128 for older PCIe devices */ 4011 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4012 devctl &= ~(0x00e0); 4013 /* Clear device status register. Write 1b to clear */ 4014 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 4015 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 4016 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4017 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 4018 bge_set_max_readrq(sc); 4019 } 4020 4021 /* From Linux: dummy read to flush PCI posted writes */ 4022 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4023 4024 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 4025 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4026 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4027 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4028 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4029 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4030 (sc->bge_flags & BGE_PCIX) != 0) 4031 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4032 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4033 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4034 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4035 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4036 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4037 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4038 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4039 4040 /* Step 11: disable PCI-X Relaxed Ordering. */ 4041 if (sc->bge_flags & BGE_PCIX) { 4042 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4043 + PCI_PCIX_CMD); 4044 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4045 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 4046 } 4047 4048 /* Step 12: Enable memory arbiter. */ 4049 if (BGE_IS_5714_FAMILY(sc)) { 4050 val = CSR_READ_4(sc, BGE_MARB_MODE); 4051 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4052 } else 4053 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4054 4055 /* XXX 5721, 5751 and 5752 */ 4056 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4057 /* Step 19: */ 4058 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4059 /* Step 20: */ 4060 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4061 } 4062 4063 /* Step 28: Fix up byte swapping */ 4064 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4065 4066 /* 4067 * Wait for the bootcode to complete initialization. 4068 * See BCM5718 programmer's guide's "step 13, Device reset Procedure, 4069 * Section 7". 4070 */ 4071 if (BGE_IS_5717_PLUS(sc)) { 4072 for (i = 0; i < 1000*1000; i++) { 4073 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4074 if (val == BGE_SRAM_FW_MB_RESET_MAGIC) 4075 break; 4076 DELAY(10); 4077 } 4078 } 4079 4080 /* Step 21: 5822 B0 errata */ 4081 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4082 pcireg_t msidata; 4083 4084 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4085 BGE_PCI_MSI_DATA); 4086 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4087 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4088 msidata); 4089 } 4090 4091 /* 4092 * Step 18: wirte mac mode 4093 * XXX Write 0x0c for 5703S and 5704S 4094 */ 4095 val = CSR_READ_4(sc, BGE_MAC_MODE); 4096 val = (val & ~mac_mode_mask) | mac_mode; 4097 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4098 DELAY(40); 4099 4100 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4101 4102 /* Step 17: Poll until the firmware initialization is complete */ 4103 bge_poll_fw(sc); 4104 4105 /* 4106 * The 5704 in TBI mode apparently needs some special 4107 * adjustment to insure the SERDES drive level is set 4108 * to 1.2V. 4109 */ 4110 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4111 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4112 uint32_t serdescfg; 4113 4114 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4115 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4116 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4117 } 4118 4119 if (sc->bge_flags & BGE_PCIE && 4120 !BGE_IS_57765_PLUS(sc) && 4121 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4122 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4123 uint32_t v; 4124 4125 /* Enable PCI Express bug fix */ 4126 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4127 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4128 v | BGE_TLP_DATA_FIFO_PROTECT); 4129 } 4130 4131 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4132 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4133 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4134 4135 if ((sc->bge_flags & BGE_PHY_EEE) != 0) { 4136 uint32_t eeemode; 4137 4138 eeemode = CSR_READ_4(sc, BGE_CPMU_EEE_MODE); 4139 printf("EEEMODE = %x\n", eeemode); 4140 CSR_WRITE_4(sc, BGE_CPMU_EEE_MODE, 0); 4141 } 4142 return 0; 4143 } 4144 4145 /* 4146 * Frame reception handling. This is called if there's a frame 4147 * on the receive return list. 4148 * 4149 * Note: we have to be able to handle two possibilities here: 4150 * 1) the frame is from the jumbo receive ring 4151 * 2) the frame is from the standard receive ring 4152 */ 4153 4154 static void 4155 bge_rxeof(struct bge_softc *sc) 4156 { 4157 struct ifnet *ifp; 4158 uint16_t rx_prod, rx_cons; 4159 int stdcnt = 0, jumbocnt = 0; 4160 bus_dmamap_t dmamap; 4161 bus_addr_t offset, toff; 4162 bus_size_t tlen; 4163 int tosync; 4164 4165 rx_cons = sc->bge_rx_saved_considx; 4166 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4167 4168 /* Nothing to do */ 4169 if (rx_cons == rx_prod) 4170 return; 4171 4172 ifp = &sc->ethercom.ec_if; 4173 4174 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4175 offsetof(struct bge_ring_data, bge_status_block), 4176 sizeof (struct bge_status_block), 4177 BUS_DMASYNC_POSTREAD); 4178 4179 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4180 tosync = rx_prod - rx_cons; 4181 4182 if (tosync != 0) 4183 rnd_add_uint32(&sc->rnd_source, tosync); 4184 4185 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4186 4187 if (tosync < 0) { 4188 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4189 sizeof (struct bge_rx_bd); 4190 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4191 toff, tlen, BUS_DMASYNC_POSTREAD); 4192 tosync = -tosync; 4193 } 4194 4195 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4196 offset, tosync * sizeof (struct bge_rx_bd), 4197 BUS_DMASYNC_POSTREAD); 4198 4199 while (rx_cons != rx_prod) { 4200 struct bge_rx_bd *cur_rx; 4201 uint32_t rxidx; 4202 struct mbuf *m = NULL; 4203 4204 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4205 4206 rxidx = cur_rx->bge_idx; 4207 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4208 4209 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4210 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4211 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4212 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4213 jumbocnt++; 4214 bus_dmamap_sync(sc->bge_dmatag, 4215 sc->bge_cdata.bge_rx_jumbo_map, 4216 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4217 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4218 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4219 ifp->if_ierrors++; 4220 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4221 continue; 4222 } 4223 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4224 NULL)== ENOBUFS) { 4225 ifp->if_ierrors++; 4226 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4227 continue; 4228 } 4229 } else { 4230 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4231 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4232 4233 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4234 stdcnt++; 4235 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4236 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4237 if (dmamap == NULL) { 4238 ifp->if_ierrors++; 4239 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4240 continue; 4241 } 4242 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4243 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4244 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4245 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4246 ifp->if_ierrors++; 4247 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4248 continue; 4249 } 4250 if (bge_newbuf_std(sc, sc->bge_std, 4251 NULL, dmamap) == ENOBUFS) { 4252 ifp->if_ierrors++; 4253 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4254 continue; 4255 } 4256 } 4257 4258 ifp->if_ipackets++; 4259 #ifndef __NO_STRICT_ALIGNMENT 4260 /* 4261 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4262 * the Rx buffer has the layer-2 header unaligned. 4263 * If our CPU requires alignment, re-align by copying. 4264 */ 4265 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4266 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4267 cur_rx->bge_len); 4268 m->m_data += ETHER_ALIGN; 4269 } 4270 #endif 4271 4272 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4273 m->m_pkthdr.rcvif = ifp; 4274 4275 /* 4276 * Handle BPF listeners. Let the BPF user see the packet. 4277 */ 4278 bpf_mtap(ifp, m); 4279 4280 bge_rxcsum(sc, cur_rx, m); 4281 4282 /* 4283 * If we received a packet with a vlan tag, pass it 4284 * to vlan_input() instead of ether_input(). 4285 */ 4286 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4287 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4288 } 4289 4290 (*ifp->if_input)(ifp, m); 4291 } 4292 4293 sc->bge_rx_saved_considx = rx_cons; 4294 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4295 if (stdcnt) 4296 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4297 if (jumbocnt) 4298 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4299 } 4300 4301 static void 4302 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4303 { 4304 4305 if (BGE_IS_5717_PLUS(sc)) { 4306 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4307 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4308 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4309 if ((cur_rx->bge_error_flag & 4310 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4311 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4312 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4313 m->m_pkthdr.csum_data = 4314 cur_rx->bge_tcp_udp_csum; 4315 m->m_pkthdr.csum_flags |= 4316 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4317 M_CSUM_DATA); 4318 } 4319 } 4320 } else { 4321 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4322 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4323 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4324 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4325 /* 4326 * Rx transport checksum-offload may also 4327 * have bugs with packets which, when transmitted, 4328 * were `runts' requiring padding. 4329 */ 4330 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4331 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4332 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4333 m->m_pkthdr.csum_data = 4334 cur_rx->bge_tcp_udp_csum; 4335 m->m_pkthdr.csum_flags |= 4336 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4337 M_CSUM_DATA); 4338 } 4339 } 4340 } 4341 4342 static void 4343 bge_txeof(struct bge_softc *sc) 4344 { 4345 struct bge_tx_bd *cur_tx = NULL; 4346 struct ifnet *ifp; 4347 struct txdmamap_pool_entry *dma; 4348 bus_addr_t offset, toff; 4349 bus_size_t tlen; 4350 int tosync; 4351 struct mbuf *m; 4352 4353 ifp = &sc->ethercom.ec_if; 4354 4355 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4356 offsetof(struct bge_ring_data, bge_status_block), 4357 sizeof (struct bge_status_block), 4358 BUS_DMASYNC_POSTREAD); 4359 4360 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4361 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4362 sc->bge_tx_saved_considx; 4363 4364 if (tosync != 0) 4365 rnd_add_uint32(&sc->rnd_source, tosync); 4366 4367 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4368 4369 if (tosync < 0) { 4370 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4371 sizeof (struct bge_tx_bd); 4372 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4373 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4374 tosync = -tosync; 4375 } 4376 4377 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4378 offset, tosync * sizeof (struct bge_tx_bd), 4379 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4380 4381 /* 4382 * Go through our tx ring and free mbufs for those 4383 * frames that have been sent. 4384 */ 4385 while (sc->bge_tx_saved_considx != 4386 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4387 uint32_t idx = 0; 4388 4389 idx = sc->bge_tx_saved_considx; 4390 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4391 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4392 ifp->if_opackets++; 4393 m = sc->bge_cdata.bge_tx_chain[idx]; 4394 if (m != NULL) { 4395 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4396 dma = sc->txdma[idx]; 4397 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4398 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4399 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4400 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4401 sc->txdma[idx] = NULL; 4402 4403 m_freem(m); 4404 } 4405 sc->bge_txcnt--; 4406 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4407 ifp->if_timer = 0; 4408 } 4409 4410 if (cur_tx != NULL) 4411 ifp->if_flags &= ~IFF_OACTIVE; 4412 } 4413 4414 static int 4415 bge_intr(void *xsc) 4416 { 4417 struct bge_softc *sc; 4418 struct ifnet *ifp; 4419 uint32_t statusword; 4420 4421 sc = xsc; 4422 ifp = &sc->ethercom.ec_if; 4423 4424 /* It is possible for the interrupt to arrive before 4425 * the status block is updated prior to the interrupt. 4426 * Reading the PCI State register will confirm whether the 4427 * interrupt is ours and will flush the status block. 4428 */ 4429 4430 /* read status word from status block */ 4431 statusword = sc->bge_rdata->bge_status_block.bge_status; 4432 4433 if ((statusword & BGE_STATFLAG_UPDATED) || 4434 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4435 /* Ack interrupt and stop others from occuring. */ 4436 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4437 4438 BGE_EVCNT_INCR(sc->bge_ev_intr); 4439 4440 /* clear status word */ 4441 sc->bge_rdata->bge_status_block.bge_status = 0; 4442 4443 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4444 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4445 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4446 bge_link_upd(sc); 4447 4448 if (ifp->if_flags & IFF_RUNNING) { 4449 /* Check RX return ring producer/consumer */ 4450 bge_rxeof(sc); 4451 4452 /* Check TX ring producer/consumer */ 4453 bge_txeof(sc); 4454 } 4455 4456 if (sc->bge_pending_rxintr_change) { 4457 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4458 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4459 uint32_t junk; 4460 4461 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4462 DELAY(10); 4463 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4464 4465 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4466 DELAY(10); 4467 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4468 4469 sc->bge_pending_rxintr_change = 0; 4470 } 4471 bge_handle_events(sc); 4472 4473 /* Re-enable interrupts. */ 4474 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4475 4476 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4477 bge_start(ifp); 4478 4479 return 1; 4480 } else 4481 return 0; 4482 } 4483 4484 static void 4485 bge_asf_driver_up(struct bge_softc *sc) 4486 { 4487 if (sc->bge_asf_mode & ASF_STACKUP) { 4488 /* Send ASF heartbeat aprox. every 2s */ 4489 if (sc->bge_asf_count) 4490 sc->bge_asf_count --; 4491 else { 4492 sc->bge_asf_count = 2; 4493 4494 bge_wait_for_event_ack(sc); 4495 4496 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4497 BGE_FW_CMD_DRV_ALIVE); 4498 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4499 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4500 BGE_FW_HB_TIMEOUT_SEC); 4501 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4502 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4503 BGE_RX_CPU_DRV_EVENT); 4504 } 4505 } 4506 } 4507 4508 static void 4509 bge_tick(void *xsc) 4510 { 4511 struct bge_softc *sc = xsc; 4512 struct mii_data *mii = &sc->bge_mii; 4513 int s; 4514 4515 s = splnet(); 4516 4517 if (BGE_IS_5705_PLUS(sc)) 4518 bge_stats_update_regs(sc); 4519 else 4520 bge_stats_update(sc); 4521 4522 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4523 /* 4524 * Since in TBI mode auto-polling can't be used we should poll 4525 * link status manually. Here we register pending link event 4526 * and trigger interrupt. 4527 */ 4528 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4529 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4530 } else { 4531 /* 4532 * Do not touch PHY if we have link up. This could break 4533 * IPMI/ASF mode or produce extra input errors. 4534 * (extra input errors was reported for bcm5701 & bcm5704). 4535 */ 4536 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4537 mii_tick(mii); 4538 } 4539 4540 bge_asf_driver_up(sc); 4541 4542 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4543 4544 splx(s); 4545 } 4546 4547 static void 4548 bge_stats_update_regs(struct bge_softc *sc) 4549 { 4550 struct ifnet *ifp = &sc->ethercom.ec_if; 4551 4552 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4553 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4554 4555 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4556 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4557 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4558 } 4559 4560 static void 4561 bge_stats_update(struct bge_softc *sc) 4562 { 4563 struct ifnet *ifp = &sc->ethercom.ec_if; 4564 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4565 4566 #define READ_STAT(sc, stats, stat) \ 4567 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4568 4569 ifp->if_collisions += 4570 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4571 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4572 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4573 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4574 ifp->if_collisions; 4575 4576 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4577 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4578 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4579 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4580 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4581 READ_STAT(sc, stats, 4582 xoffPauseFramesReceived.bge_addr_lo)); 4583 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4584 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4585 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4586 READ_STAT(sc, stats, 4587 macControlFramesReceived.bge_addr_lo)); 4588 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4589 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4590 4591 #undef READ_STAT 4592 4593 #ifdef notdef 4594 ifp->if_collisions += 4595 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4596 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4597 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4598 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4599 ifp->if_collisions; 4600 #endif 4601 } 4602 4603 /* 4604 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4605 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4606 * but when such padded frames employ the bge IP/TCP checksum offload, 4607 * the hardware checksum assist gives incorrect results (possibly 4608 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4609 * If we pad such runts with zeros, the onboard checksum comes out correct. 4610 */ 4611 static inline int 4612 bge_cksum_pad(struct mbuf *pkt) 4613 { 4614 struct mbuf *last = NULL; 4615 int padlen; 4616 4617 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4618 4619 /* if there's only the packet-header and we can pad there, use it. */ 4620 if (pkt->m_pkthdr.len == pkt->m_len && 4621 M_TRAILINGSPACE(pkt) >= padlen) { 4622 last = pkt; 4623 } else { 4624 /* 4625 * Walk packet chain to find last mbuf. We will either 4626 * pad there, or append a new mbuf and pad it 4627 * (thus perhaps avoiding the bcm5700 dma-min bug). 4628 */ 4629 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4630 continue; /* do nothing */ 4631 } 4632 4633 /* `last' now points to last in chain. */ 4634 if (M_TRAILINGSPACE(last) < padlen) { 4635 /* Allocate new empty mbuf, pad it. Compact later. */ 4636 struct mbuf *n; 4637 MGET(n, M_DONTWAIT, MT_DATA); 4638 if (n == NULL) 4639 return ENOBUFS; 4640 n->m_len = 0; 4641 last->m_next = n; 4642 last = n; 4643 } 4644 } 4645 4646 KDASSERT(!M_READONLY(last)); 4647 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4648 4649 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4650 memset(mtod(last, char *) + last->m_len, 0, padlen); 4651 last->m_len += padlen; 4652 pkt->m_pkthdr.len += padlen; 4653 return 0; 4654 } 4655 4656 /* 4657 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4658 */ 4659 static inline int 4660 bge_compact_dma_runt(struct mbuf *pkt) 4661 { 4662 struct mbuf *m, *prev; 4663 int totlen, prevlen; 4664 4665 prev = NULL; 4666 totlen = 0; 4667 prevlen = -1; 4668 4669 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4670 int mlen = m->m_len; 4671 int shortfall = 8 - mlen ; 4672 4673 totlen += mlen; 4674 if (mlen == 0) 4675 continue; 4676 if (mlen >= 8) 4677 continue; 4678 4679 /* If we get here, mbuf data is too small for DMA engine. 4680 * Try to fix by shuffling data to prev or next in chain. 4681 * If that fails, do a compacting deep-copy of the whole chain. 4682 */ 4683 4684 /* Internal frag. If fits in prev, copy it there. */ 4685 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4686 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4687 prev->m_len += mlen; 4688 m->m_len = 0; 4689 /* XXX stitch chain */ 4690 prev->m_next = m_free(m); 4691 m = prev; 4692 continue; 4693 } 4694 else if (m->m_next != NULL && 4695 M_TRAILINGSPACE(m) >= shortfall && 4696 m->m_next->m_len >= (8 + shortfall)) { 4697 /* m is writable and have enough data in next, pull up. */ 4698 4699 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4700 shortfall); 4701 m->m_len += shortfall; 4702 m->m_next->m_len -= shortfall; 4703 m->m_next->m_data += shortfall; 4704 } 4705 else if (m->m_next == NULL || 1) { 4706 /* Got a runt at the very end of the packet. 4707 * borrow data from the tail of the preceding mbuf and 4708 * update its length in-place. (The original data is still 4709 * valid, so we can do this even if prev is not writable.) 4710 */ 4711 4712 /* if we'd make prev a runt, just move all of its data. */ 4713 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4714 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4715 4716 if ((prev->m_len - shortfall) < 8) 4717 shortfall = prev->m_len; 4718 4719 #ifdef notyet /* just do the safe slow thing for now */ 4720 if (!M_READONLY(m)) { 4721 if (M_LEADINGSPACE(m) < shorfall) { 4722 void *m_dat; 4723 m_dat = (m->m_flags & M_PKTHDR) ? 4724 m->m_pktdat : m->dat; 4725 memmove(m_dat, mtod(m, void*), m->m_len); 4726 m->m_data = m_dat; 4727 } 4728 } else 4729 #endif /* just do the safe slow thing */ 4730 { 4731 struct mbuf * n = NULL; 4732 int newprevlen = prev->m_len - shortfall; 4733 4734 MGET(n, M_NOWAIT, MT_DATA); 4735 if (n == NULL) 4736 return ENOBUFS; 4737 KASSERT(m->m_len + shortfall < MLEN 4738 /*, 4739 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4740 4741 /* first copy the data we're stealing from prev */ 4742 memcpy(n->m_data, prev->m_data + newprevlen, 4743 shortfall); 4744 4745 /* update prev->m_len accordingly */ 4746 prev->m_len -= shortfall; 4747 4748 /* copy data from runt m */ 4749 memcpy(n->m_data + shortfall, m->m_data, 4750 m->m_len); 4751 4752 /* n holds what we stole from prev, plus m */ 4753 n->m_len = shortfall + m->m_len; 4754 4755 /* stitch n into chain and free m */ 4756 n->m_next = m->m_next; 4757 prev->m_next = n; 4758 /* KASSERT(m->m_next == NULL); */ 4759 m->m_next = NULL; 4760 m_free(m); 4761 m = n; /* for continuing loop */ 4762 } 4763 } 4764 prevlen = m->m_len; 4765 } 4766 return 0; 4767 } 4768 4769 /* 4770 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4771 * pointers to descriptors. 4772 */ 4773 static int 4774 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4775 { 4776 struct bge_tx_bd *f = NULL; 4777 uint32_t frag, cur; 4778 uint16_t csum_flags = 0; 4779 uint16_t txbd_tso_flags = 0; 4780 struct txdmamap_pool_entry *dma; 4781 bus_dmamap_t dmamap; 4782 int i = 0; 4783 struct m_tag *mtag; 4784 int use_tso, maxsegsize, error; 4785 4786 cur = frag = *txidx; 4787 4788 if (m_head->m_pkthdr.csum_flags) { 4789 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4790 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4791 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4792 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4793 } 4794 4795 /* 4796 * If we were asked to do an outboard checksum, and the NIC 4797 * has the bug where it sometimes adds in the Ethernet padding, 4798 * explicitly pad with zeros so the cksum will be correct either way. 4799 * (For now, do this for all chip versions, until newer 4800 * are confirmed to not require the workaround.) 4801 */ 4802 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4803 #ifdef notyet 4804 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4805 #endif 4806 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4807 goto check_dma_bug; 4808 4809 if (bge_cksum_pad(m_head) != 0) 4810 return ENOBUFS; 4811 4812 check_dma_bug: 4813 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4814 goto doit; 4815 4816 /* 4817 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4818 * less than eight bytes. If we encounter a teeny mbuf 4819 * at the end of a chain, we can pad. Otherwise, copy. 4820 */ 4821 if (bge_compact_dma_runt(m_head) != 0) 4822 return ENOBUFS; 4823 4824 doit: 4825 dma = SLIST_FIRST(&sc->txdma_list); 4826 if (dma == NULL) 4827 return ENOBUFS; 4828 dmamap = dma->dmamap; 4829 4830 /* 4831 * Set up any necessary TSO state before we start packing... 4832 */ 4833 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4834 if (!use_tso) { 4835 maxsegsize = 0; 4836 } else { /* TSO setup */ 4837 unsigned mss; 4838 struct ether_header *eh; 4839 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4840 struct mbuf * m0 = m_head; 4841 struct ip *ip; 4842 struct tcphdr *th; 4843 int iphl, hlen; 4844 4845 /* 4846 * XXX It would be nice if the mbuf pkthdr had offset 4847 * fields for the protocol headers. 4848 */ 4849 4850 eh = mtod(m0, struct ether_header *); 4851 switch (htons(eh->ether_type)) { 4852 case ETHERTYPE_IP: 4853 offset = ETHER_HDR_LEN; 4854 break; 4855 4856 case ETHERTYPE_VLAN: 4857 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4858 break; 4859 4860 default: 4861 /* 4862 * Don't support this protocol or encapsulation. 4863 */ 4864 return ENOBUFS; 4865 } 4866 4867 /* 4868 * TCP/IP headers are in the first mbuf; we can do 4869 * this the easy way. 4870 */ 4871 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4872 hlen = iphl + offset; 4873 if (__predict_false(m0->m_len < 4874 (hlen + sizeof(struct tcphdr)))) { 4875 4876 aprint_debug_dev(sc->bge_dev, 4877 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4878 "not handled yet\n", 4879 m0->m_len, hlen+ sizeof(struct tcphdr)); 4880 #ifdef NOTYET 4881 /* 4882 * XXX jonathan (at) NetBSD.org: untested. 4883 * how to force this branch to be taken? 4884 */ 4885 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4886 4887 m_copydata(m0, offset, sizeof(ip), &ip); 4888 m_copydata(m0, hlen, sizeof(th), &th); 4889 4890 ip.ip_len = 0; 4891 4892 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4893 sizeof(ip.ip_len), &ip.ip_len); 4894 4895 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4896 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4897 4898 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4899 sizeof(th.th_sum), &th.th_sum); 4900 4901 hlen += th.th_off << 2; 4902 iptcp_opt_words = hlen; 4903 #else 4904 /* 4905 * if_wm "hard" case not yet supported, can we not 4906 * mandate it out of existence? 4907 */ 4908 (void) ip; (void)th; (void) ip_tcp_hlen; 4909 4910 return ENOBUFS; 4911 #endif 4912 } else { 4913 ip = (struct ip *) (mtod(m0, char *) + offset); 4914 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4915 ip_tcp_hlen = iphl + (th->th_off << 2); 4916 4917 /* Total IP/TCP options, in 32-bit words */ 4918 iptcp_opt_words = (ip_tcp_hlen 4919 - sizeof(struct tcphdr) 4920 - sizeof(struct ip)) >> 2; 4921 } 4922 if (BGE_IS_575X_PLUS(sc)) { 4923 th->th_sum = 0; 4924 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4925 } else { 4926 /* 4927 * XXX jonathan (at) NetBSD.org: 5705 untested. 4928 * Requires TSO firmware patch for 5701/5703/5704. 4929 */ 4930 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4931 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4932 } 4933 4934 mss = m_head->m_pkthdr.segsz; 4935 txbd_tso_flags |= 4936 BGE_TXBDFLAG_CPU_PRE_DMA | 4937 BGE_TXBDFLAG_CPU_POST_DMA; 4938 4939 /* 4940 * Our NIC TSO-assist assumes TSO has standard, optionless 4941 * IPv4 and TCP headers, which total 40 bytes. By default, 4942 * the NIC copies 40 bytes of IP/TCP header from the 4943 * supplied header into the IP/TCP header portion of 4944 * each post-TSO-segment. If the supplied packet has IP or 4945 * TCP options, we need to tell the NIC to copy those extra 4946 * bytes into each post-TSO header, in addition to the normal 4947 * 40-byte IP/TCP header (and to leave space accordingly). 4948 * Unfortunately, the driver encoding of option length 4949 * varies across different ASIC families. 4950 */ 4951 tcp_seg_flags = 0; 4952 if (iptcp_opt_words) { 4953 if (BGE_IS_5705_PLUS(sc)) { 4954 tcp_seg_flags = 4955 iptcp_opt_words << 11; 4956 } else { 4957 txbd_tso_flags |= 4958 iptcp_opt_words << 12; 4959 } 4960 } 4961 maxsegsize = mss | tcp_seg_flags; 4962 ip->ip_len = htons(mss + ip_tcp_hlen); 4963 4964 } /* TSO setup */ 4965 4966 /* 4967 * Start packing the mbufs in this chain into 4968 * the fragment pointers. Stop when we run out 4969 * of fragments or hit the end of the mbuf chain. 4970 */ 4971 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4972 BUS_DMA_NOWAIT); 4973 if (error) 4974 return ENOBUFS; 4975 /* 4976 * Sanity check: avoid coming within 16 descriptors 4977 * of the end of the ring. 4978 */ 4979 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4980 BGE_TSO_PRINTF(("%s: " 4981 " dmamap_load_mbuf too close to ring wrap\n", 4982 device_xname(sc->bge_dev))); 4983 goto fail_unload; 4984 } 4985 4986 mtag = sc->ethercom.ec_nvlans ? 4987 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4988 4989 4990 /* Iterate over dmap-map fragments. */ 4991 for (i = 0; i < dmamap->dm_nsegs; i++) { 4992 f = &sc->bge_rdata->bge_tx_ring[frag]; 4993 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4994 break; 4995 4996 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4997 f->bge_len = dmamap->dm_segs[i].ds_len; 4998 4999 /* 5000 * For 5751 and follow-ons, for TSO we must turn 5001 * off checksum-assist flag in the tx-descr, and 5002 * supply the ASIC-revision-specific encoding 5003 * of TSO flags and segsize. 5004 */ 5005 if (use_tso) { 5006 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5007 f->bge_rsvd = maxsegsize; 5008 f->bge_flags = csum_flags | txbd_tso_flags; 5009 } else { 5010 f->bge_rsvd = 0; 5011 f->bge_flags = 5012 (csum_flags | txbd_tso_flags) & 0x0fff; 5013 } 5014 } else { 5015 f->bge_rsvd = 0; 5016 f->bge_flags = csum_flags; 5017 } 5018 5019 if (mtag != NULL) { 5020 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5021 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5022 } else { 5023 f->bge_vlan_tag = 0; 5024 } 5025 cur = frag; 5026 BGE_INC(frag, BGE_TX_RING_CNT); 5027 } 5028 5029 if (i < dmamap->dm_nsegs) { 5030 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5031 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5032 goto fail_unload; 5033 } 5034 5035 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5036 BUS_DMASYNC_PREWRITE); 5037 5038 if (frag == sc->bge_tx_saved_considx) { 5039 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5040 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5041 5042 goto fail_unload; 5043 } 5044 5045 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5046 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5047 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5048 sc->txdma[cur] = dma; 5049 sc->bge_txcnt += dmamap->dm_nsegs; 5050 5051 *txidx = frag; 5052 5053 return 0; 5054 5055 fail_unload: 5056 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5057 5058 return ENOBUFS; 5059 } 5060 5061 /* 5062 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5063 * to the mbuf data regions directly in the transmit descriptors. 5064 */ 5065 static void 5066 bge_start(struct ifnet *ifp) 5067 { 5068 struct bge_softc *sc; 5069 struct mbuf *m_head = NULL; 5070 uint32_t prodidx; 5071 int pkts = 0; 5072 5073 sc = ifp->if_softc; 5074 5075 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5076 return; 5077 5078 prodidx = sc->bge_tx_prodidx; 5079 5080 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5081 IFQ_POLL(&ifp->if_snd, m_head); 5082 if (m_head == NULL) 5083 break; 5084 5085 #if 0 5086 /* 5087 * XXX 5088 * safety overkill. If this is a fragmented packet chain 5089 * with delayed TCP/UDP checksums, then only encapsulate 5090 * it if we have enough descriptors to handle the entire 5091 * chain at once. 5092 * (paranoia -- may not actually be needed) 5093 */ 5094 if (m_head->m_flags & M_FIRSTFRAG && 5095 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5096 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5097 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5098 ifp->if_flags |= IFF_OACTIVE; 5099 break; 5100 } 5101 } 5102 #endif 5103 5104 /* 5105 * Pack the data into the transmit ring. If we 5106 * don't have room, set the OACTIVE flag and wait 5107 * for the NIC to drain the ring. 5108 */ 5109 if (bge_encap(sc, m_head, &prodidx)) { 5110 ifp->if_flags |= IFF_OACTIVE; 5111 break; 5112 } 5113 5114 /* now we are committed to transmit the packet */ 5115 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5116 pkts++; 5117 5118 /* 5119 * If there's a BPF listener, bounce a copy of this frame 5120 * to him. 5121 */ 5122 bpf_mtap(ifp, m_head); 5123 } 5124 if (pkts == 0) 5125 return; 5126 5127 /* Transmit */ 5128 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5129 /* 5700 b2 errata */ 5130 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5131 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5132 5133 sc->bge_tx_prodidx = prodidx; 5134 5135 /* 5136 * Set a timeout in case the chip goes out to lunch. 5137 */ 5138 ifp->if_timer = 5; 5139 } 5140 5141 static int 5142 bge_init(struct ifnet *ifp) 5143 { 5144 struct bge_softc *sc = ifp->if_softc; 5145 const uint16_t *m; 5146 uint32_t mode; 5147 int s, error = 0; 5148 5149 s = splnet(); 5150 5151 ifp = &sc->ethercom.ec_if; 5152 5153 /* Cancel pending I/O and flush buffers. */ 5154 bge_stop(ifp, 0); 5155 5156 bge_stop_fw(sc); 5157 bge_sig_pre_reset(sc, BGE_RESET_START); 5158 bge_reset(sc); 5159 bge_sig_legacy(sc, BGE_RESET_START); 5160 bge_sig_post_reset(sc, BGE_RESET_START); 5161 5162 bge_chipinit(sc); 5163 5164 /* 5165 * Init the various state machines, ring 5166 * control blocks and firmware. 5167 */ 5168 error = bge_blockinit(sc); 5169 if (error != 0) { 5170 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5171 error); 5172 splx(s); 5173 return error; 5174 } 5175 5176 ifp = &sc->ethercom.ec_if; 5177 5178 /* Specify MTU. */ 5179 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5180 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5181 5182 /* Load our MAC address. */ 5183 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5184 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5185 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5186 5187 /* Enable or disable promiscuous mode as needed. */ 5188 if (ifp->if_flags & IFF_PROMISC) 5189 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5190 else 5191 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5192 5193 /* Program multicast filter. */ 5194 bge_setmulti(sc); 5195 5196 /* Init RX ring. */ 5197 bge_init_rx_ring_std(sc); 5198 5199 /* 5200 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5201 * memory to insure that the chip has in fact read the first 5202 * entry of the ring. 5203 */ 5204 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5205 uint32_t v, i; 5206 for (i = 0; i < 10; i++) { 5207 DELAY(20); 5208 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5209 if (v == (MCLBYTES - ETHER_ALIGN)) 5210 break; 5211 } 5212 if (i == 10) 5213 aprint_error_dev(sc->bge_dev, 5214 "5705 A0 chip failed to load RX ring\n"); 5215 } 5216 5217 /* Init jumbo RX ring. */ 5218 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5219 bge_init_rx_ring_jumbo(sc); 5220 5221 /* Init our RX return ring index */ 5222 sc->bge_rx_saved_considx = 0; 5223 5224 /* Init TX ring. */ 5225 bge_init_tx_ring(sc); 5226 5227 /* Enable TX MAC state machine lockup fix. */ 5228 mode = CSR_READ_4(sc, BGE_TX_MODE); 5229 if (BGE_IS_5755_PLUS(sc) || 5230 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5231 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5232 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5233 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5234 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5235 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5236 } 5237 5238 /* Turn on transmitter */ 5239 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5240 DELAY(100); 5241 5242 /* Turn on receiver */ 5243 mode = CSR_READ_4(sc, BGE_RX_MODE); 5244 if (BGE_IS_5755_PLUS(sc)) 5245 mode |= BGE_RXMODE_IPV6_ENABLE; 5246 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5247 DELAY(10); 5248 5249 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5250 5251 /* Tell firmware we're alive. */ 5252 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5253 5254 /* Enable host interrupts. */ 5255 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5256 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5257 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5258 5259 if ((error = bge_ifmedia_upd(ifp)) != 0) 5260 goto out; 5261 5262 ifp->if_flags |= IFF_RUNNING; 5263 ifp->if_flags &= ~IFF_OACTIVE; 5264 5265 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5266 5267 out: 5268 sc->bge_if_flags = ifp->if_flags; 5269 splx(s); 5270 5271 return error; 5272 } 5273 5274 /* 5275 * Set media options. 5276 */ 5277 static int 5278 bge_ifmedia_upd(struct ifnet *ifp) 5279 { 5280 struct bge_softc *sc = ifp->if_softc; 5281 struct mii_data *mii = &sc->bge_mii; 5282 struct ifmedia *ifm = &sc->bge_ifmedia; 5283 int rc; 5284 5285 /* If this is a 1000baseX NIC, enable the TBI port. */ 5286 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5287 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5288 return EINVAL; 5289 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5290 case IFM_AUTO: 5291 /* 5292 * The BCM5704 ASIC appears to have a special 5293 * mechanism for programming the autoneg 5294 * advertisement registers in TBI mode. 5295 */ 5296 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5297 uint32_t sgdig; 5298 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5299 if (sgdig & BGE_SGDIGSTS_DONE) { 5300 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5301 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5302 sgdig |= BGE_SGDIGCFG_AUTO | 5303 BGE_SGDIGCFG_PAUSE_CAP | 5304 BGE_SGDIGCFG_ASYM_PAUSE; 5305 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5306 sgdig | BGE_SGDIGCFG_SEND); 5307 DELAY(5); 5308 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5309 sgdig); 5310 } 5311 } 5312 break; 5313 case IFM_1000_SX: 5314 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5315 BGE_CLRBIT(sc, BGE_MAC_MODE, 5316 BGE_MACMODE_HALF_DUPLEX); 5317 } else { 5318 BGE_SETBIT(sc, BGE_MAC_MODE, 5319 BGE_MACMODE_HALF_DUPLEX); 5320 } 5321 DELAY(40); 5322 break; 5323 default: 5324 return EINVAL; 5325 } 5326 /* XXX 802.3x flow control for 1000BASE-SX */ 5327 return 0; 5328 } 5329 5330 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5331 if ((rc = mii_mediachg(mii)) == ENXIO) 5332 return 0; 5333 5334 /* 5335 * Force an interrupt so that we will call bge_link_upd 5336 * if needed and clear any pending link state attention. 5337 * Without this we are not getting any further interrupts 5338 * for link state changes and thus will not UP the link and 5339 * not be able to send in bge_start. The only way to get 5340 * things working was to receive a packet and get a RX intr. 5341 */ 5342 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5343 sc->bge_flags & BGE_IS_5788) 5344 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5345 else 5346 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5347 5348 return rc; 5349 } 5350 5351 /* 5352 * Report current media status. 5353 */ 5354 static void 5355 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5356 { 5357 struct bge_softc *sc = ifp->if_softc; 5358 struct mii_data *mii = &sc->bge_mii; 5359 5360 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5361 ifmr->ifm_status = IFM_AVALID; 5362 ifmr->ifm_active = IFM_ETHER; 5363 if (CSR_READ_4(sc, BGE_MAC_STS) & 5364 BGE_MACSTAT_TBI_PCS_SYNCHED) 5365 ifmr->ifm_status |= IFM_ACTIVE; 5366 ifmr->ifm_active |= IFM_1000_SX; 5367 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5368 ifmr->ifm_active |= IFM_HDX; 5369 else 5370 ifmr->ifm_active |= IFM_FDX; 5371 return; 5372 } 5373 5374 mii_pollstat(mii); 5375 ifmr->ifm_status = mii->mii_media_status; 5376 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5377 sc->bge_flowflags; 5378 } 5379 5380 static int 5381 bge_ifflags_cb(struct ethercom *ec) 5382 { 5383 struct ifnet *ifp = &ec->ec_if; 5384 struct bge_softc *sc = ifp->if_softc; 5385 int change = ifp->if_flags ^ sc->bge_if_flags; 5386 5387 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5388 return ENETRESET; 5389 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5390 return 0; 5391 5392 if ((ifp->if_flags & IFF_PROMISC) == 0) 5393 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5394 else 5395 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5396 5397 bge_setmulti(sc); 5398 5399 sc->bge_if_flags = ifp->if_flags; 5400 return 0; 5401 } 5402 5403 static int 5404 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5405 { 5406 struct bge_softc *sc = ifp->if_softc; 5407 struct ifreq *ifr = (struct ifreq *) data; 5408 int s, error = 0; 5409 struct mii_data *mii; 5410 5411 s = splnet(); 5412 5413 switch (command) { 5414 case SIOCSIFMEDIA: 5415 /* XXX Flow control is not supported for 1000BASE-SX */ 5416 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5417 ifr->ifr_media &= ~IFM_ETH_FMASK; 5418 sc->bge_flowflags = 0; 5419 } 5420 5421 /* Flow control requires full-duplex mode. */ 5422 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5423 (ifr->ifr_media & IFM_FDX) == 0) { 5424 ifr->ifr_media &= ~IFM_ETH_FMASK; 5425 } 5426 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5427 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5428 /* We can do both TXPAUSE and RXPAUSE. */ 5429 ifr->ifr_media |= 5430 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5431 } 5432 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5433 } 5434 /* FALLTHROUGH */ 5435 case SIOCGIFMEDIA: 5436 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5437 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5438 command); 5439 } else { 5440 mii = &sc->bge_mii; 5441 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5442 command); 5443 } 5444 break; 5445 default: 5446 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5447 break; 5448 5449 error = 0; 5450 5451 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5452 ; 5453 else if (ifp->if_flags & IFF_RUNNING) 5454 bge_setmulti(sc); 5455 break; 5456 } 5457 5458 splx(s); 5459 5460 return error; 5461 } 5462 5463 static void 5464 bge_watchdog(struct ifnet *ifp) 5465 { 5466 struct bge_softc *sc; 5467 5468 sc = ifp->if_softc; 5469 5470 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5471 5472 ifp->if_flags &= ~IFF_RUNNING; 5473 bge_init(ifp); 5474 5475 ifp->if_oerrors++; 5476 } 5477 5478 static void 5479 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5480 { 5481 int i; 5482 5483 BGE_CLRBIT_FLUSH(sc, reg, bit); 5484 5485 for (i = 0; i < 1000; i++) { 5486 delay(100); 5487 if ((CSR_READ_4(sc, reg) & bit) == 0) 5488 return; 5489 } 5490 5491 /* 5492 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5493 * on some environment (and once after boot?) 5494 */ 5495 if (reg != BGE_SRS_MODE) 5496 aprint_error_dev(sc->bge_dev, 5497 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5498 (u_long)reg, bit); 5499 } 5500 5501 /* 5502 * Stop the adapter and free any mbufs allocated to the 5503 * RX and TX lists. 5504 */ 5505 static void 5506 bge_stop(struct ifnet *ifp, int disable) 5507 { 5508 struct bge_softc *sc = ifp->if_softc; 5509 5510 callout_stop(&sc->bge_timeout); 5511 5512 /* Disable host interrupts. */ 5513 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5514 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5515 5516 /* 5517 * Tell firmware we're shutting down. 5518 */ 5519 bge_stop_fw(sc); 5520 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5521 5522 /* 5523 * Disable all of the receiver blocks. 5524 */ 5525 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5526 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5527 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5528 if (BGE_IS_5700_FAMILY(sc)) 5529 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5530 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5531 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5532 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5533 5534 /* 5535 * Disable all of the transmit blocks. 5536 */ 5537 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5538 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5539 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5540 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5541 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5542 if (BGE_IS_5700_FAMILY(sc)) 5543 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5544 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5545 5546 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5547 delay(40); 5548 5549 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5550 5551 /* 5552 * Shut down all of the memory managers and related 5553 * state machines. 5554 */ 5555 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5556 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5557 if (BGE_IS_5700_FAMILY(sc)) 5558 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5559 5560 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5561 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5562 5563 if (BGE_IS_5700_FAMILY(sc)) { 5564 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5565 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5566 } 5567 5568 bge_reset(sc); 5569 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5570 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5571 5572 /* 5573 * Keep the ASF firmware running if up. 5574 */ 5575 if (sc->bge_asf_mode & ASF_STACKUP) 5576 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5577 else 5578 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5579 5580 /* Free the RX lists. */ 5581 bge_free_rx_ring_std(sc); 5582 5583 /* Free jumbo RX list. */ 5584 if (BGE_IS_JUMBO_CAPABLE(sc)) 5585 bge_free_rx_ring_jumbo(sc); 5586 5587 /* Free TX buffers. */ 5588 bge_free_tx_ring(sc); 5589 5590 /* 5591 * Isolate/power down the PHY. 5592 */ 5593 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5594 mii_down(&sc->bge_mii); 5595 5596 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5597 5598 /* Clear MAC's link state (PHY may still have link UP). */ 5599 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5600 5601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5602 } 5603 5604 static void 5605 bge_link_upd(struct bge_softc *sc) 5606 { 5607 struct ifnet *ifp = &sc->ethercom.ec_if; 5608 struct mii_data *mii = &sc->bge_mii; 5609 uint32_t status; 5610 int link; 5611 5612 /* Clear 'pending link event' flag */ 5613 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5614 5615 /* 5616 * Process link state changes. 5617 * Grrr. The link status word in the status block does 5618 * not work correctly on the BCM5700 rev AX and BX chips, 5619 * according to all available information. Hence, we have 5620 * to enable MII interrupts in order to properly obtain 5621 * async link changes. Unfortunately, this also means that 5622 * we have to read the MAC status register to detect link 5623 * changes, thereby adding an additional register access to 5624 * the interrupt handler. 5625 */ 5626 5627 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5628 status = CSR_READ_4(sc, BGE_MAC_STS); 5629 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5630 mii_pollstat(mii); 5631 5632 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5633 mii->mii_media_status & IFM_ACTIVE && 5634 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5635 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5636 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5637 (!(mii->mii_media_status & IFM_ACTIVE) || 5638 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5639 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5640 5641 /* Clear the interrupt */ 5642 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5643 BGE_EVTENB_MI_INTERRUPT); 5644 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5645 BRGPHY_MII_ISR); 5646 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5647 BRGPHY_MII_IMR, BRGPHY_INTRS); 5648 } 5649 return; 5650 } 5651 5652 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5653 status = CSR_READ_4(sc, BGE_MAC_STS); 5654 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5655 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5656 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5657 if (BGE_ASICREV(sc->bge_chipid) 5658 == BGE_ASICREV_BCM5704) { 5659 BGE_CLRBIT(sc, BGE_MAC_MODE, 5660 BGE_MACMODE_TBI_SEND_CFGS); 5661 DELAY(40); 5662 } 5663 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5664 if_link_state_change(ifp, LINK_STATE_UP); 5665 } 5666 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5667 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5668 if_link_state_change(ifp, LINK_STATE_DOWN); 5669 } 5670 /* 5671 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5672 * This should not happen since mii callouts are locked now, but 5673 * we keep this check for debug. 5674 */ 5675 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5676 /* 5677 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5678 * bit in status word always set. Workaround this bug by 5679 * reading PHY link status directly. 5680 */ 5681 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5682 BGE_STS_LINK : 0; 5683 5684 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5685 mii_pollstat(mii); 5686 5687 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5688 mii->mii_media_status & IFM_ACTIVE && 5689 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5690 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5691 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5692 (!(mii->mii_media_status & IFM_ACTIVE) || 5693 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5694 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5695 } 5696 } else { 5697 /* 5698 * For controllers that call mii_tick, we have to poll 5699 * link status. 5700 */ 5701 mii_pollstat(mii); 5702 bge_miibus_statchg(ifp); 5703 } 5704 5705 /* Clear the attention */ 5706 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5707 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5708 BGE_MACSTAT_LINK_CHANGED); 5709 } 5710 5711 static int 5712 bge_sysctl_verify(SYSCTLFN_ARGS) 5713 { 5714 int error, t; 5715 struct sysctlnode node; 5716 5717 node = *rnode; 5718 t = *(int*)rnode->sysctl_data; 5719 node.sysctl_data = &t; 5720 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5721 if (error || newp == NULL) 5722 return error; 5723 5724 #if 0 5725 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5726 node.sysctl_num, rnode->sysctl_num)); 5727 #endif 5728 5729 if (node.sysctl_num == bge_rxthresh_nodenum) { 5730 if (t < 0 || t >= NBGE_RX_THRESH) 5731 return EINVAL; 5732 bge_update_all_threshes(t); 5733 } else 5734 return EINVAL; 5735 5736 *(int*)rnode->sysctl_data = t; 5737 5738 return 0; 5739 } 5740 5741 /* 5742 * Set up sysctl(3) MIB, hw.bge.*. 5743 */ 5744 static void 5745 bge_sysctl_init(struct bge_softc *sc) 5746 { 5747 int rc, bge_root_num; 5748 const struct sysctlnode *node; 5749 5750 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5751 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5752 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5753 goto out; 5754 } 5755 5756 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5757 0, CTLTYPE_NODE, "bge", 5758 SYSCTL_DESCR("BGE interface controls"), 5759 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5760 goto out; 5761 } 5762 5763 bge_root_num = node->sysctl_num; 5764 5765 /* BGE Rx interrupt mitigation level */ 5766 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5767 CTLFLAG_READWRITE, 5768 CTLTYPE_INT, "rx_lvl", 5769 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5770 bge_sysctl_verify, 0, 5771 &bge_rx_thresh_lvl, 5772 0, CTL_HW, bge_root_num, CTL_CREATE, 5773 CTL_EOL)) != 0) { 5774 goto out; 5775 } 5776 5777 bge_rxthresh_nodenum = node->sysctl_num; 5778 5779 return; 5780 5781 out: 5782 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5783 } 5784 5785 #ifdef BGE_DEBUG 5786 void 5787 bge_debug_info(struct bge_softc *sc) 5788 { 5789 5790 printf("Hardware Flags:\n"); 5791 if (BGE_IS_57765_PLUS(sc)) 5792 printf(" - 57765 Plus\n"); 5793 if (BGE_IS_5717_PLUS(sc)) 5794 printf(" - 5717 Plus\n"); 5795 if (BGE_IS_5755_PLUS(sc)) 5796 printf(" - 5755 Plus\n"); 5797 if (BGE_IS_575X_PLUS(sc)) 5798 printf(" - 575X Plus\n"); 5799 if (BGE_IS_5705_PLUS(sc)) 5800 printf(" - 5705 Plus\n"); 5801 if (BGE_IS_5714_FAMILY(sc)) 5802 printf(" - 5714 Family\n"); 5803 if (BGE_IS_5700_FAMILY(sc)) 5804 printf(" - 5700 Family\n"); 5805 if (sc->bge_flags & BGE_IS_5788) 5806 printf(" - 5788\n"); 5807 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5808 printf(" - Supports Jumbo Frames\n"); 5809 if (sc->bge_flags & BGE_NO_EEPROM) 5810 printf(" - No EEPROM\n"); 5811 if (sc->bge_flags & BGE_PCIX) 5812 printf(" - PCI-X Bus\n"); 5813 if (sc->bge_flags & BGE_PCIE) 5814 printf(" - PCI Express Bus\n"); 5815 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5816 printf(" - RX Alignment Bug\n"); 5817 if (sc->bge_flags & BGE_APE) 5818 printf(" - APE\n"); 5819 if (sc->bge_flags & BGE_CPMU_PRESENT) 5820 printf(" - CPMU\n"); 5821 if (sc->bge_flags & BGE_TSO) 5822 printf(" - TSO\n"); 5823 5824 if (sc->bge_flags & BGE_PHY_NO_3LED) 5825 printf(" - No 3 LEDs\n"); 5826 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5827 printf(" - CRC bug\n"); 5828 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5829 printf(" - ADC bug\n"); 5830 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5831 printf(" - 5704 A0 bug\n"); 5832 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5833 printf(" - jitter bug\n"); 5834 if (sc->bge_flags & BGE_PHY_BER_BUG) 5835 printf(" - BER bug\n"); 5836 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5837 printf(" - adjust trim\n"); 5838 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5839 printf(" - no wirespeed\n"); 5840 } 5841 #endif /* BGE_DEBUG */ 5842 5843 static int 5844 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5845 { 5846 prop_dictionary_t dict; 5847 prop_data_t ea; 5848 5849 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5850 return 1; 5851 5852 dict = device_properties(sc->bge_dev); 5853 ea = prop_dictionary_get(dict, "mac-address"); 5854 if (ea != NULL) { 5855 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5856 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5857 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5858 return 0; 5859 } 5860 5861 return 1; 5862 } 5863 5864 static int 5865 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5866 { 5867 uint32_t mac_addr; 5868 5869 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5870 if ((mac_addr >> 16) == 0x484b) { 5871 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5872 ether_addr[1] = (uint8_t)mac_addr; 5873 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5874 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5875 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5876 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5877 ether_addr[5] = (uint8_t)mac_addr; 5878 return 0; 5879 } 5880 return 1; 5881 } 5882 5883 static int 5884 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5885 { 5886 int mac_offset = BGE_EE_MAC_OFFSET; 5887 5888 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5889 mac_offset = BGE_EE_MAC_OFFSET_5906; 5890 5891 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5892 ETHER_ADDR_LEN)); 5893 } 5894 5895 static int 5896 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5897 { 5898 5899 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5900 return 1; 5901 5902 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5903 ETHER_ADDR_LEN)); 5904 } 5905 5906 static int 5907 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5908 { 5909 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5910 /* NOTE: Order is critical */ 5911 bge_get_eaddr_fw, 5912 bge_get_eaddr_mem, 5913 bge_get_eaddr_nvram, 5914 bge_get_eaddr_eeprom, 5915 NULL 5916 }; 5917 const bge_eaddr_fcn_t *func; 5918 5919 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5920 if ((*func)(sc, eaddr) == 0) 5921 break; 5922 } 5923 return (*func == NULL ? ENXIO : 0); 5924 } 5925
Indexes created Mon Sep 22 21:09:42 GMT 2025