if_bge.c revision 1.234
1 /* $NetBSD: if_bge.c,v 1.234 2013/04/08 03:35:11 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.234 2013/04/08 03:35:11 msaitoh Exp $"); 83 84 #include "vlan.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/socket.h> 95 #include <sys/sysctl.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #include <sys/rnd.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 118 #include <net/bpf.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/miidevs.h> 127 #include <dev/mii/brgphyreg.h> 128 129 #include <dev/pci/if_bgereg.h> 130 #include <dev/pci/if_bgevar.h> 131 132 #include <prop/proplib.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: increasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 static const struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 170 { 32, 2 }, 171 { 50, 4 }, 172 { 100, 8 }, 173 { 192, 16 }, 174 { 416, 32 }, 175 { 598, 46 } 176 }; 177 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 178 179 /* XXX patchable; should be sysctl'able */ 180 static int bge_auto_thresh = 1; 181 static int bge_rx_thresh_lvl; 182 183 static int bge_rxthresh_nodenum; 184 185 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 186 187 static uint32_t bge_chipid(const struct pci_attach_args *pa); 188 static int bge_probe(device_t, cfdata_t, void *); 189 static void bge_attach(device_t, device_t, void *); 190 static int bge_detach(device_t, int); 191 static void bge_release_resources(struct bge_softc *); 192 193 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 198 199 static void bge_txeof(struct bge_softc *); 200 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 201 static void bge_rxeof(struct bge_softc *); 202 203 static void bge_asf_driver_up (struct bge_softc *); 204 static void bge_tick(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static void bge_stats_update_regs(struct bge_softc *); 207 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 208 209 static int bge_intr(void *); 210 static void bge_start(struct ifnet *); 211 static int bge_ifflags_cb(struct ethercom *); 212 static int bge_ioctl(struct ifnet *, u_long, void *); 213 static int bge_init(struct ifnet *); 214 static void bge_stop(struct ifnet *, int); 215 static void bge_watchdog(struct ifnet *); 216 static int bge_ifmedia_upd(struct ifnet *); 217 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 219 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 221 222 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 223 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 224 static void bge_setmulti(struct bge_softc *); 225 226 static void bge_handle_events(struct bge_softc *); 227 static int bge_alloc_jumbo_mem(struct bge_softc *); 228 #if 0 /* XXX */ 229 static void bge_free_jumbo_mem(struct bge_softc *); 230 #endif 231 static void *bge_jalloc(struct bge_softc *); 232 static void bge_jfree(struct mbuf *, void *, size_t, void *); 233 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 234 bus_dmamap_t); 235 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 236 static int bge_init_rx_ring_std(struct bge_softc *); 237 static void bge_free_rx_ring_std(struct bge_softc *); 238 static int bge_init_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_rx_ring_jumbo(struct bge_softc *); 240 static void bge_free_tx_ring(struct bge_softc *); 241 static int bge_init_tx_ring(struct bge_softc *); 242 243 static int bge_chipinit(struct bge_softc *); 244 static int bge_blockinit(struct bge_softc *); 245 static int bge_phy_addr(struct bge_softc *); 246 static uint32_t bge_readmem_ind(struct bge_softc *, int); 247 static void bge_writemem_ind(struct bge_softc *, int, int); 248 static void bge_writembx(struct bge_softc *, int, int); 249 static void bge_writembx_flush(struct bge_softc *, int, int); 250 static void bge_writemem_direct(struct bge_softc *, int, int); 251 static void bge_writereg_ind(struct bge_softc *, int, int); 252 static void bge_set_max_readrq(struct bge_softc *); 253 254 static int bge_miibus_readreg(device_t, int, int); 255 static void bge_miibus_writereg(device_t, int, int, int); 256 static void bge_miibus_statchg(struct ifnet *); 257 258 #define BGE_RESET_SHUTDOWN 0 259 #define BGE_RESET_START 1 260 #define BGE_RESET_SUSPEND 2 261 static void bge_sig_post_reset(struct bge_softc *, int); 262 static void bge_sig_legacy(struct bge_softc *, int); 263 static void bge_sig_pre_reset(struct bge_softc *, int); 264 static void bge_wait_for_event_ack(struct bge_softc *); 265 static void bge_stop_fw(struct bge_softc *); 266 static int bge_reset(struct bge_softc *); 267 static void bge_link_upd(struct bge_softc *); 268 static void bge_sysctl_init(struct bge_softc *); 269 static int bge_sysctl_verify(SYSCTLFN_PROTO); 270 271 static void bge_ape_lock_init(struct bge_softc *); 272 static void bge_ape_read_fw_ver(struct bge_softc *); 273 static int bge_ape_lock(struct bge_softc *, int); 274 static void bge_ape_unlock(struct bge_softc *, int); 275 static void bge_ape_send_event(struct bge_softc *, uint32_t); 276 static void bge_ape_driver_state_change(struct bge_softc *, int); 277 278 #ifdef BGE_DEBUG 279 #define DPRINTF(x) if (bgedebug) printf x 280 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 281 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 282 int bgedebug = 0; 283 int bge_tso_debug = 0; 284 void bge_debug_info(struct bge_softc *); 285 #else 286 #define DPRINTF(x) 287 #define DPRINTFN(n,x) 288 #define BGE_TSO_PRINTF(x) 289 #endif 290 291 #ifdef BGE_EVENT_COUNTERS 292 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 293 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 294 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 295 #else 296 #define BGE_EVCNT_INCR(ev) /* nothing */ 297 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 298 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 299 #endif 300 301 static const struct bge_product { 302 pci_vendor_id_t bp_vendor; 303 pci_product_id_t bp_product; 304 const char *bp_name; 305 } bge_products[] = { 306 /* 307 * The BCM5700 documentation seems to indicate that the hardware 308 * still has the Alteon vendor ID burned into it, though it 309 * should always be overridden by the value in the EEPROM. We'll 310 * check for it anyway. 311 */ 312 { PCI_VENDOR_ALTEON, 313 PCI_PRODUCT_ALTEON_BCM5700, 314 "Broadcom BCM5700 Gigabit Ethernet", 315 }, 316 { PCI_VENDOR_ALTEON, 317 PCI_PRODUCT_ALTEON_BCM5701, 318 "Broadcom BCM5701 Gigabit Ethernet", 319 }, 320 { PCI_VENDOR_ALTIMA, 321 PCI_PRODUCT_ALTIMA_AC1000, 322 "Altima AC1000 Gigabit Ethernet", 323 }, 324 { PCI_VENDOR_ALTIMA, 325 PCI_PRODUCT_ALTIMA_AC1001, 326 "Altima AC1001 Gigabit Ethernet", 327 }, 328 { PCI_VENDOR_ALTIMA, 329 PCI_PRODUCT_ALTIMA_AC1003, 330 "Altima AC1003 Gigabit Ethernet", 331 }, 332 { PCI_VENDOR_ALTIMA, 333 PCI_PRODUCT_ALTIMA_AC9100, 334 "Altima AC9100 Gigabit Ethernet", 335 }, 336 { PCI_VENDOR_APPLE, 337 PCI_PRODUCT_APPLE_BCM5701, 338 "APPLE BCM5701 Gigabit Ethernet", 339 }, 340 { PCI_VENDOR_BROADCOM, 341 PCI_PRODUCT_BROADCOM_BCM5700, 342 "Broadcom BCM5700 Gigabit Ethernet", 343 }, 344 { PCI_VENDOR_BROADCOM, 345 PCI_PRODUCT_BROADCOM_BCM5701, 346 "Broadcom BCM5701 Gigabit Ethernet", 347 }, 348 { PCI_VENDOR_BROADCOM, 349 PCI_PRODUCT_BROADCOM_BCM5702, 350 "Broadcom BCM5702 Gigabit Ethernet", 351 }, 352 { PCI_VENDOR_BROADCOM, 353 PCI_PRODUCT_BROADCOM_BCM5702X, 354 "Broadcom BCM5702X Gigabit Ethernet" }, 355 { PCI_VENDOR_BROADCOM, 356 PCI_PRODUCT_BROADCOM_BCM5703, 357 "Broadcom BCM5703 Gigabit Ethernet", 358 }, 359 { PCI_VENDOR_BROADCOM, 360 PCI_PRODUCT_BROADCOM_BCM5703X, 361 "Broadcom BCM5703X Gigabit Ethernet", 362 }, 363 { PCI_VENDOR_BROADCOM, 364 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 365 "Broadcom BCM5703 Gigabit Ethernet", 366 }, 367 { PCI_VENDOR_BROADCOM, 368 PCI_PRODUCT_BROADCOM_BCM5704C, 369 "Broadcom BCM5704C Dual Gigabit Ethernet", 370 }, 371 { PCI_VENDOR_BROADCOM, 372 PCI_PRODUCT_BROADCOM_BCM5704S, 373 "Broadcom BCM5704S Dual Gigabit Ethernet", 374 }, 375 { PCI_VENDOR_BROADCOM, 376 PCI_PRODUCT_BROADCOM_BCM5705, 377 "Broadcom BCM5705 Gigabit Ethernet", 378 }, 379 { PCI_VENDOR_BROADCOM, 380 PCI_PRODUCT_BROADCOM_BCM5705F, 381 "Broadcom BCM5705F Gigabit Ethernet", 382 }, 383 { PCI_VENDOR_BROADCOM, 384 PCI_PRODUCT_BROADCOM_BCM5705K, 385 "Broadcom BCM5705K Gigabit Ethernet", 386 }, 387 { PCI_VENDOR_BROADCOM, 388 PCI_PRODUCT_BROADCOM_BCM5705M, 389 "Broadcom BCM5705M Gigabit Ethernet", 390 }, 391 { PCI_VENDOR_BROADCOM, 392 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 393 "Broadcom BCM5705M Gigabit Ethernet", 394 }, 395 { PCI_VENDOR_BROADCOM, 396 PCI_PRODUCT_BROADCOM_BCM5714, 397 "Broadcom BCM5714 Gigabit Ethernet", 398 }, 399 { PCI_VENDOR_BROADCOM, 400 PCI_PRODUCT_BROADCOM_BCM5714S, 401 "Broadcom BCM5714S Gigabit Ethernet", 402 }, 403 { PCI_VENDOR_BROADCOM, 404 PCI_PRODUCT_BROADCOM_BCM5715, 405 "Broadcom BCM5715 Gigabit Ethernet", 406 }, 407 { PCI_VENDOR_BROADCOM, 408 PCI_PRODUCT_BROADCOM_BCM5715S, 409 "Broadcom BCM5715S Gigabit Ethernet", 410 }, 411 { PCI_VENDOR_BROADCOM, 412 PCI_PRODUCT_BROADCOM_BCM5717, 413 "Broadcom BCM5717 Gigabit Ethernet", 414 }, 415 { PCI_VENDOR_BROADCOM, 416 PCI_PRODUCT_BROADCOM_BCM5718, 417 "Broadcom BCM5718 Gigabit Ethernet", 418 }, 419 { PCI_VENDOR_BROADCOM, 420 PCI_PRODUCT_BROADCOM_BCM5719, 421 "Broadcom BCM5719 Gigabit Ethernet", 422 }, 423 { PCI_VENDOR_BROADCOM, 424 PCI_PRODUCT_BROADCOM_BCM5720, 425 "Broadcom BCM5720 Gigabit Ethernet", 426 }, 427 { PCI_VENDOR_BROADCOM, 428 PCI_PRODUCT_BROADCOM_BCM5721, 429 "Broadcom BCM5721 Gigabit Ethernet", 430 }, 431 { PCI_VENDOR_BROADCOM, 432 PCI_PRODUCT_BROADCOM_BCM5722, 433 "Broadcom BCM5722 Gigabit Ethernet", 434 }, 435 { PCI_VENDOR_BROADCOM, 436 PCI_PRODUCT_BROADCOM_BCM5723, 437 "Broadcom BCM5723 Gigabit Ethernet", 438 }, 439 { PCI_VENDOR_BROADCOM, 440 PCI_PRODUCT_BROADCOM_BCM5724, 441 "Broadcom BCM5724 Gigabit Ethernet", 442 }, 443 { PCI_VENDOR_BROADCOM, 444 PCI_PRODUCT_BROADCOM_BCM5750, 445 "Broadcom BCM5750 Gigabit Ethernet", 446 }, 447 { PCI_VENDOR_BROADCOM, 448 PCI_PRODUCT_BROADCOM_BCM5750M, 449 "Broadcom BCM5750M Gigabit Ethernet", 450 }, 451 { PCI_VENDOR_BROADCOM, 452 PCI_PRODUCT_BROADCOM_BCM5751, 453 "Broadcom BCM5751 Gigabit Ethernet", 454 }, 455 { PCI_VENDOR_BROADCOM, 456 PCI_PRODUCT_BROADCOM_BCM5751F, 457 "Broadcom BCM5751F Gigabit Ethernet", 458 }, 459 { PCI_VENDOR_BROADCOM, 460 PCI_PRODUCT_BROADCOM_BCM5751M, 461 "Broadcom BCM5751M Gigabit Ethernet", 462 }, 463 { PCI_VENDOR_BROADCOM, 464 PCI_PRODUCT_BROADCOM_BCM5752, 465 "Broadcom BCM5752 Gigabit Ethernet", 466 }, 467 { PCI_VENDOR_BROADCOM, 468 PCI_PRODUCT_BROADCOM_BCM5752M, 469 "Broadcom BCM5752M Gigabit Ethernet", 470 }, 471 { PCI_VENDOR_BROADCOM, 472 PCI_PRODUCT_BROADCOM_BCM5753, 473 "Broadcom BCM5753 Gigabit Ethernet", 474 }, 475 { PCI_VENDOR_BROADCOM, 476 PCI_PRODUCT_BROADCOM_BCM5753F, 477 "Broadcom BCM5753F Gigabit Ethernet", 478 }, 479 { PCI_VENDOR_BROADCOM, 480 PCI_PRODUCT_BROADCOM_BCM5753M, 481 "Broadcom BCM5753M Gigabit Ethernet", 482 }, 483 { PCI_VENDOR_BROADCOM, 484 PCI_PRODUCT_BROADCOM_BCM5754, 485 "Broadcom BCM5754 Gigabit Ethernet", 486 }, 487 { PCI_VENDOR_BROADCOM, 488 PCI_PRODUCT_BROADCOM_BCM5754M, 489 "Broadcom BCM5754M Gigabit Ethernet", 490 }, 491 { PCI_VENDOR_BROADCOM, 492 PCI_PRODUCT_BROADCOM_BCM5755, 493 "Broadcom BCM5755 Gigabit Ethernet", 494 }, 495 { PCI_VENDOR_BROADCOM, 496 PCI_PRODUCT_BROADCOM_BCM5755M, 497 "Broadcom BCM5755M Gigabit Ethernet", 498 }, 499 { PCI_VENDOR_BROADCOM, 500 PCI_PRODUCT_BROADCOM_BCM5756, 501 "Broadcom BCM5756 Gigabit Ethernet", 502 }, 503 { PCI_VENDOR_BROADCOM, 504 PCI_PRODUCT_BROADCOM_BCM5761, 505 "Broadcom BCM5761 Gigabit Ethernet", 506 }, 507 { PCI_VENDOR_BROADCOM, 508 PCI_PRODUCT_BROADCOM_BCM5761E, 509 "Broadcom BCM5761E Gigabit Ethernet", 510 }, 511 { PCI_VENDOR_BROADCOM, 512 PCI_PRODUCT_BROADCOM_BCM5761S, 513 "Broadcom BCM5761S Gigabit Ethernet", 514 }, 515 { PCI_VENDOR_BROADCOM, 516 PCI_PRODUCT_BROADCOM_BCM5761SE, 517 "Broadcom BCM5761SE Gigabit Ethernet", 518 }, 519 { PCI_VENDOR_BROADCOM, 520 PCI_PRODUCT_BROADCOM_BCM5764, 521 "Broadcom BCM5764 Gigabit Ethernet", 522 }, 523 { PCI_VENDOR_BROADCOM, 524 PCI_PRODUCT_BROADCOM_BCM5780, 525 "Broadcom BCM5780 Gigabit Ethernet", 526 }, 527 { PCI_VENDOR_BROADCOM, 528 PCI_PRODUCT_BROADCOM_BCM5780S, 529 "Broadcom BCM5780S Gigabit Ethernet", 530 }, 531 { PCI_VENDOR_BROADCOM, 532 PCI_PRODUCT_BROADCOM_BCM5781, 533 "Broadcom BCM5781 Gigabit Ethernet", 534 }, 535 { PCI_VENDOR_BROADCOM, 536 PCI_PRODUCT_BROADCOM_BCM5782, 537 "Broadcom BCM5782 Gigabit Ethernet", 538 }, 539 { PCI_VENDOR_BROADCOM, 540 PCI_PRODUCT_BROADCOM_BCM5784M, 541 "BCM5784M NetLink 1000baseT Ethernet", 542 }, 543 { PCI_VENDOR_BROADCOM, 544 PCI_PRODUCT_BROADCOM_BCM5785F, 545 "BCM5785F NetLink 10/100 Ethernet", 546 }, 547 { PCI_VENDOR_BROADCOM, 548 PCI_PRODUCT_BROADCOM_BCM5785G, 549 "BCM5785G NetLink 1000baseT Ethernet", 550 }, 551 { PCI_VENDOR_BROADCOM, 552 PCI_PRODUCT_BROADCOM_BCM5786, 553 "Broadcom BCM5786 Gigabit Ethernet", 554 }, 555 { PCI_VENDOR_BROADCOM, 556 PCI_PRODUCT_BROADCOM_BCM5787, 557 "Broadcom BCM5787 Gigabit Ethernet", 558 }, 559 { PCI_VENDOR_BROADCOM, 560 PCI_PRODUCT_BROADCOM_BCM5787F, 561 "Broadcom BCM5787F 10/100 Ethernet", 562 }, 563 { PCI_VENDOR_BROADCOM, 564 PCI_PRODUCT_BROADCOM_BCM5787M, 565 "Broadcom BCM5787M Gigabit Ethernet", 566 }, 567 { PCI_VENDOR_BROADCOM, 568 PCI_PRODUCT_BROADCOM_BCM5788, 569 "Broadcom BCM5788 Gigabit Ethernet", 570 }, 571 { PCI_VENDOR_BROADCOM, 572 PCI_PRODUCT_BROADCOM_BCM5789, 573 "Broadcom BCM5789 Gigabit Ethernet", 574 }, 575 { PCI_VENDOR_BROADCOM, 576 PCI_PRODUCT_BROADCOM_BCM5901, 577 "Broadcom BCM5901 Fast Ethernet", 578 }, 579 { PCI_VENDOR_BROADCOM, 580 PCI_PRODUCT_BROADCOM_BCM5901A2, 581 "Broadcom BCM5901A2 Fast Ethernet", 582 }, 583 { PCI_VENDOR_BROADCOM, 584 PCI_PRODUCT_BROADCOM_BCM5903M, 585 "Broadcom BCM5903M Fast Ethernet", 586 }, 587 { PCI_VENDOR_BROADCOM, 588 PCI_PRODUCT_BROADCOM_BCM5906, 589 "Broadcom BCM5906 Fast Ethernet", 590 }, 591 { PCI_VENDOR_BROADCOM, 592 PCI_PRODUCT_BROADCOM_BCM5906M, 593 "Broadcom BCM5906M Fast Ethernet", 594 }, 595 { PCI_VENDOR_BROADCOM, 596 PCI_PRODUCT_BROADCOM_BCM57760, 597 "Broadcom BCM57760 Fast Ethernet", 598 }, 599 { PCI_VENDOR_BROADCOM, 600 PCI_PRODUCT_BROADCOM_BCM57761, 601 "Broadcom BCM57761 Fast Ethernet", 602 }, 603 { PCI_VENDOR_BROADCOM, 604 PCI_PRODUCT_BROADCOM_BCM57762, 605 "Broadcom BCM57762 Gigabit Ethernet", 606 }, 607 { PCI_VENDOR_BROADCOM, 608 PCI_PRODUCT_BROADCOM_BCM57765, 609 "Broadcom BCM57765 Fast Ethernet", 610 }, 611 { PCI_VENDOR_BROADCOM, 612 PCI_PRODUCT_BROADCOM_BCM57766, 613 "Broadcom BCM57766 Fast Ethernet", 614 }, 615 { PCI_VENDOR_BROADCOM, 616 PCI_PRODUCT_BROADCOM_BCM57780, 617 "Broadcom BCM57780 Fast Ethernet", 618 }, 619 { PCI_VENDOR_BROADCOM, 620 PCI_PRODUCT_BROADCOM_BCM57781, 621 "Broadcom BCM57781 Fast Ethernet", 622 }, 623 { PCI_VENDOR_BROADCOM, 624 PCI_PRODUCT_BROADCOM_BCM57782, 625 "Broadcom BCM57782 Fast Ethernet", 626 }, 627 { PCI_VENDOR_BROADCOM, 628 PCI_PRODUCT_BROADCOM_BCM57785, 629 "Broadcom BCM57785 Fast Ethernet", 630 }, 631 { PCI_VENDOR_BROADCOM, 632 PCI_PRODUCT_BROADCOM_BCM57786, 633 "Broadcom BCM57786 Fast Ethernet", 634 }, 635 { PCI_VENDOR_BROADCOM, 636 PCI_PRODUCT_BROADCOM_BCM57788, 637 "Broadcom BCM57788 Fast Ethernet", 638 }, 639 { PCI_VENDOR_BROADCOM, 640 PCI_PRODUCT_BROADCOM_BCM57790, 641 "Broadcom BCM57790 Fast Ethernet", 642 }, 643 { PCI_VENDOR_BROADCOM, 644 PCI_PRODUCT_BROADCOM_BCM57791, 645 "Broadcom BCM57791 Fast Ethernet", 646 }, 647 { PCI_VENDOR_BROADCOM, 648 PCI_PRODUCT_BROADCOM_BCM57795, 649 "Broadcom BCM57795 Fast Ethernet", 650 }, 651 { PCI_VENDOR_SCHNEIDERKOCH, 652 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 653 "SysKonnect SK-9Dx1 Gigabit Ethernet", 654 }, 655 { PCI_VENDOR_3COM, 656 PCI_PRODUCT_3COM_3C996, 657 "3Com 3c996 Gigabit Ethernet", 658 }, 659 { PCI_VENDOR_FUJITSU4, 660 PCI_PRODUCT_FUJITSU4_PW008GE4, 661 "Fujitsu PW008GE4 Gigabit Ethernet", 662 }, 663 { PCI_VENDOR_FUJITSU4, 664 PCI_PRODUCT_FUJITSU4_PW008GE5, 665 "Fujitsu PW008GE5 Gigabit Ethernet", 666 }, 667 { PCI_VENDOR_FUJITSU4, 668 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 669 "Fujitsu Primepower 250/450 Gigabit Ethernet", 670 }, 671 { 0, 672 0, 673 NULL }, 674 }; 675 676 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 677 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 678 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 679 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 680 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 681 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 683 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 684 685 static const struct bge_revision { 686 uint32_t br_chipid; 687 const char *br_name; 688 } bge_revisions[] = { 689 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 690 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 691 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 692 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 693 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 694 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 695 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 696 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 697 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 698 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 699 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 700 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 701 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 702 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 703 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 704 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 705 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 706 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 707 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 708 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 709 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 710 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 711 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 712 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 713 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 714 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 715 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 716 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 717 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 718 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 719 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 720 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 721 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 722 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 723 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 724 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 725 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 726 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 727 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 728 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 729 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 730 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 731 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 732 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 733 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 734 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 735 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 736 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 737 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 738 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 739 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 740 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 741 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 742 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 743 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 744 /* 5754 and 5787 share the same ASIC ID */ 745 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 746 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 747 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 748 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 749 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 750 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 751 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 752 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 753 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 754 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 755 756 { 0, NULL } 757 }; 758 759 /* 760 * Some defaults for major revisions, so that newer steppings 761 * that we don't know about have a shot at working. 762 */ 763 static const struct bge_revision bge_majorrevs[] = { 764 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 765 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 766 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 767 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 768 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 769 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 770 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 772 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 773 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 774 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 775 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 776 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 777 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 778 /* 5754 and 5787 share the same ASIC ID */ 779 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 780 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 781 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 782 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 783 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 784 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 785 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 786 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 787 788 { 0, NULL } 789 }; 790 791 static int bge_allow_asf = 1; 792 793 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 794 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 795 796 static uint32_t 797 bge_readmem_ind(struct bge_softc *sc, int off) 798 { 799 pcireg_t val; 800 801 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 802 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 803 return 0; 804 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 806 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 807 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 808 return val; 809 } 810 811 static void 812 bge_writemem_ind(struct bge_softc *sc, int off, int val) 813 { 814 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 817 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 818 } 819 820 /* 821 * PCI Express only 822 */ 823 static void 824 bge_set_max_readrq(struct bge_softc *sc) 825 { 826 pcireg_t val; 827 828 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 829 + PCI_PCIE_DCSR); 830 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 831 switch (sc->bge_expmrq) { 832 case 2048: 833 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 834 break; 835 case 4096: 836 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 837 break; 838 default: 839 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 840 break; 841 } 842 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 843 + PCI_PCIE_DCSR, val); 844 } 845 846 #ifdef notdef 847 static uint32_t 848 bge_readreg_ind(struct bge_softc *sc, int off) 849 { 850 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 851 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 852 } 853 #endif 854 855 static void 856 bge_writereg_ind(struct bge_softc *sc, int off, int val) 857 { 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 859 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 860 } 861 862 static void 863 bge_writemem_direct(struct bge_softc *sc, int off, int val) 864 { 865 CSR_WRITE_4(sc, off, val); 866 } 867 868 static void 869 bge_writembx(struct bge_softc *sc, int off, int val) 870 { 871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 872 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 873 874 CSR_WRITE_4(sc, off, val); 875 } 876 877 static void 878 bge_writembx_flush(struct bge_softc *sc, int off, int val) 879 { 880 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 881 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 882 883 CSR_WRITE_4_FLUSH(sc, off, val); 884 } 885 886 /* 887 * Clear all stale locks and select the lock for this driver instance. 888 */ 889 void 890 bge_ape_lock_init(struct bge_softc *sc) 891 { 892 struct pci_attach_args *pa = &(sc->bge_pa); 893 uint32_t bit, regbase; 894 int i; 895 896 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 897 regbase = BGE_APE_LOCK_GRANT; 898 else 899 regbase = BGE_APE_PER_LOCK_GRANT; 900 901 /* Clear any stale locks. */ 902 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 903 switch (i) { 904 case BGE_APE_LOCK_PHY0: 905 case BGE_APE_LOCK_PHY1: 906 case BGE_APE_LOCK_PHY2: 907 case BGE_APE_LOCK_PHY3: 908 bit = BGE_APE_LOCK_GRANT_DRIVER0; 909 break; 910 default: 911 if (pa->pa_function == 0) 912 bit = BGE_APE_LOCK_GRANT_DRIVER0; 913 else 914 bit = (1 << pa->pa_function); 915 } 916 APE_WRITE_4(sc, regbase + 4 * i, bit); 917 } 918 919 /* Select the PHY lock based on the device's function number. */ 920 switch (pa->pa_function) { 921 case 0: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 923 break; 924 case 1: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 926 break; 927 case 2: 928 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 929 break; 930 case 3: 931 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 932 break; 933 default: 934 printf("%s: PHY lock not supported on function\n", 935 device_xname(sc->bge_dev)); 936 break; 937 } 938 } 939 940 /* 941 * Check for APE firmware, set flags, and print version info. 942 */ 943 void 944 bge_ape_read_fw_ver(struct bge_softc *sc) 945 { 946 const char *fwtype; 947 uint32_t apedata, features; 948 949 /* Check for a valid APE signature in shared memory. */ 950 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 951 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 952 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 953 return; 954 } 955 956 /* Check if APE firmware is running. */ 957 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 958 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 959 printf("%s: APE signature found but FW status not ready! " 960 "0x%08x\n", device_xname(sc->bge_dev), apedata); 961 return; 962 } 963 964 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 965 966 /* Fetch the APE firwmare type and version. */ 967 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 968 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 969 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 970 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 971 fwtype = "NCSI"; 972 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 973 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 974 fwtype = "DASH"; 975 } else 976 fwtype = "UNKN"; 977 978 /* Print the APE firmware version. */ 979 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 980 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 981 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 982 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 983 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 984 } 985 986 int 987 bge_ape_lock(struct bge_softc *sc, int locknum) 988 { 989 struct pci_attach_args *pa = &(sc->bge_pa); 990 uint32_t bit, gnt, req, status; 991 int i, off; 992 993 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 994 return (0); 995 996 /* Lock request/grant registers have different bases. */ 997 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 998 req = BGE_APE_LOCK_REQ; 999 gnt = BGE_APE_LOCK_GRANT; 1000 } else { 1001 req = BGE_APE_PER_LOCK_REQ; 1002 gnt = BGE_APE_PER_LOCK_GRANT; 1003 } 1004 1005 off = 4 * locknum; 1006 1007 switch (locknum) { 1008 case BGE_APE_LOCK_GPIO: 1009 /* Lock required when using GPIO. */ 1010 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1011 return (0); 1012 if (pa->pa_function == 0) 1013 bit = BGE_APE_LOCK_REQ_DRIVER0; 1014 else 1015 bit = (1 << pa->pa_function); 1016 break; 1017 case BGE_APE_LOCK_GRC: 1018 /* Lock required to reset the device. */ 1019 if (pa->pa_function == 0) 1020 bit = BGE_APE_LOCK_REQ_DRIVER0; 1021 else 1022 bit = (1 << pa->pa_function); 1023 break; 1024 case BGE_APE_LOCK_MEM: 1025 /* Lock required when accessing certain APE memory. */ 1026 if (pa->pa_function == 0) 1027 bit = BGE_APE_LOCK_REQ_DRIVER0; 1028 else 1029 bit = (1 << pa->pa_function); 1030 break; 1031 case BGE_APE_LOCK_PHY0: 1032 case BGE_APE_LOCK_PHY1: 1033 case BGE_APE_LOCK_PHY2: 1034 case BGE_APE_LOCK_PHY3: 1035 /* Lock required when accessing PHYs. */ 1036 bit = BGE_APE_LOCK_REQ_DRIVER0; 1037 break; 1038 default: 1039 return (EINVAL); 1040 } 1041 1042 /* Request a lock. */ 1043 APE_WRITE_4_FLUSH(sc, req + off, bit); 1044 1045 /* Wait up to 1 second to acquire lock. */ 1046 for (i = 0; i < 20000; i++) { 1047 status = APE_READ_4(sc, gnt + off); 1048 if (status == bit) 1049 break; 1050 DELAY(50); 1051 } 1052 1053 /* Handle any errors. */ 1054 if (status != bit) { 1055 printf("%s: APE lock %d request failed! " 1056 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1057 device_xname(sc->bge_dev), 1058 locknum, req + off, bit & 0xFFFF, gnt + off, 1059 status & 0xFFFF); 1060 /* Revoke the lock request. */ 1061 APE_WRITE_4(sc, gnt + off, bit); 1062 return (EBUSY); 1063 } 1064 1065 return (0); 1066 } 1067 1068 void 1069 bge_ape_unlock(struct bge_softc *sc, int locknum) 1070 { 1071 struct pci_attach_args *pa = &(sc->bge_pa); 1072 uint32_t bit, gnt; 1073 int off; 1074 1075 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1076 return; 1077 1078 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1079 gnt = BGE_APE_LOCK_GRANT; 1080 else 1081 gnt = BGE_APE_PER_LOCK_GRANT; 1082 1083 off = 4 * locknum; 1084 1085 switch (locknum) { 1086 case BGE_APE_LOCK_GPIO: 1087 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1088 return; 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_GRC: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_MEM: 1101 if (pa->pa_function == 0) 1102 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1103 else 1104 bit = (1 << pa->pa_function); 1105 break; 1106 case BGE_APE_LOCK_PHY0: 1107 case BGE_APE_LOCK_PHY1: 1108 case BGE_APE_LOCK_PHY2: 1109 case BGE_APE_LOCK_PHY3: 1110 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1111 break; 1112 default: 1113 return; 1114 } 1115 1116 /* Write and flush for consecutive bge_ape_lock() */ 1117 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1118 } 1119 1120 /* 1121 * Send an event to the APE firmware. 1122 */ 1123 void 1124 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1125 { 1126 uint32_t apedata; 1127 int i; 1128 1129 /* NCSI does not support APE events. */ 1130 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1131 return; 1132 1133 /* Wait up to 1ms for APE to service previous event. */ 1134 for (i = 10; i > 0; i--) { 1135 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1136 break; 1137 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1138 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1139 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1140 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1141 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1142 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1143 break; 1144 } 1145 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1146 DELAY(100); 1147 } 1148 if (i == 0) { 1149 printf("%s: APE event 0x%08x send timed out\n", 1150 device_xname(sc->bge_dev), event); 1151 } 1152 } 1153 1154 void 1155 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1156 { 1157 uint32_t apedata, event; 1158 1159 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1160 return; 1161 1162 switch (kind) { 1163 case BGE_RESET_START: 1164 /* If this is the first load, clear the load counter. */ 1165 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1166 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1167 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1168 else { 1169 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1170 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1171 } 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1173 BGE_APE_HOST_SEG_SIG_MAGIC); 1174 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1175 BGE_APE_HOST_SEG_LEN_MAGIC); 1176 1177 /* Add some version info if bge(4) supports it. */ 1178 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1179 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1180 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1181 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1182 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1183 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1184 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1185 BGE_APE_HOST_DRVR_STATE_START); 1186 event = BGE_APE_EVENT_STATUS_STATE_START; 1187 break; 1188 case BGE_RESET_SHUTDOWN: 1189 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1190 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1191 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1192 break; 1193 case BGE_RESET_SUSPEND: 1194 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1195 break; 1196 default: 1197 return; 1198 } 1199 1200 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1201 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1202 } 1203 1204 static uint8_t 1205 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1206 { 1207 uint32_t access, byte = 0; 1208 int i; 1209 1210 /* Lock. */ 1211 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1212 for (i = 0; i < 8000; i++) { 1213 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1214 break; 1215 DELAY(20); 1216 } 1217 if (i == 8000) 1218 return 1; 1219 1220 /* Enable access. */ 1221 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1222 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1223 1224 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1225 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1226 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1227 DELAY(10); 1228 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1229 DELAY(10); 1230 break; 1231 } 1232 } 1233 1234 if (i == BGE_TIMEOUT * 10) { 1235 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1236 return 1; 1237 } 1238 1239 /* Get result. */ 1240 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1241 1242 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1243 1244 /* Disable access. */ 1245 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1246 1247 /* Unlock. */ 1248 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1249 1250 return 0; 1251 } 1252 1253 /* 1254 * Read a sequence of bytes from NVRAM. 1255 */ 1256 static int 1257 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1258 { 1259 int error = 0, i; 1260 uint8_t byte = 0; 1261 1262 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1263 return 1; 1264 1265 for (i = 0; i < cnt; i++) { 1266 error = bge_nvram_getbyte(sc, off + i, &byte); 1267 if (error) 1268 break; 1269 *(dest + i) = byte; 1270 } 1271 1272 return (error ? 1 : 0); 1273 } 1274 1275 /* 1276 * Read a byte of data stored in the EEPROM at address 'addr.' The 1277 * BCM570x supports both the traditional bitbang interface and an 1278 * auto access interface for reading the EEPROM. We use the auto 1279 * access method. 1280 */ 1281 static uint8_t 1282 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1283 { 1284 int i; 1285 uint32_t byte = 0; 1286 1287 /* 1288 * Enable use of auto EEPROM access so we can avoid 1289 * having to use the bitbang method. 1290 */ 1291 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1292 1293 /* Reset the EEPROM, load the clock period. */ 1294 CSR_WRITE_4(sc, BGE_EE_ADDR, 1295 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1296 DELAY(20); 1297 1298 /* Issue the read EEPROM command. */ 1299 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1300 1301 /* Wait for completion */ 1302 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1303 DELAY(10); 1304 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1305 break; 1306 } 1307 1308 if (i == BGE_TIMEOUT * 10) { 1309 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1310 return 1; 1311 } 1312 1313 /* Get result. */ 1314 byte = CSR_READ_4(sc, BGE_EE_DATA); 1315 1316 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1317 1318 return 0; 1319 } 1320 1321 /* 1322 * Read a sequence of bytes from the EEPROM. 1323 */ 1324 static int 1325 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1326 { 1327 int error = 0, i; 1328 uint8_t byte = 0; 1329 char *dest = destv; 1330 1331 for (i = 0; i < cnt; i++) { 1332 error = bge_eeprom_getbyte(sc, off + i, &byte); 1333 if (error) 1334 break; 1335 *(dest + i) = byte; 1336 } 1337 1338 return (error ? 1 : 0); 1339 } 1340 1341 static int 1342 bge_miibus_readreg(device_t dev, int phy, int reg) 1343 { 1344 struct bge_softc *sc = device_private(dev); 1345 uint32_t val; 1346 uint32_t autopoll; 1347 int i; 1348 1349 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1350 return 0; 1351 1352 /* Reading with autopolling on may trigger PCI errors */ 1353 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1354 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1355 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1356 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1357 DELAY(80); 1358 } 1359 1360 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1361 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1362 1363 for (i = 0; i < BGE_TIMEOUT; i++) { 1364 delay(10); 1365 val = CSR_READ_4(sc, BGE_MI_COMM); 1366 if (!(val & BGE_MICOMM_BUSY)) { 1367 DELAY(5); 1368 val = CSR_READ_4(sc, BGE_MI_COMM); 1369 break; 1370 } 1371 } 1372 1373 if (i == BGE_TIMEOUT) { 1374 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1375 val = 0; 1376 goto done; 1377 } 1378 1379 done: 1380 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1381 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1382 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1383 DELAY(80); 1384 } 1385 1386 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1387 1388 if (val & BGE_MICOMM_READFAIL) 1389 return 0; 1390 1391 return (val & 0xFFFF); 1392 } 1393 1394 static void 1395 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1396 { 1397 struct bge_softc *sc = device_private(dev); 1398 uint32_t autopoll; 1399 int i; 1400 1401 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1402 return; 1403 1404 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1405 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1406 return; 1407 1408 /* Reading with autopolling on may trigger PCI errors */ 1409 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1410 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1411 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1412 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1413 DELAY(80); 1414 } 1415 1416 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1417 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1418 1419 for (i = 0; i < BGE_TIMEOUT; i++) { 1420 delay(10); 1421 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1422 delay(5); 1423 CSR_READ_4(sc, BGE_MI_COMM); 1424 break; 1425 } 1426 } 1427 1428 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1429 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1430 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1431 delay(80); 1432 } 1433 1434 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1435 1436 if (i == BGE_TIMEOUT) 1437 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1438 } 1439 1440 static void 1441 bge_miibus_statchg(struct ifnet *ifp) 1442 { 1443 struct bge_softc *sc = ifp->if_softc; 1444 struct mii_data *mii = &sc->bge_mii; 1445 uint32_t mac_mode, rx_mode, tx_mode; 1446 1447 /* 1448 * Get flow control negotiation result. 1449 */ 1450 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1451 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1452 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1453 mii->mii_media_active &= ~IFM_ETH_FMASK; 1454 } 1455 1456 /* Set the port mode (MII/GMII) to match the link speed. */ 1457 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1458 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1459 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1460 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1461 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1462 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1463 mac_mode |= BGE_PORTMODE_GMII; 1464 else 1465 mac_mode |= BGE_PORTMODE_MII; 1466 1467 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1468 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1469 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1470 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1471 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1472 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1473 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1474 } else 1475 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1476 1477 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1478 DELAY(40); 1479 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1480 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1481 } 1482 1483 /* 1484 * Update rx threshold levels to values in a particular slot 1485 * of the interrupt-mitigation table bge_rx_threshes. 1486 */ 1487 static void 1488 bge_set_thresh(struct ifnet *ifp, int lvl) 1489 { 1490 struct bge_softc *sc = ifp->if_softc; 1491 int s; 1492 1493 /* For now, just save the new Rx-intr thresholds and record 1494 * that a threshold update is pending. Updating the hardware 1495 * registers here (even at splhigh()) is observed to 1496 * occasionaly cause glitches where Rx-interrupts are not 1497 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1498 */ 1499 s = splnet(); 1500 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1501 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1502 sc->bge_pending_rxintr_change = 1; 1503 splx(s); 1504 } 1505 1506 1507 /* 1508 * Update Rx thresholds of all bge devices 1509 */ 1510 static void 1511 bge_update_all_threshes(int lvl) 1512 { 1513 struct ifnet *ifp; 1514 const char * const namebuf = "bge"; 1515 int namelen; 1516 1517 if (lvl < 0) 1518 lvl = 0; 1519 else if (lvl >= NBGE_RX_THRESH) 1520 lvl = NBGE_RX_THRESH - 1; 1521 1522 namelen = strlen(namebuf); 1523 /* 1524 * Now search all the interfaces for this name/number 1525 */ 1526 IFNET_FOREACH(ifp) { 1527 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1528 continue; 1529 /* We got a match: update if doing auto-threshold-tuning */ 1530 if (bge_auto_thresh) 1531 bge_set_thresh(ifp, lvl); 1532 } 1533 } 1534 1535 /* 1536 * Handle events that have triggered interrupts. 1537 */ 1538 static void 1539 bge_handle_events(struct bge_softc *sc) 1540 { 1541 1542 return; 1543 } 1544 1545 /* 1546 * Memory management for jumbo frames. 1547 */ 1548 1549 static int 1550 bge_alloc_jumbo_mem(struct bge_softc *sc) 1551 { 1552 char *ptr, *kva; 1553 bus_dma_segment_t seg; 1554 int i, rseg, state, error; 1555 struct bge_jpool_entry *entry; 1556 1557 state = error = 0; 1558 1559 /* Grab a big chunk o' storage. */ 1560 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1561 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1562 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1563 return ENOBUFS; 1564 } 1565 1566 state = 1; 1567 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1568 BUS_DMA_NOWAIT)) { 1569 aprint_error_dev(sc->bge_dev, 1570 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1571 error = ENOBUFS; 1572 goto out; 1573 } 1574 1575 state = 2; 1576 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1577 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1578 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1579 error = ENOBUFS; 1580 goto out; 1581 } 1582 1583 state = 3; 1584 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1585 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1586 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1587 error = ENOBUFS; 1588 goto out; 1589 } 1590 1591 state = 4; 1592 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1593 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1594 1595 SLIST_INIT(&sc->bge_jfree_listhead); 1596 SLIST_INIT(&sc->bge_jinuse_listhead); 1597 1598 /* 1599 * Now divide it up into 9K pieces and save the addresses 1600 * in an array. 1601 */ 1602 ptr = sc->bge_cdata.bge_jumbo_buf; 1603 for (i = 0; i < BGE_JSLOTS; i++) { 1604 sc->bge_cdata.bge_jslots[i] = ptr; 1605 ptr += BGE_JLEN; 1606 entry = malloc(sizeof(struct bge_jpool_entry), 1607 M_DEVBUF, M_NOWAIT); 1608 if (entry == NULL) { 1609 aprint_error_dev(sc->bge_dev, 1610 "no memory for jumbo buffer queue!\n"); 1611 error = ENOBUFS; 1612 goto out; 1613 } 1614 entry->slot = i; 1615 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1616 entry, jpool_entries); 1617 } 1618 out: 1619 if (error != 0) { 1620 switch (state) { 1621 case 4: 1622 bus_dmamap_unload(sc->bge_dmatag, 1623 sc->bge_cdata.bge_rx_jumbo_map); 1624 case 3: 1625 bus_dmamap_destroy(sc->bge_dmatag, 1626 sc->bge_cdata.bge_rx_jumbo_map); 1627 case 2: 1628 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1629 case 1: 1630 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1631 break; 1632 default: 1633 break; 1634 } 1635 } 1636 1637 return error; 1638 } 1639 1640 /* 1641 * Allocate a jumbo buffer. 1642 */ 1643 static void * 1644 bge_jalloc(struct bge_softc *sc) 1645 { 1646 struct bge_jpool_entry *entry; 1647 1648 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1649 1650 if (entry == NULL) { 1651 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1652 return NULL; 1653 } 1654 1655 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1656 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1657 return (sc->bge_cdata.bge_jslots[entry->slot]); 1658 } 1659 1660 /* 1661 * Release a jumbo buffer. 1662 */ 1663 static void 1664 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1665 { 1666 struct bge_jpool_entry *entry; 1667 struct bge_softc *sc; 1668 int i, s; 1669 1670 /* Extract the softc struct pointer. */ 1671 sc = (struct bge_softc *)arg; 1672 1673 if (sc == NULL) 1674 panic("bge_jfree: can't find softc pointer!"); 1675 1676 /* calculate the slot this buffer belongs to */ 1677 1678 i = ((char *)buf 1679 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1680 1681 if ((i < 0) || (i >= BGE_JSLOTS)) 1682 panic("bge_jfree: asked to free buffer that we don't manage!"); 1683 1684 s = splvm(); 1685 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1686 if (entry == NULL) 1687 panic("bge_jfree: buffer not in use!"); 1688 entry->slot = i; 1689 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1690 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1691 1692 if (__predict_true(m != NULL)) 1693 pool_cache_put(mb_cache, m); 1694 splx(s); 1695 } 1696 1697 1698 /* 1699 * Initialize a standard receive ring descriptor. 1700 */ 1701 static int 1702 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1703 bus_dmamap_t dmamap) 1704 { 1705 struct mbuf *m_new = NULL; 1706 struct bge_rx_bd *r; 1707 int error; 1708 1709 if (dmamap == NULL) { 1710 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1711 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1712 if (error != 0) 1713 return error; 1714 } 1715 1716 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1717 1718 if (m == NULL) { 1719 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1720 if (m_new == NULL) 1721 return ENOBUFS; 1722 1723 MCLGET(m_new, M_DONTWAIT); 1724 if (!(m_new->m_flags & M_EXT)) { 1725 m_freem(m_new); 1726 return ENOBUFS; 1727 } 1728 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1729 1730 } else { 1731 m_new = m; 1732 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1733 m_new->m_data = m_new->m_ext.ext_buf; 1734 } 1735 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1736 m_adj(m_new, ETHER_ALIGN); 1737 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1738 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1739 return ENOBUFS; 1740 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1741 BUS_DMASYNC_PREREAD); 1742 1743 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1744 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1745 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1746 r->bge_flags = BGE_RXBDFLAG_END; 1747 r->bge_len = m_new->m_len; 1748 r->bge_idx = i; 1749 1750 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1751 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1752 i * sizeof (struct bge_rx_bd), 1753 sizeof (struct bge_rx_bd), 1754 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1755 1756 return 0; 1757 } 1758 1759 /* 1760 * Initialize a jumbo receive ring descriptor. This allocates 1761 * a jumbo buffer from the pool managed internally by the driver. 1762 */ 1763 static int 1764 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1765 { 1766 struct mbuf *m_new = NULL; 1767 struct bge_rx_bd *r; 1768 void *buf = NULL; 1769 1770 if (m == NULL) { 1771 1772 /* Allocate the mbuf. */ 1773 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1774 if (m_new == NULL) 1775 return ENOBUFS; 1776 1777 /* Allocate the jumbo buffer */ 1778 buf = bge_jalloc(sc); 1779 if (buf == NULL) { 1780 m_freem(m_new); 1781 aprint_error_dev(sc->bge_dev, 1782 "jumbo allocation failed -- packet dropped!\n"); 1783 return ENOBUFS; 1784 } 1785 1786 /* Attach the buffer to the mbuf. */ 1787 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1788 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1789 bge_jfree, sc); 1790 m_new->m_flags |= M_EXT_RW; 1791 } else { 1792 m_new = m; 1793 buf = m_new->m_data = m_new->m_ext.ext_buf; 1794 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1795 } 1796 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1797 m_adj(m_new, ETHER_ALIGN); 1798 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1799 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1800 BUS_DMASYNC_PREREAD); 1801 /* Set up the descriptor. */ 1802 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1803 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1804 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1805 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1806 r->bge_len = m_new->m_len; 1807 r->bge_idx = i; 1808 1809 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1810 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1811 i * sizeof (struct bge_rx_bd), 1812 sizeof (struct bge_rx_bd), 1813 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1814 1815 return 0; 1816 } 1817 1818 /* 1819 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1820 * that's 1MB or memory, which is a lot. For now, we fill only the first 1821 * 256 ring entries and hope that our CPU is fast enough to keep up with 1822 * the NIC. 1823 */ 1824 static int 1825 bge_init_rx_ring_std(struct bge_softc *sc) 1826 { 1827 int i; 1828 1829 if (sc->bge_flags & BGE_RXRING_VALID) 1830 return 0; 1831 1832 for (i = 0; i < BGE_SSLOTS; i++) { 1833 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1834 return ENOBUFS; 1835 } 1836 1837 sc->bge_std = i - 1; 1838 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1839 1840 sc->bge_flags |= BGE_RXRING_VALID; 1841 1842 return 0; 1843 } 1844 1845 static void 1846 bge_free_rx_ring_std(struct bge_softc *sc) 1847 { 1848 int i; 1849 1850 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1851 return; 1852 1853 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1854 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1855 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1856 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1857 bus_dmamap_destroy(sc->bge_dmatag, 1858 sc->bge_cdata.bge_rx_std_map[i]); 1859 } 1860 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1861 sizeof(struct bge_rx_bd)); 1862 } 1863 1864 sc->bge_flags &= ~BGE_RXRING_VALID; 1865 } 1866 1867 static int 1868 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1869 { 1870 int i; 1871 volatile struct bge_rcb *rcb; 1872 1873 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1874 return 0; 1875 1876 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1877 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1878 return ENOBUFS; 1879 } 1880 1881 sc->bge_jumbo = i - 1; 1882 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1883 1884 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1885 rcb->bge_maxlen_flags = 0; 1886 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1887 1888 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1889 1890 return 0; 1891 } 1892 1893 static void 1894 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1895 { 1896 int i; 1897 1898 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1899 return; 1900 1901 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1902 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1903 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1904 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1905 } 1906 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1907 sizeof(struct bge_rx_bd)); 1908 } 1909 1910 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1911 } 1912 1913 static void 1914 bge_free_tx_ring(struct bge_softc *sc) 1915 { 1916 int i; 1917 struct txdmamap_pool_entry *dma; 1918 1919 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1920 return; 1921 1922 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1923 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1924 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1925 sc->bge_cdata.bge_tx_chain[i] = NULL; 1926 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1927 link); 1928 sc->txdma[i] = 0; 1929 } 1930 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1931 sizeof(struct bge_tx_bd)); 1932 } 1933 1934 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1935 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1936 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1937 free(dma, M_DEVBUF); 1938 } 1939 1940 sc->bge_flags &= ~BGE_TXRING_VALID; 1941 } 1942 1943 static int 1944 bge_init_tx_ring(struct bge_softc *sc) 1945 { 1946 int i; 1947 bus_dmamap_t dmamap; 1948 struct txdmamap_pool_entry *dma; 1949 1950 if (sc->bge_flags & BGE_TXRING_VALID) 1951 return 0; 1952 1953 sc->bge_txcnt = 0; 1954 sc->bge_tx_saved_considx = 0; 1955 1956 /* Initialize transmit producer index for host-memory send ring. */ 1957 sc->bge_tx_prodidx = 0; 1958 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1959 /* 5700 b2 errata */ 1960 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1961 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1962 1963 /* NIC-memory send ring not used; initialize to zero. */ 1964 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1965 /* 5700 b2 errata */ 1966 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1967 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1968 1969 SLIST_INIT(&sc->txdma_list); 1970 for (i = 0; i < BGE_RSLOTS; i++) { 1971 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1972 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1973 &dmamap)) 1974 return ENOBUFS; 1975 if (dmamap == NULL) 1976 panic("dmamap NULL in bge_init_tx_ring"); 1977 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1978 if (dma == NULL) { 1979 aprint_error_dev(sc->bge_dev, 1980 "can't alloc txdmamap_pool_entry\n"); 1981 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1982 return ENOMEM; 1983 } 1984 dma->dmamap = dmamap; 1985 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1986 } 1987 1988 sc->bge_flags |= BGE_TXRING_VALID; 1989 1990 return 0; 1991 } 1992 1993 static void 1994 bge_setmulti(struct bge_softc *sc) 1995 { 1996 struct ethercom *ac = &sc->ethercom; 1997 struct ifnet *ifp = &ac->ec_if; 1998 struct ether_multi *enm; 1999 struct ether_multistep step; 2000 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2001 uint32_t h; 2002 int i; 2003 2004 if (ifp->if_flags & IFF_PROMISC) 2005 goto allmulti; 2006 2007 /* Now program new ones. */ 2008 ETHER_FIRST_MULTI(step, ac, enm); 2009 while (enm != NULL) { 2010 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2011 /* 2012 * We must listen to a range of multicast addresses. 2013 * For now, just accept all multicasts, rather than 2014 * trying to set only those filter bits needed to match 2015 * the range. (At this time, the only use of address 2016 * ranges is for IP multicast routing, for which the 2017 * range is big enough to require all bits set.) 2018 */ 2019 goto allmulti; 2020 } 2021 2022 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2023 2024 /* Just want the 7 least-significant bits. */ 2025 h &= 0x7f; 2026 2027 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2028 ETHER_NEXT_MULTI(step, enm); 2029 } 2030 2031 ifp->if_flags &= ~IFF_ALLMULTI; 2032 goto setit; 2033 2034 allmulti: 2035 ifp->if_flags |= IFF_ALLMULTI; 2036 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2037 2038 setit: 2039 for (i = 0; i < 4; i++) 2040 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2041 } 2042 2043 static void 2044 bge_sig_pre_reset(struct bge_softc *sc, int type) 2045 { 2046 2047 /* 2048 * Some chips don't like this so only do this if ASF is enabled 2049 */ 2050 if (sc->bge_asf_mode) 2051 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2052 2053 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2054 switch (type) { 2055 case BGE_RESET_START: 2056 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2057 BGE_FW_DRV_STATE_START); 2058 break; 2059 case BGE_RESET_SHUTDOWN: 2060 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2061 BGE_FW_DRV_STATE_UNLOAD); 2062 break; 2063 case BGE_RESET_SUSPEND: 2064 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2065 BGE_FW_DRV_STATE_SUSPEND); 2066 break; 2067 } 2068 } 2069 2070 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2071 bge_ape_driver_state_change(sc, type); 2072 } 2073 2074 static void 2075 bge_sig_post_reset(struct bge_softc *sc, int type) 2076 { 2077 2078 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2079 switch (type) { 2080 case BGE_RESET_START: 2081 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2082 BGE_FW_DRV_STATE_START_DONE); 2083 /* START DONE */ 2084 break; 2085 case BGE_RESET_SHUTDOWN: 2086 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2087 BGE_FW_DRV_STATE_UNLOAD_DONE); 2088 break; 2089 } 2090 } 2091 2092 if (type == BGE_RESET_SHUTDOWN) 2093 bge_ape_driver_state_change(sc, type); 2094 } 2095 2096 static void 2097 bge_sig_legacy(struct bge_softc *sc, int type) 2098 { 2099 2100 if (sc->bge_asf_mode) { 2101 switch (type) { 2102 case BGE_RESET_START: 2103 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2104 BGE_FW_DRV_STATE_START); 2105 break; 2106 case BGE_RESET_SHUTDOWN: 2107 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2108 BGE_FW_DRV_STATE_UNLOAD); 2109 break; 2110 } 2111 } 2112 } 2113 2114 static void 2115 bge_wait_for_event_ack(struct bge_softc *sc) 2116 { 2117 int i; 2118 2119 /* wait up to 2500usec */ 2120 for (i = 0; i < 250; i++) { 2121 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2122 BGE_RX_CPU_DRV_EVENT)) 2123 break; 2124 DELAY(10); 2125 } 2126 } 2127 2128 static void 2129 bge_stop_fw(struct bge_softc *sc) 2130 { 2131 2132 if (sc->bge_asf_mode) { 2133 bge_wait_for_event_ack(sc); 2134 2135 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2136 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2137 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2138 2139 bge_wait_for_event_ack(sc); 2140 } 2141 } 2142 2143 static int 2144 bge_poll_fw(struct bge_softc *sc) 2145 { 2146 uint32_t val; 2147 int i; 2148 2149 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2150 for (i = 0; i < BGE_TIMEOUT; i++) { 2151 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2152 if (val & BGE_VCPU_STATUS_INIT_DONE) 2153 break; 2154 DELAY(100); 2155 } 2156 if (i >= BGE_TIMEOUT) { 2157 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2158 return -1; 2159 } 2160 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2161 /* 2162 * Poll the value location we just wrote until 2163 * we see the 1's complement of the magic number. 2164 * This indicates that the firmware initialization 2165 * is complete. 2166 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2167 */ 2168 for (i = 0; i < BGE_TIMEOUT; i++) { 2169 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2170 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2171 break; 2172 DELAY(10); 2173 } 2174 2175 if (i >= BGE_TIMEOUT) { 2176 aprint_error_dev(sc->bge_dev, 2177 "firmware handshake timed out, val = %x\n", val); 2178 return -1; 2179 } 2180 } 2181 2182 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2183 /* tg3 says we have to wait extra time */ 2184 delay(10 * 1000); 2185 } 2186 2187 return 0; 2188 } 2189 2190 int 2191 bge_phy_addr(struct bge_softc *sc) 2192 { 2193 struct pci_attach_args *pa = &(sc->bge_pa); 2194 int phy_addr = 1; 2195 2196 /* 2197 * PHY address mapping for various devices. 2198 * 2199 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2200 * ---------+-------+-------+-------+-------+ 2201 * BCM57XX | 1 | X | X | X | 2202 * BCM5704 | 1 | X | 1 | X | 2203 * BCM5717 | 1 | 8 | 2 | 9 | 2204 * BCM5719 | 1 | 8 | 2 | 9 | 2205 * BCM5720 | 1 | 8 | 2 | 9 | 2206 * 2207 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2208 * ---------+-------+-------+-------+-------+ 2209 * BCM57XX | X | X | X | X | 2210 * BCM5704 | X | X | X | X | 2211 * BCM5717 | X | X | X | X | 2212 * BCM5719 | 3 | 10 | 4 | 11 | 2213 * BCM5720 | X | X | X | X | 2214 * 2215 * Other addresses may respond but they are not 2216 * IEEE compliant PHYs and should be ignored. 2217 */ 2218 switch (BGE_ASICREV(sc->bge_chipid)) { 2219 case BGE_ASICREV_BCM5717: 2220 case BGE_ASICREV_BCM5719: 2221 case BGE_ASICREV_BCM5720: 2222 phy_addr = pa->pa_function; 2223 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2224 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2225 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2226 } else { 2227 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2228 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2229 } 2230 } 2231 2232 return phy_addr; 2233 } 2234 2235 /* 2236 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2237 * self-test results. 2238 */ 2239 static int 2240 bge_chipinit(struct bge_softc *sc) 2241 { 2242 uint32_t dma_rw_ctl, mode_ctl, reg; 2243 int i; 2244 2245 /* Set endianness before we access any non-PCI registers. */ 2246 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2247 BGE_INIT); 2248 2249 /* 2250 * Clear the MAC statistics block in the NIC's 2251 * internal memory. 2252 */ 2253 for (i = BGE_STATS_BLOCK; 2254 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2255 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2256 2257 for (i = BGE_STATUS_BLOCK; 2258 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2259 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2260 2261 /* 5717 workaround from tg3 */ 2262 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2263 /* Save */ 2264 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2265 2266 /* Temporary modify MODE_CTL to control TLP */ 2267 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2268 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2269 2270 /* Control TLP */ 2271 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2272 BGE_TLP_PHYCTL1); 2273 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2274 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2275 2276 /* Restore */ 2277 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2278 } 2279 2280 /* XXX Should we use 57765_FAMILY? */ 2281 if (BGE_IS_57765_PLUS(sc)) { 2282 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2283 /* Save */ 2284 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2285 2286 /* Temporary modify MODE_CTL to control TLP */ 2287 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2288 CSR_WRITE_4(sc, BGE_MODE_CTL, 2289 reg | BGE_MODECTL_PCIE_TLPADDR1); 2290 2291 /* Control TLP */ 2292 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2293 BGE_TLP_PHYCTL5); 2294 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2295 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2296 2297 /* Restore */ 2298 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2299 } 2300 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2301 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2302 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2303 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2304 2305 /* Save */ 2306 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2307 2308 /* Temporary modify MODE_CTL to control TLP */ 2309 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2310 CSR_WRITE_4(sc, BGE_MODE_CTL, 2311 reg | BGE_MODECTL_PCIE_TLPADDR0); 2312 2313 /* Control TLP */ 2314 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2315 BGE_TLP_FTSMAX); 2316 reg &= ~BGE_TLP_FTSMAX_MSK; 2317 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2318 reg | BGE_TLP_FTSMAX_VAL); 2319 2320 /* Restore */ 2321 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2322 } 2323 2324 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2325 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2326 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2327 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2328 } 2329 2330 /* Set up the PCI DMA control register. */ 2331 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2332 if (sc->bge_flags & BGE_PCIE) { 2333 /* Read watermark not used, 128 bytes for write. */ 2334 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2335 device_xname(sc->bge_dev))); 2336 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2337 } else if (sc->bge_flags & BGE_PCIX) { 2338 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2339 device_xname(sc->bge_dev))); 2340 /* PCI-X bus */ 2341 if (BGE_IS_5714_FAMILY(sc)) { 2342 /* 256 bytes for read and write. */ 2343 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2344 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2345 2346 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2347 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2348 else 2349 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2350 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2351 /* 1536 bytes for read, 384 bytes for write. */ 2352 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2353 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2354 } else { 2355 /* 384 bytes for read and write. */ 2356 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2357 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2358 (0x0F); 2359 } 2360 2361 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2362 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2363 uint32_t tmp; 2364 2365 /* Set ONEDMA_ATONCE for hardware workaround. */ 2366 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2367 if (tmp == 6 || tmp == 7) 2368 dma_rw_ctl |= 2369 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2370 2371 /* Set PCI-X DMA write workaround. */ 2372 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2373 } 2374 } else { 2375 /* Conventional PCI bus: 256 bytes for read and write. */ 2376 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2377 device_xname(sc->bge_dev))); 2378 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2379 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2380 2381 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2382 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2383 dma_rw_ctl |= 0x0F; 2384 } 2385 2386 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2387 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2388 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2389 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2390 2391 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2392 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2393 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2394 2395 if (BGE_IS_5717_PLUS(sc)) { 2396 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2397 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2398 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2399 2400 /* 2401 * Enable HW workaround for controllers that misinterpret 2402 * a status tag update and leave interrupts permanently 2403 * disabled. 2404 */ 2405 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2406 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2407 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2408 } 2409 2410 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2411 dma_rw_ctl); 2412 2413 /* 2414 * Set up general mode register. 2415 */ 2416 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2417 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2418 /* Retain Host-2-BMC settings written by APE firmware. */ 2419 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2420 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2421 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2422 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2423 } 2424 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2425 BGE_MODECTL_TX_NO_PHDR_CSUM; 2426 2427 /* 2428 * BCM5701 B5 have a bug causing data corruption when using 2429 * 64-bit DMA reads, which can be terminated early and then 2430 * completed later as 32-bit accesses, in combination with 2431 * certain bridges. 2432 */ 2433 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2434 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2435 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2436 2437 /* 2438 * Tell the firmware the driver is running 2439 */ 2440 if (sc->bge_asf_mode & ASF_STACKUP) 2441 mode_ctl |= BGE_MODECTL_STACKUP; 2442 2443 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2444 2445 /* 2446 * Disable memory write invalidate. Apparently it is not supported 2447 * properly by these devices. 2448 */ 2449 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2450 PCI_COMMAND_INVALIDATE_ENABLE); 2451 2452 #ifdef __brokenalpha__ 2453 /* 2454 * Must insure that we do not cross an 8K (bytes) boundary 2455 * for DMA reads. Our highest limit is 1K bytes. This is a 2456 * restriction on some ALPHA platforms with early revision 2457 * 21174 PCI chipsets, such as the AlphaPC 164lx 2458 */ 2459 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2460 #endif 2461 2462 /* Set the timer prescaler (always 66MHz) */ 2463 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2464 2465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2466 DELAY(40); /* XXX */ 2467 2468 /* Put PHY into ready state */ 2469 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2470 DELAY(40); 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int 2477 bge_blockinit(struct bge_softc *sc) 2478 { 2479 volatile struct bge_rcb *rcb; 2480 bus_size_t rcb_addr; 2481 struct ifnet *ifp = &sc->ethercom.ec_if; 2482 bge_hostaddr taddr; 2483 uint32_t dmactl, val; 2484 int i, limit; 2485 2486 /* 2487 * Initialize the memory window pointer register so that 2488 * we can access the first 32K of internal NIC RAM. This will 2489 * allow us to set up the TX send ring RCBs and the RX return 2490 * ring RCBs, plus other things which live in NIC memory. 2491 */ 2492 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2493 2494 /* Step 33: Configure mbuf memory pool */ 2495 if (!BGE_IS_5705_PLUS(sc)) { 2496 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2497 BGE_BUFFPOOL_1); 2498 2499 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2501 else 2502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2503 2504 /* Configure DMA resource pool */ 2505 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2506 BGE_DMA_DESCRIPTORS); 2507 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2508 } 2509 2510 /* Step 35: Configure mbuf pool watermarks */ 2511 /* new broadcom docs strongly recommend these: */ 2512 if (BGE_IS_5717_PLUS(sc)) { 2513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2514 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2515 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2516 } else if (BGE_IS_5705_PLUS(sc)) { 2517 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2518 2519 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2521 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2522 } else { 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2524 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2525 } 2526 } else { 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2530 } 2531 2532 /* Step 36: Configure DMA resource watermarks */ 2533 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2534 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2535 2536 /* Step 38: Enable buffer manager */ 2537 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2538 /* 2539 * Change the arbitration algorithm of TXMBUF read request to 2540 * round-robin instead of priority based for BCM5719. When 2541 * TXFIFO is almost empty, RDMA will hold its request until 2542 * TXFIFO is not almost empty. 2543 */ 2544 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2545 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2546 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2547 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2548 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2549 val |= BGE_BMANMODE_LOMBUF_ATTN; 2550 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2551 2552 /* Step 39: Poll for buffer manager start indication */ 2553 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2554 DELAY(10); 2555 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2556 break; 2557 } 2558 2559 if (i == BGE_TIMEOUT * 2) { 2560 aprint_error_dev(sc->bge_dev, 2561 "buffer manager failed to start\n"); 2562 return ENXIO; 2563 } 2564 2565 /* Step 40: Enable flow-through queues */ 2566 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2567 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2568 2569 /* Wait until queue initialization is complete */ 2570 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2571 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2572 break; 2573 DELAY(10); 2574 } 2575 2576 if (i == BGE_TIMEOUT * 2) { 2577 aprint_error_dev(sc->bge_dev, 2578 "flow-through queue init failed\n"); 2579 return ENXIO; 2580 } 2581 2582 /* 2583 * Summary of rings supported by the controller: 2584 * 2585 * Standard Receive Producer Ring 2586 * - This ring is used to feed receive buffers for "standard" 2587 * sized frames (typically 1536 bytes) to the controller. 2588 * 2589 * Jumbo Receive Producer Ring 2590 * - This ring is used to feed receive buffers for jumbo sized 2591 * frames (i.e. anything bigger than the "standard" frames) 2592 * to the controller. 2593 * 2594 * Mini Receive Producer Ring 2595 * - This ring is used to feed receive buffers for "mini" 2596 * sized frames to the controller. 2597 * - This feature required external memory for the controller 2598 * but was never used in a production system. Should always 2599 * be disabled. 2600 * 2601 * Receive Return Ring 2602 * - After the controller has placed an incoming frame into a 2603 * receive buffer that buffer is moved into a receive return 2604 * ring. The driver is then responsible to passing the 2605 * buffer up to the stack. Many versions of the controller 2606 * support multiple RR rings. 2607 * 2608 * Send Ring 2609 * - This ring is used for outgoing frames. Many versions of 2610 * the controller support multiple send rings. 2611 */ 2612 2613 /* Step 41: Initialize the standard RX ring control block */ 2614 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2615 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2616 if (BGE_IS_5717_PLUS(sc)) { 2617 /* 2618 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2619 * Bits 15-2 : Maximum RX frame size 2620 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2621 * Bit 0 : Reserved 2622 */ 2623 rcb->bge_maxlen_flags = 2624 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2625 } else if (BGE_IS_5705_PLUS(sc)) { 2626 /* 2627 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2628 * Bits 15-2 : Reserved (should be 0) 2629 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2630 * Bit 0 : Reserved 2631 */ 2632 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2633 } else { 2634 /* 2635 * Ring size is always XXX entries 2636 * Bits 31-16: Maximum RX frame size 2637 * Bits 15-2 : Reserved (should be 0) 2638 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2639 * Bit 0 : Reserved 2640 */ 2641 rcb->bge_maxlen_flags = 2642 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2643 } 2644 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2646 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2647 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2648 else 2649 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2650 /* Write the standard receive producer ring control block. */ 2651 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2652 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2653 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2654 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2655 2656 /* Reset the standard receive producer ring producer index. */ 2657 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2658 2659 /* 2660 * Step 42: Initialize the jumbo RX ring control block 2661 * We set the 'ring disabled' bit in the flags 2662 * field until we're actually ready to start 2663 * using this ring (i.e. once we set the MTU 2664 * high enough to require it). 2665 */ 2666 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2667 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2668 BGE_HOSTADDR(rcb->bge_hostaddr, 2669 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2670 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2671 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2672 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2674 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2675 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2676 else 2677 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2678 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2679 rcb->bge_hostaddr.bge_addr_hi); 2680 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2681 rcb->bge_hostaddr.bge_addr_lo); 2682 /* Program the jumbo receive producer ring RCB parameters. */ 2683 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2684 rcb->bge_maxlen_flags); 2685 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2686 /* Reset the jumbo receive producer ring producer index. */ 2687 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2688 } 2689 2690 /* Disable the mini receive producer ring RCB. */ 2691 if (BGE_IS_5700_FAMILY(sc)) { 2692 /* Set up dummy disabled mini ring RCB */ 2693 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2694 rcb->bge_maxlen_flags = 2695 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2696 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2697 rcb->bge_maxlen_flags); 2698 /* Reset the mini receive producer ring producer index. */ 2699 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2700 2701 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2702 offsetof(struct bge_ring_data, bge_info), 2703 sizeof (struct bge_gib), 2704 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2705 } 2706 2707 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2708 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2709 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2710 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2711 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2712 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2713 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2714 } 2715 /* 2716 * The BD ring replenish thresholds control how often the 2717 * hardware fetches new BD's from the producer rings in host 2718 * memory. Setting the value too low on a busy system can 2719 * starve the hardware and recue the throughpout. 2720 * 2721 * Set the BD ring replenish thresholds. The recommended 2722 * values are 1/8th the number of descriptors allocated to 2723 * each ring, but since we try to avoid filling the entire 2724 * ring we set these to the minimal value of 8. This needs to 2725 * be done on several of the supported chip revisions anyway, 2726 * to work around HW bugs. 2727 */ 2728 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2729 if (BGE_IS_JUMBO_CAPABLE(sc)) 2730 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2731 2732 if (BGE_IS_5717_PLUS(sc)) { 2733 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2734 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2735 } 2736 2737 /* 2738 * Disable all send rings by setting the 'ring disabled' bit 2739 * in the flags field of all the TX send ring control blocks, 2740 * located in NIC memory. 2741 */ 2742 if (BGE_IS_5700_FAMILY(sc)) { 2743 /* 5700 to 5704 had 16 send rings. */ 2744 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2745 } else 2746 limit = 1; 2747 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2748 for (i = 0; i < limit; i++) { 2749 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2750 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2751 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2752 rcb_addr += sizeof(struct bge_rcb); 2753 } 2754 2755 /* Configure send ring RCB 0 (we use only the first ring) */ 2756 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2757 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2758 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2759 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2760 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2761 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2762 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2763 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2764 else 2765 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2766 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2767 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2768 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2769 2770 /* 2771 * Disable all receive return rings by setting the 2772 * 'ring diabled' bit in the flags field of all the receive 2773 * return ring control blocks, located in NIC memory. 2774 */ 2775 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2776 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2777 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2778 /* Should be 17, use 16 until we get an SRAM map. */ 2779 limit = 16; 2780 } else if (BGE_IS_5700_FAMILY(sc)) 2781 limit = BGE_RX_RINGS_MAX; 2782 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2783 BGE_IS_57765_PLUS(sc)) 2784 limit = 4; 2785 else 2786 limit = 1; 2787 /* Disable all receive return rings */ 2788 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2789 for (i = 0; i < limit; i++) { 2790 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2791 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2792 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2793 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2794 BGE_RCB_FLAG_RING_DISABLED)); 2795 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2796 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2797 (i * (sizeof(uint64_t))), 0); 2798 rcb_addr += sizeof(struct bge_rcb); 2799 } 2800 2801 /* 2802 * Set up receive return ring 0. Note that the NIC address 2803 * for RX return rings is 0x0. The return rings live entirely 2804 * within the host, so the nicaddr field in the RCB isn't used. 2805 */ 2806 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2807 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2808 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2809 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2810 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2811 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2812 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2813 2814 /* Set random backoff seed for TX */ 2815 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2816 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2817 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2818 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2819 BGE_TX_BACKOFF_SEED_MASK); 2820 2821 /* Set inter-packet gap */ 2822 val = 0x2620; 2823 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2824 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2825 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2826 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2827 2828 /* 2829 * Specify which ring to use for packets that don't match 2830 * any RX rules. 2831 */ 2832 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2833 2834 /* 2835 * Configure number of RX lists. One interrupt distribution 2836 * list, sixteen active lists, one bad frames class. 2837 */ 2838 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2839 2840 /* Inialize RX list placement stats mask. */ 2841 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2842 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2843 2844 /* Disable host coalescing until we get it set up */ 2845 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2846 2847 /* Poll to make sure it's shut down. */ 2848 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2849 DELAY(10); 2850 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2851 break; 2852 } 2853 2854 if (i == BGE_TIMEOUT * 2) { 2855 aprint_error_dev(sc->bge_dev, 2856 "host coalescing engine failed to idle\n"); 2857 return ENXIO; 2858 } 2859 2860 /* Set up host coalescing defaults */ 2861 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2862 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2863 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2864 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2865 if (!(BGE_IS_5705_PLUS(sc))) { 2866 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2867 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2868 } 2869 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2870 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2871 2872 /* Set up address of statistics block */ 2873 if (BGE_IS_5700_FAMILY(sc)) { 2874 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2875 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2876 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2877 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2878 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2879 } 2880 2881 /* Set up address of status block */ 2882 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2883 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2884 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2885 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2886 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2887 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2888 2889 /* Set up status block size. */ 2890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2891 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2892 val = BGE_STATBLKSZ_FULL; 2893 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2894 } else { 2895 val = BGE_STATBLKSZ_32BYTE; 2896 bzero(&sc->bge_rdata->bge_status_block, 32); 2897 } 2898 2899 /* Turn on host coalescing state machine */ 2900 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2901 2902 /* Turn on RX BD completion state machine and enable attentions */ 2903 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2904 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2905 2906 /* Turn on RX list placement state machine */ 2907 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2908 2909 /* Turn on RX list selector state machine. */ 2910 if (!(BGE_IS_5705_PLUS(sc))) 2911 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2912 2913 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2914 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2915 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2916 BGE_MACMODE_FRMHDR_DMA_ENB; 2917 2918 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2919 val |= BGE_PORTMODE_TBI; 2920 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2921 val |= BGE_PORTMODE_GMII; 2922 else 2923 val |= BGE_PORTMODE_MII; 2924 2925 /* Allow APE to send/receive frames. */ 2926 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2927 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2928 2929 /* Turn on DMA, clear stats */ 2930 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2931 DELAY(40); 2932 2933 /* Set misc. local control, enable interrupts on attentions */ 2934 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2935 if (BGE_IS_5717_PLUS(sc)) { 2936 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2937 DELAY(100); 2938 } 2939 2940 /* Turn on DMA completion state machine */ 2941 if (!(BGE_IS_5705_PLUS(sc))) 2942 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2943 2944 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2945 2946 /* Enable host coalescing bug fix. */ 2947 if (BGE_IS_5755_PLUS(sc)) 2948 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2949 2950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2951 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2952 2953 /* Turn on write DMA state machine */ 2954 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2955 DELAY(40); 2956 2957 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2958 2959 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2960 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2961 2962 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2963 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2964 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2965 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2966 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2967 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2968 2969 if (sc->bge_flags & BGE_PCIE) 2970 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2971 if (sc->bge_flags & BGE_TSO) 2972 val |= BGE_RDMAMODE_TSO4_ENABLE; 2973 2974 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2975 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2976 BGE_RDMAMODE_H2BNC_VLAN_DET; 2977 /* 2978 * Allow multiple outstanding read requests from 2979 * non-LSO read DMA engine. 2980 */ 2981 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2982 } 2983 2984 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2985 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2986 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2987 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2988 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 2989 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2990 /* 2991 * Adjust tx margin to prevent TX data corruption and 2992 * fix internal FIFO overflow. 2993 */ 2994 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2995 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2996 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2997 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2998 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2999 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3000 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3001 } 3002 /* 3003 * Enable fix for read DMA FIFO overruns. 3004 * The fix is to limit the number of RX BDs 3005 * the hardware would fetch at a fime. 3006 */ 3007 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3008 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3009 } 3010 3011 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3012 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3013 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3014 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3015 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3016 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3017 /* 3018 * Allow 4KB burst length reads for non-LSO frames. 3019 * Enable 512B burst length reads for buffer descriptors. 3020 */ 3021 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3022 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3023 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3024 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3025 } 3026 3027 /* Turn on read DMA state machine */ 3028 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3029 delay(40); 3030 3031 /* Turn on RX data completion state machine */ 3032 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3033 3034 /* Turn on RX data and RX BD initiator state machine */ 3035 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3036 3037 /* Turn on Mbuf cluster free state machine */ 3038 if (!BGE_IS_5705_PLUS(sc)) 3039 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3040 3041 /* Turn on send data completion state machine */ 3042 val = BGE_SDCMODE_ENABLE; 3043 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3044 val |= BGE_SDCMODE_CDELAY; 3045 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3046 3047 /* Turn on send BD completion state machine */ 3048 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3049 3050 /* Turn on RX BD initiator state machine */ 3051 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3052 3053 /* Turn on send data initiator state machine */ 3054 if (sc->bge_flags & BGE_TSO) { 3055 /* XXX: magic value from Linux driver */ 3056 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3057 BGE_SDIMODE_HW_LSO_PRE_DMA); 3058 } else 3059 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3060 3061 /* Turn on send BD initiator state machine */ 3062 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3063 3064 /* Turn on send BD selector state machine */ 3065 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3066 3067 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3068 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3069 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3070 3071 /* ack/clear link change events */ 3072 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3073 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3074 BGE_MACSTAT_LINK_CHANGED); 3075 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3076 3077 /* 3078 * Enable attention when the link has changed state for 3079 * devices that use auto polling. 3080 */ 3081 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3082 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3083 } else { 3084 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3085 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3087 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3088 BGE_EVTENB_MI_INTERRUPT); 3089 } 3090 3091 /* 3092 * Clear any pending link state attention. 3093 * Otherwise some link state change events may be lost until attention 3094 * is cleared by bge_intr() -> bge_link_upd() sequence. 3095 * It's not necessary on newer BCM chips - perhaps enabling link 3096 * state change attentions implies clearing pending attention. 3097 */ 3098 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3099 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3100 BGE_MACSTAT_LINK_CHANGED); 3101 3102 /* Enable link state change attentions. */ 3103 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3104 3105 return 0; 3106 } 3107 3108 static const struct bge_revision * 3109 bge_lookup_rev(uint32_t chipid) 3110 { 3111 const struct bge_revision *br; 3112 3113 for (br = bge_revisions; br->br_name != NULL; br++) { 3114 if (br->br_chipid == chipid) 3115 return br; 3116 } 3117 3118 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3119 if (br->br_chipid == BGE_ASICREV(chipid)) 3120 return br; 3121 } 3122 3123 return NULL; 3124 } 3125 3126 static const struct bge_product * 3127 bge_lookup(const struct pci_attach_args *pa) 3128 { 3129 const struct bge_product *bp; 3130 3131 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3132 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3133 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3134 return bp; 3135 } 3136 3137 return NULL; 3138 } 3139 3140 static uint32_t 3141 bge_chipid(const struct pci_attach_args *pa) 3142 { 3143 uint32_t id; 3144 3145 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3146 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3147 3148 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3149 switch (PCI_PRODUCT(pa->pa_id)) { 3150 case PCI_PRODUCT_BROADCOM_BCM5717: 3151 case PCI_PRODUCT_BROADCOM_BCM5718: 3152 case PCI_PRODUCT_BROADCOM_BCM5719: 3153 case PCI_PRODUCT_BROADCOM_BCM5720: 3154 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3155 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3156 BGE_PCI_GEN2_PRODID_ASICREV); 3157 break; 3158 case PCI_PRODUCT_BROADCOM_BCM57761: 3159 case PCI_PRODUCT_BROADCOM_BCM57762: 3160 case PCI_PRODUCT_BROADCOM_BCM57765: 3161 case PCI_PRODUCT_BROADCOM_BCM57766: 3162 case PCI_PRODUCT_BROADCOM_BCM57781: 3163 case PCI_PRODUCT_BROADCOM_BCM57785: 3164 case PCI_PRODUCT_BROADCOM_BCM57791: 3165 case PCI_PRODUCT_BROADCOM_BCM57795: 3166 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3167 BGE_PCI_GEN15_PRODID_ASICREV); 3168 break; 3169 default: 3170 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3171 BGE_PCI_PRODID_ASICREV); 3172 break; 3173 } 3174 } 3175 3176 return id; 3177 } 3178 3179 /* 3180 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3181 * against our list and return its name if we find a match. Note 3182 * that since the Broadcom controller contains VPD support, we 3183 * can get the device name string from the controller itself instead 3184 * of the compiled-in string. This is a little slow, but it guarantees 3185 * we'll always announce the right product name. 3186 */ 3187 static int 3188 bge_probe(device_t parent, cfdata_t match, void *aux) 3189 { 3190 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3191 3192 if (bge_lookup(pa) != NULL) 3193 return 1; 3194 3195 return 0; 3196 } 3197 3198 static void 3199 bge_attach(device_t parent, device_t self, void *aux) 3200 { 3201 struct bge_softc *sc = device_private(self); 3202 struct pci_attach_args *pa = aux; 3203 prop_dictionary_t dict; 3204 const struct bge_product *bp; 3205 const struct bge_revision *br; 3206 pci_chipset_tag_t pc; 3207 pci_intr_handle_t ih; 3208 const char *intrstr = NULL; 3209 uint32_t hwcfg = 0; 3210 uint32_t command; 3211 struct ifnet *ifp; 3212 uint32_t misccfg; 3213 void * kva; 3214 u_char eaddr[ETHER_ADDR_LEN]; 3215 pcireg_t memtype, subid, reg; 3216 bus_addr_t memaddr; 3217 uint32_t pm_ctl; 3218 bool no_seeprom; 3219 int capmask; 3220 3221 bp = bge_lookup(pa); 3222 KASSERT(bp != NULL); 3223 3224 sc->sc_pc = pa->pa_pc; 3225 sc->sc_pcitag = pa->pa_tag; 3226 sc->bge_dev = self; 3227 3228 sc->bge_pa = *pa; 3229 pc = sc->sc_pc; 3230 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3231 3232 aprint_naive(": Ethernet controller\n"); 3233 aprint_normal(": %s\n", bp->bp_name); 3234 3235 /* 3236 * Map control/status registers. 3237 */ 3238 DPRINTFN(5, ("Map control/status regs\n")); 3239 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3240 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3241 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3242 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3243 3244 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3245 aprint_error_dev(sc->bge_dev, 3246 "failed to enable memory mapping!\n"); 3247 return; 3248 } 3249 3250 DPRINTFN(5, ("pci_mem_find\n")); 3251 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3252 switch (memtype) { 3253 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3254 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3255 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3256 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3257 &memaddr, &sc->bge_bsize) == 0) 3258 break; 3259 default: 3260 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3261 return; 3262 } 3263 3264 DPRINTFN(5, ("pci_intr_map\n")); 3265 if (pci_intr_map(pa, &ih)) { 3266 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3267 return; 3268 } 3269 3270 DPRINTFN(5, ("pci_intr_string\n")); 3271 intrstr = pci_intr_string(pc, ih); 3272 3273 DPRINTFN(5, ("pci_intr_establish\n")); 3274 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3275 3276 if (sc->bge_intrhand == NULL) { 3277 aprint_error_dev(sc->bge_dev, 3278 "couldn't establish interrupt%s%s\n", 3279 intrstr ? " at " : "", intrstr ? intrstr : ""); 3280 return; 3281 } 3282 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3283 3284 /* Save various chip information. */ 3285 sc->bge_chipid = bge_chipid(pa); 3286 sc->bge_phy_addr = bge_phy_addr(sc); 3287 3288 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3289 &sc->bge_pciecap, NULL) != 0) 3290 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3291 /* PCIe */ 3292 sc->bge_flags |= BGE_PCIE; 3293 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3294 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3295 sc->bge_expmrq = 2048; 3296 else 3297 sc->bge_expmrq = 4096; 3298 bge_set_max_readrq(sc); 3299 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3300 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3301 /* PCI-X */ 3302 sc->bge_flags |= BGE_PCIX; 3303 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3304 &sc->bge_pcixcap, NULL) == 0) 3305 aprint_error_dev(sc->bge_dev, 3306 "unable to find PCIX capability\n"); 3307 } 3308 3309 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3310 /* 3311 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3312 * can clobber the chip's PCI config-space power control 3313 * registers, leaving the card in D3 powersave state. We do 3314 * not have memory-mapped registers in this state, so force 3315 * device into D0 state before starting initialization. 3316 */ 3317 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3318 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3319 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3320 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3321 DELAY(1000); /* 27 usec is allegedly sufficent */ 3322 } 3323 3324 /* Save chipset family. */ 3325 switch (BGE_ASICREV(sc->bge_chipid)) { 3326 case BGE_ASICREV_BCM57765: 3327 case BGE_ASICREV_BCM57766: 3328 sc->bge_flags |= BGE_57765_PLUS; 3329 /* FALLTHROUGH */ 3330 case BGE_ASICREV_BCM5717: 3331 case BGE_ASICREV_BCM5719: 3332 case BGE_ASICREV_BCM5720: 3333 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3334 BGE_5705_PLUS; 3335 break; 3336 case BGE_ASICREV_BCM5755: 3337 case BGE_ASICREV_BCM5761: 3338 case BGE_ASICREV_BCM5784: 3339 case BGE_ASICREV_BCM5785: 3340 case BGE_ASICREV_BCM5787: 3341 case BGE_ASICREV_BCM57780: 3342 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3343 break; 3344 case BGE_ASICREV_BCM5700: 3345 case BGE_ASICREV_BCM5701: 3346 case BGE_ASICREV_BCM5703: 3347 case BGE_ASICREV_BCM5704: 3348 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3349 break; 3350 case BGE_ASICREV_BCM5714_A0: 3351 case BGE_ASICREV_BCM5780: 3352 case BGE_ASICREV_BCM5714: 3353 sc->bge_flags |= BGE_5714_FAMILY; 3354 /* FALLTHROUGH */ 3355 case BGE_ASICREV_BCM5750: 3356 case BGE_ASICREV_BCM5752: 3357 case BGE_ASICREV_BCM5906: 3358 sc->bge_flags |= BGE_575X_PLUS; 3359 /* FALLTHROUGH */ 3360 case BGE_ASICREV_BCM5705: 3361 sc->bge_flags |= BGE_5705_PLUS; 3362 break; 3363 } 3364 3365 /* Identify chips with APE processor. */ 3366 switch (BGE_ASICREV(sc->bge_chipid)) { 3367 case BGE_ASICREV_BCM5717: 3368 case BGE_ASICREV_BCM5719: 3369 case BGE_ASICREV_BCM5720: 3370 case BGE_ASICREV_BCM5761: 3371 sc->bge_flags |= BGE_APE; 3372 break; 3373 } 3374 3375 /* Chips with APE need BAR2 access for APE registers/memory. */ 3376 if ((sc->bge_flags & BGE_APE) != 0) { 3377 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3378 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3379 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3380 &sc->bge_apesize)) { 3381 aprint_error_dev(sc->bge_dev, 3382 "couldn't map BAR2 memory\n"); 3383 return; 3384 } 3385 3386 /* Enable APE register/memory access by host driver. */ 3387 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3388 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3389 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3390 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3391 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3392 3393 bge_ape_lock_init(sc); 3394 bge_ape_read_fw_ver(sc); 3395 } 3396 3397 /* Identify the chips that use an CPMU. */ 3398 if (BGE_IS_5717_PLUS(sc) || 3399 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3400 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3401 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3402 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3403 sc->bge_flags |= BGE_CPMU_PRESENT; 3404 3405 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3406 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_500KHZ_CONST); 3407 else 3408 CSR_WRITE_4(sc, BGE_MI_MODE, BGE_MIMODE_BASE); 3409 3410 /* 3411 * When using the BCM5701 in PCI-X mode, data corruption has 3412 * been observed in the first few bytes of some received packets. 3413 * Aligning the packet buffer in memory eliminates the corruption. 3414 * Unfortunately, this misaligns the packet payloads. On platforms 3415 * which do not support unaligned accesses, we will realign the 3416 * payloads by copying the received packets. 3417 */ 3418 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3419 sc->bge_flags & BGE_PCIX) 3420 sc->bge_flags |= BGE_RX_ALIGNBUG; 3421 3422 if (BGE_IS_5700_FAMILY(sc)) 3423 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3424 3425 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3426 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3427 3428 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3429 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3430 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3431 sc->bge_flags |= BGE_IS_5788; 3432 3433 /* 3434 * Some controllers seem to require a special firmware to use 3435 * TSO. But the firmware is not available to FreeBSD and Linux 3436 * claims that the TSO performed by the firmware is slower than 3437 * hardware based TSO. Moreover the firmware based TSO has one 3438 * known bug which can't handle TSO if ethernet header + IP/TCP 3439 * header is greater than 80 bytes. The workaround for the TSO 3440 * bug exist but it seems it's too expensive than not using 3441 * TSO at all. Some hardwares also have the TSO bug so limit 3442 * the TSO to the controllers that are not affected TSO issues 3443 * (e.g. 5755 or higher). 3444 */ 3445 if (BGE_IS_5755_PLUS(sc)) { 3446 /* 3447 * BCM5754 and BCM5787 shares the same ASIC id so 3448 * explicit device id check is required. 3449 */ 3450 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3451 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3452 sc->bge_flags |= BGE_TSO; 3453 } 3454 3455 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3456 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3457 (misccfg == 0x4000 || misccfg == 0x8000)) || 3458 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3459 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3460 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3461 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3463 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3464 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3465 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3466 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3467 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3468 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3469 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3470 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3471 capmask &= ~BMSR_EXTSTAT; 3472 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3473 } 3474 3475 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3476 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3477 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3478 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3479 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3480 3481 /* Set various PHY bug flags. */ 3482 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3483 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3484 sc->bge_flags |= BGE_PHY_CRC_BUG; 3485 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3486 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3487 sc->bge_flags |= BGE_PHY_ADC_BUG; 3488 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3489 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3490 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3492 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3493 sc->bge_flags |= BGE_PHY_NO_3LED; 3494 if (BGE_IS_5705_PLUS(sc) && 3495 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3496 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3497 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3498 !BGE_IS_5717_PLUS(sc)) { 3499 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3500 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3503 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3504 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3505 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3506 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3507 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3508 } else 3509 sc->bge_flags |= BGE_PHY_BER_BUG; 3510 } 3511 3512 /* 3513 * SEEPROM check. 3514 * First check if firmware knows we do not have SEEPROM. 3515 */ 3516 if (prop_dictionary_get_bool(device_properties(self), 3517 "without-seeprom", &no_seeprom) && no_seeprom) 3518 sc->bge_flags |= BGE_NO_EEPROM; 3519 3520 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3521 sc->bge_flags |= BGE_NO_EEPROM; 3522 3523 /* Now check the 'ROM failed' bit on the RX CPU */ 3524 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3525 sc->bge_flags |= BGE_NO_EEPROM; 3526 3527 sc->bge_asf_mode = 0; 3528 /* No ASF if APE present. */ 3529 if ((sc->bge_flags & BGE_APE) == 0) { 3530 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3531 BGE_SRAM_DATA_SIG_MAGIC)) { 3532 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3533 BGE_HWCFG_ASF) { 3534 sc->bge_asf_mode |= ASF_ENABLE; 3535 sc->bge_asf_mode |= ASF_STACKUP; 3536 if (BGE_IS_575X_PLUS(sc)) 3537 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3538 } 3539 } 3540 } 3541 3542 #if 0 3543 /* 3544 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3545 * lock in bge_reset(). 3546 */ 3547 CSR_WRITE_4(sc, BGE_EE_ADDR, 3548 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3549 delay(1000); 3550 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3551 #endif 3552 3553 bge_stop_fw(sc); 3554 bge_sig_pre_reset(sc, BGE_RESET_START); 3555 if (bge_reset(sc)) 3556 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3557 3558 bge_sig_legacy(sc, BGE_RESET_START); 3559 bge_sig_post_reset(sc, BGE_RESET_START); 3560 3561 if (bge_chipinit(sc)) { 3562 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3563 bge_release_resources(sc); 3564 return; 3565 } 3566 3567 /* 3568 * Get station address from the EEPROM. 3569 */ 3570 if (bge_get_eaddr(sc, eaddr)) { 3571 aprint_error_dev(sc->bge_dev, 3572 "failed to read station address\n"); 3573 bge_release_resources(sc); 3574 return; 3575 } 3576 3577 br = bge_lookup_rev(sc->bge_chipid); 3578 3579 if (br == NULL) { 3580 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3581 sc->bge_chipid); 3582 } else { 3583 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3584 br->br_name, sc->bge_chipid); 3585 } 3586 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3587 3588 /* Allocate the general information block and ring buffers. */ 3589 if (pci_dma64_available(pa)) 3590 sc->bge_dmatag = pa->pa_dmat64; 3591 else 3592 sc->bge_dmatag = pa->pa_dmat; 3593 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3594 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3595 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3596 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3597 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3598 return; 3599 } 3600 DPRINTFN(5, ("bus_dmamem_map\n")); 3601 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3602 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3603 BUS_DMA_NOWAIT)) { 3604 aprint_error_dev(sc->bge_dev, 3605 "can't map DMA buffers (%zu bytes)\n", 3606 sizeof(struct bge_ring_data)); 3607 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3608 sc->bge_ring_rseg); 3609 return; 3610 } 3611 DPRINTFN(5, ("bus_dmamem_create\n")); 3612 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3613 sizeof(struct bge_ring_data), 0, 3614 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3615 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3616 bus_dmamem_unmap(sc->bge_dmatag, kva, 3617 sizeof(struct bge_ring_data)); 3618 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3619 sc->bge_ring_rseg); 3620 return; 3621 } 3622 DPRINTFN(5, ("bus_dmamem_load\n")); 3623 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3624 sizeof(struct bge_ring_data), NULL, 3625 BUS_DMA_NOWAIT)) { 3626 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3627 bus_dmamem_unmap(sc->bge_dmatag, kva, 3628 sizeof(struct bge_ring_data)); 3629 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3630 sc->bge_ring_rseg); 3631 return; 3632 } 3633 3634 DPRINTFN(5, ("bzero\n")); 3635 sc->bge_rdata = (struct bge_ring_data *)kva; 3636 3637 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3638 3639 /* Try to allocate memory for jumbo buffers. */ 3640 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3641 if (bge_alloc_jumbo_mem(sc)) { 3642 aprint_error_dev(sc->bge_dev, 3643 "jumbo buffer allocation failed\n"); 3644 } else 3645 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3646 } 3647 3648 /* Set default tuneable values. */ 3649 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3650 sc->bge_rx_coal_ticks = 150; 3651 sc->bge_rx_max_coal_bds = 64; 3652 sc->bge_tx_coal_ticks = 300; 3653 sc->bge_tx_max_coal_bds = 400; 3654 if (BGE_IS_5705_PLUS(sc)) { 3655 sc->bge_tx_coal_ticks = (12 * 5); 3656 sc->bge_tx_max_coal_bds = (12 * 5); 3657 aprint_verbose_dev(sc->bge_dev, 3658 "setting short Tx thresholds\n"); 3659 } 3660 3661 if (BGE_IS_5717_PLUS(sc)) 3662 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3663 else if (BGE_IS_5705_PLUS(sc)) 3664 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3665 else 3666 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3667 3668 /* Set up ifnet structure */ 3669 ifp = &sc->ethercom.ec_if; 3670 ifp->if_softc = sc; 3671 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3672 ifp->if_ioctl = bge_ioctl; 3673 ifp->if_stop = bge_stop; 3674 ifp->if_start = bge_start; 3675 ifp->if_init = bge_init; 3676 ifp->if_watchdog = bge_watchdog; 3677 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3678 IFQ_SET_READY(&ifp->if_snd); 3679 DPRINTFN(5, ("strcpy if_xname\n")); 3680 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3681 3682 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3683 sc->ethercom.ec_if.if_capabilities |= 3684 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3685 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3686 sc->ethercom.ec_if.if_capabilities |= 3687 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3688 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3689 #endif 3690 sc->ethercom.ec_capabilities |= 3691 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3692 3693 if (sc->bge_flags & BGE_TSO) 3694 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3695 3696 /* 3697 * Do MII setup. 3698 */ 3699 DPRINTFN(5, ("mii setup\n")); 3700 sc->bge_mii.mii_ifp = ifp; 3701 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3702 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3703 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3704 3705 /* 3706 * Figure out what sort of media we have by checking the hardware 3707 * config word in the first 32k of NIC internal memory, or fall back to 3708 * the config word in the EEPROM. Note: on some BCM5700 cards, 3709 * this value appears to be unset. If that's the case, we have to rely 3710 * on identifying the NIC by its PCI subsystem ID, as we do below for 3711 * the SysKonnect SK-9D41. 3712 */ 3713 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) { 3714 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3715 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3716 bge_read_eeprom(sc, (void *)&hwcfg, 3717 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3718 hwcfg = be32toh(hwcfg); 3719 } 3720 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3721 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3722 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3723 if (BGE_IS_5714_FAMILY(sc)) 3724 sc->bge_flags |= BGE_PHY_FIBER_MII; 3725 else 3726 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3727 } 3728 3729 /* set phyflags and chipid before mii_attach() */ 3730 dict = device_properties(self); 3731 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3732 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3733 3734 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3735 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3736 bge_ifmedia_sts); 3737 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3738 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3739 0, NULL); 3740 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3741 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3742 /* Pretend the user requested this setting */ 3743 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3744 } else { 3745 /* 3746 * Do transceiver setup and tell the firmware the 3747 * driver is down so we can try to get access the 3748 * probe if ASF is running. Retry a couple of times 3749 * if we get a conflict with the ASF firmware accessing 3750 * the PHY. 3751 */ 3752 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3753 bge_asf_driver_up(sc); 3754 3755 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3756 bge_ifmedia_sts); 3757 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3758 sc->bge_phy_addr, MII_OFFSET_ANY, 3759 MIIF_DOPAUSE); 3760 3761 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3762 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3763 ifmedia_add(&sc->bge_mii.mii_media, 3764 IFM_ETHER|IFM_MANUAL, 0, NULL); 3765 ifmedia_set(&sc->bge_mii.mii_media, 3766 IFM_ETHER|IFM_MANUAL); 3767 } else 3768 ifmedia_set(&sc->bge_mii.mii_media, 3769 IFM_ETHER|IFM_AUTO); 3770 3771 /* 3772 * Now tell the firmware we are going up after probing the PHY 3773 */ 3774 if (sc->bge_asf_mode & ASF_STACKUP) 3775 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3776 } 3777 3778 /* 3779 * Call MI attach routine. 3780 */ 3781 DPRINTFN(5, ("if_attach\n")); 3782 if_attach(ifp); 3783 DPRINTFN(5, ("ether_ifattach\n")); 3784 ether_ifattach(ifp, eaddr); 3785 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3786 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3787 RND_TYPE_NET, 0); 3788 #ifdef BGE_EVENT_COUNTERS 3789 /* 3790 * Attach event counters. 3791 */ 3792 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3793 NULL, device_xname(sc->bge_dev), "intr"); 3794 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3795 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3796 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3797 NULL, device_xname(sc->bge_dev), "tx_xon"); 3798 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3799 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3800 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3801 NULL, device_xname(sc->bge_dev), "rx_xon"); 3802 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3803 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3804 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3805 NULL, device_xname(sc->bge_dev), "xoffentered"); 3806 #endif /* BGE_EVENT_COUNTERS */ 3807 DPRINTFN(5, ("callout_init\n")); 3808 callout_init(&sc->bge_timeout, 0); 3809 3810 if (pmf_device_register(self, NULL, NULL)) 3811 pmf_class_network_register(self, ifp); 3812 else 3813 aprint_error_dev(self, "couldn't establish power handler\n"); 3814 3815 bge_sysctl_init(sc); 3816 3817 #ifdef BGE_DEBUG 3818 bge_debug_info(sc); 3819 #endif 3820 } 3821 3822 /* 3823 * Stop all chip I/O so that the kernel's probe routines don't 3824 * get confused by errant DMAs when rebooting. 3825 */ 3826 static int 3827 bge_detach(device_t self, int flags __unused) 3828 { 3829 struct bge_softc *sc = device_private(self); 3830 struct ifnet *ifp = &sc->ethercom.ec_if; 3831 int s; 3832 3833 s = splnet(); 3834 /* Stop the interface. Callouts are stopped in it. */ 3835 bge_stop(ifp, 1); 3836 splx(s); 3837 3838 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3839 3840 /* Delete all remaining media. */ 3841 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3842 3843 ether_ifdetach(ifp); 3844 if_detach(ifp); 3845 3846 bge_release_resources(sc); 3847 3848 return 0; 3849 } 3850 3851 static void 3852 bge_release_resources(struct bge_softc *sc) 3853 { 3854 3855 /* Disestablish the interrupt handler */ 3856 if (sc->bge_intrhand != NULL) { 3857 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3858 sc->bge_intrhand = NULL; 3859 } 3860 3861 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3862 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3863 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3864 sizeof(struct bge_ring_data)); 3865 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3866 3867 /* Unmap the device registers */ 3868 if (sc->bge_bsize != 0) { 3869 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3870 sc->bge_bsize = 0; 3871 } 3872 3873 /* Unmap the APE registers */ 3874 if (sc->bge_apesize != 0) { 3875 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3876 sc->bge_apesize); 3877 sc->bge_apesize = 0; 3878 } 3879 } 3880 3881 static int 3882 bge_reset(struct bge_softc *sc) 3883 { 3884 uint32_t cachesize, command; 3885 uint32_t reset, mac_mode, mac_mode_mask; 3886 pcireg_t devctl, reg; 3887 int i, val; 3888 void (*write_op)(struct bge_softc *, int, int); 3889 3890 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3891 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3892 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3893 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3894 3895 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3896 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3897 if (sc->bge_flags & BGE_PCIE) 3898 write_op = bge_writemem_direct; 3899 else 3900 write_op = bge_writemem_ind; 3901 } else 3902 write_op = bge_writereg_ind; 3903 3904 #if 0 3905 if ((sc->bge_flags & BGE_NO_EEPROM) == 0 && 3906 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3907 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3908 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3909 for (i = 0; i < 8000; i++) { 3910 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3911 BGE_NVRAMSWARB_GNT1) 3912 break; 3913 DELAY(20); 3914 } 3915 if (i == 8000) { 3916 printf("%s: NVRAM lock timedout!\n", 3917 device_xname(sc->bge_dev)); 3918 } 3919 } 3920 #endif 3921 /* Take APE lock when performing reset. */ 3922 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3923 3924 /* Save some important PCI state. */ 3925 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3926 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3927 3928 /* Step 5b-5d: */ 3929 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3930 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3931 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3932 3933 /* XXX ???: Disable fastboot on controllers that support it. */ 3934 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3935 BGE_IS_5755_PLUS(sc)) 3936 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3937 3938 /* 3939 * Step 6: Write the magic number to SRAM at offset 0xB50. 3940 * When firmware finishes its initialization it will 3941 * write ~BGE_MAGIC_NUMBER to the same location. 3942 */ 3943 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3944 3945 /* Step 7: */ 3946 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3947 /* 3948 * XXX: from FreeBSD/Linux; no documentation 3949 */ 3950 if (sc->bge_flags & BGE_PCIE) { 3951 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 3952 !BGE_IS_57765_PLUS(sc) && 3953 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 3954 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 3955 /* PCI Express 1.0 system */ 3956 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 3957 BGE_PHY_PCIE_SCRAM_MODE); 3958 } 3959 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3960 /* 3961 * Prevent PCI Express link training 3962 * during global reset. 3963 */ 3964 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3965 reset |= (1 << 29); 3966 } 3967 } 3968 3969 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3970 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3971 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3972 i | BGE_VCPU_STATUS_DRV_RESET); 3973 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3974 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3975 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3976 } 3977 3978 /* 3979 * Set GPHY Power Down Override to leave GPHY 3980 * powered up in D0 uninitialized. 3981 */ 3982 if (BGE_IS_5705_PLUS(sc) && 3983 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3984 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3985 3986 /* Issue global reset */ 3987 write_op(sc, BGE_MISC_CFG, reset); 3988 3989 /* Step 8: wait for complete */ 3990 if (sc->bge_flags & BGE_PCIE) 3991 delay(100*1000); /* too big */ 3992 else 3993 delay(1000); 3994 3995 if (sc->bge_flags & BGE_PCIE) { 3996 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3997 DELAY(500000); 3998 /* XXX: Magic Numbers */ 3999 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4000 BGE_PCI_UNKNOWN0); 4001 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4002 BGE_PCI_UNKNOWN0, 4003 reg | (1 << 15)); 4004 } 4005 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4006 sc->bge_pciecap + PCI_PCIE_DCSR); 4007 /* Clear enable no snoop and disable relaxed ordering. */ 4008 devctl &= ~(PCI_PCIE_DCSR_ENA_RELAX_ORD | 4009 PCI_PCIE_DCSR_ENA_NO_SNOOP); 4010 4011 /* Set PCIE max payload size to 128 for older PCIe devices */ 4012 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4013 devctl &= ~(0x00e0); 4014 /* Clear device status register. Write 1b to clear */ 4015 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 4016 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 4017 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4018 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 4019 bge_set_max_readrq(sc); 4020 } 4021 4022 /* From Linux: dummy read to flush PCI posted writes */ 4023 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4024 4025 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 4026 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4027 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4028 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4029 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4030 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4031 (sc->bge_flags & BGE_PCIX) != 0) 4032 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4033 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4034 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4035 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4036 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4037 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4038 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4039 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4040 4041 /* Step 11: disable PCI-X Relaxed Ordering. */ 4042 if (sc->bge_flags & BGE_PCIX) { 4043 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4044 + PCI_PCIX_CMD); 4045 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4046 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 4047 } 4048 4049 /* Step 12: Enable memory arbiter. */ 4050 if (BGE_IS_5714_FAMILY(sc)) { 4051 val = CSR_READ_4(sc, BGE_MARB_MODE); 4052 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4053 } else 4054 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4055 4056 /* XXX 5721, 5751 and 5752 */ 4057 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4058 /* Step 19: */ 4059 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4060 /* Step 20: */ 4061 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4062 } 4063 4064 /* Step 28: Fix up byte swapping */ 4065 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4066 4067 /* 4068 * Wait for the bootcode to complete initialization. 4069 * See BCM5718 programmer's guide's "step 13, Device reset Procedure, 4070 * Section 7". 4071 */ 4072 if (BGE_IS_5717_PLUS(sc)) { 4073 for (i = 0; i < 1000*1000; i++) { 4074 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4075 if (val == BGE_SRAM_FW_MB_RESET_MAGIC) 4076 break; 4077 DELAY(10); 4078 } 4079 } 4080 4081 /* Step 21: 5822 B0 errata */ 4082 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4083 pcireg_t msidata; 4084 4085 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4086 BGE_PCI_MSI_DATA); 4087 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4088 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4089 msidata); 4090 } 4091 4092 /* 4093 * Step 18: wirte mac mode 4094 * XXX Write 0x0c for 5703S and 5704S 4095 */ 4096 val = CSR_READ_4(sc, BGE_MAC_MODE); 4097 val = (val & ~mac_mode_mask) | mac_mode; 4098 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4099 DELAY(40); 4100 4101 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4102 4103 /* Step 17: Poll until the firmware initialization is complete */ 4104 bge_poll_fw(sc); 4105 4106 /* 4107 * The 5704 in TBI mode apparently needs some special 4108 * adjustment to insure the SERDES drive level is set 4109 * to 1.2V. 4110 */ 4111 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4112 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4113 uint32_t serdescfg; 4114 4115 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4116 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4117 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4118 } 4119 4120 if (sc->bge_flags & BGE_PCIE && 4121 !BGE_IS_57765_PLUS(sc) && 4122 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4123 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4124 uint32_t v; 4125 4126 /* Enable PCI Express bug fix */ 4127 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4128 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4129 v | BGE_TLP_DATA_FIFO_PROTECT); 4130 } 4131 4132 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4133 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4134 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4135 4136 return 0; 4137 } 4138 4139 /* 4140 * Frame reception handling. This is called if there's a frame 4141 * on the receive return list. 4142 * 4143 * Note: we have to be able to handle two possibilities here: 4144 * 1) the frame is from the jumbo receive ring 4145 * 2) the frame is from the standard receive ring 4146 */ 4147 4148 static void 4149 bge_rxeof(struct bge_softc *sc) 4150 { 4151 struct ifnet *ifp; 4152 uint16_t rx_prod, rx_cons; 4153 int stdcnt = 0, jumbocnt = 0; 4154 bus_dmamap_t dmamap; 4155 bus_addr_t offset, toff; 4156 bus_size_t tlen; 4157 int tosync; 4158 4159 rx_cons = sc->bge_rx_saved_considx; 4160 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4161 4162 /* Nothing to do */ 4163 if (rx_cons == rx_prod) 4164 return; 4165 4166 ifp = &sc->ethercom.ec_if; 4167 4168 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4169 offsetof(struct bge_ring_data, bge_status_block), 4170 sizeof (struct bge_status_block), 4171 BUS_DMASYNC_POSTREAD); 4172 4173 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4174 tosync = rx_prod - rx_cons; 4175 4176 if (tosync != 0) 4177 rnd_add_uint32(&sc->rnd_source, tosync); 4178 4179 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4180 4181 if (tosync < 0) { 4182 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4183 sizeof (struct bge_rx_bd); 4184 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4185 toff, tlen, BUS_DMASYNC_POSTREAD); 4186 tosync = -tosync; 4187 } 4188 4189 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4190 offset, tosync * sizeof (struct bge_rx_bd), 4191 BUS_DMASYNC_POSTREAD); 4192 4193 while (rx_cons != rx_prod) { 4194 struct bge_rx_bd *cur_rx; 4195 uint32_t rxidx; 4196 struct mbuf *m = NULL; 4197 4198 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4199 4200 rxidx = cur_rx->bge_idx; 4201 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4202 4203 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4204 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4205 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4206 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4207 jumbocnt++; 4208 bus_dmamap_sync(sc->bge_dmatag, 4209 sc->bge_cdata.bge_rx_jumbo_map, 4210 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4211 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4212 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4213 ifp->if_ierrors++; 4214 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4215 continue; 4216 } 4217 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4218 NULL)== ENOBUFS) { 4219 ifp->if_ierrors++; 4220 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4221 continue; 4222 } 4223 } else { 4224 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4225 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4226 4227 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4228 stdcnt++; 4229 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4230 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4231 if (dmamap == NULL) { 4232 ifp->if_ierrors++; 4233 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4234 continue; 4235 } 4236 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4237 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4238 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4239 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4240 ifp->if_ierrors++; 4241 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4242 continue; 4243 } 4244 if (bge_newbuf_std(sc, sc->bge_std, 4245 NULL, dmamap) == ENOBUFS) { 4246 ifp->if_ierrors++; 4247 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4248 continue; 4249 } 4250 } 4251 4252 ifp->if_ipackets++; 4253 #ifndef __NO_STRICT_ALIGNMENT 4254 /* 4255 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4256 * the Rx buffer has the layer-2 header unaligned. 4257 * If our CPU requires alignment, re-align by copying. 4258 */ 4259 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4260 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4261 cur_rx->bge_len); 4262 m->m_data += ETHER_ALIGN; 4263 } 4264 #endif 4265 4266 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4267 m->m_pkthdr.rcvif = ifp; 4268 4269 /* 4270 * Handle BPF listeners. Let the BPF user see the packet. 4271 */ 4272 bpf_mtap(ifp, m); 4273 4274 bge_rxcsum(sc, cur_rx, m); 4275 4276 /* 4277 * If we received a packet with a vlan tag, pass it 4278 * to vlan_input() instead of ether_input(). 4279 */ 4280 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4281 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4282 } 4283 4284 (*ifp->if_input)(ifp, m); 4285 } 4286 4287 sc->bge_rx_saved_considx = rx_cons; 4288 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4289 if (stdcnt) 4290 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4291 if (jumbocnt) 4292 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4293 } 4294 4295 static void 4296 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4297 { 4298 4299 if (BGE_IS_5717_PLUS(sc)) { 4300 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4301 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4302 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4303 if ((cur_rx->bge_error_flag & 4304 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4305 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4306 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4307 m->m_pkthdr.csum_data = 4308 cur_rx->bge_tcp_udp_csum; 4309 m->m_pkthdr.csum_flags |= 4310 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4311 M_CSUM_DATA); 4312 } 4313 } 4314 } else { 4315 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4316 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4317 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4318 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4319 /* 4320 * Rx transport checksum-offload may also 4321 * have bugs with packets which, when transmitted, 4322 * were `runts' requiring padding. 4323 */ 4324 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4325 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4326 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4327 m->m_pkthdr.csum_data = 4328 cur_rx->bge_tcp_udp_csum; 4329 m->m_pkthdr.csum_flags |= 4330 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4331 M_CSUM_DATA); 4332 } 4333 } 4334 } 4335 4336 static void 4337 bge_txeof(struct bge_softc *sc) 4338 { 4339 struct bge_tx_bd *cur_tx = NULL; 4340 struct ifnet *ifp; 4341 struct txdmamap_pool_entry *dma; 4342 bus_addr_t offset, toff; 4343 bus_size_t tlen; 4344 int tosync; 4345 struct mbuf *m; 4346 4347 ifp = &sc->ethercom.ec_if; 4348 4349 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4350 offsetof(struct bge_ring_data, bge_status_block), 4351 sizeof (struct bge_status_block), 4352 BUS_DMASYNC_POSTREAD); 4353 4354 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4355 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4356 sc->bge_tx_saved_considx; 4357 4358 if (tosync != 0) 4359 rnd_add_uint32(&sc->rnd_source, tosync); 4360 4361 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4362 4363 if (tosync < 0) { 4364 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4365 sizeof (struct bge_tx_bd); 4366 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4367 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4368 tosync = -tosync; 4369 } 4370 4371 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4372 offset, tosync * sizeof (struct bge_tx_bd), 4373 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4374 4375 /* 4376 * Go through our tx ring and free mbufs for those 4377 * frames that have been sent. 4378 */ 4379 while (sc->bge_tx_saved_considx != 4380 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4381 uint32_t idx = 0; 4382 4383 idx = sc->bge_tx_saved_considx; 4384 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4385 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4386 ifp->if_opackets++; 4387 m = sc->bge_cdata.bge_tx_chain[idx]; 4388 if (m != NULL) { 4389 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4390 dma = sc->txdma[idx]; 4391 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4392 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4393 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4394 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4395 sc->txdma[idx] = NULL; 4396 4397 m_freem(m); 4398 } 4399 sc->bge_txcnt--; 4400 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4401 ifp->if_timer = 0; 4402 } 4403 4404 if (cur_tx != NULL) 4405 ifp->if_flags &= ~IFF_OACTIVE; 4406 } 4407 4408 static int 4409 bge_intr(void *xsc) 4410 { 4411 struct bge_softc *sc; 4412 struct ifnet *ifp; 4413 uint32_t statusword; 4414 4415 sc = xsc; 4416 ifp = &sc->ethercom.ec_if; 4417 4418 /* It is possible for the interrupt to arrive before 4419 * the status block is updated prior to the interrupt. 4420 * Reading the PCI State register will confirm whether the 4421 * interrupt is ours and will flush the status block. 4422 */ 4423 4424 /* read status word from status block */ 4425 statusword = sc->bge_rdata->bge_status_block.bge_status; 4426 4427 if ((statusword & BGE_STATFLAG_UPDATED) || 4428 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 4429 /* Ack interrupt and stop others from occuring. */ 4430 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4431 4432 BGE_EVCNT_INCR(sc->bge_ev_intr); 4433 4434 /* clear status word */ 4435 sc->bge_rdata->bge_status_block.bge_status = 0; 4436 4437 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4438 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4439 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4440 bge_link_upd(sc); 4441 4442 if (ifp->if_flags & IFF_RUNNING) { 4443 /* Check RX return ring producer/consumer */ 4444 bge_rxeof(sc); 4445 4446 /* Check TX ring producer/consumer */ 4447 bge_txeof(sc); 4448 } 4449 4450 if (sc->bge_pending_rxintr_change) { 4451 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4452 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4453 uint32_t junk; 4454 4455 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4456 DELAY(10); 4457 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4458 4459 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4460 DELAY(10); 4461 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4462 4463 sc->bge_pending_rxintr_change = 0; 4464 } 4465 bge_handle_events(sc); 4466 4467 /* Re-enable interrupts. */ 4468 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4469 4470 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4471 bge_start(ifp); 4472 4473 return 1; 4474 } else 4475 return 0; 4476 } 4477 4478 static void 4479 bge_asf_driver_up(struct bge_softc *sc) 4480 { 4481 if (sc->bge_asf_mode & ASF_STACKUP) { 4482 /* Send ASF heartbeat aprox. every 2s */ 4483 if (sc->bge_asf_count) 4484 sc->bge_asf_count --; 4485 else { 4486 sc->bge_asf_count = 2; 4487 4488 bge_wait_for_event_ack(sc); 4489 4490 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4491 BGE_FW_CMD_DRV_ALIVE); 4492 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4493 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4494 BGE_FW_HB_TIMEOUT_SEC); 4495 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4496 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4497 BGE_RX_CPU_DRV_EVENT); 4498 } 4499 } 4500 } 4501 4502 static void 4503 bge_tick(void *xsc) 4504 { 4505 struct bge_softc *sc = xsc; 4506 struct mii_data *mii = &sc->bge_mii; 4507 int s; 4508 4509 s = splnet(); 4510 4511 if (BGE_IS_5705_PLUS(sc)) 4512 bge_stats_update_regs(sc); 4513 else 4514 bge_stats_update(sc); 4515 4516 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4517 /* 4518 * Since in TBI mode auto-polling can't be used we should poll 4519 * link status manually. Here we register pending link event 4520 * and trigger interrupt. 4521 */ 4522 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4523 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4524 } else { 4525 /* 4526 * Do not touch PHY if we have link up. This could break 4527 * IPMI/ASF mode or produce extra input errors. 4528 * (extra input errors was reported for bcm5701 & bcm5704). 4529 */ 4530 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4531 mii_tick(mii); 4532 } 4533 4534 bge_asf_driver_up(sc); 4535 4536 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4537 4538 splx(s); 4539 } 4540 4541 static void 4542 bge_stats_update_regs(struct bge_softc *sc) 4543 { 4544 struct ifnet *ifp = &sc->ethercom.ec_if; 4545 4546 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4547 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4548 4549 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4550 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4551 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4552 } 4553 4554 static void 4555 bge_stats_update(struct bge_softc *sc) 4556 { 4557 struct ifnet *ifp = &sc->ethercom.ec_if; 4558 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4559 4560 #define READ_STAT(sc, stats, stat) \ 4561 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4562 4563 ifp->if_collisions += 4564 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4565 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4566 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4567 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4568 ifp->if_collisions; 4569 4570 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4571 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4572 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4573 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4574 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4575 READ_STAT(sc, stats, 4576 xoffPauseFramesReceived.bge_addr_lo)); 4577 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4578 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4579 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4580 READ_STAT(sc, stats, 4581 macControlFramesReceived.bge_addr_lo)); 4582 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4583 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4584 4585 #undef READ_STAT 4586 4587 #ifdef notdef 4588 ifp->if_collisions += 4589 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4590 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4591 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4592 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4593 ifp->if_collisions; 4594 #endif 4595 } 4596 4597 /* 4598 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4599 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4600 * but when such padded frames employ the bge IP/TCP checksum offload, 4601 * the hardware checksum assist gives incorrect results (possibly 4602 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4603 * If we pad such runts with zeros, the onboard checksum comes out correct. 4604 */ 4605 static inline int 4606 bge_cksum_pad(struct mbuf *pkt) 4607 { 4608 struct mbuf *last = NULL; 4609 int padlen; 4610 4611 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4612 4613 /* if there's only the packet-header and we can pad there, use it. */ 4614 if (pkt->m_pkthdr.len == pkt->m_len && 4615 M_TRAILINGSPACE(pkt) >= padlen) { 4616 last = pkt; 4617 } else { 4618 /* 4619 * Walk packet chain to find last mbuf. We will either 4620 * pad there, or append a new mbuf and pad it 4621 * (thus perhaps avoiding the bcm5700 dma-min bug). 4622 */ 4623 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4624 continue; /* do nothing */ 4625 } 4626 4627 /* `last' now points to last in chain. */ 4628 if (M_TRAILINGSPACE(last) < padlen) { 4629 /* Allocate new empty mbuf, pad it. Compact later. */ 4630 struct mbuf *n; 4631 MGET(n, M_DONTWAIT, MT_DATA); 4632 if (n == NULL) 4633 return ENOBUFS; 4634 n->m_len = 0; 4635 last->m_next = n; 4636 last = n; 4637 } 4638 } 4639 4640 KDASSERT(!M_READONLY(last)); 4641 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4642 4643 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4644 memset(mtod(last, char *) + last->m_len, 0, padlen); 4645 last->m_len += padlen; 4646 pkt->m_pkthdr.len += padlen; 4647 return 0; 4648 } 4649 4650 /* 4651 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4652 */ 4653 static inline int 4654 bge_compact_dma_runt(struct mbuf *pkt) 4655 { 4656 struct mbuf *m, *prev; 4657 int totlen, prevlen; 4658 4659 prev = NULL; 4660 totlen = 0; 4661 prevlen = -1; 4662 4663 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4664 int mlen = m->m_len; 4665 int shortfall = 8 - mlen ; 4666 4667 totlen += mlen; 4668 if (mlen == 0) 4669 continue; 4670 if (mlen >= 8) 4671 continue; 4672 4673 /* If we get here, mbuf data is too small for DMA engine. 4674 * Try to fix by shuffling data to prev or next in chain. 4675 * If that fails, do a compacting deep-copy of the whole chain. 4676 */ 4677 4678 /* Internal frag. If fits in prev, copy it there. */ 4679 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4680 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4681 prev->m_len += mlen; 4682 m->m_len = 0; 4683 /* XXX stitch chain */ 4684 prev->m_next = m_free(m); 4685 m = prev; 4686 continue; 4687 } 4688 else if (m->m_next != NULL && 4689 M_TRAILINGSPACE(m) >= shortfall && 4690 m->m_next->m_len >= (8 + shortfall)) { 4691 /* m is writable and have enough data in next, pull up. */ 4692 4693 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4694 shortfall); 4695 m->m_len += shortfall; 4696 m->m_next->m_len -= shortfall; 4697 m->m_next->m_data += shortfall; 4698 } 4699 else if (m->m_next == NULL || 1) { 4700 /* Got a runt at the very end of the packet. 4701 * borrow data from the tail of the preceding mbuf and 4702 * update its length in-place. (The original data is still 4703 * valid, so we can do this even if prev is not writable.) 4704 */ 4705 4706 /* if we'd make prev a runt, just move all of its data. */ 4707 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4708 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4709 4710 if ((prev->m_len - shortfall) < 8) 4711 shortfall = prev->m_len; 4712 4713 #ifdef notyet /* just do the safe slow thing for now */ 4714 if (!M_READONLY(m)) { 4715 if (M_LEADINGSPACE(m) < shorfall) { 4716 void *m_dat; 4717 m_dat = (m->m_flags & M_PKTHDR) ? 4718 m->m_pktdat : m->dat; 4719 memmove(m_dat, mtod(m, void*), m->m_len); 4720 m->m_data = m_dat; 4721 } 4722 } else 4723 #endif /* just do the safe slow thing */ 4724 { 4725 struct mbuf * n = NULL; 4726 int newprevlen = prev->m_len - shortfall; 4727 4728 MGET(n, M_NOWAIT, MT_DATA); 4729 if (n == NULL) 4730 return ENOBUFS; 4731 KASSERT(m->m_len + shortfall < MLEN 4732 /*, 4733 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4734 4735 /* first copy the data we're stealing from prev */ 4736 memcpy(n->m_data, prev->m_data + newprevlen, 4737 shortfall); 4738 4739 /* update prev->m_len accordingly */ 4740 prev->m_len -= shortfall; 4741 4742 /* copy data from runt m */ 4743 memcpy(n->m_data + shortfall, m->m_data, 4744 m->m_len); 4745 4746 /* n holds what we stole from prev, plus m */ 4747 n->m_len = shortfall + m->m_len; 4748 4749 /* stitch n into chain and free m */ 4750 n->m_next = m->m_next; 4751 prev->m_next = n; 4752 /* KASSERT(m->m_next == NULL); */ 4753 m->m_next = NULL; 4754 m_free(m); 4755 m = n; /* for continuing loop */ 4756 } 4757 } 4758 prevlen = m->m_len; 4759 } 4760 return 0; 4761 } 4762 4763 /* 4764 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4765 * pointers to descriptors. 4766 */ 4767 static int 4768 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4769 { 4770 struct bge_tx_bd *f = NULL; 4771 uint32_t frag, cur; 4772 uint16_t csum_flags = 0; 4773 uint16_t txbd_tso_flags = 0; 4774 struct txdmamap_pool_entry *dma; 4775 bus_dmamap_t dmamap; 4776 int i = 0; 4777 struct m_tag *mtag; 4778 int use_tso, maxsegsize, error; 4779 4780 cur = frag = *txidx; 4781 4782 if (m_head->m_pkthdr.csum_flags) { 4783 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4784 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4785 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4786 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4787 } 4788 4789 /* 4790 * If we were asked to do an outboard checksum, and the NIC 4791 * has the bug where it sometimes adds in the Ethernet padding, 4792 * explicitly pad with zeros so the cksum will be correct either way. 4793 * (For now, do this for all chip versions, until newer 4794 * are confirmed to not require the workaround.) 4795 */ 4796 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4797 #ifdef notyet 4798 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4799 #endif 4800 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4801 goto check_dma_bug; 4802 4803 if (bge_cksum_pad(m_head) != 0) 4804 return ENOBUFS; 4805 4806 check_dma_bug: 4807 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4808 goto doit; 4809 4810 /* 4811 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4812 * less than eight bytes. If we encounter a teeny mbuf 4813 * at the end of a chain, we can pad. Otherwise, copy. 4814 */ 4815 if (bge_compact_dma_runt(m_head) != 0) 4816 return ENOBUFS; 4817 4818 doit: 4819 dma = SLIST_FIRST(&sc->txdma_list); 4820 if (dma == NULL) 4821 return ENOBUFS; 4822 dmamap = dma->dmamap; 4823 4824 /* 4825 * Set up any necessary TSO state before we start packing... 4826 */ 4827 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4828 if (!use_tso) { 4829 maxsegsize = 0; 4830 } else { /* TSO setup */ 4831 unsigned mss; 4832 struct ether_header *eh; 4833 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4834 struct mbuf * m0 = m_head; 4835 struct ip *ip; 4836 struct tcphdr *th; 4837 int iphl, hlen; 4838 4839 /* 4840 * XXX It would be nice if the mbuf pkthdr had offset 4841 * fields for the protocol headers. 4842 */ 4843 4844 eh = mtod(m0, struct ether_header *); 4845 switch (htons(eh->ether_type)) { 4846 case ETHERTYPE_IP: 4847 offset = ETHER_HDR_LEN; 4848 break; 4849 4850 case ETHERTYPE_VLAN: 4851 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4852 break; 4853 4854 default: 4855 /* 4856 * Don't support this protocol or encapsulation. 4857 */ 4858 return ENOBUFS; 4859 } 4860 4861 /* 4862 * TCP/IP headers are in the first mbuf; we can do 4863 * this the easy way. 4864 */ 4865 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4866 hlen = iphl + offset; 4867 if (__predict_false(m0->m_len < 4868 (hlen + sizeof(struct tcphdr)))) { 4869 4870 aprint_debug_dev(sc->bge_dev, 4871 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4872 "not handled yet\n", 4873 m0->m_len, hlen+ sizeof(struct tcphdr)); 4874 #ifdef NOTYET 4875 /* 4876 * XXX jonathan (at) NetBSD.org: untested. 4877 * how to force this branch to be taken? 4878 */ 4879 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4880 4881 m_copydata(m0, offset, sizeof(ip), &ip); 4882 m_copydata(m0, hlen, sizeof(th), &th); 4883 4884 ip.ip_len = 0; 4885 4886 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4887 sizeof(ip.ip_len), &ip.ip_len); 4888 4889 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4890 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4891 4892 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4893 sizeof(th.th_sum), &th.th_sum); 4894 4895 hlen += th.th_off << 2; 4896 iptcp_opt_words = hlen; 4897 #else 4898 /* 4899 * if_wm "hard" case not yet supported, can we not 4900 * mandate it out of existence? 4901 */ 4902 (void) ip; (void)th; (void) ip_tcp_hlen; 4903 4904 return ENOBUFS; 4905 #endif 4906 } else { 4907 ip = (struct ip *) (mtod(m0, char *) + offset); 4908 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4909 ip_tcp_hlen = iphl + (th->th_off << 2); 4910 4911 /* Total IP/TCP options, in 32-bit words */ 4912 iptcp_opt_words = (ip_tcp_hlen 4913 - sizeof(struct tcphdr) 4914 - sizeof(struct ip)) >> 2; 4915 } 4916 if (BGE_IS_575X_PLUS(sc)) { 4917 th->th_sum = 0; 4918 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4919 } else { 4920 /* 4921 * XXX jonathan (at) NetBSD.org: 5705 untested. 4922 * Requires TSO firmware patch for 5701/5703/5704. 4923 */ 4924 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4925 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4926 } 4927 4928 mss = m_head->m_pkthdr.segsz; 4929 txbd_tso_flags |= 4930 BGE_TXBDFLAG_CPU_PRE_DMA | 4931 BGE_TXBDFLAG_CPU_POST_DMA; 4932 4933 /* 4934 * Our NIC TSO-assist assumes TSO has standard, optionless 4935 * IPv4 and TCP headers, which total 40 bytes. By default, 4936 * the NIC copies 40 bytes of IP/TCP header from the 4937 * supplied header into the IP/TCP header portion of 4938 * each post-TSO-segment. If the supplied packet has IP or 4939 * TCP options, we need to tell the NIC to copy those extra 4940 * bytes into each post-TSO header, in addition to the normal 4941 * 40-byte IP/TCP header (and to leave space accordingly). 4942 * Unfortunately, the driver encoding of option length 4943 * varies across different ASIC families. 4944 */ 4945 tcp_seg_flags = 0; 4946 if (iptcp_opt_words) { 4947 if (BGE_IS_5705_PLUS(sc)) { 4948 tcp_seg_flags = 4949 iptcp_opt_words << 11; 4950 } else { 4951 txbd_tso_flags |= 4952 iptcp_opt_words << 12; 4953 } 4954 } 4955 maxsegsize = mss | tcp_seg_flags; 4956 ip->ip_len = htons(mss + ip_tcp_hlen); 4957 4958 } /* TSO setup */ 4959 4960 /* 4961 * Start packing the mbufs in this chain into 4962 * the fragment pointers. Stop when we run out 4963 * of fragments or hit the end of the mbuf chain. 4964 */ 4965 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4966 BUS_DMA_NOWAIT); 4967 if (error) 4968 return ENOBUFS; 4969 /* 4970 * Sanity check: avoid coming within 16 descriptors 4971 * of the end of the ring. 4972 */ 4973 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4974 BGE_TSO_PRINTF(("%s: " 4975 " dmamap_load_mbuf too close to ring wrap\n", 4976 device_xname(sc->bge_dev))); 4977 goto fail_unload; 4978 } 4979 4980 mtag = sc->ethercom.ec_nvlans ? 4981 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4982 4983 4984 /* Iterate over dmap-map fragments. */ 4985 for (i = 0; i < dmamap->dm_nsegs; i++) { 4986 f = &sc->bge_rdata->bge_tx_ring[frag]; 4987 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4988 break; 4989 4990 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4991 f->bge_len = dmamap->dm_segs[i].ds_len; 4992 4993 /* 4994 * For 5751 and follow-ons, for TSO we must turn 4995 * off checksum-assist flag in the tx-descr, and 4996 * supply the ASIC-revision-specific encoding 4997 * of TSO flags and segsize. 4998 */ 4999 if (use_tso) { 5000 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5001 f->bge_rsvd = maxsegsize; 5002 f->bge_flags = csum_flags | txbd_tso_flags; 5003 } else { 5004 f->bge_rsvd = 0; 5005 f->bge_flags = 5006 (csum_flags | txbd_tso_flags) & 0x0fff; 5007 } 5008 } else { 5009 f->bge_rsvd = 0; 5010 f->bge_flags = csum_flags; 5011 } 5012 5013 if (mtag != NULL) { 5014 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5015 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5016 } else { 5017 f->bge_vlan_tag = 0; 5018 } 5019 cur = frag; 5020 BGE_INC(frag, BGE_TX_RING_CNT); 5021 } 5022 5023 if (i < dmamap->dm_nsegs) { 5024 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5025 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5026 goto fail_unload; 5027 } 5028 5029 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5030 BUS_DMASYNC_PREWRITE); 5031 5032 if (frag == sc->bge_tx_saved_considx) { 5033 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5034 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5035 5036 goto fail_unload; 5037 } 5038 5039 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5040 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5041 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5042 sc->txdma[cur] = dma; 5043 sc->bge_txcnt += dmamap->dm_nsegs; 5044 5045 *txidx = frag; 5046 5047 return 0; 5048 5049 fail_unload: 5050 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5051 5052 return ENOBUFS; 5053 } 5054 5055 /* 5056 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5057 * to the mbuf data regions directly in the transmit descriptors. 5058 */ 5059 static void 5060 bge_start(struct ifnet *ifp) 5061 { 5062 struct bge_softc *sc; 5063 struct mbuf *m_head = NULL; 5064 uint32_t prodidx; 5065 int pkts = 0; 5066 5067 sc = ifp->if_softc; 5068 5069 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5070 return; 5071 5072 prodidx = sc->bge_tx_prodidx; 5073 5074 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5075 IFQ_POLL(&ifp->if_snd, m_head); 5076 if (m_head == NULL) 5077 break; 5078 5079 #if 0 5080 /* 5081 * XXX 5082 * safety overkill. If this is a fragmented packet chain 5083 * with delayed TCP/UDP checksums, then only encapsulate 5084 * it if we have enough descriptors to handle the entire 5085 * chain at once. 5086 * (paranoia -- may not actually be needed) 5087 */ 5088 if (m_head->m_flags & M_FIRSTFRAG && 5089 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5090 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5091 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5092 ifp->if_flags |= IFF_OACTIVE; 5093 break; 5094 } 5095 } 5096 #endif 5097 5098 /* 5099 * Pack the data into the transmit ring. If we 5100 * don't have room, set the OACTIVE flag and wait 5101 * for the NIC to drain the ring. 5102 */ 5103 if (bge_encap(sc, m_head, &prodidx)) { 5104 ifp->if_flags |= IFF_OACTIVE; 5105 break; 5106 } 5107 5108 /* now we are committed to transmit the packet */ 5109 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5110 pkts++; 5111 5112 /* 5113 * If there's a BPF listener, bounce a copy of this frame 5114 * to him. 5115 */ 5116 bpf_mtap(ifp, m_head); 5117 } 5118 if (pkts == 0) 5119 return; 5120 5121 /* Transmit */ 5122 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5123 /* 5700 b2 errata */ 5124 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5125 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5126 5127 sc->bge_tx_prodidx = prodidx; 5128 5129 /* 5130 * Set a timeout in case the chip goes out to lunch. 5131 */ 5132 ifp->if_timer = 5; 5133 } 5134 5135 static int 5136 bge_init(struct ifnet *ifp) 5137 { 5138 struct bge_softc *sc = ifp->if_softc; 5139 const uint16_t *m; 5140 uint32_t mode; 5141 int s, error = 0; 5142 5143 s = splnet(); 5144 5145 ifp = &sc->ethercom.ec_if; 5146 5147 /* Cancel pending I/O and flush buffers. */ 5148 bge_stop(ifp, 0); 5149 5150 bge_stop_fw(sc); 5151 bge_sig_pre_reset(sc, BGE_RESET_START); 5152 bge_reset(sc); 5153 bge_sig_legacy(sc, BGE_RESET_START); 5154 bge_sig_post_reset(sc, BGE_RESET_START); 5155 5156 bge_chipinit(sc); 5157 5158 /* 5159 * Init the various state machines, ring 5160 * control blocks and firmware. 5161 */ 5162 error = bge_blockinit(sc); 5163 if (error != 0) { 5164 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5165 error); 5166 splx(s); 5167 return error; 5168 } 5169 5170 ifp = &sc->ethercom.ec_if; 5171 5172 /* Specify MTU. */ 5173 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5174 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5175 5176 /* Load our MAC address. */ 5177 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5178 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5179 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5180 5181 /* Enable or disable promiscuous mode as needed. */ 5182 if (ifp->if_flags & IFF_PROMISC) 5183 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5184 else 5185 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5186 5187 /* Program multicast filter. */ 5188 bge_setmulti(sc); 5189 5190 /* Init RX ring. */ 5191 bge_init_rx_ring_std(sc); 5192 5193 /* 5194 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5195 * memory to insure that the chip has in fact read the first 5196 * entry of the ring. 5197 */ 5198 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5199 uint32_t v, i; 5200 for (i = 0; i < 10; i++) { 5201 DELAY(20); 5202 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5203 if (v == (MCLBYTES - ETHER_ALIGN)) 5204 break; 5205 } 5206 if (i == 10) 5207 aprint_error_dev(sc->bge_dev, 5208 "5705 A0 chip failed to load RX ring\n"); 5209 } 5210 5211 /* Init jumbo RX ring. */ 5212 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5213 bge_init_rx_ring_jumbo(sc); 5214 5215 /* Init our RX return ring index */ 5216 sc->bge_rx_saved_considx = 0; 5217 5218 /* Init TX ring. */ 5219 bge_init_tx_ring(sc); 5220 5221 /* Enable TX MAC state machine lockup fix. */ 5222 mode = CSR_READ_4(sc, BGE_TX_MODE); 5223 if (BGE_IS_5755_PLUS(sc) || 5224 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5225 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5226 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5227 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5228 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5229 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5230 } 5231 5232 /* Turn on transmitter */ 5233 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5234 DELAY(100); 5235 5236 /* Turn on receiver */ 5237 mode = CSR_READ_4(sc, BGE_RX_MODE); 5238 if (BGE_IS_5755_PLUS(sc)) 5239 mode |= BGE_RXMODE_IPV6_ENABLE; 5240 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5241 DELAY(10); 5242 5243 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5244 5245 /* Tell firmware we're alive. */ 5246 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5247 5248 /* Enable host interrupts. */ 5249 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5250 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5251 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5252 5253 if ((error = bge_ifmedia_upd(ifp)) != 0) 5254 goto out; 5255 5256 ifp->if_flags |= IFF_RUNNING; 5257 ifp->if_flags &= ~IFF_OACTIVE; 5258 5259 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5260 5261 out: 5262 sc->bge_if_flags = ifp->if_flags; 5263 splx(s); 5264 5265 return error; 5266 } 5267 5268 /* 5269 * Set media options. 5270 */ 5271 static int 5272 bge_ifmedia_upd(struct ifnet *ifp) 5273 { 5274 struct bge_softc *sc = ifp->if_softc; 5275 struct mii_data *mii = &sc->bge_mii; 5276 struct ifmedia *ifm = &sc->bge_ifmedia; 5277 int rc; 5278 5279 /* If this is a 1000baseX NIC, enable the TBI port. */ 5280 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5281 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5282 return EINVAL; 5283 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5284 case IFM_AUTO: 5285 /* 5286 * The BCM5704 ASIC appears to have a special 5287 * mechanism for programming the autoneg 5288 * advertisement registers in TBI mode. 5289 */ 5290 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5291 uint32_t sgdig; 5292 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5293 if (sgdig & BGE_SGDIGSTS_DONE) { 5294 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5295 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5296 sgdig |= BGE_SGDIGCFG_AUTO | 5297 BGE_SGDIGCFG_PAUSE_CAP | 5298 BGE_SGDIGCFG_ASYM_PAUSE; 5299 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5300 sgdig | BGE_SGDIGCFG_SEND); 5301 DELAY(5); 5302 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5303 sgdig); 5304 } 5305 } 5306 break; 5307 case IFM_1000_SX: 5308 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5309 BGE_CLRBIT(sc, BGE_MAC_MODE, 5310 BGE_MACMODE_HALF_DUPLEX); 5311 } else { 5312 BGE_SETBIT(sc, BGE_MAC_MODE, 5313 BGE_MACMODE_HALF_DUPLEX); 5314 } 5315 DELAY(40); 5316 break; 5317 default: 5318 return EINVAL; 5319 } 5320 /* XXX 802.3x flow control for 1000BASE-SX */ 5321 return 0; 5322 } 5323 5324 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5325 if ((rc = mii_mediachg(mii)) == ENXIO) 5326 return 0; 5327 5328 /* 5329 * Force an interrupt so that we will call bge_link_upd 5330 * if needed and clear any pending link state attention. 5331 * Without this we are not getting any further interrupts 5332 * for link state changes and thus will not UP the link and 5333 * not be able to send in bge_start. The only way to get 5334 * things working was to receive a packet and get a RX intr. 5335 */ 5336 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5337 sc->bge_flags & BGE_IS_5788) 5338 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5339 else 5340 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5341 5342 return rc; 5343 } 5344 5345 /* 5346 * Report current media status. 5347 */ 5348 static void 5349 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5350 { 5351 struct bge_softc *sc = ifp->if_softc; 5352 struct mii_data *mii = &sc->bge_mii; 5353 5354 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5355 ifmr->ifm_status = IFM_AVALID; 5356 ifmr->ifm_active = IFM_ETHER; 5357 if (CSR_READ_4(sc, BGE_MAC_STS) & 5358 BGE_MACSTAT_TBI_PCS_SYNCHED) 5359 ifmr->ifm_status |= IFM_ACTIVE; 5360 ifmr->ifm_active |= IFM_1000_SX; 5361 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5362 ifmr->ifm_active |= IFM_HDX; 5363 else 5364 ifmr->ifm_active |= IFM_FDX; 5365 return; 5366 } 5367 5368 mii_pollstat(mii); 5369 ifmr->ifm_status = mii->mii_media_status; 5370 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5371 sc->bge_flowflags; 5372 } 5373 5374 static int 5375 bge_ifflags_cb(struct ethercom *ec) 5376 { 5377 struct ifnet *ifp = &ec->ec_if; 5378 struct bge_softc *sc = ifp->if_softc; 5379 int change = ifp->if_flags ^ sc->bge_if_flags; 5380 5381 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5382 return ENETRESET; 5383 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5384 return 0; 5385 5386 if ((ifp->if_flags & IFF_PROMISC) == 0) 5387 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5388 else 5389 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5390 5391 bge_setmulti(sc); 5392 5393 sc->bge_if_flags = ifp->if_flags; 5394 return 0; 5395 } 5396 5397 static int 5398 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5399 { 5400 struct bge_softc *sc = ifp->if_softc; 5401 struct ifreq *ifr = (struct ifreq *) data; 5402 int s, error = 0; 5403 struct mii_data *mii; 5404 5405 s = splnet(); 5406 5407 switch (command) { 5408 case SIOCSIFMEDIA: 5409 /* XXX Flow control is not supported for 1000BASE-SX */ 5410 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5411 ifr->ifr_media &= ~IFM_ETH_FMASK; 5412 sc->bge_flowflags = 0; 5413 } 5414 5415 /* Flow control requires full-duplex mode. */ 5416 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5417 (ifr->ifr_media & IFM_FDX) == 0) { 5418 ifr->ifr_media &= ~IFM_ETH_FMASK; 5419 } 5420 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5421 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5422 /* We can do both TXPAUSE and RXPAUSE. */ 5423 ifr->ifr_media |= 5424 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5425 } 5426 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5427 } 5428 /* FALLTHROUGH */ 5429 case SIOCGIFMEDIA: 5430 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5431 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5432 command); 5433 } else { 5434 mii = &sc->bge_mii; 5435 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5436 command); 5437 } 5438 break; 5439 default: 5440 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5441 break; 5442 5443 error = 0; 5444 5445 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5446 ; 5447 else if (ifp->if_flags & IFF_RUNNING) 5448 bge_setmulti(sc); 5449 break; 5450 } 5451 5452 splx(s); 5453 5454 return error; 5455 } 5456 5457 static void 5458 bge_watchdog(struct ifnet *ifp) 5459 { 5460 struct bge_softc *sc; 5461 5462 sc = ifp->if_softc; 5463 5464 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5465 5466 ifp->if_flags &= ~IFF_RUNNING; 5467 bge_init(ifp); 5468 5469 ifp->if_oerrors++; 5470 } 5471 5472 static void 5473 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5474 { 5475 int i; 5476 5477 BGE_CLRBIT_FLUSH(sc, reg, bit); 5478 5479 for (i = 0; i < 1000; i++) { 5480 delay(100); 5481 if ((CSR_READ_4(sc, reg) & bit) == 0) 5482 return; 5483 } 5484 5485 /* 5486 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5487 * on some environment (and once after boot?) 5488 */ 5489 if (reg != BGE_SRS_MODE) 5490 aprint_error_dev(sc->bge_dev, 5491 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5492 (u_long)reg, bit); 5493 } 5494 5495 /* 5496 * Stop the adapter and free any mbufs allocated to the 5497 * RX and TX lists. 5498 */ 5499 static void 5500 bge_stop(struct ifnet *ifp, int disable) 5501 { 5502 struct bge_softc *sc = ifp->if_softc; 5503 5504 callout_stop(&sc->bge_timeout); 5505 5506 /* Disable host interrupts. */ 5507 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5508 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5509 5510 /* 5511 * Tell firmware we're shutting down. 5512 */ 5513 bge_stop_fw(sc); 5514 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5515 5516 /* 5517 * Disable all of the receiver blocks. 5518 */ 5519 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5520 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5521 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5522 if (BGE_IS_5700_FAMILY(sc)) 5523 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5524 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5525 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5526 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5527 5528 /* 5529 * Disable all of the transmit blocks. 5530 */ 5531 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5532 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5533 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5534 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5535 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5536 if (BGE_IS_5700_FAMILY(sc)) 5537 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5538 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5539 5540 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5541 delay(40); 5542 5543 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5544 5545 /* 5546 * Shut down all of the memory managers and related 5547 * state machines. 5548 */ 5549 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5550 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5551 if (BGE_IS_5700_FAMILY(sc)) 5552 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5553 5554 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5555 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5556 5557 if (BGE_IS_5700_FAMILY(sc)) { 5558 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5559 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5560 } 5561 5562 bge_reset(sc); 5563 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5564 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5565 5566 /* 5567 * Keep the ASF firmware running if up. 5568 */ 5569 if (sc->bge_asf_mode & ASF_STACKUP) 5570 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5571 else 5572 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5573 5574 /* Free the RX lists. */ 5575 bge_free_rx_ring_std(sc); 5576 5577 /* Free jumbo RX list. */ 5578 if (BGE_IS_JUMBO_CAPABLE(sc)) 5579 bge_free_rx_ring_jumbo(sc); 5580 5581 /* Free TX buffers. */ 5582 bge_free_tx_ring(sc); 5583 5584 /* 5585 * Isolate/power down the PHY. 5586 */ 5587 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5588 mii_down(&sc->bge_mii); 5589 5590 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5591 5592 /* Clear MAC's link state (PHY may still have link UP). */ 5593 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5594 5595 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5596 } 5597 5598 static void 5599 bge_link_upd(struct bge_softc *sc) 5600 { 5601 struct ifnet *ifp = &sc->ethercom.ec_if; 5602 struct mii_data *mii = &sc->bge_mii; 5603 uint32_t status; 5604 int link; 5605 5606 /* Clear 'pending link event' flag */ 5607 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5608 5609 /* 5610 * Process link state changes. 5611 * Grrr. The link status word in the status block does 5612 * not work correctly on the BCM5700 rev AX and BX chips, 5613 * according to all available information. Hence, we have 5614 * to enable MII interrupts in order to properly obtain 5615 * async link changes. Unfortunately, this also means that 5616 * we have to read the MAC status register to detect link 5617 * changes, thereby adding an additional register access to 5618 * the interrupt handler. 5619 */ 5620 5621 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5622 status = CSR_READ_4(sc, BGE_MAC_STS); 5623 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5624 mii_pollstat(mii); 5625 5626 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5627 mii->mii_media_status & IFM_ACTIVE && 5628 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5629 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5630 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5631 (!(mii->mii_media_status & IFM_ACTIVE) || 5632 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5633 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5634 5635 /* Clear the interrupt */ 5636 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5637 BGE_EVTENB_MI_INTERRUPT); 5638 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5639 BRGPHY_MII_ISR); 5640 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5641 BRGPHY_MII_IMR, BRGPHY_INTRS); 5642 } 5643 return; 5644 } 5645 5646 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5647 status = CSR_READ_4(sc, BGE_MAC_STS); 5648 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5649 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5650 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5651 if (BGE_ASICREV(sc->bge_chipid) 5652 == BGE_ASICREV_BCM5704) { 5653 BGE_CLRBIT(sc, BGE_MAC_MODE, 5654 BGE_MACMODE_TBI_SEND_CFGS); 5655 DELAY(40); 5656 } 5657 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5658 if_link_state_change(ifp, LINK_STATE_UP); 5659 } 5660 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5661 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5662 if_link_state_change(ifp, LINK_STATE_DOWN); 5663 } 5664 /* 5665 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5666 * This should not happen since mii callouts are locked now, but 5667 * we keep this check for debug. 5668 */ 5669 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5670 /* 5671 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5672 * bit in status word always set. Workaround this bug by 5673 * reading PHY link status directly. 5674 */ 5675 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5676 BGE_STS_LINK : 0; 5677 5678 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5679 mii_pollstat(mii); 5680 5681 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5682 mii->mii_media_status & IFM_ACTIVE && 5683 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5684 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5685 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5686 (!(mii->mii_media_status & IFM_ACTIVE) || 5687 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5688 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5689 } 5690 } 5691 5692 /* Clear the attention */ 5693 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5694 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5695 BGE_MACSTAT_LINK_CHANGED); 5696 } 5697 5698 static int 5699 bge_sysctl_verify(SYSCTLFN_ARGS) 5700 { 5701 int error, t; 5702 struct sysctlnode node; 5703 5704 node = *rnode; 5705 t = *(int*)rnode->sysctl_data; 5706 node.sysctl_data = &t; 5707 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5708 if (error || newp == NULL) 5709 return error; 5710 5711 #if 0 5712 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5713 node.sysctl_num, rnode->sysctl_num)); 5714 #endif 5715 5716 if (node.sysctl_num == bge_rxthresh_nodenum) { 5717 if (t < 0 || t >= NBGE_RX_THRESH) 5718 return EINVAL; 5719 bge_update_all_threshes(t); 5720 } else 5721 return EINVAL; 5722 5723 *(int*)rnode->sysctl_data = t; 5724 5725 return 0; 5726 } 5727 5728 /* 5729 * Set up sysctl(3) MIB, hw.bge.*. 5730 */ 5731 static void 5732 bge_sysctl_init(struct bge_softc *sc) 5733 { 5734 int rc, bge_root_num; 5735 const struct sysctlnode *node; 5736 5737 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5738 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5739 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5740 goto out; 5741 } 5742 5743 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5744 0, CTLTYPE_NODE, "bge", 5745 SYSCTL_DESCR("BGE interface controls"), 5746 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5747 goto out; 5748 } 5749 5750 bge_root_num = node->sysctl_num; 5751 5752 /* BGE Rx interrupt mitigation level */ 5753 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5754 CTLFLAG_READWRITE, 5755 CTLTYPE_INT, "rx_lvl", 5756 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5757 bge_sysctl_verify, 0, 5758 &bge_rx_thresh_lvl, 5759 0, CTL_HW, bge_root_num, CTL_CREATE, 5760 CTL_EOL)) != 0) { 5761 goto out; 5762 } 5763 5764 bge_rxthresh_nodenum = node->sysctl_num; 5765 5766 return; 5767 5768 out: 5769 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5770 } 5771 5772 #ifdef BGE_DEBUG 5773 void 5774 bge_debug_info(struct bge_softc *sc) 5775 { 5776 5777 printf("Hardware Flags:\n"); 5778 if (BGE_IS_57765_PLUS(sc)) 5779 printf(" - 57765 Plus\n"); 5780 if (BGE_IS_5717_PLUS(sc)) 5781 printf(" - 5717 Plus\n"); 5782 if (BGE_IS_5755_PLUS(sc)) 5783 printf(" - 5755 Plus\n"); 5784 if (BGE_IS_575X_PLUS(sc)) 5785 printf(" - 575X Plus\n"); 5786 if (BGE_IS_5705_PLUS(sc)) 5787 printf(" - 5705 Plus\n"); 5788 if (BGE_IS_5714_FAMILY(sc)) 5789 printf(" - 5714 Family\n"); 5790 if (BGE_IS_5700_FAMILY(sc)) 5791 printf(" - 5700 Family\n"); 5792 if (sc->bge_flags & BGE_IS_5788) 5793 printf(" - 5788\n"); 5794 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5795 printf(" - Supports Jumbo Frames\n"); 5796 if (sc->bge_flags & BGE_NO_EEPROM) 5797 printf(" - No EEPROM\n"); 5798 if (sc->bge_flags & BGE_PCIX) 5799 printf(" - PCI-X Bus\n"); 5800 if (sc->bge_flags & BGE_PCIE) 5801 printf(" - PCI Express Bus\n"); 5802 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5803 printf(" - RX Alignment Bug\n"); 5804 if (sc->bge_flags & BGE_APE) 5805 printf(" - APE\n"); 5806 if (sc->bge_flags & BGE_CPMU_PRESENT) 5807 printf(" - CPMU\n"); 5808 if (sc->bge_flags & BGE_TSO) 5809 printf(" - TSO\n"); 5810 5811 if (sc->bge_flags & BGE_PHY_NO_3LED) 5812 printf(" - No 3 LEDs\n"); 5813 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5814 printf(" - CRC bug\n"); 5815 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5816 printf(" - ADC bug\n"); 5817 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5818 printf(" - 5704 A0 bug\n"); 5819 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5820 printf(" - jitter bug\n"); 5821 if (sc->bge_flags & BGE_PHY_BER_BUG) 5822 printf(" - BER bug\n"); 5823 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5824 printf(" - adjust trim\n"); 5825 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5826 printf(" - no wirespeed\n"); 5827 } 5828 #endif /* BGE_DEBUG */ 5829 5830 static int 5831 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5832 { 5833 prop_dictionary_t dict; 5834 prop_data_t ea; 5835 5836 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5837 return 1; 5838 5839 dict = device_properties(sc->bge_dev); 5840 ea = prop_dictionary_get(dict, "mac-address"); 5841 if (ea != NULL) { 5842 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5843 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5844 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5845 return 0; 5846 } 5847 5848 return 1; 5849 } 5850 5851 static int 5852 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5853 { 5854 uint32_t mac_addr; 5855 5856 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5857 if ((mac_addr >> 16) == 0x484b) { 5858 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5859 ether_addr[1] = (uint8_t)mac_addr; 5860 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5861 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5862 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5863 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5864 ether_addr[5] = (uint8_t)mac_addr; 5865 return 0; 5866 } 5867 return 1; 5868 } 5869 5870 static int 5871 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5872 { 5873 int mac_offset = BGE_EE_MAC_OFFSET; 5874 5875 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5876 mac_offset = BGE_EE_MAC_OFFSET_5906; 5877 5878 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5879 ETHER_ADDR_LEN)); 5880 } 5881 5882 static int 5883 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5884 { 5885 5886 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5887 return 1; 5888 5889 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5890 ETHER_ADDR_LEN)); 5891 } 5892 5893 static int 5894 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5895 { 5896 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5897 /* NOTE: Order is critical */ 5898 bge_get_eaddr_fw, 5899 bge_get_eaddr_mem, 5900 bge_get_eaddr_nvram, 5901 bge_get_eaddr_eeprom, 5902 NULL 5903 }; 5904 const bge_eaddr_fcn_t *func; 5905 5906 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5907 if ((*func)(sc, eaddr) == 0) 5908 break; 5909 } 5910 return (*func == NULL ? ENXIO : 0); 5911 } 5912
Indexes created Tue Sep 23 23:09:58 GMT 2025