if_bge.c revision 1.250
1 /* $NetBSD: if_bge.c,v 1.250 2013/05/28 17:03:34 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.250 2013/05/28 17:03:34 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rnd.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 680 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 682 683 static const struct bge_revision { 684 uint32_t br_chipid; 685 const char *br_name; 686 } bge_revisions[] = { 687 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 688 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 689 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 690 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 691 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 692 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 693 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 694 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 695 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 696 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 697 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 698 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 699 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 700 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 701 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 702 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 703 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 704 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 705 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 706 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 707 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 708 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 709 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 710 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 711 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 712 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 713 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 714 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 715 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 716 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 717 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 718 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 719 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 720 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 721 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 722 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 723 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 724 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 725 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 726 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 727 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 728 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 729 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 730 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 731 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 732 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 733 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 734 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 735 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 736 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 737 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 738 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 739 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 740 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 741 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 742 /* 5754 and 5787 share the same ASIC ID */ 743 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 744 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 745 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 746 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 747 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 748 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 749 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 750 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 751 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 752 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 753 754 { 0, NULL } 755 }; 756 757 /* 758 * Some defaults for major revisions, so that newer steppings 759 * that we don't know about have a shot at working. 760 */ 761 static const struct bge_revision bge_majorrevs[] = { 762 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 763 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 764 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 765 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 766 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 767 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 768 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 769 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 771 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 772 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 773 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 774 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 775 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 776 /* 5754 and 5787 share the same ASIC ID */ 777 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 778 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 779 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 780 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 781 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 782 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 783 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 784 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 785 786 { 0, NULL } 787 }; 788 789 static int bge_allow_asf = 1; 790 791 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 792 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 793 794 static uint32_t 795 bge_readmem_ind(struct bge_softc *sc, int off) 796 { 797 pcireg_t val; 798 799 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 800 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 801 return 0; 802 803 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 804 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 806 return val; 807 } 808 809 static void 810 bge_writemem_ind(struct bge_softc *sc, int off, int val) 811 { 812 813 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 816 } 817 818 /* 819 * PCI Express only 820 */ 821 static void 822 bge_set_max_readrq(struct bge_softc *sc) 823 { 824 pcireg_t val; 825 826 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 827 + PCIE_DCSR); 828 val &= ~PCIE_DCSR_MAX_READ_REQ; 829 switch (sc->bge_expmrq) { 830 case 2048: 831 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 832 break; 833 case 4096: 834 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 835 break; 836 default: 837 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 838 break; 839 } 840 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 841 + PCIE_DCSR, val); 842 } 843 844 #ifdef notdef 845 static uint32_t 846 bge_readreg_ind(struct bge_softc *sc, int off) 847 { 848 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 849 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 850 } 851 #endif 852 853 static void 854 bge_writereg_ind(struct bge_softc *sc, int off, int val) 855 { 856 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 858 } 859 860 static void 861 bge_writemem_direct(struct bge_softc *sc, int off, int val) 862 { 863 CSR_WRITE_4(sc, off, val); 864 } 865 866 static void 867 bge_writembx(struct bge_softc *sc, int off, int val) 868 { 869 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 870 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 871 872 CSR_WRITE_4(sc, off, val); 873 } 874 875 static void 876 bge_writembx_flush(struct bge_softc *sc, int off, int val) 877 { 878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 879 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 880 881 CSR_WRITE_4_FLUSH(sc, off, val); 882 } 883 884 /* 885 * Clear all stale locks and select the lock for this driver instance. 886 */ 887 void 888 bge_ape_lock_init(struct bge_softc *sc) 889 { 890 struct pci_attach_args *pa = &(sc->bge_pa); 891 uint32_t bit, regbase; 892 int i; 893 894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 895 regbase = BGE_APE_LOCK_GRANT; 896 else 897 regbase = BGE_APE_PER_LOCK_GRANT; 898 899 /* Clear any stale locks. */ 900 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 901 switch (i) { 902 case BGE_APE_LOCK_PHY0: 903 case BGE_APE_LOCK_PHY1: 904 case BGE_APE_LOCK_PHY2: 905 case BGE_APE_LOCK_PHY3: 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 break; 908 default: 909 if (pa->pa_function == 0) 910 bit = BGE_APE_LOCK_GRANT_DRIVER0; 911 else 912 bit = (1 << pa->pa_function); 913 } 914 APE_WRITE_4(sc, regbase + 4 * i, bit); 915 } 916 917 /* Select the PHY lock based on the device's function number. */ 918 switch (pa->pa_function) { 919 case 0: 920 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 921 break; 922 case 1: 923 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 924 break; 925 case 2: 926 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 927 break; 928 case 3: 929 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 930 break; 931 default: 932 printf("%s: PHY lock not supported on function\n", 933 device_xname(sc->bge_dev)); 934 break; 935 } 936 } 937 938 /* 939 * Check for APE firmware, set flags, and print version info. 940 */ 941 void 942 bge_ape_read_fw_ver(struct bge_softc *sc) 943 { 944 const char *fwtype; 945 uint32_t apedata, features; 946 947 /* Check for a valid APE signature in shared memory. */ 948 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 949 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 950 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 951 return; 952 } 953 954 /* Check if APE firmware is running. */ 955 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 956 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 957 printf("%s: APE signature found but FW status not ready! " 958 "0x%08x\n", device_xname(sc->bge_dev), apedata); 959 return; 960 } 961 962 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 963 964 /* Fetch the APE firwmare type and version. */ 965 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 966 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 967 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 968 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 969 fwtype = "NCSI"; 970 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 971 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 972 fwtype = "DASH"; 973 } else 974 fwtype = "UNKN"; 975 976 /* Print the APE firmware version. */ 977 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 978 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 979 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 980 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 981 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 982 } 983 984 int 985 bge_ape_lock(struct bge_softc *sc, int locknum) 986 { 987 struct pci_attach_args *pa = &(sc->bge_pa); 988 uint32_t bit, gnt, req, status; 989 int i, off; 990 991 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 992 return (0); 993 994 /* Lock request/grant registers have different bases. */ 995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 996 req = BGE_APE_LOCK_REQ; 997 gnt = BGE_APE_LOCK_GRANT; 998 } else { 999 req = BGE_APE_PER_LOCK_REQ; 1000 gnt = BGE_APE_PER_LOCK_GRANT; 1001 } 1002 1003 off = 4 * locknum; 1004 1005 switch (locknum) { 1006 case BGE_APE_LOCK_GPIO: 1007 /* Lock required when using GPIO. */ 1008 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1009 return (0); 1010 if (pa->pa_function == 0) 1011 bit = BGE_APE_LOCK_REQ_DRIVER0; 1012 else 1013 bit = (1 << pa->pa_function); 1014 break; 1015 case BGE_APE_LOCK_GRC: 1016 /* Lock required to reset the device. */ 1017 if (pa->pa_function == 0) 1018 bit = BGE_APE_LOCK_REQ_DRIVER0; 1019 else 1020 bit = (1 << pa->pa_function); 1021 break; 1022 case BGE_APE_LOCK_MEM: 1023 /* Lock required when accessing certain APE memory. */ 1024 if (pa->pa_function == 0) 1025 bit = BGE_APE_LOCK_REQ_DRIVER0; 1026 else 1027 bit = (1 << pa->pa_function); 1028 break; 1029 case BGE_APE_LOCK_PHY0: 1030 case BGE_APE_LOCK_PHY1: 1031 case BGE_APE_LOCK_PHY2: 1032 case BGE_APE_LOCK_PHY3: 1033 /* Lock required when accessing PHYs. */ 1034 bit = BGE_APE_LOCK_REQ_DRIVER0; 1035 break; 1036 default: 1037 return (EINVAL); 1038 } 1039 1040 /* Request a lock. */ 1041 APE_WRITE_4_FLUSH(sc, req + off, bit); 1042 1043 /* Wait up to 1 second to acquire lock. */ 1044 for (i = 0; i < 20000; i++) { 1045 status = APE_READ_4(sc, gnt + off); 1046 if (status == bit) 1047 break; 1048 DELAY(50); 1049 } 1050 1051 /* Handle any errors. */ 1052 if (status != bit) { 1053 printf("%s: APE lock %d request failed! " 1054 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1055 device_xname(sc->bge_dev), 1056 locknum, req + off, bit & 0xFFFF, gnt + off, 1057 status & 0xFFFF); 1058 /* Revoke the lock request. */ 1059 APE_WRITE_4(sc, gnt + off, bit); 1060 return (EBUSY); 1061 } 1062 1063 return (0); 1064 } 1065 1066 void 1067 bge_ape_unlock(struct bge_softc *sc, int locknum) 1068 { 1069 struct pci_attach_args *pa = &(sc->bge_pa); 1070 uint32_t bit, gnt; 1071 int off; 1072 1073 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1074 return; 1075 1076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1077 gnt = BGE_APE_LOCK_GRANT; 1078 else 1079 gnt = BGE_APE_PER_LOCK_GRANT; 1080 1081 off = 4 * locknum; 1082 1083 switch (locknum) { 1084 case BGE_APE_LOCK_GPIO: 1085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1086 return; 1087 if (pa->pa_function == 0) 1088 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1089 else 1090 bit = (1 << pa->pa_function); 1091 break; 1092 case BGE_APE_LOCK_GRC: 1093 if (pa->pa_function == 0) 1094 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1095 else 1096 bit = (1 << pa->pa_function); 1097 break; 1098 case BGE_APE_LOCK_MEM: 1099 if (pa->pa_function == 0) 1100 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1101 else 1102 bit = (1 << pa->pa_function); 1103 break; 1104 case BGE_APE_LOCK_PHY0: 1105 case BGE_APE_LOCK_PHY1: 1106 case BGE_APE_LOCK_PHY2: 1107 case BGE_APE_LOCK_PHY3: 1108 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1109 break; 1110 default: 1111 return; 1112 } 1113 1114 /* Write and flush for consecutive bge_ape_lock() */ 1115 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1116 } 1117 1118 /* 1119 * Send an event to the APE firmware. 1120 */ 1121 void 1122 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1123 { 1124 uint32_t apedata; 1125 int i; 1126 1127 /* NCSI does not support APE events. */ 1128 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1129 return; 1130 1131 /* Wait up to 1ms for APE to service previous event. */ 1132 for (i = 10; i > 0; i--) { 1133 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1134 break; 1135 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1136 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1137 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1138 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1141 break; 1142 } 1143 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1144 DELAY(100); 1145 } 1146 if (i == 0) { 1147 printf("%s: APE event 0x%08x send timed out\n", 1148 device_xname(sc->bge_dev), event); 1149 } 1150 } 1151 1152 void 1153 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1154 { 1155 uint32_t apedata, event; 1156 1157 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1158 return; 1159 1160 switch (kind) { 1161 case BGE_RESET_START: 1162 /* If this is the first load, clear the load counter. */ 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1164 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1165 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1166 else { 1167 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1168 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1169 } 1170 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1171 BGE_APE_HOST_SEG_SIG_MAGIC); 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1173 BGE_APE_HOST_SEG_LEN_MAGIC); 1174 1175 /* Add some version info if bge(4) supports it. */ 1176 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1177 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1178 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1179 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1180 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1181 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1182 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1183 BGE_APE_HOST_DRVR_STATE_START); 1184 event = BGE_APE_EVENT_STATUS_STATE_START; 1185 break; 1186 case BGE_RESET_SHUTDOWN: 1187 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1188 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1189 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1190 break; 1191 case BGE_RESET_SUSPEND: 1192 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1193 break; 1194 default: 1195 return; 1196 } 1197 1198 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1199 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1200 } 1201 1202 static uint8_t 1203 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1204 { 1205 uint32_t access, byte = 0; 1206 int i; 1207 1208 /* Lock. */ 1209 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1210 for (i = 0; i < 8000; i++) { 1211 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1212 break; 1213 DELAY(20); 1214 } 1215 if (i == 8000) 1216 return 1; 1217 1218 /* Enable access. */ 1219 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1220 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1221 1222 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1223 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1224 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1225 DELAY(10); 1226 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1227 DELAY(10); 1228 break; 1229 } 1230 } 1231 1232 if (i == BGE_TIMEOUT * 10) { 1233 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1234 return 1; 1235 } 1236 1237 /* Get result. */ 1238 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1239 1240 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1241 1242 /* Disable access. */ 1243 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1244 1245 /* Unlock. */ 1246 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1247 1248 return 0; 1249 } 1250 1251 /* 1252 * Read a sequence of bytes from NVRAM. 1253 */ 1254 static int 1255 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1256 { 1257 int error = 0, i; 1258 uint8_t byte = 0; 1259 1260 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1261 return 1; 1262 1263 for (i = 0; i < cnt; i++) { 1264 error = bge_nvram_getbyte(sc, off + i, &byte); 1265 if (error) 1266 break; 1267 *(dest + i) = byte; 1268 } 1269 1270 return (error ? 1 : 0); 1271 } 1272 1273 /* 1274 * Read a byte of data stored in the EEPROM at address 'addr.' The 1275 * BCM570x supports both the traditional bitbang interface and an 1276 * auto access interface for reading the EEPROM. We use the auto 1277 * access method. 1278 */ 1279 static uint8_t 1280 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1281 { 1282 int i; 1283 uint32_t byte = 0; 1284 1285 /* 1286 * Enable use of auto EEPROM access so we can avoid 1287 * having to use the bitbang method. 1288 */ 1289 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1290 1291 /* Reset the EEPROM, load the clock period. */ 1292 CSR_WRITE_4(sc, BGE_EE_ADDR, 1293 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1294 DELAY(20); 1295 1296 /* Issue the read EEPROM command. */ 1297 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1298 1299 /* Wait for completion */ 1300 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1301 DELAY(10); 1302 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1303 break; 1304 } 1305 1306 if (i == BGE_TIMEOUT * 10) { 1307 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1308 return 1; 1309 } 1310 1311 /* Get result. */ 1312 byte = CSR_READ_4(sc, BGE_EE_DATA); 1313 1314 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1315 1316 return 0; 1317 } 1318 1319 /* 1320 * Read a sequence of bytes from the EEPROM. 1321 */ 1322 static int 1323 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1324 { 1325 int error = 0, i; 1326 uint8_t byte = 0; 1327 char *dest = destv; 1328 1329 for (i = 0; i < cnt; i++) { 1330 error = bge_eeprom_getbyte(sc, off + i, &byte); 1331 if (error) 1332 break; 1333 *(dest + i) = byte; 1334 } 1335 1336 return (error ? 1 : 0); 1337 } 1338 1339 static int 1340 bge_miibus_readreg(device_t dev, int phy, int reg) 1341 { 1342 struct bge_softc *sc = device_private(dev); 1343 uint32_t val; 1344 uint32_t autopoll; 1345 int i; 1346 1347 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1348 return 0; 1349 1350 /* Reading with autopolling on may trigger PCI errors */ 1351 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1352 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1353 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1354 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1355 DELAY(80); 1356 } 1357 1358 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1359 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1360 1361 for (i = 0; i < BGE_TIMEOUT; i++) { 1362 delay(10); 1363 val = CSR_READ_4(sc, BGE_MI_COMM); 1364 if (!(val & BGE_MICOMM_BUSY)) { 1365 DELAY(5); 1366 val = CSR_READ_4(sc, BGE_MI_COMM); 1367 break; 1368 } 1369 } 1370 1371 if (i == BGE_TIMEOUT) { 1372 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1373 val = 0; 1374 goto done; 1375 } 1376 1377 done: 1378 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1379 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1380 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1381 DELAY(80); 1382 } 1383 1384 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1385 1386 if (val & BGE_MICOMM_READFAIL) 1387 return 0; 1388 1389 return (val & 0xFFFF); 1390 } 1391 1392 static void 1393 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1394 { 1395 struct bge_softc *sc = device_private(dev); 1396 uint32_t autopoll; 1397 int i; 1398 1399 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1400 return; 1401 1402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1403 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1404 return; 1405 1406 /* Reading with autopolling on may trigger PCI errors */ 1407 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1408 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1409 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1410 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1411 DELAY(80); 1412 } 1413 1414 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1415 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1416 1417 for (i = 0; i < BGE_TIMEOUT; i++) { 1418 delay(10); 1419 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1420 delay(5); 1421 CSR_READ_4(sc, BGE_MI_COMM); 1422 break; 1423 } 1424 } 1425 1426 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1427 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1428 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1429 delay(80); 1430 } 1431 1432 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1433 1434 if (i == BGE_TIMEOUT) 1435 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1436 } 1437 1438 static void 1439 bge_miibus_statchg(struct ifnet *ifp) 1440 { 1441 struct bge_softc *sc = ifp->if_softc; 1442 struct mii_data *mii = &sc->bge_mii; 1443 uint32_t mac_mode, rx_mode, tx_mode; 1444 1445 /* 1446 * Get flow control negotiation result. 1447 */ 1448 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1449 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1450 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1451 mii->mii_media_active &= ~IFM_ETH_FMASK; 1452 } 1453 1454 /* Set the port mode (MII/GMII) to match the link speed. */ 1455 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1456 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1457 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1458 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1459 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1460 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1461 mac_mode |= BGE_PORTMODE_GMII; 1462 else 1463 mac_mode |= BGE_PORTMODE_MII; 1464 1465 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1466 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1467 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1468 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1469 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1470 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1471 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1472 } else 1473 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1474 1475 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1476 DELAY(40); 1477 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1478 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1479 } 1480 1481 /* 1482 * Update rx threshold levels to values in a particular slot 1483 * of the interrupt-mitigation table bge_rx_threshes. 1484 */ 1485 static void 1486 bge_set_thresh(struct ifnet *ifp, int lvl) 1487 { 1488 struct bge_softc *sc = ifp->if_softc; 1489 int s; 1490 1491 /* For now, just save the new Rx-intr thresholds and record 1492 * that a threshold update is pending. Updating the hardware 1493 * registers here (even at splhigh()) is observed to 1494 * occasionaly cause glitches where Rx-interrupts are not 1495 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1496 */ 1497 s = splnet(); 1498 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1499 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1500 sc->bge_pending_rxintr_change = 1; 1501 splx(s); 1502 } 1503 1504 1505 /* 1506 * Update Rx thresholds of all bge devices 1507 */ 1508 static void 1509 bge_update_all_threshes(int lvl) 1510 { 1511 struct ifnet *ifp; 1512 const char * const namebuf = "bge"; 1513 int namelen; 1514 1515 if (lvl < 0) 1516 lvl = 0; 1517 else if (lvl >= NBGE_RX_THRESH) 1518 lvl = NBGE_RX_THRESH - 1; 1519 1520 namelen = strlen(namebuf); 1521 /* 1522 * Now search all the interfaces for this name/number 1523 */ 1524 IFNET_FOREACH(ifp) { 1525 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1526 continue; 1527 /* We got a match: update if doing auto-threshold-tuning */ 1528 if (bge_auto_thresh) 1529 bge_set_thresh(ifp, lvl); 1530 } 1531 } 1532 1533 /* 1534 * Handle events that have triggered interrupts. 1535 */ 1536 static void 1537 bge_handle_events(struct bge_softc *sc) 1538 { 1539 1540 return; 1541 } 1542 1543 /* 1544 * Memory management for jumbo frames. 1545 */ 1546 1547 static int 1548 bge_alloc_jumbo_mem(struct bge_softc *sc) 1549 { 1550 char *ptr, *kva; 1551 bus_dma_segment_t seg; 1552 int i, rseg, state, error; 1553 struct bge_jpool_entry *entry; 1554 1555 state = error = 0; 1556 1557 /* Grab a big chunk o' storage. */ 1558 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1560 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1561 return ENOBUFS; 1562 } 1563 1564 state = 1; 1565 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1566 BUS_DMA_NOWAIT)) { 1567 aprint_error_dev(sc->bge_dev, 1568 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1569 error = ENOBUFS; 1570 goto out; 1571 } 1572 1573 state = 2; 1574 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1575 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1576 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1577 error = ENOBUFS; 1578 goto out; 1579 } 1580 1581 state = 3; 1582 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1583 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1584 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1585 error = ENOBUFS; 1586 goto out; 1587 } 1588 1589 state = 4; 1590 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1591 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1592 1593 SLIST_INIT(&sc->bge_jfree_listhead); 1594 SLIST_INIT(&sc->bge_jinuse_listhead); 1595 1596 /* 1597 * Now divide it up into 9K pieces and save the addresses 1598 * in an array. 1599 */ 1600 ptr = sc->bge_cdata.bge_jumbo_buf; 1601 for (i = 0; i < BGE_JSLOTS; i++) { 1602 sc->bge_cdata.bge_jslots[i] = ptr; 1603 ptr += BGE_JLEN; 1604 entry = malloc(sizeof(struct bge_jpool_entry), 1605 M_DEVBUF, M_NOWAIT); 1606 if (entry == NULL) { 1607 aprint_error_dev(sc->bge_dev, 1608 "no memory for jumbo buffer queue!\n"); 1609 error = ENOBUFS; 1610 goto out; 1611 } 1612 entry->slot = i; 1613 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1614 entry, jpool_entries); 1615 } 1616 out: 1617 if (error != 0) { 1618 switch (state) { 1619 case 4: 1620 bus_dmamap_unload(sc->bge_dmatag, 1621 sc->bge_cdata.bge_rx_jumbo_map); 1622 case 3: 1623 bus_dmamap_destroy(sc->bge_dmatag, 1624 sc->bge_cdata.bge_rx_jumbo_map); 1625 case 2: 1626 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1627 case 1: 1628 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1629 break; 1630 default: 1631 break; 1632 } 1633 } 1634 1635 return error; 1636 } 1637 1638 /* 1639 * Allocate a jumbo buffer. 1640 */ 1641 static void * 1642 bge_jalloc(struct bge_softc *sc) 1643 { 1644 struct bge_jpool_entry *entry; 1645 1646 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1647 1648 if (entry == NULL) { 1649 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1650 return NULL; 1651 } 1652 1653 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1654 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1655 return (sc->bge_cdata.bge_jslots[entry->slot]); 1656 } 1657 1658 /* 1659 * Release a jumbo buffer. 1660 */ 1661 static void 1662 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1663 { 1664 struct bge_jpool_entry *entry; 1665 struct bge_softc *sc; 1666 int i, s; 1667 1668 /* Extract the softc struct pointer. */ 1669 sc = (struct bge_softc *)arg; 1670 1671 if (sc == NULL) 1672 panic("bge_jfree: can't find softc pointer!"); 1673 1674 /* calculate the slot this buffer belongs to */ 1675 1676 i = ((char *)buf 1677 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1678 1679 if ((i < 0) || (i >= BGE_JSLOTS)) 1680 panic("bge_jfree: asked to free buffer that we don't manage!"); 1681 1682 s = splvm(); 1683 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1684 if (entry == NULL) 1685 panic("bge_jfree: buffer not in use!"); 1686 entry->slot = i; 1687 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1688 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1689 1690 if (__predict_true(m != NULL)) 1691 pool_cache_put(mb_cache, m); 1692 splx(s); 1693 } 1694 1695 1696 /* 1697 * Initialize a standard receive ring descriptor. 1698 */ 1699 static int 1700 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1701 bus_dmamap_t dmamap) 1702 { 1703 struct mbuf *m_new = NULL; 1704 struct bge_rx_bd *r; 1705 int error; 1706 1707 if (dmamap == NULL) { 1708 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1709 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1710 if (error != 0) 1711 return error; 1712 } 1713 1714 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1715 1716 if (m == NULL) { 1717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1718 if (m_new == NULL) 1719 return ENOBUFS; 1720 1721 MCLGET(m_new, M_DONTWAIT); 1722 if (!(m_new->m_flags & M_EXT)) { 1723 m_freem(m_new); 1724 return ENOBUFS; 1725 } 1726 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1727 1728 } else { 1729 m_new = m; 1730 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1731 m_new->m_data = m_new->m_ext.ext_buf; 1732 } 1733 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1734 m_adj(m_new, ETHER_ALIGN); 1735 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1736 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1737 return ENOBUFS; 1738 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1739 BUS_DMASYNC_PREREAD); 1740 1741 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1742 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1743 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1744 r->bge_flags = BGE_RXBDFLAG_END; 1745 r->bge_len = m_new->m_len; 1746 r->bge_idx = i; 1747 1748 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1749 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1750 i * sizeof (struct bge_rx_bd), 1751 sizeof (struct bge_rx_bd), 1752 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1753 1754 return 0; 1755 } 1756 1757 /* 1758 * Initialize a jumbo receive ring descriptor. This allocates 1759 * a jumbo buffer from the pool managed internally by the driver. 1760 */ 1761 static int 1762 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1763 { 1764 struct mbuf *m_new = NULL; 1765 struct bge_rx_bd *r; 1766 void *buf = NULL; 1767 1768 if (m == NULL) { 1769 1770 /* Allocate the mbuf. */ 1771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1772 if (m_new == NULL) 1773 return ENOBUFS; 1774 1775 /* Allocate the jumbo buffer */ 1776 buf = bge_jalloc(sc); 1777 if (buf == NULL) { 1778 m_freem(m_new); 1779 aprint_error_dev(sc->bge_dev, 1780 "jumbo allocation failed -- packet dropped!\n"); 1781 return ENOBUFS; 1782 } 1783 1784 /* Attach the buffer to the mbuf. */ 1785 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1786 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1787 bge_jfree, sc); 1788 m_new->m_flags |= M_EXT_RW; 1789 } else { 1790 m_new = m; 1791 buf = m_new->m_data = m_new->m_ext.ext_buf; 1792 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1793 } 1794 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1795 m_adj(m_new, ETHER_ALIGN); 1796 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1797 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1798 BUS_DMASYNC_PREREAD); 1799 /* Set up the descriptor. */ 1800 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1801 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1802 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1803 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1804 r->bge_len = m_new->m_len; 1805 r->bge_idx = i; 1806 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1808 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1809 i * sizeof (struct bge_rx_bd), 1810 sizeof (struct bge_rx_bd), 1811 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1812 1813 return 0; 1814 } 1815 1816 /* 1817 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1818 * that's 1MB or memory, which is a lot. For now, we fill only the first 1819 * 256 ring entries and hope that our CPU is fast enough to keep up with 1820 * the NIC. 1821 */ 1822 static int 1823 bge_init_rx_ring_std(struct bge_softc *sc) 1824 { 1825 int i; 1826 1827 if (sc->bge_flags & BGE_RXRING_VALID) 1828 return 0; 1829 1830 for (i = 0; i < BGE_SSLOTS; i++) { 1831 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1832 return ENOBUFS; 1833 } 1834 1835 sc->bge_std = i - 1; 1836 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1837 1838 sc->bge_flags |= BGE_RXRING_VALID; 1839 1840 return 0; 1841 } 1842 1843 static void 1844 bge_free_rx_ring_std(struct bge_softc *sc) 1845 { 1846 int i; 1847 1848 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1849 return; 1850 1851 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1852 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1853 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1854 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1855 bus_dmamap_destroy(sc->bge_dmatag, 1856 sc->bge_cdata.bge_rx_std_map[i]); 1857 } 1858 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1859 sizeof(struct bge_rx_bd)); 1860 } 1861 1862 sc->bge_flags &= ~BGE_RXRING_VALID; 1863 } 1864 1865 static int 1866 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1867 { 1868 int i; 1869 volatile struct bge_rcb *rcb; 1870 1871 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1872 return 0; 1873 1874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1875 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1876 return ENOBUFS; 1877 } 1878 1879 sc->bge_jumbo = i - 1; 1880 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1881 1882 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1883 rcb->bge_maxlen_flags = 0; 1884 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1885 1886 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1887 1888 return 0; 1889 } 1890 1891 static void 1892 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1893 { 1894 int i; 1895 1896 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1897 return; 1898 1899 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1900 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1901 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1902 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1903 } 1904 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1905 sizeof(struct bge_rx_bd)); 1906 } 1907 1908 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1909 } 1910 1911 static void 1912 bge_free_tx_ring(struct bge_softc *sc) 1913 { 1914 int i; 1915 struct txdmamap_pool_entry *dma; 1916 1917 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1918 return; 1919 1920 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1921 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1922 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1923 sc->bge_cdata.bge_tx_chain[i] = NULL; 1924 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1925 link); 1926 sc->txdma[i] = 0; 1927 } 1928 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1929 sizeof(struct bge_tx_bd)); 1930 } 1931 1932 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1933 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1934 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1935 free(dma, M_DEVBUF); 1936 } 1937 1938 sc->bge_flags &= ~BGE_TXRING_VALID; 1939 } 1940 1941 static int 1942 bge_init_tx_ring(struct bge_softc *sc) 1943 { 1944 int i; 1945 bus_dmamap_t dmamap; 1946 struct txdmamap_pool_entry *dma; 1947 1948 if (sc->bge_flags & BGE_TXRING_VALID) 1949 return 0; 1950 1951 sc->bge_txcnt = 0; 1952 sc->bge_tx_saved_considx = 0; 1953 1954 /* Initialize transmit producer index for host-memory send ring. */ 1955 sc->bge_tx_prodidx = 0; 1956 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1957 /* 5700 b2 errata */ 1958 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1959 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1960 1961 /* NIC-memory send ring not used; initialize to zero. */ 1962 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1963 /* 5700 b2 errata */ 1964 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1965 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1966 1967 SLIST_INIT(&sc->txdma_list); 1968 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1969 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1970 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1971 &dmamap)) 1972 return ENOBUFS; 1973 if (dmamap == NULL) 1974 panic("dmamap NULL in bge_init_tx_ring"); 1975 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1976 if (dma == NULL) { 1977 aprint_error_dev(sc->bge_dev, 1978 "can't alloc txdmamap_pool_entry\n"); 1979 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1980 return ENOMEM; 1981 } 1982 dma->dmamap = dmamap; 1983 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1984 } 1985 1986 sc->bge_flags |= BGE_TXRING_VALID; 1987 1988 return 0; 1989 } 1990 1991 static void 1992 bge_setmulti(struct bge_softc *sc) 1993 { 1994 struct ethercom *ac = &sc->ethercom; 1995 struct ifnet *ifp = &ac->ec_if; 1996 struct ether_multi *enm; 1997 struct ether_multistep step; 1998 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1999 uint32_t h; 2000 int i; 2001 2002 if (ifp->if_flags & IFF_PROMISC) 2003 goto allmulti; 2004 2005 /* Now program new ones. */ 2006 ETHER_FIRST_MULTI(step, ac, enm); 2007 while (enm != NULL) { 2008 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2009 /* 2010 * We must listen to a range of multicast addresses. 2011 * For now, just accept all multicasts, rather than 2012 * trying to set only those filter bits needed to match 2013 * the range. (At this time, the only use of address 2014 * ranges is for IP multicast routing, for which the 2015 * range is big enough to require all bits set.) 2016 */ 2017 goto allmulti; 2018 } 2019 2020 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2021 2022 /* Just want the 7 least-significant bits. */ 2023 h &= 0x7f; 2024 2025 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2026 ETHER_NEXT_MULTI(step, enm); 2027 } 2028 2029 ifp->if_flags &= ~IFF_ALLMULTI; 2030 goto setit; 2031 2032 allmulti: 2033 ifp->if_flags |= IFF_ALLMULTI; 2034 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2035 2036 setit: 2037 for (i = 0; i < 4; i++) 2038 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2039 } 2040 2041 static void 2042 bge_sig_pre_reset(struct bge_softc *sc, int type) 2043 { 2044 2045 /* 2046 * Some chips don't like this so only do this if ASF is enabled 2047 */ 2048 if (sc->bge_asf_mode) 2049 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2050 2051 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2052 switch (type) { 2053 case BGE_RESET_START: 2054 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2055 BGE_FW_DRV_STATE_START); 2056 break; 2057 case BGE_RESET_SHUTDOWN: 2058 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2059 BGE_FW_DRV_STATE_UNLOAD); 2060 break; 2061 case BGE_RESET_SUSPEND: 2062 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2063 BGE_FW_DRV_STATE_SUSPEND); 2064 break; 2065 } 2066 } 2067 2068 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2069 bge_ape_driver_state_change(sc, type); 2070 } 2071 2072 static void 2073 bge_sig_post_reset(struct bge_softc *sc, int type) 2074 { 2075 2076 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2077 switch (type) { 2078 case BGE_RESET_START: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_START_DONE); 2081 /* START DONE */ 2082 break; 2083 case BGE_RESET_SHUTDOWN: 2084 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2085 BGE_FW_DRV_STATE_UNLOAD_DONE); 2086 break; 2087 } 2088 } 2089 2090 if (type == BGE_RESET_SHUTDOWN) 2091 bge_ape_driver_state_change(sc, type); 2092 } 2093 2094 static void 2095 bge_sig_legacy(struct bge_softc *sc, int type) 2096 { 2097 2098 if (sc->bge_asf_mode) { 2099 switch (type) { 2100 case BGE_RESET_START: 2101 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2102 BGE_FW_DRV_STATE_START); 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD); 2107 break; 2108 } 2109 } 2110 } 2111 2112 static void 2113 bge_wait_for_event_ack(struct bge_softc *sc) 2114 { 2115 int i; 2116 2117 /* wait up to 2500usec */ 2118 for (i = 0; i < 250; i++) { 2119 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2120 BGE_RX_CPU_DRV_EVENT)) 2121 break; 2122 DELAY(10); 2123 } 2124 } 2125 2126 static void 2127 bge_stop_fw(struct bge_softc *sc) 2128 { 2129 2130 if (sc->bge_asf_mode) { 2131 bge_wait_for_event_ack(sc); 2132 2133 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2134 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2135 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2136 2137 bge_wait_for_event_ack(sc); 2138 } 2139 } 2140 2141 static int 2142 bge_poll_fw(struct bge_softc *sc) 2143 { 2144 uint32_t val; 2145 int i; 2146 2147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2148 for (i = 0; i < BGE_TIMEOUT; i++) { 2149 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2150 if (val & BGE_VCPU_STATUS_INIT_DONE) 2151 break; 2152 DELAY(100); 2153 } 2154 if (i >= BGE_TIMEOUT) { 2155 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2156 return -1; 2157 } 2158 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2159 /* 2160 * Poll the value location we just wrote until 2161 * we see the 1's complement of the magic number. 2162 * This indicates that the firmware initialization 2163 * is complete. 2164 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2165 */ 2166 for (i = 0; i < BGE_TIMEOUT; i++) { 2167 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2168 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2169 break; 2170 DELAY(10); 2171 } 2172 2173 if (i >= BGE_TIMEOUT) { 2174 aprint_error_dev(sc->bge_dev, 2175 "firmware handshake timed out, val = %x\n", val); 2176 return -1; 2177 } 2178 } 2179 2180 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2181 /* tg3 says we have to wait extra time */ 2182 delay(10 * 1000); 2183 } 2184 2185 return 0; 2186 } 2187 2188 int 2189 bge_phy_addr(struct bge_softc *sc) 2190 { 2191 struct pci_attach_args *pa = &(sc->bge_pa); 2192 int phy_addr = 1; 2193 2194 /* 2195 * PHY address mapping for various devices. 2196 * 2197 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2198 * ---------+-------+-------+-------+-------+ 2199 * BCM57XX | 1 | X | X | X | 2200 * BCM5704 | 1 | X | 1 | X | 2201 * BCM5717 | 1 | 8 | 2 | 9 | 2202 * BCM5719 | 1 | 8 | 2 | 9 | 2203 * BCM5720 | 1 | 8 | 2 | 9 | 2204 * 2205 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2206 * ---------+-------+-------+-------+-------+ 2207 * BCM57XX | X | X | X | X | 2208 * BCM5704 | X | X | X | X | 2209 * BCM5717 | X | X | X | X | 2210 * BCM5719 | 3 | 10 | 4 | 11 | 2211 * BCM5720 | X | X | X | X | 2212 * 2213 * Other addresses may respond but they are not 2214 * IEEE compliant PHYs and should be ignored. 2215 */ 2216 switch (BGE_ASICREV(sc->bge_chipid)) { 2217 case BGE_ASICREV_BCM5717: 2218 case BGE_ASICREV_BCM5719: 2219 case BGE_ASICREV_BCM5720: 2220 phy_addr = pa->pa_function; 2221 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2222 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2223 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2224 } else { 2225 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2226 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2227 } 2228 } 2229 2230 return phy_addr; 2231 } 2232 2233 /* 2234 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2235 * self-test results. 2236 */ 2237 static int 2238 bge_chipinit(struct bge_softc *sc) 2239 { 2240 uint32_t dma_rw_ctl, mode_ctl, reg; 2241 int i; 2242 2243 /* Set endianness before we access any non-PCI registers. */ 2244 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2245 BGE_INIT); 2246 2247 /* 2248 * Clear the MAC statistics block in the NIC's 2249 * internal memory. 2250 */ 2251 for (i = BGE_STATS_BLOCK; 2252 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2253 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2254 2255 for (i = BGE_STATUS_BLOCK; 2256 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2257 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2258 2259 /* 5717 workaround from tg3 */ 2260 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2261 /* Save */ 2262 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2263 2264 /* Temporary modify MODE_CTL to control TLP */ 2265 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2266 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2267 2268 /* Control TLP */ 2269 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2270 BGE_TLP_PHYCTL1); 2271 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2272 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2273 2274 /* Restore */ 2275 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2276 } 2277 2278 /* XXX Should we use 57765_FAMILY? */ 2279 if (BGE_IS_57765_PLUS(sc)) { 2280 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2281 /* Save */ 2282 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2283 2284 /* Temporary modify MODE_CTL to control TLP */ 2285 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2286 CSR_WRITE_4(sc, BGE_MODE_CTL, 2287 reg | BGE_MODECTL_PCIE_TLPADDR1); 2288 2289 /* Control TLP */ 2290 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2291 BGE_TLP_PHYCTL5); 2292 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2293 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2294 2295 /* Restore */ 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2297 } 2298 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2299 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2300 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2301 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2302 2303 /* Save */ 2304 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2305 2306 /* Temporary modify MODE_CTL to control TLP */ 2307 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2308 CSR_WRITE_4(sc, BGE_MODE_CTL, 2309 reg | BGE_MODECTL_PCIE_TLPADDR0); 2310 2311 /* Control TLP */ 2312 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2313 BGE_TLP_FTSMAX); 2314 reg &= ~BGE_TLP_FTSMAX_MSK; 2315 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2316 reg | BGE_TLP_FTSMAX_VAL); 2317 2318 /* Restore */ 2319 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2320 } 2321 2322 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2323 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2324 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2325 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2326 } 2327 2328 /* Set up the PCI DMA control register. */ 2329 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2330 if (sc->bge_flags & BGE_PCIE) { 2331 /* Read watermark not used, 128 bytes for write. */ 2332 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2333 device_xname(sc->bge_dev))); 2334 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2335 } else if (sc->bge_flags & BGE_PCIX) { 2336 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2337 device_xname(sc->bge_dev))); 2338 /* PCI-X bus */ 2339 if (BGE_IS_5714_FAMILY(sc)) { 2340 /* 256 bytes for read and write. */ 2341 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2342 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2343 2344 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2345 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2346 else 2347 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2348 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2349 /* 1536 bytes for read, 384 bytes for write. */ 2350 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2351 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2352 } else { 2353 /* 384 bytes for read and write. */ 2354 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2355 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2356 (0x0F); 2357 } 2358 2359 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2360 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2361 uint32_t tmp; 2362 2363 /* Set ONEDMA_ATONCE for hardware workaround. */ 2364 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2365 if (tmp == 6 || tmp == 7) 2366 dma_rw_ctl |= 2367 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2368 2369 /* Set PCI-X DMA write workaround. */ 2370 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2371 } 2372 } else { 2373 /* Conventional PCI bus: 256 bytes for read and write. */ 2374 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2375 device_xname(sc->bge_dev))); 2376 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2377 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2378 2379 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2380 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2381 dma_rw_ctl |= 0x0F; 2382 } 2383 2384 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2385 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2386 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2387 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2388 2389 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2390 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2391 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2392 2393 if (BGE_IS_5717_PLUS(sc)) { 2394 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2395 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2396 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2397 2398 /* 2399 * Enable HW workaround for controllers that misinterpret 2400 * a status tag update and leave interrupts permanently 2401 * disabled. 2402 */ 2403 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2404 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2405 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2406 } 2407 2408 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2409 dma_rw_ctl); 2410 2411 /* 2412 * Set up general mode register. 2413 */ 2414 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2415 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2416 /* Retain Host-2-BMC settings written by APE firmware. */ 2417 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2418 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2419 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2420 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2421 } 2422 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2423 BGE_MODECTL_TX_NO_PHDR_CSUM; 2424 2425 /* 2426 * BCM5701 B5 have a bug causing data corruption when using 2427 * 64-bit DMA reads, which can be terminated early and then 2428 * completed later as 32-bit accesses, in combination with 2429 * certain bridges. 2430 */ 2431 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2432 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2433 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2434 2435 /* 2436 * Tell the firmware the driver is running 2437 */ 2438 if (sc->bge_asf_mode & ASF_STACKUP) 2439 mode_ctl |= BGE_MODECTL_STACKUP; 2440 2441 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2442 2443 /* 2444 * Disable memory write invalidate. Apparently it is not supported 2445 * properly by these devices. 2446 */ 2447 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2448 PCI_COMMAND_INVALIDATE_ENABLE); 2449 2450 #ifdef __brokenalpha__ 2451 /* 2452 * Must insure that we do not cross an 8K (bytes) boundary 2453 * for DMA reads. Our highest limit is 1K bytes. This is a 2454 * restriction on some ALPHA platforms with early revision 2455 * 21174 PCI chipsets, such as the AlphaPC 164lx 2456 */ 2457 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2458 #endif 2459 2460 /* Set the timer prescaler (always 66MHz) */ 2461 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2462 2463 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2464 DELAY(40); /* XXX */ 2465 2466 /* Put PHY into ready state */ 2467 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2468 DELAY(40); 2469 } 2470 2471 return 0; 2472 } 2473 2474 static int 2475 bge_blockinit(struct bge_softc *sc) 2476 { 2477 volatile struct bge_rcb *rcb; 2478 bus_size_t rcb_addr; 2479 struct ifnet *ifp = &sc->ethercom.ec_if; 2480 bge_hostaddr taddr; 2481 uint32_t dmactl, val; 2482 int i, limit; 2483 2484 /* 2485 * Initialize the memory window pointer register so that 2486 * we can access the first 32K of internal NIC RAM. This will 2487 * allow us to set up the TX send ring RCBs and the RX return 2488 * ring RCBs, plus other things which live in NIC memory. 2489 */ 2490 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2491 2492 if (!BGE_IS_5705_PLUS(sc)) { 2493 /* 57XX step 33 */ 2494 /* Configure mbuf memory pool */ 2495 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2496 BGE_BUFFPOOL_1); 2497 2498 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2499 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2500 else 2501 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2502 2503 /* 57XX step 34 */ 2504 /* Configure DMA resource pool */ 2505 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2506 BGE_DMA_DESCRIPTORS); 2507 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2508 } 2509 2510 /* 5718 step 11, 57XX step 35 */ 2511 /* 2512 * Configure mbuf pool watermarks. New broadcom docs strongly 2513 * recommend these. 2514 */ 2515 if (BGE_IS_5717_PLUS(sc)) { 2516 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2517 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2518 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2519 } else if (BGE_IS_5705_PLUS(sc)) { 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2521 2522 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2524 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2525 } else { 2526 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2528 } 2529 } else { 2530 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2531 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2532 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2533 } 2534 2535 /* 57XX step 36 */ 2536 /* Configure DMA resource watermarks */ 2537 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2538 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2539 2540 /* 5718 step 13, 57XX step 38 */ 2541 /* Enable buffer manager */ 2542 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2543 /* 2544 * Change the arbitration algorithm of TXMBUF read request to 2545 * round-robin instead of priority based for BCM5719. When 2546 * TXFIFO is almost empty, RDMA will hold its request until 2547 * TXFIFO is not almost empty. 2548 */ 2549 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2550 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2551 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2552 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2553 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2554 val |= BGE_BMANMODE_LOMBUF_ATTN; 2555 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2556 2557 /* 57XX step 39 */ 2558 /* Poll for buffer manager start indication */ 2559 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2560 DELAY(10); 2561 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2562 break; 2563 } 2564 2565 if (i == BGE_TIMEOUT * 2) { 2566 aprint_error_dev(sc->bge_dev, 2567 "buffer manager failed to start\n"); 2568 return ENXIO; 2569 } 2570 2571 /* 57XX step 40 */ 2572 /* Enable flow-through queues */ 2573 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2574 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2575 2576 /* Wait until queue initialization is complete */ 2577 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2578 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2579 break; 2580 DELAY(10); 2581 } 2582 2583 if (i == BGE_TIMEOUT * 2) { 2584 aprint_error_dev(sc->bge_dev, 2585 "flow-through queue init failed\n"); 2586 return ENXIO; 2587 } 2588 2589 /* 2590 * Summary of rings supported by the controller: 2591 * 2592 * Standard Receive Producer Ring 2593 * - This ring is used to feed receive buffers for "standard" 2594 * sized frames (typically 1536 bytes) to the controller. 2595 * 2596 * Jumbo Receive Producer Ring 2597 * - This ring is used to feed receive buffers for jumbo sized 2598 * frames (i.e. anything bigger than the "standard" frames) 2599 * to the controller. 2600 * 2601 * Mini Receive Producer Ring 2602 * - This ring is used to feed receive buffers for "mini" 2603 * sized frames to the controller. 2604 * - This feature required external memory for the controller 2605 * but was never used in a production system. Should always 2606 * be disabled. 2607 * 2608 * Receive Return Ring 2609 * - After the controller has placed an incoming frame into a 2610 * receive buffer that buffer is moved into a receive return 2611 * ring. The driver is then responsible to passing the 2612 * buffer up to the stack. Many versions of the controller 2613 * support multiple RR rings. 2614 * 2615 * Send Ring 2616 * - This ring is used for outgoing frames. Many versions of 2617 * the controller support multiple send rings. 2618 */ 2619 2620 /* 5718 step 15, 57XX step 41 */ 2621 /* Initialize the standard RX ring control block */ 2622 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2623 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2624 /* 5718 step 16 */ 2625 if (BGE_IS_5717_PLUS(sc)) { 2626 /* 2627 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2628 * Bits 15-2 : Maximum RX frame size 2629 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2630 * Bit 0 : Reserved 2631 */ 2632 rcb->bge_maxlen_flags = 2633 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2634 } else if (BGE_IS_5705_PLUS(sc)) { 2635 /* 2636 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2637 * Bits 15-2 : Reserved (should be 0) 2638 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2639 * Bit 0 : Reserved 2640 */ 2641 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2642 } else { 2643 /* 2644 * Ring size is always XXX entries 2645 * Bits 31-16: Maximum RX frame size 2646 * Bits 15-2 : Reserved (should be 0) 2647 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2648 * Bit 0 : Reserved 2649 */ 2650 rcb->bge_maxlen_flags = 2651 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2652 } 2653 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2654 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2655 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2656 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2657 else 2658 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2659 /* Write the standard receive producer ring control block. */ 2660 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2661 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2662 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2663 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2664 2665 /* Reset the standard receive producer ring producer index. */ 2666 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2667 2668 /* 57XX step 42 */ 2669 /* 2670 * Initialize the jumbo RX ring control block 2671 * We set the 'ring disabled' bit in the flags 2672 * field until we're actually ready to start 2673 * using this ring (i.e. once we set the MTU 2674 * high enough to require it). 2675 */ 2676 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2677 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2678 BGE_HOSTADDR(rcb->bge_hostaddr, 2679 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2680 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2681 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2682 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2683 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2684 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2685 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2686 else 2687 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2688 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2689 rcb->bge_hostaddr.bge_addr_hi); 2690 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2691 rcb->bge_hostaddr.bge_addr_lo); 2692 /* Program the jumbo receive producer ring RCB parameters. */ 2693 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2694 rcb->bge_maxlen_flags); 2695 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2696 /* Reset the jumbo receive producer ring producer index. */ 2697 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2698 } 2699 2700 /* 57XX step 43 */ 2701 /* Disable the mini receive producer ring RCB. */ 2702 if (BGE_IS_5700_FAMILY(sc)) { 2703 /* Set up dummy disabled mini ring RCB */ 2704 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2705 rcb->bge_maxlen_flags = 2706 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2707 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2708 rcb->bge_maxlen_flags); 2709 /* Reset the mini receive producer ring producer index. */ 2710 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2711 2712 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2713 offsetof(struct bge_ring_data, bge_info), 2714 sizeof (struct bge_gib), 2715 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2716 } 2717 2718 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2719 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2720 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2721 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2722 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2723 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2724 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2725 } 2726 /* 5718 step 14, 57XX step 44 */ 2727 /* 2728 * The BD ring replenish thresholds control how often the 2729 * hardware fetches new BD's from the producer rings in host 2730 * memory. Setting the value too low on a busy system can 2731 * starve the hardware and recue the throughpout. 2732 * 2733 * Set the BD ring replenish thresholds. The recommended 2734 * values are 1/8th the number of descriptors allocated to 2735 * each ring, but since we try to avoid filling the entire 2736 * ring we set these to the minimal value of 8. This needs to 2737 * be done on several of the supported chip revisions anyway, 2738 * to work around HW bugs. 2739 */ 2740 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2741 if (BGE_IS_JUMBO_CAPABLE(sc)) 2742 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2743 2744 /* 5718 step 18 */ 2745 if (BGE_IS_5717_PLUS(sc)) { 2746 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2747 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2748 } 2749 2750 /* 57XX step 45 */ 2751 /* 2752 * Disable all send rings by setting the 'ring disabled' bit 2753 * in the flags field of all the TX send ring control blocks, 2754 * located in NIC memory. 2755 */ 2756 if (BGE_IS_5700_FAMILY(sc)) { 2757 /* 5700 to 5704 had 16 send rings. */ 2758 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2759 } else 2760 limit = 1; 2761 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2762 for (i = 0; i < limit; i++) { 2763 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2764 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2765 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2766 rcb_addr += sizeof(struct bge_rcb); 2767 } 2768 2769 /* 57XX step 46 and 47 */ 2770 /* Configure send ring RCB 0 (we use only the first ring) */ 2771 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2772 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2773 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2774 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2775 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2776 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2777 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2778 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2779 else 2780 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2781 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2782 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2783 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2784 2785 /* 57XX step 48 */ 2786 /* 2787 * Disable all receive return rings by setting the 2788 * 'ring diabled' bit in the flags field of all the receive 2789 * return ring control blocks, located in NIC memory. 2790 */ 2791 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2792 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2793 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2794 /* Should be 17, use 16 until we get an SRAM map. */ 2795 limit = 16; 2796 } else if (BGE_IS_5700_FAMILY(sc)) 2797 limit = BGE_RX_RINGS_MAX; 2798 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2799 BGE_IS_57765_PLUS(sc)) 2800 limit = 4; 2801 else 2802 limit = 1; 2803 /* Disable all receive return rings */ 2804 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2805 for (i = 0; i < limit; i++) { 2806 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2807 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2808 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2809 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2810 BGE_RCB_FLAG_RING_DISABLED)); 2811 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2812 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2813 (i * (sizeof(uint64_t))), 0); 2814 rcb_addr += sizeof(struct bge_rcb); 2815 } 2816 2817 /* 57XX step 49 */ 2818 /* 2819 * Set up receive return ring 0. Note that the NIC address 2820 * for RX return rings is 0x0. The return rings live entirely 2821 * within the host, so the nicaddr field in the RCB isn't used. 2822 */ 2823 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2824 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2825 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2826 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2827 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2828 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2829 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2830 2831 /* 5718 step 24, 57XX step 53 */ 2832 /* Set random backoff seed for TX */ 2833 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2834 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2835 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2836 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2837 BGE_TX_BACKOFF_SEED_MASK); 2838 2839 /* 5718 step 26, 57XX step 55 */ 2840 /* Set inter-packet gap */ 2841 val = 0x2620; 2842 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2843 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2844 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2845 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2846 2847 /* 5718 step 27, 57XX step 56 */ 2848 /* 2849 * Specify which ring to use for packets that don't match 2850 * any RX rules. 2851 */ 2852 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2853 2854 /* 5718 step 28, 57XX step 57 */ 2855 /* 2856 * Configure number of RX lists. One interrupt distribution 2857 * list, sixteen active lists, one bad frames class. 2858 */ 2859 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2860 2861 /* 5718 step 29, 57XX step 58 */ 2862 /* Inialize RX list placement stats mask. */ 2863 if (BGE_IS_575X_PLUS(sc)) { 2864 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2865 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2866 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2867 } else 2868 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2869 2870 /* 5718 step 30, 57XX step 59 */ 2871 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2872 2873 /* 5718 step 33, 57XX step 62 */ 2874 /* Disable host coalescing until we get it set up */ 2875 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2876 2877 /* 5718 step 34, 57XX step 63 */ 2878 /* Poll to make sure it's shut down. */ 2879 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2880 DELAY(10); 2881 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2882 break; 2883 } 2884 2885 if (i == BGE_TIMEOUT * 2) { 2886 aprint_error_dev(sc->bge_dev, 2887 "host coalescing engine failed to idle\n"); 2888 return ENXIO; 2889 } 2890 2891 /* 5718 step 35, 36, 37 */ 2892 /* Set up host coalescing defaults */ 2893 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2894 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2895 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2896 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2897 if (!(BGE_IS_5705_PLUS(sc))) { 2898 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2899 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2900 } 2901 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2902 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2903 2904 /* Set up address of statistics block */ 2905 if (BGE_IS_5700_FAMILY(sc)) { 2906 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2907 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2908 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2909 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2910 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2911 } 2912 2913 /* 5718 step 38 */ 2914 /* Set up address of status block */ 2915 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2916 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2917 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2918 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2919 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2920 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2921 2922 /* Set up status block size. */ 2923 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2924 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2925 val = BGE_STATBLKSZ_FULL; 2926 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2927 } else { 2928 val = BGE_STATBLKSZ_32BYTE; 2929 bzero(&sc->bge_rdata->bge_status_block, 32); 2930 } 2931 2932 /* 5718 step 39, 57XX step 73 */ 2933 /* Turn on host coalescing state machine */ 2934 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2935 2936 /* 5718 step 40, 57XX step 74 */ 2937 /* Turn on RX BD completion state machine and enable attentions */ 2938 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2939 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2940 2941 /* 5718 step 41, 57XX step 75 */ 2942 /* Turn on RX list placement state machine */ 2943 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2944 2945 /* 57XX step 76 */ 2946 /* Turn on RX list selector state machine. */ 2947 if (!(BGE_IS_5705_PLUS(sc))) 2948 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2949 2950 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2951 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2952 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2953 BGE_MACMODE_FRMHDR_DMA_ENB; 2954 2955 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2956 val |= BGE_PORTMODE_TBI; 2957 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2958 val |= BGE_PORTMODE_GMII; 2959 else 2960 val |= BGE_PORTMODE_MII; 2961 2962 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2963 /* Allow APE to send/receive frames. */ 2964 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2965 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2966 2967 /* Turn on DMA, clear stats */ 2968 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2969 /* 5718 step 44 */ 2970 DELAY(40); 2971 2972 /* 5718 step 45, 57XX step 79 */ 2973 /* Set misc. local control, enable interrupts on attentions */ 2974 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2975 if (BGE_IS_5717_PLUS(sc)) { 2976 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2977 /* 5718 step 46 */ 2978 DELAY(100); 2979 } 2980 2981 /* 57XX step 81 */ 2982 /* Turn on DMA completion state machine */ 2983 if (!(BGE_IS_5705_PLUS(sc))) 2984 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2985 2986 /* 5718 step 47, 57XX step 82 */ 2987 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2988 2989 /* 5718 step 48 */ 2990 /* Enable host coalescing bug fix. */ 2991 if (BGE_IS_5755_PLUS(sc)) 2992 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2993 2994 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2995 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2996 2997 /* Turn on write DMA state machine */ 2998 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2999 /* 5718 step 49 */ 3000 DELAY(40); 3001 3002 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3003 3004 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3005 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3006 3007 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3008 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3009 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3010 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3011 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3012 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3013 3014 if (sc->bge_flags & BGE_PCIE) 3015 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3016 if (sc->bge_flags & BGE_TSO) 3017 val |= BGE_RDMAMODE_TSO4_ENABLE; 3018 3019 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3020 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3021 BGE_RDMAMODE_H2BNC_VLAN_DET; 3022 /* 3023 * Allow multiple outstanding read requests from 3024 * non-LSO read DMA engine. 3025 */ 3026 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3027 } 3028 3029 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3030 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3031 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3032 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3033 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 3034 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3035 /* 3036 * Adjust tx margin to prevent TX data corruption and 3037 * fix internal FIFO overflow. 3038 */ 3039 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3040 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3041 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3042 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3043 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3044 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3045 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3046 } 3047 /* 3048 * Enable fix for read DMA FIFO overruns. 3049 * The fix is to limit the number of RX BDs 3050 * the hardware would fetch at a fime. 3051 */ 3052 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3053 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3054 } 3055 3056 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3057 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3058 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3059 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3060 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3061 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3062 /* 3063 * Allow 4KB burst length reads for non-LSO frames. 3064 * Enable 512B burst length reads for buffer descriptors. 3065 */ 3066 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3067 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3068 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3069 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3070 } 3071 3072 /* Turn on read DMA state machine */ 3073 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3074 /* 5718 step 52 */ 3075 delay(40); 3076 3077 /* 5718 step 56, 57XX step 84 */ 3078 /* Turn on RX data completion state machine */ 3079 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3080 3081 /* Turn on RX data and RX BD initiator state machine */ 3082 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3083 3084 /* 57XX step 85 */ 3085 /* Turn on Mbuf cluster free state machine */ 3086 if (!BGE_IS_5705_PLUS(sc)) 3087 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3088 3089 /* 5718 step 57, 57XX step 86 */ 3090 /* Turn on send data completion state machine */ 3091 val = BGE_SDCMODE_ENABLE; 3092 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3093 val |= BGE_SDCMODE_CDELAY; 3094 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3095 3096 /* 5718 step 58 */ 3097 /* Turn on send BD completion state machine */ 3098 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3099 3100 /* 57XX step 88 */ 3101 /* Turn on RX BD initiator state machine */ 3102 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3103 3104 /* 5718 step 60, 57XX step 90 */ 3105 /* Turn on send data initiator state machine */ 3106 if (sc->bge_flags & BGE_TSO) { 3107 /* XXX: magic value from Linux driver */ 3108 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3109 BGE_SDIMODE_HW_LSO_PRE_DMA); 3110 } else 3111 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3112 3113 /* 5718 step 61, 57XX step 91 */ 3114 /* Turn on send BD initiator state machine */ 3115 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3116 3117 /* 5718 step 62, 57XX step 92 */ 3118 /* Turn on send BD selector state machine */ 3119 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3120 3121 /* 5718 step 31, 57XX step 60 */ 3122 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3123 /* 5718 step 32, 57XX step 61 */ 3124 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3125 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3126 3127 /* ack/clear link change events */ 3128 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3129 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3130 BGE_MACSTAT_LINK_CHANGED); 3131 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3132 3133 /* 3134 * Enable attention when the link has changed state for 3135 * devices that use auto polling. 3136 */ 3137 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3138 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3139 } else { 3140 /* 5718 step 68 */ 3141 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3142 /* 5718 step 69 (optionally) */ 3143 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3144 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3145 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3146 BGE_EVTENB_MI_INTERRUPT); 3147 } 3148 3149 /* 3150 * Clear any pending link state attention. 3151 * Otherwise some link state change events may be lost until attention 3152 * is cleared by bge_intr() -> bge_link_upd() sequence. 3153 * It's not necessary on newer BCM chips - perhaps enabling link 3154 * state change attentions implies clearing pending attention. 3155 */ 3156 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3157 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3158 BGE_MACSTAT_LINK_CHANGED); 3159 3160 /* Enable link state change attentions. */ 3161 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3162 3163 return 0; 3164 } 3165 3166 static const struct bge_revision * 3167 bge_lookup_rev(uint32_t chipid) 3168 { 3169 const struct bge_revision *br; 3170 3171 for (br = bge_revisions; br->br_name != NULL; br++) { 3172 if (br->br_chipid == chipid) 3173 return br; 3174 } 3175 3176 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3177 if (br->br_chipid == BGE_ASICREV(chipid)) 3178 return br; 3179 } 3180 3181 return NULL; 3182 } 3183 3184 static const struct bge_product * 3185 bge_lookup(const struct pci_attach_args *pa) 3186 { 3187 const struct bge_product *bp; 3188 3189 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3190 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3191 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3192 return bp; 3193 } 3194 3195 return NULL; 3196 } 3197 3198 static uint32_t 3199 bge_chipid(const struct pci_attach_args *pa) 3200 { 3201 uint32_t id; 3202 3203 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3204 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3205 3206 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3207 switch (PCI_PRODUCT(pa->pa_id)) { 3208 case PCI_PRODUCT_BROADCOM_BCM5717: 3209 case PCI_PRODUCT_BROADCOM_BCM5718: 3210 case PCI_PRODUCT_BROADCOM_BCM5719: 3211 case PCI_PRODUCT_BROADCOM_BCM5720: 3212 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3213 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3214 BGE_PCI_GEN2_PRODID_ASICREV); 3215 break; 3216 case PCI_PRODUCT_BROADCOM_BCM57761: 3217 case PCI_PRODUCT_BROADCOM_BCM57762: 3218 case PCI_PRODUCT_BROADCOM_BCM57765: 3219 case PCI_PRODUCT_BROADCOM_BCM57766: 3220 case PCI_PRODUCT_BROADCOM_BCM57781: 3221 case PCI_PRODUCT_BROADCOM_BCM57785: 3222 case PCI_PRODUCT_BROADCOM_BCM57791: 3223 case PCI_PRODUCT_BROADCOM_BCM57795: 3224 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3225 BGE_PCI_GEN15_PRODID_ASICREV); 3226 break; 3227 default: 3228 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3229 BGE_PCI_PRODID_ASICREV); 3230 break; 3231 } 3232 } 3233 3234 return id; 3235 } 3236 3237 /* 3238 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3239 * against our list and return its name if we find a match. Note 3240 * that since the Broadcom controller contains VPD support, we 3241 * can get the device name string from the controller itself instead 3242 * of the compiled-in string. This is a little slow, but it guarantees 3243 * we'll always announce the right product name. 3244 */ 3245 static int 3246 bge_probe(device_t parent, cfdata_t match, void *aux) 3247 { 3248 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3249 3250 if (bge_lookup(pa) != NULL) 3251 return 1; 3252 3253 return 0; 3254 } 3255 3256 static void 3257 bge_attach(device_t parent, device_t self, void *aux) 3258 { 3259 struct bge_softc *sc = device_private(self); 3260 struct pci_attach_args *pa = aux; 3261 prop_dictionary_t dict; 3262 const struct bge_product *bp; 3263 const struct bge_revision *br; 3264 pci_chipset_tag_t pc; 3265 pci_intr_handle_t ih; 3266 const char *intrstr = NULL; 3267 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4; 3268 uint32_t command; 3269 struct ifnet *ifp; 3270 uint32_t misccfg, mimode; 3271 void * kva; 3272 u_char eaddr[ETHER_ADDR_LEN]; 3273 pcireg_t memtype, subid, reg; 3274 bus_addr_t memaddr; 3275 uint32_t pm_ctl; 3276 bool no_seeprom; 3277 int capmask; 3278 3279 bp = bge_lookup(pa); 3280 KASSERT(bp != NULL); 3281 3282 sc->sc_pc = pa->pa_pc; 3283 sc->sc_pcitag = pa->pa_tag; 3284 sc->bge_dev = self; 3285 3286 sc->bge_pa = *pa; 3287 pc = sc->sc_pc; 3288 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3289 3290 aprint_naive(": Ethernet controller\n"); 3291 aprint_normal(": %s\n", bp->bp_name); 3292 3293 /* 3294 * Map control/status registers. 3295 */ 3296 DPRINTFN(5, ("Map control/status regs\n")); 3297 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3298 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3299 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3300 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3301 3302 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3303 aprint_error_dev(sc->bge_dev, 3304 "failed to enable memory mapping!\n"); 3305 return; 3306 } 3307 3308 DPRINTFN(5, ("pci_mem_find\n")); 3309 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3310 switch (memtype) { 3311 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3312 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3313 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3314 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3315 &memaddr, &sc->bge_bsize) == 0) 3316 break; 3317 default: 3318 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3319 return; 3320 } 3321 3322 DPRINTFN(5, ("pci_intr_map\n")); 3323 if (pci_intr_map(pa, &ih)) { 3324 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3325 return; 3326 } 3327 3328 DPRINTFN(5, ("pci_intr_string\n")); 3329 intrstr = pci_intr_string(pc, ih); 3330 3331 DPRINTFN(5, ("pci_intr_establish\n")); 3332 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3333 3334 if (sc->bge_intrhand == NULL) { 3335 aprint_error_dev(sc->bge_dev, 3336 "couldn't establish interrupt%s%s\n", 3337 intrstr ? " at " : "", intrstr ? intrstr : ""); 3338 return; 3339 } 3340 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3341 3342 /* Save various chip information. */ 3343 sc->bge_chipid = bge_chipid(pa); 3344 sc->bge_phy_addr = bge_phy_addr(sc); 3345 3346 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3347 &sc->bge_pciecap, NULL) != 0) 3348 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3349 /* PCIe */ 3350 sc->bge_flags |= BGE_PCIE; 3351 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3352 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3353 sc->bge_expmrq = 2048; 3354 else 3355 sc->bge_expmrq = 4096; 3356 bge_set_max_readrq(sc); 3357 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3358 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3359 /* PCI-X */ 3360 sc->bge_flags |= BGE_PCIX; 3361 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3362 &sc->bge_pcixcap, NULL) == 0) 3363 aprint_error_dev(sc->bge_dev, 3364 "unable to find PCIX capability\n"); 3365 } 3366 3367 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3368 /* 3369 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3370 * can clobber the chip's PCI config-space power control 3371 * registers, leaving the card in D3 powersave state. We do 3372 * not have memory-mapped registers in this state, so force 3373 * device into D0 state before starting initialization. 3374 */ 3375 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3376 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3377 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3378 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3379 DELAY(1000); /* 27 usec is allegedly sufficent */ 3380 } 3381 3382 /* Save chipset family. */ 3383 switch (BGE_ASICREV(sc->bge_chipid)) { 3384 case BGE_ASICREV_BCM57765: 3385 case BGE_ASICREV_BCM57766: 3386 sc->bge_flags |= BGE_57765_PLUS; 3387 /* FALLTHROUGH */ 3388 case BGE_ASICREV_BCM5717: 3389 case BGE_ASICREV_BCM5719: 3390 case BGE_ASICREV_BCM5720: 3391 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 3392 BGE_5705_PLUS; 3393 break; 3394 case BGE_ASICREV_BCM5755: 3395 case BGE_ASICREV_BCM5761: 3396 case BGE_ASICREV_BCM5784: 3397 case BGE_ASICREV_BCM5785: 3398 case BGE_ASICREV_BCM5787: 3399 case BGE_ASICREV_BCM57780: 3400 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3401 break; 3402 case BGE_ASICREV_BCM5700: 3403 case BGE_ASICREV_BCM5701: 3404 case BGE_ASICREV_BCM5703: 3405 case BGE_ASICREV_BCM5704: 3406 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3407 break; 3408 case BGE_ASICREV_BCM5714_A0: 3409 case BGE_ASICREV_BCM5780: 3410 case BGE_ASICREV_BCM5714: 3411 sc->bge_flags |= BGE_5714_FAMILY; 3412 /* FALLTHROUGH */ 3413 case BGE_ASICREV_BCM5750: 3414 case BGE_ASICREV_BCM5752: 3415 case BGE_ASICREV_BCM5906: 3416 sc->bge_flags |= BGE_575X_PLUS; 3417 /* FALLTHROUGH */ 3418 case BGE_ASICREV_BCM5705: 3419 sc->bge_flags |= BGE_5705_PLUS; 3420 break; 3421 } 3422 3423 /* Identify chips with APE processor. */ 3424 switch (BGE_ASICREV(sc->bge_chipid)) { 3425 case BGE_ASICREV_BCM5717: 3426 case BGE_ASICREV_BCM5719: 3427 case BGE_ASICREV_BCM5720: 3428 case BGE_ASICREV_BCM5761: 3429 sc->bge_flags |= BGE_APE; 3430 break; 3431 } 3432 3433 /* Chips with APE need BAR2 access for APE registers/memory. */ 3434 if ((sc->bge_flags & BGE_APE) != 0) { 3435 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3436 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3437 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3438 &sc->bge_apesize)) { 3439 aprint_error_dev(sc->bge_dev, 3440 "couldn't map BAR2 memory\n"); 3441 return; 3442 } 3443 3444 /* Enable APE register/memory access by host driver. */ 3445 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3446 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3447 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3448 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3449 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3450 3451 bge_ape_lock_init(sc); 3452 bge_ape_read_fw_ver(sc); 3453 } 3454 3455 /* Identify the chips that use an CPMU. */ 3456 if (BGE_IS_5717_PLUS(sc) || 3457 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3458 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3459 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3460 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3461 sc->bge_flags |= BGE_CPMU_PRESENT; 3462 3463 /* Set MI_MODE */ 3464 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3465 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3466 mimode |= BGE_MIMODE_500KHZ_CONST; 3467 else 3468 mimode |= BGE_MIMODE_BASE; 3469 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3470 3471 /* 3472 * When using the BCM5701 in PCI-X mode, data corruption has 3473 * been observed in the first few bytes of some received packets. 3474 * Aligning the packet buffer in memory eliminates the corruption. 3475 * Unfortunately, this misaligns the packet payloads. On platforms 3476 * which do not support unaligned accesses, we will realign the 3477 * payloads by copying the received packets. 3478 */ 3479 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3480 sc->bge_flags & BGE_PCIX) 3481 sc->bge_flags |= BGE_RX_ALIGNBUG; 3482 3483 if (BGE_IS_5700_FAMILY(sc)) 3484 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3485 3486 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3487 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3488 3489 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3490 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3491 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3492 sc->bge_flags |= BGE_IS_5788; 3493 3494 /* 3495 * Some controllers seem to require a special firmware to use 3496 * TSO. But the firmware is not available to FreeBSD and Linux 3497 * claims that the TSO performed by the firmware is slower than 3498 * hardware based TSO. Moreover the firmware based TSO has one 3499 * known bug which can't handle TSO if ethernet header + IP/TCP 3500 * header is greater than 80 bytes. The workaround for the TSO 3501 * bug exist but it seems it's too expensive than not using 3502 * TSO at all. Some hardwares also have the TSO bug so limit 3503 * the TSO to the controllers that are not affected TSO issues 3504 * (e.g. 5755 or higher). 3505 */ 3506 if (BGE_IS_5755_PLUS(sc)) { 3507 /* 3508 * BCM5754 and BCM5787 shares the same ASIC id so 3509 * explicit device id check is required. 3510 */ 3511 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3512 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3513 sc->bge_flags |= BGE_TSO; 3514 } 3515 3516 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3517 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3518 (misccfg == 0x4000 || misccfg == 0x8000)) || 3519 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3520 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3521 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3522 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3523 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3524 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3525 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3526 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3527 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3528 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3529 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3530 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3531 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3532 capmask &= ~BMSR_EXTSTAT; 3533 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3534 } 3535 3536 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3537 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3538 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3539 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3540 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3541 3542 /* Set various PHY bug flags. */ 3543 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3544 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3545 sc->bge_flags |= BGE_PHY_CRC_BUG; 3546 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3547 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3548 sc->bge_flags |= BGE_PHY_ADC_BUG; 3549 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3550 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3551 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3552 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3553 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3554 sc->bge_flags |= BGE_PHY_NO_3LED; 3555 if (BGE_IS_5705_PLUS(sc) && 3556 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3557 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3558 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3559 !BGE_IS_5717_PLUS(sc)) { 3560 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3561 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3562 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3563 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3564 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3565 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3566 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3567 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3568 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3569 } else 3570 sc->bge_flags |= BGE_PHY_BER_BUG; 3571 } 3572 3573 /* 3574 * SEEPROM check. 3575 * First check if firmware knows we do not have SEEPROM. 3576 */ 3577 if (prop_dictionary_get_bool(device_properties(self), 3578 "without-seeprom", &no_seeprom) && no_seeprom) 3579 sc->bge_flags |= BGE_NO_EEPROM; 3580 3581 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3582 sc->bge_flags |= BGE_NO_EEPROM; 3583 3584 /* Now check the 'ROM failed' bit on the RX CPU */ 3585 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3586 sc->bge_flags |= BGE_NO_EEPROM; 3587 3588 sc->bge_asf_mode = 0; 3589 /* No ASF if APE present. */ 3590 if ((sc->bge_flags & BGE_APE) == 0) { 3591 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3592 BGE_SRAM_DATA_SIG_MAGIC)) { 3593 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3594 BGE_HWCFG_ASF) { 3595 sc->bge_asf_mode |= ASF_ENABLE; 3596 sc->bge_asf_mode |= ASF_STACKUP; 3597 if (BGE_IS_575X_PLUS(sc)) 3598 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3599 } 3600 } 3601 } 3602 3603 /* 3604 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3605 * lock in bge_reset(). 3606 */ 3607 CSR_WRITE_4(sc, BGE_EE_ADDR, 3608 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3609 delay(1000); 3610 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3611 3612 bge_stop_fw(sc); 3613 bge_sig_pre_reset(sc, BGE_RESET_START); 3614 if (bge_reset(sc)) 3615 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3616 3617 /* 3618 * Read the hardware config word in the first 32k of NIC internal 3619 * memory, or fall back to the config word in the EEPROM. 3620 * Note: on some BCM5700 cards, this value appears to be unset. 3621 */ 3622 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = 0; 3623 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3624 BGE_SRAM_DATA_SIG_MAGIC) { 3625 uint32_t tmp; 3626 3627 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3628 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3629 BGE_SRAM_DATA_VER_SHIFT; 3630 if ((0 < tmp) && (tmp < 0x100)) 3631 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3632 if (sc->bge_flags & BGE_PCIE) 3633 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3634 if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) 3635 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3636 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3637 bge_read_eeprom(sc, (void *)&hwcfg, 3638 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3639 hwcfg = be32toh(hwcfg); 3640 } 3641 aprint_normal_dev(sc->bge_dev, "HW config %08x, %08x, %08x, %08x\n", 3642 hwcfg, hwcfg2, hwcfg3, hwcfg4); 3643 3644 bge_sig_legacy(sc, BGE_RESET_START); 3645 bge_sig_post_reset(sc, BGE_RESET_START); 3646 3647 if (bge_chipinit(sc)) { 3648 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3649 bge_release_resources(sc); 3650 return; 3651 } 3652 3653 /* 3654 * Get station address from the EEPROM. 3655 */ 3656 if (bge_get_eaddr(sc, eaddr)) { 3657 aprint_error_dev(sc->bge_dev, 3658 "failed to read station address\n"); 3659 bge_release_resources(sc); 3660 return; 3661 } 3662 3663 br = bge_lookup_rev(sc->bge_chipid); 3664 3665 if (br == NULL) { 3666 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3667 sc->bge_chipid); 3668 } else { 3669 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3670 br->br_name, sc->bge_chipid); 3671 } 3672 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3673 3674 /* Allocate the general information block and ring buffers. */ 3675 if (pci_dma64_available(pa)) 3676 sc->bge_dmatag = pa->pa_dmat64; 3677 else 3678 sc->bge_dmatag = pa->pa_dmat; 3679 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3680 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3681 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3682 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3683 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3684 return; 3685 } 3686 DPRINTFN(5, ("bus_dmamem_map\n")); 3687 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3688 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3689 BUS_DMA_NOWAIT)) { 3690 aprint_error_dev(sc->bge_dev, 3691 "can't map DMA buffers (%zu bytes)\n", 3692 sizeof(struct bge_ring_data)); 3693 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3694 sc->bge_ring_rseg); 3695 return; 3696 } 3697 DPRINTFN(5, ("bus_dmamem_create\n")); 3698 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3699 sizeof(struct bge_ring_data), 0, 3700 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3701 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3702 bus_dmamem_unmap(sc->bge_dmatag, kva, 3703 sizeof(struct bge_ring_data)); 3704 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3705 sc->bge_ring_rseg); 3706 return; 3707 } 3708 DPRINTFN(5, ("bus_dmamem_load\n")); 3709 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3710 sizeof(struct bge_ring_data), NULL, 3711 BUS_DMA_NOWAIT)) { 3712 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3713 bus_dmamem_unmap(sc->bge_dmatag, kva, 3714 sizeof(struct bge_ring_data)); 3715 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3716 sc->bge_ring_rseg); 3717 return; 3718 } 3719 3720 DPRINTFN(5, ("bzero\n")); 3721 sc->bge_rdata = (struct bge_ring_data *)kva; 3722 3723 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3724 3725 /* Try to allocate memory for jumbo buffers. */ 3726 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3727 if (bge_alloc_jumbo_mem(sc)) { 3728 aprint_error_dev(sc->bge_dev, 3729 "jumbo buffer allocation failed\n"); 3730 } else 3731 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3732 } 3733 3734 /* Set default tuneable values. */ 3735 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3736 sc->bge_rx_coal_ticks = 150; 3737 sc->bge_rx_max_coal_bds = 64; 3738 sc->bge_tx_coal_ticks = 300; 3739 sc->bge_tx_max_coal_bds = 400; 3740 if (BGE_IS_5705_PLUS(sc)) { 3741 sc->bge_tx_coal_ticks = (12 * 5); 3742 sc->bge_tx_max_coal_bds = (12 * 5); 3743 aprint_verbose_dev(sc->bge_dev, 3744 "setting short Tx thresholds\n"); 3745 } 3746 3747 if (BGE_IS_5717_PLUS(sc)) 3748 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3749 else if (BGE_IS_5705_PLUS(sc)) 3750 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3751 else 3752 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3753 3754 /* Set up ifnet structure */ 3755 ifp = &sc->ethercom.ec_if; 3756 ifp->if_softc = sc; 3757 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3758 ifp->if_ioctl = bge_ioctl; 3759 ifp->if_stop = bge_stop; 3760 ifp->if_start = bge_start; 3761 ifp->if_init = bge_init; 3762 ifp->if_watchdog = bge_watchdog; 3763 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3764 IFQ_SET_READY(&ifp->if_snd); 3765 DPRINTFN(5, ("strcpy if_xname\n")); 3766 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3767 3768 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3769 sc->ethercom.ec_if.if_capabilities |= 3770 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3771 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3772 sc->ethercom.ec_if.if_capabilities |= 3773 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3774 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3775 #endif 3776 sc->ethercom.ec_capabilities |= 3777 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3778 3779 if (sc->bge_flags & BGE_TSO) 3780 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3781 3782 /* 3783 * Do MII setup. 3784 */ 3785 DPRINTFN(5, ("mii setup\n")); 3786 sc->bge_mii.mii_ifp = ifp; 3787 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3788 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3789 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3790 3791 /* 3792 * Figure out what sort of media we have by checking the hardware 3793 * config word. Note: on some BCM5700 cards, this value appears to be 3794 * unset. If that's the case, we have to rely on identifying the NIC 3795 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3796 * The SysKonnect SK-9D41 is a 1000baseSX card. 3797 */ 3798 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3799 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3800 if (BGE_IS_5714_FAMILY(sc)) 3801 sc->bge_flags |= BGE_PHY_FIBER_MII; 3802 else 3803 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3804 } 3805 3806 /* set phyflags and chipid before mii_attach() */ 3807 dict = device_properties(self); 3808 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3809 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3810 3811 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3812 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3813 bge_ifmedia_sts); 3814 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3815 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3816 0, NULL); 3817 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3818 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3819 /* Pretend the user requested this setting */ 3820 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3821 } else { 3822 /* 3823 * Do transceiver setup and tell the firmware the 3824 * driver is down so we can try to get access the 3825 * probe if ASF is running. Retry a couple of times 3826 * if we get a conflict with the ASF firmware accessing 3827 * the PHY. 3828 */ 3829 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3830 bge_asf_driver_up(sc); 3831 3832 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3833 bge_ifmedia_sts); 3834 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3835 sc->bge_phy_addr, MII_OFFSET_ANY, 3836 MIIF_DOPAUSE); 3837 3838 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3839 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3840 ifmedia_add(&sc->bge_mii.mii_media, 3841 IFM_ETHER|IFM_MANUAL, 0, NULL); 3842 ifmedia_set(&sc->bge_mii.mii_media, 3843 IFM_ETHER|IFM_MANUAL); 3844 } else 3845 ifmedia_set(&sc->bge_mii.mii_media, 3846 IFM_ETHER|IFM_AUTO); 3847 3848 /* 3849 * Now tell the firmware we are going up after probing the PHY 3850 */ 3851 if (sc->bge_asf_mode & ASF_STACKUP) 3852 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3853 } 3854 3855 /* 3856 * Call MI attach routine. 3857 */ 3858 DPRINTFN(5, ("if_attach\n")); 3859 if_attach(ifp); 3860 DPRINTFN(5, ("ether_ifattach\n")); 3861 ether_ifattach(ifp, eaddr); 3862 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3863 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3864 RND_TYPE_NET, 0); 3865 #ifdef BGE_EVENT_COUNTERS 3866 /* 3867 * Attach event counters. 3868 */ 3869 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3870 NULL, device_xname(sc->bge_dev), "intr"); 3871 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3872 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3873 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3874 NULL, device_xname(sc->bge_dev), "tx_xon"); 3875 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3876 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3877 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3878 NULL, device_xname(sc->bge_dev), "rx_xon"); 3879 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3880 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3881 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3882 NULL, device_xname(sc->bge_dev), "xoffentered"); 3883 #endif /* BGE_EVENT_COUNTERS */ 3884 DPRINTFN(5, ("callout_init\n")); 3885 callout_init(&sc->bge_timeout, 0); 3886 3887 if (pmf_device_register(self, NULL, NULL)) 3888 pmf_class_network_register(self, ifp); 3889 else 3890 aprint_error_dev(self, "couldn't establish power handler\n"); 3891 3892 bge_sysctl_init(sc); 3893 3894 #ifdef BGE_DEBUG 3895 bge_debug_info(sc); 3896 #endif 3897 } 3898 3899 /* 3900 * Stop all chip I/O so that the kernel's probe routines don't 3901 * get confused by errant DMAs when rebooting. 3902 */ 3903 static int 3904 bge_detach(device_t self, int flags __unused) 3905 { 3906 struct bge_softc *sc = device_private(self); 3907 struct ifnet *ifp = &sc->ethercom.ec_if; 3908 int s; 3909 3910 s = splnet(); 3911 /* Stop the interface. Callouts are stopped in it. */ 3912 bge_stop(ifp, 1); 3913 splx(s); 3914 3915 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3916 3917 /* Delete all remaining media. */ 3918 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3919 3920 ether_ifdetach(ifp); 3921 if_detach(ifp); 3922 3923 bge_release_resources(sc); 3924 3925 return 0; 3926 } 3927 3928 static void 3929 bge_release_resources(struct bge_softc *sc) 3930 { 3931 3932 /* Disestablish the interrupt handler */ 3933 if (sc->bge_intrhand != NULL) { 3934 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3935 sc->bge_intrhand = NULL; 3936 } 3937 3938 if (sc->bge_dmatag != NULL) { 3939 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3940 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3941 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3942 sizeof(struct bge_ring_data)); 3943 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3944 } 3945 3946 /* Unmap the device registers */ 3947 if (sc->bge_bsize != 0) { 3948 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3949 sc->bge_bsize = 0; 3950 } 3951 3952 /* Unmap the APE registers */ 3953 if (sc->bge_apesize != 0) { 3954 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3955 sc->bge_apesize); 3956 sc->bge_apesize = 0; 3957 } 3958 } 3959 3960 static int 3961 bge_reset(struct bge_softc *sc) 3962 { 3963 uint32_t cachesize, command; 3964 uint32_t reset, mac_mode, mac_mode_mask; 3965 pcireg_t devctl, reg; 3966 int i, val; 3967 void (*write_op)(struct bge_softc *, int, int); 3968 3969 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3970 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3971 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3972 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & ~mac_mode_mask; 3973 3974 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3975 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3976 if (sc->bge_flags & BGE_PCIE) 3977 write_op = bge_writemem_direct; 3978 else 3979 write_op = bge_writemem_ind; 3980 } else 3981 write_op = bge_writereg_ind; 3982 3983 /* 57XX step 4 */ 3984 /* Acquire the NVM lock */ 3985 if ((sc->bge_flags & BGE_NO_EEPROM) == 0 && 3986 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3987 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3988 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3989 for (i = 0; i < 8000; i++) { 3990 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3991 BGE_NVRAMSWARB_GNT1) 3992 break; 3993 DELAY(20); 3994 } 3995 if (i == 8000) { 3996 printf("%s: NVRAM lock timedout!\n", 3997 device_xname(sc->bge_dev)); 3998 } 3999 } 4000 4001 /* Take APE lock when performing reset. */ 4002 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4003 4004 /* 57XX step 3 */ 4005 /* Save some important PCI state. */ 4006 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4007 /* 5718 reset step 3 */ 4008 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4009 4010 /* 5718 reset step 5, 57XX step 5b-5d */ 4011 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4012 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4013 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4014 4015 /* XXX ???: Disable fastboot on controllers that support it. */ 4016 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4017 BGE_IS_5755_PLUS(sc)) 4018 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4019 4020 /* 5718 reset step 2, 57XX step 6 */ 4021 /* 4022 * Write the magic number to SRAM at offset 0xB50. 4023 * When firmware finishes its initialization it will 4024 * write ~BGE_MAGIC_NUMBER to the same location. 4025 */ 4026 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4027 4028 /* 5718 reset step 6, 57XX step 7 */ 4029 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4030 /* 4031 * XXX: from FreeBSD/Linux; no documentation 4032 */ 4033 if (sc->bge_flags & BGE_PCIE) { 4034 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 4035 !BGE_IS_57765_PLUS(sc) && 4036 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4037 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4038 /* PCI Express 1.0 system */ 4039 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4040 BGE_PHY_PCIE_SCRAM_MODE); 4041 } 4042 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4043 /* 4044 * Prevent PCI Express link training 4045 * during global reset. 4046 */ 4047 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4048 reset |= (1 << 29); 4049 } 4050 } 4051 4052 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4053 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4054 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4055 i | BGE_VCPU_STATUS_DRV_RESET); 4056 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4057 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4058 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4059 } 4060 4061 /* 4062 * Set GPHY Power Down Override to leave GPHY 4063 * powered up in D0 uninitialized. 4064 */ 4065 if (BGE_IS_5705_PLUS(sc) && 4066 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4067 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4068 4069 /* Issue global reset */ 4070 write_op(sc, BGE_MISC_CFG, reset); 4071 4072 /* 5718 reset step 7, 57XX step 8 */ 4073 if (sc->bge_flags & BGE_PCIE) 4074 delay(100*1000); /* too big */ 4075 else 4076 delay(1000); 4077 4078 if (sc->bge_flags & BGE_PCIE) { 4079 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4080 DELAY(500000); 4081 /* XXX: Magic Numbers */ 4082 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4083 BGE_PCI_UNKNOWN0); 4084 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4085 BGE_PCI_UNKNOWN0, 4086 reg | (1 << 15)); 4087 } 4088 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4089 sc->bge_pciecap + PCIE_DCSR); 4090 /* Clear enable no snoop and disable relaxed ordering. */ 4091 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4092 PCIE_DCSR_ENA_NO_SNOOP); 4093 4094 /* Set PCIE max payload size to 128 for older PCIe devices */ 4095 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4096 devctl &= ~(0x00e0); 4097 /* Clear device status register. Write 1b to clear */ 4098 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4099 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4100 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4101 sc->bge_pciecap + PCIE_DCSR, devctl); 4102 bge_set_max_readrq(sc); 4103 } 4104 4105 /* From Linux: dummy read to flush PCI posted writes */ 4106 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4107 4108 /* 4109 * Reset some of the PCI state that got zapped by reset 4110 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4111 * set, too. 4112 */ 4113 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4114 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4115 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4116 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4117 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4118 (sc->bge_flags & BGE_PCIX) != 0) 4119 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4120 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4121 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4122 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4123 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4124 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4125 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4126 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4127 4128 /* Step 11: disable PCI-X Relaxed Ordering. */ 4129 if (sc->bge_flags & BGE_PCIX) { 4130 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4131 + PCIX_CMD); 4132 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4133 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4134 } 4135 4136 /* 5718 reset step 10, 57XX step 12 */ 4137 /* Enable memory arbiter. */ 4138 if (BGE_IS_5714_FAMILY(sc)) { 4139 val = CSR_READ_4(sc, BGE_MARB_MODE); 4140 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4141 } else 4142 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4143 4144 /* XXX 5721, 5751 and 5752 */ 4145 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4146 /* Step 19: */ 4147 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4148 /* Step 20: */ 4149 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4150 } 4151 4152 /* 5718 reset step 12, 57XX step 15 and 16 */ 4153 /* Fix up byte swapping */ 4154 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4155 4156 /* 5718 reset step 13, 57XX step 17 */ 4157 /* 4158 * Wait for the bootcode to complete initialization. 4159 * See BCM5718 programmer's guide's "step 13, Device reset Procedure, 4160 * Section 7". For 57XX, it's optional. 4161 */ 4162 if (BGE_IS_5717_PLUS(sc)) { 4163 for (i = 0; i < 1000*1000; i++) { 4164 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4165 if (val == BGE_SRAM_FW_MB_RESET_MAGIC) 4166 break; 4167 DELAY(10); 4168 } 4169 } 4170 4171 /* 57XX step 21 */ 4172 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4173 pcireg_t msidata; 4174 4175 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4176 BGE_PCI_MSI_DATA); 4177 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4178 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4179 msidata); 4180 } 4181 4182 /* 57XX step 18 */ 4183 /* Write mac mode. 4184 * XXX Write 0x0c for 5703S and 5704S 4185 */ 4186 val = CSR_READ_4(sc, BGE_MAC_MODE); 4187 val = (val & ~mac_mode_mask) | mac_mode; 4188 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4189 DELAY(40); 4190 4191 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4192 4193 /* 57XX step 17 */ 4194 /* Poll until the firmware initialization is complete */ 4195 bge_poll_fw(sc); 4196 4197 /* 4198 * The 5704 in TBI mode apparently needs some special 4199 * adjustment to insure the SERDES drive level is set 4200 * to 1.2V. 4201 */ 4202 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4203 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4204 uint32_t serdescfg; 4205 4206 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4207 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4208 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4209 } 4210 4211 if (sc->bge_flags & BGE_PCIE && 4212 !BGE_IS_57765_PLUS(sc) && 4213 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4214 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4215 uint32_t v; 4216 4217 /* Enable PCI Express bug fix */ 4218 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4219 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4220 v | BGE_TLP_DATA_FIFO_PROTECT); 4221 } 4222 4223 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4224 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4225 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4226 4227 return 0; 4228 } 4229 4230 /* 4231 * Frame reception handling. This is called if there's a frame 4232 * on the receive return list. 4233 * 4234 * Note: we have to be able to handle two possibilities here: 4235 * 1) the frame is from the jumbo receive ring 4236 * 2) the frame is from the standard receive ring 4237 */ 4238 4239 static void 4240 bge_rxeof(struct bge_softc *sc) 4241 { 4242 struct ifnet *ifp; 4243 uint16_t rx_prod, rx_cons; 4244 int stdcnt = 0, jumbocnt = 0; 4245 bus_dmamap_t dmamap; 4246 bus_addr_t offset, toff; 4247 bus_size_t tlen; 4248 int tosync; 4249 4250 rx_cons = sc->bge_rx_saved_considx; 4251 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4252 4253 /* Nothing to do */ 4254 if (rx_cons == rx_prod) 4255 return; 4256 4257 ifp = &sc->ethercom.ec_if; 4258 4259 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4260 offsetof(struct bge_ring_data, bge_status_block), 4261 sizeof (struct bge_status_block), 4262 BUS_DMASYNC_POSTREAD); 4263 4264 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4265 tosync = rx_prod - rx_cons; 4266 4267 if (tosync != 0) 4268 rnd_add_uint32(&sc->rnd_source, tosync); 4269 4270 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4271 4272 if (tosync < 0) { 4273 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4274 sizeof (struct bge_rx_bd); 4275 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4276 toff, tlen, BUS_DMASYNC_POSTREAD); 4277 tosync = -tosync; 4278 } 4279 4280 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4281 offset, tosync * sizeof (struct bge_rx_bd), 4282 BUS_DMASYNC_POSTREAD); 4283 4284 while (rx_cons != rx_prod) { 4285 struct bge_rx_bd *cur_rx; 4286 uint32_t rxidx; 4287 struct mbuf *m = NULL; 4288 4289 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4290 4291 rxidx = cur_rx->bge_idx; 4292 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4293 4294 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4295 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4296 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4297 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4298 jumbocnt++; 4299 bus_dmamap_sync(sc->bge_dmatag, 4300 sc->bge_cdata.bge_rx_jumbo_map, 4301 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4302 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4303 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4304 ifp->if_ierrors++; 4305 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4306 continue; 4307 } 4308 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4309 NULL)== ENOBUFS) { 4310 ifp->if_ierrors++; 4311 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4312 continue; 4313 } 4314 } else { 4315 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4316 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4317 4318 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4319 stdcnt++; 4320 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4321 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4322 if (dmamap == NULL) { 4323 ifp->if_ierrors++; 4324 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4325 continue; 4326 } 4327 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4328 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4329 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4330 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4331 ifp->if_ierrors++; 4332 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4333 continue; 4334 } 4335 if (bge_newbuf_std(sc, sc->bge_std, 4336 NULL, dmamap) == ENOBUFS) { 4337 ifp->if_ierrors++; 4338 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4339 continue; 4340 } 4341 } 4342 4343 ifp->if_ipackets++; 4344 #ifndef __NO_STRICT_ALIGNMENT 4345 /* 4346 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4347 * the Rx buffer has the layer-2 header unaligned. 4348 * If our CPU requires alignment, re-align by copying. 4349 */ 4350 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4351 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4352 cur_rx->bge_len); 4353 m->m_data += ETHER_ALIGN; 4354 } 4355 #endif 4356 4357 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4358 m->m_pkthdr.rcvif = ifp; 4359 4360 /* 4361 * Handle BPF listeners. Let the BPF user see the packet. 4362 */ 4363 bpf_mtap(ifp, m); 4364 4365 bge_rxcsum(sc, cur_rx, m); 4366 4367 /* 4368 * If we received a packet with a vlan tag, pass it 4369 * to vlan_input() instead of ether_input(). 4370 */ 4371 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4372 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4373 } 4374 4375 (*ifp->if_input)(ifp, m); 4376 } 4377 4378 sc->bge_rx_saved_considx = rx_cons; 4379 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4380 if (stdcnt) 4381 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4382 if (jumbocnt) 4383 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4384 } 4385 4386 static void 4387 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4388 { 4389 4390 if (BGE_IS_5717_PLUS(sc)) { 4391 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4392 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4393 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4394 if ((cur_rx->bge_error_flag & 4395 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4396 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4397 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4398 m->m_pkthdr.csum_data = 4399 cur_rx->bge_tcp_udp_csum; 4400 m->m_pkthdr.csum_flags |= 4401 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4402 M_CSUM_DATA); 4403 } 4404 } 4405 } else { 4406 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4407 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4408 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4409 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4410 /* 4411 * Rx transport checksum-offload may also 4412 * have bugs with packets which, when transmitted, 4413 * were `runts' requiring padding. 4414 */ 4415 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4416 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4417 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4418 m->m_pkthdr.csum_data = 4419 cur_rx->bge_tcp_udp_csum; 4420 m->m_pkthdr.csum_flags |= 4421 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4422 M_CSUM_DATA); 4423 } 4424 } 4425 } 4426 4427 static void 4428 bge_txeof(struct bge_softc *sc) 4429 { 4430 struct bge_tx_bd *cur_tx = NULL; 4431 struct ifnet *ifp; 4432 struct txdmamap_pool_entry *dma; 4433 bus_addr_t offset, toff; 4434 bus_size_t tlen; 4435 int tosync; 4436 struct mbuf *m; 4437 4438 ifp = &sc->ethercom.ec_if; 4439 4440 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4441 offsetof(struct bge_ring_data, bge_status_block), 4442 sizeof (struct bge_status_block), 4443 BUS_DMASYNC_POSTREAD); 4444 4445 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4446 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4447 sc->bge_tx_saved_considx; 4448 4449 if (tosync != 0) 4450 rnd_add_uint32(&sc->rnd_source, tosync); 4451 4452 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4453 4454 if (tosync < 0) { 4455 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4456 sizeof (struct bge_tx_bd); 4457 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4458 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4459 tosync = -tosync; 4460 } 4461 4462 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4463 offset, tosync * sizeof (struct bge_tx_bd), 4464 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4465 4466 /* 4467 * Go through our tx ring and free mbufs for those 4468 * frames that have been sent. 4469 */ 4470 while (sc->bge_tx_saved_considx != 4471 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4472 uint32_t idx = 0; 4473 4474 idx = sc->bge_tx_saved_considx; 4475 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4476 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4477 ifp->if_opackets++; 4478 m = sc->bge_cdata.bge_tx_chain[idx]; 4479 if (m != NULL) { 4480 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4481 dma = sc->txdma[idx]; 4482 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4483 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4484 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4485 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4486 sc->txdma[idx] = NULL; 4487 4488 m_freem(m); 4489 } 4490 sc->bge_txcnt--; 4491 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4492 ifp->if_timer = 0; 4493 } 4494 4495 if (cur_tx != NULL) 4496 ifp->if_flags &= ~IFF_OACTIVE; 4497 } 4498 4499 static int 4500 bge_intr(void *xsc) 4501 { 4502 struct bge_softc *sc; 4503 struct ifnet *ifp; 4504 uint32_t statusword; 4505 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4506 4507 sc = xsc; 4508 ifp = &sc->ethercom.ec_if; 4509 4510 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4511 if (BGE_IS_5717_PLUS(sc)) 4512 intrmask = 0; 4513 4514 /* It is possible for the interrupt to arrive before 4515 * the status block is updated prior to the interrupt. 4516 * Reading the PCI State register will confirm whether the 4517 * interrupt is ours and will flush the status block. 4518 */ 4519 4520 /* read status word from status block */ 4521 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4522 offsetof(struct bge_ring_data, bge_status_block), 4523 sizeof (struct bge_status_block), 4524 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4525 statusword = sc->bge_rdata->bge_status_block.bge_status; 4526 4527 if ((statusword & BGE_STATFLAG_UPDATED) || 4528 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) { 4529 /* Ack interrupt and stop others from occuring. */ 4530 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4531 4532 BGE_EVCNT_INCR(sc->bge_ev_intr); 4533 4534 /* clear status word */ 4535 sc->bge_rdata->bge_status_block.bge_status = 0; 4536 4537 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4538 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4539 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4540 bge_link_upd(sc); 4541 4542 if (ifp->if_flags & IFF_RUNNING) { 4543 /* Check RX return ring producer/consumer */ 4544 bge_rxeof(sc); 4545 4546 /* Check TX ring producer/consumer */ 4547 bge_txeof(sc); 4548 } 4549 4550 if (sc->bge_pending_rxintr_change) { 4551 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4552 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4553 uint32_t junk; 4554 4555 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4556 DELAY(10); 4557 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4558 4559 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4560 DELAY(10); 4561 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4562 4563 sc->bge_pending_rxintr_change = 0; 4564 } 4565 bge_handle_events(sc); 4566 4567 /* Re-enable interrupts. */ 4568 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4569 4570 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4571 bge_start(ifp); 4572 4573 return 1; 4574 } else 4575 return 0; 4576 } 4577 4578 static void 4579 bge_asf_driver_up(struct bge_softc *sc) 4580 { 4581 if (sc->bge_asf_mode & ASF_STACKUP) { 4582 /* Send ASF heartbeat aprox. every 2s */ 4583 if (sc->bge_asf_count) 4584 sc->bge_asf_count --; 4585 else { 4586 sc->bge_asf_count = 2; 4587 4588 bge_wait_for_event_ack(sc); 4589 4590 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4591 BGE_FW_CMD_DRV_ALIVE); 4592 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4593 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4594 BGE_FW_HB_TIMEOUT_SEC); 4595 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4596 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4597 BGE_RX_CPU_DRV_EVENT); 4598 } 4599 } 4600 } 4601 4602 static void 4603 bge_tick(void *xsc) 4604 { 4605 struct bge_softc *sc = xsc; 4606 struct mii_data *mii = &sc->bge_mii; 4607 int s; 4608 4609 s = splnet(); 4610 4611 if (BGE_IS_5705_PLUS(sc)) 4612 bge_stats_update_regs(sc); 4613 else 4614 bge_stats_update(sc); 4615 4616 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4617 /* 4618 * Since in TBI mode auto-polling can't be used we should poll 4619 * link status manually. Here we register pending link event 4620 * and trigger interrupt. 4621 */ 4622 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4623 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4624 } else { 4625 /* 4626 * Do not touch PHY if we have link up. This could break 4627 * IPMI/ASF mode or produce extra input errors. 4628 * (extra input errors was reported for bcm5701 & bcm5704). 4629 */ 4630 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4631 mii_tick(mii); 4632 } 4633 4634 bge_asf_driver_up(sc); 4635 4636 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4637 4638 splx(s); 4639 } 4640 4641 static void 4642 bge_stats_update_regs(struct bge_softc *sc) 4643 { 4644 struct ifnet *ifp = &sc->ethercom.ec_if; 4645 4646 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4647 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4648 4649 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4650 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4651 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4652 } 4653 4654 static void 4655 bge_stats_update(struct bge_softc *sc) 4656 { 4657 struct ifnet *ifp = &sc->ethercom.ec_if; 4658 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4659 4660 #define READ_STAT(sc, stats, stat) \ 4661 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4662 4663 ifp->if_collisions += 4664 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4665 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4666 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4667 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4668 ifp->if_collisions; 4669 4670 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4671 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4672 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4673 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4674 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4675 READ_STAT(sc, stats, 4676 xoffPauseFramesReceived.bge_addr_lo)); 4677 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4678 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4679 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4680 READ_STAT(sc, stats, 4681 macControlFramesReceived.bge_addr_lo)); 4682 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4683 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4684 4685 #undef READ_STAT 4686 4687 #ifdef notdef 4688 ifp->if_collisions += 4689 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4690 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4691 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4692 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4693 ifp->if_collisions; 4694 #endif 4695 } 4696 4697 /* 4698 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4699 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4700 * but when such padded frames employ the bge IP/TCP checksum offload, 4701 * the hardware checksum assist gives incorrect results (possibly 4702 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4703 * If we pad such runts with zeros, the onboard checksum comes out correct. 4704 */ 4705 static inline int 4706 bge_cksum_pad(struct mbuf *pkt) 4707 { 4708 struct mbuf *last = NULL; 4709 int padlen; 4710 4711 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4712 4713 /* if there's only the packet-header and we can pad there, use it. */ 4714 if (pkt->m_pkthdr.len == pkt->m_len && 4715 M_TRAILINGSPACE(pkt) >= padlen) { 4716 last = pkt; 4717 } else { 4718 /* 4719 * Walk packet chain to find last mbuf. We will either 4720 * pad there, or append a new mbuf and pad it 4721 * (thus perhaps avoiding the bcm5700 dma-min bug). 4722 */ 4723 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4724 continue; /* do nothing */ 4725 } 4726 4727 /* `last' now points to last in chain. */ 4728 if (M_TRAILINGSPACE(last) < padlen) { 4729 /* Allocate new empty mbuf, pad it. Compact later. */ 4730 struct mbuf *n; 4731 MGET(n, M_DONTWAIT, MT_DATA); 4732 if (n == NULL) 4733 return ENOBUFS; 4734 n->m_len = 0; 4735 last->m_next = n; 4736 last = n; 4737 } 4738 } 4739 4740 KDASSERT(!M_READONLY(last)); 4741 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4742 4743 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4744 memset(mtod(last, char *) + last->m_len, 0, padlen); 4745 last->m_len += padlen; 4746 pkt->m_pkthdr.len += padlen; 4747 return 0; 4748 } 4749 4750 /* 4751 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4752 */ 4753 static inline int 4754 bge_compact_dma_runt(struct mbuf *pkt) 4755 { 4756 struct mbuf *m, *prev; 4757 int totlen, prevlen; 4758 4759 prev = NULL; 4760 totlen = 0; 4761 prevlen = -1; 4762 4763 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4764 int mlen = m->m_len; 4765 int shortfall = 8 - mlen ; 4766 4767 totlen += mlen; 4768 if (mlen == 0) 4769 continue; 4770 if (mlen >= 8) 4771 continue; 4772 4773 /* If we get here, mbuf data is too small for DMA engine. 4774 * Try to fix by shuffling data to prev or next in chain. 4775 * If that fails, do a compacting deep-copy of the whole chain. 4776 */ 4777 4778 /* Internal frag. If fits in prev, copy it there. */ 4779 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4780 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4781 prev->m_len += mlen; 4782 m->m_len = 0; 4783 /* XXX stitch chain */ 4784 prev->m_next = m_free(m); 4785 m = prev; 4786 continue; 4787 } 4788 else if (m->m_next != NULL && 4789 M_TRAILINGSPACE(m) >= shortfall && 4790 m->m_next->m_len >= (8 + shortfall)) { 4791 /* m is writable and have enough data in next, pull up. */ 4792 4793 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4794 shortfall); 4795 m->m_len += shortfall; 4796 m->m_next->m_len -= shortfall; 4797 m->m_next->m_data += shortfall; 4798 } 4799 else if (m->m_next == NULL || 1) { 4800 /* Got a runt at the very end of the packet. 4801 * borrow data from the tail of the preceding mbuf and 4802 * update its length in-place. (The original data is still 4803 * valid, so we can do this even if prev is not writable.) 4804 */ 4805 4806 /* if we'd make prev a runt, just move all of its data. */ 4807 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4808 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4809 4810 if ((prev->m_len - shortfall) < 8) 4811 shortfall = prev->m_len; 4812 4813 #ifdef notyet /* just do the safe slow thing for now */ 4814 if (!M_READONLY(m)) { 4815 if (M_LEADINGSPACE(m) < shorfall) { 4816 void *m_dat; 4817 m_dat = (m->m_flags & M_PKTHDR) ? 4818 m->m_pktdat : m->dat; 4819 memmove(m_dat, mtod(m, void*), m->m_len); 4820 m->m_data = m_dat; 4821 } 4822 } else 4823 #endif /* just do the safe slow thing */ 4824 { 4825 struct mbuf * n = NULL; 4826 int newprevlen = prev->m_len - shortfall; 4827 4828 MGET(n, M_NOWAIT, MT_DATA); 4829 if (n == NULL) 4830 return ENOBUFS; 4831 KASSERT(m->m_len + shortfall < MLEN 4832 /*, 4833 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4834 4835 /* first copy the data we're stealing from prev */ 4836 memcpy(n->m_data, prev->m_data + newprevlen, 4837 shortfall); 4838 4839 /* update prev->m_len accordingly */ 4840 prev->m_len -= shortfall; 4841 4842 /* copy data from runt m */ 4843 memcpy(n->m_data + shortfall, m->m_data, 4844 m->m_len); 4845 4846 /* n holds what we stole from prev, plus m */ 4847 n->m_len = shortfall + m->m_len; 4848 4849 /* stitch n into chain and free m */ 4850 n->m_next = m->m_next; 4851 prev->m_next = n; 4852 /* KASSERT(m->m_next == NULL); */ 4853 m->m_next = NULL; 4854 m_free(m); 4855 m = n; /* for continuing loop */ 4856 } 4857 } 4858 prevlen = m->m_len; 4859 } 4860 return 0; 4861 } 4862 4863 /* 4864 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4865 * pointers to descriptors. 4866 */ 4867 static int 4868 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4869 { 4870 struct bge_tx_bd *f = NULL; 4871 uint32_t frag, cur; 4872 uint16_t csum_flags = 0; 4873 uint16_t txbd_tso_flags = 0; 4874 struct txdmamap_pool_entry *dma; 4875 bus_dmamap_t dmamap; 4876 int i = 0; 4877 struct m_tag *mtag; 4878 int use_tso, maxsegsize, error; 4879 4880 cur = frag = *txidx; 4881 4882 if (m_head->m_pkthdr.csum_flags) { 4883 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4884 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4885 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4886 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4887 } 4888 4889 /* 4890 * If we were asked to do an outboard checksum, and the NIC 4891 * has the bug where it sometimes adds in the Ethernet padding, 4892 * explicitly pad with zeros so the cksum will be correct either way. 4893 * (For now, do this for all chip versions, until newer 4894 * are confirmed to not require the workaround.) 4895 */ 4896 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4897 #ifdef notyet 4898 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4899 #endif 4900 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4901 goto check_dma_bug; 4902 4903 if (bge_cksum_pad(m_head) != 0) 4904 return ENOBUFS; 4905 4906 check_dma_bug: 4907 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4908 goto doit; 4909 4910 /* 4911 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4912 * less than eight bytes. If we encounter a teeny mbuf 4913 * at the end of a chain, we can pad. Otherwise, copy. 4914 */ 4915 if (bge_compact_dma_runt(m_head) != 0) 4916 return ENOBUFS; 4917 4918 doit: 4919 dma = SLIST_FIRST(&sc->txdma_list); 4920 if (dma == NULL) 4921 return ENOBUFS; 4922 dmamap = dma->dmamap; 4923 4924 /* 4925 * Set up any necessary TSO state before we start packing... 4926 */ 4927 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4928 if (!use_tso) { 4929 maxsegsize = 0; 4930 } else { /* TSO setup */ 4931 unsigned mss; 4932 struct ether_header *eh; 4933 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4934 struct mbuf * m0 = m_head; 4935 struct ip *ip; 4936 struct tcphdr *th; 4937 int iphl, hlen; 4938 4939 /* 4940 * XXX It would be nice if the mbuf pkthdr had offset 4941 * fields for the protocol headers. 4942 */ 4943 4944 eh = mtod(m0, struct ether_header *); 4945 switch (htons(eh->ether_type)) { 4946 case ETHERTYPE_IP: 4947 offset = ETHER_HDR_LEN; 4948 break; 4949 4950 case ETHERTYPE_VLAN: 4951 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4952 break; 4953 4954 default: 4955 /* 4956 * Don't support this protocol or encapsulation. 4957 */ 4958 return ENOBUFS; 4959 } 4960 4961 /* 4962 * TCP/IP headers are in the first mbuf; we can do 4963 * this the easy way. 4964 */ 4965 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4966 hlen = iphl + offset; 4967 if (__predict_false(m0->m_len < 4968 (hlen + sizeof(struct tcphdr)))) { 4969 4970 aprint_debug_dev(sc->bge_dev, 4971 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4972 "not handled yet\n", 4973 m0->m_len, hlen+ sizeof(struct tcphdr)); 4974 #ifdef NOTYET 4975 /* 4976 * XXX jonathan (at) NetBSD.org: untested. 4977 * how to force this branch to be taken? 4978 */ 4979 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4980 4981 m_copydata(m0, offset, sizeof(ip), &ip); 4982 m_copydata(m0, hlen, sizeof(th), &th); 4983 4984 ip.ip_len = 0; 4985 4986 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4987 sizeof(ip.ip_len), &ip.ip_len); 4988 4989 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4990 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4991 4992 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4993 sizeof(th.th_sum), &th.th_sum); 4994 4995 hlen += th.th_off << 2; 4996 iptcp_opt_words = hlen; 4997 #else 4998 /* 4999 * if_wm "hard" case not yet supported, can we not 5000 * mandate it out of existence? 5001 */ 5002 (void) ip; (void)th; (void) ip_tcp_hlen; 5003 5004 return ENOBUFS; 5005 #endif 5006 } else { 5007 ip = (struct ip *) (mtod(m0, char *) + offset); 5008 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5009 ip_tcp_hlen = iphl + (th->th_off << 2); 5010 5011 /* Total IP/TCP options, in 32-bit words */ 5012 iptcp_opt_words = (ip_tcp_hlen 5013 - sizeof(struct tcphdr) 5014 - sizeof(struct ip)) >> 2; 5015 } 5016 if (BGE_IS_575X_PLUS(sc)) { 5017 th->th_sum = 0; 5018 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5019 } else { 5020 /* 5021 * XXX jonathan (at) NetBSD.org: 5705 untested. 5022 * Requires TSO firmware patch for 5701/5703/5704. 5023 */ 5024 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5025 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5026 } 5027 5028 mss = m_head->m_pkthdr.segsz; 5029 txbd_tso_flags |= 5030 BGE_TXBDFLAG_CPU_PRE_DMA | 5031 BGE_TXBDFLAG_CPU_POST_DMA; 5032 5033 /* 5034 * Our NIC TSO-assist assumes TSO has standard, optionless 5035 * IPv4 and TCP headers, which total 40 bytes. By default, 5036 * the NIC copies 40 bytes of IP/TCP header from the 5037 * supplied header into the IP/TCP header portion of 5038 * each post-TSO-segment. If the supplied packet has IP or 5039 * TCP options, we need to tell the NIC to copy those extra 5040 * bytes into each post-TSO header, in addition to the normal 5041 * 40-byte IP/TCP header (and to leave space accordingly). 5042 * Unfortunately, the driver encoding of option length 5043 * varies across different ASIC families. 5044 */ 5045 tcp_seg_flags = 0; 5046 if (iptcp_opt_words) { 5047 if (BGE_IS_5705_PLUS(sc)) { 5048 tcp_seg_flags = 5049 iptcp_opt_words << 11; 5050 } else { 5051 txbd_tso_flags |= 5052 iptcp_opt_words << 12; 5053 } 5054 } 5055 maxsegsize = mss | tcp_seg_flags; 5056 ip->ip_len = htons(mss + ip_tcp_hlen); 5057 5058 } /* TSO setup */ 5059 5060 /* 5061 * Start packing the mbufs in this chain into 5062 * the fragment pointers. Stop when we run out 5063 * of fragments or hit the end of the mbuf chain. 5064 */ 5065 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5066 BUS_DMA_NOWAIT); 5067 if (error) 5068 return ENOBUFS; 5069 /* 5070 * Sanity check: avoid coming within 16 descriptors 5071 * of the end of the ring. 5072 */ 5073 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5074 BGE_TSO_PRINTF(("%s: " 5075 " dmamap_load_mbuf too close to ring wrap\n", 5076 device_xname(sc->bge_dev))); 5077 goto fail_unload; 5078 } 5079 5080 mtag = sc->ethercom.ec_nvlans ? 5081 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5082 5083 5084 /* Iterate over dmap-map fragments. */ 5085 for (i = 0; i < dmamap->dm_nsegs; i++) { 5086 f = &sc->bge_rdata->bge_tx_ring[frag]; 5087 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5088 break; 5089 5090 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5091 f->bge_len = dmamap->dm_segs[i].ds_len; 5092 5093 /* 5094 * For 5751 and follow-ons, for TSO we must turn 5095 * off checksum-assist flag in the tx-descr, and 5096 * supply the ASIC-revision-specific encoding 5097 * of TSO flags and segsize. 5098 */ 5099 if (use_tso) { 5100 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5101 f->bge_rsvd = maxsegsize; 5102 f->bge_flags = csum_flags | txbd_tso_flags; 5103 } else { 5104 f->bge_rsvd = 0; 5105 f->bge_flags = 5106 (csum_flags | txbd_tso_flags) & 0x0fff; 5107 } 5108 } else { 5109 f->bge_rsvd = 0; 5110 f->bge_flags = csum_flags; 5111 } 5112 5113 if (mtag != NULL) { 5114 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5115 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5116 } else { 5117 f->bge_vlan_tag = 0; 5118 } 5119 cur = frag; 5120 BGE_INC(frag, BGE_TX_RING_CNT); 5121 } 5122 5123 if (i < dmamap->dm_nsegs) { 5124 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5125 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5126 goto fail_unload; 5127 } 5128 5129 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5130 BUS_DMASYNC_PREWRITE); 5131 5132 if (frag == sc->bge_tx_saved_considx) { 5133 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5134 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5135 5136 goto fail_unload; 5137 } 5138 5139 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5140 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5141 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5142 sc->txdma[cur] = dma; 5143 sc->bge_txcnt += dmamap->dm_nsegs; 5144 5145 *txidx = frag; 5146 5147 return 0; 5148 5149 fail_unload: 5150 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5151 5152 return ENOBUFS; 5153 } 5154 5155 /* 5156 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5157 * to the mbuf data regions directly in the transmit descriptors. 5158 */ 5159 static void 5160 bge_start(struct ifnet *ifp) 5161 { 5162 struct bge_softc *sc; 5163 struct mbuf *m_head = NULL; 5164 uint32_t prodidx; 5165 int pkts = 0; 5166 5167 sc = ifp->if_softc; 5168 5169 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5170 return; 5171 5172 prodidx = sc->bge_tx_prodidx; 5173 5174 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5175 IFQ_POLL(&ifp->if_snd, m_head); 5176 if (m_head == NULL) 5177 break; 5178 5179 #if 0 5180 /* 5181 * XXX 5182 * safety overkill. If this is a fragmented packet chain 5183 * with delayed TCP/UDP checksums, then only encapsulate 5184 * it if we have enough descriptors to handle the entire 5185 * chain at once. 5186 * (paranoia -- may not actually be needed) 5187 */ 5188 if (m_head->m_flags & M_FIRSTFRAG && 5189 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5190 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5191 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5192 ifp->if_flags |= IFF_OACTIVE; 5193 break; 5194 } 5195 } 5196 #endif 5197 5198 /* 5199 * Pack the data into the transmit ring. If we 5200 * don't have room, set the OACTIVE flag and wait 5201 * for the NIC to drain the ring. 5202 */ 5203 if (bge_encap(sc, m_head, &prodidx)) { 5204 ifp->if_flags |= IFF_OACTIVE; 5205 break; 5206 } 5207 5208 /* now we are committed to transmit the packet */ 5209 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5210 pkts++; 5211 5212 /* 5213 * If there's a BPF listener, bounce a copy of this frame 5214 * to him. 5215 */ 5216 bpf_mtap(ifp, m_head); 5217 } 5218 if (pkts == 0) 5219 return; 5220 5221 /* Transmit */ 5222 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5223 /* 5700 b2 errata */ 5224 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5225 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5226 5227 sc->bge_tx_prodidx = prodidx; 5228 5229 /* 5230 * Set a timeout in case the chip goes out to lunch. 5231 */ 5232 ifp->if_timer = 5; 5233 } 5234 5235 static int 5236 bge_init(struct ifnet *ifp) 5237 { 5238 struct bge_softc *sc = ifp->if_softc; 5239 const uint16_t *m; 5240 uint32_t mode; 5241 int s, error = 0; 5242 5243 s = splnet(); 5244 5245 ifp = &sc->ethercom.ec_if; 5246 5247 /* Cancel pending I/O and flush buffers. */ 5248 bge_stop(ifp, 0); 5249 5250 bge_stop_fw(sc); 5251 bge_sig_pre_reset(sc, BGE_RESET_START); 5252 bge_reset(sc); 5253 bge_sig_legacy(sc, BGE_RESET_START); 5254 bge_sig_post_reset(sc, BGE_RESET_START); 5255 5256 bge_chipinit(sc); 5257 5258 /* 5259 * Init the various state machines, ring 5260 * control blocks and firmware. 5261 */ 5262 error = bge_blockinit(sc); 5263 if (error != 0) { 5264 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5265 error); 5266 splx(s); 5267 return error; 5268 } 5269 5270 ifp = &sc->ethercom.ec_if; 5271 5272 /* 5718 step 25, 57XX step 54 */ 5273 /* Specify MTU. */ 5274 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5275 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5276 5277 /* 5718 step 23 */ 5278 /* Load our MAC address. */ 5279 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5280 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5281 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5282 5283 /* Enable or disable promiscuous mode as needed. */ 5284 if (ifp->if_flags & IFF_PROMISC) 5285 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5286 else 5287 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5288 5289 /* Program multicast filter. */ 5290 bge_setmulti(sc); 5291 5292 /* Init RX ring. */ 5293 bge_init_rx_ring_std(sc); 5294 5295 /* 5296 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5297 * memory to insure that the chip has in fact read the first 5298 * entry of the ring. 5299 */ 5300 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5301 uint32_t v, i; 5302 for (i = 0; i < 10; i++) { 5303 DELAY(20); 5304 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5305 if (v == (MCLBYTES - ETHER_ALIGN)) 5306 break; 5307 } 5308 if (i == 10) 5309 aprint_error_dev(sc->bge_dev, 5310 "5705 A0 chip failed to load RX ring\n"); 5311 } 5312 5313 /* Init jumbo RX ring. */ 5314 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5315 bge_init_rx_ring_jumbo(sc); 5316 5317 /* Init our RX return ring index */ 5318 sc->bge_rx_saved_considx = 0; 5319 5320 /* Init TX ring. */ 5321 bge_init_tx_ring(sc); 5322 5323 /* 5718 step 63, 57XX step 94 */ 5324 /* Enable TX MAC state machine lockup fix. */ 5325 mode = CSR_READ_4(sc, BGE_TX_MODE); 5326 if (BGE_IS_5755_PLUS(sc) || 5327 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5328 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5329 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5330 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5331 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5332 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5333 } 5334 5335 /* Turn on transmitter */ 5336 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5337 /* 5718 step 64 */ 5338 DELAY(100); 5339 5340 /* 5718 step 65, 57XX step 95 */ 5341 /* Turn on receiver */ 5342 mode = CSR_READ_4(sc, BGE_RX_MODE); 5343 if (BGE_IS_5755_PLUS(sc)) 5344 mode |= BGE_RXMODE_IPV6_ENABLE; 5345 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5346 /* 5718 step 66 */ 5347 DELAY(10); 5348 5349 /* 5718 step 12 */ 5350 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5351 5352 /* Tell firmware we're alive. */ 5353 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5354 5355 /* Enable host interrupts. */ 5356 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5357 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5358 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5359 5360 if ((error = bge_ifmedia_upd(ifp)) != 0) 5361 goto out; 5362 5363 ifp->if_flags |= IFF_RUNNING; 5364 ifp->if_flags &= ~IFF_OACTIVE; 5365 5366 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5367 5368 out: 5369 sc->bge_if_flags = ifp->if_flags; 5370 splx(s); 5371 5372 return error; 5373 } 5374 5375 /* 5376 * Set media options. 5377 */ 5378 static int 5379 bge_ifmedia_upd(struct ifnet *ifp) 5380 { 5381 struct bge_softc *sc = ifp->if_softc; 5382 struct mii_data *mii = &sc->bge_mii; 5383 struct ifmedia *ifm = &sc->bge_ifmedia; 5384 int rc; 5385 5386 /* If this is a 1000baseX NIC, enable the TBI port. */ 5387 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5388 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5389 return EINVAL; 5390 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5391 case IFM_AUTO: 5392 /* 5393 * The BCM5704 ASIC appears to have a special 5394 * mechanism for programming the autoneg 5395 * advertisement registers in TBI mode. 5396 */ 5397 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5398 uint32_t sgdig; 5399 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5400 if (sgdig & BGE_SGDIGSTS_DONE) { 5401 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5402 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5403 sgdig |= BGE_SGDIGCFG_AUTO | 5404 BGE_SGDIGCFG_PAUSE_CAP | 5405 BGE_SGDIGCFG_ASYM_PAUSE; 5406 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5407 sgdig | BGE_SGDIGCFG_SEND); 5408 DELAY(5); 5409 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5410 sgdig); 5411 } 5412 } 5413 break; 5414 case IFM_1000_SX: 5415 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5416 BGE_CLRBIT(sc, BGE_MAC_MODE, 5417 BGE_MACMODE_HALF_DUPLEX); 5418 } else { 5419 BGE_SETBIT(sc, BGE_MAC_MODE, 5420 BGE_MACMODE_HALF_DUPLEX); 5421 } 5422 DELAY(40); 5423 break; 5424 default: 5425 return EINVAL; 5426 } 5427 /* XXX 802.3x flow control for 1000BASE-SX */ 5428 return 0; 5429 } 5430 5431 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5432 if ((rc = mii_mediachg(mii)) == ENXIO) 5433 return 0; 5434 5435 /* 5436 * Force an interrupt so that we will call bge_link_upd 5437 * if needed and clear any pending link state attention. 5438 * Without this we are not getting any further interrupts 5439 * for link state changes and thus will not UP the link and 5440 * not be able to send in bge_start. The only way to get 5441 * things working was to receive a packet and get a RX intr. 5442 */ 5443 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5444 sc->bge_flags & BGE_IS_5788) 5445 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5446 else 5447 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5448 5449 return rc; 5450 } 5451 5452 /* 5453 * Report current media status. 5454 */ 5455 static void 5456 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5457 { 5458 struct bge_softc *sc = ifp->if_softc; 5459 struct mii_data *mii = &sc->bge_mii; 5460 5461 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5462 ifmr->ifm_status = IFM_AVALID; 5463 ifmr->ifm_active = IFM_ETHER; 5464 if (CSR_READ_4(sc, BGE_MAC_STS) & 5465 BGE_MACSTAT_TBI_PCS_SYNCHED) 5466 ifmr->ifm_status |= IFM_ACTIVE; 5467 ifmr->ifm_active |= IFM_1000_SX; 5468 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5469 ifmr->ifm_active |= IFM_HDX; 5470 else 5471 ifmr->ifm_active |= IFM_FDX; 5472 return; 5473 } 5474 5475 mii_pollstat(mii); 5476 ifmr->ifm_status = mii->mii_media_status; 5477 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5478 sc->bge_flowflags; 5479 } 5480 5481 static int 5482 bge_ifflags_cb(struct ethercom *ec) 5483 { 5484 struct ifnet *ifp = &ec->ec_if; 5485 struct bge_softc *sc = ifp->if_softc; 5486 int change = ifp->if_flags ^ sc->bge_if_flags; 5487 5488 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5489 return ENETRESET; 5490 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5491 return 0; 5492 5493 if ((ifp->if_flags & IFF_PROMISC) == 0) 5494 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5495 else 5496 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5497 5498 bge_setmulti(sc); 5499 5500 sc->bge_if_flags = ifp->if_flags; 5501 return 0; 5502 } 5503 5504 static int 5505 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5506 { 5507 struct bge_softc *sc = ifp->if_softc; 5508 struct ifreq *ifr = (struct ifreq *) data; 5509 int s, error = 0; 5510 struct mii_data *mii; 5511 5512 s = splnet(); 5513 5514 switch (command) { 5515 case SIOCSIFMEDIA: 5516 /* XXX Flow control is not supported for 1000BASE-SX */ 5517 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5518 ifr->ifr_media &= ~IFM_ETH_FMASK; 5519 sc->bge_flowflags = 0; 5520 } 5521 5522 /* Flow control requires full-duplex mode. */ 5523 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5524 (ifr->ifr_media & IFM_FDX) == 0) { 5525 ifr->ifr_media &= ~IFM_ETH_FMASK; 5526 } 5527 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5528 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5529 /* We can do both TXPAUSE and RXPAUSE. */ 5530 ifr->ifr_media |= 5531 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5532 } 5533 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5534 } 5535 /* FALLTHROUGH */ 5536 case SIOCGIFMEDIA: 5537 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5538 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5539 command); 5540 } else { 5541 mii = &sc->bge_mii; 5542 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5543 command); 5544 } 5545 break; 5546 default: 5547 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5548 break; 5549 5550 error = 0; 5551 5552 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5553 ; 5554 else if (ifp->if_flags & IFF_RUNNING) 5555 bge_setmulti(sc); 5556 break; 5557 } 5558 5559 splx(s); 5560 5561 return error; 5562 } 5563 5564 static void 5565 bge_watchdog(struct ifnet *ifp) 5566 { 5567 struct bge_softc *sc; 5568 5569 sc = ifp->if_softc; 5570 5571 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5572 5573 ifp->if_flags &= ~IFF_RUNNING; 5574 bge_init(ifp); 5575 5576 ifp->if_oerrors++; 5577 } 5578 5579 static void 5580 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5581 { 5582 int i; 5583 5584 BGE_CLRBIT_FLUSH(sc, reg, bit); 5585 5586 for (i = 0; i < 1000; i++) { 5587 delay(100); 5588 if ((CSR_READ_4(sc, reg) & bit) == 0) 5589 return; 5590 } 5591 5592 /* 5593 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5594 * on some environment (and once after boot?) 5595 */ 5596 if (reg != BGE_SRS_MODE) 5597 aprint_error_dev(sc->bge_dev, 5598 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5599 (u_long)reg, bit); 5600 } 5601 5602 /* 5603 * Stop the adapter and free any mbufs allocated to the 5604 * RX and TX lists. 5605 */ 5606 static void 5607 bge_stop(struct ifnet *ifp, int disable) 5608 { 5609 struct bge_softc *sc = ifp->if_softc; 5610 5611 callout_stop(&sc->bge_timeout); 5612 5613 /* Disable host interrupts. */ 5614 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5615 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5616 5617 /* 5618 * Tell firmware we're shutting down. 5619 */ 5620 bge_stop_fw(sc); 5621 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5622 5623 /* 5624 * Disable all of the receiver blocks. 5625 */ 5626 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5627 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5628 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5629 if (BGE_IS_5700_FAMILY(sc)) 5630 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5631 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5632 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5633 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5634 5635 /* 5636 * Disable all of the transmit blocks. 5637 */ 5638 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5639 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5640 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5641 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5642 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5643 if (BGE_IS_5700_FAMILY(sc)) 5644 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5645 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5646 5647 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5648 delay(40); 5649 5650 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5651 5652 /* 5653 * Shut down all of the memory managers and related 5654 * state machines. 5655 */ 5656 /* 5718 step 5a,5b */ 5657 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5658 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5659 if (BGE_IS_5700_FAMILY(sc)) 5660 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5661 5662 /* 5718 step 5c,5d */ 5663 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5664 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5665 5666 if (BGE_IS_5700_FAMILY(sc)) { 5667 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5668 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5669 } 5670 5671 bge_reset(sc); 5672 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5673 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5674 5675 /* 5676 * Keep the ASF firmware running if up. 5677 */ 5678 if (sc->bge_asf_mode & ASF_STACKUP) 5679 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5680 else 5681 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5682 5683 /* Free the RX lists. */ 5684 bge_free_rx_ring_std(sc); 5685 5686 /* Free jumbo RX list. */ 5687 if (BGE_IS_JUMBO_CAPABLE(sc)) 5688 bge_free_rx_ring_jumbo(sc); 5689 5690 /* Free TX buffers. */ 5691 bge_free_tx_ring(sc); 5692 5693 /* 5694 * Isolate/power down the PHY. 5695 */ 5696 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5697 mii_down(&sc->bge_mii); 5698 5699 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5700 5701 /* Clear MAC's link state (PHY may still have link UP). */ 5702 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5703 5704 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5705 } 5706 5707 static void 5708 bge_link_upd(struct bge_softc *sc) 5709 { 5710 struct ifnet *ifp = &sc->ethercom.ec_if; 5711 struct mii_data *mii = &sc->bge_mii; 5712 uint32_t status; 5713 int link; 5714 5715 /* Clear 'pending link event' flag */ 5716 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5717 5718 /* 5719 * Process link state changes. 5720 * Grrr. The link status word in the status block does 5721 * not work correctly on the BCM5700 rev AX and BX chips, 5722 * according to all available information. Hence, we have 5723 * to enable MII interrupts in order to properly obtain 5724 * async link changes. Unfortunately, this also means that 5725 * we have to read the MAC status register to detect link 5726 * changes, thereby adding an additional register access to 5727 * the interrupt handler. 5728 */ 5729 5730 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5731 status = CSR_READ_4(sc, BGE_MAC_STS); 5732 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5733 mii_pollstat(mii); 5734 5735 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5736 mii->mii_media_status & IFM_ACTIVE && 5737 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5738 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5739 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5740 (!(mii->mii_media_status & IFM_ACTIVE) || 5741 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5742 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5743 5744 /* Clear the interrupt */ 5745 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5746 BGE_EVTENB_MI_INTERRUPT); 5747 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5748 BRGPHY_MII_ISR); 5749 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5750 BRGPHY_MII_IMR, BRGPHY_INTRS); 5751 } 5752 return; 5753 } 5754 5755 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5756 status = CSR_READ_4(sc, BGE_MAC_STS); 5757 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5758 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5759 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5760 if (BGE_ASICREV(sc->bge_chipid) 5761 == BGE_ASICREV_BCM5704) { 5762 BGE_CLRBIT(sc, BGE_MAC_MODE, 5763 BGE_MACMODE_TBI_SEND_CFGS); 5764 DELAY(40); 5765 } 5766 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5767 if_link_state_change(ifp, LINK_STATE_UP); 5768 } 5769 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5770 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5771 if_link_state_change(ifp, LINK_STATE_DOWN); 5772 } 5773 /* 5774 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5775 * This should not happen since mii callouts are locked now, but 5776 * we keep this check for debug. 5777 */ 5778 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5779 /* 5780 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5781 * bit in status word always set. Workaround this bug by 5782 * reading PHY link status directly. 5783 */ 5784 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5785 BGE_STS_LINK : 0; 5786 5787 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5788 mii_pollstat(mii); 5789 5790 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5791 mii->mii_media_status & IFM_ACTIVE && 5792 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5793 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5794 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5795 (!(mii->mii_media_status & IFM_ACTIVE) || 5796 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5797 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5798 } 5799 } 5800 5801 /* Clear the attention */ 5802 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5803 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5804 BGE_MACSTAT_LINK_CHANGED); 5805 } 5806 5807 static int 5808 bge_sysctl_verify(SYSCTLFN_ARGS) 5809 { 5810 int error, t; 5811 struct sysctlnode node; 5812 5813 node = *rnode; 5814 t = *(int*)rnode->sysctl_data; 5815 node.sysctl_data = &t; 5816 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5817 if (error || newp == NULL) 5818 return error; 5819 5820 #if 0 5821 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5822 node.sysctl_num, rnode->sysctl_num)); 5823 #endif 5824 5825 if (node.sysctl_num == bge_rxthresh_nodenum) { 5826 if (t < 0 || t >= NBGE_RX_THRESH) 5827 return EINVAL; 5828 bge_update_all_threshes(t); 5829 } else 5830 return EINVAL; 5831 5832 *(int*)rnode->sysctl_data = t; 5833 5834 return 0; 5835 } 5836 5837 /* 5838 * Set up sysctl(3) MIB, hw.bge.*. 5839 */ 5840 static void 5841 bge_sysctl_init(struct bge_softc *sc) 5842 { 5843 int rc, bge_root_num; 5844 const struct sysctlnode *node; 5845 5846 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5847 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5848 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5849 goto out; 5850 } 5851 5852 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5853 0, CTLTYPE_NODE, "bge", 5854 SYSCTL_DESCR("BGE interface controls"), 5855 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5856 goto out; 5857 } 5858 5859 bge_root_num = node->sysctl_num; 5860 5861 /* BGE Rx interrupt mitigation level */ 5862 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5863 CTLFLAG_READWRITE, 5864 CTLTYPE_INT, "rx_lvl", 5865 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5866 bge_sysctl_verify, 0, 5867 &bge_rx_thresh_lvl, 5868 0, CTL_HW, bge_root_num, CTL_CREATE, 5869 CTL_EOL)) != 0) { 5870 goto out; 5871 } 5872 5873 bge_rxthresh_nodenum = node->sysctl_num; 5874 5875 return; 5876 5877 out: 5878 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5879 } 5880 5881 #ifdef BGE_DEBUG 5882 void 5883 bge_debug_info(struct bge_softc *sc) 5884 { 5885 5886 printf("Hardware Flags:\n"); 5887 if (BGE_IS_57765_PLUS(sc)) 5888 printf(" - 57765 Plus\n"); 5889 if (BGE_IS_5717_PLUS(sc)) 5890 printf(" - 5717 Plus\n"); 5891 if (BGE_IS_5755_PLUS(sc)) 5892 printf(" - 5755 Plus\n"); 5893 if (BGE_IS_575X_PLUS(sc)) 5894 printf(" - 575X Plus\n"); 5895 if (BGE_IS_5705_PLUS(sc)) 5896 printf(" - 5705 Plus\n"); 5897 if (BGE_IS_5714_FAMILY(sc)) 5898 printf(" - 5714 Family\n"); 5899 if (BGE_IS_5700_FAMILY(sc)) 5900 printf(" - 5700 Family\n"); 5901 if (sc->bge_flags & BGE_IS_5788) 5902 printf(" - 5788\n"); 5903 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5904 printf(" - Supports Jumbo Frames\n"); 5905 if (sc->bge_flags & BGE_NO_EEPROM) 5906 printf(" - No EEPROM\n"); 5907 if (sc->bge_flags & BGE_PCIX) 5908 printf(" - PCI-X Bus\n"); 5909 if (sc->bge_flags & BGE_PCIE) 5910 printf(" - PCI Express Bus\n"); 5911 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5912 printf(" - RX Alignment Bug\n"); 5913 if (sc->bge_flags & BGE_APE) 5914 printf(" - APE\n"); 5915 if (sc->bge_flags & BGE_CPMU_PRESENT) 5916 printf(" - CPMU\n"); 5917 if (sc->bge_flags & BGE_TSO) 5918 printf(" - TSO\n"); 5919 5920 if (sc->bge_flags & BGE_PHY_NO_3LED) 5921 printf(" - No 3 LEDs\n"); 5922 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5923 printf(" - CRC bug\n"); 5924 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5925 printf(" - ADC bug\n"); 5926 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5927 printf(" - 5704 A0 bug\n"); 5928 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5929 printf(" - jitter bug\n"); 5930 if (sc->bge_flags & BGE_PHY_BER_BUG) 5931 printf(" - BER bug\n"); 5932 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5933 printf(" - adjust trim\n"); 5934 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5935 printf(" - no wirespeed\n"); 5936 } 5937 #endif /* BGE_DEBUG */ 5938 5939 static int 5940 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5941 { 5942 prop_dictionary_t dict; 5943 prop_data_t ea; 5944 5945 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5946 return 1; 5947 5948 dict = device_properties(sc->bge_dev); 5949 ea = prop_dictionary_get(dict, "mac-address"); 5950 if (ea != NULL) { 5951 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5952 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5953 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5954 return 0; 5955 } 5956 5957 return 1; 5958 } 5959 5960 static int 5961 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5962 { 5963 uint32_t mac_addr; 5964 5965 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5966 if ((mac_addr >> 16) == 0x484b) { 5967 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5968 ether_addr[1] = (uint8_t)mac_addr; 5969 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5970 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5971 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5972 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5973 ether_addr[5] = (uint8_t)mac_addr; 5974 return 0; 5975 } 5976 return 1; 5977 } 5978 5979 static int 5980 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5981 { 5982 int mac_offset = BGE_EE_MAC_OFFSET; 5983 5984 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5985 mac_offset = BGE_EE_MAC_OFFSET_5906; 5986 5987 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5988 ETHER_ADDR_LEN)); 5989 } 5990 5991 static int 5992 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5993 { 5994 5995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5996 return 1; 5997 5998 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5999 ETHER_ADDR_LEN)); 6000 } 6001 6002 static int 6003 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6004 { 6005 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6006 /* NOTE: Order is critical */ 6007 bge_get_eaddr_fw, 6008 bge_get_eaddr_mem, 6009 bge_get_eaddr_nvram, 6010 bge_get_eaddr_eeprom, 6011 NULL 6012 }; 6013 const bge_eaddr_fcn_t *func; 6014 6015 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6016 if ((*func)(sc, eaddr) == 0) 6017 break; 6018 } 6019 return (*func == NULL ? ENXIO : 0); 6020 } 6021
Indexes created Tue Sep 23 07:09:52 GMT 2025