if_bge.c revision 1.254
1 /* $NetBSD: if_bge.c,v 1.254 2013/07/03 05:49:36 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.254 2013/07/03 05:49:36 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rnd.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 680 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 682 683 static const struct bge_revision { 684 uint32_t br_chipid; 685 const char *br_name; 686 } bge_revisions[] = { 687 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 688 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 689 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 690 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 691 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 692 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 693 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 694 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 695 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 696 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 697 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 698 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 699 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 700 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 701 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 702 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 703 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 704 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 705 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 706 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 707 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 708 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 709 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 710 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 711 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 712 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 713 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 714 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 715 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 716 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 717 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 718 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 719 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 720 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 721 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 722 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 723 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 724 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 725 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 726 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 727 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 728 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 729 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 730 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 731 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 732 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 733 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 734 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 735 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 736 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 737 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 738 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 739 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 740 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 741 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 742 /* 5754 and 5787 share the same ASIC ID */ 743 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 744 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 745 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 746 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 747 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 748 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 749 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 750 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 751 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 752 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 753 754 { 0, NULL } 755 }; 756 757 /* 758 * Some defaults for major revisions, so that newer steppings 759 * that we don't know about have a shot at working. 760 */ 761 static const struct bge_revision bge_majorrevs[] = { 762 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 763 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 764 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 765 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 766 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 767 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 768 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 769 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 771 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 772 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 773 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 774 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 775 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 776 /* 5754 and 5787 share the same ASIC ID */ 777 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 778 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 779 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 780 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 781 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 782 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 783 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 784 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 785 786 { 0, NULL } 787 }; 788 789 static int bge_allow_asf = 1; 790 791 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 792 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 793 794 static uint32_t 795 bge_readmem_ind(struct bge_softc *sc, int off) 796 { 797 pcireg_t val; 798 799 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 800 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 801 return 0; 802 803 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 804 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 806 return val; 807 } 808 809 static void 810 bge_writemem_ind(struct bge_softc *sc, int off, int val) 811 { 812 813 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 816 } 817 818 /* 819 * PCI Express only 820 */ 821 static void 822 bge_set_max_readrq(struct bge_softc *sc) 823 { 824 pcireg_t val; 825 826 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 827 + PCIE_DCSR); 828 val &= ~PCIE_DCSR_MAX_READ_REQ; 829 switch (sc->bge_expmrq) { 830 case 2048: 831 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 832 break; 833 case 4096: 834 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 835 break; 836 default: 837 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 838 break; 839 } 840 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 841 + PCIE_DCSR, val); 842 } 843 844 #ifdef notdef 845 static uint32_t 846 bge_readreg_ind(struct bge_softc *sc, int off) 847 { 848 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 849 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 850 } 851 #endif 852 853 static void 854 bge_writereg_ind(struct bge_softc *sc, int off, int val) 855 { 856 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 858 } 859 860 static void 861 bge_writemem_direct(struct bge_softc *sc, int off, int val) 862 { 863 CSR_WRITE_4(sc, off, val); 864 } 865 866 static void 867 bge_writembx(struct bge_softc *sc, int off, int val) 868 { 869 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 870 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 871 872 CSR_WRITE_4(sc, off, val); 873 } 874 875 static void 876 bge_writembx_flush(struct bge_softc *sc, int off, int val) 877 { 878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 879 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 880 881 CSR_WRITE_4_FLUSH(sc, off, val); 882 } 883 884 /* 885 * Clear all stale locks and select the lock for this driver instance. 886 */ 887 void 888 bge_ape_lock_init(struct bge_softc *sc) 889 { 890 struct pci_attach_args *pa = &(sc->bge_pa); 891 uint32_t bit, regbase; 892 int i; 893 894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 895 regbase = BGE_APE_LOCK_GRANT; 896 else 897 regbase = BGE_APE_PER_LOCK_GRANT; 898 899 /* Clear any stale locks. */ 900 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 901 switch (i) { 902 case BGE_APE_LOCK_PHY0: 903 case BGE_APE_LOCK_PHY1: 904 case BGE_APE_LOCK_PHY2: 905 case BGE_APE_LOCK_PHY3: 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 break; 908 default: 909 if (pa->pa_function == 0) 910 bit = BGE_APE_LOCK_GRANT_DRIVER0; 911 else 912 bit = (1 << pa->pa_function); 913 } 914 APE_WRITE_4(sc, regbase + 4 * i, bit); 915 } 916 917 /* Select the PHY lock based on the device's function number. */ 918 switch (pa->pa_function) { 919 case 0: 920 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 921 break; 922 case 1: 923 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 924 break; 925 case 2: 926 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 927 break; 928 case 3: 929 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 930 break; 931 default: 932 printf("%s: PHY lock not supported on function\n", 933 device_xname(sc->bge_dev)); 934 break; 935 } 936 } 937 938 /* 939 * Check for APE firmware, set flags, and print version info. 940 */ 941 void 942 bge_ape_read_fw_ver(struct bge_softc *sc) 943 { 944 const char *fwtype; 945 uint32_t apedata, features; 946 947 /* Check for a valid APE signature in shared memory. */ 948 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 949 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 950 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 951 return; 952 } 953 954 /* Check if APE firmware is running. */ 955 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 956 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 957 printf("%s: APE signature found but FW status not ready! " 958 "0x%08x\n", device_xname(sc->bge_dev), apedata); 959 return; 960 } 961 962 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 963 964 /* Fetch the APE firwmare type and version. */ 965 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 966 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 967 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 968 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 969 fwtype = "NCSI"; 970 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 971 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 972 fwtype = "DASH"; 973 } else 974 fwtype = "UNKN"; 975 976 /* Print the APE firmware version. */ 977 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 978 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 979 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 980 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 981 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 982 } 983 984 int 985 bge_ape_lock(struct bge_softc *sc, int locknum) 986 { 987 struct pci_attach_args *pa = &(sc->bge_pa); 988 uint32_t bit, gnt, req, status; 989 int i, off; 990 991 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 992 return (0); 993 994 /* Lock request/grant registers have different bases. */ 995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 996 req = BGE_APE_LOCK_REQ; 997 gnt = BGE_APE_LOCK_GRANT; 998 } else { 999 req = BGE_APE_PER_LOCK_REQ; 1000 gnt = BGE_APE_PER_LOCK_GRANT; 1001 } 1002 1003 off = 4 * locknum; 1004 1005 switch (locknum) { 1006 case BGE_APE_LOCK_GPIO: 1007 /* Lock required when using GPIO. */ 1008 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1009 return (0); 1010 if (pa->pa_function == 0) 1011 bit = BGE_APE_LOCK_REQ_DRIVER0; 1012 else 1013 bit = (1 << pa->pa_function); 1014 break; 1015 case BGE_APE_LOCK_GRC: 1016 /* Lock required to reset the device. */ 1017 if (pa->pa_function == 0) 1018 bit = BGE_APE_LOCK_REQ_DRIVER0; 1019 else 1020 bit = (1 << pa->pa_function); 1021 break; 1022 case BGE_APE_LOCK_MEM: 1023 /* Lock required when accessing certain APE memory. */ 1024 if (pa->pa_function == 0) 1025 bit = BGE_APE_LOCK_REQ_DRIVER0; 1026 else 1027 bit = (1 << pa->pa_function); 1028 break; 1029 case BGE_APE_LOCK_PHY0: 1030 case BGE_APE_LOCK_PHY1: 1031 case BGE_APE_LOCK_PHY2: 1032 case BGE_APE_LOCK_PHY3: 1033 /* Lock required when accessing PHYs. */ 1034 bit = BGE_APE_LOCK_REQ_DRIVER0; 1035 break; 1036 default: 1037 return (EINVAL); 1038 } 1039 1040 /* Request a lock. */ 1041 APE_WRITE_4_FLUSH(sc, req + off, bit); 1042 1043 /* Wait up to 1 second to acquire lock. */ 1044 for (i = 0; i < 20000; i++) { 1045 status = APE_READ_4(sc, gnt + off); 1046 if (status == bit) 1047 break; 1048 DELAY(50); 1049 } 1050 1051 /* Handle any errors. */ 1052 if (status != bit) { 1053 printf("%s: APE lock %d request failed! " 1054 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1055 device_xname(sc->bge_dev), 1056 locknum, req + off, bit & 0xFFFF, gnt + off, 1057 status & 0xFFFF); 1058 /* Revoke the lock request. */ 1059 APE_WRITE_4(sc, gnt + off, bit); 1060 return (EBUSY); 1061 } 1062 1063 return (0); 1064 } 1065 1066 void 1067 bge_ape_unlock(struct bge_softc *sc, int locknum) 1068 { 1069 struct pci_attach_args *pa = &(sc->bge_pa); 1070 uint32_t bit, gnt; 1071 int off; 1072 1073 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1074 return; 1075 1076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1077 gnt = BGE_APE_LOCK_GRANT; 1078 else 1079 gnt = BGE_APE_PER_LOCK_GRANT; 1080 1081 off = 4 * locknum; 1082 1083 switch (locknum) { 1084 case BGE_APE_LOCK_GPIO: 1085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1086 return; 1087 if (pa->pa_function == 0) 1088 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1089 else 1090 bit = (1 << pa->pa_function); 1091 break; 1092 case BGE_APE_LOCK_GRC: 1093 if (pa->pa_function == 0) 1094 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1095 else 1096 bit = (1 << pa->pa_function); 1097 break; 1098 case BGE_APE_LOCK_MEM: 1099 if (pa->pa_function == 0) 1100 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1101 else 1102 bit = (1 << pa->pa_function); 1103 break; 1104 case BGE_APE_LOCK_PHY0: 1105 case BGE_APE_LOCK_PHY1: 1106 case BGE_APE_LOCK_PHY2: 1107 case BGE_APE_LOCK_PHY3: 1108 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1109 break; 1110 default: 1111 return; 1112 } 1113 1114 /* Write and flush for consecutive bge_ape_lock() */ 1115 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1116 } 1117 1118 /* 1119 * Send an event to the APE firmware. 1120 */ 1121 void 1122 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1123 { 1124 uint32_t apedata; 1125 int i; 1126 1127 /* NCSI does not support APE events. */ 1128 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1129 return; 1130 1131 /* Wait up to 1ms for APE to service previous event. */ 1132 for (i = 10; i > 0; i--) { 1133 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1134 break; 1135 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1136 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1137 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1138 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1141 break; 1142 } 1143 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1144 DELAY(100); 1145 } 1146 if (i == 0) { 1147 printf("%s: APE event 0x%08x send timed out\n", 1148 device_xname(sc->bge_dev), event); 1149 } 1150 } 1151 1152 void 1153 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1154 { 1155 uint32_t apedata, event; 1156 1157 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1158 return; 1159 1160 switch (kind) { 1161 case BGE_RESET_START: 1162 /* If this is the first load, clear the load counter. */ 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1164 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1165 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1166 else { 1167 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1168 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1169 } 1170 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1171 BGE_APE_HOST_SEG_SIG_MAGIC); 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1173 BGE_APE_HOST_SEG_LEN_MAGIC); 1174 1175 /* Add some version info if bge(4) supports it. */ 1176 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1177 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1178 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1179 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1180 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1181 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1182 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1183 BGE_APE_HOST_DRVR_STATE_START); 1184 event = BGE_APE_EVENT_STATUS_STATE_START; 1185 break; 1186 case BGE_RESET_SHUTDOWN: 1187 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1188 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1189 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1190 break; 1191 case BGE_RESET_SUSPEND: 1192 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1193 break; 1194 default: 1195 return; 1196 } 1197 1198 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1199 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1200 } 1201 1202 static uint8_t 1203 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1204 { 1205 uint32_t access, byte = 0; 1206 int i; 1207 1208 /* Lock. */ 1209 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1210 for (i = 0; i < 8000; i++) { 1211 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1212 break; 1213 DELAY(20); 1214 } 1215 if (i == 8000) 1216 return 1; 1217 1218 /* Enable access. */ 1219 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1220 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1221 1222 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1223 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1224 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1225 DELAY(10); 1226 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1227 DELAY(10); 1228 break; 1229 } 1230 } 1231 1232 if (i == BGE_TIMEOUT * 10) { 1233 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1234 return 1; 1235 } 1236 1237 /* Get result. */ 1238 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1239 1240 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1241 1242 /* Disable access. */ 1243 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1244 1245 /* Unlock. */ 1246 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1247 1248 return 0; 1249 } 1250 1251 /* 1252 * Read a sequence of bytes from NVRAM. 1253 */ 1254 static int 1255 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1256 { 1257 int error = 0, i; 1258 uint8_t byte = 0; 1259 1260 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1261 return 1; 1262 1263 for (i = 0; i < cnt; i++) { 1264 error = bge_nvram_getbyte(sc, off + i, &byte); 1265 if (error) 1266 break; 1267 *(dest + i) = byte; 1268 } 1269 1270 return (error ? 1 : 0); 1271 } 1272 1273 /* 1274 * Read a byte of data stored in the EEPROM at address 'addr.' The 1275 * BCM570x supports both the traditional bitbang interface and an 1276 * auto access interface for reading the EEPROM. We use the auto 1277 * access method. 1278 */ 1279 static uint8_t 1280 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1281 { 1282 int i; 1283 uint32_t byte = 0; 1284 1285 /* 1286 * Enable use of auto EEPROM access so we can avoid 1287 * having to use the bitbang method. 1288 */ 1289 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1290 1291 /* Reset the EEPROM, load the clock period. */ 1292 CSR_WRITE_4(sc, BGE_EE_ADDR, 1293 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1294 DELAY(20); 1295 1296 /* Issue the read EEPROM command. */ 1297 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1298 1299 /* Wait for completion */ 1300 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1301 DELAY(10); 1302 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1303 break; 1304 } 1305 1306 if (i == BGE_TIMEOUT * 10) { 1307 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1308 return 1; 1309 } 1310 1311 /* Get result. */ 1312 byte = CSR_READ_4(sc, BGE_EE_DATA); 1313 1314 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1315 1316 return 0; 1317 } 1318 1319 /* 1320 * Read a sequence of bytes from the EEPROM. 1321 */ 1322 static int 1323 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1324 { 1325 int error = 0, i; 1326 uint8_t byte = 0; 1327 char *dest = destv; 1328 1329 for (i = 0; i < cnt; i++) { 1330 error = bge_eeprom_getbyte(sc, off + i, &byte); 1331 if (error) 1332 break; 1333 *(dest + i) = byte; 1334 } 1335 1336 return (error ? 1 : 0); 1337 } 1338 1339 static int 1340 bge_miibus_readreg(device_t dev, int phy, int reg) 1341 { 1342 struct bge_softc *sc = device_private(dev); 1343 uint32_t val; 1344 uint32_t autopoll; 1345 int i; 1346 1347 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1348 return 0; 1349 1350 /* Reading with autopolling on may trigger PCI errors */ 1351 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1352 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1353 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1354 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1355 DELAY(80); 1356 } 1357 1358 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1359 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1360 1361 for (i = 0; i < BGE_TIMEOUT; i++) { 1362 delay(10); 1363 val = CSR_READ_4(sc, BGE_MI_COMM); 1364 if (!(val & BGE_MICOMM_BUSY)) { 1365 DELAY(5); 1366 val = CSR_READ_4(sc, BGE_MI_COMM); 1367 break; 1368 } 1369 } 1370 1371 if (i == BGE_TIMEOUT) { 1372 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1373 val = 0; 1374 goto done; 1375 } 1376 1377 done: 1378 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1379 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1380 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1381 DELAY(80); 1382 } 1383 1384 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1385 1386 if (val & BGE_MICOMM_READFAIL) 1387 return 0; 1388 1389 return (val & 0xFFFF); 1390 } 1391 1392 static void 1393 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1394 { 1395 struct bge_softc *sc = device_private(dev); 1396 uint32_t autopoll; 1397 int i; 1398 1399 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1400 return; 1401 1402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1403 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1404 return; 1405 1406 /* Reading with autopolling on may trigger PCI errors */ 1407 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1408 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1409 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1410 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1411 DELAY(80); 1412 } 1413 1414 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1415 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1416 1417 for (i = 0; i < BGE_TIMEOUT; i++) { 1418 delay(10); 1419 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1420 delay(5); 1421 CSR_READ_4(sc, BGE_MI_COMM); 1422 break; 1423 } 1424 } 1425 1426 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1427 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1428 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1429 delay(80); 1430 } 1431 1432 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1433 1434 if (i == BGE_TIMEOUT) 1435 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1436 } 1437 1438 static void 1439 bge_miibus_statchg(struct ifnet *ifp) 1440 { 1441 struct bge_softc *sc = ifp->if_softc; 1442 struct mii_data *mii = &sc->bge_mii; 1443 uint32_t mac_mode, rx_mode, tx_mode; 1444 1445 /* 1446 * Get flow control negotiation result. 1447 */ 1448 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1449 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1450 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1451 mii->mii_media_active &= ~IFM_ETH_FMASK; 1452 } 1453 1454 /* Set the port mode (MII/GMII) to match the link speed. */ 1455 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1456 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1457 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1458 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1459 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1460 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1461 mac_mode |= BGE_PORTMODE_GMII; 1462 else 1463 mac_mode |= BGE_PORTMODE_MII; 1464 1465 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1466 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1467 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1468 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1469 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1470 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1471 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1472 } else 1473 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1474 1475 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1476 DELAY(40); 1477 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1478 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1479 } 1480 1481 /* 1482 * Update rx threshold levels to values in a particular slot 1483 * of the interrupt-mitigation table bge_rx_threshes. 1484 */ 1485 static void 1486 bge_set_thresh(struct ifnet *ifp, int lvl) 1487 { 1488 struct bge_softc *sc = ifp->if_softc; 1489 int s; 1490 1491 /* For now, just save the new Rx-intr thresholds and record 1492 * that a threshold update is pending. Updating the hardware 1493 * registers here (even at splhigh()) is observed to 1494 * occasionaly cause glitches where Rx-interrupts are not 1495 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1496 */ 1497 s = splnet(); 1498 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1499 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1500 sc->bge_pending_rxintr_change = 1; 1501 splx(s); 1502 } 1503 1504 1505 /* 1506 * Update Rx thresholds of all bge devices 1507 */ 1508 static void 1509 bge_update_all_threshes(int lvl) 1510 { 1511 struct ifnet *ifp; 1512 const char * const namebuf = "bge"; 1513 int namelen; 1514 1515 if (lvl < 0) 1516 lvl = 0; 1517 else if (lvl >= NBGE_RX_THRESH) 1518 lvl = NBGE_RX_THRESH - 1; 1519 1520 namelen = strlen(namebuf); 1521 /* 1522 * Now search all the interfaces for this name/number 1523 */ 1524 IFNET_FOREACH(ifp) { 1525 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1526 continue; 1527 /* We got a match: update if doing auto-threshold-tuning */ 1528 if (bge_auto_thresh) 1529 bge_set_thresh(ifp, lvl); 1530 } 1531 } 1532 1533 /* 1534 * Handle events that have triggered interrupts. 1535 */ 1536 static void 1537 bge_handle_events(struct bge_softc *sc) 1538 { 1539 1540 return; 1541 } 1542 1543 /* 1544 * Memory management for jumbo frames. 1545 */ 1546 1547 static int 1548 bge_alloc_jumbo_mem(struct bge_softc *sc) 1549 { 1550 char *ptr, *kva; 1551 bus_dma_segment_t seg; 1552 int i, rseg, state, error; 1553 struct bge_jpool_entry *entry; 1554 1555 state = error = 0; 1556 1557 /* Grab a big chunk o' storage. */ 1558 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1560 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1561 return ENOBUFS; 1562 } 1563 1564 state = 1; 1565 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1566 BUS_DMA_NOWAIT)) { 1567 aprint_error_dev(sc->bge_dev, 1568 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1569 error = ENOBUFS; 1570 goto out; 1571 } 1572 1573 state = 2; 1574 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1575 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1576 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1577 error = ENOBUFS; 1578 goto out; 1579 } 1580 1581 state = 3; 1582 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1583 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1584 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1585 error = ENOBUFS; 1586 goto out; 1587 } 1588 1589 state = 4; 1590 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1591 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1592 1593 SLIST_INIT(&sc->bge_jfree_listhead); 1594 SLIST_INIT(&sc->bge_jinuse_listhead); 1595 1596 /* 1597 * Now divide it up into 9K pieces and save the addresses 1598 * in an array. 1599 */ 1600 ptr = sc->bge_cdata.bge_jumbo_buf; 1601 for (i = 0; i < BGE_JSLOTS; i++) { 1602 sc->bge_cdata.bge_jslots[i] = ptr; 1603 ptr += BGE_JLEN; 1604 entry = malloc(sizeof(struct bge_jpool_entry), 1605 M_DEVBUF, M_NOWAIT); 1606 if (entry == NULL) { 1607 aprint_error_dev(sc->bge_dev, 1608 "no memory for jumbo buffer queue!\n"); 1609 error = ENOBUFS; 1610 goto out; 1611 } 1612 entry->slot = i; 1613 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1614 entry, jpool_entries); 1615 } 1616 out: 1617 if (error != 0) { 1618 switch (state) { 1619 case 4: 1620 bus_dmamap_unload(sc->bge_dmatag, 1621 sc->bge_cdata.bge_rx_jumbo_map); 1622 case 3: 1623 bus_dmamap_destroy(sc->bge_dmatag, 1624 sc->bge_cdata.bge_rx_jumbo_map); 1625 case 2: 1626 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1627 case 1: 1628 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1629 break; 1630 default: 1631 break; 1632 } 1633 } 1634 1635 return error; 1636 } 1637 1638 /* 1639 * Allocate a jumbo buffer. 1640 */ 1641 static void * 1642 bge_jalloc(struct bge_softc *sc) 1643 { 1644 struct bge_jpool_entry *entry; 1645 1646 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1647 1648 if (entry == NULL) { 1649 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1650 return NULL; 1651 } 1652 1653 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1654 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1655 return (sc->bge_cdata.bge_jslots[entry->slot]); 1656 } 1657 1658 /* 1659 * Release a jumbo buffer. 1660 */ 1661 static void 1662 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1663 { 1664 struct bge_jpool_entry *entry; 1665 struct bge_softc *sc; 1666 int i, s; 1667 1668 /* Extract the softc struct pointer. */ 1669 sc = (struct bge_softc *)arg; 1670 1671 if (sc == NULL) 1672 panic("bge_jfree: can't find softc pointer!"); 1673 1674 /* calculate the slot this buffer belongs to */ 1675 1676 i = ((char *)buf 1677 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1678 1679 if ((i < 0) || (i >= BGE_JSLOTS)) 1680 panic("bge_jfree: asked to free buffer that we don't manage!"); 1681 1682 s = splvm(); 1683 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1684 if (entry == NULL) 1685 panic("bge_jfree: buffer not in use!"); 1686 entry->slot = i; 1687 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1688 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1689 1690 if (__predict_true(m != NULL)) 1691 pool_cache_put(mb_cache, m); 1692 splx(s); 1693 } 1694 1695 1696 /* 1697 * Initialize a standard receive ring descriptor. 1698 */ 1699 static int 1700 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1701 bus_dmamap_t dmamap) 1702 { 1703 struct mbuf *m_new = NULL; 1704 struct bge_rx_bd *r; 1705 int error; 1706 1707 if (dmamap == NULL) { 1708 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1709 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1710 if (error != 0) 1711 return error; 1712 } 1713 1714 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1715 1716 if (m == NULL) { 1717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1718 if (m_new == NULL) 1719 return ENOBUFS; 1720 1721 MCLGET(m_new, M_DONTWAIT); 1722 if (!(m_new->m_flags & M_EXT)) { 1723 m_freem(m_new); 1724 return ENOBUFS; 1725 } 1726 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1727 1728 } else { 1729 m_new = m; 1730 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1731 m_new->m_data = m_new->m_ext.ext_buf; 1732 } 1733 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1734 m_adj(m_new, ETHER_ALIGN); 1735 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1736 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1737 return ENOBUFS; 1738 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1739 BUS_DMASYNC_PREREAD); 1740 1741 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1742 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1743 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1744 r->bge_flags = BGE_RXBDFLAG_END; 1745 r->bge_len = m_new->m_len; 1746 r->bge_idx = i; 1747 1748 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1749 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1750 i * sizeof (struct bge_rx_bd), 1751 sizeof (struct bge_rx_bd), 1752 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1753 1754 return 0; 1755 } 1756 1757 /* 1758 * Initialize a jumbo receive ring descriptor. This allocates 1759 * a jumbo buffer from the pool managed internally by the driver. 1760 */ 1761 static int 1762 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1763 { 1764 struct mbuf *m_new = NULL; 1765 struct bge_rx_bd *r; 1766 void *buf = NULL; 1767 1768 if (m == NULL) { 1769 1770 /* Allocate the mbuf. */ 1771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1772 if (m_new == NULL) 1773 return ENOBUFS; 1774 1775 /* Allocate the jumbo buffer */ 1776 buf = bge_jalloc(sc); 1777 if (buf == NULL) { 1778 m_freem(m_new); 1779 aprint_error_dev(sc->bge_dev, 1780 "jumbo allocation failed -- packet dropped!\n"); 1781 return ENOBUFS; 1782 } 1783 1784 /* Attach the buffer to the mbuf. */ 1785 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1786 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1787 bge_jfree, sc); 1788 m_new->m_flags |= M_EXT_RW; 1789 } else { 1790 m_new = m; 1791 buf = m_new->m_data = m_new->m_ext.ext_buf; 1792 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1793 } 1794 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1795 m_adj(m_new, ETHER_ALIGN); 1796 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1797 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1798 BUS_DMASYNC_PREREAD); 1799 /* Set up the descriptor. */ 1800 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1801 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1802 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1803 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1804 r->bge_len = m_new->m_len; 1805 r->bge_idx = i; 1806 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1808 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1809 i * sizeof (struct bge_rx_bd), 1810 sizeof (struct bge_rx_bd), 1811 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1812 1813 return 0; 1814 } 1815 1816 /* 1817 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1818 * that's 1MB or memory, which is a lot. For now, we fill only the first 1819 * 256 ring entries and hope that our CPU is fast enough to keep up with 1820 * the NIC. 1821 */ 1822 static int 1823 bge_init_rx_ring_std(struct bge_softc *sc) 1824 { 1825 int i; 1826 1827 if (sc->bge_flags & BGE_RXRING_VALID) 1828 return 0; 1829 1830 for (i = 0; i < BGE_SSLOTS; i++) { 1831 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1832 return ENOBUFS; 1833 } 1834 1835 sc->bge_std = i - 1; 1836 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1837 1838 sc->bge_flags |= BGE_RXRING_VALID; 1839 1840 return 0; 1841 } 1842 1843 static void 1844 bge_free_rx_ring_std(struct bge_softc *sc) 1845 { 1846 int i; 1847 1848 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1849 return; 1850 1851 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1852 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1853 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1854 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1855 bus_dmamap_destroy(sc->bge_dmatag, 1856 sc->bge_cdata.bge_rx_std_map[i]); 1857 } 1858 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1859 sizeof(struct bge_rx_bd)); 1860 } 1861 1862 sc->bge_flags &= ~BGE_RXRING_VALID; 1863 } 1864 1865 static int 1866 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1867 { 1868 int i; 1869 volatile struct bge_rcb *rcb; 1870 1871 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1872 return 0; 1873 1874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1875 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1876 return ENOBUFS; 1877 } 1878 1879 sc->bge_jumbo = i - 1; 1880 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1881 1882 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1883 rcb->bge_maxlen_flags = 0; 1884 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1885 1886 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1887 1888 return 0; 1889 } 1890 1891 static void 1892 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1893 { 1894 int i; 1895 1896 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1897 return; 1898 1899 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1900 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1901 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1902 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1903 } 1904 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1905 sizeof(struct bge_rx_bd)); 1906 } 1907 1908 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1909 } 1910 1911 static void 1912 bge_free_tx_ring(struct bge_softc *sc) 1913 { 1914 int i; 1915 struct txdmamap_pool_entry *dma; 1916 1917 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1918 return; 1919 1920 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1921 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1922 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1923 sc->bge_cdata.bge_tx_chain[i] = NULL; 1924 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1925 link); 1926 sc->txdma[i] = 0; 1927 } 1928 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1929 sizeof(struct bge_tx_bd)); 1930 } 1931 1932 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1933 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1934 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1935 free(dma, M_DEVBUF); 1936 } 1937 1938 sc->bge_flags &= ~BGE_TXRING_VALID; 1939 } 1940 1941 static int 1942 bge_init_tx_ring(struct bge_softc *sc) 1943 { 1944 int i; 1945 bus_dmamap_t dmamap; 1946 struct txdmamap_pool_entry *dma; 1947 1948 if (sc->bge_flags & BGE_TXRING_VALID) 1949 return 0; 1950 1951 sc->bge_txcnt = 0; 1952 sc->bge_tx_saved_considx = 0; 1953 1954 /* Initialize transmit producer index for host-memory send ring. */ 1955 sc->bge_tx_prodidx = 0; 1956 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1957 /* 5700 b2 errata */ 1958 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1959 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1960 1961 /* NIC-memory send ring not used; initialize to zero. */ 1962 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1963 /* 5700 b2 errata */ 1964 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1965 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1966 1967 SLIST_INIT(&sc->txdma_list); 1968 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1969 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1970 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1971 &dmamap)) 1972 return ENOBUFS; 1973 if (dmamap == NULL) 1974 panic("dmamap NULL in bge_init_tx_ring"); 1975 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1976 if (dma == NULL) { 1977 aprint_error_dev(sc->bge_dev, 1978 "can't alloc txdmamap_pool_entry\n"); 1979 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1980 return ENOMEM; 1981 } 1982 dma->dmamap = dmamap; 1983 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1984 } 1985 1986 sc->bge_flags |= BGE_TXRING_VALID; 1987 1988 return 0; 1989 } 1990 1991 static void 1992 bge_setmulti(struct bge_softc *sc) 1993 { 1994 struct ethercom *ac = &sc->ethercom; 1995 struct ifnet *ifp = &ac->ec_if; 1996 struct ether_multi *enm; 1997 struct ether_multistep step; 1998 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1999 uint32_t h; 2000 int i; 2001 2002 if (ifp->if_flags & IFF_PROMISC) 2003 goto allmulti; 2004 2005 /* Now program new ones. */ 2006 ETHER_FIRST_MULTI(step, ac, enm); 2007 while (enm != NULL) { 2008 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2009 /* 2010 * We must listen to a range of multicast addresses. 2011 * For now, just accept all multicasts, rather than 2012 * trying to set only those filter bits needed to match 2013 * the range. (At this time, the only use of address 2014 * ranges is for IP multicast routing, for which the 2015 * range is big enough to require all bits set.) 2016 */ 2017 goto allmulti; 2018 } 2019 2020 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2021 2022 /* Just want the 7 least-significant bits. */ 2023 h &= 0x7f; 2024 2025 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2026 ETHER_NEXT_MULTI(step, enm); 2027 } 2028 2029 ifp->if_flags &= ~IFF_ALLMULTI; 2030 goto setit; 2031 2032 allmulti: 2033 ifp->if_flags |= IFF_ALLMULTI; 2034 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2035 2036 setit: 2037 for (i = 0; i < 4; i++) 2038 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2039 } 2040 2041 static void 2042 bge_sig_pre_reset(struct bge_softc *sc, int type) 2043 { 2044 2045 /* 2046 * Some chips don't like this so only do this if ASF is enabled 2047 */ 2048 if (sc->bge_asf_mode) 2049 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2050 2051 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2052 switch (type) { 2053 case BGE_RESET_START: 2054 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2055 BGE_FW_DRV_STATE_START); 2056 break; 2057 case BGE_RESET_SHUTDOWN: 2058 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2059 BGE_FW_DRV_STATE_UNLOAD); 2060 break; 2061 case BGE_RESET_SUSPEND: 2062 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2063 BGE_FW_DRV_STATE_SUSPEND); 2064 break; 2065 } 2066 } 2067 2068 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2069 bge_ape_driver_state_change(sc, type); 2070 } 2071 2072 static void 2073 bge_sig_post_reset(struct bge_softc *sc, int type) 2074 { 2075 2076 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2077 switch (type) { 2078 case BGE_RESET_START: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_START_DONE); 2081 /* START DONE */ 2082 break; 2083 case BGE_RESET_SHUTDOWN: 2084 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2085 BGE_FW_DRV_STATE_UNLOAD_DONE); 2086 break; 2087 } 2088 } 2089 2090 if (type == BGE_RESET_SHUTDOWN) 2091 bge_ape_driver_state_change(sc, type); 2092 } 2093 2094 static void 2095 bge_sig_legacy(struct bge_softc *sc, int type) 2096 { 2097 2098 if (sc->bge_asf_mode) { 2099 switch (type) { 2100 case BGE_RESET_START: 2101 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2102 BGE_FW_DRV_STATE_START); 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD); 2107 break; 2108 } 2109 } 2110 } 2111 2112 static void 2113 bge_wait_for_event_ack(struct bge_softc *sc) 2114 { 2115 int i; 2116 2117 /* wait up to 2500usec */ 2118 for (i = 0; i < 250; i++) { 2119 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2120 BGE_RX_CPU_DRV_EVENT)) 2121 break; 2122 DELAY(10); 2123 } 2124 } 2125 2126 static void 2127 bge_stop_fw(struct bge_softc *sc) 2128 { 2129 2130 if (sc->bge_asf_mode) { 2131 bge_wait_for_event_ack(sc); 2132 2133 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2134 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2135 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2136 2137 bge_wait_for_event_ack(sc); 2138 } 2139 } 2140 2141 static int 2142 bge_poll_fw(struct bge_softc *sc) 2143 { 2144 uint32_t val; 2145 int i; 2146 2147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2148 for (i = 0; i < BGE_TIMEOUT; i++) { 2149 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2150 if (val & BGE_VCPU_STATUS_INIT_DONE) 2151 break; 2152 DELAY(100); 2153 } 2154 if (i >= BGE_TIMEOUT) { 2155 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2156 return -1; 2157 } 2158 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2159 /* 2160 * Poll the value location we just wrote until 2161 * we see the 1's complement of the magic number. 2162 * This indicates that the firmware initialization 2163 * is complete. 2164 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2165 */ 2166 for (i = 0; i < BGE_TIMEOUT; i++) { 2167 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2168 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2169 break; 2170 DELAY(10); 2171 } 2172 2173 if (i >= BGE_TIMEOUT) { 2174 aprint_error_dev(sc->bge_dev, 2175 "firmware handshake timed out, val = %x\n", val); 2176 return -1; 2177 } 2178 } 2179 2180 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2181 /* tg3 says we have to wait extra time */ 2182 delay(10 * 1000); 2183 } 2184 2185 return 0; 2186 } 2187 2188 int 2189 bge_phy_addr(struct bge_softc *sc) 2190 { 2191 struct pci_attach_args *pa = &(sc->bge_pa); 2192 int phy_addr = 1; 2193 2194 /* 2195 * PHY address mapping for various devices. 2196 * 2197 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2198 * ---------+-------+-------+-------+-------+ 2199 * BCM57XX | 1 | X | X | X | 2200 * BCM5704 | 1 | X | 1 | X | 2201 * BCM5717 | 1 | 8 | 2 | 9 | 2202 * BCM5719 | 1 | 8 | 2 | 9 | 2203 * BCM5720 | 1 | 8 | 2 | 9 | 2204 * 2205 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2206 * ---------+-------+-------+-------+-------+ 2207 * BCM57XX | X | X | X | X | 2208 * BCM5704 | X | X | X | X | 2209 * BCM5717 | X | X | X | X | 2210 * BCM5719 | 3 | 10 | 4 | 11 | 2211 * BCM5720 | X | X | X | X | 2212 * 2213 * Other addresses may respond but they are not 2214 * IEEE compliant PHYs and should be ignored. 2215 */ 2216 switch (BGE_ASICREV(sc->bge_chipid)) { 2217 case BGE_ASICREV_BCM5717: 2218 case BGE_ASICREV_BCM5719: 2219 case BGE_ASICREV_BCM5720: 2220 phy_addr = pa->pa_function; 2221 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2222 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2223 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2224 } else { 2225 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2226 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2227 } 2228 } 2229 2230 return phy_addr; 2231 } 2232 2233 /* 2234 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2235 * self-test results. 2236 */ 2237 static int 2238 bge_chipinit(struct bge_softc *sc) 2239 { 2240 uint32_t dma_rw_ctl, mode_ctl, reg; 2241 int i; 2242 2243 /* Set endianness before we access any non-PCI registers. */ 2244 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2245 BGE_INIT); 2246 2247 /* 2248 * Clear the MAC statistics block in the NIC's 2249 * internal memory. 2250 */ 2251 for (i = BGE_STATS_BLOCK; 2252 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2253 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2254 2255 for (i = BGE_STATUS_BLOCK; 2256 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2257 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2258 2259 /* 5717 workaround from tg3 */ 2260 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2261 /* Save */ 2262 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2263 2264 /* Temporary modify MODE_CTL to control TLP */ 2265 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2266 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2267 2268 /* Control TLP */ 2269 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2270 BGE_TLP_PHYCTL1); 2271 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2272 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2273 2274 /* Restore */ 2275 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2276 } 2277 2278 /* XXX Should we use 57765_FAMILY? */ 2279 if (BGE_IS_57765_PLUS(sc)) { 2280 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2281 /* Save */ 2282 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2283 2284 /* Temporary modify MODE_CTL to control TLP */ 2285 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2286 CSR_WRITE_4(sc, BGE_MODE_CTL, 2287 reg | BGE_MODECTL_PCIE_TLPADDR1); 2288 2289 /* Control TLP */ 2290 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2291 BGE_TLP_PHYCTL5); 2292 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2293 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2294 2295 /* Restore */ 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2297 } 2298 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2299 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2300 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2301 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2302 2303 /* Save */ 2304 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2305 2306 /* Temporary modify MODE_CTL to control TLP */ 2307 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2308 CSR_WRITE_4(sc, BGE_MODE_CTL, 2309 reg | BGE_MODECTL_PCIE_TLPADDR0); 2310 2311 /* Control TLP */ 2312 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2313 BGE_TLP_FTSMAX); 2314 reg &= ~BGE_TLP_FTSMAX_MSK; 2315 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2316 reg | BGE_TLP_FTSMAX_VAL); 2317 2318 /* Restore */ 2319 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2320 } 2321 2322 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2323 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2324 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2325 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2326 } 2327 2328 /* Set up the PCI DMA control register. */ 2329 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2330 if (sc->bge_flags & BGE_PCIE) { 2331 /* Read watermark not used, 128 bytes for write. */ 2332 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2333 device_xname(sc->bge_dev))); 2334 if (sc->bge_mps >= 256) 2335 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2336 else 2337 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2338 } else if (sc->bge_flags & BGE_PCIX) { 2339 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2340 device_xname(sc->bge_dev))); 2341 /* PCI-X bus */ 2342 if (BGE_IS_5714_FAMILY(sc)) { 2343 /* 256 bytes for read and write. */ 2344 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2345 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2346 2347 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2348 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2349 else 2350 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2351 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2352 /* 1536 bytes for read, 384 bytes for write. */ 2353 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2354 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2355 } else { 2356 /* 384 bytes for read and write. */ 2357 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2358 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2359 (0x0F); 2360 } 2361 2362 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2363 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2364 uint32_t tmp; 2365 2366 /* Set ONEDMA_ATONCE for hardware workaround. */ 2367 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2368 if (tmp == 6 || tmp == 7) 2369 dma_rw_ctl |= 2370 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2371 2372 /* Set PCI-X DMA write workaround. */ 2373 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2374 } 2375 } else { 2376 /* Conventional PCI bus: 256 bytes for read and write. */ 2377 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2378 device_xname(sc->bge_dev))); 2379 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2380 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2381 2382 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2383 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2384 dma_rw_ctl |= 0x0F; 2385 } 2386 2387 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2388 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2389 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2390 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2391 2392 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2393 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2394 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2395 2396 if (BGE_IS_5717_PLUS(sc)) { 2397 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2398 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2399 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2400 2401 /* 2402 * Enable HW workaround for controllers that misinterpret 2403 * a status tag update and leave interrupts permanently 2404 * disabled. 2405 */ 2406 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2407 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2408 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2409 } 2410 2411 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2412 dma_rw_ctl); 2413 2414 /* 2415 * Set up general mode register. 2416 */ 2417 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2418 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2419 /* Retain Host-2-BMC settings written by APE firmware. */ 2420 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2421 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2422 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2423 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2424 } 2425 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2426 BGE_MODECTL_TX_NO_PHDR_CSUM; 2427 2428 /* 2429 * BCM5701 B5 have a bug causing data corruption when using 2430 * 64-bit DMA reads, which can be terminated early and then 2431 * completed later as 32-bit accesses, in combination with 2432 * certain bridges. 2433 */ 2434 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2435 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2436 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2437 2438 /* 2439 * Tell the firmware the driver is running 2440 */ 2441 if (sc->bge_asf_mode & ASF_STACKUP) 2442 mode_ctl |= BGE_MODECTL_STACKUP; 2443 2444 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2445 2446 /* 2447 * Disable memory write invalidate. Apparently it is not supported 2448 * properly by these devices. 2449 */ 2450 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2451 PCI_COMMAND_INVALIDATE_ENABLE); 2452 2453 #ifdef __brokenalpha__ 2454 /* 2455 * Must insure that we do not cross an 8K (bytes) boundary 2456 * for DMA reads. Our highest limit is 1K bytes. This is a 2457 * restriction on some ALPHA platforms with early revision 2458 * 21174 PCI chipsets, such as the AlphaPC 164lx 2459 */ 2460 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2461 #endif 2462 2463 /* Set the timer prescaler (always 66MHz) */ 2464 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2465 2466 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2467 DELAY(40); /* XXX */ 2468 2469 /* Put PHY into ready state */ 2470 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2471 DELAY(40); 2472 } 2473 2474 return 0; 2475 } 2476 2477 static int 2478 bge_blockinit(struct bge_softc *sc) 2479 { 2480 volatile struct bge_rcb *rcb; 2481 bus_size_t rcb_addr; 2482 struct ifnet *ifp = &sc->ethercom.ec_if; 2483 bge_hostaddr taddr; 2484 uint32_t dmactl, val; 2485 int i, limit; 2486 2487 /* 2488 * Initialize the memory window pointer register so that 2489 * we can access the first 32K of internal NIC RAM. This will 2490 * allow us to set up the TX send ring RCBs and the RX return 2491 * ring RCBs, plus other things which live in NIC memory. 2492 */ 2493 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2494 2495 if (!BGE_IS_5705_PLUS(sc)) { 2496 /* 57XX step 33 */ 2497 /* Configure mbuf memory pool */ 2498 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2499 BGE_BUFFPOOL_1); 2500 2501 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2503 else 2504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2505 2506 /* 57XX step 34 */ 2507 /* Configure DMA resource pool */ 2508 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2509 BGE_DMA_DESCRIPTORS); 2510 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2511 } 2512 2513 /* 5718 step 11, 57XX step 35 */ 2514 /* 2515 * Configure mbuf pool watermarks. New broadcom docs strongly 2516 * recommend these. 2517 */ 2518 if (BGE_IS_5717_PLUS(sc)) { 2519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2521 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2522 } else if (BGE_IS_5705_PLUS(sc)) { 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2524 2525 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2526 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2528 } else { 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2530 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2531 } 2532 } else { 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2534 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2535 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2536 } 2537 2538 /* 57XX step 36 */ 2539 /* Configure DMA resource watermarks */ 2540 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2541 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2542 2543 /* 5718 step 13, 57XX step 38 */ 2544 /* Enable buffer manager */ 2545 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2546 /* 2547 * Change the arbitration algorithm of TXMBUF read request to 2548 * round-robin instead of priority based for BCM5719. When 2549 * TXFIFO is almost empty, RDMA will hold its request until 2550 * TXFIFO is not almost empty. 2551 */ 2552 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2553 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2554 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2555 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2556 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2557 val |= BGE_BMANMODE_LOMBUF_ATTN; 2558 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2559 2560 /* 57XX step 39 */ 2561 /* Poll for buffer manager start indication */ 2562 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2563 DELAY(10); 2564 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2565 break; 2566 } 2567 2568 if (i == BGE_TIMEOUT * 2) { 2569 aprint_error_dev(sc->bge_dev, 2570 "buffer manager failed to start\n"); 2571 return ENXIO; 2572 } 2573 2574 /* 57XX step 40 */ 2575 /* Enable flow-through queues */ 2576 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2577 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2578 2579 /* Wait until queue initialization is complete */ 2580 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2581 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2582 break; 2583 DELAY(10); 2584 } 2585 2586 if (i == BGE_TIMEOUT * 2) { 2587 aprint_error_dev(sc->bge_dev, 2588 "flow-through queue init failed\n"); 2589 return ENXIO; 2590 } 2591 2592 /* 2593 * Summary of rings supported by the controller: 2594 * 2595 * Standard Receive Producer Ring 2596 * - This ring is used to feed receive buffers for "standard" 2597 * sized frames (typically 1536 bytes) to the controller. 2598 * 2599 * Jumbo Receive Producer Ring 2600 * - This ring is used to feed receive buffers for jumbo sized 2601 * frames (i.e. anything bigger than the "standard" frames) 2602 * to the controller. 2603 * 2604 * Mini Receive Producer Ring 2605 * - This ring is used to feed receive buffers for "mini" 2606 * sized frames to the controller. 2607 * - This feature required external memory for the controller 2608 * but was never used in a production system. Should always 2609 * be disabled. 2610 * 2611 * Receive Return Ring 2612 * - After the controller has placed an incoming frame into a 2613 * receive buffer that buffer is moved into a receive return 2614 * ring. The driver is then responsible to passing the 2615 * buffer up to the stack. Many versions of the controller 2616 * support multiple RR rings. 2617 * 2618 * Send Ring 2619 * - This ring is used for outgoing frames. Many versions of 2620 * the controller support multiple send rings. 2621 */ 2622 2623 /* 5718 step 15, 57XX step 41 */ 2624 /* Initialize the standard RX ring control block */ 2625 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2626 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2627 /* 5718 step 16 */ 2628 if (BGE_IS_5717_PLUS(sc)) { 2629 /* 2630 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2631 * Bits 15-2 : Maximum RX frame size 2632 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2633 * Bit 0 : Reserved 2634 */ 2635 rcb->bge_maxlen_flags = 2636 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2637 } else if (BGE_IS_5705_PLUS(sc)) { 2638 /* 2639 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2640 * Bits 15-2 : Reserved (should be 0) 2641 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2642 * Bit 0 : Reserved 2643 */ 2644 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2645 } else { 2646 /* 2647 * Ring size is always XXX entries 2648 * Bits 31-16: Maximum RX frame size 2649 * Bits 15-2 : Reserved (should be 0) 2650 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2651 * Bit 0 : Reserved 2652 */ 2653 rcb->bge_maxlen_flags = 2654 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2655 } 2656 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2657 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2658 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2659 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2660 else 2661 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2662 /* Write the standard receive producer ring control block. */ 2663 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2664 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2665 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2666 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2667 2668 /* Reset the standard receive producer ring producer index. */ 2669 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2670 2671 /* 57XX step 42 */ 2672 /* 2673 * Initialize the jumbo RX ring control block 2674 * We set the 'ring disabled' bit in the flags 2675 * field until we're actually ready to start 2676 * using this ring (i.e. once we set the MTU 2677 * high enough to require it). 2678 */ 2679 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2680 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2681 BGE_HOSTADDR(rcb->bge_hostaddr, 2682 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2683 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2684 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2685 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2686 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2687 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2688 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2689 else 2690 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2691 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2692 rcb->bge_hostaddr.bge_addr_hi); 2693 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2694 rcb->bge_hostaddr.bge_addr_lo); 2695 /* Program the jumbo receive producer ring RCB parameters. */ 2696 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2697 rcb->bge_maxlen_flags); 2698 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2699 /* Reset the jumbo receive producer ring producer index. */ 2700 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2701 } 2702 2703 /* 57XX step 43 */ 2704 /* Disable the mini receive producer ring RCB. */ 2705 if (BGE_IS_5700_FAMILY(sc)) { 2706 /* Set up dummy disabled mini ring RCB */ 2707 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2708 rcb->bge_maxlen_flags = 2709 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2710 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2711 rcb->bge_maxlen_flags); 2712 /* Reset the mini receive producer ring producer index. */ 2713 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2714 2715 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2716 offsetof(struct bge_ring_data, bge_info), 2717 sizeof (struct bge_gib), 2718 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2719 } 2720 2721 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2722 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2723 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2724 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2725 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2726 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2727 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2728 } 2729 /* 5718 step 14, 57XX step 44 */ 2730 /* 2731 * The BD ring replenish thresholds control how often the 2732 * hardware fetches new BD's from the producer rings in host 2733 * memory. Setting the value too low on a busy system can 2734 * starve the hardware and recue the throughpout. 2735 * 2736 * Set the BD ring replenish thresholds. The recommended 2737 * values are 1/8th the number of descriptors allocated to 2738 * each ring, but since we try to avoid filling the entire 2739 * ring we set these to the minimal value of 8. This needs to 2740 * be done on several of the supported chip revisions anyway, 2741 * to work around HW bugs. 2742 */ 2743 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2744 if (BGE_IS_JUMBO_CAPABLE(sc)) 2745 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2746 2747 /* 5718 step 18 */ 2748 if (BGE_IS_5717_PLUS(sc)) { 2749 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2750 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2751 } 2752 2753 /* 57XX step 45 */ 2754 /* 2755 * Disable all send rings by setting the 'ring disabled' bit 2756 * in the flags field of all the TX send ring control blocks, 2757 * located in NIC memory. 2758 */ 2759 if (BGE_IS_5700_FAMILY(sc)) { 2760 /* 5700 to 5704 had 16 send rings. */ 2761 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2762 } else 2763 limit = 1; 2764 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2765 for (i = 0; i < limit; i++) { 2766 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2767 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2768 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2769 rcb_addr += sizeof(struct bge_rcb); 2770 } 2771 2772 /* 57XX step 46 and 47 */ 2773 /* Configure send ring RCB 0 (we use only the first ring) */ 2774 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2775 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2776 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2777 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2778 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2779 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2780 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2781 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2782 else 2783 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2784 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2785 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2786 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2787 2788 /* 57XX step 48 */ 2789 /* 2790 * Disable all receive return rings by setting the 2791 * 'ring diabled' bit in the flags field of all the receive 2792 * return ring control blocks, located in NIC memory. 2793 */ 2794 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2795 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2796 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2797 /* Should be 17, use 16 until we get an SRAM map. */ 2798 limit = 16; 2799 } else if (BGE_IS_5700_FAMILY(sc)) 2800 limit = BGE_RX_RINGS_MAX; 2801 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2802 BGE_IS_57765_PLUS(sc)) 2803 limit = 4; 2804 else 2805 limit = 1; 2806 /* Disable all receive return rings */ 2807 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2808 for (i = 0; i < limit; i++) { 2809 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2810 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2811 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2812 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2813 BGE_RCB_FLAG_RING_DISABLED)); 2814 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2815 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2816 (i * (sizeof(uint64_t))), 0); 2817 rcb_addr += sizeof(struct bge_rcb); 2818 } 2819 2820 /* 57XX step 49 */ 2821 /* 2822 * Set up receive return ring 0. Note that the NIC address 2823 * for RX return rings is 0x0. The return rings live entirely 2824 * within the host, so the nicaddr field in the RCB isn't used. 2825 */ 2826 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2827 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2828 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2829 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2830 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2831 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2832 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2833 2834 /* 5718 step 24, 57XX step 53 */ 2835 /* Set random backoff seed for TX */ 2836 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2837 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2838 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2839 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2840 BGE_TX_BACKOFF_SEED_MASK); 2841 2842 /* 5718 step 26, 57XX step 55 */ 2843 /* Set inter-packet gap */ 2844 val = 0x2620; 2845 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2846 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2847 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2848 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2849 2850 /* 5718 step 27, 57XX step 56 */ 2851 /* 2852 * Specify which ring to use for packets that don't match 2853 * any RX rules. 2854 */ 2855 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2856 2857 /* 5718 step 28, 57XX step 57 */ 2858 /* 2859 * Configure number of RX lists. One interrupt distribution 2860 * list, sixteen active lists, one bad frames class. 2861 */ 2862 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2863 2864 /* 5718 step 29, 57XX step 58 */ 2865 /* Inialize RX list placement stats mask. */ 2866 if (BGE_IS_575X_PLUS(sc)) { 2867 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2868 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2869 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2870 } else 2871 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2872 2873 /* 5718 step 30, 57XX step 59 */ 2874 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2875 2876 /* 5718 step 33, 57XX step 62 */ 2877 /* Disable host coalescing until we get it set up */ 2878 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2879 2880 /* 5718 step 34, 57XX step 63 */ 2881 /* Poll to make sure it's shut down. */ 2882 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2883 DELAY(10); 2884 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2885 break; 2886 } 2887 2888 if (i == BGE_TIMEOUT * 2) { 2889 aprint_error_dev(sc->bge_dev, 2890 "host coalescing engine failed to idle\n"); 2891 return ENXIO; 2892 } 2893 2894 /* 5718 step 35, 36, 37 */ 2895 /* Set up host coalescing defaults */ 2896 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2897 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2898 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2899 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2900 if (!(BGE_IS_5705_PLUS(sc))) { 2901 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2902 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2903 } 2904 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2905 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2906 2907 /* Set up address of statistics block */ 2908 if (BGE_IS_5700_FAMILY(sc)) { 2909 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2910 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2911 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2912 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2913 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2914 } 2915 2916 /* 5718 step 38 */ 2917 /* Set up address of status block */ 2918 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2919 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2920 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2921 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2922 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2923 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2924 2925 /* Set up status block size. */ 2926 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2927 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2928 val = BGE_STATBLKSZ_FULL; 2929 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2930 } else { 2931 val = BGE_STATBLKSZ_32BYTE; 2932 bzero(&sc->bge_rdata->bge_status_block, 32); 2933 } 2934 2935 /* 5718 step 39, 57XX step 73 */ 2936 /* Turn on host coalescing state machine */ 2937 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2938 2939 /* 5718 step 40, 57XX step 74 */ 2940 /* Turn on RX BD completion state machine and enable attentions */ 2941 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2942 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2943 2944 /* 5718 step 41, 57XX step 75 */ 2945 /* Turn on RX list placement state machine */ 2946 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2947 2948 /* 57XX step 76 */ 2949 /* Turn on RX list selector state machine. */ 2950 if (!(BGE_IS_5705_PLUS(sc))) 2951 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2952 2953 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2954 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2955 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2956 BGE_MACMODE_FRMHDR_DMA_ENB; 2957 2958 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2959 val |= BGE_PORTMODE_TBI; 2960 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2961 val |= BGE_PORTMODE_GMII; 2962 else 2963 val |= BGE_PORTMODE_MII; 2964 2965 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2966 /* Allow APE to send/receive frames. */ 2967 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2968 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2969 2970 /* Turn on DMA, clear stats */ 2971 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2972 /* 5718 step 44 */ 2973 DELAY(40); 2974 2975 /* 5718 step 45, 57XX step 79 */ 2976 /* Set misc. local control, enable interrupts on attentions */ 2977 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2978 if (BGE_IS_5717_PLUS(sc)) { 2979 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2980 /* 5718 step 46 */ 2981 DELAY(100); 2982 } 2983 2984 /* 57XX step 81 */ 2985 /* Turn on DMA completion state machine */ 2986 if (!(BGE_IS_5705_PLUS(sc))) 2987 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2988 2989 /* 5718 step 47, 57XX step 82 */ 2990 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2991 2992 /* 5718 step 48 */ 2993 /* Enable host coalescing bug fix. */ 2994 if (BGE_IS_5755_PLUS(sc)) 2995 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2996 2997 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2998 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2999 3000 /* Turn on write DMA state machine */ 3001 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3002 /* 5718 step 49 */ 3003 DELAY(40); 3004 3005 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3006 3007 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3008 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3009 3010 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3011 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3012 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3013 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3014 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3015 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3016 3017 if (sc->bge_flags & BGE_PCIE) 3018 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3019 if (sc->bge_flags & BGE_TSO) 3020 val |= BGE_RDMAMODE_TSO4_ENABLE; 3021 3022 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3023 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3024 BGE_RDMAMODE_H2BNC_VLAN_DET; 3025 /* 3026 * Allow multiple outstanding read requests from 3027 * non-LSO read DMA engine. 3028 */ 3029 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3030 } 3031 3032 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3033 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3034 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3035 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3036 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 3037 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3038 /* 3039 * Adjust tx margin to prevent TX data corruption and 3040 * fix internal FIFO overflow. 3041 */ 3042 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3043 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3044 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3045 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3046 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3047 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3048 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3049 } 3050 /* 3051 * Enable fix for read DMA FIFO overruns. 3052 * The fix is to limit the number of RX BDs 3053 * the hardware would fetch at a fime. 3054 */ 3055 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3056 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3057 } 3058 3059 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3060 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3061 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3062 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3063 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3064 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3065 /* 3066 * Allow 4KB burst length reads for non-LSO frames. 3067 * Enable 512B burst length reads for buffer descriptors. 3068 */ 3069 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3070 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3071 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3072 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3073 } 3074 3075 /* Turn on read DMA state machine */ 3076 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3077 /* 5718 step 52 */ 3078 delay(40); 3079 3080 /* 5718 step 56, 57XX step 84 */ 3081 /* Turn on RX data completion state machine */ 3082 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3083 3084 /* Turn on RX data and RX BD initiator state machine */ 3085 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3086 3087 /* 57XX step 85 */ 3088 /* Turn on Mbuf cluster free state machine */ 3089 if (!BGE_IS_5705_PLUS(sc)) 3090 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3091 3092 /* 5718 step 57, 57XX step 86 */ 3093 /* Turn on send data completion state machine */ 3094 val = BGE_SDCMODE_ENABLE; 3095 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3096 val |= BGE_SDCMODE_CDELAY; 3097 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3098 3099 /* 5718 step 58 */ 3100 /* Turn on send BD completion state machine */ 3101 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3102 3103 /* 57XX step 88 */ 3104 /* Turn on RX BD initiator state machine */ 3105 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3106 3107 /* 5718 step 60, 57XX step 90 */ 3108 /* Turn on send data initiator state machine */ 3109 if (sc->bge_flags & BGE_TSO) { 3110 /* XXX: magic value from Linux driver */ 3111 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3112 BGE_SDIMODE_HW_LSO_PRE_DMA); 3113 } else 3114 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3115 3116 /* 5718 step 61, 57XX step 91 */ 3117 /* Turn on send BD initiator state machine */ 3118 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3119 3120 /* 5718 step 62, 57XX step 92 */ 3121 /* Turn on send BD selector state machine */ 3122 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3123 3124 /* 5718 step 31, 57XX step 60 */ 3125 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3126 /* 5718 step 32, 57XX step 61 */ 3127 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3128 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3129 3130 /* ack/clear link change events */ 3131 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3132 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3133 BGE_MACSTAT_LINK_CHANGED); 3134 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3135 3136 /* 3137 * Enable attention when the link has changed state for 3138 * devices that use auto polling. 3139 */ 3140 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3141 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3142 } else { 3143 /* 5718 step 68 */ 3144 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3145 /* 5718 step 69 (optionally) */ 3146 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3148 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3149 BGE_EVTENB_MI_INTERRUPT); 3150 } 3151 3152 /* 3153 * Clear any pending link state attention. 3154 * Otherwise some link state change events may be lost until attention 3155 * is cleared by bge_intr() -> bge_link_upd() sequence. 3156 * It's not necessary on newer BCM chips - perhaps enabling link 3157 * state change attentions implies clearing pending attention. 3158 */ 3159 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3160 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3161 BGE_MACSTAT_LINK_CHANGED); 3162 3163 /* Enable link state change attentions. */ 3164 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3165 3166 return 0; 3167 } 3168 3169 static const struct bge_revision * 3170 bge_lookup_rev(uint32_t chipid) 3171 { 3172 const struct bge_revision *br; 3173 3174 for (br = bge_revisions; br->br_name != NULL; br++) { 3175 if (br->br_chipid == chipid) 3176 return br; 3177 } 3178 3179 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3180 if (br->br_chipid == BGE_ASICREV(chipid)) 3181 return br; 3182 } 3183 3184 return NULL; 3185 } 3186 3187 static const struct bge_product * 3188 bge_lookup(const struct pci_attach_args *pa) 3189 { 3190 const struct bge_product *bp; 3191 3192 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3193 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3194 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3195 return bp; 3196 } 3197 3198 return NULL; 3199 } 3200 3201 static uint32_t 3202 bge_chipid(const struct pci_attach_args *pa) 3203 { 3204 uint32_t id; 3205 3206 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3207 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3208 3209 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3210 switch (PCI_PRODUCT(pa->pa_id)) { 3211 case PCI_PRODUCT_BROADCOM_BCM5717: 3212 case PCI_PRODUCT_BROADCOM_BCM5718: 3213 case PCI_PRODUCT_BROADCOM_BCM5719: 3214 case PCI_PRODUCT_BROADCOM_BCM5720: 3215 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3216 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3217 BGE_PCI_GEN2_PRODID_ASICREV); 3218 break; 3219 case PCI_PRODUCT_BROADCOM_BCM57761: 3220 case PCI_PRODUCT_BROADCOM_BCM57762: 3221 case PCI_PRODUCT_BROADCOM_BCM57765: 3222 case PCI_PRODUCT_BROADCOM_BCM57766: 3223 case PCI_PRODUCT_BROADCOM_BCM57781: 3224 case PCI_PRODUCT_BROADCOM_BCM57785: 3225 case PCI_PRODUCT_BROADCOM_BCM57791: 3226 case PCI_PRODUCT_BROADCOM_BCM57795: 3227 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3228 BGE_PCI_GEN15_PRODID_ASICREV); 3229 break; 3230 default: 3231 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3232 BGE_PCI_PRODID_ASICREV); 3233 break; 3234 } 3235 } 3236 3237 return id; 3238 } 3239 3240 /* 3241 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3242 * against our list and return its name if we find a match. Note 3243 * that since the Broadcom controller contains VPD support, we 3244 * can get the device name string from the controller itself instead 3245 * of the compiled-in string. This is a little slow, but it guarantees 3246 * we'll always announce the right product name. 3247 */ 3248 static int 3249 bge_probe(device_t parent, cfdata_t match, void *aux) 3250 { 3251 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3252 3253 if (bge_lookup(pa) != NULL) 3254 return 1; 3255 3256 return 0; 3257 } 3258 3259 static void 3260 bge_attach(device_t parent, device_t self, void *aux) 3261 { 3262 struct bge_softc *sc = device_private(self); 3263 struct pci_attach_args *pa = aux; 3264 prop_dictionary_t dict; 3265 const struct bge_product *bp; 3266 const struct bge_revision *br; 3267 pci_chipset_tag_t pc; 3268 pci_intr_handle_t ih; 3269 const char *intrstr = NULL; 3270 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4; 3271 uint32_t command; 3272 struct ifnet *ifp; 3273 uint32_t misccfg, mimode; 3274 void * kva; 3275 u_char eaddr[ETHER_ADDR_LEN]; 3276 pcireg_t memtype, subid, reg; 3277 bus_addr_t memaddr; 3278 uint32_t pm_ctl; 3279 bool no_seeprom; 3280 int capmask; 3281 3282 bp = bge_lookup(pa); 3283 KASSERT(bp != NULL); 3284 3285 sc->sc_pc = pa->pa_pc; 3286 sc->sc_pcitag = pa->pa_tag; 3287 sc->bge_dev = self; 3288 3289 sc->bge_pa = *pa; 3290 pc = sc->sc_pc; 3291 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3292 3293 aprint_naive(": Ethernet controller\n"); 3294 aprint_normal(": %s\n", bp->bp_name); 3295 3296 /* 3297 * Map control/status registers. 3298 */ 3299 DPRINTFN(5, ("Map control/status regs\n")); 3300 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3301 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3302 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3303 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3304 3305 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3306 aprint_error_dev(sc->bge_dev, 3307 "failed to enable memory mapping!\n"); 3308 return; 3309 } 3310 3311 DPRINTFN(5, ("pci_mem_find\n")); 3312 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3313 switch (memtype) { 3314 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3315 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3316 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3317 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3318 &memaddr, &sc->bge_bsize) == 0) 3319 break; 3320 default: 3321 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3322 return; 3323 } 3324 3325 DPRINTFN(5, ("pci_intr_map\n")); 3326 if (pci_intr_map(pa, &ih)) { 3327 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3328 return; 3329 } 3330 3331 DPRINTFN(5, ("pci_intr_string\n")); 3332 intrstr = pci_intr_string(pc, ih); 3333 3334 DPRINTFN(5, ("pci_intr_establish\n")); 3335 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3336 3337 if (sc->bge_intrhand == NULL) { 3338 aprint_error_dev(sc->bge_dev, 3339 "couldn't establish interrupt%s%s\n", 3340 intrstr ? " at " : "", intrstr ? intrstr : ""); 3341 return; 3342 } 3343 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3344 3345 /* Save various chip information. */ 3346 sc->bge_chipid = bge_chipid(pa); 3347 sc->bge_phy_addr = bge_phy_addr(sc); 3348 3349 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3350 &sc->bge_pciecap, NULL) != 0) 3351 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3352 /* PCIe */ 3353 sc->bge_flags |= BGE_PCIE; 3354 /* Extract supported maximum payload size. */ 3355 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3356 sc->bge_pciecap + PCIE_DCAP); 3357 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3358 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3359 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3360 sc->bge_expmrq = 2048; 3361 else 3362 sc->bge_expmrq = 4096; 3363 bge_set_max_readrq(sc); 3364 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3365 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3366 /* PCI-X */ 3367 sc->bge_flags |= BGE_PCIX; 3368 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3369 &sc->bge_pcixcap, NULL) == 0) 3370 aprint_error_dev(sc->bge_dev, 3371 "unable to find PCIX capability\n"); 3372 } 3373 3374 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3375 /* 3376 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3377 * can clobber the chip's PCI config-space power control 3378 * registers, leaving the card in D3 powersave state. We do 3379 * not have memory-mapped registers in this state, so force 3380 * device into D0 state before starting initialization. 3381 */ 3382 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3383 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3384 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3385 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3386 DELAY(1000); /* 27 usec is allegedly sufficent */ 3387 } 3388 3389 /* Save chipset family. */ 3390 switch (BGE_ASICREV(sc->bge_chipid)) { 3391 case BGE_ASICREV_BCM57765: 3392 case BGE_ASICREV_BCM57766: 3393 sc->bge_flags |= BGE_57765_PLUS; 3394 /* FALLTHROUGH */ 3395 case BGE_ASICREV_BCM5717: 3396 case BGE_ASICREV_BCM5719: 3397 case BGE_ASICREV_BCM5720: 3398 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | 3399 BGE_575X_PLUS | BGE_5705_PLUS | BGE_JUMBO_CAPABLE; 3400 /* Jumbo frame on BCM5719 A0 does not work. */ 3401 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3402 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3403 sc->bge_flags |= ~BGE_JUMBO_CAPABLE; 3404 break; 3405 case BGE_ASICREV_BCM5755: 3406 case BGE_ASICREV_BCM5761: 3407 case BGE_ASICREV_BCM5784: 3408 case BGE_ASICREV_BCM5785: 3409 case BGE_ASICREV_BCM5787: 3410 case BGE_ASICREV_BCM57780: 3411 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3412 break; 3413 case BGE_ASICREV_BCM5700: 3414 case BGE_ASICREV_BCM5701: 3415 case BGE_ASICREV_BCM5703: 3416 case BGE_ASICREV_BCM5704: 3417 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3418 break; 3419 case BGE_ASICREV_BCM5714_A0: 3420 case BGE_ASICREV_BCM5780: 3421 case BGE_ASICREV_BCM5714: 3422 sc->bge_flags |= BGE_5714_FAMILY | BGE_JUMBO_CAPABLE; 3423 /* FALLTHROUGH */ 3424 case BGE_ASICREV_BCM5750: 3425 case BGE_ASICREV_BCM5752: 3426 case BGE_ASICREV_BCM5906: 3427 sc->bge_flags |= BGE_575X_PLUS; 3428 /* FALLTHROUGH */ 3429 case BGE_ASICREV_BCM5705: 3430 sc->bge_flags |= BGE_5705_PLUS; 3431 break; 3432 } 3433 3434 /* Identify chips with APE processor. */ 3435 switch (BGE_ASICREV(sc->bge_chipid)) { 3436 case BGE_ASICREV_BCM5717: 3437 case BGE_ASICREV_BCM5719: 3438 case BGE_ASICREV_BCM5720: 3439 case BGE_ASICREV_BCM5761: 3440 sc->bge_flags |= BGE_APE; 3441 break; 3442 } 3443 3444 /* Chips with APE need BAR2 access for APE registers/memory. */ 3445 if ((sc->bge_flags & BGE_APE) != 0) { 3446 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3447 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3448 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3449 &sc->bge_apesize)) { 3450 aprint_error_dev(sc->bge_dev, 3451 "couldn't map BAR2 memory\n"); 3452 return; 3453 } 3454 3455 /* Enable APE register/memory access by host driver. */ 3456 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3457 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3458 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3459 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3460 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3461 3462 bge_ape_lock_init(sc); 3463 bge_ape_read_fw_ver(sc); 3464 } 3465 3466 /* Identify the chips that use an CPMU. */ 3467 if (BGE_IS_5717_PLUS(sc) || 3468 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3469 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3470 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3471 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3472 sc->bge_flags |= BGE_CPMU_PRESENT; 3473 3474 /* Set MI_MODE */ 3475 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3476 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3477 mimode |= BGE_MIMODE_500KHZ_CONST; 3478 else 3479 mimode |= BGE_MIMODE_BASE; 3480 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3481 3482 /* 3483 * When using the BCM5701 in PCI-X mode, data corruption has 3484 * been observed in the first few bytes of some received packets. 3485 * Aligning the packet buffer in memory eliminates the corruption. 3486 * Unfortunately, this misaligns the packet payloads. On platforms 3487 * which do not support unaligned accesses, we will realign the 3488 * payloads by copying the received packets. 3489 */ 3490 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3491 sc->bge_flags & BGE_PCIX) 3492 sc->bge_flags |= BGE_RX_ALIGNBUG; 3493 3494 if (BGE_IS_5700_FAMILY(sc)) 3495 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3496 3497 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3498 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3499 3500 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3501 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3502 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3503 sc->bge_flags |= BGE_IS_5788; 3504 3505 /* 3506 * Some controllers seem to require a special firmware to use 3507 * TSO. But the firmware is not available to FreeBSD and Linux 3508 * claims that the TSO performed by the firmware is slower than 3509 * hardware based TSO. Moreover the firmware based TSO has one 3510 * known bug which can't handle TSO if ethernet header + IP/TCP 3511 * header is greater than 80 bytes. The workaround for the TSO 3512 * bug exist but it seems it's too expensive than not using 3513 * TSO at all. Some hardwares also have the TSO bug so limit 3514 * the TSO to the controllers that are not affected TSO issues 3515 * (e.g. 5755 or higher). 3516 */ 3517 if (BGE_IS_5755_PLUS(sc)) { 3518 /* 3519 * BCM5754 and BCM5787 shares the same ASIC id so 3520 * explicit device id check is required. 3521 */ 3522 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3523 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3524 sc->bge_flags |= BGE_TSO; 3525 } 3526 3527 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3528 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3529 (misccfg == 0x4000 || misccfg == 0x8000)) || 3530 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3531 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3532 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3533 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3534 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3535 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3536 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3537 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3538 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3539 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3540 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3541 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3542 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3543 capmask &= ~BMSR_EXTSTAT; 3544 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3545 } 3546 3547 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3548 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3549 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3550 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3551 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3552 3553 /* Set various PHY bug flags. */ 3554 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3555 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3556 sc->bge_flags |= BGE_PHY_CRC_BUG; 3557 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3558 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3559 sc->bge_flags |= BGE_PHY_ADC_BUG; 3560 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3561 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3562 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3563 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3564 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3565 sc->bge_flags |= BGE_PHY_NO_3LED; 3566 if (BGE_IS_5705_PLUS(sc) && 3567 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3568 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3569 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3570 !BGE_IS_5717_PLUS(sc)) { 3571 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3572 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3573 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3574 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3575 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3576 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3577 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3578 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3579 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3580 } else 3581 sc->bge_flags |= BGE_PHY_BER_BUG; 3582 } 3583 3584 /* 3585 * SEEPROM check. 3586 * First check if firmware knows we do not have SEEPROM. 3587 */ 3588 if (prop_dictionary_get_bool(device_properties(self), 3589 "without-seeprom", &no_seeprom) && no_seeprom) 3590 sc->bge_flags |= BGE_NO_EEPROM; 3591 3592 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3593 sc->bge_flags |= BGE_NO_EEPROM; 3594 3595 /* Now check the 'ROM failed' bit on the RX CPU */ 3596 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3597 sc->bge_flags |= BGE_NO_EEPROM; 3598 3599 sc->bge_asf_mode = 0; 3600 /* No ASF if APE present. */ 3601 if ((sc->bge_flags & BGE_APE) == 0) { 3602 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3603 BGE_SRAM_DATA_SIG_MAGIC)) { 3604 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3605 BGE_HWCFG_ASF) { 3606 sc->bge_asf_mode |= ASF_ENABLE; 3607 sc->bge_asf_mode |= ASF_STACKUP; 3608 if (BGE_IS_575X_PLUS(sc)) 3609 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3610 } 3611 } 3612 } 3613 3614 /* 3615 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3616 * lock in bge_reset(). 3617 */ 3618 CSR_WRITE_4(sc, BGE_EE_ADDR, 3619 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3620 delay(1000); 3621 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3622 3623 bge_stop_fw(sc); 3624 bge_sig_pre_reset(sc, BGE_RESET_START); 3625 if (bge_reset(sc)) 3626 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3627 3628 /* 3629 * Read the hardware config word in the first 32k of NIC internal 3630 * memory, or fall back to the config word in the EEPROM. 3631 * Note: on some BCM5700 cards, this value appears to be unset. 3632 */ 3633 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = 0; 3634 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3635 BGE_SRAM_DATA_SIG_MAGIC) { 3636 uint32_t tmp; 3637 3638 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3639 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3640 BGE_SRAM_DATA_VER_SHIFT; 3641 if ((0 < tmp) && (tmp < 0x100)) 3642 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3643 if (sc->bge_flags & BGE_PCIE) 3644 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3645 if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) 3646 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3647 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3648 bge_read_eeprom(sc, (void *)&hwcfg, 3649 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3650 hwcfg = be32toh(hwcfg); 3651 } 3652 aprint_normal_dev(sc->bge_dev, "HW config %08x, %08x, %08x, %08x\n", 3653 hwcfg, hwcfg2, hwcfg3, hwcfg4); 3654 3655 bge_sig_legacy(sc, BGE_RESET_START); 3656 bge_sig_post_reset(sc, BGE_RESET_START); 3657 3658 if (bge_chipinit(sc)) { 3659 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3660 bge_release_resources(sc); 3661 return; 3662 } 3663 3664 /* 3665 * Get station address from the EEPROM. 3666 */ 3667 if (bge_get_eaddr(sc, eaddr)) { 3668 aprint_error_dev(sc->bge_dev, 3669 "failed to read station address\n"); 3670 bge_release_resources(sc); 3671 return; 3672 } 3673 3674 br = bge_lookup_rev(sc->bge_chipid); 3675 3676 if (br == NULL) { 3677 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3678 sc->bge_chipid); 3679 } else { 3680 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3681 br->br_name, sc->bge_chipid); 3682 } 3683 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3684 3685 /* Allocate the general information block and ring buffers. */ 3686 if (pci_dma64_available(pa)) 3687 sc->bge_dmatag = pa->pa_dmat64; 3688 else 3689 sc->bge_dmatag = pa->pa_dmat; 3690 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3691 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3692 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3693 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3694 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3695 return; 3696 } 3697 DPRINTFN(5, ("bus_dmamem_map\n")); 3698 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3699 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3700 BUS_DMA_NOWAIT)) { 3701 aprint_error_dev(sc->bge_dev, 3702 "can't map DMA buffers (%zu bytes)\n", 3703 sizeof(struct bge_ring_data)); 3704 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3705 sc->bge_ring_rseg); 3706 return; 3707 } 3708 DPRINTFN(5, ("bus_dmamem_create\n")); 3709 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3710 sizeof(struct bge_ring_data), 0, 3711 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3712 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3713 bus_dmamem_unmap(sc->bge_dmatag, kva, 3714 sizeof(struct bge_ring_data)); 3715 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3716 sc->bge_ring_rseg); 3717 return; 3718 } 3719 DPRINTFN(5, ("bus_dmamem_load\n")); 3720 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3721 sizeof(struct bge_ring_data), NULL, 3722 BUS_DMA_NOWAIT)) { 3723 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3724 bus_dmamem_unmap(sc->bge_dmatag, kva, 3725 sizeof(struct bge_ring_data)); 3726 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3727 sc->bge_ring_rseg); 3728 return; 3729 } 3730 3731 DPRINTFN(5, ("bzero\n")); 3732 sc->bge_rdata = (struct bge_ring_data *)kva; 3733 3734 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3735 3736 /* Try to allocate memory for jumbo buffers. */ 3737 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3738 if (bge_alloc_jumbo_mem(sc)) { 3739 aprint_error_dev(sc->bge_dev, 3740 "jumbo buffer allocation failed\n"); 3741 } else 3742 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3743 } 3744 3745 /* Set default tuneable values. */ 3746 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3747 sc->bge_rx_coal_ticks = 150; 3748 sc->bge_rx_max_coal_bds = 64; 3749 sc->bge_tx_coal_ticks = 300; 3750 sc->bge_tx_max_coal_bds = 400; 3751 if (BGE_IS_5705_PLUS(sc)) { 3752 sc->bge_tx_coal_ticks = (12 * 5); 3753 sc->bge_tx_max_coal_bds = (12 * 5); 3754 aprint_verbose_dev(sc->bge_dev, 3755 "setting short Tx thresholds\n"); 3756 } 3757 3758 if (BGE_IS_5717_PLUS(sc)) 3759 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3760 else if (BGE_IS_5705_PLUS(sc)) 3761 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3762 else 3763 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3764 3765 /* Set up ifnet structure */ 3766 ifp = &sc->ethercom.ec_if; 3767 ifp->if_softc = sc; 3768 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3769 ifp->if_ioctl = bge_ioctl; 3770 ifp->if_stop = bge_stop; 3771 ifp->if_start = bge_start; 3772 ifp->if_init = bge_init; 3773 ifp->if_watchdog = bge_watchdog; 3774 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3775 IFQ_SET_READY(&ifp->if_snd); 3776 DPRINTFN(5, ("strcpy if_xname\n")); 3777 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3778 3779 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3780 sc->ethercom.ec_if.if_capabilities |= 3781 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3782 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3783 sc->ethercom.ec_if.if_capabilities |= 3784 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3785 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3786 #endif 3787 sc->ethercom.ec_capabilities |= 3788 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3789 3790 if (sc->bge_flags & BGE_TSO) 3791 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3792 3793 /* 3794 * Do MII setup. 3795 */ 3796 DPRINTFN(5, ("mii setup\n")); 3797 sc->bge_mii.mii_ifp = ifp; 3798 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3799 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3800 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3801 3802 /* 3803 * Figure out what sort of media we have by checking the hardware 3804 * config word. Note: on some BCM5700 cards, this value appears to be 3805 * unset. If that's the case, we have to rely on identifying the NIC 3806 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3807 * The SysKonnect SK-9D41 is a 1000baseSX card. 3808 */ 3809 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3810 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3811 if (BGE_IS_5714_FAMILY(sc)) 3812 sc->bge_flags |= BGE_PHY_FIBER_MII; 3813 else 3814 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3815 } 3816 3817 /* set phyflags and chipid before mii_attach() */ 3818 dict = device_properties(self); 3819 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3820 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3821 3822 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3823 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3824 bge_ifmedia_sts); 3825 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3826 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3827 0, NULL); 3828 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3829 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3830 /* Pretend the user requested this setting */ 3831 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3832 } else { 3833 /* 3834 * Do transceiver setup and tell the firmware the 3835 * driver is down so we can try to get access the 3836 * probe if ASF is running. Retry a couple of times 3837 * if we get a conflict with the ASF firmware accessing 3838 * the PHY. 3839 */ 3840 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3841 bge_asf_driver_up(sc); 3842 3843 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3844 bge_ifmedia_sts); 3845 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3846 sc->bge_phy_addr, MII_OFFSET_ANY, 3847 MIIF_DOPAUSE); 3848 3849 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3850 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3851 ifmedia_add(&sc->bge_mii.mii_media, 3852 IFM_ETHER|IFM_MANUAL, 0, NULL); 3853 ifmedia_set(&sc->bge_mii.mii_media, 3854 IFM_ETHER|IFM_MANUAL); 3855 } else 3856 ifmedia_set(&sc->bge_mii.mii_media, 3857 IFM_ETHER|IFM_AUTO); 3858 3859 /* 3860 * Now tell the firmware we are going up after probing the PHY 3861 */ 3862 if (sc->bge_asf_mode & ASF_STACKUP) 3863 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3864 } 3865 3866 /* 3867 * Call MI attach routine. 3868 */ 3869 DPRINTFN(5, ("if_attach\n")); 3870 if_attach(ifp); 3871 DPRINTFN(5, ("ether_ifattach\n")); 3872 ether_ifattach(ifp, eaddr); 3873 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3874 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3875 RND_TYPE_NET, 0); 3876 #ifdef BGE_EVENT_COUNTERS 3877 /* 3878 * Attach event counters. 3879 */ 3880 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3881 NULL, device_xname(sc->bge_dev), "intr"); 3882 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3883 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3884 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3885 NULL, device_xname(sc->bge_dev), "tx_xon"); 3886 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3887 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3888 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3889 NULL, device_xname(sc->bge_dev), "rx_xon"); 3890 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3891 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3892 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3893 NULL, device_xname(sc->bge_dev), "xoffentered"); 3894 #endif /* BGE_EVENT_COUNTERS */ 3895 DPRINTFN(5, ("callout_init\n")); 3896 callout_init(&sc->bge_timeout, 0); 3897 3898 if (pmf_device_register(self, NULL, NULL)) 3899 pmf_class_network_register(self, ifp); 3900 else 3901 aprint_error_dev(self, "couldn't establish power handler\n"); 3902 3903 bge_sysctl_init(sc); 3904 3905 #ifdef BGE_DEBUG 3906 bge_debug_info(sc); 3907 #endif 3908 } 3909 3910 /* 3911 * Stop all chip I/O so that the kernel's probe routines don't 3912 * get confused by errant DMAs when rebooting. 3913 */ 3914 static int 3915 bge_detach(device_t self, int flags __unused) 3916 { 3917 struct bge_softc *sc = device_private(self); 3918 struct ifnet *ifp = &sc->ethercom.ec_if; 3919 int s; 3920 3921 s = splnet(); 3922 /* Stop the interface. Callouts are stopped in it. */ 3923 bge_stop(ifp, 1); 3924 splx(s); 3925 3926 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3927 3928 /* Delete all remaining media. */ 3929 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3930 3931 ether_ifdetach(ifp); 3932 if_detach(ifp); 3933 3934 bge_release_resources(sc); 3935 3936 return 0; 3937 } 3938 3939 static void 3940 bge_release_resources(struct bge_softc *sc) 3941 { 3942 3943 /* Disestablish the interrupt handler */ 3944 if (sc->bge_intrhand != NULL) { 3945 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3946 sc->bge_intrhand = NULL; 3947 } 3948 3949 if (sc->bge_dmatag != NULL) { 3950 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3951 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3952 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3953 sizeof(struct bge_ring_data)); 3954 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3955 } 3956 3957 /* Unmap the device registers */ 3958 if (sc->bge_bsize != 0) { 3959 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3960 sc->bge_bsize = 0; 3961 } 3962 3963 /* Unmap the APE registers */ 3964 if (sc->bge_apesize != 0) { 3965 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3966 sc->bge_apesize); 3967 sc->bge_apesize = 0; 3968 } 3969 } 3970 3971 static int 3972 bge_reset(struct bge_softc *sc) 3973 { 3974 uint32_t cachesize, command; 3975 uint32_t reset, mac_mode, mac_mode_mask; 3976 pcireg_t devctl, reg; 3977 int i, val; 3978 void (*write_op)(struct bge_softc *, int, int); 3979 3980 /* Make mask for BGE_MAC_MODE register. */ 3981 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3982 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3983 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3984 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 3985 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3986 3987 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3988 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3989 if (sc->bge_flags & BGE_PCIE) 3990 write_op = bge_writemem_direct; 3991 else 3992 write_op = bge_writemem_ind; 3993 } else 3994 write_op = bge_writereg_ind; 3995 3996 /* 57XX step 4 */ 3997 /* Acquire the NVM lock */ 3998 if ((sc->bge_flags & BGE_NO_EEPROM) == 0 && 3999 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4000 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4001 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4002 for (i = 0; i < 8000; i++) { 4003 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4004 BGE_NVRAMSWARB_GNT1) 4005 break; 4006 DELAY(20); 4007 } 4008 if (i == 8000) { 4009 printf("%s: NVRAM lock timedout!\n", 4010 device_xname(sc->bge_dev)); 4011 } 4012 } 4013 4014 /* Take APE lock when performing reset. */ 4015 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4016 4017 /* 57XX step 3 */ 4018 /* Save some important PCI state. */ 4019 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4020 /* 5718 reset step 3 */ 4021 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4022 4023 /* 5718 reset step 5, 57XX step 5b-5d */ 4024 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4025 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4026 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4027 4028 /* XXX ???: Disable fastboot on controllers that support it. */ 4029 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4030 BGE_IS_5755_PLUS(sc)) 4031 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4032 4033 /* 5718 reset step 2, 57XX step 6 */ 4034 /* 4035 * Write the magic number to SRAM at offset 0xB50. 4036 * When firmware finishes its initialization it will 4037 * write ~BGE_MAGIC_NUMBER to the same location. 4038 */ 4039 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4040 4041 /* 5718 reset step 6, 57XX step 7 */ 4042 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4043 /* 4044 * XXX: from FreeBSD/Linux; no documentation 4045 */ 4046 if (sc->bge_flags & BGE_PCIE) { 4047 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 4048 !BGE_IS_57765_PLUS(sc) && 4049 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4050 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4051 /* PCI Express 1.0 system */ 4052 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4053 BGE_PHY_PCIE_SCRAM_MODE); 4054 } 4055 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4056 /* 4057 * Prevent PCI Express link training 4058 * during global reset. 4059 */ 4060 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4061 reset |= (1 << 29); 4062 } 4063 } 4064 4065 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4066 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4067 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4068 i | BGE_VCPU_STATUS_DRV_RESET); 4069 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4070 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4071 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4072 } 4073 4074 /* 4075 * Set GPHY Power Down Override to leave GPHY 4076 * powered up in D0 uninitialized. 4077 */ 4078 if (BGE_IS_5705_PLUS(sc) && 4079 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4080 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4081 4082 /* Issue global reset */ 4083 write_op(sc, BGE_MISC_CFG, reset); 4084 4085 /* 5718 reset step 7, 57XX step 8 */ 4086 if (sc->bge_flags & BGE_PCIE) 4087 delay(100*1000); /* too big */ 4088 else 4089 delay(1000); 4090 4091 if (sc->bge_flags & BGE_PCIE) { 4092 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4093 DELAY(500000); 4094 /* XXX: Magic Numbers */ 4095 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4096 BGE_PCI_UNKNOWN0); 4097 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4098 BGE_PCI_UNKNOWN0, 4099 reg | (1 << 15)); 4100 } 4101 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4102 sc->bge_pciecap + PCIE_DCSR); 4103 /* Clear enable no snoop and disable relaxed ordering. */ 4104 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4105 PCIE_DCSR_ENA_NO_SNOOP); 4106 4107 /* Set PCIE max payload size to 128 for older PCIe devices */ 4108 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4109 devctl &= ~(0x00e0); 4110 /* Clear device status register. Write 1b to clear */ 4111 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4112 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4113 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4114 sc->bge_pciecap + PCIE_DCSR, devctl); 4115 bge_set_max_readrq(sc); 4116 } 4117 4118 /* From Linux: dummy read to flush PCI posted writes */ 4119 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4120 4121 /* 4122 * Reset some of the PCI state that got zapped by reset 4123 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4124 * set, too. 4125 */ 4126 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4127 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4128 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4129 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4130 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4131 (sc->bge_flags & BGE_PCIX) != 0) 4132 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4133 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4134 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4135 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4136 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4137 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4138 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4139 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4140 4141 /* Step 11: disable PCI-X Relaxed Ordering. */ 4142 if (sc->bge_flags & BGE_PCIX) { 4143 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4144 + PCIX_CMD); 4145 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4146 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4147 } 4148 4149 /* 5718 reset step 10, 57XX step 12 */ 4150 /* Enable memory arbiter. */ 4151 if (BGE_IS_5714_FAMILY(sc)) { 4152 val = CSR_READ_4(sc, BGE_MARB_MODE); 4153 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4154 } else 4155 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4156 4157 /* XXX 5721, 5751 and 5752 */ 4158 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4159 /* Step 19: */ 4160 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4161 /* Step 20: */ 4162 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4163 } 4164 4165 /* 5718 reset step 13, 57XX step 17 */ 4166 /* Poll until the firmware initialization is complete */ 4167 bge_poll_fw(sc); 4168 4169 /* 5718 reset step 12, 57XX step 15 and 16 */ 4170 /* Fix up byte swapping */ 4171 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4172 4173 /* 57XX step 21 */ 4174 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4175 pcireg_t msidata; 4176 4177 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4178 BGE_PCI_MSI_DATA); 4179 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4180 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4181 msidata); 4182 } 4183 4184 /* 57XX step 18 */ 4185 /* Write mac mode. */ 4186 val = CSR_READ_4(sc, BGE_MAC_MODE); 4187 /* Restore mac_mode_mask's bits using mac_mode */ 4188 val = (val & ~mac_mode_mask) | mac_mode; 4189 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4190 DELAY(40); 4191 4192 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4193 4194 /* 4195 * The 5704 in TBI mode apparently needs some special 4196 * adjustment to insure the SERDES drive level is set 4197 * to 1.2V. 4198 */ 4199 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4200 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4201 uint32_t serdescfg; 4202 4203 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4204 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4205 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4206 } 4207 4208 if (sc->bge_flags & BGE_PCIE && 4209 !BGE_IS_57765_PLUS(sc) && 4210 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4211 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4212 uint32_t v; 4213 4214 /* Enable PCI Express bug fix */ 4215 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4216 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4217 v | BGE_TLP_DATA_FIFO_PROTECT); 4218 } 4219 4220 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4221 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4222 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4223 4224 return 0; 4225 } 4226 4227 /* 4228 * Frame reception handling. This is called if there's a frame 4229 * on the receive return list. 4230 * 4231 * Note: we have to be able to handle two possibilities here: 4232 * 1) the frame is from the jumbo receive ring 4233 * 2) the frame is from the standard receive ring 4234 */ 4235 4236 static void 4237 bge_rxeof(struct bge_softc *sc) 4238 { 4239 struct ifnet *ifp; 4240 uint16_t rx_prod, rx_cons; 4241 int stdcnt = 0, jumbocnt = 0; 4242 bus_dmamap_t dmamap; 4243 bus_addr_t offset, toff; 4244 bus_size_t tlen; 4245 int tosync; 4246 4247 rx_cons = sc->bge_rx_saved_considx; 4248 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4249 4250 /* Nothing to do */ 4251 if (rx_cons == rx_prod) 4252 return; 4253 4254 ifp = &sc->ethercom.ec_if; 4255 4256 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4257 offsetof(struct bge_ring_data, bge_status_block), 4258 sizeof (struct bge_status_block), 4259 BUS_DMASYNC_POSTREAD); 4260 4261 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4262 tosync = rx_prod - rx_cons; 4263 4264 if (tosync != 0) 4265 rnd_add_uint32(&sc->rnd_source, tosync); 4266 4267 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4268 4269 if (tosync < 0) { 4270 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4271 sizeof (struct bge_rx_bd); 4272 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4273 toff, tlen, BUS_DMASYNC_POSTREAD); 4274 tosync = -tosync; 4275 } 4276 4277 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4278 offset, tosync * sizeof (struct bge_rx_bd), 4279 BUS_DMASYNC_POSTREAD); 4280 4281 while (rx_cons != rx_prod) { 4282 struct bge_rx_bd *cur_rx; 4283 uint32_t rxidx; 4284 struct mbuf *m = NULL; 4285 4286 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4287 4288 rxidx = cur_rx->bge_idx; 4289 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4290 4291 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4292 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4293 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4294 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4295 jumbocnt++; 4296 bus_dmamap_sync(sc->bge_dmatag, 4297 sc->bge_cdata.bge_rx_jumbo_map, 4298 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4299 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4300 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4301 ifp->if_ierrors++; 4302 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4303 continue; 4304 } 4305 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4306 NULL)== ENOBUFS) { 4307 ifp->if_ierrors++; 4308 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4309 continue; 4310 } 4311 } else { 4312 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4313 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4314 4315 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4316 stdcnt++; 4317 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4318 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4319 if (dmamap == NULL) { 4320 ifp->if_ierrors++; 4321 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4322 continue; 4323 } 4324 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4325 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4326 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4327 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4328 ifp->if_ierrors++; 4329 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4330 continue; 4331 } 4332 if (bge_newbuf_std(sc, sc->bge_std, 4333 NULL, dmamap) == ENOBUFS) { 4334 ifp->if_ierrors++; 4335 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4336 continue; 4337 } 4338 } 4339 4340 ifp->if_ipackets++; 4341 #ifndef __NO_STRICT_ALIGNMENT 4342 /* 4343 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4344 * the Rx buffer has the layer-2 header unaligned. 4345 * If our CPU requires alignment, re-align by copying. 4346 */ 4347 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4348 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4349 cur_rx->bge_len); 4350 m->m_data += ETHER_ALIGN; 4351 } 4352 #endif 4353 4354 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4355 m->m_pkthdr.rcvif = ifp; 4356 4357 /* 4358 * Handle BPF listeners. Let the BPF user see the packet. 4359 */ 4360 bpf_mtap(ifp, m); 4361 4362 bge_rxcsum(sc, cur_rx, m); 4363 4364 /* 4365 * If we received a packet with a vlan tag, pass it 4366 * to vlan_input() instead of ether_input(). 4367 */ 4368 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4369 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4370 } 4371 4372 (*ifp->if_input)(ifp, m); 4373 } 4374 4375 sc->bge_rx_saved_considx = rx_cons; 4376 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4377 if (stdcnt) 4378 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4379 if (jumbocnt) 4380 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4381 } 4382 4383 static void 4384 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4385 { 4386 4387 if (BGE_IS_5717_PLUS(sc)) { 4388 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4389 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4390 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4391 if ((cur_rx->bge_error_flag & 4392 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4393 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4394 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4395 m->m_pkthdr.csum_data = 4396 cur_rx->bge_tcp_udp_csum; 4397 m->m_pkthdr.csum_flags |= 4398 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4399 M_CSUM_DATA); 4400 } 4401 } 4402 } else { 4403 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4404 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4405 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4406 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4407 /* 4408 * Rx transport checksum-offload may also 4409 * have bugs with packets which, when transmitted, 4410 * were `runts' requiring padding. 4411 */ 4412 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4413 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4414 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4415 m->m_pkthdr.csum_data = 4416 cur_rx->bge_tcp_udp_csum; 4417 m->m_pkthdr.csum_flags |= 4418 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4419 M_CSUM_DATA); 4420 } 4421 } 4422 } 4423 4424 static void 4425 bge_txeof(struct bge_softc *sc) 4426 { 4427 struct bge_tx_bd *cur_tx = NULL; 4428 struct ifnet *ifp; 4429 struct txdmamap_pool_entry *dma; 4430 bus_addr_t offset, toff; 4431 bus_size_t tlen; 4432 int tosync; 4433 struct mbuf *m; 4434 4435 ifp = &sc->ethercom.ec_if; 4436 4437 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4438 offsetof(struct bge_ring_data, bge_status_block), 4439 sizeof (struct bge_status_block), 4440 BUS_DMASYNC_POSTREAD); 4441 4442 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4443 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4444 sc->bge_tx_saved_considx; 4445 4446 if (tosync != 0) 4447 rnd_add_uint32(&sc->rnd_source, tosync); 4448 4449 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4450 4451 if (tosync < 0) { 4452 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4453 sizeof (struct bge_tx_bd); 4454 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4455 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4456 tosync = -tosync; 4457 } 4458 4459 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4460 offset, tosync * sizeof (struct bge_tx_bd), 4461 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4462 4463 /* 4464 * Go through our tx ring and free mbufs for those 4465 * frames that have been sent. 4466 */ 4467 while (sc->bge_tx_saved_considx != 4468 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4469 uint32_t idx = 0; 4470 4471 idx = sc->bge_tx_saved_considx; 4472 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4473 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4474 ifp->if_opackets++; 4475 m = sc->bge_cdata.bge_tx_chain[idx]; 4476 if (m != NULL) { 4477 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4478 dma = sc->txdma[idx]; 4479 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4480 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4481 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4482 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4483 sc->txdma[idx] = NULL; 4484 4485 m_freem(m); 4486 } 4487 sc->bge_txcnt--; 4488 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4489 ifp->if_timer = 0; 4490 } 4491 4492 if (cur_tx != NULL) 4493 ifp->if_flags &= ~IFF_OACTIVE; 4494 } 4495 4496 static int 4497 bge_intr(void *xsc) 4498 { 4499 struct bge_softc *sc; 4500 struct ifnet *ifp; 4501 uint32_t statusword; 4502 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4503 4504 sc = xsc; 4505 ifp = &sc->ethercom.ec_if; 4506 4507 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4508 if (BGE_IS_5717_PLUS(sc)) 4509 intrmask = 0; 4510 4511 /* It is possible for the interrupt to arrive before 4512 * the status block is updated prior to the interrupt. 4513 * Reading the PCI State register will confirm whether the 4514 * interrupt is ours and will flush the status block. 4515 */ 4516 4517 /* read status word from status block */ 4518 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4519 offsetof(struct bge_ring_data, bge_status_block), 4520 sizeof (struct bge_status_block), 4521 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4522 statusword = sc->bge_rdata->bge_status_block.bge_status; 4523 4524 if ((statusword & BGE_STATFLAG_UPDATED) || 4525 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) { 4526 /* Ack interrupt and stop others from occuring. */ 4527 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4528 4529 BGE_EVCNT_INCR(sc->bge_ev_intr); 4530 4531 /* clear status word */ 4532 sc->bge_rdata->bge_status_block.bge_status = 0; 4533 4534 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4535 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4536 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4537 bge_link_upd(sc); 4538 4539 if (ifp->if_flags & IFF_RUNNING) { 4540 /* Check RX return ring producer/consumer */ 4541 bge_rxeof(sc); 4542 4543 /* Check TX ring producer/consumer */ 4544 bge_txeof(sc); 4545 } 4546 4547 if (sc->bge_pending_rxintr_change) { 4548 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4549 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4550 uint32_t junk; 4551 4552 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4553 DELAY(10); 4554 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4555 4556 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4557 DELAY(10); 4558 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4559 4560 sc->bge_pending_rxintr_change = 0; 4561 } 4562 bge_handle_events(sc); 4563 4564 /* Re-enable interrupts. */ 4565 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4566 4567 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4568 bge_start(ifp); 4569 4570 return 1; 4571 } else 4572 return 0; 4573 } 4574 4575 static void 4576 bge_asf_driver_up(struct bge_softc *sc) 4577 { 4578 if (sc->bge_asf_mode & ASF_STACKUP) { 4579 /* Send ASF heartbeat aprox. every 2s */ 4580 if (sc->bge_asf_count) 4581 sc->bge_asf_count --; 4582 else { 4583 sc->bge_asf_count = 2; 4584 4585 bge_wait_for_event_ack(sc); 4586 4587 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4588 BGE_FW_CMD_DRV_ALIVE); 4589 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4590 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4591 BGE_FW_HB_TIMEOUT_SEC); 4592 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4593 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4594 BGE_RX_CPU_DRV_EVENT); 4595 } 4596 } 4597 } 4598 4599 static void 4600 bge_tick(void *xsc) 4601 { 4602 struct bge_softc *sc = xsc; 4603 struct mii_data *mii = &sc->bge_mii; 4604 int s; 4605 4606 s = splnet(); 4607 4608 if (BGE_IS_5705_PLUS(sc)) 4609 bge_stats_update_regs(sc); 4610 else 4611 bge_stats_update(sc); 4612 4613 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4614 /* 4615 * Since in TBI mode auto-polling can't be used we should poll 4616 * link status manually. Here we register pending link event 4617 * and trigger interrupt. 4618 */ 4619 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4620 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4621 } else { 4622 /* 4623 * Do not touch PHY if we have link up. This could break 4624 * IPMI/ASF mode or produce extra input errors. 4625 * (extra input errors was reported for bcm5701 & bcm5704). 4626 */ 4627 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4628 mii_tick(mii); 4629 } 4630 4631 bge_asf_driver_up(sc); 4632 4633 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4634 4635 splx(s); 4636 } 4637 4638 static void 4639 bge_stats_update_regs(struct bge_softc *sc) 4640 { 4641 struct ifnet *ifp = &sc->ethercom.ec_if; 4642 4643 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4644 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4645 4646 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4647 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4648 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4649 } 4650 4651 static void 4652 bge_stats_update(struct bge_softc *sc) 4653 { 4654 struct ifnet *ifp = &sc->ethercom.ec_if; 4655 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4656 4657 #define READ_STAT(sc, stats, stat) \ 4658 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4659 4660 ifp->if_collisions += 4661 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4662 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4663 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4664 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4665 ifp->if_collisions; 4666 4667 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4668 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4669 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4670 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4671 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4672 READ_STAT(sc, stats, 4673 xoffPauseFramesReceived.bge_addr_lo)); 4674 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4675 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4676 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4677 READ_STAT(sc, stats, 4678 macControlFramesReceived.bge_addr_lo)); 4679 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4680 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4681 4682 #undef READ_STAT 4683 4684 #ifdef notdef 4685 ifp->if_collisions += 4686 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4687 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4688 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4689 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4690 ifp->if_collisions; 4691 #endif 4692 } 4693 4694 /* 4695 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4696 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4697 * but when such padded frames employ the bge IP/TCP checksum offload, 4698 * the hardware checksum assist gives incorrect results (possibly 4699 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4700 * If we pad such runts with zeros, the onboard checksum comes out correct. 4701 */ 4702 static inline int 4703 bge_cksum_pad(struct mbuf *pkt) 4704 { 4705 struct mbuf *last = NULL; 4706 int padlen; 4707 4708 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4709 4710 /* if there's only the packet-header and we can pad there, use it. */ 4711 if (pkt->m_pkthdr.len == pkt->m_len && 4712 M_TRAILINGSPACE(pkt) >= padlen) { 4713 last = pkt; 4714 } else { 4715 /* 4716 * Walk packet chain to find last mbuf. We will either 4717 * pad there, or append a new mbuf and pad it 4718 * (thus perhaps avoiding the bcm5700 dma-min bug). 4719 */ 4720 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4721 continue; /* do nothing */ 4722 } 4723 4724 /* `last' now points to last in chain. */ 4725 if (M_TRAILINGSPACE(last) < padlen) { 4726 /* Allocate new empty mbuf, pad it. Compact later. */ 4727 struct mbuf *n; 4728 MGET(n, M_DONTWAIT, MT_DATA); 4729 if (n == NULL) 4730 return ENOBUFS; 4731 n->m_len = 0; 4732 last->m_next = n; 4733 last = n; 4734 } 4735 } 4736 4737 KDASSERT(!M_READONLY(last)); 4738 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4739 4740 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4741 memset(mtod(last, char *) + last->m_len, 0, padlen); 4742 last->m_len += padlen; 4743 pkt->m_pkthdr.len += padlen; 4744 return 0; 4745 } 4746 4747 /* 4748 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4749 */ 4750 static inline int 4751 bge_compact_dma_runt(struct mbuf *pkt) 4752 { 4753 struct mbuf *m, *prev; 4754 int totlen, prevlen; 4755 4756 prev = NULL; 4757 totlen = 0; 4758 prevlen = -1; 4759 4760 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4761 int mlen = m->m_len; 4762 int shortfall = 8 - mlen ; 4763 4764 totlen += mlen; 4765 if (mlen == 0) 4766 continue; 4767 if (mlen >= 8) 4768 continue; 4769 4770 /* If we get here, mbuf data is too small for DMA engine. 4771 * Try to fix by shuffling data to prev or next in chain. 4772 * If that fails, do a compacting deep-copy of the whole chain. 4773 */ 4774 4775 /* Internal frag. If fits in prev, copy it there. */ 4776 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4777 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4778 prev->m_len += mlen; 4779 m->m_len = 0; 4780 /* XXX stitch chain */ 4781 prev->m_next = m_free(m); 4782 m = prev; 4783 continue; 4784 } 4785 else if (m->m_next != NULL && 4786 M_TRAILINGSPACE(m) >= shortfall && 4787 m->m_next->m_len >= (8 + shortfall)) { 4788 /* m is writable and have enough data in next, pull up. */ 4789 4790 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4791 shortfall); 4792 m->m_len += shortfall; 4793 m->m_next->m_len -= shortfall; 4794 m->m_next->m_data += shortfall; 4795 } 4796 else if (m->m_next == NULL || 1) { 4797 /* Got a runt at the very end of the packet. 4798 * borrow data from the tail of the preceding mbuf and 4799 * update its length in-place. (The original data is still 4800 * valid, so we can do this even if prev is not writable.) 4801 */ 4802 4803 /* if we'd make prev a runt, just move all of its data. */ 4804 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4805 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4806 4807 if ((prev->m_len - shortfall) < 8) 4808 shortfall = prev->m_len; 4809 4810 #ifdef notyet /* just do the safe slow thing for now */ 4811 if (!M_READONLY(m)) { 4812 if (M_LEADINGSPACE(m) < shorfall) { 4813 void *m_dat; 4814 m_dat = (m->m_flags & M_PKTHDR) ? 4815 m->m_pktdat : m->dat; 4816 memmove(m_dat, mtod(m, void*), m->m_len); 4817 m->m_data = m_dat; 4818 } 4819 } else 4820 #endif /* just do the safe slow thing */ 4821 { 4822 struct mbuf * n = NULL; 4823 int newprevlen = prev->m_len - shortfall; 4824 4825 MGET(n, M_NOWAIT, MT_DATA); 4826 if (n == NULL) 4827 return ENOBUFS; 4828 KASSERT(m->m_len + shortfall < MLEN 4829 /*, 4830 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4831 4832 /* first copy the data we're stealing from prev */ 4833 memcpy(n->m_data, prev->m_data + newprevlen, 4834 shortfall); 4835 4836 /* update prev->m_len accordingly */ 4837 prev->m_len -= shortfall; 4838 4839 /* copy data from runt m */ 4840 memcpy(n->m_data + shortfall, m->m_data, 4841 m->m_len); 4842 4843 /* n holds what we stole from prev, plus m */ 4844 n->m_len = shortfall + m->m_len; 4845 4846 /* stitch n into chain and free m */ 4847 n->m_next = m->m_next; 4848 prev->m_next = n; 4849 /* KASSERT(m->m_next == NULL); */ 4850 m->m_next = NULL; 4851 m_free(m); 4852 m = n; /* for continuing loop */ 4853 } 4854 } 4855 prevlen = m->m_len; 4856 } 4857 return 0; 4858 } 4859 4860 /* 4861 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4862 * pointers to descriptors. 4863 */ 4864 static int 4865 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4866 { 4867 struct bge_tx_bd *f = NULL; 4868 uint32_t frag, cur; 4869 uint16_t csum_flags = 0; 4870 uint16_t txbd_tso_flags = 0; 4871 struct txdmamap_pool_entry *dma; 4872 bus_dmamap_t dmamap; 4873 int i = 0; 4874 struct m_tag *mtag; 4875 int use_tso, maxsegsize, error; 4876 4877 cur = frag = *txidx; 4878 4879 if (m_head->m_pkthdr.csum_flags) { 4880 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4881 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4882 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4883 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4884 } 4885 4886 /* 4887 * If we were asked to do an outboard checksum, and the NIC 4888 * has the bug where it sometimes adds in the Ethernet padding, 4889 * explicitly pad with zeros so the cksum will be correct either way. 4890 * (For now, do this for all chip versions, until newer 4891 * are confirmed to not require the workaround.) 4892 */ 4893 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4894 #ifdef notyet 4895 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4896 #endif 4897 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4898 goto check_dma_bug; 4899 4900 if (bge_cksum_pad(m_head) != 0) 4901 return ENOBUFS; 4902 4903 check_dma_bug: 4904 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4905 goto doit; 4906 4907 /* 4908 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4909 * less than eight bytes. If we encounter a teeny mbuf 4910 * at the end of a chain, we can pad. Otherwise, copy. 4911 */ 4912 if (bge_compact_dma_runt(m_head) != 0) 4913 return ENOBUFS; 4914 4915 doit: 4916 dma = SLIST_FIRST(&sc->txdma_list); 4917 if (dma == NULL) 4918 return ENOBUFS; 4919 dmamap = dma->dmamap; 4920 4921 /* 4922 * Set up any necessary TSO state before we start packing... 4923 */ 4924 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4925 if (!use_tso) { 4926 maxsegsize = 0; 4927 } else { /* TSO setup */ 4928 unsigned mss; 4929 struct ether_header *eh; 4930 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4931 struct mbuf * m0 = m_head; 4932 struct ip *ip; 4933 struct tcphdr *th; 4934 int iphl, hlen; 4935 4936 /* 4937 * XXX It would be nice if the mbuf pkthdr had offset 4938 * fields for the protocol headers. 4939 */ 4940 4941 eh = mtod(m0, struct ether_header *); 4942 switch (htons(eh->ether_type)) { 4943 case ETHERTYPE_IP: 4944 offset = ETHER_HDR_LEN; 4945 break; 4946 4947 case ETHERTYPE_VLAN: 4948 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4949 break; 4950 4951 default: 4952 /* 4953 * Don't support this protocol or encapsulation. 4954 */ 4955 return ENOBUFS; 4956 } 4957 4958 /* 4959 * TCP/IP headers are in the first mbuf; we can do 4960 * this the easy way. 4961 */ 4962 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4963 hlen = iphl + offset; 4964 if (__predict_false(m0->m_len < 4965 (hlen + sizeof(struct tcphdr)))) { 4966 4967 aprint_debug_dev(sc->bge_dev, 4968 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4969 "not handled yet\n", 4970 m0->m_len, hlen+ sizeof(struct tcphdr)); 4971 #ifdef NOTYET 4972 /* 4973 * XXX jonathan (at) NetBSD.org: untested. 4974 * how to force this branch to be taken? 4975 */ 4976 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4977 4978 m_copydata(m0, offset, sizeof(ip), &ip); 4979 m_copydata(m0, hlen, sizeof(th), &th); 4980 4981 ip.ip_len = 0; 4982 4983 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4984 sizeof(ip.ip_len), &ip.ip_len); 4985 4986 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4987 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4988 4989 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4990 sizeof(th.th_sum), &th.th_sum); 4991 4992 hlen += th.th_off << 2; 4993 iptcp_opt_words = hlen; 4994 #else 4995 /* 4996 * if_wm "hard" case not yet supported, can we not 4997 * mandate it out of existence? 4998 */ 4999 (void) ip; (void)th; (void) ip_tcp_hlen; 5000 5001 return ENOBUFS; 5002 #endif 5003 } else { 5004 ip = (struct ip *) (mtod(m0, char *) + offset); 5005 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5006 ip_tcp_hlen = iphl + (th->th_off << 2); 5007 5008 /* Total IP/TCP options, in 32-bit words */ 5009 iptcp_opt_words = (ip_tcp_hlen 5010 - sizeof(struct tcphdr) 5011 - sizeof(struct ip)) >> 2; 5012 } 5013 if (BGE_IS_575X_PLUS(sc)) { 5014 th->th_sum = 0; 5015 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5016 } else { 5017 /* 5018 * XXX jonathan (at) NetBSD.org: 5705 untested. 5019 * Requires TSO firmware patch for 5701/5703/5704. 5020 */ 5021 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5022 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5023 } 5024 5025 mss = m_head->m_pkthdr.segsz; 5026 txbd_tso_flags |= 5027 BGE_TXBDFLAG_CPU_PRE_DMA | 5028 BGE_TXBDFLAG_CPU_POST_DMA; 5029 5030 /* 5031 * Our NIC TSO-assist assumes TSO has standard, optionless 5032 * IPv4 and TCP headers, which total 40 bytes. By default, 5033 * the NIC copies 40 bytes of IP/TCP header from the 5034 * supplied header into the IP/TCP header portion of 5035 * each post-TSO-segment. If the supplied packet has IP or 5036 * TCP options, we need to tell the NIC to copy those extra 5037 * bytes into each post-TSO header, in addition to the normal 5038 * 40-byte IP/TCP header (and to leave space accordingly). 5039 * Unfortunately, the driver encoding of option length 5040 * varies across different ASIC families. 5041 */ 5042 tcp_seg_flags = 0; 5043 if (iptcp_opt_words) { 5044 if (BGE_IS_5705_PLUS(sc)) { 5045 tcp_seg_flags = 5046 iptcp_opt_words << 11; 5047 } else { 5048 txbd_tso_flags |= 5049 iptcp_opt_words << 12; 5050 } 5051 } 5052 maxsegsize = mss | tcp_seg_flags; 5053 ip->ip_len = htons(mss + ip_tcp_hlen); 5054 5055 } /* TSO setup */ 5056 5057 /* 5058 * Start packing the mbufs in this chain into 5059 * the fragment pointers. Stop when we run out 5060 * of fragments or hit the end of the mbuf chain. 5061 */ 5062 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5063 BUS_DMA_NOWAIT); 5064 if (error) 5065 return ENOBUFS; 5066 /* 5067 * Sanity check: avoid coming within 16 descriptors 5068 * of the end of the ring. 5069 */ 5070 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5071 BGE_TSO_PRINTF(("%s: " 5072 " dmamap_load_mbuf too close to ring wrap\n", 5073 device_xname(sc->bge_dev))); 5074 goto fail_unload; 5075 } 5076 5077 mtag = sc->ethercom.ec_nvlans ? 5078 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5079 5080 5081 /* Iterate over dmap-map fragments. */ 5082 for (i = 0; i < dmamap->dm_nsegs; i++) { 5083 f = &sc->bge_rdata->bge_tx_ring[frag]; 5084 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5085 break; 5086 5087 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5088 f->bge_len = dmamap->dm_segs[i].ds_len; 5089 5090 /* 5091 * For 5751 and follow-ons, for TSO we must turn 5092 * off checksum-assist flag in the tx-descr, and 5093 * supply the ASIC-revision-specific encoding 5094 * of TSO flags and segsize. 5095 */ 5096 if (use_tso) { 5097 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5098 f->bge_rsvd = maxsegsize; 5099 f->bge_flags = csum_flags | txbd_tso_flags; 5100 } else { 5101 f->bge_rsvd = 0; 5102 f->bge_flags = 5103 (csum_flags | txbd_tso_flags) & 0x0fff; 5104 } 5105 } else { 5106 f->bge_rsvd = 0; 5107 f->bge_flags = csum_flags; 5108 } 5109 5110 if (mtag != NULL) { 5111 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5112 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5113 } else { 5114 f->bge_vlan_tag = 0; 5115 } 5116 cur = frag; 5117 BGE_INC(frag, BGE_TX_RING_CNT); 5118 } 5119 5120 if (i < dmamap->dm_nsegs) { 5121 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5122 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5123 goto fail_unload; 5124 } 5125 5126 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5127 BUS_DMASYNC_PREWRITE); 5128 5129 if (frag == sc->bge_tx_saved_considx) { 5130 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5131 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5132 5133 goto fail_unload; 5134 } 5135 5136 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5137 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5138 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5139 sc->txdma[cur] = dma; 5140 sc->bge_txcnt += dmamap->dm_nsegs; 5141 5142 *txidx = frag; 5143 5144 return 0; 5145 5146 fail_unload: 5147 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5148 5149 return ENOBUFS; 5150 } 5151 5152 /* 5153 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5154 * to the mbuf data regions directly in the transmit descriptors. 5155 */ 5156 static void 5157 bge_start(struct ifnet *ifp) 5158 { 5159 struct bge_softc *sc; 5160 struct mbuf *m_head = NULL; 5161 uint32_t prodidx; 5162 int pkts = 0; 5163 5164 sc = ifp->if_softc; 5165 5166 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5167 return; 5168 5169 prodidx = sc->bge_tx_prodidx; 5170 5171 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5172 IFQ_POLL(&ifp->if_snd, m_head); 5173 if (m_head == NULL) 5174 break; 5175 5176 #if 0 5177 /* 5178 * XXX 5179 * safety overkill. If this is a fragmented packet chain 5180 * with delayed TCP/UDP checksums, then only encapsulate 5181 * it if we have enough descriptors to handle the entire 5182 * chain at once. 5183 * (paranoia -- may not actually be needed) 5184 */ 5185 if (m_head->m_flags & M_FIRSTFRAG && 5186 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5187 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5188 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5189 ifp->if_flags |= IFF_OACTIVE; 5190 break; 5191 } 5192 } 5193 #endif 5194 5195 /* 5196 * Pack the data into the transmit ring. If we 5197 * don't have room, set the OACTIVE flag and wait 5198 * for the NIC to drain the ring. 5199 */ 5200 if (bge_encap(sc, m_head, &prodidx)) { 5201 ifp->if_flags |= IFF_OACTIVE; 5202 break; 5203 } 5204 5205 /* now we are committed to transmit the packet */ 5206 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5207 pkts++; 5208 5209 /* 5210 * If there's a BPF listener, bounce a copy of this frame 5211 * to him. 5212 */ 5213 bpf_mtap(ifp, m_head); 5214 } 5215 if (pkts == 0) 5216 return; 5217 5218 /* Transmit */ 5219 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5220 /* 5700 b2 errata */ 5221 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5222 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5223 5224 sc->bge_tx_prodidx = prodidx; 5225 5226 /* 5227 * Set a timeout in case the chip goes out to lunch. 5228 */ 5229 ifp->if_timer = 5; 5230 } 5231 5232 static int 5233 bge_init(struct ifnet *ifp) 5234 { 5235 struct bge_softc *sc = ifp->if_softc; 5236 const uint16_t *m; 5237 uint32_t mode; 5238 int s, error = 0; 5239 5240 s = splnet(); 5241 5242 ifp = &sc->ethercom.ec_if; 5243 5244 /* Cancel pending I/O and flush buffers. */ 5245 bge_stop(ifp, 0); 5246 5247 bge_stop_fw(sc); 5248 bge_sig_pre_reset(sc, BGE_RESET_START); 5249 bge_reset(sc); 5250 bge_sig_legacy(sc, BGE_RESET_START); 5251 bge_sig_post_reset(sc, BGE_RESET_START); 5252 5253 bge_chipinit(sc); 5254 5255 /* 5256 * Init the various state machines, ring 5257 * control blocks and firmware. 5258 */ 5259 error = bge_blockinit(sc); 5260 if (error != 0) { 5261 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5262 error); 5263 splx(s); 5264 return error; 5265 } 5266 5267 ifp = &sc->ethercom.ec_if; 5268 5269 /* 5718 step 25, 57XX step 54 */ 5270 /* Specify MTU. */ 5271 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5272 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5273 5274 /* 5718 step 23 */ 5275 /* Load our MAC address. */ 5276 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5277 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5278 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5279 5280 /* Enable or disable promiscuous mode as needed. */ 5281 if (ifp->if_flags & IFF_PROMISC) 5282 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5283 else 5284 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5285 5286 /* Program multicast filter. */ 5287 bge_setmulti(sc); 5288 5289 /* Init RX ring. */ 5290 bge_init_rx_ring_std(sc); 5291 5292 /* 5293 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5294 * memory to insure that the chip has in fact read the first 5295 * entry of the ring. 5296 */ 5297 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5298 uint32_t v, i; 5299 for (i = 0; i < 10; i++) { 5300 DELAY(20); 5301 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5302 if (v == (MCLBYTES - ETHER_ALIGN)) 5303 break; 5304 } 5305 if (i == 10) 5306 aprint_error_dev(sc->bge_dev, 5307 "5705 A0 chip failed to load RX ring\n"); 5308 } 5309 5310 /* Init jumbo RX ring. */ 5311 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5312 bge_init_rx_ring_jumbo(sc); 5313 5314 /* Init our RX return ring index */ 5315 sc->bge_rx_saved_considx = 0; 5316 5317 /* Init TX ring. */ 5318 bge_init_tx_ring(sc); 5319 5320 /* 5718 step 63, 57XX step 94 */ 5321 /* Enable TX MAC state machine lockup fix. */ 5322 mode = CSR_READ_4(sc, BGE_TX_MODE); 5323 if (BGE_IS_5755_PLUS(sc) || 5324 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5325 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5326 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5327 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5328 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5329 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5330 } 5331 5332 /* Turn on transmitter */ 5333 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5334 /* 5718 step 64 */ 5335 DELAY(100); 5336 5337 /* 5718 step 65, 57XX step 95 */ 5338 /* Turn on receiver */ 5339 mode = CSR_READ_4(sc, BGE_RX_MODE); 5340 if (BGE_IS_5755_PLUS(sc)) 5341 mode |= BGE_RXMODE_IPV6_ENABLE; 5342 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5343 /* 5718 step 66 */ 5344 DELAY(10); 5345 5346 /* 5718 step 12 */ 5347 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5348 5349 /* Tell firmware we're alive. */ 5350 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5351 5352 /* Enable host interrupts. */ 5353 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5354 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5355 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5356 5357 if ((error = bge_ifmedia_upd(ifp)) != 0) 5358 goto out; 5359 5360 ifp->if_flags |= IFF_RUNNING; 5361 ifp->if_flags &= ~IFF_OACTIVE; 5362 5363 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5364 5365 out: 5366 sc->bge_if_flags = ifp->if_flags; 5367 splx(s); 5368 5369 return error; 5370 } 5371 5372 /* 5373 * Set media options. 5374 */ 5375 static int 5376 bge_ifmedia_upd(struct ifnet *ifp) 5377 { 5378 struct bge_softc *sc = ifp->if_softc; 5379 struct mii_data *mii = &sc->bge_mii; 5380 struct ifmedia *ifm = &sc->bge_ifmedia; 5381 int rc; 5382 5383 /* If this is a 1000baseX NIC, enable the TBI port. */ 5384 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5385 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5386 return EINVAL; 5387 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5388 case IFM_AUTO: 5389 /* 5390 * The BCM5704 ASIC appears to have a special 5391 * mechanism for programming the autoneg 5392 * advertisement registers in TBI mode. 5393 */ 5394 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5395 uint32_t sgdig; 5396 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5397 if (sgdig & BGE_SGDIGSTS_DONE) { 5398 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5399 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5400 sgdig |= BGE_SGDIGCFG_AUTO | 5401 BGE_SGDIGCFG_PAUSE_CAP | 5402 BGE_SGDIGCFG_ASYM_PAUSE; 5403 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5404 sgdig | BGE_SGDIGCFG_SEND); 5405 DELAY(5); 5406 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5407 sgdig); 5408 } 5409 } 5410 break; 5411 case IFM_1000_SX: 5412 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5413 BGE_CLRBIT(sc, BGE_MAC_MODE, 5414 BGE_MACMODE_HALF_DUPLEX); 5415 } else { 5416 BGE_SETBIT(sc, BGE_MAC_MODE, 5417 BGE_MACMODE_HALF_DUPLEX); 5418 } 5419 DELAY(40); 5420 break; 5421 default: 5422 return EINVAL; 5423 } 5424 /* XXX 802.3x flow control for 1000BASE-SX */ 5425 return 0; 5426 } 5427 5428 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5429 if ((rc = mii_mediachg(mii)) == ENXIO) 5430 return 0; 5431 5432 /* 5433 * Force an interrupt so that we will call bge_link_upd 5434 * if needed and clear any pending link state attention. 5435 * Without this we are not getting any further interrupts 5436 * for link state changes and thus will not UP the link and 5437 * not be able to send in bge_start. The only way to get 5438 * things working was to receive a packet and get a RX intr. 5439 */ 5440 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5441 sc->bge_flags & BGE_IS_5788) 5442 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5443 else 5444 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5445 5446 return rc; 5447 } 5448 5449 /* 5450 * Report current media status. 5451 */ 5452 static void 5453 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5454 { 5455 struct bge_softc *sc = ifp->if_softc; 5456 struct mii_data *mii = &sc->bge_mii; 5457 5458 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5459 ifmr->ifm_status = IFM_AVALID; 5460 ifmr->ifm_active = IFM_ETHER; 5461 if (CSR_READ_4(sc, BGE_MAC_STS) & 5462 BGE_MACSTAT_TBI_PCS_SYNCHED) 5463 ifmr->ifm_status |= IFM_ACTIVE; 5464 ifmr->ifm_active |= IFM_1000_SX; 5465 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5466 ifmr->ifm_active |= IFM_HDX; 5467 else 5468 ifmr->ifm_active |= IFM_FDX; 5469 return; 5470 } 5471 5472 mii_pollstat(mii); 5473 ifmr->ifm_status = mii->mii_media_status; 5474 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5475 sc->bge_flowflags; 5476 } 5477 5478 static int 5479 bge_ifflags_cb(struct ethercom *ec) 5480 { 5481 struct ifnet *ifp = &ec->ec_if; 5482 struct bge_softc *sc = ifp->if_softc; 5483 int change = ifp->if_flags ^ sc->bge_if_flags; 5484 5485 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5486 return ENETRESET; 5487 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5488 return 0; 5489 5490 if ((ifp->if_flags & IFF_PROMISC) == 0) 5491 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5492 else 5493 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5494 5495 bge_setmulti(sc); 5496 5497 sc->bge_if_flags = ifp->if_flags; 5498 return 0; 5499 } 5500 5501 static int 5502 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5503 { 5504 struct bge_softc *sc = ifp->if_softc; 5505 struct ifreq *ifr = (struct ifreq *) data; 5506 int s, error = 0; 5507 struct mii_data *mii; 5508 5509 s = splnet(); 5510 5511 switch (command) { 5512 case SIOCSIFMEDIA: 5513 /* XXX Flow control is not supported for 1000BASE-SX */ 5514 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5515 ifr->ifr_media &= ~IFM_ETH_FMASK; 5516 sc->bge_flowflags = 0; 5517 } 5518 5519 /* Flow control requires full-duplex mode. */ 5520 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5521 (ifr->ifr_media & IFM_FDX) == 0) { 5522 ifr->ifr_media &= ~IFM_ETH_FMASK; 5523 } 5524 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5525 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5526 /* We can do both TXPAUSE and RXPAUSE. */ 5527 ifr->ifr_media |= 5528 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5529 } 5530 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5531 } 5532 /* FALLTHROUGH */ 5533 case SIOCGIFMEDIA: 5534 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5535 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5536 command); 5537 } else { 5538 mii = &sc->bge_mii; 5539 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5540 command); 5541 } 5542 break; 5543 default: 5544 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5545 break; 5546 5547 error = 0; 5548 5549 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5550 ; 5551 else if (ifp->if_flags & IFF_RUNNING) 5552 bge_setmulti(sc); 5553 break; 5554 } 5555 5556 splx(s); 5557 5558 return error; 5559 } 5560 5561 static void 5562 bge_watchdog(struct ifnet *ifp) 5563 { 5564 struct bge_softc *sc; 5565 5566 sc = ifp->if_softc; 5567 5568 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5569 5570 ifp->if_flags &= ~IFF_RUNNING; 5571 bge_init(ifp); 5572 5573 ifp->if_oerrors++; 5574 } 5575 5576 static void 5577 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5578 { 5579 int i; 5580 5581 BGE_CLRBIT_FLUSH(sc, reg, bit); 5582 5583 for (i = 0; i < 1000; i++) { 5584 delay(100); 5585 if ((CSR_READ_4(sc, reg) & bit) == 0) 5586 return; 5587 } 5588 5589 /* 5590 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5591 * on some environment (and once after boot?) 5592 */ 5593 if (reg != BGE_SRS_MODE) 5594 aprint_error_dev(sc->bge_dev, 5595 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5596 (u_long)reg, bit); 5597 } 5598 5599 /* 5600 * Stop the adapter and free any mbufs allocated to the 5601 * RX and TX lists. 5602 */ 5603 static void 5604 bge_stop(struct ifnet *ifp, int disable) 5605 { 5606 struct bge_softc *sc = ifp->if_softc; 5607 5608 callout_stop(&sc->bge_timeout); 5609 5610 /* Disable host interrupts. */ 5611 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5612 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5613 5614 /* 5615 * Tell firmware we're shutting down. 5616 */ 5617 bge_stop_fw(sc); 5618 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5619 5620 /* 5621 * Disable all of the receiver blocks. 5622 */ 5623 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5624 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5625 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5626 if (BGE_IS_5700_FAMILY(sc)) 5627 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5628 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5629 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5630 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5631 5632 /* 5633 * Disable all of the transmit blocks. 5634 */ 5635 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5636 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5637 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5638 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5639 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5640 if (BGE_IS_5700_FAMILY(sc)) 5641 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5642 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5643 5644 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5645 delay(40); 5646 5647 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5648 5649 /* 5650 * Shut down all of the memory managers and related 5651 * state machines. 5652 */ 5653 /* 5718 step 5a,5b */ 5654 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5655 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5656 if (BGE_IS_5700_FAMILY(sc)) 5657 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5658 5659 /* 5718 step 5c,5d */ 5660 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5661 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5662 5663 if (BGE_IS_5700_FAMILY(sc)) { 5664 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5665 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5666 } 5667 5668 bge_reset(sc); 5669 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5670 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5671 5672 /* 5673 * Keep the ASF firmware running if up. 5674 */ 5675 if (sc->bge_asf_mode & ASF_STACKUP) 5676 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5677 else 5678 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5679 5680 /* Free the RX lists. */ 5681 bge_free_rx_ring_std(sc); 5682 5683 /* Free jumbo RX list. */ 5684 if (BGE_IS_JUMBO_CAPABLE(sc)) 5685 bge_free_rx_ring_jumbo(sc); 5686 5687 /* Free TX buffers. */ 5688 bge_free_tx_ring(sc); 5689 5690 /* 5691 * Isolate/power down the PHY. 5692 */ 5693 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5694 mii_down(&sc->bge_mii); 5695 5696 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5697 5698 /* Clear MAC's link state (PHY may still have link UP). */ 5699 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5700 5701 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5702 } 5703 5704 static void 5705 bge_link_upd(struct bge_softc *sc) 5706 { 5707 struct ifnet *ifp = &sc->ethercom.ec_if; 5708 struct mii_data *mii = &sc->bge_mii; 5709 uint32_t status; 5710 int link; 5711 5712 /* Clear 'pending link event' flag */ 5713 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5714 5715 /* 5716 * Process link state changes. 5717 * Grrr. The link status word in the status block does 5718 * not work correctly on the BCM5700 rev AX and BX chips, 5719 * according to all available information. Hence, we have 5720 * to enable MII interrupts in order to properly obtain 5721 * async link changes. Unfortunately, this also means that 5722 * we have to read the MAC status register to detect link 5723 * changes, thereby adding an additional register access to 5724 * the interrupt handler. 5725 */ 5726 5727 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5728 status = CSR_READ_4(sc, BGE_MAC_STS); 5729 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5730 mii_pollstat(mii); 5731 5732 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5733 mii->mii_media_status & IFM_ACTIVE && 5734 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5735 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5736 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5737 (!(mii->mii_media_status & IFM_ACTIVE) || 5738 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5739 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5740 5741 /* Clear the interrupt */ 5742 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5743 BGE_EVTENB_MI_INTERRUPT); 5744 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5745 BRGPHY_MII_ISR); 5746 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5747 BRGPHY_MII_IMR, BRGPHY_INTRS); 5748 } 5749 return; 5750 } 5751 5752 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5753 status = CSR_READ_4(sc, BGE_MAC_STS); 5754 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5755 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5756 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5757 if (BGE_ASICREV(sc->bge_chipid) 5758 == BGE_ASICREV_BCM5704) { 5759 BGE_CLRBIT(sc, BGE_MAC_MODE, 5760 BGE_MACMODE_TBI_SEND_CFGS); 5761 DELAY(40); 5762 } 5763 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5764 if_link_state_change(ifp, LINK_STATE_UP); 5765 } 5766 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5767 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5768 if_link_state_change(ifp, LINK_STATE_DOWN); 5769 } 5770 /* 5771 * Discard link events for MII/GMII cards if MI auto-polling disabled. 5772 * This should not happen since mii callouts are locked now, but 5773 * we keep this check for debug. 5774 */ 5775 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5776 /* 5777 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5778 * bit in status word always set. Workaround this bug by 5779 * reading PHY link status directly. 5780 */ 5781 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5782 BGE_STS_LINK : 0; 5783 5784 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5785 mii_pollstat(mii); 5786 5787 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5788 mii->mii_media_status & IFM_ACTIVE && 5789 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5790 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5791 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5792 (!(mii->mii_media_status & IFM_ACTIVE) || 5793 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5794 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5795 } 5796 } 5797 5798 /* Clear the attention */ 5799 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5800 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5801 BGE_MACSTAT_LINK_CHANGED); 5802 } 5803 5804 static int 5805 bge_sysctl_verify(SYSCTLFN_ARGS) 5806 { 5807 int error, t; 5808 struct sysctlnode node; 5809 5810 node = *rnode; 5811 t = *(int*)rnode->sysctl_data; 5812 node.sysctl_data = &t; 5813 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5814 if (error || newp == NULL) 5815 return error; 5816 5817 #if 0 5818 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5819 node.sysctl_num, rnode->sysctl_num)); 5820 #endif 5821 5822 if (node.sysctl_num == bge_rxthresh_nodenum) { 5823 if (t < 0 || t >= NBGE_RX_THRESH) 5824 return EINVAL; 5825 bge_update_all_threshes(t); 5826 } else 5827 return EINVAL; 5828 5829 *(int*)rnode->sysctl_data = t; 5830 5831 return 0; 5832 } 5833 5834 /* 5835 * Set up sysctl(3) MIB, hw.bge.*. 5836 */ 5837 static void 5838 bge_sysctl_init(struct bge_softc *sc) 5839 { 5840 int rc, bge_root_num; 5841 const struct sysctlnode *node; 5842 5843 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5844 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5845 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5846 goto out; 5847 } 5848 5849 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5850 0, CTLTYPE_NODE, "bge", 5851 SYSCTL_DESCR("BGE interface controls"), 5852 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5853 goto out; 5854 } 5855 5856 bge_root_num = node->sysctl_num; 5857 5858 /* BGE Rx interrupt mitigation level */ 5859 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5860 CTLFLAG_READWRITE, 5861 CTLTYPE_INT, "rx_lvl", 5862 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5863 bge_sysctl_verify, 0, 5864 &bge_rx_thresh_lvl, 5865 0, CTL_HW, bge_root_num, CTL_CREATE, 5866 CTL_EOL)) != 0) { 5867 goto out; 5868 } 5869 5870 bge_rxthresh_nodenum = node->sysctl_num; 5871 5872 return; 5873 5874 out: 5875 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5876 } 5877 5878 #ifdef BGE_DEBUG 5879 void 5880 bge_debug_info(struct bge_softc *sc) 5881 { 5882 5883 printf("Hardware Flags:\n"); 5884 if (BGE_IS_57765_PLUS(sc)) 5885 printf(" - 57765 Plus\n"); 5886 if (BGE_IS_5717_PLUS(sc)) 5887 printf(" - 5717 Plus\n"); 5888 if (BGE_IS_5755_PLUS(sc)) 5889 printf(" - 5755 Plus\n"); 5890 if (BGE_IS_575X_PLUS(sc)) 5891 printf(" - 575X Plus\n"); 5892 if (BGE_IS_5705_PLUS(sc)) 5893 printf(" - 5705 Plus\n"); 5894 if (BGE_IS_5714_FAMILY(sc)) 5895 printf(" - 5714 Family\n"); 5896 if (BGE_IS_5700_FAMILY(sc)) 5897 printf(" - 5700 Family\n"); 5898 if (sc->bge_flags & BGE_IS_5788) 5899 printf(" - 5788\n"); 5900 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5901 printf(" - Supports Jumbo Frames\n"); 5902 if (sc->bge_flags & BGE_NO_EEPROM) 5903 printf(" - No EEPROM\n"); 5904 if (sc->bge_flags & BGE_PCIX) 5905 printf(" - PCI-X Bus\n"); 5906 if (sc->bge_flags & BGE_PCIE) 5907 printf(" - PCI Express Bus\n"); 5908 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5909 printf(" - RX Alignment Bug\n"); 5910 if (sc->bge_flags & BGE_APE) 5911 printf(" - APE\n"); 5912 if (sc->bge_flags & BGE_CPMU_PRESENT) 5913 printf(" - CPMU\n"); 5914 if (sc->bge_flags & BGE_TSO) 5915 printf(" - TSO\n"); 5916 5917 if (sc->bge_flags & BGE_PHY_NO_3LED) 5918 printf(" - No 3 LEDs\n"); 5919 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5920 printf(" - CRC bug\n"); 5921 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5922 printf(" - ADC bug\n"); 5923 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5924 printf(" - 5704 A0 bug\n"); 5925 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5926 printf(" - jitter bug\n"); 5927 if (sc->bge_flags & BGE_PHY_BER_BUG) 5928 printf(" - BER bug\n"); 5929 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5930 printf(" - adjust trim\n"); 5931 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5932 printf(" - no wirespeed\n"); 5933 } 5934 #endif /* BGE_DEBUG */ 5935 5936 static int 5937 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5938 { 5939 prop_dictionary_t dict; 5940 prop_data_t ea; 5941 5942 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5943 return 1; 5944 5945 dict = device_properties(sc->bge_dev); 5946 ea = prop_dictionary_get(dict, "mac-address"); 5947 if (ea != NULL) { 5948 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5949 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5950 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5951 return 0; 5952 } 5953 5954 return 1; 5955 } 5956 5957 static int 5958 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5959 { 5960 uint32_t mac_addr; 5961 5962 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5963 if ((mac_addr >> 16) == 0x484b) { 5964 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5965 ether_addr[1] = (uint8_t)mac_addr; 5966 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5967 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5968 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5969 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5970 ether_addr[5] = (uint8_t)mac_addr; 5971 return 0; 5972 } 5973 return 1; 5974 } 5975 5976 static int 5977 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5978 { 5979 int mac_offset = BGE_EE_MAC_OFFSET; 5980 5981 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5982 mac_offset = BGE_EE_MAC_OFFSET_5906; 5983 5984 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5985 ETHER_ADDR_LEN)); 5986 } 5987 5988 static int 5989 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5990 { 5991 5992 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5993 return 1; 5994 5995 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5996 ETHER_ADDR_LEN)); 5997 } 5998 5999 static int 6000 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6001 { 6002 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6003 /* NOTE: Order is critical */ 6004 bge_get_eaddr_fw, 6005 bge_get_eaddr_mem, 6006 bge_get_eaddr_nvram, 6007 bge_get_eaddr_eeprom, 6008 NULL 6009 }; 6010 const bge_eaddr_fcn_t *func; 6011 6012 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6013 if ((*func)(sc, eaddr) == 0) 6014 break; 6015 } 6016 return (*func == NULL ? ENXIO : 0); 6017 } 6018
Indexes created Mon Sep 22 13:09:51 GMT 2025