if_bge.c revision 1.256
1 /* $NetBSD: if_bge.c,v 1.256 2013/07/05 07:08:26 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.256 2013/07/05 07:08:26 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rnd.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 680 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 682 683 static const struct bge_revision { 684 uint32_t br_chipid; 685 const char *br_name; 686 } bge_revisions[] = { 687 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 688 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 689 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 690 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 691 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 692 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 693 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 694 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 695 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 696 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 697 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 698 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 699 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 700 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 701 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 702 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 703 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 704 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 705 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 706 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 707 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 708 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 709 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 710 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 711 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 712 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 713 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 714 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 715 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 716 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 717 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 718 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 719 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 720 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 721 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 722 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 723 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 724 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 725 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 726 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 727 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 728 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 729 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 730 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 731 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 732 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 733 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 734 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 735 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 736 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 737 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 738 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 739 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 740 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 741 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 742 /* 5754 and 5787 share the same ASIC ID */ 743 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 744 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 745 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 746 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 747 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 748 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 749 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 750 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 751 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 752 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 753 754 { 0, NULL } 755 }; 756 757 /* 758 * Some defaults for major revisions, so that newer steppings 759 * that we don't know about have a shot at working. 760 */ 761 static const struct bge_revision bge_majorrevs[] = { 762 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 763 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 764 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 765 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 766 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 767 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 768 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 769 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 771 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 772 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 773 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 774 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 775 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 776 /* 5754 and 5787 share the same ASIC ID */ 777 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 778 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 779 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 780 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 781 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 782 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 783 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 784 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 785 786 { 0, NULL } 787 }; 788 789 static int bge_allow_asf = 1; 790 791 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 792 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 793 794 static uint32_t 795 bge_readmem_ind(struct bge_softc *sc, int off) 796 { 797 pcireg_t val; 798 799 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 800 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 801 return 0; 802 803 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 804 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 806 return val; 807 } 808 809 static void 810 bge_writemem_ind(struct bge_softc *sc, int off, int val) 811 { 812 813 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 816 } 817 818 /* 819 * PCI Express only 820 */ 821 static void 822 bge_set_max_readrq(struct bge_softc *sc) 823 { 824 pcireg_t val; 825 826 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 827 + PCIE_DCSR); 828 val &= ~PCIE_DCSR_MAX_READ_REQ; 829 switch (sc->bge_expmrq) { 830 case 2048: 831 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 832 break; 833 case 4096: 834 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 835 break; 836 default: 837 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 838 break; 839 } 840 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 841 + PCIE_DCSR, val); 842 } 843 844 #ifdef notdef 845 static uint32_t 846 bge_readreg_ind(struct bge_softc *sc, int off) 847 { 848 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 849 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 850 } 851 #endif 852 853 static void 854 bge_writereg_ind(struct bge_softc *sc, int off, int val) 855 { 856 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 858 } 859 860 static void 861 bge_writemem_direct(struct bge_softc *sc, int off, int val) 862 { 863 CSR_WRITE_4(sc, off, val); 864 } 865 866 static void 867 bge_writembx(struct bge_softc *sc, int off, int val) 868 { 869 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 870 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 871 872 CSR_WRITE_4(sc, off, val); 873 } 874 875 static void 876 bge_writembx_flush(struct bge_softc *sc, int off, int val) 877 { 878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 879 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 880 881 CSR_WRITE_4_FLUSH(sc, off, val); 882 } 883 884 /* 885 * Clear all stale locks and select the lock for this driver instance. 886 */ 887 void 888 bge_ape_lock_init(struct bge_softc *sc) 889 { 890 struct pci_attach_args *pa = &(sc->bge_pa); 891 uint32_t bit, regbase; 892 int i; 893 894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 895 regbase = BGE_APE_LOCK_GRANT; 896 else 897 regbase = BGE_APE_PER_LOCK_GRANT; 898 899 /* Clear any stale locks. */ 900 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 901 switch (i) { 902 case BGE_APE_LOCK_PHY0: 903 case BGE_APE_LOCK_PHY1: 904 case BGE_APE_LOCK_PHY2: 905 case BGE_APE_LOCK_PHY3: 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 break; 908 default: 909 if (pa->pa_function == 0) 910 bit = BGE_APE_LOCK_GRANT_DRIVER0; 911 else 912 bit = (1 << pa->pa_function); 913 } 914 APE_WRITE_4(sc, regbase + 4 * i, bit); 915 } 916 917 /* Select the PHY lock based on the device's function number. */ 918 switch (pa->pa_function) { 919 case 0: 920 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 921 break; 922 case 1: 923 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 924 break; 925 case 2: 926 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 927 break; 928 case 3: 929 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 930 break; 931 default: 932 printf("%s: PHY lock not supported on function\n", 933 device_xname(sc->bge_dev)); 934 break; 935 } 936 } 937 938 /* 939 * Check for APE firmware, set flags, and print version info. 940 */ 941 void 942 bge_ape_read_fw_ver(struct bge_softc *sc) 943 { 944 const char *fwtype; 945 uint32_t apedata, features; 946 947 /* Check for a valid APE signature in shared memory. */ 948 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 949 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 950 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 951 return; 952 } 953 954 /* Check if APE firmware is running. */ 955 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 956 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 957 printf("%s: APE signature found but FW status not ready! " 958 "0x%08x\n", device_xname(sc->bge_dev), apedata); 959 return; 960 } 961 962 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 963 964 /* Fetch the APE firwmare type and version. */ 965 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 966 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 967 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 968 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 969 fwtype = "NCSI"; 970 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 971 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 972 fwtype = "DASH"; 973 } else 974 fwtype = "UNKN"; 975 976 /* Print the APE firmware version. */ 977 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 978 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 979 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 980 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 981 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 982 } 983 984 int 985 bge_ape_lock(struct bge_softc *sc, int locknum) 986 { 987 struct pci_attach_args *pa = &(sc->bge_pa); 988 uint32_t bit, gnt, req, status; 989 int i, off; 990 991 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 992 return (0); 993 994 /* Lock request/grant registers have different bases. */ 995 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 996 req = BGE_APE_LOCK_REQ; 997 gnt = BGE_APE_LOCK_GRANT; 998 } else { 999 req = BGE_APE_PER_LOCK_REQ; 1000 gnt = BGE_APE_PER_LOCK_GRANT; 1001 } 1002 1003 off = 4 * locknum; 1004 1005 switch (locknum) { 1006 case BGE_APE_LOCK_GPIO: 1007 /* Lock required when using GPIO. */ 1008 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1009 return (0); 1010 if (pa->pa_function == 0) 1011 bit = BGE_APE_LOCK_REQ_DRIVER0; 1012 else 1013 bit = (1 << pa->pa_function); 1014 break; 1015 case BGE_APE_LOCK_GRC: 1016 /* Lock required to reset the device. */ 1017 if (pa->pa_function == 0) 1018 bit = BGE_APE_LOCK_REQ_DRIVER0; 1019 else 1020 bit = (1 << pa->pa_function); 1021 break; 1022 case BGE_APE_LOCK_MEM: 1023 /* Lock required when accessing certain APE memory. */ 1024 if (pa->pa_function == 0) 1025 bit = BGE_APE_LOCK_REQ_DRIVER0; 1026 else 1027 bit = (1 << pa->pa_function); 1028 break; 1029 case BGE_APE_LOCK_PHY0: 1030 case BGE_APE_LOCK_PHY1: 1031 case BGE_APE_LOCK_PHY2: 1032 case BGE_APE_LOCK_PHY3: 1033 /* Lock required when accessing PHYs. */ 1034 bit = BGE_APE_LOCK_REQ_DRIVER0; 1035 break; 1036 default: 1037 return (EINVAL); 1038 } 1039 1040 /* Request a lock. */ 1041 APE_WRITE_4_FLUSH(sc, req + off, bit); 1042 1043 /* Wait up to 1 second to acquire lock. */ 1044 for (i = 0; i < 20000; i++) { 1045 status = APE_READ_4(sc, gnt + off); 1046 if (status == bit) 1047 break; 1048 DELAY(50); 1049 } 1050 1051 /* Handle any errors. */ 1052 if (status != bit) { 1053 printf("%s: APE lock %d request failed! " 1054 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1055 device_xname(sc->bge_dev), 1056 locknum, req + off, bit & 0xFFFF, gnt + off, 1057 status & 0xFFFF); 1058 /* Revoke the lock request. */ 1059 APE_WRITE_4(sc, gnt + off, bit); 1060 return (EBUSY); 1061 } 1062 1063 return (0); 1064 } 1065 1066 void 1067 bge_ape_unlock(struct bge_softc *sc, int locknum) 1068 { 1069 struct pci_attach_args *pa = &(sc->bge_pa); 1070 uint32_t bit, gnt; 1071 int off; 1072 1073 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1074 return; 1075 1076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1077 gnt = BGE_APE_LOCK_GRANT; 1078 else 1079 gnt = BGE_APE_PER_LOCK_GRANT; 1080 1081 off = 4 * locknum; 1082 1083 switch (locknum) { 1084 case BGE_APE_LOCK_GPIO: 1085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1086 return; 1087 if (pa->pa_function == 0) 1088 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1089 else 1090 bit = (1 << pa->pa_function); 1091 break; 1092 case BGE_APE_LOCK_GRC: 1093 if (pa->pa_function == 0) 1094 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1095 else 1096 bit = (1 << pa->pa_function); 1097 break; 1098 case BGE_APE_LOCK_MEM: 1099 if (pa->pa_function == 0) 1100 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1101 else 1102 bit = (1 << pa->pa_function); 1103 break; 1104 case BGE_APE_LOCK_PHY0: 1105 case BGE_APE_LOCK_PHY1: 1106 case BGE_APE_LOCK_PHY2: 1107 case BGE_APE_LOCK_PHY3: 1108 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1109 break; 1110 default: 1111 return; 1112 } 1113 1114 /* Write and flush for consecutive bge_ape_lock() */ 1115 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1116 } 1117 1118 /* 1119 * Send an event to the APE firmware. 1120 */ 1121 void 1122 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1123 { 1124 uint32_t apedata; 1125 int i; 1126 1127 /* NCSI does not support APE events. */ 1128 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1129 return; 1130 1131 /* Wait up to 1ms for APE to service previous event. */ 1132 for (i = 10; i > 0; i--) { 1133 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1134 break; 1135 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1136 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1137 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1138 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1141 break; 1142 } 1143 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1144 DELAY(100); 1145 } 1146 if (i == 0) { 1147 printf("%s: APE event 0x%08x send timed out\n", 1148 device_xname(sc->bge_dev), event); 1149 } 1150 } 1151 1152 void 1153 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1154 { 1155 uint32_t apedata, event; 1156 1157 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1158 return; 1159 1160 switch (kind) { 1161 case BGE_RESET_START: 1162 /* If this is the first load, clear the load counter. */ 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1164 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1165 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1166 else { 1167 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1168 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1169 } 1170 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1171 BGE_APE_HOST_SEG_SIG_MAGIC); 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1173 BGE_APE_HOST_SEG_LEN_MAGIC); 1174 1175 /* Add some version info if bge(4) supports it. */ 1176 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1177 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1178 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1179 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1180 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1181 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1182 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1183 BGE_APE_HOST_DRVR_STATE_START); 1184 event = BGE_APE_EVENT_STATUS_STATE_START; 1185 break; 1186 case BGE_RESET_SHUTDOWN: 1187 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1188 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1189 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1190 break; 1191 case BGE_RESET_SUSPEND: 1192 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1193 break; 1194 default: 1195 return; 1196 } 1197 1198 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1199 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1200 } 1201 1202 static uint8_t 1203 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1204 { 1205 uint32_t access, byte = 0; 1206 int i; 1207 1208 /* Lock. */ 1209 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1210 for (i = 0; i < 8000; i++) { 1211 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1212 break; 1213 DELAY(20); 1214 } 1215 if (i == 8000) 1216 return 1; 1217 1218 /* Enable access. */ 1219 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1220 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1221 1222 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1223 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1224 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1225 DELAY(10); 1226 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1227 DELAY(10); 1228 break; 1229 } 1230 } 1231 1232 if (i == BGE_TIMEOUT * 10) { 1233 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1234 return 1; 1235 } 1236 1237 /* Get result. */ 1238 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1239 1240 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1241 1242 /* Disable access. */ 1243 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1244 1245 /* Unlock. */ 1246 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1247 1248 return 0; 1249 } 1250 1251 /* 1252 * Read a sequence of bytes from NVRAM. 1253 */ 1254 static int 1255 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1256 { 1257 int error = 0, i; 1258 uint8_t byte = 0; 1259 1260 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1261 return 1; 1262 1263 for (i = 0; i < cnt; i++) { 1264 error = bge_nvram_getbyte(sc, off + i, &byte); 1265 if (error) 1266 break; 1267 *(dest + i) = byte; 1268 } 1269 1270 return (error ? 1 : 0); 1271 } 1272 1273 /* 1274 * Read a byte of data stored in the EEPROM at address 'addr.' The 1275 * BCM570x supports both the traditional bitbang interface and an 1276 * auto access interface for reading the EEPROM. We use the auto 1277 * access method. 1278 */ 1279 static uint8_t 1280 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1281 { 1282 int i; 1283 uint32_t byte = 0; 1284 1285 /* 1286 * Enable use of auto EEPROM access so we can avoid 1287 * having to use the bitbang method. 1288 */ 1289 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1290 1291 /* Reset the EEPROM, load the clock period. */ 1292 CSR_WRITE_4(sc, BGE_EE_ADDR, 1293 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1294 DELAY(20); 1295 1296 /* Issue the read EEPROM command. */ 1297 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1298 1299 /* Wait for completion */ 1300 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1301 DELAY(10); 1302 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1303 break; 1304 } 1305 1306 if (i == BGE_TIMEOUT * 10) { 1307 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1308 return 1; 1309 } 1310 1311 /* Get result. */ 1312 byte = CSR_READ_4(sc, BGE_EE_DATA); 1313 1314 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1315 1316 return 0; 1317 } 1318 1319 /* 1320 * Read a sequence of bytes from the EEPROM. 1321 */ 1322 static int 1323 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1324 { 1325 int error = 0, i; 1326 uint8_t byte = 0; 1327 char *dest = destv; 1328 1329 for (i = 0; i < cnt; i++) { 1330 error = bge_eeprom_getbyte(sc, off + i, &byte); 1331 if (error) 1332 break; 1333 *(dest + i) = byte; 1334 } 1335 1336 return (error ? 1 : 0); 1337 } 1338 1339 static int 1340 bge_miibus_readreg(device_t dev, int phy, int reg) 1341 { 1342 struct bge_softc *sc = device_private(dev); 1343 uint32_t val; 1344 uint32_t autopoll; 1345 int i; 1346 1347 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1348 return 0; 1349 1350 /* Reading with autopolling on may trigger PCI errors */ 1351 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1352 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1353 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1354 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1355 DELAY(80); 1356 } 1357 1358 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1359 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1360 1361 for (i = 0; i < BGE_TIMEOUT; i++) { 1362 delay(10); 1363 val = CSR_READ_4(sc, BGE_MI_COMM); 1364 if (!(val & BGE_MICOMM_BUSY)) { 1365 DELAY(5); 1366 val = CSR_READ_4(sc, BGE_MI_COMM); 1367 break; 1368 } 1369 } 1370 1371 if (i == BGE_TIMEOUT) { 1372 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1373 val = 0; 1374 goto done; 1375 } 1376 1377 done: 1378 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1379 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1380 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1381 DELAY(80); 1382 } 1383 1384 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1385 1386 if (val & BGE_MICOMM_READFAIL) 1387 return 0; 1388 1389 return (val & 0xFFFF); 1390 } 1391 1392 static void 1393 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1394 { 1395 struct bge_softc *sc = device_private(dev); 1396 uint32_t autopoll; 1397 int i; 1398 1399 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1400 return; 1401 1402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1403 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1404 return; 1405 1406 /* Reading with autopolling on may trigger PCI errors */ 1407 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1408 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1409 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1410 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1411 DELAY(80); 1412 } 1413 1414 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1415 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1416 1417 for (i = 0; i < BGE_TIMEOUT; i++) { 1418 delay(10); 1419 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1420 delay(5); 1421 CSR_READ_4(sc, BGE_MI_COMM); 1422 break; 1423 } 1424 } 1425 1426 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1427 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1428 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1429 delay(80); 1430 } 1431 1432 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1433 1434 if (i == BGE_TIMEOUT) 1435 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1436 } 1437 1438 static void 1439 bge_miibus_statchg(struct ifnet *ifp) 1440 { 1441 struct bge_softc *sc = ifp->if_softc; 1442 struct mii_data *mii = &sc->bge_mii; 1443 uint32_t mac_mode, rx_mode, tx_mode; 1444 1445 /* 1446 * Get flow control negotiation result. 1447 */ 1448 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1449 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1450 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1451 1452 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1453 mii->mii_media_status & IFM_ACTIVE && 1454 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1455 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1456 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1457 (!(mii->mii_media_status & IFM_ACTIVE) || 1458 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1459 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1460 1461 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1462 return; 1463 1464 /* Set the port mode (MII/GMII) to match the link speed. */ 1465 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1466 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1467 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1468 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1469 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1470 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1471 mac_mode |= BGE_PORTMODE_GMII; 1472 else 1473 mac_mode |= BGE_PORTMODE_MII; 1474 1475 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1476 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1477 if ((mii->mii_media_active & IFM_FDX) != 0) { 1478 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1479 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1480 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1481 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1482 } else 1483 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1484 1485 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1486 DELAY(40); 1487 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1488 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1489 } 1490 1491 /* 1492 * Update rx threshold levels to values in a particular slot 1493 * of the interrupt-mitigation table bge_rx_threshes. 1494 */ 1495 static void 1496 bge_set_thresh(struct ifnet *ifp, int lvl) 1497 { 1498 struct bge_softc *sc = ifp->if_softc; 1499 int s; 1500 1501 /* For now, just save the new Rx-intr thresholds and record 1502 * that a threshold update is pending. Updating the hardware 1503 * registers here (even at splhigh()) is observed to 1504 * occasionaly cause glitches where Rx-interrupts are not 1505 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1506 */ 1507 s = splnet(); 1508 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1509 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1510 sc->bge_pending_rxintr_change = 1; 1511 splx(s); 1512 } 1513 1514 1515 /* 1516 * Update Rx thresholds of all bge devices 1517 */ 1518 static void 1519 bge_update_all_threshes(int lvl) 1520 { 1521 struct ifnet *ifp; 1522 const char * const namebuf = "bge"; 1523 int namelen; 1524 1525 if (lvl < 0) 1526 lvl = 0; 1527 else if (lvl >= NBGE_RX_THRESH) 1528 lvl = NBGE_RX_THRESH - 1; 1529 1530 namelen = strlen(namebuf); 1531 /* 1532 * Now search all the interfaces for this name/number 1533 */ 1534 IFNET_FOREACH(ifp) { 1535 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1536 continue; 1537 /* We got a match: update if doing auto-threshold-tuning */ 1538 if (bge_auto_thresh) 1539 bge_set_thresh(ifp, lvl); 1540 } 1541 } 1542 1543 /* 1544 * Handle events that have triggered interrupts. 1545 */ 1546 static void 1547 bge_handle_events(struct bge_softc *sc) 1548 { 1549 1550 return; 1551 } 1552 1553 /* 1554 * Memory management for jumbo frames. 1555 */ 1556 1557 static int 1558 bge_alloc_jumbo_mem(struct bge_softc *sc) 1559 { 1560 char *ptr, *kva; 1561 bus_dma_segment_t seg; 1562 int i, rseg, state, error; 1563 struct bge_jpool_entry *entry; 1564 1565 state = error = 0; 1566 1567 /* Grab a big chunk o' storage. */ 1568 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1569 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1570 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1571 return ENOBUFS; 1572 } 1573 1574 state = 1; 1575 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1576 BUS_DMA_NOWAIT)) { 1577 aprint_error_dev(sc->bge_dev, 1578 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1579 error = ENOBUFS; 1580 goto out; 1581 } 1582 1583 state = 2; 1584 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1585 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1586 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1587 error = ENOBUFS; 1588 goto out; 1589 } 1590 1591 state = 3; 1592 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1593 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1594 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1595 error = ENOBUFS; 1596 goto out; 1597 } 1598 1599 state = 4; 1600 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1601 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1602 1603 SLIST_INIT(&sc->bge_jfree_listhead); 1604 SLIST_INIT(&sc->bge_jinuse_listhead); 1605 1606 /* 1607 * Now divide it up into 9K pieces and save the addresses 1608 * in an array. 1609 */ 1610 ptr = sc->bge_cdata.bge_jumbo_buf; 1611 for (i = 0; i < BGE_JSLOTS; i++) { 1612 sc->bge_cdata.bge_jslots[i] = ptr; 1613 ptr += BGE_JLEN; 1614 entry = malloc(sizeof(struct bge_jpool_entry), 1615 M_DEVBUF, M_NOWAIT); 1616 if (entry == NULL) { 1617 aprint_error_dev(sc->bge_dev, 1618 "no memory for jumbo buffer queue!\n"); 1619 error = ENOBUFS; 1620 goto out; 1621 } 1622 entry->slot = i; 1623 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1624 entry, jpool_entries); 1625 } 1626 out: 1627 if (error != 0) { 1628 switch (state) { 1629 case 4: 1630 bus_dmamap_unload(sc->bge_dmatag, 1631 sc->bge_cdata.bge_rx_jumbo_map); 1632 case 3: 1633 bus_dmamap_destroy(sc->bge_dmatag, 1634 sc->bge_cdata.bge_rx_jumbo_map); 1635 case 2: 1636 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1637 case 1: 1638 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1639 break; 1640 default: 1641 break; 1642 } 1643 } 1644 1645 return error; 1646 } 1647 1648 /* 1649 * Allocate a jumbo buffer. 1650 */ 1651 static void * 1652 bge_jalloc(struct bge_softc *sc) 1653 { 1654 struct bge_jpool_entry *entry; 1655 1656 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1657 1658 if (entry == NULL) { 1659 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1660 return NULL; 1661 } 1662 1663 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1664 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1665 return (sc->bge_cdata.bge_jslots[entry->slot]); 1666 } 1667 1668 /* 1669 * Release a jumbo buffer. 1670 */ 1671 static void 1672 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1673 { 1674 struct bge_jpool_entry *entry; 1675 struct bge_softc *sc; 1676 int i, s; 1677 1678 /* Extract the softc struct pointer. */ 1679 sc = (struct bge_softc *)arg; 1680 1681 if (sc == NULL) 1682 panic("bge_jfree: can't find softc pointer!"); 1683 1684 /* calculate the slot this buffer belongs to */ 1685 1686 i = ((char *)buf 1687 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1688 1689 if ((i < 0) || (i >= BGE_JSLOTS)) 1690 panic("bge_jfree: asked to free buffer that we don't manage!"); 1691 1692 s = splvm(); 1693 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1694 if (entry == NULL) 1695 panic("bge_jfree: buffer not in use!"); 1696 entry->slot = i; 1697 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1698 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1699 1700 if (__predict_true(m != NULL)) 1701 pool_cache_put(mb_cache, m); 1702 splx(s); 1703 } 1704 1705 1706 /* 1707 * Initialize a standard receive ring descriptor. 1708 */ 1709 static int 1710 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1711 bus_dmamap_t dmamap) 1712 { 1713 struct mbuf *m_new = NULL; 1714 struct bge_rx_bd *r; 1715 int error; 1716 1717 if (dmamap == NULL) { 1718 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1719 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1720 if (error != 0) 1721 return error; 1722 } 1723 1724 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1725 1726 if (m == NULL) { 1727 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1728 if (m_new == NULL) 1729 return ENOBUFS; 1730 1731 MCLGET(m_new, M_DONTWAIT); 1732 if (!(m_new->m_flags & M_EXT)) { 1733 m_freem(m_new); 1734 return ENOBUFS; 1735 } 1736 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1737 1738 } else { 1739 m_new = m; 1740 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1741 m_new->m_data = m_new->m_ext.ext_buf; 1742 } 1743 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1744 m_adj(m_new, ETHER_ALIGN); 1745 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1746 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1747 return ENOBUFS; 1748 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1749 BUS_DMASYNC_PREREAD); 1750 1751 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1752 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1753 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1754 r->bge_flags = BGE_RXBDFLAG_END; 1755 r->bge_len = m_new->m_len; 1756 r->bge_idx = i; 1757 1758 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1759 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1760 i * sizeof (struct bge_rx_bd), 1761 sizeof (struct bge_rx_bd), 1762 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1763 1764 return 0; 1765 } 1766 1767 /* 1768 * Initialize a jumbo receive ring descriptor. This allocates 1769 * a jumbo buffer from the pool managed internally by the driver. 1770 */ 1771 static int 1772 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1773 { 1774 struct mbuf *m_new = NULL; 1775 struct bge_rx_bd *r; 1776 void *buf = NULL; 1777 1778 if (m == NULL) { 1779 1780 /* Allocate the mbuf. */ 1781 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1782 if (m_new == NULL) 1783 return ENOBUFS; 1784 1785 /* Allocate the jumbo buffer */ 1786 buf = bge_jalloc(sc); 1787 if (buf == NULL) { 1788 m_freem(m_new); 1789 aprint_error_dev(sc->bge_dev, 1790 "jumbo allocation failed -- packet dropped!\n"); 1791 return ENOBUFS; 1792 } 1793 1794 /* Attach the buffer to the mbuf. */ 1795 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1796 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1797 bge_jfree, sc); 1798 m_new->m_flags |= M_EXT_RW; 1799 } else { 1800 m_new = m; 1801 buf = m_new->m_data = m_new->m_ext.ext_buf; 1802 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1803 } 1804 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1805 m_adj(m_new, ETHER_ALIGN); 1806 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1807 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1808 BUS_DMASYNC_PREREAD); 1809 /* Set up the descriptor. */ 1810 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1811 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1812 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1813 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1814 r->bge_len = m_new->m_len; 1815 r->bge_idx = i; 1816 1817 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1818 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1819 i * sizeof (struct bge_rx_bd), 1820 sizeof (struct bge_rx_bd), 1821 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1822 1823 return 0; 1824 } 1825 1826 /* 1827 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1828 * that's 1MB or memory, which is a lot. For now, we fill only the first 1829 * 256 ring entries and hope that our CPU is fast enough to keep up with 1830 * the NIC. 1831 */ 1832 static int 1833 bge_init_rx_ring_std(struct bge_softc *sc) 1834 { 1835 int i; 1836 1837 if (sc->bge_flags & BGE_RXRING_VALID) 1838 return 0; 1839 1840 for (i = 0; i < BGE_SSLOTS; i++) { 1841 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1842 return ENOBUFS; 1843 } 1844 1845 sc->bge_std = i - 1; 1846 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1847 1848 sc->bge_flags |= BGE_RXRING_VALID; 1849 1850 return 0; 1851 } 1852 1853 static void 1854 bge_free_rx_ring_std(struct bge_softc *sc) 1855 { 1856 int i; 1857 1858 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1859 return; 1860 1861 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1862 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1863 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1864 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1865 bus_dmamap_destroy(sc->bge_dmatag, 1866 sc->bge_cdata.bge_rx_std_map[i]); 1867 } 1868 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1869 sizeof(struct bge_rx_bd)); 1870 } 1871 1872 sc->bge_flags &= ~BGE_RXRING_VALID; 1873 } 1874 1875 static int 1876 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1877 { 1878 int i; 1879 volatile struct bge_rcb *rcb; 1880 1881 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1882 return 0; 1883 1884 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1885 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1886 return ENOBUFS; 1887 } 1888 1889 sc->bge_jumbo = i - 1; 1890 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1891 1892 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1893 rcb->bge_maxlen_flags = 0; 1894 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1895 1896 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1897 1898 return 0; 1899 } 1900 1901 static void 1902 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1903 { 1904 int i; 1905 1906 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1907 return; 1908 1909 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1910 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1911 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1912 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1913 } 1914 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1915 sizeof(struct bge_rx_bd)); 1916 } 1917 1918 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1919 } 1920 1921 static void 1922 bge_free_tx_ring(struct bge_softc *sc) 1923 { 1924 int i; 1925 struct txdmamap_pool_entry *dma; 1926 1927 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1928 return; 1929 1930 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1931 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1932 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1933 sc->bge_cdata.bge_tx_chain[i] = NULL; 1934 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1935 link); 1936 sc->txdma[i] = 0; 1937 } 1938 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1939 sizeof(struct bge_tx_bd)); 1940 } 1941 1942 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1943 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1944 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1945 free(dma, M_DEVBUF); 1946 } 1947 1948 sc->bge_flags &= ~BGE_TXRING_VALID; 1949 } 1950 1951 static int 1952 bge_init_tx_ring(struct bge_softc *sc) 1953 { 1954 int i; 1955 bus_dmamap_t dmamap; 1956 struct txdmamap_pool_entry *dma; 1957 1958 if (sc->bge_flags & BGE_TXRING_VALID) 1959 return 0; 1960 1961 sc->bge_txcnt = 0; 1962 sc->bge_tx_saved_considx = 0; 1963 1964 /* Initialize transmit producer index for host-memory send ring. */ 1965 sc->bge_tx_prodidx = 0; 1966 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1967 /* 5700 b2 errata */ 1968 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1969 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1970 1971 /* NIC-memory send ring not used; initialize to zero. */ 1972 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1973 /* 5700 b2 errata */ 1974 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1975 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1976 1977 SLIST_INIT(&sc->txdma_list); 1978 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1979 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1980 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1981 &dmamap)) 1982 return ENOBUFS; 1983 if (dmamap == NULL) 1984 panic("dmamap NULL in bge_init_tx_ring"); 1985 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1986 if (dma == NULL) { 1987 aprint_error_dev(sc->bge_dev, 1988 "can't alloc txdmamap_pool_entry\n"); 1989 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1990 return ENOMEM; 1991 } 1992 dma->dmamap = dmamap; 1993 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1994 } 1995 1996 sc->bge_flags |= BGE_TXRING_VALID; 1997 1998 return 0; 1999 } 2000 2001 static void 2002 bge_setmulti(struct bge_softc *sc) 2003 { 2004 struct ethercom *ac = &sc->ethercom; 2005 struct ifnet *ifp = &ac->ec_if; 2006 struct ether_multi *enm; 2007 struct ether_multistep step; 2008 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2009 uint32_t h; 2010 int i; 2011 2012 if (ifp->if_flags & IFF_PROMISC) 2013 goto allmulti; 2014 2015 /* Now program new ones. */ 2016 ETHER_FIRST_MULTI(step, ac, enm); 2017 while (enm != NULL) { 2018 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2019 /* 2020 * We must listen to a range of multicast addresses. 2021 * For now, just accept all multicasts, rather than 2022 * trying to set only those filter bits needed to match 2023 * the range. (At this time, the only use of address 2024 * ranges is for IP multicast routing, for which the 2025 * range is big enough to require all bits set.) 2026 */ 2027 goto allmulti; 2028 } 2029 2030 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2031 2032 /* Just want the 7 least-significant bits. */ 2033 h &= 0x7f; 2034 2035 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2036 ETHER_NEXT_MULTI(step, enm); 2037 } 2038 2039 ifp->if_flags &= ~IFF_ALLMULTI; 2040 goto setit; 2041 2042 allmulti: 2043 ifp->if_flags |= IFF_ALLMULTI; 2044 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2045 2046 setit: 2047 for (i = 0; i < 4; i++) 2048 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2049 } 2050 2051 static void 2052 bge_sig_pre_reset(struct bge_softc *sc, int type) 2053 { 2054 2055 /* 2056 * Some chips don't like this so only do this if ASF is enabled 2057 */ 2058 if (sc->bge_asf_mode) 2059 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2060 2061 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2062 switch (type) { 2063 case BGE_RESET_START: 2064 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2065 BGE_FW_DRV_STATE_START); 2066 break; 2067 case BGE_RESET_SHUTDOWN: 2068 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2069 BGE_FW_DRV_STATE_UNLOAD); 2070 break; 2071 case BGE_RESET_SUSPEND: 2072 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2073 BGE_FW_DRV_STATE_SUSPEND); 2074 break; 2075 } 2076 } 2077 2078 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2079 bge_ape_driver_state_change(sc, type); 2080 } 2081 2082 static void 2083 bge_sig_post_reset(struct bge_softc *sc, int type) 2084 { 2085 2086 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2087 switch (type) { 2088 case BGE_RESET_START: 2089 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2090 BGE_FW_DRV_STATE_START_DONE); 2091 /* START DONE */ 2092 break; 2093 case BGE_RESET_SHUTDOWN: 2094 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2095 BGE_FW_DRV_STATE_UNLOAD_DONE); 2096 break; 2097 } 2098 } 2099 2100 if (type == BGE_RESET_SHUTDOWN) 2101 bge_ape_driver_state_change(sc, type); 2102 } 2103 2104 static void 2105 bge_sig_legacy(struct bge_softc *sc, int type) 2106 { 2107 2108 if (sc->bge_asf_mode) { 2109 switch (type) { 2110 case BGE_RESET_START: 2111 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2112 BGE_FW_DRV_STATE_START); 2113 break; 2114 case BGE_RESET_SHUTDOWN: 2115 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2116 BGE_FW_DRV_STATE_UNLOAD); 2117 break; 2118 } 2119 } 2120 } 2121 2122 static void 2123 bge_wait_for_event_ack(struct bge_softc *sc) 2124 { 2125 int i; 2126 2127 /* wait up to 2500usec */ 2128 for (i = 0; i < 250; i++) { 2129 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2130 BGE_RX_CPU_DRV_EVENT)) 2131 break; 2132 DELAY(10); 2133 } 2134 } 2135 2136 static void 2137 bge_stop_fw(struct bge_softc *sc) 2138 { 2139 2140 if (sc->bge_asf_mode) { 2141 bge_wait_for_event_ack(sc); 2142 2143 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2144 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2145 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2146 2147 bge_wait_for_event_ack(sc); 2148 } 2149 } 2150 2151 static int 2152 bge_poll_fw(struct bge_softc *sc) 2153 { 2154 uint32_t val; 2155 int i; 2156 2157 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2158 for (i = 0; i < BGE_TIMEOUT; i++) { 2159 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2160 if (val & BGE_VCPU_STATUS_INIT_DONE) 2161 break; 2162 DELAY(100); 2163 } 2164 if (i >= BGE_TIMEOUT) { 2165 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2166 return -1; 2167 } 2168 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2169 /* 2170 * Poll the value location we just wrote until 2171 * we see the 1's complement of the magic number. 2172 * This indicates that the firmware initialization 2173 * is complete. 2174 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2175 */ 2176 for (i = 0; i < BGE_TIMEOUT; i++) { 2177 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2178 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2179 break; 2180 DELAY(10); 2181 } 2182 2183 if (i >= BGE_TIMEOUT) { 2184 aprint_error_dev(sc->bge_dev, 2185 "firmware handshake timed out, val = %x\n", val); 2186 return -1; 2187 } 2188 } 2189 2190 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2191 /* tg3 says we have to wait extra time */ 2192 delay(10 * 1000); 2193 } 2194 2195 return 0; 2196 } 2197 2198 int 2199 bge_phy_addr(struct bge_softc *sc) 2200 { 2201 struct pci_attach_args *pa = &(sc->bge_pa); 2202 int phy_addr = 1; 2203 2204 /* 2205 * PHY address mapping for various devices. 2206 * 2207 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2208 * ---------+-------+-------+-------+-------+ 2209 * BCM57XX | 1 | X | X | X | 2210 * BCM5704 | 1 | X | 1 | X | 2211 * BCM5717 | 1 | 8 | 2 | 9 | 2212 * BCM5719 | 1 | 8 | 2 | 9 | 2213 * BCM5720 | 1 | 8 | 2 | 9 | 2214 * 2215 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2216 * ---------+-------+-------+-------+-------+ 2217 * BCM57XX | X | X | X | X | 2218 * BCM5704 | X | X | X | X | 2219 * BCM5717 | X | X | X | X | 2220 * BCM5719 | 3 | 10 | 4 | 11 | 2221 * BCM5720 | X | X | X | X | 2222 * 2223 * Other addresses may respond but they are not 2224 * IEEE compliant PHYs and should be ignored. 2225 */ 2226 switch (BGE_ASICREV(sc->bge_chipid)) { 2227 case BGE_ASICREV_BCM5717: 2228 case BGE_ASICREV_BCM5719: 2229 case BGE_ASICREV_BCM5720: 2230 phy_addr = pa->pa_function; 2231 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2232 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2233 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2234 } else { 2235 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2236 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2237 } 2238 } 2239 2240 return phy_addr; 2241 } 2242 2243 /* 2244 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2245 * self-test results. 2246 */ 2247 static int 2248 bge_chipinit(struct bge_softc *sc) 2249 { 2250 uint32_t dma_rw_ctl, mode_ctl, reg; 2251 int i; 2252 2253 /* Set endianness before we access any non-PCI registers. */ 2254 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2255 BGE_INIT); 2256 2257 /* 2258 * Clear the MAC statistics block in the NIC's 2259 * internal memory. 2260 */ 2261 for (i = BGE_STATS_BLOCK; 2262 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2263 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2264 2265 for (i = BGE_STATUS_BLOCK; 2266 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2267 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2268 2269 /* 5717 workaround from tg3 */ 2270 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2271 /* Save */ 2272 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2273 2274 /* Temporary modify MODE_CTL to control TLP */ 2275 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2276 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2277 2278 /* Control TLP */ 2279 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2280 BGE_TLP_PHYCTL1); 2281 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2282 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2283 2284 /* Restore */ 2285 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2286 } 2287 2288 /* XXX Should we use 57765_FAMILY? */ 2289 if (BGE_IS_57765_PLUS(sc)) { 2290 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2291 /* Save */ 2292 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2293 2294 /* Temporary modify MODE_CTL to control TLP */ 2295 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, 2297 reg | BGE_MODECTL_PCIE_TLPADDR1); 2298 2299 /* Control TLP */ 2300 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2301 BGE_TLP_PHYCTL5); 2302 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2303 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2304 2305 /* Restore */ 2306 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2307 } 2308 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2309 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2310 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2311 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2312 2313 /* Save */ 2314 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2315 2316 /* Temporary modify MODE_CTL to control TLP */ 2317 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2318 CSR_WRITE_4(sc, BGE_MODE_CTL, 2319 reg | BGE_MODECTL_PCIE_TLPADDR0); 2320 2321 /* Control TLP */ 2322 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2323 BGE_TLP_FTSMAX); 2324 reg &= ~BGE_TLP_FTSMAX_MSK; 2325 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2326 reg | BGE_TLP_FTSMAX_VAL); 2327 2328 /* Restore */ 2329 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2330 } 2331 2332 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2333 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2334 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2335 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2336 } 2337 2338 /* Set up the PCI DMA control register. */ 2339 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2340 if (sc->bge_flags & BGE_PCIE) { 2341 /* Read watermark not used, 128 bytes for write. */ 2342 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2343 device_xname(sc->bge_dev))); 2344 if (sc->bge_mps >= 256) 2345 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2346 else 2347 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2348 } else if (sc->bge_flags & BGE_PCIX) { 2349 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2350 device_xname(sc->bge_dev))); 2351 /* PCI-X bus */ 2352 if (BGE_IS_5714_FAMILY(sc)) { 2353 /* 256 bytes for read and write. */ 2354 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2355 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2356 2357 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2358 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2359 else 2360 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2361 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2362 /* 1536 bytes for read, 384 bytes for write. */ 2363 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2364 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2365 } else { 2366 /* 384 bytes for read and write. */ 2367 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2368 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2369 (0x0F); 2370 } 2371 2372 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2373 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2374 uint32_t tmp; 2375 2376 /* Set ONEDMA_ATONCE for hardware workaround. */ 2377 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2378 if (tmp == 6 || tmp == 7) 2379 dma_rw_ctl |= 2380 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2381 2382 /* Set PCI-X DMA write workaround. */ 2383 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2384 } 2385 } else { 2386 /* Conventional PCI bus: 256 bytes for read and write. */ 2387 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2388 device_xname(sc->bge_dev))); 2389 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2390 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2391 2392 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2393 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2394 dma_rw_ctl |= 0x0F; 2395 } 2396 2397 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2398 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2399 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2400 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2401 2402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2403 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2404 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2405 2406 if (BGE_IS_5717_PLUS(sc)) { 2407 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2408 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2409 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2410 2411 /* 2412 * Enable HW workaround for controllers that misinterpret 2413 * a status tag update and leave interrupts permanently 2414 * disabled. 2415 */ 2416 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2417 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) 2418 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2419 } 2420 2421 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2422 dma_rw_ctl); 2423 2424 /* 2425 * Set up general mode register. 2426 */ 2427 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2428 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2429 /* Retain Host-2-BMC settings written by APE firmware. */ 2430 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2431 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2432 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2433 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2434 } 2435 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2436 BGE_MODECTL_TX_NO_PHDR_CSUM; 2437 2438 /* 2439 * BCM5701 B5 have a bug causing data corruption when using 2440 * 64-bit DMA reads, which can be terminated early and then 2441 * completed later as 32-bit accesses, in combination with 2442 * certain bridges. 2443 */ 2444 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2445 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2446 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2447 2448 /* 2449 * Tell the firmware the driver is running 2450 */ 2451 if (sc->bge_asf_mode & ASF_STACKUP) 2452 mode_ctl |= BGE_MODECTL_STACKUP; 2453 2454 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2455 2456 /* 2457 * Disable memory write invalidate. Apparently it is not supported 2458 * properly by these devices. 2459 */ 2460 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2461 PCI_COMMAND_INVALIDATE_ENABLE); 2462 2463 #ifdef __brokenalpha__ 2464 /* 2465 * Must insure that we do not cross an 8K (bytes) boundary 2466 * for DMA reads. Our highest limit is 1K bytes. This is a 2467 * restriction on some ALPHA platforms with early revision 2468 * 21174 PCI chipsets, such as the AlphaPC 164lx 2469 */ 2470 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2471 #endif 2472 2473 /* Set the timer prescaler (always 66MHz) */ 2474 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2475 2476 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2477 DELAY(40); /* XXX */ 2478 2479 /* Put PHY into ready state */ 2480 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2481 DELAY(40); 2482 } 2483 2484 return 0; 2485 } 2486 2487 static int 2488 bge_blockinit(struct bge_softc *sc) 2489 { 2490 volatile struct bge_rcb *rcb; 2491 bus_size_t rcb_addr; 2492 struct ifnet *ifp = &sc->ethercom.ec_if; 2493 bge_hostaddr taddr; 2494 uint32_t dmactl, val; 2495 int i, limit; 2496 2497 /* 2498 * Initialize the memory window pointer register so that 2499 * we can access the first 32K of internal NIC RAM. This will 2500 * allow us to set up the TX send ring RCBs and the RX return 2501 * ring RCBs, plus other things which live in NIC memory. 2502 */ 2503 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2504 2505 if (!BGE_IS_5705_PLUS(sc)) { 2506 /* 57XX step 33 */ 2507 /* Configure mbuf memory pool */ 2508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2509 BGE_BUFFPOOL_1); 2510 2511 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2513 else 2514 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2515 2516 /* 57XX step 34 */ 2517 /* Configure DMA resource pool */ 2518 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2519 BGE_DMA_DESCRIPTORS); 2520 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2521 } 2522 2523 /* 5718 step 11, 57XX step 35 */ 2524 /* 2525 * Configure mbuf pool watermarks. New broadcom docs strongly 2526 * recommend these. 2527 */ 2528 if (BGE_IS_5717_PLUS(sc)) { 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2530 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2531 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2532 } else if (BGE_IS_5705_PLUS(sc)) { 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2534 2535 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2536 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2537 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2538 } else { 2539 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2540 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2541 } 2542 } else { 2543 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2544 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2545 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2546 } 2547 2548 /* 57XX step 36 */ 2549 /* Configure DMA resource watermarks */ 2550 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2551 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2552 2553 /* 5718 step 13, 57XX step 38 */ 2554 /* Enable buffer manager */ 2555 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2556 /* 2557 * Change the arbitration algorithm of TXMBUF read request to 2558 * round-robin instead of priority based for BCM5719. When 2559 * TXFIFO is almost empty, RDMA will hold its request until 2560 * TXFIFO is not almost empty. 2561 */ 2562 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2563 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2564 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2565 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2566 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2567 val |= BGE_BMANMODE_LOMBUF_ATTN; 2568 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2569 2570 /* 57XX step 39 */ 2571 /* Poll for buffer manager start indication */ 2572 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2573 DELAY(10); 2574 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2575 break; 2576 } 2577 2578 if (i == BGE_TIMEOUT * 2) { 2579 aprint_error_dev(sc->bge_dev, 2580 "buffer manager failed to start\n"); 2581 return ENXIO; 2582 } 2583 2584 /* 57XX step 40 */ 2585 /* Enable flow-through queues */ 2586 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2587 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2588 2589 /* Wait until queue initialization is complete */ 2590 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2591 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2592 break; 2593 DELAY(10); 2594 } 2595 2596 if (i == BGE_TIMEOUT * 2) { 2597 aprint_error_dev(sc->bge_dev, 2598 "flow-through queue init failed\n"); 2599 return ENXIO; 2600 } 2601 2602 /* 2603 * Summary of rings supported by the controller: 2604 * 2605 * Standard Receive Producer Ring 2606 * - This ring is used to feed receive buffers for "standard" 2607 * sized frames (typically 1536 bytes) to the controller. 2608 * 2609 * Jumbo Receive Producer Ring 2610 * - This ring is used to feed receive buffers for jumbo sized 2611 * frames (i.e. anything bigger than the "standard" frames) 2612 * to the controller. 2613 * 2614 * Mini Receive Producer Ring 2615 * - This ring is used to feed receive buffers for "mini" 2616 * sized frames to the controller. 2617 * - This feature required external memory for the controller 2618 * but was never used in a production system. Should always 2619 * be disabled. 2620 * 2621 * Receive Return Ring 2622 * - After the controller has placed an incoming frame into a 2623 * receive buffer that buffer is moved into a receive return 2624 * ring. The driver is then responsible to passing the 2625 * buffer up to the stack. Many versions of the controller 2626 * support multiple RR rings. 2627 * 2628 * Send Ring 2629 * - This ring is used for outgoing frames. Many versions of 2630 * the controller support multiple send rings. 2631 */ 2632 2633 /* 5718 step 15, 57XX step 41 */ 2634 /* Initialize the standard RX ring control block */ 2635 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2636 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2637 /* 5718 step 16 */ 2638 if (BGE_IS_5717_PLUS(sc)) { 2639 /* 2640 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2641 * Bits 15-2 : Maximum RX frame size 2642 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2643 * Bit 0 : Reserved 2644 */ 2645 rcb->bge_maxlen_flags = 2646 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2647 } else if (BGE_IS_5705_PLUS(sc)) { 2648 /* 2649 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2650 * Bits 15-2 : Reserved (should be 0) 2651 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2652 * Bit 0 : Reserved 2653 */ 2654 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2655 } else { 2656 /* 2657 * Ring size is always XXX entries 2658 * Bits 31-16: Maximum RX frame size 2659 * Bits 15-2 : Reserved (should be 0) 2660 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2661 * Bit 0 : Reserved 2662 */ 2663 rcb->bge_maxlen_flags = 2664 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2665 } 2666 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2667 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2668 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2669 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2670 else 2671 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2672 /* Write the standard receive producer ring control block. */ 2673 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2674 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2675 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2676 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2677 2678 /* Reset the standard receive producer ring producer index. */ 2679 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2680 2681 /* 57XX step 42 */ 2682 /* 2683 * Initialize the jumbo RX ring control block 2684 * We set the 'ring disabled' bit in the flags 2685 * field until we're actually ready to start 2686 * using this ring (i.e. once we set the MTU 2687 * high enough to require it). 2688 */ 2689 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2690 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2691 BGE_HOSTADDR(rcb->bge_hostaddr, 2692 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2693 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2694 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2695 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2696 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2697 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2698 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2699 else 2700 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2701 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2702 rcb->bge_hostaddr.bge_addr_hi); 2703 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2704 rcb->bge_hostaddr.bge_addr_lo); 2705 /* Program the jumbo receive producer ring RCB parameters. */ 2706 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2707 rcb->bge_maxlen_flags); 2708 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2709 /* Reset the jumbo receive producer ring producer index. */ 2710 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2711 } 2712 2713 /* 57XX step 43 */ 2714 /* Disable the mini receive producer ring RCB. */ 2715 if (BGE_IS_5700_FAMILY(sc)) { 2716 /* Set up dummy disabled mini ring RCB */ 2717 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2718 rcb->bge_maxlen_flags = 2719 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2720 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2721 rcb->bge_maxlen_flags); 2722 /* Reset the mini receive producer ring producer index. */ 2723 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2724 2725 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2726 offsetof(struct bge_ring_data, bge_info), 2727 sizeof (struct bge_gib), 2728 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2729 } 2730 2731 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2732 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2733 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2734 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2735 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2736 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2737 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2738 } 2739 /* 5718 step 14, 57XX step 44 */ 2740 /* 2741 * The BD ring replenish thresholds control how often the 2742 * hardware fetches new BD's from the producer rings in host 2743 * memory. Setting the value too low on a busy system can 2744 * starve the hardware and recue the throughpout. 2745 * 2746 * Set the BD ring replenish thresholds. The recommended 2747 * values are 1/8th the number of descriptors allocated to 2748 * each ring, but since we try to avoid filling the entire 2749 * ring we set these to the minimal value of 8. This needs to 2750 * be done on several of the supported chip revisions anyway, 2751 * to work around HW bugs. 2752 */ 2753 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2754 if (BGE_IS_JUMBO_CAPABLE(sc)) 2755 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2756 2757 /* 5718 step 18 */ 2758 if (BGE_IS_5717_PLUS(sc)) { 2759 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2760 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2761 } 2762 2763 /* 57XX step 45 */ 2764 /* 2765 * Disable all send rings by setting the 'ring disabled' bit 2766 * in the flags field of all the TX send ring control blocks, 2767 * located in NIC memory. 2768 */ 2769 if (BGE_IS_5700_FAMILY(sc)) { 2770 /* 5700 to 5704 had 16 send rings. */ 2771 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2772 } else 2773 limit = 1; 2774 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2775 for (i = 0; i < limit; i++) { 2776 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2777 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2778 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2779 rcb_addr += sizeof(struct bge_rcb); 2780 } 2781 2782 /* 57XX step 46 and 47 */ 2783 /* Configure send ring RCB 0 (we use only the first ring) */ 2784 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2785 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2786 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2787 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2788 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2789 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2790 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2791 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2792 else 2793 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2794 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2795 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2796 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2797 2798 /* 57XX step 48 */ 2799 /* 2800 * Disable all receive return rings by setting the 2801 * 'ring diabled' bit in the flags field of all the receive 2802 * return ring control blocks, located in NIC memory. 2803 */ 2804 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2805 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2806 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2807 /* Should be 17, use 16 until we get an SRAM map. */ 2808 limit = 16; 2809 } else if (BGE_IS_5700_FAMILY(sc)) 2810 limit = BGE_RX_RINGS_MAX; 2811 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2812 BGE_IS_57765_PLUS(sc)) 2813 limit = 4; 2814 else 2815 limit = 1; 2816 /* Disable all receive return rings */ 2817 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2818 for (i = 0; i < limit; i++) { 2819 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2820 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2821 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2822 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2823 BGE_RCB_FLAG_RING_DISABLED)); 2824 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2825 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2826 (i * (sizeof(uint64_t))), 0); 2827 rcb_addr += sizeof(struct bge_rcb); 2828 } 2829 2830 /* 57XX step 49 */ 2831 /* 2832 * Set up receive return ring 0. Note that the NIC address 2833 * for RX return rings is 0x0. The return rings live entirely 2834 * within the host, so the nicaddr field in the RCB isn't used. 2835 */ 2836 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2837 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2838 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2839 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2840 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2841 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2842 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2843 2844 /* 5718 step 24, 57XX step 53 */ 2845 /* Set random backoff seed for TX */ 2846 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2847 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2848 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2849 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2850 BGE_TX_BACKOFF_SEED_MASK); 2851 2852 /* 5718 step 26, 57XX step 55 */ 2853 /* Set inter-packet gap */ 2854 val = 0x2620; 2855 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2856 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2857 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2858 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2859 2860 /* 5718 step 27, 57XX step 56 */ 2861 /* 2862 * Specify which ring to use for packets that don't match 2863 * any RX rules. 2864 */ 2865 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2866 2867 /* 5718 step 28, 57XX step 57 */ 2868 /* 2869 * Configure number of RX lists. One interrupt distribution 2870 * list, sixteen active lists, one bad frames class. 2871 */ 2872 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2873 2874 /* 5718 step 29, 57XX step 58 */ 2875 /* Inialize RX list placement stats mask. */ 2876 if (BGE_IS_575X_PLUS(sc)) { 2877 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2878 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2879 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2880 } else 2881 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2882 2883 /* 5718 step 30, 57XX step 59 */ 2884 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2885 2886 /* 5718 step 33, 57XX step 62 */ 2887 /* Disable host coalescing until we get it set up */ 2888 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2889 2890 /* 5718 step 34, 57XX step 63 */ 2891 /* Poll to make sure it's shut down. */ 2892 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2893 DELAY(10); 2894 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2895 break; 2896 } 2897 2898 if (i == BGE_TIMEOUT * 2) { 2899 aprint_error_dev(sc->bge_dev, 2900 "host coalescing engine failed to idle\n"); 2901 return ENXIO; 2902 } 2903 2904 /* 5718 step 35, 36, 37 */ 2905 /* Set up host coalescing defaults */ 2906 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2907 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2908 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2909 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2910 if (!(BGE_IS_5705_PLUS(sc))) { 2911 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2912 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2913 } 2914 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2915 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2916 2917 /* Set up address of statistics block */ 2918 if (BGE_IS_5700_FAMILY(sc)) { 2919 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2920 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2921 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2922 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2923 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2924 } 2925 2926 /* 5718 step 38 */ 2927 /* Set up address of status block */ 2928 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2929 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2930 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2931 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2932 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2933 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2934 2935 /* Set up status block size. */ 2936 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2937 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2938 val = BGE_STATBLKSZ_FULL; 2939 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2940 } else { 2941 val = BGE_STATBLKSZ_32BYTE; 2942 bzero(&sc->bge_rdata->bge_status_block, 32); 2943 } 2944 2945 /* 5718 step 39, 57XX step 73 */ 2946 /* Turn on host coalescing state machine */ 2947 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2948 2949 /* 5718 step 40, 57XX step 74 */ 2950 /* Turn on RX BD completion state machine and enable attentions */ 2951 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2952 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2953 2954 /* 5718 step 41, 57XX step 75 */ 2955 /* Turn on RX list placement state machine */ 2956 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2957 2958 /* 57XX step 76 */ 2959 /* Turn on RX list selector state machine. */ 2960 if (!(BGE_IS_5705_PLUS(sc))) 2961 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2962 2963 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2964 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2965 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2966 BGE_MACMODE_FRMHDR_DMA_ENB; 2967 2968 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2969 val |= BGE_PORTMODE_TBI; 2970 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2971 val |= BGE_PORTMODE_GMII; 2972 else 2973 val |= BGE_PORTMODE_MII; 2974 2975 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2976 /* Allow APE to send/receive frames. */ 2977 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2978 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2979 2980 /* Turn on DMA, clear stats */ 2981 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2982 /* 5718 step 44 */ 2983 DELAY(40); 2984 2985 /* 5718 step 45, 57XX step 79 */ 2986 /* Set misc. local control, enable interrupts on attentions */ 2987 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2988 if (BGE_IS_5717_PLUS(sc)) { 2989 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2990 /* 5718 step 46 */ 2991 DELAY(100); 2992 } 2993 2994 /* 57XX step 81 */ 2995 /* Turn on DMA completion state machine */ 2996 if (!(BGE_IS_5705_PLUS(sc))) 2997 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2998 2999 /* 5718 step 47, 57XX step 82 */ 3000 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3001 3002 /* 5718 step 48 */ 3003 /* Enable host coalescing bug fix. */ 3004 if (BGE_IS_5755_PLUS(sc)) 3005 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3006 3007 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3008 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3009 3010 /* Turn on write DMA state machine */ 3011 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3012 /* 5718 step 49 */ 3013 DELAY(40); 3014 3015 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3016 3017 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3018 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3019 3020 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3021 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3022 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3023 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3024 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3025 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3026 3027 if (sc->bge_flags & BGE_PCIE) 3028 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3029 if (sc->bge_flags & BGE_TSO) 3030 val |= BGE_RDMAMODE_TSO4_ENABLE; 3031 3032 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3033 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3034 BGE_RDMAMODE_H2BNC_VLAN_DET; 3035 /* 3036 * Allow multiple outstanding read requests from 3037 * non-LSO read DMA engine. 3038 */ 3039 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3040 } 3041 3042 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3043 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3044 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3045 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3046 BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ 3047 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3048 /* 3049 * Adjust tx margin to prevent TX data corruption and 3050 * fix internal FIFO overflow. 3051 */ 3052 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3053 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3054 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3055 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3056 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3057 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3058 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3059 } 3060 /* 3061 * Enable fix for read DMA FIFO overruns. 3062 * The fix is to limit the number of RX BDs 3063 * the hardware would fetch at a fime. 3064 */ 3065 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3066 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3067 } 3068 3069 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3070 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3071 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3072 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3073 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3074 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3075 /* 3076 * Allow 4KB burst length reads for non-LSO frames. 3077 * Enable 512B burst length reads for buffer descriptors. 3078 */ 3079 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3080 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3081 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3082 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3083 } 3084 3085 /* Turn on read DMA state machine */ 3086 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3087 /* 5718 step 52 */ 3088 delay(40); 3089 3090 /* 5718 step 56, 57XX step 84 */ 3091 /* Turn on RX data completion state machine */ 3092 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3093 3094 /* Turn on RX data and RX BD initiator state machine */ 3095 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3096 3097 /* 57XX step 85 */ 3098 /* Turn on Mbuf cluster free state machine */ 3099 if (!BGE_IS_5705_PLUS(sc)) 3100 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3101 3102 /* 5718 step 57, 57XX step 86 */ 3103 /* Turn on send data completion state machine */ 3104 val = BGE_SDCMODE_ENABLE; 3105 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3106 val |= BGE_SDCMODE_CDELAY; 3107 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3108 3109 /* 5718 step 58 */ 3110 /* Turn on send BD completion state machine */ 3111 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3112 3113 /* 57XX step 88 */ 3114 /* Turn on RX BD initiator state machine */ 3115 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3116 3117 /* 5718 step 60, 57XX step 90 */ 3118 /* Turn on send data initiator state machine */ 3119 if (sc->bge_flags & BGE_TSO) { 3120 /* XXX: magic value from Linux driver */ 3121 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3122 BGE_SDIMODE_HW_LSO_PRE_DMA); 3123 } else 3124 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3125 3126 /* 5718 step 61, 57XX step 91 */ 3127 /* Turn on send BD initiator state machine */ 3128 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3129 3130 /* 5718 step 62, 57XX step 92 */ 3131 /* Turn on send BD selector state machine */ 3132 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3133 3134 /* 5718 step 31, 57XX step 60 */ 3135 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3136 /* 5718 step 32, 57XX step 61 */ 3137 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3138 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3139 3140 /* ack/clear link change events */ 3141 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3142 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3143 BGE_MACSTAT_LINK_CHANGED); 3144 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3145 3146 /* 3147 * Enable attention when the link has changed state for 3148 * devices that use auto polling. 3149 */ 3150 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3151 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3152 } else { 3153 /* 5718 step 68 */ 3154 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3155 /* 5718 step 69 (optionally) */ 3156 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3157 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3158 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3159 BGE_EVTENB_MI_INTERRUPT); 3160 } 3161 3162 /* 3163 * Clear any pending link state attention. 3164 * Otherwise some link state change events may be lost until attention 3165 * is cleared by bge_intr() -> bge_link_upd() sequence. 3166 * It's not necessary on newer BCM chips - perhaps enabling link 3167 * state change attentions implies clearing pending attention. 3168 */ 3169 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3170 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3171 BGE_MACSTAT_LINK_CHANGED); 3172 3173 /* Enable link state change attentions. */ 3174 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3175 3176 return 0; 3177 } 3178 3179 static const struct bge_revision * 3180 bge_lookup_rev(uint32_t chipid) 3181 { 3182 const struct bge_revision *br; 3183 3184 for (br = bge_revisions; br->br_name != NULL; br++) { 3185 if (br->br_chipid == chipid) 3186 return br; 3187 } 3188 3189 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3190 if (br->br_chipid == BGE_ASICREV(chipid)) 3191 return br; 3192 } 3193 3194 return NULL; 3195 } 3196 3197 static const struct bge_product * 3198 bge_lookup(const struct pci_attach_args *pa) 3199 { 3200 const struct bge_product *bp; 3201 3202 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3203 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3204 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3205 return bp; 3206 } 3207 3208 return NULL; 3209 } 3210 3211 static uint32_t 3212 bge_chipid(const struct pci_attach_args *pa) 3213 { 3214 uint32_t id; 3215 3216 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3217 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3218 3219 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3220 switch (PCI_PRODUCT(pa->pa_id)) { 3221 case PCI_PRODUCT_BROADCOM_BCM5717: 3222 case PCI_PRODUCT_BROADCOM_BCM5718: 3223 case PCI_PRODUCT_BROADCOM_BCM5719: 3224 case PCI_PRODUCT_BROADCOM_BCM5720: 3225 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3226 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3227 BGE_PCI_GEN2_PRODID_ASICREV); 3228 break; 3229 case PCI_PRODUCT_BROADCOM_BCM57761: 3230 case PCI_PRODUCT_BROADCOM_BCM57762: 3231 case PCI_PRODUCT_BROADCOM_BCM57765: 3232 case PCI_PRODUCT_BROADCOM_BCM57766: 3233 case PCI_PRODUCT_BROADCOM_BCM57781: 3234 case PCI_PRODUCT_BROADCOM_BCM57785: 3235 case PCI_PRODUCT_BROADCOM_BCM57791: 3236 case PCI_PRODUCT_BROADCOM_BCM57795: 3237 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3238 BGE_PCI_GEN15_PRODID_ASICREV); 3239 break; 3240 default: 3241 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3242 BGE_PCI_PRODID_ASICREV); 3243 break; 3244 } 3245 } 3246 3247 return id; 3248 } 3249 3250 /* 3251 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3252 * against our list and return its name if we find a match. Note 3253 * that since the Broadcom controller contains VPD support, we 3254 * can get the device name string from the controller itself instead 3255 * of the compiled-in string. This is a little slow, but it guarantees 3256 * we'll always announce the right product name. 3257 */ 3258 static int 3259 bge_probe(device_t parent, cfdata_t match, void *aux) 3260 { 3261 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3262 3263 if (bge_lookup(pa) != NULL) 3264 return 1; 3265 3266 return 0; 3267 } 3268 3269 static void 3270 bge_attach(device_t parent, device_t self, void *aux) 3271 { 3272 struct bge_softc *sc = device_private(self); 3273 struct pci_attach_args *pa = aux; 3274 prop_dictionary_t dict; 3275 const struct bge_product *bp; 3276 const struct bge_revision *br; 3277 pci_chipset_tag_t pc; 3278 pci_intr_handle_t ih; 3279 const char *intrstr = NULL; 3280 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4; 3281 uint32_t command; 3282 struct ifnet *ifp; 3283 uint32_t misccfg, mimode; 3284 void * kva; 3285 u_char eaddr[ETHER_ADDR_LEN]; 3286 pcireg_t memtype, subid, reg; 3287 bus_addr_t memaddr; 3288 uint32_t pm_ctl; 3289 bool no_seeprom; 3290 int capmask; 3291 3292 bp = bge_lookup(pa); 3293 KASSERT(bp != NULL); 3294 3295 sc->sc_pc = pa->pa_pc; 3296 sc->sc_pcitag = pa->pa_tag; 3297 sc->bge_dev = self; 3298 3299 sc->bge_pa = *pa; 3300 pc = sc->sc_pc; 3301 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3302 3303 aprint_naive(": Ethernet controller\n"); 3304 aprint_normal(": %s\n", bp->bp_name); 3305 3306 /* 3307 * Map control/status registers. 3308 */ 3309 DPRINTFN(5, ("Map control/status regs\n")); 3310 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3311 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3312 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3313 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3314 3315 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3316 aprint_error_dev(sc->bge_dev, 3317 "failed to enable memory mapping!\n"); 3318 return; 3319 } 3320 3321 DPRINTFN(5, ("pci_mem_find\n")); 3322 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3323 switch (memtype) { 3324 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3325 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3326 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3327 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3328 &memaddr, &sc->bge_bsize) == 0) 3329 break; 3330 default: 3331 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3332 return; 3333 } 3334 3335 DPRINTFN(5, ("pci_intr_map\n")); 3336 if (pci_intr_map(pa, &ih)) { 3337 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3338 return; 3339 } 3340 3341 DPRINTFN(5, ("pci_intr_string\n")); 3342 intrstr = pci_intr_string(pc, ih); 3343 3344 DPRINTFN(5, ("pci_intr_establish\n")); 3345 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3346 3347 if (sc->bge_intrhand == NULL) { 3348 aprint_error_dev(sc->bge_dev, 3349 "couldn't establish interrupt%s%s\n", 3350 intrstr ? " at " : "", intrstr ? intrstr : ""); 3351 return; 3352 } 3353 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3354 3355 /* Save various chip information. */ 3356 sc->bge_chipid = bge_chipid(pa); 3357 sc->bge_phy_addr = bge_phy_addr(sc); 3358 3359 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3360 &sc->bge_pciecap, NULL) != 0) 3361 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3362 /* PCIe */ 3363 sc->bge_flags |= BGE_PCIE; 3364 /* Extract supported maximum payload size. */ 3365 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3366 sc->bge_pciecap + PCIE_DCAP); 3367 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3369 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3370 sc->bge_expmrq = 2048; 3371 else 3372 sc->bge_expmrq = 4096; 3373 bge_set_max_readrq(sc); 3374 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3375 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3376 /* PCI-X */ 3377 sc->bge_flags |= BGE_PCIX; 3378 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3379 &sc->bge_pcixcap, NULL) == 0) 3380 aprint_error_dev(sc->bge_dev, 3381 "unable to find PCIX capability\n"); 3382 } 3383 3384 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3385 /* 3386 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3387 * can clobber the chip's PCI config-space power control 3388 * registers, leaving the card in D3 powersave state. We do 3389 * not have memory-mapped registers in this state, so force 3390 * device into D0 state before starting initialization. 3391 */ 3392 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3393 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3394 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3395 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3396 DELAY(1000); /* 27 usec is allegedly sufficent */ 3397 } 3398 3399 /* Save chipset family. */ 3400 switch (BGE_ASICREV(sc->bge_chipid)) { 3401 case BGE_ASICREV_BCM57765: 3402 case BGE_ASICREV_BCM57766: 3403 sc->bge_flags |= BGE_57765_PLUS; 3404 /* FALLTHROUGH */ 3405 case BGE_ASICREV_BCM5717: 3406 case BGE_ASICREV_BCM5719: 3407 case BGE_ASICREV_BCM5720: 3408 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | 3409 BGE_575X_PLUS | BGE_5705_PLUS | BGE_JUMBO_CAPABLE; 3410 /* Jumbo frame on BCM5719 A0 does not work. */ 3411 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3412 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3413 sc->bge_flags &= ~BGE_JUMBO_CAPABLE; 3414 break; 3415 case BGE_ASICREV_BCM5755: 3416 case BGE_ASICREV_BCM5761: 3417 case BGE_ASICREV_BCM5784: 3418 case BGE_ASICREV_BCM5785: 3419 case BGE_ASICREV_BCM5787: 3420 case BGE_ASICREV_BCM57780: 3421 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3422 break; 3423 case BGE_ASICREV_BCM5700: 3424 case BGE_ASICREV_BCM5701: 3425 case BGE_ASICREV_BCM5703: 3426 case BGE_ASICREV_BCM5704: 3427 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3428 break; 3429 case BGE_ASICREV_BCM5714_A0: 3430 case BGE_ASICREV_BCM5780: 3431 case BGE_ASICREV_BCM5714: 3432 sc->bge_flags |= BGE_5714_FAMILY | BGE_JUMBO_CAPABLE; 3433 /* FALLTHROUGH */ 3434 case BGE_ASICREV_BCM5750: 3435 case BGE_ASICREV_BCM5752: 3436 case BGE_ASICREV_BCM5906: 3437 sc->bge_flags |= BGE_575X_PLUS; 3438 /* FALLTHROUGH */ 3439 case BGE_ASICREV_BCM5705: 3440 sc->bge_flags |= BGE_5705_PLUS; 3441 break; 3442 } 3443 3444 /* Identify chips with APE processor. */ 3445 switch (BGE_ASICREV(sc->bge_chipid)) { 3446 case BGE_ASICREV_BCM5717: 3447 case BGE_ASICREV_BCM5719: 3448 case BGE_ASICREV_BCM5720: 3449 case BGE_ASICREV_BCM5761: 3450 sc->bge_flags |= BGE_APE; 3451 break; 3452 } 3453 3454 /* Chips with APE need BAR2 access for APE registers/memory. */ 3455 if ((sc->bge_flags & BGE_APE) != 0) { 3456 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3457 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3458 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3459 &sc->bge_apesize)) { 3460 aprint_error_dev(sc->bge_dev, 3461 "couldn't map BAR2 memory\n"); 3462 return; 3463 } 3464 3465 /* Enable APE register/memory access by host driver. */ 3466 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3467 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3468 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3469 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3470 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3471 3472 bge_ape_lock_init(sc); 3473 bge_ape_read_fw_ver(sc); 3474 } 3475 3476 /* Identify the chips that use an CPMU. */ 3477 if (BGE_IS_5717_PLUS(sc) || 3478 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3479 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3480 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3481 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3482 sc->bge_flags |= BGE_CPMU_PRESENT; 3483 3484 /* Set MI_MODE */ 3485 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3486 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3487 mimode |= BGE_MIMODE_500KHZ_CONST; 3488 else 3489 mimode |= BGE_MIMODE_BASE; 3490 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3491 3492 /* 3493 * When using the BCM5701 in PCI-X mode, data corruption has 3494 * been observed in the first few bytes of some received packets. 3495 * Aligning the packet buffer in memory eliminates the corruption. 3496 * Unfortunately, this misaligns the packet payloads. On platforms 3497 * which do not support unaligned accesses, we will realign the 3498 * payloads by copying the received packets. 3499 */ 3500 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3501 sc->bge_flags & BGE_PCIX) 3502 sc->bge_flags |= BGE_RX_ALIGNBUG; 3503 3504 if (BGE_IS_5700_FAMILY(sc)) 3505 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3506 3507 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3508 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3509 3510 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3511 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3512 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3513 sc->bge_flags |= BGE_IS_5788; 3514 3515 /* 3516 * Some controllers seem to require a special firmware to use 3517 * TSO. But the firmware is not available to FreeBSD and Linux 3518 * claims that the TSO performed by the firmware is slower than 3519 * hardware based TSO. Moreover the firmware based TSO has one 3520 * known bug which can't handle TSO if ethernet header + IP/TCP 3521 * header is greater than 80 bytes. The workaround for the TSO 3522 * bug exist but it seems it's too expensive than not using 3523 * TSO at all. Some hardwares also have the TSO bug so limit 3524 * the TSO to the controllers that are not affected TSO issues 3525 * (e.g. 5755 or higher). 3526 */ 3527 if (BGE_IS_5755_PLUS(sc)) { 3528 /* 3529 * BCM5754 and BCM5787 shares the same ASIC id so 3530 * explicit device id check is required. 3531 */ 3532 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3533 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3534 sc->bge_flags |= BGE_TSO; 3535 } 3536 3537 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3538 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3539 (misccfg == 0x4000 || misccfg == 0x8000)) || 3540 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3541 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3542 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3543 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3544 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3545 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3546 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3547 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3548 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3549 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3550 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3551 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3552 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3553 capmask &= ~BMSR_EXTSTAT; 3554 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3555 } 3556 3557 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3558 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3559 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3560 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3561 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3562 3563 /* Set various PHY bug flags. */ 3564 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3565 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3566 sc->bge_flags |= BGE_PHY_CRC_BUG; 3567 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3568 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3569 sc->bge_flags |= BGE_PHY_ADC_BUG; 3570 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3571 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3572 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3573 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3574 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3575 sc->bge_flags |= BGE_PHY_NO_3LED; 3576 if (BGE_IS_5705_PLUS(sc) && 3577 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3578 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3579 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3580 !BGE_IS_5717_PLUS(sc)) { 3581 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3582 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3583 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3584 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3585 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3586 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3587 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3588 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3589 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3590 } else 3591 sc->bge_flags |= BGE_PHY_BER_BUG; 3592 } 3593 3594 /* 3595 * SEEPROM check. 3596 * First check if firmware knows we do not have SEEPROM. 3597 */ 3598 if (prop_dictionary_get_bool(device_properties(self), 3599 "without-seeprom", &no_seeprom) && no_seeprom) 3600 sc->bge_flags |= BGE_NO_EEPROM; 3601 3602 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3603 sc->bge_flags |= BGE_NO_EEPROM; 3604 3605 /* Now check the 'ROM failed' bit on the RX CPU */ 3606 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3607 sc->bge_flags |= BGE_NO_EEPROM; 3608 3609 sc->bge_asf_mode = 0; 3610 /* No ASF if APE present. */ 3611 if ((sc->bge_flags & BGE_APE) == 0) { 3612 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3613 BGE_SRAM_DATA_SIG_MAGIC)) { 3614 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3615 BGE_HWCFG_ASF) { 3616 sc->bge_asf_mode |= ASF_ENABLE; 3617 sc->bge_asf_mode |= ASF_STACKUP; 3618 if (BGE_IS_575X_PLUS(sc)) 3619 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3620 } 3621 } 3622 } 3623 3624 /* 3625 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3626 * lock in bge_reset(). 3627 */ 3628 CSR_WRITE_4(sc, BGE_EE_ADDR, 3629 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3630 delay(1000); 3631 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3632 3633 bge_stop_fw(sc); 3634 bge_sig_pre_reset(sc, BGE_RESET_START); 3635 if (bge_reset(sc)) 3636 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3637 3638 /* 3639 * Read the hardware config word in the first 32k of NIC internal 3640 * memory, or fall back to the config word in the EEPROM. 3641 * Note: on some BCM5700 cards, this value appears to be unset. 3642 */ 3643 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = 0; 3644 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3645 BGE_SRAM_DATA_SIG_MAGIC) { 3646 uint32_t tmp; 3647 3648 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3649 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3650 BGE_SRAM_DATA_VER_SHIFT; 3651 if ((0 < tmp) && (tmp < 0x100)) 3652 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3653 if (sc->bge_flags & BGE_PCIE) 3654 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3655 if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) 3656 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3657 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3658 bge_read_eeprom(sc, (void *)&hwcfg, 3659 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3660 hwcfg = be32toh(hwcfg); 3661 } 3662 aprint_normal_dev(sc->bge_dev, "HW config %08x, %08x, %08x, %08x\n", 3663 hwcfg, hwcfg2, hwcfg3, hwcfg4); 3664 3665 bge_sig_legacy(sc, BGE_RESET_START); 3666 bge_sig_post_reset(sc, BGE_RESET_START); 3667 3668 if (bge_chipinit(sc)) { 3669 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3670 bge_release_resources(sc); 3671 return; 3672 } 3673 3674 /* 3675 * Get station address from the EEPROM. 3676 */ 3677 if (bge_get_eaddr(sc, eaddr)) { 3678 aprint_error_dev(sc->bge_dev, 3679 "failed to read station address\n"); 3680 bge_release_resources(sc); 3681 return; 3682 } 3683 3684 br = bge_lookup_rev(sc->bge_chipid); 3685 3686 if (br == NULL) { 3687 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3688 sc->bge_chipid); 3689 } else { 3690 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3691 br->br_name, sc->bge_chipid); 3692 } 3693 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3694 3695 /* Allocate the general information block and ring buffers. */ 3696 if (pci_dma64_available(pa)) 3697 sc->bge_dmatag = pa->pa_dmat64; 3698 else 3699 sc->bge_dmatag = pa->pa_dmat; 3700 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3701 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3702 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3703 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3704 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3705 return; 3706 } 3707 DPRINTFN(5, ("bus_dmamem_map\n")); 3708 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3709 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3710 BUS_DMA_NOWAIT)) { 3711 aprint_error_dev(sc->bge_dev, 3712 "can't map DMA buffers (%zu bytes)\n", 3713 sizeof(struct bge_ring_data)); 3714 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3715 sc->bge_ring_rseg); 3716 return; 3717 } 3718 DPRINTFN(5, ("bus_dmamem_create\n")); 3719 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3720 sizeof(struct bge_ring_data), 0, 3721 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3722 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3723 bus_dmamem_unmap(sc->bge_dmatag, kva, 3724 sizeof(struct bge_ring_data)); 3725 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3726 sc->bge_ring_rseg); 3727 return; 3728 } 3729 DPRINTFN(5, ("bus_dmamem_load\n")); 3730 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3731 sizeof(struct bge_ring_data), NULL, 3732 BUS_DMA_NOWAIT)) { 3733 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3734 bus_dmamem_unmap(sc->bge_dmatag, kva, 3735 sizeof(struct bge_ring_data)); 3736 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3737 sc->bge_ring_rseg); 3738 return; 3739 } 3740 3741 DPRINTFN(5, ("bzero\n")); 3742 sc->bge_rdata = (struct bge_ring_data *)kva; 3743 3744 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3745 3746 /* Try to allocate memory for jumbo buffers. */ 3747 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3748 if (bge_alloc_jumbo_mem(sc)) { 3749 aprint_error_dev(sc->bge_dev, 3750 "jumbo buffer allocation failed\n"); 3751 } else 3752 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3753 } 3754 3755 /* Set default tuneable values. */ 3756 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3757 sc->bge_rx_coal_ticks = 150; 3758 sc->bge_rx_max_coal_bds = 64; 3759 sc->bge_tx_coal_ticks = 300; 3760 sc->bge_tx_max_coal_bds = 400; 3761 if (BGE_IS_5705_PLUS(sc)) { 3762 sc->bge_tx_coal_ticks = (12 * 5); 3763 sc->bge_tx_max_coal_bds = (12 * 5); 3764 aprint_verbose_dev(sc->bge_dev, 3765 "setting short Tx thresholds\n"); 3766 } 3767 3768 if (BGE_IS_5717_PLUS(sc)) 3769 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3770 else if (BGE_IS_5705_PLUS(sc)) 3771 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3772 else 3773 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3774 3775 /* Set up ifnet structure */ 3776 ifp = &sc->ethercom.ec_if; 3777 ifp->if_softc = sc; 3778 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3779 ifp->if_ioctl = bge_ioctl; 3780 ifp->if_stop = bge_stop; 3781 ifp->if_start = bge_start; 3782 ifp->if_init = bge_init; 3783 ifp->if_watchdog = bge_watchdog; 3784 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3785 IFQ_SET_READY(&ifp->if_snd); 3786 DPRINTFN(5, ("strcpy if_xname\n")); 3787 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3788 3789 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3790 sc->ethercom.ec_if.if_capabilities |= 3791 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3792 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3793 sc->ethercom.ec_if.if_capabilities |= 3794 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3795 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3796 #endif 3797 sc->ethercom.ec_capabilities |= 3798 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3799 3800 if (sc->bge_flags & BGE_TSO) 3801 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3802 3803 /* 3804 * Do MII setup. 3805 */ 3806 DPRINTFN(5, ("mii setup\n")); 3807 sc->bge_mii.mii_ifp = ifp; 3808 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3809 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3810 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3811 3812 /* 3813 * Figure out what sort of media we have by checking the hardware 3814 * config word. Note: on some BCM5700 cards, this value appears to be 3815 * unset. If that's the case, we have to rely on identifying the NIC 3816 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3817 * The SysKonnect SK-9D41 is a 1000baseSX card. 3818 */ 3819 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3820 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3821 if (BGE_IS_5714_FAMILY(sc)) 3822 sc->bge_flags |= BGE_PHY_FIBER_MII; 3823 else 3824 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3825 } 3826 3827 /* set phyflags and chipid before mii_attach() */ 3828 dict = device_properties(self); 3829 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3830 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3831 3832 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3833 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3834 bge_ifmedia_sts); 3835 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3836 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3837 0, NULL); 3838 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3839 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3840 /* Pretend the user requested this setting */ 3841 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3842 } else { 3843 /* 3844 * Do transceiver setup and tell the firmware the 3845 * driver is down so we can try to get access the 3846 * probe if ASF is running. Retry a couple of times 3847 * if we get a conflict with the ASF firmware accessing 3848 * the PHY. 3849 */ 3850 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3851 bge_asf_driver_up(sc); 3852 3853 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3854 bge_ifmedia_sts); 3855 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3856 sc->bge_phy_addr, MII_OFFSET_ANY, 3857 MIIF_DOPAUSE); 3858 3859 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3860 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3861 ifmedia_add(&sc->bge_mii.mii_media, 3862 IFM_ETHER|IFM_MANUAL, 0, NULL); 3863 ifmedia_set(&sc->bge_mii.mii_media, 3864 IFM_ETHER|IFM_MANUAL); 3865 } else 3866 ifmedia_set(&sc->bge_mii.mii_media, 3867 IFM_ETHER|IFM_AUTO); 3868 3869 /* 3870 * Now tell the firmware we are going up after probing the PHY 3871 */ 3872 if (sc->bge_asf_mode & ASF_STACKUP) 3873 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3874 } 3875 3876 /* 3877 * Call MI attach routine. 3878 */ 3879 DPRINTFN(5, ("if_attach\n")); 3880 if_attach(ifp); 3881 DPRINTFN(5, ("ether_ifattach\n")); 3882 ether_ifattach(ifp, eaddr); 3883 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3884 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3885 RND_TYPE_NET, 0); 3886 #ifdef BGE_EVENT_COUNTERS 3887 /* 3888 * Attach event counters. 3889 */ 3890 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3891 NULL, device_xname(sc->bge_dev), "intr"); 3892 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3893 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3894 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3895 NULL, device_xname(sc->bge_dev), "tx_xon"); 3896 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3897 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3898 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3899 NULL, device_xname(sc->bge_dev), "rx_xon"); 3900 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3901 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3902 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3903 NULL, device_xname(sc->bge_dev), "xoffentered"); 3904 #endif /* BGE_EVENT_COUNTERS */ 3905 DPRINTFN(5, ("callout_init\n")); 3906 callout_init(&sc->bge_timeout, 0); 3907 3908 if (pmf_device_register(self, NULL, NULL)) 3909 pmf_class_network_register(self, ifp); 3910 else 3911 aprint_error_dev(self, "couldn't establish power handler\n"); 3912 3913 bge_sysctl_init(sc); 3914 3915 #ifdef BGE_DEBUG 3916 bge_debug_info(sc); 3917 #endif 3918 } 3919 3920 /* 3921 * Stop all chip I/O so that the kernel's probe routines don't 3922 * get confused by errant DMAs when rebooting. 3923 */ 3924 static int 3925 bge_detach(device_t self, int flags __unused) 3926 { 3927 struct bge_softc *sc = device_private(self); 3928 struct ifnet *ifp = &sc->ethercom.ec_if; 3929 int s; 3930 3931 s = splnet(); 3932 /* Stop the interface. Callouts are stopped in it. */ 3933 bge_stop(ifp, 1); 3934 splx(s); 3935 3936 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3937 3938 /* Delete all remaining media. */ 3939 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3940 3941 ether_ifdetach(ifp); 3942 if_detach(ifp); 3943 3944 bge_release_resources(sc); 3945 3946 return 0; 3947 } 3948 3949 static void 3950 bge_release_resources(struct bge_softc *sc) 3951 { 3952 3953 /* Disestablish the interrupt handler */ 3954 if (sc->bge_intrhand != NULL) { 3955 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3956 sc->bge_intrhand = NULL; 3957 } 3958 3959 if (sc->bge_dmatag != NULL) { 3960 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3961 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3962 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3963 sizeof(struct bge_ring_data)); 3964 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3965 } 3966 3967 /* Unmap the device registers */ 3968 if (sc->bge_bsize != 0) { 3969 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3970 sc->bge_bsize = 0; 3971 } 3972 3973 /* Unmap the APE registers */ 3974 if (sc->bge_apesize != 0) { 3975 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3976 sc->bge_apesize); 3977 sc->bge_apesize = 0; 3978 } 3979 } 3980 3981 static int 3982 bge_reset(struct bge_softc *sc) 3983 { 3984 uint32_t cachesize, command; 3985 uint32_t reset, mac_mode, mac_mode_mask; 3986 pcireg_t devctl, reg; 3987 int i, val; 3988 void (*write_op)(struct bge_softc *, int, int); 3989 3990 /* Make mask for BGE_MAC_MODE register. */ 3991 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3993 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3994 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 3995 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3996 3997 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3998 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3999 if (sc->bge_flags & BGE_PCIE) 4000 write_op = bge_writemem_direct; 4001 else 4002 write_op = bge_writemem_ind; 4003 } else 4004 write_op = bge_writereg_ind; 4005 4006 /* 57XX step 4 */ 4007 /* Acquire the NVM lock */ 4008 if ((sc->bge_flags & BGE_NO_EEPROM) == 0 && 4009 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4010 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4011 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4012 for (i = 0; i < 8000; i++) { 4013 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4014 BGE_NVRAMSWARB_GNT1) 4015 break; 4016 DELAY(20); 4017 } 4018 if (i == 8000) { 4019 printf("%s: NVRAM lock timedout!\n", 4020 device_xname(sc->bge_dev)); 4021 } 4022 } 4023 4024 /* Take APE lock when performing reset. */ 4025 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4026 4027 /* 57XX step 3 */ 4028 /* Save some important PCI state. */ 4029 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4030 /* 5718 reset step 3 */ 4031 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4032 4033 /* 5718 reset step 5, 57XX step 5b-5d */ 4034 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4035 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4036 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4037 4038 /* XXX ???: Disable fastboot on controllers that support it. */ 4039 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4040 BGE_IS_5755_PLUS(sc)) 4041 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4042 4043 /* 5718 reset step 2, 57XX step 6 */ 4044 /* 4045 * Write the magic number to SRAM at offset 0xB50. 4046 * When firmware finishes its initialization it will 4047 * write ~BGE_MAGIC_NUMBER to the same location. 4048 */ 4049 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4050 4051 /* 5718 reset step 6, 57XX step 7 */ 4052 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4053 /* 4054 * XXX: from FreeBSD/Linux; no documentation 4055 */ 4056 if (sc->bge_flags & BGE_PCIE) { 4057 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 4058 !BGE_IS_57765_PLUS(sc) && 4059 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4060 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4061 /* PCI Express 1.0 system */ 4062 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4063 BGE_PHY_PCIE_SCRAM_MODE); 4064 } 4065 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4066 /* 4067 * Prevent PCI Express link training 4068 * during global reset. 4069 */ 4070 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4071 reset |= (1 << 29); 4072 } 4073 } 4074 4075 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4076 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4077 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4078 i | BGE_VCPU_STATUS_DRV_RESET); 4079 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4080 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4081 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4082 } 4083 4084 /* 4085 * Set GPHY Power Down Override to leave GPHY 4086 * powered up in D0 uninitialized. 4087 */ 4088 if (BGE_IS_5705_PLUS(sc) && 4089 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4090 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4091 4092 /* Issue global reset */ 4093 write_op(sc, BGE_MISC_CFG, reset); 4094 4095 /* 5718 reset step 7, 57XX step 8 */ 4096 if (sc->bge_flags & BGE_PCIE) 4097 delay(100*1000); /* too big */ 4098 else 4099 delay(1000); 4100 4101 if (sc->bge_flags & BGE_PCIE) { 4102 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4103 DELAY(500000); 4104 /* XXX: Magic Numbers */ 4105 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4106 BGE_PCI_UNKNOWN0); 4107 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4108 BGE_PCI_UNKNOWN0, 4109 reg | (1 << 15)); 4110 } 4111 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4112 sc->bge_pciecap + PCIE_DCSR); 4113 /* Clear enable no snoop and disable relaxed ordering. */ 4114 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4115 PCIE_DCSR_ENA_NO_SNOOP); 4116 4117 /* Set PCIE max payload size to 128 for older PCIe devices */ 4118 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4119 devctl &= ~(0x00e0); 4120 /* Clear device status register. Write 1b to clear */ 4121 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4122 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4123 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4124 sc->bge_pciecap + PCIE_DCSR, devctl); 4125 bge_set_max_readrq(sc); 4126 } 4127 4128 /* From Linux: dummy read to flush PCI posted writes */ 4129 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4130 4131 /* 4132 * Reset some of the PCI state that got zapped by reset 4133 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4134 * set, too. 4135 */ 4136 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4137 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4138 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4139 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4140 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4141 (sc->bge_flags & BGE_PCIX) != 0) 4142 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4143 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4144 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4145 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4146 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4147 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4148 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4149 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4150 4151 /* Step 11: disable PCI-X Relaxed Ordering. */ 4152 if (sc->bge_flags & BGE_PCIX) { 4153 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4154 + PCIX_CMD); 4155 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4156 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4157 } 4158 4159 /* 5718 reset step 10, 57XX step 12 */ 4160 /* Enable memory arbiter. */ 4161 if (BGE_IS_5714_FAMILY(sc)) { 4162 val = CSR_READ_4(sc, BGE_MARB_MODE); 4163 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4164 } else 4165 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4166 4167 /* XXX 5721, 5751 and 5752 */ 4168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4169 /* Step 19: */ 4170 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4171 /* Step 20: */ 4172 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4173 } 4174 4175 /* 5718 reset step 13, 57XX step 17 */ 4176 /* Poll until the firmware initialization is complete */ 4177 bge_poll_fw(sc); 4178 4179 /* 5718 reset step 12, 57XX step 15 and 16 */ 4180 /* Fix up byte swapping */ 4181 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4182 4183 /* 57XX step 21 */ 4184 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4185 pcireg_t msidata; 4186 4187 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4188 BGE_PCI_MSI_DATA); 4189 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4190 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4191 msidata); 4192 } 4193 4194 /* 57XX step 18 */ 4195 /* Write mac mode. */ 4196 val = CSR_READ_4(sc, BGE_MAC_MODE); 4197 /* Restore mac_mode_mask's bits using mac_mode */ 4198 val = (val & ~mac_mode_mask) | mac_mode; 4199 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4200 DELAY(40); 4201 4202 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4203 4204 /* 4205 * The 5704 in TBI mode apparently needs some special 4206 * adjustment to insure the SERDES drive level is set 4207 * to 1.2V. 4208 */ 4209 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4210 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4211 uint32_t serdescfg; 4212 4213 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4214 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4215 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4216 } 4217 4218 if (sc->bge_flags & BGE_PCIE && 4219 !BGE_IS_57765_PLUS(sc) && 4220 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4221 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4222 uint32_t v; 4223 4224 /* Enable PCI Express bug fix */ 4225 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4226 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4227 v | BGE_TLP_DATA_FIFO_PROTECT); 4228 } 4229 4230 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4231 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4232 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4233 4234 return 0; 4235 } 4236 4237 /* 4238 * Frame reception handling. This is called if there's a frame 4239 * on the receive return list. 4240 * 4241 * Note: we have to be able to handle two possibilities here: 4242 * 1) the frame is from the jumbo receive ring 4243 * 2) the frame is from the standard receive ring 4244 */ 4245 4246 static void 4247 bge_rxeof(struct bge_softc *sc) 4248 { 4249 struct ifnet *ifp; 4250 uint16_t rx_prod, rx_cons; 4251 int stdcnt = 0, jumbocnt = 0; 4252 bus_dmamap_t dmamap; 4253 bus_addr_t offset, toff; 4254 bus_size_t tlen; 4255 int tosync; 4256 4257 rx_cons = sc->bge_rx_saved_considx; 4258 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4259 4260 /* Nothing to do */ 4261 if (rx_cons == rx_prod) 4262 return; 4263 4264 ifp = &sc->ethercom.ec_if; 4265 4266 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4267 offsetof(struct bge_ring_data, bge_status_block), 4268 sizeof (struct bge_status_block), 4269 BUS_DMASYNC_POSTREAD); 4270 4271 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4272 tosync = rx_prod - rx_cons; 4273 4274 if (tosync != 0) 4275 rnd_add_uint32(&sc->rnd_source, tosync); 4276 4277 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4278 4279 if (tosync < 0) { 4280 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4281 sizeof (struct bge_rx_bd); 4282 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4283 toff, tlen, BUS_DMASYNC_POSTREAD); 4284 tosync = -tosync; 4285 } 4286 4287 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4288 offset, tosync * sizeof (struct bge_rx_bd), 4289 BUS_DMASYNC_POSTREAD); 4290 4291 while (rx_cons != rx_prod) { 4292 struct bge_rx_bd *cur_rx; 4293 uint32_t rxidx; 4294 struct mbuf *m = NULL; 4295 4296 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4297 4298 rxidx = cur_rx->bge_idx; 4299 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4300 4301 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4302 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4303 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4304 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4305 jumbocnt++; 4306 bus_dmamap_sync(sc->bge_dmatag, 4307 sc->bge_cdata.bge_rx_jumbo_map, 4308 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4309 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4310 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4311 ifp->if_ierrors++; 4312 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4313 continue; 4314 } 4315 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4316 NULL)== ENOBUFS) { 4317 ifp->if_ierrors++; 4318 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4319 continue; 4320 } 4321 } else { 4322 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4323 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4324 4325 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4326 stdcnt++; 4327 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4328 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4329 if (dmamap == NULL) { 4330 ifp->if_ierrors++; 4331 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4332 continue; 4333 } 4334 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4335 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4336 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4337 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4338 ifp->if_ierrors++; 4339 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4340 continue; 4341 } 4342 if (bge_newbuf_std(sc, sc->bge_std, 4343 NULL, dmamap) == ENOBUFS) { 4344 ifp->if_ierrors++; 4345 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4346 continue; 4347 } 4348 } 4349 4350 ifp->if_ipackets++; 4351 #ifndef __NO_STRICT_ALIGNMENT 4352 /* 4353 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4354 * the Rx buffer has the layer-2 header unaligned. 4355 * If our CPU requires alignment, re-align by copying. 4356 */ 4357 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4358 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4359 cur_rx->bge_len); 4360 m->m_data += ETHER_ALIGN; 4361 } 4362 #endif 4363 4364 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4365 m->m_pkthdr.rcvif = ifp; 4366 4367 /* 4368 * Handle BPF listeners. Let the BPF user see the packet. 4369 */ 4370 bpf_mtap(ifp, m); 4371 4372 bge_rxcsum(sc, cur_rx, m); 4373 4374 /* 4375 * If we received a packet with a vlan tag, pass it 4376 * to vlan_input() instead of ether_input(). 4377 */ 4378 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4379 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4380 } 4381 4382 (*ifp->if_input)(ifp, m); 4383 } 4384 4385 sc->bge_rx_saved_considx = rx_cons; 4386 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4387 if (stdcnt) 4388 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4389 if (jumbocnt) 4390 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4391 } 4392 4393 static void 4394 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4395 { 4396 4397 if (BGE_IS_5717_PLUS(sc)) { 4398 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4399 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4400 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4401 if ((cur_rx->bge_error_flag & 4402 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4403 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4404 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4405 m->m_pkthdr.csum_data = 4406 cur_rx->bge_tcp_udp_csum; 4407 m->m_pkthdr.csum_flags |= 4408 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4409 M_CSUM_DATA); 4410 } 4411 } 4412 } else { 4413 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4414 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4415 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4416 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4417 /* 4418 * Rx transport checksum-offload may also 4419 * have bugs with packets which, when transmitted, 4420 * were `runts' requiring padding. 4421 */ 4422 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4423 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4424 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4425 m->m_pkthdr.csum_data = 4426 cur_rx->bge_tcp_udp_csum; 4427 m->m_pkthdr.csum_flags |= 4428 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4429 M_CSUM_DATA); 4430 } 4431 } 4432 } 4433 4434 static void 4435 bge_txeof(struct bge_softc *sc) 4436 { 4437 struct bge_tx_bd *cur_tx = NULL; 4438 struct ifnet *ifp; 4439 struct txdmamap_pool_entry *dma; 4440 bus_addr_t offset, toff; 4441 bus_size_t tlen; 4442 int tosync; 4443 struct mbuf *m; 4444 4445 ifp = &sc->ethercom.ec_if; 4446 4447 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4448 offsetof(struct bge_ring_data, bge_status_block), 4449 sizeof (struct bge_status_block), 4450 BUS_DMASYNC_POSTREAD); 4451 4452 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4453 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4454 sc->bge_tx_saved_considx; 4455 4456 if (tosync != 0) 4457 rnd_add_uint32(&sc->rnd_source, tosync); 4458 4459 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4460 4461 if (tosync < 0) { 4462 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4463 sizeof (struct bge_tx_bd); 4464 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4465 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4466 tosync = -tosync; 4467 } 4468 4469 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4470 offset, tosync * sizeof (struct bge_tx_bd), 4471 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4472 4473 /* 4474 * Go through our tx ring and free mbufs for those 4475 * frames that have been sent. 4476 */ 4477 while (sc->bge_tx_saved_considx != 4478 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4479 uint32_t idx = 0; 4480 4481 idx = sc->bge_tx_saved_considx; 4482 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4483 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4484 ifp->if_opackets++; 4485 m = sc->bge_cdata.bge_tx_chain[idx]; 4486 if (m != NULL) { 4487 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4488 dma = sc->txdma[idx]; 4489 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4490 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4491 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4492 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4493 sc->txdma[idx] = NULL; 4494 4495 m_freem(m); 4496 } 4497 sc->bge_txcnt--; 4498 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4499 ifp->if_timer = 0; 4500 } 4501 4502 if (cur_tx != NULL) 4503 ifp->if_flags &= ~IFF_OACTIVE; 4504 } 4505 4506 static int 4507 bge_intr(void *xsc) 4508 { 4509 struct bge_softc *sc; 4510 struct ifnet *ifp; 4511 uint32_t statusword; 4512 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4513 4514 sc = xsc; 4515 ifp = &sc->ethercom.ec_if; 4516 4517 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4518 if (BGE_IS_5717_PLUS(sc)) 4519 intrmask = 0; 4520 4521 /* It is possible for the interrupt to arrive before 4522 * the status block is updated prior to the interrupt. 4523 * Reading the PCI State register will confirm whether the 4524 * interrupt is ours and will flush the status block. 4525 */ 4526 4527 /* read status word from status block */ 4528 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4529 offsetof(struct bge_ring_data, bge_status_block), 4530 sizeof (struct bge_status_block), 4531 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4532 statusword = sc->bge_rdata->bge_status_block.bge_status; 4533 4534 if ((statusword & BGE_STATFLAG_UPDATED) || 4535 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) { 4536 /* Ack interrupt and stop others from occuring. */ 4537 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4538 4539 BGE_EVCNT_INCR(sc->bge_ev_intr); 4540 4541 /* clear status word */ 4542 sc->bge_rdata->bge_status_block.bge_status = 0; 4543 4544 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4545 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4546 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4547 bge_link_upd(sc); 4548 4549 if (ifp->if_flags & IFF_RUNNING) { 4550 /* Check RX return ring producer/consumer */ 4551 bge_rxeof(sc); 4552 4553 /* Check TX ring producer/consumer */ 4554 bge_txeof(sc); 4555 } 4556 4557 if (sc->bge_pending_rxintr_change) { 4558 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4559 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4560 uint32_t junk; 4561 4562 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4563 DELAY(10); 4564 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4565 4566 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4567 DELAY(10); 4568 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4569 4570 sc->bge_pending_rxintr_change = 0; 4571 } 4572 bge_handle_events(sc); 4573 4574 /* Re-enable interrupts. */ 4575 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4576 4577 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4578 bge_start(ifp); 4579 4580 return 1; 4581 } else 4582 return 0; 4583 } 4584 4585 static void 4586 bge_asf_driver_up(struct bge_softc *sc) 4587 { 4588 if (sc->bge_asf_mode & ASF_STACKUP) { 4589 /* Send ASF heartbeat aprox. every 2s */ 4590 if (sc->bge_asf_count) 4591 sc->bge_asf_count --; 4592 else { 4593 sc->bge_asf_count = 2; 4594 4595 bge_wait_for_event_ack(sc); 4596 4597 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4598 BGE_FW_CMD_DRV_ALIVE); 4599 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4600 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4601 BGE_FW_HB_TIMEOUT_SEC); 4602 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4603 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4604 BGE_RX_CPU_DRV_EVENT); 4605 } 4606 } 4607 } 4608 4609 static void 4610 bge_tick(void *xsc) 4611 { 4612 struct bge_softc *sc = xsc; 4613 struct mii_data *mii = &sc->bge_mii; 4614 int s; 4615 4616 s = splnet(); 4617 4618 if (BGE_IS_5705_PLUS(sc)) 4619 bge_stats_update_regs(sc); 4620 else 4621 bge_stats_update(sc); 4622 4623 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4624 /* 4625 * Since in TBI mode auto-polling can't be used we should poll 4626 * link status manually. Here we register pending link event 4627 * and trigger interrupt. 4628 */ 4629 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4630 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4631 } else { 4632 /* 4633 * Do not touch PHY if we have link up. This could break 4634 * IPMI/ASF mode or produce extra input errors. 4635 * (extra input errors was reported for bcm5701 & bcm5704). 4636 */ 4637 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4638 mii_tick(mii); 4639 } 4640 4641 bge_asf_driver_up(sc); 4642 4643 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4644 4645 splx(s); 4646 } 4647 4648 static void 4649 bge_stats_update_regs(struct bge_softc *sc) 4650 { 4651 struct ifnet *ifp = &sc->ethercom.ec_if; 4652 4653 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4654 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4655 4656 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4657 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4658 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4659 } 4660 4661 static void 4662 bge_stats_update(struct bge_softc *sc) 4663 { 4664 struct ifnet *ifp = &sc->ethercom.ec_if; 4665 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4666 4667 #define READ_STAT(sc, stats, stat) \ 4668 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4669 4670 ifp->if_collisions += 4671 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4672 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4673 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4674 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4675 ifp->if_collisions; 4676 4677 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4678 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4679 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4680 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4681 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4682 READ_STAT(sc, stats, 4683 xoffPauseFramesReceived.bge_addr_lo)); 4684 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4685 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4686 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4687 READ_STAT(sc, stats, 4688 macControlFramesReceived.bge_addr_lo)); 4689 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4690 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4691 4692 #undef READ_STAT 4693 4694 #ifdef notdef 4695 ifp->if_collisions += 4696 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4697 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4698 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4699 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4700 ifp->if_collisions; 4701 #endif 4702 } 4703 4704 /* 4705 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4706 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4707 * but when such padded frames employ the bge IP/TCP checksum offload, 4708 * the hardware checksum assist gives incorrect results (possibly 4709 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4710 * If we pad such runts with zeros, the onboard checksum comes out correct. 4711 */ 4712 static inline int 4713 bge_cksum_pad(struct mbuf *pkt) 4714 { 4715 struct mbuf *last = NULL; 4716 int padlen; 4717 4718 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4719 4720 /* if there's only the packet-header and we can pad there, use it. */ 4721 if (pkt->m_pkthdr.len == pkt->m_len && 4722 M_TRAILINGSPACE(pkt) >= padlen) { 4723 last = pkt; 4724 } else { 4725 /* 4726 * Walk packet chain to find last mbuf. We will either 4727 * pad there, or append a new mbuf and pad it 4728 * (thus perhaps avoiding the bcm5700 dma-min bug). 4729 */ 4730 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4731 continue; /* do nothing */ 4732 } 4733 4734 /* `last' now points to last in chain. */ 4735 if (M_TRAILINGSPACE(last) < padlen) { 4736 /* Allocate new empty mbuf, pad it. Compact later. */ 4737 struct mbuf *n; 4738 MGET(n, M_DONTWAIT, MT_DATA); 4739 if (n == NULL) 4740 return ENOBUFS; 4741 n->m_len = 0; 4742 last->m_next = n; 4743 last = n; 4744 } 4745 } 4746 4747 KDASSERT(!M_READONLY(last)); 4748 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4749 4750 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4751 memset(mtod(last, char *) + last->m_len, 0, padlen); 4752 last->m_len += padlen; 4753 pkt->m_pkthdr.len += padlen; 4754 return 0; 4755 } 4756 4757 /* 4758 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4759 */ 4760 static inline int 4761 bge_compact_dma_runt(struct mbuf *pkt) 4762 { 4763 struct mbuf *m, *prev; 4764 int totlen, prevlen; 4765 4766 prev = NULL; 4767 totlen = 0; 4768 prevlen = -1; 4769 4770 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4771 int mlen = m->m_len; 4772 int shortfall = 8 - mlen ; 4773 4774 totlen += mlen; 4775 if (mlen == 0) 4776 continue; 4777 if (mlen >= 8) 4778 continue; 4779 4780 /* If we get here, mbuf data is too small for DMA engine. 4781 * Try to fix by shuffling data to prev or next in chain. 4782 * If that fails, do a compacting deep-copy of the whole chain. 4783 */ 4784 4785 /* Internal frag. If fits in prev, copy it there. */ 4786 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4787 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4788 prev->m_len += mlen; 4789 m->m_len = 0; 4790 /* XXX stitch chain */ 4791 prev->m_next = m_free(m); 4792 m = prev; 4793 continue; 4794 } 4795 else if (m->m_next != NULL && 4796 M_TRAILINGSPACE(m) >= shortfall && 4797 m->m_next->m_len >= (8 + shortfall)) { 4798 /* m is writable and have enough data in next, pull up. */ 4799 4800 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4801 shortfall); 4802 m->m_len += shortfall; 4803 m->m_next->m_len -= shortfall; 4804 m->m_next->m_data += shortfall; 4805 } 4806 else if (m->m_next == NULL || 1) { 4807 /* Got a runt at the very end of the packet. 4808 * borrow data from the tail of the preceding mbuf and 4809 * update its length in-place. (The original data is still 4810 * valid, so we can do this even if prev is not writable.) 4811 */ 4812 4813 /* if we'd make prev a runt, just move all of its data. */ 4814 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4815 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4816 4817 if ((prev->m_len - shortfall) < 8) 4818 shortfall = prev->m_len; 4819 4820 #ifdef notyet /* just do the safe slow thing for now */ 4821 if (!M_READONLY(m)) { 4822 if (M_LEADINGSPACE(m) < shorfall) { 4823 void *m_dat; 4824 m_dat = (m->m_flags & M_PKTHDR) ? 4825 m->m_pktdat : m->dat; 4826 memmove(m_dat, mtod(m, void*), m->m_len); 4827 m->m_data = m_dat; 4828 } 4829 } else 4830 #endif /* just do the safe slow thing */ 4831 { 4832 struct mbuf * n = NULL; 4833 int newprevlen = prev->m_len - shortfall; 4834 4835 MGET(n, M_NOWAIT, MT_DATA); 4836 if (n == NULL) 4837 return ENOBUFS; 4838 KASSERT(m->m_len + shortfall < MLEN 4839 /*, 4840 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4841 4842 /* first copy the data we're stealing from prev */ 4843 memcpy(n->m_data, prev->m_data + newprevlen, 4844 shortfall); 4845 4846 /* update prev->m_len accordingly */ 4847 prev->m_len -= shortfall; 4848 4849 /* copy data from runt m */ 4850 memcpy(n->m_data + shortfall, m->m_data, 4851 m->m_len); 4852 4853 /* n holds what we stole from prev, plus m */ 4854 n->m_len = shortfall + m->m_len; 4855 4856 /* stitch n into chain and free m */ 4857 n->m_next = m->m_next; 4858 prev->m_next = n; 4859 /* KASSERT(m->m_next == NULL); */ 4860 m->m_next = NULL; 4861 m_free(m); 4862 m = n; /* for continuing loop */ 4863 } 4864 } 4865 prevlen = m->m_len; 4866 } 4867 return 0; 4868 } 4869 4870 /* 4871 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4872 * pointers to descriptors. 4873 */ 4874 static int 4875 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4876 { 4877 struct bge_tx_bd *f = NULL; 4878 uint32_t frag, cur; 4879 uint16_t csum_flags = 0; 4880 uint16_t txbd_tso_flags = 0; 4881 struct txdmamap_pool_entry *dma; 4882 bus_dmamap_t dmamap; 4883 int i = 0; 4884 struct m_tag *mtag; 4885 int use_tso, maxsegsize, error; 4886 4887 cur = frag = *txidx; 4888 4889 if (m_head->m_pkthdr.csum_flags) { 4890 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4891 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4892 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4893 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4894 } 4895 4896 /* 4897 * If we were asked to do an outboard checksum, and the NIC 4898 * has the bug where it sometimes adds in the Ethernet padding, 4899 * explicitly pad with zeros so the cksum will be correct either way. 4900 * (For now, do this for all chip versions, until newer 4901 * are confirmed to not require the workaround.) 4902 */ 4903 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4904 #ifdef notyet 4905 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4906 #endif 4907 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4908 goto check_dma_bug; 4909 4910 if (bge_cksum_pad(m_head) != 0) 4911 return ENOBUFS; 4912 4913 check_dma_bug: 4914 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4915 goto doit; 4916 4917 /* 4918 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4919 * less than eight bytes. If we encounter a teeny mbuf 4920 * at the end of a chain, we can pad. Otherwise, copy. 4921 */ 4922 if (bge_compact_dma_runt(m_head) != 0) 4923 return ENOBUFS; 4924 4925 doit: 4926 dma = SLIST_FIRST(&sc->txdma_list); 4927 if (dma == NULL) 4928 return ENOBUFS; 4929 dmamap = dma->dmamap; 4930 4931 /* 4932 * Set up any necessary TSO state before we start packing... 4933 */ 4934 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4935 if (!use_tso) { 4936 maxsegsize = 0; 4937 } else { /* TSO setup */ 4938 unsigned mss; 4939 struct ether_header *eh; 4940 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4941 struct mbuf * m0 = m_head; 4942 struct ip *ip; 4943 struct tcphdr *th; 4944 int iphl, hlen; 4945 4946 /* 4947 * XXX It would be nice if the mbuf pkthdr had offset 4948 * fields for the protocol headers. 4949 */ 4950 4951 eh = mtod(m0, struct ether_header *); 4952 switch (htons(eh->ether_type)) { 4953 case ETHERTYPE_IP: 4954 offset = ETHER_HDR_LEN; 4955 break; 4956 4957 case ETHERTYPE_VLAN: 4958 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4959 break; 4960 4961 default: 4962 /* 4963 * Don't support this protocol or encapsulation. 4964 */ 4965 return ENOBUFS; 4966 } 4967 4968 /* 4969 * TCP/IP headers are in the first mbuf; we can do 4970 * this the easy way. 4971 */ 4972 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4973 hlen = iphl + offset; 4974 if (__predict_false(m0->m_len < 4975 (hlen + sizeof(struct tcphdr)))) { 4976 4977 aprint_debug_dev(sc->bge_dev, 4978 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4979 "not handled yet\n", 4980 m0->m_len, hlen+ sizeof(struct tcphdr)); 4981 #ifdef NOTYET 4982 /* 4983 * XXX jonathan (at) NetBSD.org: untested. 4984 * how to force this branch to be taken? 4985 */ 4986 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4987 4988 m_copydata(m0, offset, sizeof(ip), &ip); 4989 m_copydata(m0, hlen, sizeof(th), &th); 4990 4991 ip.ip_len = 0; 4992 4993 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4994 sizeof(ip.ip_len), &ip.ip_len); 4995 4996 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4997 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4998 4999 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5000 sizeof(th.th_sum), &th.th_sum); 5001 5002 hlen += th.th_off << 2; 5003 iptcp_opt_words = hlen; 5004 #else 5005 /* 5006 * if_wm "hard" case not yet supported, can we not 5007 * mandate it out of existence? 5008 */ 5009 (void) ip; (void)th; (void) ip_tcp_hlen; 5010 5011 return ENOBUFS; 5012 #endif 5013 } else { 5014 ip = (struct ip *) (mtod(m0, char *) + offset); 5015 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5016 ip_tcp_hlen = iphl + (th->th_off << 2); 5017 5018 /* Total IP/TCP options, in 32-bit words */ 5019 iptcp_opt_words = (ip_tcp_hlen 5020 - sizeof(struct tcphdr) 5021 - sizeof(struct ip)) >> 2; 5022 } 5023 if (BGE_IS_575X_PLUS(sc)) { 5024 th->th_sum = 0; 5025 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5026 } else { 5027 /* 5028 * XXX jonathan (at) NetBSD.org: 5705 untested. 5029 * Requires TSO firmware patch for 5701/5703/5704. 5030 */ 5031 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5032 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5033 } 5034 5035 mss = m_head->m_pkthdr.segsz; 5036 txbd_tso_flags |= 5037 BGE_TXBDFLAG_CPU_PRE_DMA | 5038 BGE_TXBDFLAG_CPU_POST_DMA; 5039 5040 /* 5041 * Our NIC TSO-assist assumes TSO has standard, optionless 5042 * IPv4 and TCP headers, which total 40 bytes. By default, 5043 * the NIC copies 40 bytes of IP/TCP header from the 5044 * supplied header into the IP/TCP header portion of 5045 * each post-TSO-segment. If the supplied packet has IP or 5046 * TCP options, we need to tell the NIC to copy those extra 5047 * bytes into each post-TSO header, in addition to the normal 5048 * 40-byte IP/TCP header (and to leave space accordingly). 5049 * Unfortunately, the driver encoding of option length 5050 * varies across different ASIC families. 5051 */ 5052 tcp_seg_flags = 0; 5053 if (iptcp_opt_words) { 5054 if (BGE_IS_5705_PLUS(sc)) { 5055 tcp_seg_flags = 5056 iptcp_opt_words << 11; 5057 } else { 5058 txbd_tso_flags |= 5059 iptcp_opt_words << 12; 5060 } 5061 } 5062 maxsegsize = mss | tcp_seg_flags; 5063 ip->ip_len = htons(mss + ip_tcp_hlen); 5064 5065 } /* TSO setup */ 5066 5067 /* 5068 * Start packing the mbufs in this chain into 5069 * the fragment pointers. Stop when we run out 5070 * of fragments or hit the end of the mbuf chain. 5071 */ 5072 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5073 BUS_DMA_NOWAIT); 5074 if (error) 5075 return ENOBUFS; 5076 /* 5077 * Sanity check: avoid coming within 16 descriptors 5078 * of the end of the ring. 5079 */ 5080 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5081 BGE_TSO_PRINTF(("%s: " 5082 " dmamap_load_mbuf too close to ring wrap\n", 5083 device_xname(sc->bge_dev))); 5084 goto fail_unload; 5085 } 5086 5087 mtag = sc->ethercom.ec_nvlans ? 5088 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5089 5090 5091 /* Iterate over dmap-map fragments. */ 5092 for (i = 0; i < dmamap->dm_nsegs; i++) { 5093 f = &sc->bge_rdata->bge_tx_ring[frag]; 5094 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5095 break; 5096 5097 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5098 f->bge_len = dmamap->dm_segs[i].ds_len; 5099 5100 /* 5101 * For 5751 and follow-ons, for TSO we must turn 5102 * off checksum-assist flag in the tx-descr, and 5103 * supply the ASIC-revision-specific encoding 5104 * of TSO flags and segsize. 5105 */ 5106 if (use_tso) { 5107 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5108 f->bge_rsvd = maxsegsize; 5109 f->bge_flags = csum_flags | txbd_tso_flags; 5110 } else { 5111 f->bge_rsvd = 0; 5112 f->bge_flags = 5113 (csum_flags | txbd_tso_flags) & 0x0fff; 5114 } 5115 } else { 5116 f->bge_rsvd = 0; 5117 f->bge_flags = csum_flags; 5118 } 5119 5120 if (mtag != NULL) { 5121 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5122 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5123 } else { 5124 f->bge_vlan_tag = 0; 5125 } 5126 cur = frag; 5127 BGE_INC(frag, BGE_TX_RING_CNT); 5128 } 5129 5130 if (i < dmamap->dm_nsegs) { 5131 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5132 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5133 goto fail_unload; 5134 } 5135 5136 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5137 BUS_DMASYNC_PREWRITE); 5138 5139 if (frag == sc->bge_tx_saved_considx) { 5140 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5141 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5142 5143 goto fail_unload; 5144 } 5145 5146 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5147 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5148 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5149 sc->txdma[cur] = dma; 5150 sc->bge_txcnt += dmamap->dm_nsegs; 5151 5152 *txidx = frag; 5153 5154 return 0; 5155 5156 fail_unload: 5157 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5158 5159 return ENOBUFS; 5160 } 5161 5162 /* 5163 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5164 * to the mbuf data regions directly in the transmit descriptors. 5165 */ 5166 static void 5167 bge_start(struct ifnet *ifp) 5168 { 5169 struct bge_softc *sc; 5170 struct mbuf *m_head = NULL; 5171 uint32_t prodidx; 5172 int pkts = 0; 5173 5174 sc = ifp->if_softc; 5175 5176 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5177 return; 5178 5179 prodidx = sc->bge_tx_prodidx; 5180 5181 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5182 IFQ_POLL(&ifp->if_snd, m_head); 5183 if (m_head == NULL) 5184 break; 5185 5186 #if 0 5187 /* 5188 * XXX 5189 * safety overkill. If this is a fragmented packet chain 5190 * with delayed TCP/UDP checksums, then only encapsulate 5191 * it if we have enough descriptors to handle the entire 5192 * chain at once. 5193 * (paranoia -- may not actually be needed) 5194 */ 5195 if (m_head->m_flags & M_FIRSTFRAG && 5196 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5197 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5198 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5199 ifp->if_flags |= IFF_OACTIVE; 5200 break; 5201 } 5202 } 5203 #endif 5204 5205 /* 5206 * Pack the data into the transmit ring. If we 5207 * don't have room, set the OACTIVE flag and wait 5208 * for the NIC to drain the ring. 5209 */ 5210 if (bge_encap(sc, m_head, &prodidx)) { 5211 ifp->if_flags |= IFF_OACTIVE; 5212 break; 5213 } 5214 5215 /* now we are committed to transmit the packet */ 5216 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5217 pkts++; 5218 5219 /* 5220 * If there's a BPF listener, bounce a copy of this frame 5221 * to him. 5222 */ 5223 bpf_mtap(ifp, m_head); 5224 } 5225 if (pkts == 0) 5226 return; 5227 5228 /* Transmit */ 5229 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5230 /* 5700 b2 errata */ 5231 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5232 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5233 5234 sc->bge_tx_prodidx = prodidx; 5235 5236 /* 5237 * Set a timeout in case the chip goes out to lunch. 5238 */ 5239 ifp->if_timer = 5; 5240 } 5241 5242 static int 5243 bge_init(struct ifnet *ifp) 5244 { 5245 struct bge_softc *sc = ifp->if_softc; 5246 const uint16_t *m; 5247 uint32_t mode; 5248 int s, error = 0; 5249 5250 s = splnet(); 5251 5252 ifp = &sc->ethercom.ec_if; 5253 5254 /* Cancel pending I/O and flush buffers. */ 5255 bge_stop(ifp, 0); 5256 5257 bge_stop_fw(sc); 5258 bge_sig_pre_reset(sc, BGE_RESET_START); 5259 bge_reset(sc); 5260 bge_sig_legacy(sc, BGE_RESET_START); 5261 bge_sig_post_reset(sc, BGE_RESET_START); 5262 5263 bge_chipinit(sc); 5264 5265 /* 5266 * Init the various state machines, ring 5267 * control blocks and firmware. 5268 */ 5269 error = bge_blockinit(sc); 5270 if (error != 0) { 5271 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5272 error); 5273 splx(s); 5274 return error; 5275 } 5276 5277 ifp = &sc->ethercom.ec_if; 5278 5279 /* 5718 step 25, 57XX step 54 */ 5280 /* Specify MTU. */ 5281 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5282 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5283 5284 /* 5718 step 23 */ 5285 /* Load our MAC address. */ 5286 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5287 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5288 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5289 5290 /* Enable or disable promiscuous mode as needed. */ 5291 if (ifp->if_flags & IFF_PROMISC) 5292 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5293 else 5294 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5295 5296 /* Program multicast filter. */ 5297 bge_setmulti(sc); 5298 5299 /* Init RX ring. */ 5300 bge_init_rx_ring_std(sc); 5301 5302 /* 5303 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5304 * memory to insure that the chip has in fact read the first 5305 * entry of the ring. 5306 */ 5307 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5308 uint32_t v, i; 5309 for (i = 0; i < 10; i++) { 5310 DELAY(20); 5311 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5312 if (v == (MCLBYTES - ETHER_ALIGN)) 5313 break; 5314 } 5315 if (i == 10) 5316 aprint_error_dev(sc->bge_dev, 5317 "5705 A0 chip failed to load RX ring\n"); 5318 } 5319 5320 /* Init jumbo RX ring. */ 5321 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5322 bge_init_rx_ring_jumbo(sc); 5323 5324 /* Init our RX return ring index */ 5325 sc->bge_rx_saved_considx = 0; 5326 5327 /* Init TX ring. */ 5328 bge_init_tx_ring(sc); 5329 5330 /* 5718 step 63, 57XX step 94 */ 5331 /* Enable TX MAC state machine lockup fix. */ 5332 mode = CSR_READ_4(sc, BGE_TX_MODE); 5333 if (BGE_IS_5755_PLUS(sc) || 5334 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5335 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5336 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5337 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5338 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5339 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5340 } 5341 5342 /* Turn on transmitter */ 5343 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5344 /* 5718 step 64 */ 5345 DELAY(100); 5346 5347 /* 5718 step 65, 57XX step 95 */ 5348 /* Turn on receiver */ 5349 mode = CSR_READ_4(sc, BGE_RX_MODE); 5350 if (BGE_IS_5755_PLUS(sc)) 5351 mode |= BGE_RXMODE_IPV6_ENABLE; 5352 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5353 /* 5718 step 66 */ 5354 DELAY(10); 5355 5356 /* 5718 step 12 */ 5357 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5358 5359 /* Tell firmware we're alive. */ 5360 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5361 5362 /* Enable host interrupts. */ 5363 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5364 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5365 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5366 5367 if ((error = bge_ifmedia_upd(ifp)) != 0) 5368 goto out; 5369 5370 ifp->if_flags |= IFF_RUNNING; 5371 ifp->if_flags &= ~IFF_OACTIVE; 5372 5373 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5374 5375 out: 5376 sc->bge_if_flags = ifp->if_flags; 5377 splx(s); 5378 5379 return error; 5380 } 5381 5382 /* 5383 * Set media options. 5384 */ 5385 static int 5386 bge_ifmedia_upd(struct ifnet *ifp) 5387 { 5388 struct bge_softc *sc = ifp->if_softc; 5389 struct mii_data *mii = &sc->bge_mii; 5390 struct ifmedia *ifm = &sc->bge_ifmedia; 5391 int rc; 5392 5393 /* If this is a 1000baseX NIC, enable the TBI port. */ 5394 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5395 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5396 return EINVAL; 5397 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5398 case IFM_AUTO: 5399 /* 5400 * The BCM5704 ASIC appears to have a special 5401 * mechanism for programming the autoneg 5402 * advertisement registers in TBI mode. 5403 */ 5404 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5405 uint32_t sgdig; 5406 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5407 if (sgdig & BGE_SGDIGSTS_DONE) { 5408 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5409 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5410 sgdig |= BGE_SGDIGCFG_AUTO | 5411 BGE_SGDIGCFG_PAUSE_CAP | 5412 BGE_SGDIGCFG_ASYM_PAUSE; 5413 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5414 sgdig | BGE_SGDIGCFG_SEND); 5415 DELAY(5); 5416 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5417 sgdig); 5418 } 5419 } 5420 break; 5421 case IFM_1000_SX: 5422 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5423 BGE_CLRBIT(sc, BGE_MAC_MODE, 5424 BGE_MACMODE_HALF_DUPLEX); 5425 } else { 5426 BGE_SETBIT(sc, BGE_MAC_MODE, 5427 BGE_MACMODE_HALF_DUPLEX); 5428 } 5429 DELAY(40); 5430 break; 5431 default: 5432 return EINVAL; 5433 } 5434 /* XXX 802.3x flow control for 1000BASE-SX */ 5435 return 0; 5436 } 5437 5438 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5439 if ((rc = mii_mediachg(mii)) == ENXIO) 5440 return 0; 5441 5442 /* 5443 * Force an interrupt so that we will call bge_link_upd 5444 * if needed and clear any pending link state attention. 5445 * Without this we are not getting any further interrupts 5446 * for link state changes and thus will not UP the link and 5447 * not be able to send in bge_start. The only way to get 5448 * things working was to receive a packet and get a RX intr. 5449 */ 5450 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5451 sc->bge_flags & BGE_IS_5788) 5452 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5453 else 5454 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5455 5456 return rc; 5457 } 5458 5459 /* 5460 * Report current media status. 5461 */ 5462 static void 5463 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5464 { 5465 struct bge_softc *sc = ifp->if_softc; 5466 struct mii_data *mii = &sc->bge_mii; 5467 5468 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5469 ifmr->ifm_status = IFM_AVALID; 5470 ifmr->ifm_active = IFM_ETHER; 5471 if (CSR_READ_4(sc, BGE_MAC_STS) & 5472 BGE_MACSTAT_TBI_PCS_SYNCHED) 5473 ifmr->ifm_status |= IFM_ACTIVE; 5474 ifmr->ifm_active |= IFM_1000_SX; 5475 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5476 ifmr->ifm_active |= IFM_HDX; 5477 else 5478 ifmr->ifm_active |= IFM_FDX; 5479 return; 5480 } 5481 5482 mii_pollstat(mii); 5483 ifmr->ifm_status = mii->mii_media_status; 5484 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5485 sc->bge_flowflags; 5486 } 5487 5488 static int 5489 bge_ifflags_cb(struct ethercom *ec) 5490 { 5491 struct ifnet *ifp = &ec->ec_if; 5492 struct bge_softc *sc = ifp->if_softc; 5493 int change = ifp->if_flags ^ sc->bge_if_flags; 5494 5495 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5496 return ENETRESET; 5497 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5498 return 0; 5499 5500 if ((ifp->if_flags & IFF_PROMISC) == 0) 5501 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5502 else 5503 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5504 5505 bge_setmulti(sc); 5506 5507 sc->bge_if_flags = ifp->if_flags; 5508 return 0; 5509 } 5510 5511 static int 5512 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5513 { 5514 struct bge_softc *sc = ifp->if_softc; 5515 struct ifreq *ifr = (struct ifreq *) data; 5516 int s, error = 0; 5517 struct mii_data *mii; 5518 5519 s = splnet(); 5520 5521 switch (command) { 5522 case SIOCSIFMEDIA: 5523 /* XXX Flow control is not supported for 1000BASE-SX */ 5524 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5525 ifr->ifr_media &= ~IFM_ETH_FMASK; 5526 sc->bge_flowflags = 0; 5527 } 5528 5529 /* Flow control requires full-duplex mode. */ 5530 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5531 (ifr->ifr_media & IFM_FDX) == 0) { 5532 ifr->ifr_media &= ~IFM_ETH_FMASK; 5533 } 5534 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5535 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5536 /* We can do both TXPAUSE and RXPAUSE. */ 5537 ifr->ifr_media |= 5538 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5539 } 5540 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5541 } 5542 /* FALLTHROUGH */ 5543 case SIOCGIFMEDIA: 5544 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5545 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5546 command); 5547 } else { 5548 mii = &sc->bge_mii; 5549 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5550 command); 5551 } 5552 break; 5553 default: 5554 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5555 break; 5556 5557 error = 0; 5558 5559 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5560 ; 5561 else if (ifp->if_flags & IFF_RUNNING) 5562 bge_setmulti(sc); 5563 break; 5564 } 5565 5566 splx(s); 5567 5568 return error; 5569 } 5570 5571 static void 5572 bge_watchdog(struct ifnet *ifp) 5573 { 5574 struct bge_softc *sc; 5575 5576 sc = ifp->if_softc; 5577 5578 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5579 5580 ifp->if_flags &= ~IFF_RUNNING; 5581 bge_init(ifp); 5582 5583 ifp->if_oerrors++; 5584 } 5585 5586 static void 5587 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5588 { 5589 int i; 5590 5591 BGE_CLRBIT_FLUSH(sc, reg, bit); 5592 5593 for (i = 0; i < 1000; i++) { 5594 delay(100); 5595 if ((CSR_READ_4(sc, reg) & bit) == 0) 5596 return; 5597 } 5598 5599 /* 5600 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5601 * on some environment (and once after boot?) 5602 */ 5603 if (reg != BGE_SRS_MODE) 5604 aprint_error_dev(sc->bge_dev, 5605 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5606 (u_long)reg, bit); 5607 } 5608 5609 /* 5610 * Stop the adapter and free any mbufs allocated to the 5611 * RX and TX lists. 5612 */ 5613 static void 5614 bge_stop(struct ifnet *ifp, int disable) 5615 { 5616 struct bge_softc *sc = ifp->if_softc; 5617 5618 callout_stop(&sc->bge_timeout); 5619 5620 /* Disable host interrupts. */ 5621 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5622 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5623 5624 /* 5625 * Tell firmware we're shutting down. 5626 */ 5627 bge_stop_fw(sc); 5628 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5629 5630 /* 5631 * Disable all of the receiver blocks. 5632 */ 5633 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5634 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5635 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5636 if (BGE_IS_5700_FAMILY(sc)) 5637 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5638 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5639 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5640 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5641 5642 /* 5643 * Disable all of the transmit blocks. 5644 */ 5645 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5646 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5647 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5648 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5649 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5650 if (BGE_IS_5700_FAMILY(sc)) 5651 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5652 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5653 5654 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5655 delay(40); 5656 5657 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5658 5659 /* 5660 * Shut down all of the memory managers and related 5661 * state machines. 5662 */ 5663 /* 5718 step 5a,5b */ 5664 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5665 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5666 if (BGE_IS_5700_FAMILY(sc)) 5667 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5668 5669 /* 5718 step 5c,5d */ 5670 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5671 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5672 5673 if (BGE_IS_5700_FAMILY(sc)) { 5674 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5675 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5676 } 5677 5678 bge_reset(sc); 5679 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5680 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5681 5682 /* 5683 * Keep the ASF firmware running if up. 5684 */ 5685 if (sc->bge_asf_mode & ASF_STACKUP) 5686 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5687 else 5688 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5689 5690 /* Free the RX lists. */ 5691 bge_free_rx_ring_std(sc); 5692 5693 /* Free jumbo RX list. */ 5694 if (BGE_IS_JUMBO_CAPABLE(sc)) 5695 bge_free_rx_ring_jumbo(sc); 5696 5697 /* Free TX buffers. */ 5698 bge_free_tx_ring(sc); 5699 5700 /* 5701 * Isolate/power down the PHY. 5702 */ 5703 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5704 mii_down(&sc->bge_mii); 5705 5706 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5707 5708 /* Clear MAC's link state (PHY may still have link UP). */ 5709 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5710 5711 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5712 } 5713 5714 static void 5715 bge_link_upd(struct bge_softc *sc) 5716 { 5717 struct ifnet *ifp = &sc->ethercom.ec_if; 5718 struct mii_data *mii = &sc->bge_mii; 5719 uint32_t status; 5720 int link; 5721 5722 /* Clear 'pending link event' flag */ 5723 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5724 5725 /* 5726 * Process link state changes. 5727 * Grrr. The link status word in the status block does 5728 * not work correctly on the BCM5700 rev AX and BX chips, 5729 * according to all available information. Hence, we have 5730 * to enable MII interrupts in order to properly obtain 5731 * async link changes. Unfortunately, this also means that 5732 * we have to read the MAC status register to detect link 5733 * changes, thereby adding an additional register access to 5734 * the interrupt handler. 5735 */ 5736 5737 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5738 status = CSR_READ_4(sc, BGE_MAC_STS); 5739 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5740 mii_pollstat(mii); 5741 5742 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5743 mii->mii_media_status & IFM_ACTIVE && 5744 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5745 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5746 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5747 (!(mii->mii_media_status & IFM_ACTIVE) || 5748 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5749 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5750 5751 /* Clear the interrupt */ 5752 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5753 BGE_EVTENB_MI_INTERRUPT); 5754 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5755 BRGPHY_MII_ISR); 5756 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5757 BRGPHY_MII_IMR, BRGPHY_INTRS); 5758 } 5759 return; 5760 } 5761 5762 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5763 status = CSR_READ_4(sc, BGE_MAC_STS); 5764 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5765 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5766 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5767 if (BGE_ASICREV(sc->bge_chipid) 5768 == BGE_ASICREV_BCM5704) { 5769 BGE_CLRBIT(sc, BGE_MAC_MODE, 5770 BGE_MACMODE_TBI_SEND_CFGS); 5771 DELAY(40); 5772 } 5773 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5774 if_link_state_change(ifp, LINK_STATE_UP); 5775 } 5776 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5777 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5778 if_link_state_change(ifp, LINK_STATE_DOWN); 5779 } 5780 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5781 /* 5782 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5783 * bit in status word always set. Workaround this bug by 5784 * reading PHY link status directly. 5785 */ 5786 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5787 BGE_STS_LINK : 0; 5788 5789 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5790 mii_pollstat(mii); 5791 5792 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5793 mii->mii_media_status & IFM_ACTIVE && 5794 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5795 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5796 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5797 (!(mii->mii_media_status & IFM_ACTIVE) || 5798 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5799 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5800 } 5801 } else { 5802 /* 5803 * For controllers that call mii_tick, we have to poll 5804 * link status. 5805 */ 5806 mii_pollstat(mii); 5807 } 5808 5809 /* Clear the attention */ 5810 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5811 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5812 BGE_MACSTAT_LINK_CHANGED); 5813 } 5814 5815 static int 5816 bge_sysctl_verify(SYSCTLFN_ARGS) 5817 { 5818 int error, t; 5819 struct sysctlnode node; 5820 5821 node = *rnode; 5822 t = *(int*)rnode->sysctl_data; 5823 node.sysctl_data = &t; 5824 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5825 if (error || newp == NULL) 5826 return error; 5827 5828 #if 0 5829 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5830 node.sysctl_num, rnode->sysctl_num)); 5831 #endif 5832 5833 if (node.sysctl_num == bge_rxthresh_nodenum) { 5834 if (t < 0 || t >= NBGE_RX_THRESH) 5835 return EINVAL; 5836 bge_update_all_threshes(t); 5837 } else 5838 return EINVAL; 5839 5840 *(int*)rnode->sysctl_data = t; 5841 5842 return 0; 5843 } 5844 5845 /* 5846 * Set up sysctl(3) MIB, hw.bge.*. 5847 */ 5848 static void 5849 bge_sysctl_init(struct bge_softc *sc) 5850 { 5851 int rc, bge_root_num; 5852 const struct sysctlnode *node; 5853 5854 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5855 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5856 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5857 goto out; 5858 } 5859 5860 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5861 0, CTLTYPE_NODE, "bge", 5862 SYSCTL_DESCR("BGE interface controls"), 5863 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5864 goto out; 5865 } 5866 5867 bge_root_num = node->sysctl_num; 5868 5869 /* BGE Rx interrupt mitigation level */ 5870 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5871 CTLFLAG_READWRITE, 5872 CTLTYPE_INT, "rx_lvl", 5873 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5874 bge_sysctl_verify, 0, 5875 &bge_rx_thresh_lvl, 5876 0, CTL_HW, bge_root_num, CTL_CREATE, 5877 CTL_EOL)) != 0) { 5878 goto out; 5879 } 5880 5881 bge_rxthresh_nodenum = node->sysctl_num; 5882 5883 return; 5884 5885 out: 5886 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5887 } 5888 5889 #ifdef BGE_DEBUG 5890 void 5891 bge_debug_info(struct bge_softc *sc) 5892 { 5893 5894 printf("Hardware Flags:\n"); 5895 if (BGE_IS_57765_PLUS(sc)) 5896 printf(" - 57765 Plus\n"); 5897 if (BGE_IS_5717_PLUS(sc)) 5898 printf(" - 5717 Plus\n"); 5899 if (BGE_IS_5755_PLUS(sc)) 5900 printf(" - 5755 Plus\n"); 5901 if (BGE_IS_575X_PLUS(sc)) 5902 printf(" - 575X Plus\n"); 5903 if (BGE_IS_5705_PLUS(sc)) 5904 printf(" - 5705 Plus\n"); 5905 if (BGE_IS_5714_FAMILY(sc)) 5906 printf(" - 5714 Family\n"); 5907 if (BGE_IS_5700_FAMILY(sc)) 5908 printf(" - 5700 Family\n"); 5909 if (sc->bge_flags & BGE_IS_5788) 5910 printf(" - 5788\n"); 5911 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5912 printf(" - Supports Jumbo Frames\n"); 5913 if (sc->bge_flags & BGE_NO_EEPROM) 5914 printf(" - No EEPROM\n"); 5915 if (sc->bge_flags & BGE_PCIX) 5916 printf(" - PCI-X Bus\n"); 5917 if (sc->bge_flags & BGE_PCIE) 5918 printf(" - PCI Express Bus\n"); 5919 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5920 printf(" - RX Alignment Bug\n"); 5921 if (sc->bge_flags & BGE_APE) 5922 printf(" - APE\n"); 5923 if (sc->bge_flags & BGE_CPMU_PRESENT) 5924 printf(" - CPMU\n"); 5925 if (sc->bge_flags & BGE_TSO) 5926 printf(" - TSO\n"); 5927 5928 if (sc->bge_flags & BGE_PHY_NO_3LED) 5929 printf(" - No 3 LEDs\n"); 5930 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5931 printf(" - CRC bug\n"); 5932 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5933 printf(" - ADC bug\n"); 5934 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5935 printf(" - 5704 A0 bug\n"); 5936 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5937 printf(" - jitter bug\n"); 5938 if (sc->bge_flags & BGE_PHY_BER_BUG) 5939 printf(" - BER bug\n"); 5940 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5941 printf(" - adjust trim\n"); 5942 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5943 printf(" - no wirespeed\n"); 5944 } 5945 #endif /* BGE_DEBUG */ 5946 5947 static int 5948 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5949 { 5950 prop_dictionary_t dict; 5951 prop_data_t ea; 5952 5953 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5954 return 1; 5955 5956 dict = device_properties(sc->bge_dev); 5957 ea = prop_dictionary_get(dict, "mac-address"); 5958 if (ea != NULL) { 5959 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5960 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5961 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5962 return 0; 5963 } 5964 5965 return 1; 5966 } 5967 5968 static int 5969 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5970 { 5971 uint32_t mac_addr; 5972 5973 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5974 if ((mac_addr >> 16) == 0x484b) { 5975 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5976 ether_addr[1] = (uint8_t)mac_addr; 5977 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 5978 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5979 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5980 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5981 ether_addr[5] = (uint8_t)mac_addr; 5982 return 0; 5983 } 5984 return 1; 5985 } 5986 5987 static int 5988 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5989 { 5990 int mac_offset = BGE_EE_MAC_OFFSET; 5991 5992 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5993 mac_offset = BGE_EE_MAC_OFFSET_5906; 5994 5995 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5996 ETHER_ADDR_LEN)); 5997 } 5998 5999 static int 6000 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6001 { 6002 6003 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6004 return 1; 6005 6006 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6007 ETHER_ADDR_LEN)); 6008 } 6009 6010 static int 6011 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6012 { 6013 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6014 /* NOTE: Order is critical */ 6015 bge_get_eaddr_fw, 6016 bge_get_eaddr_mem, 6017 bge_get_eaddr_nvram, 6018 bge_get_eaddr_eeprom, 6019 NULL 6020 }; 6021 const bge_eaddr_fcn_t *func; 6022 6023 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6024 if ((*func)(sc, eaddr) == 0) 6025 break; 6026 } 6027 return (*func == NULL ? ENXIO : 0); 6028 } 6029
Indexes created Thu Sep 25 16:09:42 GMT 2025