if_bge.c revision 1.259
1 /* $NetBSD: if_bge.c,v 1.259 2013/09/12 21:11:37 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.259 2013/09/12 21:11:37 martin Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rnd.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 680 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGE_57765_FAMILY) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 683 684 static const struct bge_revision { 685 uint32_t br_chipid; 686 const char *br_name; 687 } bge_revisions[] = { 688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 743 /* 5754 and 5787 share the same ASIC ID */ 744 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 745 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 746 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 747 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 748 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 749 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 750 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 751 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 752 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 753 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 754 755 { 0, NULL } 756 }; 757 758 /* 759 * Some defaults for major revisions, so that newer steppings 760 * that we don't know about have a shot at working. 761 */ 762 static const struct bge_revision bge_majorrevs[] = { 763 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 764 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 765 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 766 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 767 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 768 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 769 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 772 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 773 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 774 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 775 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 776 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 777 /* 5754 and 5787 share the same ASIC ID */ 778 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 779 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 780 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 781 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 782 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 783 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 784 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 785 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 786 787 { 0, NULL } 788 }; 789 790 static int bge_allow_asf = 1; 791 792 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 793 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 794 795 static uint32_t 796 bge_readmem_ind(struct bge_softc *sc, int off) 797 { 798 pcireg_t val; 799 800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 801 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 802 return 0; 803 804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 805 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 806 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 807 return val; 808 } 809 810 static void 811 bge_writemem_ind(struct bge_softc *sc, int off, int val) 812 { 813 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 817 } 818 819 /* 820 * PCI Express only 821 */ 822 static void 823 bge_set_max_readrq(struct bge_softc *sc) 824 { 825 pcireg_t val; 826 827 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 828 + PCIE_DCSR); 829 val &= ~PCIE_DCSR_MAX_READ_REQ; 830 switch (sc->bge_expmrq) { 831 case 2048: 832 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 833 break; 834 case 4096: 835 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 836 break; 837 default: 838 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 839 break; 840 } 841 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 842 + PCIE_DCSR, val); 843 } 844 845 #ifdef notdef 846 static uint32_t 847 bge_readreg_ind(struct bge_softc *sc, int off) 848 { 849 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 850 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 851 } 852 #endif 853 854 static void 855 bge_writereg_ind(struct bge_softc *sc, int off, int val) 856 { 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 859 } 860 861 static void 862 bge_writemem_direct(struct bge_softc *sc, int off, int val) 863 { 864 CSR_WRITE_4(sc, off, val); 865 } 866 867 static void 868 bge_writembx(struct bge_softc *sc, int off, int val) 869 { 870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 871 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 872 873 CSR_WRITE_4(sc, off, val); 874 } 875 876 static void 877 bge_writembx_flush(struct bge_softc *sc, int off, int val) 878 { 879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 880 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 881 882 CSR_WRITE_4_FLUSH(sc, off, val); 883 } 884 885 /* 886 * Clear all stale locks and select the lock for this driver instance. 887 */ 888 void 889 bge_ape_lock_init(struct bge_softc *sc) 890 { 891 struct pci_attach_args *pa = &(sc->bge_pa); 892 uint32_t bit, regbase; 893 int i; 894 895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 896 regbase = BGE_APE_LOCK_GRANT; 897 else 898 regbase = BGE_APE_PER_LOCK_GRANT; 899 900 /* Clear any stale locks. */ 901 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 902 switch (i) { 903 case BGE_APE_LOCK_PHY0: 904 case BGE_APE_LOCK_PHY1: 905 case BGE_APE_LOCK_PHY2: 906 case BGE_APE_LOCK_PHY3: 907 bit = BGE_APE_LOCK_GRANT_DRIVER0; 908 break; 909 default: 910 if (pa->pa_function == 0) 911 bit = BGE_APE_LOCK_GRANT_DRIVER0; 912 else 913 bit = (1 << pa->pa_function); 914 } 915 APE_WRITE_4(sc, regbase + 4 * i, bit); 916 } 917 918 /* Select the PHY lock based on the device's function number. */ 919 switch (pa->pa_function) { 920 case 0: 921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 922 break; 923 case 1: 924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 925 break; 926 case 2: 927 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 928 break; 929 case 3: 930 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 931 break; 932 default: 933 printf("%s: PHY lock not supported on function\n", 934 device_xname(sc->bge_dev)); 935 break; 936 } 937 } 938 939 /* 940 * Check for APE firmware, set flags, and print version info. 941 */ 942 void 943 bge_ape_read_fw_ver(struct bge_softc *sc) 944 { 945 const char *fwtype; 946 uint32_t apedata, features; 947 948 /* Check for a valid APE signature in shared memory. */ 949 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 950 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 951 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 952 return; 953 } 954 955 /* Check if APE firmware is running. */ 956 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 957 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 958 printf("%s: APE signature found but FW status not ready! " 959 "0x%08x\n", device_xname(sc->bge_dev), apedata); 960 return; 961 } 962 963 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 964 965 /* Fetch the APE firwmare type and version. */ 966 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 967 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 968 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 969 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 970 fwtype = "NCSI"; 971 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 972 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 973 fwtype = "DASH"; 974 } else 975 fwtype = "UNKN"; 976 977 /* Print the APE firmware version. */ 978 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 979 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 980 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 981 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 982 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 983 } 984 985 int 986 bge_ape_lock(struct bge_softc *sc, int locknum) 987 { 988 struct pci_attach_args *pa = &(sc->bge_pa); 989 uint32_t bit, gnt, req, status; 990 int i, off; 991 992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 993 return (0); 994 995 /* Lock request/grant registers have different bases. */ 996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 997 req = BGE_APE_LOCK_REQ; 998 gnt = BGE_APE_LOCK_GRANT; 999 } else { 1000 req = BGE_APE_PER_LOCK_REQ; 1001 gnt = BGE_APE_PER_LOCK_GRANT; 1002 } 1003 1004 off = 4 * locknum; 1005 1006 switch (locknum) { 1007 case BGE_APE_LOCK_GPIO: 1008 /* Lock required when using GPIO. */ 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1010 return (0); 1011 if (pa->pa_function == 0) 1012 bit = BGE_APE_LOCK_REQ_DRIVER0; 1013 else 1014 bit = (1 << pa->pa_function); 1015 break; 1016 case BGE_APE_LOCK_GRC: 1017 /* Lock required to reset the device. */ 1018 if (pa->pa_function == 0) 1019 bit = BGE_APE_LOCK_REQ_DRIVER0; 1020 else 1021 bit = (1 << pa->pa_function); 1022 break; 1023 case BGE_APE_LOCK_MEM: 1024 /* Lock required when accessing certain APE memory. */ 1025 if (pa->pa_function == 0) 1026 bit = BGE_APE_LOCK_REQ_DRIVER0; 1027 else 1028 bit = (1 << pa->pa_function); 1029 break; 1030 case BGE_APE_LOCK_PHY0: 1031 case BGE_APE_LOCK_PHY1: 1032 case BGE_APE_LOCK_PHY2: 1033 case BGE_APE_LOCK_PHY3: 1034 /* Lock required when accessing PHYs. */ 1035 bit = BGE_APE_LOCK_REQ_DRIVER0; 1036 break; 1037 default: 1038 return (EINVAL); 1039 } 1040 1041 /* Request a lock. */ 1042 APE_WRITE_4_FLUSH(sc, req + off, bit); 1043 1044 /* Wait up to 1 second to acquire lock. */ 1045 for (i = 0; i < 20000; i++) { 1046 status = APE_READ_4(sc, gnt + off); 1047 if (status == bit) 1048 break; 1049 DELAY(50); 1050 } 1051 1052 /* Handle any errors. */ 1053 if (status != bit) { 1054 printf("%s: APE lock %d request failed! " 1055 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1056 device_xname(sc->bge_dev), 1057 locknum, req + off, bit & 0xFFFF, gnt + off, 1058 status & 0xFFFF); 1059 /* Revoke the lock request. */ 1060 APE_WRITE_4(sc, gnt + off, bit); 1061 return (EBUSY); 1062 } 1063 1064 return (0); 1065 } 1066 1067 void 1068 bge_ape_unlock(struct bge_softc *sc, int locknum) 1069 { 1070 struct pci_attach_args *pa = &(sc->bge_pa); 1071 uint32_t bit, gnt; 1072 int off; 1073 1074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1075 return; 1076 1077 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1078 gnt = BGE_APE_LOCK_GRANT; 1079 else 1080 gnt = BGE_APE_PER_LOCK_GRANT; 1081 1082 off = 4 * locknum; 1083 1084 switch (locknum) { 1085 case BGE_APE_LOCK_GPIO: 1086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1087 return; 1088 if (pa->pa_function == 0) 1089 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1090 else 1091 bit = (1 << pa->pa_function); 1092 break; 1093 case BGE_APE_LOCK_GRC: 1094 if (pa->pa_function == 0) 1095 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1096 else 1097 bit = (1 << pa->pa_function); 1098 break; 1099 case BGE_APE_LOCK_MEM: 1100 if (pa->pa_function == 0) 1101 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1102 else 1103 bit = (1 << pa->pa_function); 1104 break; 1105 case BGE_APE_LOCK_PHY0: 1106 case BGE_APE_LOCK_PHY1: 1107 case BGE_APE_LOCK_PHY2: 1108 case BGE_APE_LOCK_PHY3: 1109 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1110 break; 1111 default: 1112 return; 1113 } 1114 1115 /* Write and flush for consecutive bge_ape_lock() */ 1116 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1117 } 1118 1119 /* 1120 * Send an event to the APE firmware. 1121 */ 1122 void 1123 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1124 { 1125 uint32_t apedata; 1126 int i; 1127 1128 /* NCSI does not support APE events. */ 1129 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1130 return; 1131 1132 /* Wait up to 1ms for APE to service previous event. */ 1133 for (i = 10; i > 0; i--) { 1134 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1135 break; 1136 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1137 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1138 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1139 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1141 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1142 break; 1143 } 1144 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1145 DELAY(100); 1146 } 1147 if (i == 0) { 1148 printf("%s: APE event 0x%08x send timed out\n", 1149 device_xname(sc->bge_dev), event); 1150 } 1151 } 1152 1153 void 1154 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1155 { 1156 uint32_t apedata, event; 1157 1158 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1159 return; 1160 1161 switch (kind) { 1162 case BGE_RESET_START: 1163 /* If this is the first load, clear the load counter. */ 1164 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1165 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1166 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1167 else { 1168 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1169 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1170 } 1171 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1172 BGE_APE_HOST_SEG_SIG_MAGIC); 1173 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1174 BGE_APE_HOST_SEG_LEN_MAGIC); 1175 1176 /* Add some version info if bge(4) supports it. */ 1177 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1178 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1179 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1180 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1181 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1182 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_START); 1185 event = BGE_APE_EVENT_STATUS_STATE_START; 1186 break; 1187 case BGE_RESET_SHUTDOWN: 1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1189 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1190 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1191 break; 1192 case BGE_RESET_SUSPEND: 1193 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1194 break; 1195 default: 1196 return; 1197 } 1198 1199 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1200 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1201 } 1202 1203 static uint8_t 1204 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1205 { 1206 uint32_t access, byte = 0; 1207 int i; 1208 1209 /* Lock. */ 1210 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1211 for (i = 0; i < 8000; i++) { 1212 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1213 break; 1214 DELAY(20); 1215 } 1216 if (i == 8000) 1217 return 1; 1218 1219 /* Enable access. */ 1220 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1221 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1222 1223 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1224 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1225 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1226 DELAY(10); 1227 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1228 DELAY(10); 1229 break; 1230 } 1231 } 1232 1233 if (i == BGE_TIMEOUT * 10) { 1234 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1235 return 1; 1236 } 1237 1238 /* Get result. */ 1239 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1240 1241 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1242 1243 /* Disable access. */ 1244 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1245 1246 /* Unlock. */ 1247 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Read a sequence of bytes from NVRAM. 1254 */ 1255 static int 1256 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1257 { 1258 int error = 0, i; 1259 uint8_t byte = 0; 1260 1261 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1262 return 1; 1263 1264 for (i = 0; i < cnt; i++) { 1265 error = bge_nvram_getbyte(sc, off + i, &byte); 1266 if (error) 1267 break; 1268 *(dest + i) = byte; 1269 } 1270 1271 return (error ? 1 : 0); 1272 } 1273 1274 /* 1275 * Read a byte of data stored in the EEPROM at address 'addr.' The 1276 * BCM570x supports both the traditional bitbang interface and an 1277 * auto access interface for reading the EEPROM. We use the auto 1278 * access method. 1279 */ 1280 static uint8_t 1281 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1282 { 1283 int i; 1284 uint32_t byte = 0; 1285 1286 /* 1287 * Enable use of auto EEPROM access so we can avoid 1288 * having to use the bitbang method. 1289 */ 1290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1291 1292 /* Reset the EEPROM, load the clock period. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, 1294 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1295 DELAY(20); 1296 1297 /* Issue the read EEPROM command. */ 1298 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1299 1300 /* Wait for completion */ 1301 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1302 DELAY(10); 1303 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1304 break; 1305 } 1306 1307 if (i == BGE_TIMEOUT * 10) { 1308 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1309 return 1; 1310 } 1311 1312 /* Get result. */ 1313 byte = CSR_READ_4(sc, BGE_EE_DATA); 1314 1315 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1316 1317 return 0; 1318 } 1319 1320 /* 1321 * Read a sequence of bytes from the EEPROM. 1322 */ 1323 static int 1324 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1325 { 1326 int error = 0, i; 1327 uint8_t byte = 0; 1328 char *dest = destv; 1329 1330 for (i = 0; i < cnt; i++) { 1331 error = bge_eeprom_getbyte(sc, off + i, &byte); 1332 if (error) 1333 break; 1334 *(dest + i) = byte; 1335 } 1336 1337 return (error ? 1 : 0); 1338 } 1339 1340 static int 1341 bge_miibus_readreg(device_t dev, int phy, int reg) 1342 { 1343 struct bge_softc *sc = device_private(dev); 1344 uint32_t val; 1345 uint32_t autopoll; 1346 int i; 1347 1348 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1349 return 0; 1350 1351 /* Reading with autopolling on may trigger PCI errors */ 1352 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1353 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1354 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1355 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1356 DELAY(80); 1357 } 1358 1359 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1360 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1361 1362 for (i = 0; i < BGE_TIMEOUT; i++) { 1363 delay(10); 1364 val = CSR_READ_4(sc, BGE_MI_COMM); 1365 if (!(val & BGE_MICOMM_BUSY)) { 1366 DELAY(5); 1367 val = CSR_READ_4(sc, BGE_MI_COMM); 1368 break; 1369 } 1370 } 1371 1372 if (i == BGE_TIMEOUT) { 1373 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1374 val = 0; 1375 goto done; 1376 } 1377 1378 done: 1379 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1380 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1381 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1382 DELAY(80); 1383 } 1384 1385 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1386 1387 if (val & BGE_MICOMM_READFAIL) 1388 return 0; 1389 1390 return (val & 0xFFFF); 1391 } 1392 1393 static void 1394 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1395 { 1396 struct bge_softc *sc = device_private(dev); 1397 uint32_t autopoll; 1398 int i; 1399 1400 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1401 return; 1402 1403 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1404 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1405 return; 1406 1407 /* Reading with autopolling on may trigger PCI errors */ 1408 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1409 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1410 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1411 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1412 DELAY(80); 1413 } 1414 1415 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1416 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1417 1418 for (i = 0; i < BGE_TIMEOUT; i++) { 1419 delay(10); 1420 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1421 delay(5); 1422 CSR_READ_4(sc, BGE_MI_COMM); 1423 break; 1424 } 1425 } 1426 1427 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1428 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1429 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1430 delay(80); 1431 } 1432 1433 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1434 1435 if (i == BGE_TIMEOUT) 1436 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1437 } 1438 1439 static void 1440 bge_miibus_statchg(struct ifnet *ifp) 1441 { 1442 struct bge_softc *sc = ifp->if_softc; 1443 struct mii_data *mii = &sc->bge_mii; 1444 uint32_t mac_mode, rx_mode, tx_mode; 1445 1446 /* 1447 * Get flow control negotiation result. 1448 */ 1449 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1450 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1451 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1452 1453 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1454 mii->mii_media_status & IFM_ACTIVE && 1455 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1456 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1457 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1458 (!(mii->mii_media_status & IFM_ACTIVE) || 1459 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1460 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1461 1462 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1463 return; 1464 1465 /* Set the port mode (MII/GMII) to match the link speed. */ 1466 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1467 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1468 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1469 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1470 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1471 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1472 mac_mode |= BGE_PORTMODE_GMII; 1473 else 1474 mac_mode |= BGE_PORTMODE_MII; 1475 1476 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1477 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1478 if ((mii->mii_media_active & IFM_FDX) != 0) { 1479 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1480 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1481 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1482 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1483 } else 1484 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1485 1486 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1487 DELAY(40); 1488 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1489 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1490 } 1491 1492 /* 1493 * Update rx threshold levels to values in a particular slot 1494 * of the interrupt-mitigation table bge_rx_threshes. 1495 */ 1496 static void 1497 bge_set_thresh(struct ifnet *ifp, int lvl) 1498 { 1499 struct bge_softc *sc = ifp->if_softc; 1500 int s; 1501 1502 /* For now, just save the new Rx-intr thresholds and record 1503 * that a threshold update is pending. Updating the hardware 1504 * registers here (even at splhigh()) is observed to 1505 * occasionaly cause glitches where Rx-interrupts are not 1506 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1507 */ 1508 s = splnet(); 1509 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1510 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1511 sc->bge_pending_rxintr_change = 1; 1512 splx(s); 1513 } 1514 1515 1516 /* 1517 * Update Rx thresholds of all bge devices 1518 */ 1519 static void 1520 bge_update_all_threshes(int lvl) 1521 { 1522 struct ifnet *ifp; 1523 const char * const namebuf = "bge"; 1524 int namelen; 1525 1526 if (lvl < 0) 1527 lvl = 0; 1528 else if (lvl >= NBGE_RX_THRESH) 1529 lvl = NBGE_RX_THRESH - 1; 1530 1531 namelen = strlen(namebuf); 1532 /* 1533 * Now search all the interfaces for this name/number 1534 */ 1535 IFNET_FOREACH(ifp) { 1536 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1537 continue; 1538 /* We got a match: update if doing auto-threshold-tuning */ 1539 if (bge_auto_thresh) 1540 bge_set_thresh(ifp, lvl); 1541 } 1542 } 1543 1544 /* 1545 * Handle events that have triggered interrupts. 1546 */ 1547 static void 1548 bge_handle_events(struct bge_softc *sc) 1549 { 1550 1551 return; 1552 } 1553 1554 /* 1555 * Memory management for jumbo frames. 1556 */ 1557 1558 static int 1559 bge_alloc_jumbo_mem(struct bge_softc *sc) 1560 { 1561 char *ptr, *kva; 1562 bus_dma_segment_t seg; 1563 int i, rseg, state, error; 1564 struct bge_jpool_entry *entry; 1565 1566 state = error = 0; 1567 1568 /* Grab a big chunk o' storage. */ 1569 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1570 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1571 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1572 return ENOBUFS; 1573 } 1574 1575 state = 1; 1576 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1577 BUS_DMA_NOWAIT)) { 1578 aprint_error_dev(sc->bge_dev, 1579 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1580 error = ENOBUFS; 1581 goto out; 1582 } 1583 1584 state = 2; 1585 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1586 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1587 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1588 error = ENOBUFS; 1589 goto out; 1590 } 1591 1592 state = 3; 1593 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1594 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1595 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1596 error = ENOBUFS; 1597 goto out; 1598 } 1599 1600 state = 4; 1601 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1602 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1603 1604 SLIST_INIT(&sc->bge_jfree_listhead); 1605 SLIST_INIT(&sc->bge_jinuse_listhead); 1606 1607 /* 1608 * Now divide it up into 9K pieces and save the addresses 1609 * in an array. 1610 */ 1611 ptr = sc->bge_cdata.bge_jumbo_buf; 1612 for (i = 0; i < BGE_JSLOTS; i++) { 1613 sc->bge_cdata.bge_jslots[i] = ptr; 1614 ptr += BGE_JLEN; 1615 entry = malloc(sizeof(struct bge_jpool_entry), 1616 M_DEVBUF, M_NOWAIT); 1617 if (entry == NULL) { 1618 aprint_error_dev(sc->bge_dev, 1619 "no memory for jumbo buffer queue!\n"); 1620 error = ENOBUFS; 1621 goto out; 1622 } 1623 entry->slot = i; 1624 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1625 entry, jpool_entries); 1626 } 1627 out: 1628 if (error != 0) { 1629 switch (state) { 1630 case 4: 1631 bus_dmamap_unload(sc->bge_dmatag, 1632 sc->bge_cdata.bge_rx_jumbo_map); 1633 case 3: 1634 bus_dmamap_destroy(sc->bge_dmatag, 1635 sc->bge_cdata.bge_rx_jumbo_map); 1636 case 2: 1637 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1638 case 1: 1639 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1640 break; 1641 default: 1642 break; 1643 } 1644 } 1645 1646 return error; 1647 } 1648 1649 /* 1650 * Allocate a jumbo buffer. 1651 */ 1652 static void * 1653 bge_jalloc(struct bge_softc *sc) 1654 { 1655 struct bge_jpool_entry *entry; 1656 1657 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1658 1659 if (entry == NULL) { 1660 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1661 return NULL; 1662 } 1663 1664 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1665 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1666 return (sc->bge_cdata.bge_jslots[entry->slot]); 1667 } 1668 1669 /* 1670 * Release a jumbo buffer. 1671 */ 1672 static void 1673 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1674 { 1675 struct bge_jpool_entry *entry; 1676 struct bge_softc *sc; 1677 int i, s; 1678 1679 /* Extract the softc struct pointer. */ 1680 sc = (struct bge_softc *)arg; 1681 1682 if (sc == NULL) 1683 panic("bge_jfree: can't find softc pointer!"); 1684 1685 /* calculate the slot this buffer belongs to */ 1686 1687 i = ((char *)buf 1688 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1689 1690 if ((i < 0) || (i >= BGE_JSLOTS)) 1691 panic("bge_jfree: asked to free buffer that we don't manage!"); 1692 1693 s = splvm(); 1694 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1695 if (entry == NULL) 1696 panic("bge_jfree: buffer not in use!"); 1697 entry->slot = i; 1698 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1699 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1700 1701 if (__predict_true(m != NULL)) 1702 pool_cache_put(mb_cache, m); 1703 splx(s); 1704 } 1705 1706 1707 /* 1708 * Initialize a standard receive ring descriptor. 1709 */ 1710 static int 1711 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1712 bus_dmamap_t dmamap) 1713 { 1714 struct mbuf *m_new = NULL; 1715 struct bge_rx_bd *r; 1716 int error; 1717 1718 if (dmamap == NULL) { 1719 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1720 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1721 if (error != 0) 1722 return error; 1723 } 1724 1725 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1726 1727 if (m == NULL) { 1728 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1729 if (m_new == NULL) 1730 return ENOBUFS; 1731 1732 MCLGET(m_new, M_DONTWAIT); 1733 if (!(m_new->m_flags & M_EXT)) { 1734 m_freem(m_new); 1735 return ENOBUFS; 1736 } 1737 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1738 1739 } else { 1740 m_new = m; 1741 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1742 m_new->m_data = m_new->m_ext.ext_buf; 1743 } 1744 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1745 m_adj(m_new, ETHER_ALIGN); 1746 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1747 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1748 return ENOBUFS; 1749 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1750 BUS_DMASYNC_PREREAD); 1751 1752 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1753 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1754 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1755 r->bge_flags = BGE_RXBDFLAG_END; 1756 r->bge_len = m_new->m_len; 1757 r->bge_idx = i; 1758 1759 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1760 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1761 i * sizeof (struct bge_rx_bd), 1762 sizeof (struct bge_rx_bd), 1763 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1764 1765 return 0; 1766 } 1767 1768 /* 1769 * Initialize a jumbo receive ring descriptor. This allocates 1770 * a jumbo buffer from the pool managed internally by the driver. 1771 */ 1772 static int 1773 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1774 { 1775 struct mbuf *m_new = NULL; 1776 struct bge_rx_bd *r; 1777 void *buf = NULL; 1778 1779 if (m == NULL) { 1780 1781 /* Allocate the mbuf. */ 1782 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1783 if (m_new == NULL) 1784 return ENOBUFS; 1785 1786 /* Allocate the jumbo buffer */ 1787 buf = bge_jalloc(sc); 1788 if (buf == NULL) { 1789 m_freem(m_new); 1790 aprint_error_dev(sc->bge_dev, 1791 "jumbo allocation failed -- packet dropped!\n"); 1792 return ENOBUFS; 1793 } 1794 1795 /* Attach the buffer to the mbuf. */ 1796 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1797 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1798 bge_jfree, sc); 1799 m_new->m_flags |= M_EXT_RW; 1800 } else { 1801 m_new = m; 1802 buf = m_new->m_data = m_new->m_ext.ext_buf; 1803 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1804 } 1805 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1806 m_adj(m_new, ETHER_ALIGN); 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1808 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1809 BUS_DMASYNC_PREREAD); 1810 /* Set up the descriptor. */ 1811 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1812 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1813 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1814 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1815 r->bge_len = m_new->m_len; 1816 r->bge_idx = i; 1817 1818 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1819 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1820 i * sizeof (struct bge_rx_bd), 1821 sizeof (struct bge_rx_bd), 1822 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1823 1824 return 0; 1825 } 1826 1827 /* 1828 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1829 * that's 1MB or memory, which is a lot. For now, we fill only the first 1830 * 256 ring entries and hope that our CPU is fast enough to keep up with 1831 * the NIC. 1832 */ 1833 static int 1834 bge_init_rx_ring_std(struct bge_softc *sc) 1835 { 1836 int i; 1837 1838 if (sc->bge_flags & BGE_RXRING_VALID) 1839 return 0; 1840 1841 for (i = 0; i < BGE_SSLOTS; i++) { 1842 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1843 return ENOBUFS; 1844 } 1845 1846 sc->bge_std = i - 1; 1847 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1848 1849 sc->bge_flags |= BGE_RXRING_VALID; 1850 1851 return 0; 1852 } 1853 1854 static void 1855 bge_free_rx_ring_std(struct bge_softc *sc) 1856 { 1857 int i; 1858 1859 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1860 return; 1861 1862 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1863 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1864 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1865 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1866 bus_dmamap_destroy(sc->bge_dmatag, 1867 sc->bge_cdata.bge_rx_std_map[i]); 1868 } 1869 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1870 sizeof(struct bge_rx_bd)); 1871 } 1872 1873 sc->bge_flags &= ~BGE_RXRING_VALID; 1874 } 1875 1876 static int 1877 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1878 { 1879 int i; 1880 volatile struct bge_rcb *rcb; 1881 1882 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1883 return 0; 1884 1885 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1886 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1887 return ENOBUFS; 1888 } 1889 1890 sc->bge_jumbo = i - 1; 1891 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1892 1893 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1894 rcb->bge_maxlen_flags = 0; 1895 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1896 1897 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1898 1899 return 0; 1900 } 1901 1902 static void 1903 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1904 { 1905 int i; 1906 1907 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1908 return; 1909 1910 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1911 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1912 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1913 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1914 } 1915 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1916 sizeof(struct bge_rx_bd)); 1917 } 1918 1919 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1920 } 1921 1922 static void 1923 bge_free_tx_ring(struct bge_softc *sc) 1924 { 1925 int i; 1926 struct txdmamap_pool_entry *dma; 1927 1928 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1929 return; 1930 1931 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1932 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1933 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1934 sc->bge_cdata.bge_tx_chain[i] = NULL; 1935 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1936 link); 1937 sc->txdma[i] = 0; 1938 } 1939 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1940 sizeof(struct bge_tx_bd)); 1941 } 1942 1943 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1944 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1945 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1946 free(dma, M_DEVBUF); 1947 } 1948 1949 sc->bge_flags &= ~BGE_TXRING_VALID; 1950 } 1951 1952 static int 1953 bge_init_tx_ring(struct bge_softc *sc) 1954 { 1955 struct ifnet *ifp = &sc->ethercom.ec_if; 1956 int i; 1957 bus_dmamap_t dmamap; 1958 bus_size_t maxsegsz; 1959 struct txdmamap_pool_entry *dma; 1960 1961 if (sc->bge_flags & BGE_TXRING_VALID) 1962 return 0; 1963 1964 sc->bge_txcnt = 0; 1965 sc->bge_tx_saved_considx = 0; 1966 1967 /* Initialize transmit producer index for host-memory send ring. */ 1968 sc->bge_tx_prodidx = 0; 1969 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1970 /* 5700 b2 errata */ 1971 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1972 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1973 1974 /* NIC-memory send ring not used; initialize to zero. */ 1975 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1976 /* 5700 b2 errata */ 1977 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1978 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1979 1980 /* Limit DMA segment size for some chips */ 1981 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1982 (ifp->if_mtu <= ETHERMTU)) 1983 maxsegsz = 2048; 1984 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1985 maxsegsz = 4096; 1986 else 1987 maxsegsz = ETHER_MAX_LEN_JUMBO; 1988 SLIST_INIT(&sc->txdma_list); 1989 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1990 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1991 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, 1992 &dmamap)) 1993 return ENOBUFS; 1994 if (dmamap == NULL) 1995 panic("dmamap NULL in bge_init_tx_ring"); 1996 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1997 if (dma == NULL) { 1998 aprint_error_dev(sc->bge_dev, 1999 "can't alloc txdmamap_pool_entry\n"); 2000 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2001 return ENOMEM; 2002 } 2003 dma->dmamap = dmamap; 2004 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2005 } 2006 2007 sc->bge_flags |= BGE_TXRING_VALID; 2008 2009 return 0; 2010 } 2011 2012 static void 2013 bge_setmulti(struct bge_softc *sc) 2014 { 2015 struct ethercom *ac = &sc->ethercom; 2016 struct ifnet *ifp = &ac->ec_if; 2017 struct ether_multi *enm; 2018 struct ether_multistep step; 2019 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2020 uint32_t h; 2021 int i; 2022 2023 if (ifp->if_flags & IFF_PROMISC) 2024 goto allmulti; 2025 2026 /* Now program new ones. */ 2027 ETHER_FIRST_MULTI(step, ac, enm); 2028 while (enm != NULL) { 2029 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2030 /* 2031 * We must listen to a range of multicast addresses. 2032 * For now, just accept all multicasts, rather than 2033 * trying to set only those filter bits needed to match 2034 * the range. (At this time, the only use of address 2035 * ranges is for IP multicast routing, for which the 2036 * range is big enough to require all bits set.) 2037 */ 2038 goto allmulti; 2039 } 2040 2041 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2042 2043 /* Just want the 7 least-significant bits. */ 2044 h &= 0x7f; 2045 2046 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2047 ETHER_NEXT_MULTI(step, enm); 2048 } 2049 2050 ifp->if_flags &= ~IFF_ALLMULTI; 2051 goto setit; 2052 2053 allmulti: 2054 ifp->if_flags |= IFF_ALLMULTI; 2055 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2056 2057 setit: 2058 for (i = 0; i < 4; i++) 2059 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2060 } 2061 2062 static void 2063 bge_sig_pre_reset(struct bge_softc *sc, int type) 2064 { 2065 2066 /* 2067 * Some chips don't like this so only do this if ASF is enabled 2068 */ 2069 if (sc->bge_asf_mode) 2070 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2071 2072 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2073 switch (type) { 2074 case BGE_RESET_START: 2075 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2076 BGE_FW_DRV_STATE_START); 2077 break; 2078 case BGE_RESET_SHUTDOWN: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_UNLOAD); 2081 break; 2082 case BGE_RESET_SUSPEND: 2083 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2084 BGE_FW_DRV_STATE_SUSPEND); 2085 break; 2086 } 2087 } 2088 2089 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2090 bge_ape_driver_state_change(sc, type); 2091 } 2092 2093 static void 2094 bge_sig_post_reset(struct bge_softc *sc, int type) 2095 { 2096 2097 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2098 switch (type) { 2099 case BGE_RESET_START: 2100 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2101 BGE_FW_DRV_STATE_START_DONE); 2102 /* START DONE */ 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD_DONE); 2107 break; 2108 } 2109 } 2110 2111 if (type == BGE_RESET_SHUTDOWN) 2112 bge_ape_driver_state_change(sc, type); 2113 } 2114 2115 static void 2116 bge_sig_legacy(struct bge_softc *sc, int type) 2117 { 2118 2119 if (sc->bge_asf_mode) { 2120 switch (type) { 2121 case BGE_RESET_START: 2122 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2123 BGE_FW_DRV_STATE_START); 2124 break; 2125 case BGE_RESET_SHUTDOWN: 2126 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2127 BGE_FW_DRV_STATE_UNLOAD); 2128 break; 2129 } 2130 } 2131 } 2132 2133 static void 2134 bge_wait_for_event_ack(struct bge_softc *sc) 2135 { 2136 int i; 2137 2138 /* wait up to 2500usec */ 2139 for (i = 0; i < 250; i++) { 2140 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2141 BGE_RX_CPU_DRV_EVENT)) 2142 break; 2143 DELAY(10); 2144 } 2145 } 2146 2147 static void 2148 bge_stop_fw(struct bge_softc *sc) 2149 { 2150 2151 if (sc->bge_asf_mode) { 2152 bge_wait_for_event_ack(sc); 2153 2154 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2155 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2156 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2157 2158 bge_wait_for_event_ack(sc); 2159 } 2160 } 2161 2162 static int 2163 bge_poll_fw(struct bge_softc *sc) 2164 { 2165 uint32_t val; 2166 int i; 2167 2168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2169 for (i = 0; i < BGE_TIMEOUT; i++) { 2170 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2171 if (val & BGE_VCPU_STATUS_INIT_DONE) 2172 break; 2173 DELAY(100); 2174 } 2175 if (i >= BGE_TIMEOUT) { 2176 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2177 return -1; 2178 } 2179 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 2180 /* 2181 * Poll the value location we just wrote until 2182 * we see the 1's complement of the magic number. 2183 * This indicates that the firmware initialization 2184 * is complete. 2185 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2186 */ 2187 for (i = 0; i < BGE_TIMEOUT; i++) { 2188 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2189 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2190 break; 2191 DELAY(10); 2192 } 2193 2194 if (i >= BGE_TIMEOUT) { 2195 aprint_error_dev(sc->bge_dev, 2196 "firmware handshake timed out, val = %x\n", val); 2197 return -1; 2198 } 2199 } 2200 2201 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2202 /* tg3 says we have to wait extra time */ 2203 delay(10 * 1000); 2204 } 2205 2206 return 0; 2207 } 2208 2209 int 2210 bge_phy_addr(struct bge_softc *sc) 2211 { 2212 struct pci_attach_args *pa = &(sc->bge_pa); 2213 int phy_addr = 1; 2214 2215 /* 2216 * PHY address mapping for various devices. 2217 * 2218 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2219 * ---------+-------+-------+-------+-------+ 2220 * BCM57XX | 1 | X | X | X | 2221 * BCM5704 | 1 | X | 1 | X | 2222 * BCM5717 | 1 | 8 | 2 | 9 | 2223 * BCM5719 | 1 | 8 | 2 | 9 | 2224 * BCM5720 | 1 | 8 | 2 | 9 | 2225 * 2226 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2227 * ---------+-------+-------+-------+-------+ 2228 * BCM57XX | X | X | X | X | 2229 * BCM5704 | X | X | X | X | 2230 * BCM5717 | X | X | X | X | 2231 * BCM5719 | 3 | 10 | 4 | 11 | 2232 * BCM5720 | X | X | X | X | 2233 * 2234 * Other addresses may respond but they are not 2235 * IEEE compliant PHYs and should be ignored. 2236 */ 2237 switch (BGE_ASICREV(sc->bge_chipid)) { 2238 case BGE_ASICREV_BCM5717: 2239 case BGE_ASICREV_BCM5719: 2240 case BGE_ASICREV_BCM5720: 2241 phy_addr = pa->pa_function; 2242 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2243 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2244 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2245 } else { 2246 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2247 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2248 } 2249 } 2250 2251 return phy_addr; 2252 } 2253 2254 /* 2255 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2256 * self-test results. 2257 */ 2258 static int 2259 bge_chipinit(struct bge_softc *sc) 2260 { 2261 uint32_t dma_rw_ctl, mode_ctl, reg; 2262 int i; 2263 2264 /* Set endianness before we access any non-PCI registers. */ 2265 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2266 BGE_INIT); 2267 2268 /* 2269 * Clear the MAC statistics block in the NIC's 2270 * internal memory. 2271 */ 2272 for (i = BGE_STATS_BLOCK; 2273 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2274 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2275 2276 for (i = BGE_STATUS_BLOCK; 2277 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2278 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2279 2280 /* 5717 workaround from tg3 */ 2281 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2282 /* Save */ 2283 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2284 2285 /* Temporary modify MODE_CTL to control TLP */ 2286 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2287 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2288 2289 /* Control TLP */ 2290 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2291 BGE_TLP_PHYCTL1); 2292 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2293 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2294 2295 /* Restore */ 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2297 } 2298 2299 if (BGE_IS_57765_FAMILY(sc)) { 2300 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2301 /* Save */ 2302 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2303 2304 /* Temporary modify MODE_CTL to control TLP */ 2305 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2306 CSR_WRITE_4(sc, BGE_MODE_CTL, 2307 reg | BGE_MODECTL_PCIE_TLPADDR1); 2308 2309 /* Control TLP */ 2310 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2311 BGE_TLP_PHYCTL5); 2312 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2313 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2314 2315 /* Restore */ 2316 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2317 } 2318 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2319 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2320 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2321 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2322 2323 /* Save */ 2324 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2325 2326 /* Temporary modify MODE_CTL to control TLP */ 2327 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2328 CSR_WRITE_4(sc, BGE_MODE_CTL, 2329 reg | BGE_MODECTL_PCIE_TLPADDR0); 2330 2331 /* Control TLP */ 2332 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2333 BGE_TLP_FTSMAX); 2334 reg &= ~BGE_TLP_FTSMAX_MSK; 2335 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2336 reg | BGE_TLP_FTSMAX_VAL); 2337 2338 /* Restore */ 2339 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2340 } 2341 2342 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2343 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2344 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2345 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2346 } 2347 2348 /* Set up the PCI DMA control register. */ 2349 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2350 if (sc->bge_flags & BGE_PCIE) { 2351 /* Read watermark not used, 128 bytes for write. */ 2352 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2353 device_xname(sc->bge_dev))); 2354 if (sc->bge_mps >= 256) 2355 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2356 else 2357 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2358 } else if (sc->bge_flags & BGE_PCIX) { 2359 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2360 device_xname(sc->bge_dev))); 2361 /* PCI-X bus */ 2362 if (BGE_IS_5714_FAMILY(sc)) { 2363 /* 256 bytes for read and write. */ 2364 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2365 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2366 2367 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2368 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2369 else 2370 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2371 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2372 /* 1536 bytes for read, 384 bytes for write. */ 2373 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2374 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2375 } else { 2376 /* 384 bytes for read and write. */ 2377 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2378 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2379 (0x0F); 2380 } 2381 2382 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2383 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2384 uint32_t tmp; 2385 2386 /* Set ONEDMA_ATONCE for hardware workaround. */ 2387 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2388 if (tmp == 6 || tmp == 7) 2389 dma_rw_ctl |= 2390 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2391 2392 /* Set PCI-X DMA write workaround. */ 2393 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2394 } 2395 } else { 2396 /* Conventional PCI bus: 256 bytes for read and write. */ 2397 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2398 device_xname(sc->bge_dev))); 2399 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2400 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2401 2402 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2403 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2404 dma_rw_ctl |= 0x0F; 2405 } 2406 2407 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2408 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2409 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2410 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2411 2412 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2413 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2414 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2415 2416 if (BGE_IS_57765_PLUS(sc)) { 2417 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2418 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2419 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2420 2421 /* 2422 * Enable HW workaround for controllers that misinterpret 2423 * a status tag update and leave interrupts permanently 2424 * disabled. 2425 */ 2426 if (!BGE_IS_57765_FAMILY(sc) && 2427 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2428 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2429 } 2430 2431 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2432 dma_rw_ctl); 2433 2434 /* 2435 * Set up general mode register. 2436 */ 2437 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2438 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2439 /* Retain Host-2-BMC settings written by APE firmware. */ 2440 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2441 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2442 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2443 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2444 } 2445 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2446 BGE_MODECTL_TX_NO_PHDR_CSUM; 2447 2448 /* 2449 * BCM5701 B5 have a bug causing data corruption when using 2450 * 64-bit DMA reads, which can be terminated early and then 2451 * completed later as 32-bit accesses, in combination with 2452 * certain bridges. 2453 */ 2454 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2455 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2456 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2457 2458 /* 2459 * Tell the firmware the driver is running 2460 */ 2461 if (sc->bge_asf_mode & ASF_STACKUP) 2462 mode_ctl |= BGE_MODECTL_STACKUP; 2463 2464 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2465 2466 /* 2467 * Disable memory write invalidate. Apparently it is not supported 2468 * properly by these devices. 2469 */ 2470 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2471 PCI_COMMAND_INVALIDATE_ENABLE); 2472 2473 #ifdef __brokenalpha__ 2474 /* 2475 * Must insure that we do not cross an 8K (bytes) boundary 2476 * for DMA reads. Our highest limit is 1K bytes. This is a 2477 * restriction on some ALPHA platforms with early revision 2478 * 21174 PCI chipsets, such as the AlphaPC 164lx 2479 */ 2480 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2481 #endif 2482 2483 /* Set the timer prescaler (always 66MHz) */ 2484 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2485 2486 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2487 DELAY(40); /* XXX */ 2488 2489 /* Put PHY into ready state */ 2490 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2491 DELAY(40); 2492 } 2493 2494 return 0; 2495 } 2496 2497 static int 2498 bge_blockinit(struct bge_softc *sc) 2499 { 2500 volatile struct bge_rcb *rcb; 2501 bus_size_t rcb_addr; 2502 struct ifnet *ifp = &sc->ethercom.ec_if; 2503 bge_hostaddr taddr; 2504 uint32_t dmactl, val; 2505 int i, limit; 2506 2507 /* 2508 * Initialize the memory window pointer register so that 2509 * we can access the first 32K of internal NIC RAM. This will 2510 * allow us to set up the TX send ring RCBs and the RX return 2511 * ring RCBs, plus other things which live in NIC memory. 2512 */ 2513 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2514 2515 if (!BGE_IS_5705_PLUS(sc)) { 2516 /* 57XX step 33 */ 2517 /* Configure mbuf memory pool */ 2518 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2519 BGE_BUFFPOOL_1); 2520 2521 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2522 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2523 else 2524 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2525 2526 /* 57XX step 34 */ 2527 /* Configure DMA resource pool */ 2528 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2529 BGE_DMA_DESCRIPTORS); 2530 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2531 } 2532 2533 /* 5718 step 11, 57XX step 35 */ 2534 /* 2535 * Configure mbuf pool watermarks. New broadcom docs strongly 2536 * recommend these. 2537 */ 2538 if (BGE_IS_5717_PLUS(sc)) { 2539 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2540 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2541 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2542 } else if (BGE_IS_5705_PLUS(sc)) { 2543 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2544 2545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2546 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2547 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2548 } else { 2549 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2550 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2551 } 2552 } else { 2553 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2554 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2555 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2556 } 2557 2558 /* 57XX step 36 */ 2559 /* Configure DMA resource watermarks */ 2560 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2561 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2562 2563 /* 5718 step 13, 57XX step 38 */ 2564 /* Enable buffer manager */ 2565 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2566 /* 2567 * Change the arbitration algorithm of TXMBUF read request to 2568 * round-robin instead of priority based for BCM5719. When 2569 * TXFIFO is almost empty, RDMA will hold its request until 2570 * TXFIFO is not almost empty. 2571 */ 2572 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2573 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2574 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2575 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2576 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2577 val |= BGE_BMANMODE_LOMBUF_ATTN; 2578 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2579 2580 /* 57XX step 39 */ 2581 /* Poll for buffer manager start indication */ 2582 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2583 DELAY(10); 2584 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2585 break; 2586 } 2587 2588 if (i == BGE_TIMEOUT * 2) { 2589 aprint_error_dev(sc->bge_dev, 2590 "buffer manager failed to start\n"); 2591 return ENXIO; 2592 } 2593 2594 /* 57XX step 40 */ 2595 /* Enable flow-through queues */ 2596 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2597 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2598 2599 /* Wait until queue initialization is complete */ 2600 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2601 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2602 break; 2603 DELAY(10); 2604 } 2605 2606 if (i == BGE_TIMEOUT * 2) { 2607 aprint_error_dev(sc->bge_dev, 2608 "flow-through queue init failed\n"); 2609 return ENXIO; 2610 } 2611 2612 /* 2613 * Summary of rings supported by the controller: 2614 * 2615 * Standard Receive Producer Ring 2616 * - This ring is used to feed receive buffers for "standard" 2617 * sized frames (typically 1536 bytes) to the controller. 2618 * 2619 * Jumbo Receive Producer Ring 2620 * - This ring is used to feed receive buffers for jumbo sized 2621 * frames (i.e. anything bigger than the "standard" frames) 2622 * to the controller. 2623 * 2624 * Mini Receive Producer Ring 2625 * - This ring is used to feed receive buffers for "mini" 2626 * sized frames to the controller. 2627 * - This feature required external memory for the controller 2628 * but was never used in a production system. Should always 2629 * be disabled. 2630 * 2631 * Receive Return Ring 2632 * - After the controller has placed an incoming frame into a 2633 * receive buffer that buffer is moved into a receive return 2634 * ring. The driver is then responsible to passing the 2635 * buffer up to the stack. Many versions of the controller 2636 * support multiple RR rings. 2637 * 2638 * Send Ring 2639 * - This ring is used for outgoing frames. Many versions of 2640 * the controller support multiple send rings. 2641 */ 2642 2643 /* 5718 step 15, 57XX step 41 */ 2644 /* Initialize the standard RX ring control block */ 2645 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2646 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2647 /* 5718 step 16 */ 2648 if (BGE_IS_57765_PLUS(sc)) { 2649 /* 2650 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2651 * Bits 15-2 : Maximum RX frame size 2652 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2653 * Bit 0 : Reserved 2654 */ 2655 rcb->bge_maxlen_flags = 2656 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2657 } else if (BGE_IS_5705_PLUS(sc)) { 2658 /* 2659 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2660 * Bits 15-2 : Reserved (should be 0) 2661 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2662 * Bit 0 : Reserved 2663 */ 2664 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2665 } else { 2666 /* 2667 * Ring size is always XXX entries 2668 * Bits 31-16: Maximum RX frame size 2669 * Bits 15-2 : Reserved (should be 0) 2670 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2671 * Bit 0 : Reserved 2672 */ 2673 rcb->bge_maxlen_flags = 2674 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2675 } 2676 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2677 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2678 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2679 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2680 else 2681 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2682 /* Write the standard receive producer ring control block. */ 2683 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2684 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2685 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2686 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2687 2688 /* Reset the standard receive producer ring producer index. */ 2689 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2690 2691 /* 57XX step 42 */ 2692 /* 2693 * Initialize the jumbo RX ring control block 2694 * We set the 'ring disabled' bit in the flags 2695 * field until we're actually ready to start 2696 * using this ring (i.e. once we set the MTU 2697 * high enough to require it). 2698 */ 2699 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2700 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2701 BGE_HOSTADDR(rcb->bge_hostaddr, 2702 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2703 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2704 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2705 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2706 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2707 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2708 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2709 else 2710 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2711 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2712 rcb->bge_hostaddr.bge_addr_hi); 2713 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2714 rcb->bge_hostaddr.bge_addr_lo); 2715 /* Program the jumbo receive producer ring RCB parameters. */ 2716 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2717 rcb->bge_maxlen_flags); 2718 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2719 /* Reset the jumbo receive producer ring producer index. */ 2720 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2721 } 2722 2723 /* 57XX step 43 */ 2724 /* Disable the mini receive producer ring RCB. */ 2725 if (BGE_IS_5700_FAMILY(sc)) { 2726 /* Set up dummy disabled mini ring RCB */ 2727 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2728 rcb->bge_maxlen_flags = 2729 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2730 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2731 rcb->bge_maxlen_flags); 2732 /* Reset the mini receive producer ring producer index. */ 2733 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2734 2735 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2736 offsetof(struct bge_ring_data, bge_info), 2737 sizeof (struct bge_gib), 2738 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2739 } 2740 2741 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2742 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2743 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2744 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2745 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2746 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2747 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2748 } 2749 /* 5718 step 14, 57XX step 44 */ 2750 /* 2751 * The BD ring replenish thresholds control how often the 2752 * hardware fetches new BD's from the producer rings in host 2753 * memory. Setting the value too low on a busy system can 2754 * starve the hardware and recue the throughpout. 2755 * 2756 * Set the BD ring replenish thresholds. The recommended 2757 * values are 1/8th the number of descriptors allocated to 2758 * each ring, but since we try to avoid filling the entire 2759 * ring we set these to the minimal value of 8. This needs to 2760 * be done on several of the supported chip revisions anyway, 2761 * to work around HW bugs. 2762 */ 2763 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2764 if (BGE_IS_JUMBO_CAPABLE(sc)) 2765 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2766 2767 /* 5718 step 18 */ 2768 if (BGE_IS_5717_PLUS(sc)) { 2769 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2770 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2771 } 2772 2773 /* 57XX step 45 */ 2774 /* 2775 * Disable all send rings by setting the 'ring disabled' bit 2776 * in the flags field of all the TX send ring control blocks, 2777 * located in NIC memory. 2778 */ 2779 if (BGE_IS_5700_FAMILY(sc)) { 2780 /* 5700 to 5704 had 16 send rings. */ 2781 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2782 } else if (BGE_IS_5717_PLUS(sc)) { 2783 limit = BGE_TX_RINGS_5717_MAX; 2784 } else if (BGE_IS_57765_FAMILY(sc)) { 2785 limit = BGE_TX_RINGS_57765_MAX; 2786 } else 2787 limit = 1; 2788 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2789 for (i = 0; i < limit; i++) { 2790 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2791 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2792 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2793 rcb_addr += sizeof(struct bge_rcb); 2794 } 2795 2796 /* 57XX step 46 and 47 */ 2797 /* Configure send ring RCB 0 (we use only the first ring) */ 2798 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2799 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2800 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2801 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2802 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2803 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2804 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2805 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2806 else 2807 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2808 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2809 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2810 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2811 2812 /* 57XX step 48 */ 2813 /* 2814 * Disable all receive return rings by setting the 2815 * 'ring diabled' bit in the flags field of all the receive 2816 * return ring control blocks, located in NIC memory. 2817 */ 2818 if (BGE_IS_5717_PLUS(sc)) { 2819 /* Should be 17, use 16 until we get an SRAM map. */ 2820 limit = 16; 2821 } else if (BGE_IS_5700_FAMILY(sc)) 2822 limit = BGE_RX_RINGS_MAX; 2823 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2824 BGE_IS_57765_FAMILY(sc)) 2825 limit = 4; 2826 else 2827 limit = 1; 2828 /* Disable all receive return rings */ 2829 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2830 for (i = 0; i < limit; i++) { 2831 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2832 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2833 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2834 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2835 BGE_RCB_FLAG_RING_DISABLED)); 2836 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2837 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2838 (i * (sizeof(uint64_t))), 0); 2839 rcb_addr += sizeof(struct bge_rcb); 2840 } 2841 2842 /* 57XX step 49 */ 2843 /* 2844 * Set up receive return ring 0. Note that the NIC address 2845 * for RX return rings is 0x0. The return rings live entirely 2846 * within the host, so the nicaddr field in the RCB isn't used. 2847 */ 2848 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2849 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2850 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2851 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2852 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2853 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2854 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2855 2856 /* 5718 step 24, 57XX step 53 */ 2857 /* Set random backoff seed for TX */ 2858 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2859 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2860 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2861 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2862 BGE_TX_BACKOFF_SEED_MASK); 2863 2864 /* 5718 step 26, 57XX step 55 */ 2865 /* Set inter-packet gap */ 2866 val = 0x2620; 2867 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2868 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2869 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2870 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2871 2872 /* 5718 step 27, 57XX step 56 */ 2873 /* 2874 * Specify which ring to use for packets that don't match 2875 * any RX rules. 2876 */ 2877 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2878 2879 /* 5718 step 28, 57XX step 57 */ 2880 /* 2881 * Configure number of RX lists. One interrupt distribution 2882 * list, sixteen active lists, one bad frames class. 2883 */ 2884 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2885 2886 /* 5718 step 29, 57XX step 58 */ 2887 /* Inialize RX list placement stats mask. */ 2888 if (BGE_IS_575X_PLUS(sc)) { 2889 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2890 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2891 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2892 } else 2893 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2894 2895 /* 5718 step 30, 57XX step 59 */ 2896 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2897 2898 /* 5718 step 33, 57XX step 62 */ 2899 /* Disable host coalescing until we get it set up */ 2900 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2901 2902 /* 5718 step 34, 57XX step 63 */ 2903 /* Poll to make sure it's shut down. */ 2904 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2905 DELAY(10); 2906 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2907 break; 2908 } 2909 2910 if (i == BGE_TIMEOUT * 2) { 2911 aprint_error_dev(sc->bge_dev, 2912 "host coalescing engine failed to idle\n"); 2913 return ENXIO; 2914 } 2915 2916 /* 5718 step 35, 36, 37 */ 2917 /* Set up host coalescing defaults */ 2918 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2919 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2920 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2921 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2922 if (!(BGE_IS_5705_PLUS(sc))) { 2923 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2924 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2925 } 2926 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2927 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2928 2929 /* Set up address of statistics block */ 2930 if (BGE_IS_5700_FAMILY(sc)) { 2931 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2932 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2933 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2934 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2935 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2936 } 2937 2938 /* 5718 step 38 */ 2939 /* Set up address of status block */ 2940 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2941 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2942 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2943 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2944 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2945 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2946 2947 /* Set up status block size. */ 2948 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2949 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2950 val = BGE_STATBLKSZ_FULL; 2951 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2952 } else { 2953 val = BGE_STATBLKSZ_32BYTE; 2954 bzero(&sc->bge_rdata->bge_status_block, 32); 2955 } 2956 2957 /* 5718 step 39, 57XX step 73 */ 2958 /* Turn on host coalescing state machine */ 2959 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2960 2961 /* 5718 step 40, 57XX step 74 */ 2962 /* Turn on RX BD completion state machine and enable attentions */ 2963 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2964 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2965 2966 /* 5718 step 41, 57XX step 75 */ 2967 /* Turn on RX list placement state machine */ 2968 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2969 2970 /* 57XX step 76 */ 2971 /* Turn on RX list selector state machine. */ 2972 if (!(BGE_IS_5705_PLUS(sc))) 2973 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2974 2975 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2976 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2977 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2978 BGE_MACMODE_FRMHDR_DMA_ENB; 2979 2980 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2981 val |= BGE_PORTMODE_TBI; 2982 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2983 val |= BGE_PORTMODE_GMII; 2984 else 2985 val |= BGE_PORTMODE_MII; 2986 2987 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2988 /* Allow APE to send/receive frames. */ 2989 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2990 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2991 2992 /* Turn on DMA, clear stats */ 2993 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2994 /* 5718 step 44 */ 2995 DELAY(40); 2996 2997 /* 5718 step 45, 57XX step 79 */ 2998 /* Set misc. local control, enable interrupts on attentions */ 2999 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3000 if (BGE_IS_5717_PLUS(sc)) { 3001 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3002 /* 5718 step 46 */ 3003 DELAY(100); 3004 } 3005 3006 /* 57XX step 81 */ 3007 /* Turn on DMA completion state machine */ 3008 if (!(BGE_IS_5705_PLUS(sc))) 3009 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3010 3011 /* 5718 step 47, 57XX step 82 */ 3012 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3013 3014 /* 5718 step 48 */ 3015 /* Enable host coalescing bug fix. */ 3016 if (BGE_IS_5755_PLUS(sc)) 3017 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3018 3019 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3020 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3021 3022 /* Turn on write DMA state machine */ 3023 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3024 /* 5718 step 49 */ 3025 DELAY(40); 3026 3027 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3028 3029 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3030 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3031 3032 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3033 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3034 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3035 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3036 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3037 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3038 3039 if (sc->bge_flags & BGE_PCIE) 3040 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3041 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3042 if (ifp->if_mtu <= ETHERMTU) 3043 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3044 } 3045 if (sc->bge_flags & BGE_TSO) 3046 val |= BGE_RDMAMODE_TSO4_ENABLE; 3047 3048 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3049 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3050 BGE_RDMAMODE_H2BNC_VLAN_DET; 3051 /* 3052 * Allow multiple outstanding read requests from 3053 * non-LSO read DMA engine. 3054 */ 3055 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3056 } 3057 3058 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3059 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3060 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3061 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3062 BGE_IS_57765_PLUS(sc)) { 3063 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3064 /* 3065 * Adjust tx margin to prevent TX data corruption and 3066 * fix internal FIFO overflow. 3067 */ 3068 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3069 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3070 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3071 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3072 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3073 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3074 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3075 } 3076 /* 3077 * Enable fix for read DMA FIFO overruns. 3078 * The fix is to limit the number of RX BDs 3079 * the hardware would fetch at a fime. 3080 */ 3081 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3082 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3083 } 3084 3085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3086 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3087 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3088 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3089 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3090 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3091 /* 3092 * Allow 4KB burst length reads for non-LSO frames. 3093 * Enable 512B burst length reads for buffer descriptors. 3094 */ 3095 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3096 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3097 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3098 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3099 } 3100 3101 /* Turn on read DMA state machine */ 3102 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3103 /* 5718 step 52 */ 3104 delay(40); 3105 3106 /* 5718 step 56, 57XX step 84 */ 3107 /* Turn on RX data completion state machine */ 3108 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3109 3110 /* Turn on RX data and RX BD initiator state machine */ 3111 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3112 3113 /* 57XX step 85 */ 3114 /* Turn on Mbuf cluster free state machine */ 3115 if (!BGE_IS_5705_PLUS(sc)) 3116 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3117 3118 /* 5718 step 57, 57XX step 86 */ 3119 /* Turn on send data completion state machine */ 3120 val = BGE_SDCMODE_ENABLE; 3121 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3122 val |= BGE_SDCMODE_CDELAY; 3123 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3124 3125 /* 5718 step 58 */ 3126 /* Turn on send BD completion state machine */ 3127 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3128 3129 /* 57XX step 88 */ 3130 /* Turn on RX BD initiator state machine */ 3131 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3132 3133 /* 5718 step 60, 57XX step 90 */ 3134 /* Turn on send data initiator state machine */ 3135 if (sc->bge_flags & BGE_TSO) { 3136 /* XXX: magic value from Linux driver */ 3137 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3138 BGE_SDIMODE_HW_LSO_PRE_DMA); 3139 } else 3140 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3141 3142 /* 5718 step 61, 57XX step 91 */ 3143 /* Turn on send BD initiator state machine */ 3144 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3145 3146 /* 5718 step 62, 57XX step 92 */ 3147 /* Turn on send BD selector state machine */ 3148 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3149 3150 /* 5718 step 31, 57XX step 60 */ 3151 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3152 /* 5718 step 32, 57XX step 61 */ 3153 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3154 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3155 3156 /* ack/clear link change events */ 3157 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3158 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3159 BGE_MACSTAT_LINK_CHANGED); 3160 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3161 3162 /* 3163 * Enable attention when the link has changed state for 3164 * devices that use auto polling. 3165 */ 3166 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3167 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3168 } else { 3169 /* 5718 step 68 */ 3170 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3171 /* 5718 step 69 (optionally) */ 3172 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3173 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3174 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3175 BGE_EVTENB_MI_INTERRUPT); 3176 } 3177 3178 /* 3179 * Clear any pending link state attention. 3180 * Otherwise some link state change events may be lost until attention 3181 * is cleared by bge_intr() -> bge_link_upd() sequence. 3182 * It's not necessary on newer BCM chips - perhaps enabling link 3183 * state change attentions implies clearing pending attention. 3184 */ 3185 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3186 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3187 BGE_MACSTAT_LINK_CHANGED); 3188 3189 /* Enable link state change attentions. */ 3190 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3191 3192 return 0; 3193 } 3194 3195 static const struct bge_revision * 3196 bge_lookup_rev(uint32_t chipid) 3197 { 3198 const struct bge_revision *br; 3199 3200 for (br = bge_revisions; br->br_name != NULL; br++) { 3201 if (br->br_chipid == chipid) 3202 return br; 3203 } 3204 3205 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3206 if (br->br_chipid == BGE_ASICREV(chipid)) 3207 return br; 3208 } 3209 3210 return NULL; 3211 } 3212 3213 static const struct bge_product * 3214 bge_lookup(const struct pci_attach_args *pa) 3215 { 3216 const struct bge_product *bp; 3217 3218 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3219 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3220 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3221 return bp; 3222 } 3223 3224 return NULL; 3225 } 3226 3227 static uint32_t 3228 bge_chipid(const struct pci_attach_args *pa) 3229 { 3230 uint32_t id; 3231 3232 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3233 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3234 3235 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3236 switch (PCI_PRODUCT(pa->pa_id)) { 3237 case PCI_PRODUCT_BROADCOM_BCM5717: 3238 case PCI_PRODUCT_BROADCOM_BCM5718: 3239 case PCI_PRODUCT_BROADCOM_BCM5719: 3240 case PCI_PRODUCT_BROADCOM_BCM5720: 3241 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3242 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3243 BGE_PCI_GEN2_PRODID_ASICREV); 3244 break; 3245 case PCI_PRODUCT_BROADCOM_BCM57761: 3246 case PCI_PRODUCT_BROADCOM_BCM57762: 3247 case PCI_PRODUCT_BROADCOM_BCM57765: 3248 case PCI_PRODUCT_BROADCOM_BCM57766: 3249 case PCI_PRODUCT_BROADCOM_BCM57781: 3250 case PCI_PRODUCT_BROADCOM_BCM57785: 3251 case PCI_PRODUCT_BROADCOM_BCM57791: 3252 case PCI_PRODUCT_BROADCOM_BCM57795: 3253 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3254 BGE_PCI_GEN15_PRODID_ASICREV); 3255 break; 3256 default: 3257 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3258 BGE_PCI_PRODID_ASICREV); 3259 break; 3260 } 3261 } 3262 3263 return id; 3264 } 3265 3266 /* 3267 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3268 * against our list and return its name if we find a match. Note 3269 * that since the Broadcom controller contains VPD support, we 3270 * can get the device name string from the controller itself instead 3271 * of the compiled-in string. This is a little slow, but it guarantees 3272 * we'll always announce the right product name. 3273 */ 3274 static int 3275 bge_probe(device_t parent, cfdata_t match, void *aux) 3276 { 3277 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3278 3279 if (bge_lookup(pa) != NULL) 3280 return 1; 3281 3282 return 0; 3283 } 3284 3285 static void 3286 bge_attach(device_t parent, device_t self, void *aux) 3287 { 3288 struct bge_softc *sc = device_private(self); 3289 struct pci_attach_args *pa = aux; 3290 prop_dictionary_t dict; 3291 const struct bge_product *bp; 3292 const struct bge_revision *br; 3293 pci_chipset_tag_t pc; 3294 pci_intr_handle_t ih; 3295 const char *intrstr = NULL; 3296 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4; 3297 uint32_t command; 3298 struct ifnet *ifp; 3299 uint32_t misccfg, mimode; 3300 void * kva; 3301 u_char eaddr[ETHER_ADDR_LEN]; 3302 pcireg_t memtype, subid, reg; 3303 bus_addr_t memaddr; 3304 uint32_t pm_ctl; 3305 bool no_seeprom; 3306 int capmask; 3307 3308 bp = bge_lookup(pa); 3309 KASSERT(bp != NULL); 3310 3311 sc->sc_pc = pa->pa_pc; 3312 sc->sc_pcitag = pa->pa_tag; 3313 sc->bge_dev = self; 3314 3315 sc->bge_pa = *pa; 3316 pc = sc->sc_pc; 3317 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3318 3319 aprint_naive(": Ethernet controller\n"); 3320 aprint_normal(": %s\n", bp->bp_name); 3321 3322 /* 3323 * Map control/status registers. 3324 */ 3325 DPRINTFN(5, ("Map control/status regs\n")); 3326 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3327 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3328 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3329 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3330 3331 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3332 aprint_error_dev(sc->bge_dev, 3333 "failed to enable memory mapping!\n"); 3334 return; 3335 } 3336 3337 DPRINTFN(5, ("pci_mem_find\n")); 3338 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3339 switch (memtype) { 3340 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3341 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3342 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3343 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3344 &memaddr, &sc->bge_bsize) == 0) 3345 break; 3346 default: 3347 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3348 return; 3349 } 3350 3351 DPRINTFN(5, ("pci_intr_map\n")); 3352 if (pci_intr_map(pa, &ih)) { 3353 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3354 return; 3355 } 3356 3357 DPRINTFN(5, ("pci_intr_string\n")); 3358 intrstr = pci_intr_string(pc, ih); 3359 3360 DPRINTFN(5, ("pci_intr_establish\n")); 3361 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3362 3363 if (sc->bge_intrhand == NULL) { 3364 aprint_error_dev(sc->bge_dev, 3365 "couldn't establish interrupt%s%s\n", 3366 intrstr ? " at " : "", intrstr ? intrstr : ""); 3367 return; 3368 } 3369 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3370 3371 /* Save various chip information. */ 3372 sc->bge_chipid = bge_chipid(pa); 3373 sc->bge_phy_addr = bge_phy_addr(sc); 3374 3375 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3376 &sc->bge_pciecap, NULL) != 0) 3377 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3378 /* PCIe */ 3379 sc->bge_flags |= BGE_PCIE; 3380 /* Extract supported maximum payload size. */ 3381 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3382 sc->bge_pciecap + PCIE_DCAP); 3383 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3384 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3385 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3386 sc->bge_expmrq = 2048; 3387 else 3388 sc->bge_expmrq = 4096; 3389 bge_set_max_readrq(sc); 3390 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3391 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3392 /* PCI-X */ 3393 sc->bge_flags |= BGE_PCIX; 3394 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3395 &sc->bge_pcixcap, NULL) == 0) 3396 aprint_error_dev(sc->bge_dev, 3397 "unable to find PCIX capability\n"); 3398 } 3399 3400 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3401 /* 3402 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3403 * can clobber the chip's PCI config-space power control 3404 * registers, leaving the card in D3 powersave state. We do 3405 * not have memory-mapped registers in this state, so force 3406 * device into D0 state before starting initialization. 3407 */ 3408 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3409 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3410 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3411 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3412 DELAY(1000); /* 27 usec is allegedly sufficent */ 3413 } 3414 3415 /* Save chipset family. */ 3416 switch (BGE_ASICREV(sc->bge_chipid)) { 3417 case BGE_ASICREV_BCM5717: 3418 case BGE_ASICREV_BCM5719: 3419 case BGE_ASICREV_BCM5720: 3420 sc->bge_flags |= BGE_5717_PLUS; 3421 /* FALLTHROUGH */ 3422 case BGE_ASICREV_BCM57765: 3423 case BGE_ASICREV_BCM57766: 3424 if (!BGE_IS_5717_PLUS(sc)) 3425 sc->bge_flags |= BGE_57765_FAMILY; 3426 sc->bge_flags |= BGE_57765_PLUS | BGE_5755_PLUS | 3427 BGE_575X_PLUS | BGE_5705_PLUS | BGE_JUMBO_CAPABLE; 3428 /* Jumbo frame on BCM5719 A0 does not work. */ 3429 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3430 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3431 sc->bge_flags &= ~BGE_JUMBO_CAPABLE; 3432 break; 3433 case BGE_ASICREV_BCM5755: 3434 case BGE_ASICREV_BCM5761: 3435 case BGE_ASICREV_BCM5784: 3436 case BGE_ASICREV_BCM5785: 3437 case BGE_ASICREV_BCM5787: 3438 case BGE_ASICREV_BCM57780: 3439 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 3440 break; 3441 case BGE_ASICREV_BCM5700: 3442 case BGE_ASICREV_BCM5701: 3443 case BGE_ASICREV_BCM5703: 3444 case BGE_ASICREV_BCM5704: 3445 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; 3446 break; 3447 case BGE_ASICREV_BCM5714_A0: 3448 case BGE_ASICREV_BCM5780: 3449 case BGE_ASICREV_BCM5714: 3450 sc->bge_flags |= BGE_5714_FAMILY | BGE_JUMBO_CAPABLE; 3451 /* FALLTHROUGH */ 3452 case BGE_ASICREV_BCM5750: 3453 case BGE_ASICREV_BCM5752: 3454 case BGE_ASICREV_BCM5906: 3455 sc->bge_flags |= BGE_575X_PLUS; 3456 /* FALLTHROUGH */ 3457 case BGE_ASICREV_BCM5705: 3458 sc->bge_flags |= BGE_5705_PLUS; 3459 break; 3460 } 3461 3462 /* Identify chips with APE processor. */ 3463 switch (BGE_ASICREV(sc->bge_chipid)) { 3464 case BGE_ASICREV_BCM5717: 3465 case BGE_ASICREV_BCM5719: 3466 case BGE_ASICREV_BCM5720: 3467 case BGE_ASICREV_BCM5761: 3468 sc->bge_flags |= BGE_APE; 3469 break; 3470 } 3471 3472 /* Chips with APE need BAR2 access for APE registers/memory. */ 3473 if ((sc->bge_flags & BGE_APE) != 0) { 3474 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3475 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3476 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3477 &sc->bge_apesize)) { 3478 aprint_error_dev(sc->bge_dev, 3479 "couldn't map BAR2 memory\n"); 3480 return; 3481 } 3482 3483 /* Enable APE register/memory access by host driver. */ 3484 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3485 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3486 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3487 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3488 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3489 3490 bge_ape_lock_init(sc); 3491 bge_ape_read_fw_ver(sc); 3492 } 3493 3494 /* Identify the chips that use an CPMU. */ 3495 if (BGE_IS_5717_PLUS(sc) || 3496 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3497 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3498 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3499 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3500 sc->bge_flags |= BGE_CPMU_PRESENT; 3501 3502 /* Set MI_MODE */ 3503 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3504 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 3505 mimode |= BGE_MIMODE_500KHZ_CONST; 3506 else 3507 mimode |= BGE_MIMODE_BASE; 3508 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3509 3510 /* 3511 * When using the BCM5701 in PCI-X mode, data corruption has 3512 * been observed in the first few bytes of some received packets. 3513 * Aligning the packet buffer in memory eliminates the corruption. 3514 * Unfortunately, this misaligns the packet payloads. On platforms 3515 * which do not support unaligned accesses, we will realign the 3516 * payloads by copying the received packets. 3517 */ 3518 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3519 sc->bge_flags & BGE_PCIX) 3520 sc->bge_flags |= BGE_RX_ALIGNBUG; 3521 3522 if (BGE_IS_5700_FAMILY(sc)) 3523 sc->bge_flags |= BGE_JUMBO_CAPABLE; 3524 3525 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3526 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3527 3528 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3529 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3530 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3531 sc->bge_flags |= BGE_IS_5788; 3532 3533 /* 3534 * Some controllers seem to require a special firmware to use 3535 * TSO. But the firmware is not available to FreeBSD and Linux 3536 * claims that the TSO performed by the firmware is slower than 3537 * hardware based TSO. Moreover the firmware based TSO has one 3538 * known bug which can't handle TSO if ethernet header + IP/TCP 3539 * header is greater than 80 bytes. The workaround for the TSO 3540 * bug exist but it seems it's too expensive than not using 3541 * TSO at all. Some hardwares also have the TSO bug so limit 3542 * the TSO to the controllers that are not affected TSO issues 3543 * (e.g. 5755 or higher). 3544 */ 3545 if (BGE_IS_5755_PLUS(sc)) { 3546 /* 3547 * BCM5754 and BCM5787 shares the same ASIC id so 3548 * explicit device id check is required. 3549 */ 3550 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3551 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3552 sc->bge_flags |= BGE_TSO; 3553 } 3554 3555 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3556 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3557 (misccfg == 0x4000 || misccfg == 0x8000)) || 3558 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3559 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3560 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3561 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3562 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3563 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3564 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3565 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3566 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3567 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3568 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3569 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3570 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3571 capmask &= ~BMSR_EXTSTAT; 3572 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3573 } 3574 3575 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3576 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3577 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3578 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3579 sc->bge_flags |= BGE_PHY_NO_WIRESPEED; 3580 3581 /* Set various PHY bug flags. */ 3582 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3583 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3584 sc->bge_flags |= BGE_PHY_CRC_BUG; 3585 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3586 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3587 sc->bge_flags |= BGE_PHY_ADC_BUG; 3588 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3589 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 3590 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3591 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3592 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3593 sc->bge_flags |= BGE_PHY_NO_3LED; 3594 if (BGE_IS_5705_PLUS(sc) && 3595 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3596 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3597 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3598 !BGE_IS_57765_PLUS(sc)) { 3599 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3600 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3601 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3602 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3603 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3604 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3605 sc->bge_flags |= BGE_PHY_JITTER_BUG; 3606 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3607 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 3608 } else 3609 sc->bge_flags |= BGE_PHY_BER_BUG; 3610 } 3611 3612 /* 3613 * SEEPROM check. 3614 * First check if firmware knows we do not have SEEPROM. 3615 */ 3616 if (prop_dictionary_get_bool(device_properties(self), 3617 "without-seeprom", &no_seeprom) && no_seeprom) 3618 sc->bge_flags |= BGE_NO_EEPROM; 3619 3620 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3621 sc->bge_flags |= BGE_NO_EEPROM; 3622 3623 /* Now check the 'ROM failed' bit on the RX CPU */ 3624 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3625 sc->bge_flags |= BGE_NO_EEPROM; 3626 3627 sc->bge_asf_mode = 0; 3628 /* No ASF if APE present. */ 3629 if ((sc->bge_flags & BGE_APE) == 0) { 3630 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3631 BGE_SRAM_DATA_SIG_MAGIC)) { 3632 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3633 BGE_HWCFG_ASF) { 3634 sc->bge_asf_mode |= ASF_ENABLE; 3635 sc->bge_asf_mode |= ASF_STACKUP; 3636 if (BGE_IS_575X_PLUS(sc)) 3637 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3638 } 3639 } 3640 } 3641 3642 /* 3643 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3644 * lock in bge_reset(). 3645 */ 3646 CSR_WRITE_4(sc, BGE_EE_ADDR, 3647 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3648 delay(1000); 3649 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3650 3651 bge_stop_fw(sc); 3652 bge_sig_pre_reset(sc, BGE_RESET_START); 3653 if (bge_reset(sc)) 3654 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3655 3656 /* 3657 * Read the hardware config word in the first 32k of NIC internal 3658 * memory, or fall back to the config word in the EEPROM. 3659 * Note: on some BCM5700 cards, this value appears to be unset. 3660 */ 3661 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = 0; 3662 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3663 BGE_SRAM_DATA_SIG_MAGIC) { 3664 uint32_t tmp; 3665 3666 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3667 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3668 BGE_SRAM_DATA_VER_SHIFT; 3669 if ((0 < tmp) && (tmp < 0x100)) 3670 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3671 if (sc->bge_flags & BGE_PCIE) 3672 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3673 if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) 3674 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3675 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3676 bge_read_eeprom(sc, (void *)&hwcfg, 3677 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3678 hwcfg = be32toh(hwcfg); 3679 } 3680 aprint_normal_dev(sc->bge_dev, "HW config %08x, %08x, %08x, %08x\n", 3681 hwcfg, hwcfg2, hwcfg3, hwcfg4); 3682 3683 bge_sig_legacy(sc, BGE_RESET_START); 3684 bge_sig_post_reset(sc, BGE_RESET_START); 3685 3686 if (bge_chipinit(sc)) { 3687 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3688 bge_release_resources(sc); 3689 return; 3690 } 3691 3692 /* 3693 * Get station address from the EEPROM. 3694 */ 3695 if (bge_get_eaddr(sc, eaddr)) { 3696 aprint_error_dev(sc->bge_dev, 3697 "failed to read station address\n"); 3698 bge_release_resources(sc); 3699 return; 3700 } 3701 3702 br = bge_lookup_rev(sc->bge_chipid); 3703 3704 if (br == NULL) { 3705 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3706 sc->bge_chipid); 3707 } else { 3708 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3709 br->br_name, sc->bge_chipid); 3710 } 3711 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3712 3713 /* Allocate the general information block and ring buffers. */ 3714 if (pci_dma64_available(pa)) 3715 sc->bge_dmatag = pa->pa_dmat64; 3716 else 3717 sc->bge_dmatag = pa->pa_dmat; 3718 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3719 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3720 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3721 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3722 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3723 return; 3724 } 3725 DPRINTFN(5, ("bus_dmamem_map\n")); 3726 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3727 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3728 BUS_DMA_NOWAIT)) { 3729 aprint_error_dev(sc->bge_dev, 3730 "can't map DMA buffers (%zu bytes)\n", 3731 sizeof(struct bge_ring_data)); 3732 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3733 sc->bge_ring_rseg); 3734 return; 3735 } 3736 DPRINTFN(5, ("bus_dmamem_create\n")); 3737 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3738 sizeof(struct bge_ring_data), 0, 3739 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3740 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3741 bus_dmamem_unmap(sc->bge_dmatag, kva, 3742 sizeof(struct bge_ring_data)); 3743 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3744 sc->bge_ring_rseg); 3745 return; 3746 } 3747 DPRINTFN(5, ("bus_dmamem_load\n")); 3748 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3749 sizeof(struct bge_ring_data), NULL, 3750 BUS_DMA_NOWAIT)) { 3751 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3752 bus_dmamem_unmap(sc->bge_dmatag, kva, 3753 sizeof(struct bge_ring_data)); 3754 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3755 sc->bge_ring_rseg); 3756 return; 3757 } 3758 3759 DPRINTFN(5, ("bzero\n")); 3760 sc->bge_rdata = (struct bge_ring_data *)kva; 3761 3762 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3763 3764 /* Try to allocate memory for jumbo buffers. */ 3765 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3766 if (bge_alloc_jumbo_mem(sc)) { 3767 aprint_error_dev(sc->bge_dev, 3768 "jumbo buffer allocation failed\n"); 3769 } else 3770 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3771 } 3772 3773 /* Set default tuneable values. */ 3774 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3775 sc->bge_rx_coal_ticks = 150; 3776 sc->bge_rx_max_coal_bds = 64; 3777 sc->bge_tx_coal_ticks = 300; 3778 sc->bge_tx_max_coal_bds = 400; 3779 if (BGE_IS_5705_PLUS(sc)) { 3780 sc->bge_tx_coal_ticks = (12 * 5); 3781 sc->bge_tx_max_coal_bds = (12 * 5); 3782 aprint_verbose_dev(sc->bge_dev, 3783 "setting short Tx thresholds\n"); 3784 } 3785 3786 if (BGE_IS_5717_PLUS(sc)) 3787 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3788 else if (BGE_IS_5705_PLUS(sc)) 3789 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3790 else 3791 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3792 3793 /* Set up ifnet structure */ 3794 ifp = &sc->ethercom.ec_if; 3795 ifp->if_softc = sc; 3796 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3797 ifp->if_ioctl = bge_ioctl; 3798 ifp->if_stop = bge_stop; 3799 ifp->if_start = bge_start; 3800 ifp->if_init = bge_init; 3801 ifp->if_watchdog = bge_watchdog; 3802 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3803 IFQ_SET_READY(&ifp->if_snd); 3804 DPRINTFN(5, ("strcpy if_xname\n")); 3805 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3806 3807 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3808 sc->ethercom.ec_if.if_capabilities |= 3809 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3810 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3811 sc->ethercom.ec_if.if_capabilities |= 3812 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3813 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3814 #endif 3815 sc->ethercom.ec_capabilities |= 3816 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3817 3818 if (sc->bge_flags & BGE_TSO) 3819 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3820 3821 /* 3822 * Do MII setup. 3823 */ 3824 DPRINTFN(5, ("mii setup\n")); 3825 sc->bge_mii.mii_ifp = ifp; 3826 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3827 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3828 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3829 3830 /* 3831 * Figure out what sort of media we have by checking the hardware 3832 * config word. Note: on some BCM5700 cards, this value appears to be 3833 * unset. If that's the case, we have to rely on identifying the NIC 3834 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3835 * The SysKonnect SK-9D41 is a 1000baseSX card. 3836 */ 3837 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3838 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3839 if (BGE_IS_5714_FAMILY(sc)) 3840 sc->bge_flags |= BGE_PHY_FIBER_MII; 3841 else 3842 sc->bge_flags |= BGE_PHY_FIBER_TBI; 3843 } 3844 3845 /* set phyflags and chipid before mii_attach() */ 3846 dict = device_properties(self); 3847 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 3848 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3849 3850 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3851 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3852 bge_ifmedia_sts); 3853 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3854 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3855 0, NULL); 3856 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3857 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3858 /* Pretend the user requested this setting */ 3859 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3860 } else { 3861 /* 3862 * Do transceiver setup and tell the firmware the 3863 * driver is down so we can try to get access the 3864 * probe if ASF is running. Retry a couple of times 3865 * if we get a conflict with the ASF firmware accessing 3866 * the PHY. 3867 */ 3868 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3869 bge_asf_driver_up(sc); 3870 3871 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3872 bge_ifmedia_sts); 3873 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3874 sc->bge_phy_addr, MII_OFFSET_ANY, 3875 MIIF_DOPAUSE); 3876 3877 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3878 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3879 ifmedia_add(&sc->bge_mii.mii_media, 3880 IFM_ETHER|IFM_MANUAL, 0, NULL); 3881 ifmedia_set(&sc->bge_mii.mii_media, 3882 IFM_ETHER|IFM_MANUAL); 3883 } else 3884 ifmedia_set(&sc->bge_mii.mii_media, 3885 IFM_ETHER|IFM_AUTO); 3886 3887 /* 3888 * Now tell the firmware we are going up after probing the PHY 3889 */ 3890 if (sc->bge_asf_mode & ASF_STACKUP) 3891 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3892 } 3893 3894 /* 3895 * Call MI attach routine. 3896 */ 3897 DPRINTFN(5, ("if_attach\n")); 3898 if_attach(ifp); 3899 DPRINTFN(5, ("ether_ifattach\n")); 3900 ether_ifattach(ifp, eaddr); 3901 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3902 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3903 RND_TYPE_NET, 0); 3904 #ifdef BGE_EVENT_COUNTERS 3905 /* 3906 * Attach event counters. 3907 */ 3908 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3909 NULL, device_xname(sc->bge_dev), "intr"); 3910 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3911 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3912 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3913 NULL, device_xname(sc->bge_dev), "tx_xon"); 3914 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3915 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3916 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3917 NULL, device_xname(sc->bge_dev), "rx_xon"); 3918 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3919 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3920 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3921 NULL, device_xname(sc->bge_dev), "xoffentered"); 3922 #endif /* BGE_EVENT_COUNTERS */ 3923 DPRINTFN(5, ("callout_init\n")); 3924 callout_init(&sc->bge_timeout, 0); 3925 3926 if (pmf_device_register(self, NULL, NULL)) 3927 pmf_class_network_register(self, ifp); 3928 else 3929 aprint_error_dev(self, "couldn't establish power handler\n"); 3930 3931 bge_sysctl_init(sc); 3932 3933 #ifdef BGE_DEBUG 3934 bge_debug_info(sc); 3935 #endif 3936 } 3937 3938 /* 3939 * Stop all chip I/O so that the kernel's probe routines don't 3940 * get confused by errant DMAs when rebooting. 3941 */ 3942 static int 3943 bge_detach(device_t self, int flags __unused) 3944 { 3945 struct bge_softc *sc = device_private(self); 3946 struct ifnet *ifp = &sc->ethercom.ec_if; 3947 int s; 3948 3949 s = splnet(); 3950 /* Stop the interface. Callouts are stopped in it. */ 3951 bge_stop(ifp, 1); 3952 splx(s); 3953 3954 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3955 3956 /* Delete all remaining media. */ 3957 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3958 3959 ether_ifdetach(ifp); 3960 if_detach(ifp); 3961 3962 bge_release_resources(sc); 3963 3964 return 0; 3965 } 3966 3967 static void 3968 bge_release_resources(struct bge_softc *sc) 3969 { 3970 3971 /* Disestablish the interrupt handler */ 3972 if (sc->bge_intrhand != NULL) { 3973 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3974 sc->bge_intrhand = NULL; 3975 } 3976 3977 if (sc->bge_dmatag != NULL) { 3978 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3979 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3980 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3981 sizeof(struct bge_ring_data)); 3982 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3983 } 3984 3985 /* Unmap the device registers */ 3986 if (sc->bge_bsize != 0) { 3987 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3988 sc->bge_bsize = 0; 3989 } 3990 3991 /* Unmap the APE registers */ 3992 if (sc->bge_apesize != 0) { 3993 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3994 sc->bge_apesize); 3995 sc->bge_apesize = 0; 3996 } 3997 } 3998 3999 static int 4000 bge_reset(struct bge_softc *sc) 4001 { 4002 uint32_t cachesize, command; 4003 uint32_t reset, mac_mode, mac_mode_mask; 4004 pcireg_t devctl, reg; 4005 int i, val; 4006 void (*write_op)(struct bge_softc *, int, int); 4007 4008 /* Make mask for BGE_MAC_MODE register. */ 4009 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4010 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4011 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4012 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4013 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4014 4015 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4016 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4017 if (sc->bge_flags & BGE_PCIE) 4018 write_op = bge_writemem_direct; 4019 else 4020 write_op = bge_writemem_ind; 4021 } else 4022 write_op = bge_writereg_ind; 4023 4024 /* 57XX step 4 */ 4025 /* Acquire the NVM lock */ 4026 if ((sc->bge_flags & BGE_NO_EEPROM) == 0 && 4027 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4028 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4029 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4030 for (i = 0; i < 8000; i++) { 4031 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4032 BGE_NVRAMSWARB_GNT1) 4033 break; 4034 DELAY(20); 4035 } 4036 if (i == 8000) { 4037 printf("%s: NVRAM lock timedout!\n", 4038 device_xname(sc->bge_dev)); 4039 } 4040 } 4041 4042 /* Take APE lock when performing reset. */ 4043 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4044 4045 /* 57XX step 3 */ 4046 /* Save some important PCI state. */ 4047 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4048 /* 5718 reset step 3 */ 4049 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4050 4051 /* 5718 reset step 5, 57XX step 5b-5d */ 4052 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4053 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4054 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4055 4056 /* XXX ???: Disable fastboot on controllers that support it. */ 4057 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4058 BGE_IS_5755_PLUS(sc)) 4059 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4060 4061 /* 5718 reset step 2, 57XX step 6 */ 4062 /* 4063 * Write the magic number to SRAM at offset 0xB50. 4064 * When firmware finishes its initialization it will 4065 * write ~BGE_MAGIC_NUMBER to the same location. 4066 */ 4067 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4068 4069 /* 5718 reset step 6, 57XX step 7 */ 4070 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4071 /* 4072 * XXX: from FreeBSD/Linux; no documentation 4073 */ 4074 if (sc->bge_flags & BGE_PCIE) { 4075 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 4076 !BGE_IS_57765_PLUS(sc) && 4077 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4078 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4079 /* PCI Express 1.0 system */ 4080 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4081 BGE_PHY_PCIE_SCRAM_MODE); 4082 } 4083 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4084 /* 4085 * Prevent PCI Express link training 4086 * during global reset. 4087 */ 4088 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4089 reset |= (1 << 29); 4090 } 4091 } 4092 4093 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4094 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4095 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4096 i | BGE_VCPU_STATUS_DRV_RESET); 4097 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4098 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4099 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4100 } 4101 4102 /* 4103 * Set GPHY Power Down Override to leave GPHY 4104 * powered up in D0 uninitialized. 4105 */ 4106 if (BGE_IS_5705_PLUS(sc) && 4107 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4108 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4109 4110 /* Issue global reset */ 4111 write_op(sc, BGE_MISC_CFG, reset); 4112 4113 /* 5718 reset step 7, 57XX step 8 */ 4114 if (sc->bge_flags & BGE_PCIE) 4115 delay(100*1000); /* too big */ 4116 else 4117 delay(1000); 4118 4119 if (sc->bge_flags & BGE_PCIE) { 4120 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4121 DELAY(500000); 4122 /* XXX: Magic Numbers */ 4123 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4124 BGE_PCI_UNKNOWN0); 4125 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4126 BGE_PCI_UNKNOWN0, 4127 reg | (1 << 15)); 4128 } 4129 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4130 sc->bge_pciecap + PCIE_DCSR); 4131 /* Clear enable no snoop and disable relaxed ordering. */ 4132 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4133 PCIE_DCSR_ENA_NO_SNOOP); 4134 4135 /* Set PCIE max payload size to 128 for older PCIe devices */ 4136 if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) 4137 devctl &= ~(0x00e0); 4138 /* Clear device status register. Write 1b to clear */ 4139 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4140 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4141 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4142 sc->bge_pciecap + PCIE_DCSR, devctl); 4143 bge_set_max_readrq(sc); 4144 } 4145 4146 /* From Linux: dummy read to flush PCI posted writes */ 4147 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4148 4149 /* 4150 * Reset some of the PCI state that got zapped by reset 4151 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4152 * set, too. 4153 */ 4154 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4155 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4156 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4157 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4158 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4159 (sc->bge_flags & BGE_PCIX) != 0) 4160 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4161 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4162 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4163 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4164 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4165 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4166 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4167 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4168 4169 /* Step 11: disable PCI-X Relaxed Ordering. */ 4170 if (sc->bge_flags & BGE_PCIX) { 4171 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4172 + PCIX_CMD); 4173 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4174 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4175 } 4176 4177 /* 5718 reset step 10, 57XX step 12 */ 4178 /* Enable memory arbiter. */ 4179 if (BGE_IS_5714_FAMILY(sc)) { 4180 val = CSR_READ_4(sc, BGE_MARB_MODE); 4181 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4182 } else 4183 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4184 4185 /* XXX 5721, 5751 and 5752 */ 4186 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4187 /* Step 19: */ 4188 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4189 /* Step 20: */ 4190 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4191 } 4192 4193 /* 5718 reset step 13, 57XX step 17 */ 4194 /* Poll until the firmware initialization is complete */ 4195 bge_poll_fw(sc); 4196 4197 /* 5718 reset step 12, 57XX step 15 and 16 */ 4198 /* Fix up byte swapping */ 4199 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4200 4201 /* 57XX step 21 */ 4202 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4203 pcireg_t msidata; 4204 4205 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4206 BGE_PCI_MSI_DATA); 4207 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4208 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4209 msidata); 4210 } 4211 4212 /* 57XX step 18 */ 4213 /* Write mac mode. */ 4214 val = CSR_READ_4(sc, BGE_MAC_MODE); 4215 /* Restore mac_mode_mask's bits using mac_mode */ 4216 val = (val & ~mac_mode_mask) | mac_mode; 4217 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4218 DELAY(40); 4219 4220 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4221 4222 /* 4223 * The 5704 in TBI mode apparently needs some special 4224 * adjustment to insure the SERDES drive level is set 4225 * to 1.2V. 4226 */ 4227 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 4228 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4229 uint32_t serdescfg; 4230 4231 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4232 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4233 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4234 } 4235 4236 if (sc->bge_flags & BGE_PCIE && 4237 !BGE_IS_57765_PLUS(sc) && 4238 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4239 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4240 uint32_t v; 4241 4242 /* Enable PCI Express bug fix */ 4243 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4244 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4245 v | BGE_TLP_DATA_FIFO_PROTECT); 4246 } 4247 4248 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4249 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4250 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4251 4252 return 0; 4253 } 4254 4255 /* 4256 * Frame reception handling. This is called if there's a frame 4257 * on the receive return list. 4258 * 4259 * Note: we have to be able to handle two possibilities here: 4260 * 1) the frame is from the jumbo receive ring 4261 * 2) the frame is from the standard receive ring 4262 */ 4263 4264 static void 4265 bge_rxeof(struct bge_softc *sc) 4266 { 4267 struct ifnet *ifp; 4268 uint16_t rx_prod, rx_cons; 4269 int stdcnt = 0, jumbocnt = 0; 4270 bus_dmamap_t dmamap; 4271 bus_addr_t offset, toff; 4272 bus_size_t tlen; 4273 int tosync; 4274 4275 rx_cons = sc->bge_rx_saved_considx; 4276 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4277 4278 /* Nothing to do */ 4279 if (rx_cons == rx_prod) 4280 return; 4281 4282 ifp = &sc->ethercom.ec_if; 4283 4284 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4285 offsetof(struct bge_ring_data, bge_status_block), 4286 sizeof (struct bge_status_block), 4287 BUS_DMASYNC_POSTREAD); 4288 4289 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4290 tosync = rx_prod - rx_cons; 4291 4292 if (tosync != 0) 4293 rnd_add_uint32(&sc->rnd_source, tosync); 4294 4295 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4296 4297 if (tosync < 0) { 4298 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4299 sizeof (struct bge_rx_bd); 4300 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4301 toff, tlen, BUS_DMASYNC_POSTREAD); 4302 tosync = -tosync; 4303 } 4304 4305 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4306 offset, tosync * sizeof (struct bge_rx_bd), 4307 BUS_DMASYNC_POSTREAD); 4308 4309 while (rx_cons != rx_prod) { 4310 struct bge_rx_bd *cur_rx; 4311 uint32_t rxidx; 4312 struct mbuf *m = NULL; 4313 4314 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4315 4316 rxidx = cur_rx->bge_idx; 4317 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4318 4319 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4320 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4321 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4322 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4323 jumbocnt++; 4324 bus_dmamap_sync(sc->bge_dmatag, 4325 sc->bge_cdata.bge_rx_jumbo_map, 4326 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4327 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4328 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4329 ifp->if_ierrors++; 4330 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4331 continue; 4332 } 4333 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4334 NULL)== ENOBUFS) { 4335 ifp->if_ierrors++; 4336 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4337 continue; 4338 } 4339 } else { 4340 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4341 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4342 4343 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4344 stdcnt++; 4345 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4346 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4347 if (dmamap == NULL) { 4348 ifp->if_ierrors++; 4349 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4350 continue; 4351 } 4352 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4353 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4354 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4355 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4356 ifp->if_ierrors++; 4357 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4358 continue; 4359 } 4360 if (bge_newbuf_std(sc, sc->bge_std, 4361 NULL, dmamap) == ENOBUFS) { 4362 ifp->if_ierrors++; 4363 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4364 continue; 4365 } 4366 } 4367 4368 ifp->if_ipackets++; 4369 #ifndef __NO_STRICT_ALIGNMENT 4370 /* 4371 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4372 * the Rx buffer has the layer-2 header unaligned. 4373 * If our CPU requires alignment, re-align by copying. 4374 */ 4375 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 4376 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4377 cur_rx->bge_len); 4378 m->m_data += ETHER_ALIGN; 4379 } 4380 #endif 4381 4382 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4383 m->m_pkthdr.rcvif = ifp; 4384 4385 /* 4386 * Handle BPF listeners. Let the BPF user see the packet. 4387 */ 4388 bpf_mtap(ifp, m); 4389 4390 bge_rxcsum(sc, cur_rx, m); 4391 4392 /* 4393 * If we received a packet with a vlan tag, pass it 4394 * to vlan_input() instead of ether_input(). 4395 */ 4396 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4397 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4398 } 4399 4400 (*ifp->if_input)(ifp, m); 4401 } 4402 4403 sc->bge_rx_saved_considx = rx_cons; 4404 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4405 if (stdcnt) 4406 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4407 if (jumbocnt) 4408 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4409 } 4410 4411 static void 4412 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4413 { 4414 4415 if (BGE_IS_57765_PLUS(sc)) { 4416 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4417 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4418 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4419 if ((cur_rx->bge_error_flag & 4420 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4421 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4422 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4423 m->m_pkthdr.csum_data = 4424 cur_rx->bge_tcp_udp_csum; 4425 m->m_pkthdr.csum_flags |= 4426 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4427 M_CSUM_DATA); 4428 } 4429 } 4430 } else { 4431 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4432 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4433 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4434 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4435 /* 4436 * Rx transport checksum-offload may also 4437 * have bugs with packets which, when transmitted, 4438 * were `runts' requiring padding. 4439 */ 4440 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4441 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4442 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4443 m->m_pkthdr.csum_data = 4444 cur_rx->bge_tcp_udp_csum; 4445 m->m_pkthdr.csum_flags |= 4446 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4447 M_CSUM_DATA); 4448 } 4449 } 4450 } 4451 4452 static void 4453 bge_txeof(struct bge_softc *sc) 4454 { 4455 struct bge_tx_bd *cur_tx = NULL; 4456 struct ifnet *ifp; 4457 struct txdmamap_pool_entry *dma; 4458 bus_addr_t offset, toff; 4459 bus_size_t tlen; 4460 int tosync; 4461 struct mbuf *m; 4462 4463 ifp = &sc->ethercom.ec_if; 4464 4465 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4466 offsetof(struct bge_ring_data, bge_status_block), 4467 sizeof (struct bge_status_block), 4468 BUS_DMASYNC_POSTREAD); 4469 4470 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4471 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4472 sc->bge_tx_saved_considx; 4473 4474 if (tosync != 0) 4475 rnd_add_uint32(&sc->rnd_source, tosync); 4476 4477 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4478 4479 if (tosync < 0) { 4480 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4481 sizeof (struct bge_tx_bd); 4482 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4483 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4484 tosync = -tosync; 4485 } 4486 4487 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4488 offset, tosync * sizeof (struct bge_tx_bd), 4489 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4490 4491 /* 4492 * Go through our tx ring and free mbufs for those 4493 * frames that have been sent. 4494 */ 4495 while (sc->bge_tx_saved_considx != 4496 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4497 uint32_t idx = 0; 4498 4499 idx = sc->bge_tx_saved_considx; 4500 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4501 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4502 ifp->if_opackets++; 4503 m = sc->bge_cdata.bge_tx_chain[idx]; 4504 if (m != NULL) { 4505 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4506 dma = sc->txdma[idx]; 4507 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4508 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4509 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4510 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4511 sc->txdma[idx] = NULL; 4512 4513 m_freem(m); 4514 } 4515 sc->bge_txcnt--; 4516 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4517 ifp->if_timer = 0; 4518 } 4519 4520 if (cur_tx != NULL) 4521 ifp->if_flags &= ~IFF_OACTIVE; 4522 } 4523 4524 static int 4525 bge_intr(void *xsc) 4526 { 4527 struct bge_softc *sc; 4528 struct ifnet *ifp; 4529 uint32_t statusword; 4530 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4531 4532 sc = xsc; 4533 ifp = &sc->ethercom.ec_if; 4534 4535 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4536 if (BGE_IS_5717_PLUS(sc)) 4537 intrmask = 0; 4538 4539 /* It is possible for the interrupt to arrive before 4540 * the status block is updated prior to the interrupt. 4541 * Reading the PCI State register will confirm whether the 4542 * interrupt is ours and will flush the status block. 4543 */ 4544 4545 /* read status word from status block */ 4546 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4547 offsetof(struct bge_ring_data, bge_status_block), 4548 sizeof (struct bge_status_block), 4549 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4550 statusword = sc->bge_rdata->bge_status_block.bge_status; 4551 4552 if ((statusword & BGE_STATFLAG_UPDATED) || 4553 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) { 4554 /* Ack interrupt and stop others from occuring. */ 4555 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4556 4557 BGE_EVCNT_INCR(sc->bge_ev_intr); 4558 4559 /* clear status word */ 4560 sc->bge_rdata->bge_status_block.bge_status = 0; 4561 4562 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4563 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4564 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4565 bge_link_upd(sc); 4566 4567 if (ifp->if_flags & IFF_RUNNING) { 4568 /* Check RX return ring producer/consumer */ 4569 bge_rxeof(sc); 4570 4571 /* Check TX ring producer/consumer */ 4572 bge_txeof(sc); 4573 } 4574 4575 if (sc->bge_pending_rxintr_change) { 4576 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4577 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4578 4579 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4580 DELAY(10); 4581 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4582 4583 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4584 DELAY(10); 4585 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4586 4587 sc->bge_pending_rxintr_change = 0; 4588 } 4589 bge_handle_events(sc); 4590 4591 /* Re-enable interrupts. */ 4592 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4593 4594 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4595 bge_start(ifp); 4596 4597 return 1; 4598 } else 4599 return 0; 4600 } 4601 4602 static void 4603 bge_asf_driver_up(struct bge_softc *sc) 4604 { 4605 if (sc->bge_asf_mode & ASF_STACKUP) { 4606 /* Send ASF heartbeat aprox. every 2s */ 4607 if (sc->bge_asf_count) 4608 sc->bge_asf_count --; 4609 else { 4610 sc->bge_asf_count = 2; 4611 4612 bge_wait_for_event_ack(sc); 4613 4614 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4615 BGE_FW_CMD_DRV_ALIVE); 4616 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4617 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4618 BGE_FW_HB_TIMEOUT_SEC); 4619 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4620 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4621 BGE_RX_CPU_DRV_EVENT); 4622 } 4623 } 4624 } 4625 4626 static void 4627 bge_tick(void *xsc) 4628 { 4629 struct bge_softc *sc = xsc; 4630 struct mii_data *mii = &sc->bge_mii; 4631 int s; 4632 4633 s = splnet(); 4634 4635 if (BGE_IS_5705_PLUS(sc)) 4636 bge_stats_update_regs(sc); 4637 else 4638 bge_stats_update(sc); 4639 4640 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4641 /* 4642 * Since in TBI mode auto-polling can't be used we should poll 4643 * link status manually. Here we register pending link event 4644 * and trigger interrupt. 4645 */ 4646 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4647 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4648 } else { 4649 /* 4650 * Do not touch PHY if we have link up. This could break 4651 * IPMI/ASF mode or produce extra input errors. 4652 * (extra input errors was reported for bcm5701 & bcm5704). 4653 */ 4654 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4655 mii_tick(mii); 4656 } 4657 4658 bge_asf_driver_up(sc); 4659 4660 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4661 4662 splx(s); 4663 } 4664 4665 static void 4666 bge_stats_update_regs(struct bge_softc *sc) 4667 { 4668 struct ifnet *ifp = &sc->ethercom.ec_if; 4669 4670 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4671 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4672 4673 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4674 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4675 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4676 } 4677 4678 static void 4679 bge_stats_update(struct bge_softc *sc) 4680 { 4681 struct ifnet *ifp = &sc->ethercom.ec_if; 4682 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4683 4684 #define READ_STAT(sc, stats, stat) \ 4685 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4686 4687 ifp->if_collisions += 4688 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4689 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4690 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4691 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4692 ifp->if_collisions; 4693 4694 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4695 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4696 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4697 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4698 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4699 READ_STAT(sc, stats, 4700 xoffPauseFramesReceived.bge_addr_lo)); 4701 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4702 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4703 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4704 READ_STAT(sc, stats, 4705 macControlFramesReceived.bge_addr_lo)); 4706 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4707 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4708 4709 #undef READ_STAT 4710 4711 #ifdef notdef 4712 ifp->if_collisions += 4713 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4714 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4715 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4716 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4717 ifp->if_collisions; 4718 #endif 4719 } 4720 4721 /* 4722 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4723 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4724 * but when such padded frames employ the bge IP/TCP checksum offload, 4725 * the hardware checksum assist gives incorrect results (possibly 4726 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4727 * If we pad such runts with zeros, the onboard checksum comes out correct. 4728 */ 4729 static inline int 4730 bge_cksum_pad(struct mbuf *pkt) 4731 { 4732 struct mbuf *last = NULL; 4733 int padlen; 4734 4735 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4736 4737 /* if there's only the packet-header and we can pad there, use it. */ 4738 if (pkt->m_pkthdr.len == pkt->m_len && 4739 M_TRAILINGSPACE(pkt) >= padlen) { 4740 last = pkt; 4741 } else { 4742 /* 4743 * Walk packet chain to find last mbuf. We will either 4744 * pad there, or append a new mbuf and pad it 4745 * (thus perhaps avoiding the bcm5700 dma-min bug). 4746 */ 4747 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4748 continue; /* do nothing */ 4749 } 4750 4751 /* `last' now points to last in chain. */ 4752 if (M_TRAILINGSPACE(last) < padlen) { 4753 /* Allocate new empty mbuf, pad it. Compact later. */ 4754 struct mbuf *n; 4755 MGET(n, M_DONTWAIT, MT_DATA); 4756 if (n == NULL) 4757 return ENOBUFS; 4758 n->m_len = 0; 4759 last->m_next = n; 4760 last = n; 4761 } 4762 } 4763 4764 KDASSERT(!M_READONLY(last)); 4765 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4766 4767 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4768 memset(mtod(last, char *) + last->m_len, 0, padlen); 4769 last->m_len += padlen; 4770 pkt->m_pkthdr.len += padlen; 4771 return 0; 4772 } 4773 4774 /* 4775 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4776 */ 4777 static inline int 4778 bge_compact_dma_runt(struct mbuf *pkt) 4779 { 4780 struct mbuf *m, *prev; 4781 int totlen; 4782 4783 prev = NULL; 4784 totlen = 0; 4785 4786 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4787 int mlen = m->m_len; 4788 int shortfall = 8 - mlen ; 4789 4790 totlen += mlen; 4791 if (mlen == 0) 4792 continue; 4793 if (mlen >= 8) 4794 continue; 4795 4796 /* If we get here, mbuf data is too small for DMA engine. 4797 * Try to fix by shuffling data to prev or next in chain. 4798 * If that fails, do a compacting deep-copy of the whole chain. 4799 */ 4800 4801 /* Internal frag. If fits in prev, copy it there. */ 4802 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4803 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4804 prev->m_len += mlen; 4805 m->m_len = 0; 4806 /* XXX stitch chain */ 4807 prev->m_next = m_free(m); 4808 m = prev; 4809 continue; 4810 } 4811 else if (m->m_next != NULL && 4812 M_TRAILINGSPACE(m) >= shortfall && 4813 m->m_next->m_len >= (8 + shortfall)) { 4814 /* m is writable and have enough data in next, pull up. */ 4815 4816 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4817 shortfall); 4818 m->m_len += shortfall; 4819 m->m_next->m_len -= shortfall; 4820 m->m_next->m_data += shortfall; 4821 } 4822 else if (m->m_next == NULL || 1) { 4823 /* Got a runt at the very end of the packet. 4824 * borrow data from the tail of the preceding mbuf and 4825 * update its length in-place. (The original data is still 4826 * valid, so we can do this even if prev is not writable.) 4827 */ 4828 4829 /* if we'd make prev a runt, just move all of its data. */ 4830 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4831 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4832 4833 if ((prev->m_len - shortfall) < 8) 4834 shortfall = prev->m_len; 4835 4836 #ifdef notyet /* just do the safe slow thing for now */ 4837 if (!M_READONLY(m)) { 4838 if (M_LEADINGSPACE(m) < shorfall) { 4839 void *m_dat; 4840 m_dat = (m->m_flags & M_PKTHDR) ? 4841 m->m_pktdat : m->dat; 4842 memmove(m_dat, mtod(m, void*), m->m_len); 4843 m->m_data = m_dat; 4844 } 4845 } else 4846 #endif /* just do the safe slow thing */ 4847 { 4848 struct mbuf * n = NULL; 4849 int newprevlen = prev->m_len - shortfall; 4850 4851 MGET(n, M_NOWAIT, MT_DATA); 4852 if (n == NULL) 4853 return ENOBUFS; 4854 KASSERT(m->m_len + shortfall < MLEN 4855 /*, 4856 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4857 4858 /* first copy the data we're stealing from prev */ 4859 memcpy(n->m_data, prev->m_data + newprevlen, 4860 shortfall); 4861 4862 /* update prev->m_len accordingly */ 4863 prev->m_len -= shortfall; 4864 4865 /* copy data from runt m */ 4866 memcpy(n->m_data + shortfall, m->m_data, 4867 m->m_len); 4868 4869 /* n holds what we stole from prev, plus m */ 4870 n->m_len = shortfall + m->m_len; 4871 4872 /* stitch n into chain and free m */ 4873 n->m_next = m->m_next; 4874 prev->m_next = n; 4875 /* KASSERT(m->m_next == NULL); */ 4876 m->m_next = NULL; 4877 m_free(m); 4878 m = n; /* for continuing loop */ 4879 } 4880 } 4881 } 4882 return 0; 4883 } 4884 4885 /* 4886 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4887 * pointers to descriptors. 4888 */ 4889 static int 4890 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4891 { 4892 struct bge_tx_bd *f = NULL; 4893 uint32_t frag, cur; 4894 uint16_t csum_flags = 0; 4895 uint16_t txbd_tso_flags = 0; 4896 struct txdmamap_pool_entry *dma; 4897 bus_dmamap_t dmamap; 4898 int i = 0; 4899 struct m_tag *mtag; 4900 int use_tso, maxsegsize, error; 4901 4902 cur = frag = *txidx; 4903 4904 if (m_head->m_pkthdr.csum_flags) { 4905 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4906 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4907 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4908 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4909 } 4910 4911 /* 4912 * If we were asked to do an outboard checksum, and the NIC 4913 * has the bug where it sometimes adds in the Ethernet padding, 4914 * explicitly pad with zeros so the cksum will be correct either way. 4915 * (For now, do this for all chip versions, until newer 4916 * are confirmed to not require the workaround.) 4917 */ 4918 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4919 #ifdef notyet 4920 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4921 #endif 4922 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4923 goto check_dma_bug; 4924 4925 if (bge_cksum_pad(m_head) != 0) 4926 return ENOBUFS; 4927 4928 check_dma_bug: 4929 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4930 goto doit; 4931 4932 /* 4933 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4934 * less than eight bytes. If we encounter a teeny mbuf 4935 * at the end of a chain, we can pad. Otherwise, copy. 4936 */ 4937 if (bge_compact_dma_runt(m_head) != 0) 4938 return ENOBUFS; 4939 4940 doit: 4941 dma = SLIST_FIRST(&sc->txdma_list); 4942 if (dma == NULL) 4943 return ENOBUFS; 4944 dmamap = dma->dmamap; 4945 4946 /* 4947 * Set up any necessary TSO state before we start packing... 4948 */ 4949 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4950 if (!use_tso) { 4951 maxsegsize = 0; 4952 } else { /* TSO setup */ 4953 unsigned mss; 4954 struct ether_header *eh; 4955 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4956 struct mbuf * m0 = m_head; 4957 struct ip *ip; 4958 struct tcphdr *th; 4959 int iphl, hlen; 4960 4961 /* 4962 * XXX It would be nice if the mbuf pkthdr had offset 4963 * fields for the protocol headers. 4964 */ 4965 4966 eh = mtod(m0, struct ether_header *); 4967 switch (htons(eh->ether_type)) { 4968 case ETHERTYPE_IP: 4969 offset = ETHER_HDR_LEN; 4970 break; 4971 4972 case ETHERTYPE_VLAN: 4973 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4974 break; 4975 4976 default: 4977 /* 4978 * Don't support this protocol or encapsulation. 4979 */ 4980 return ENOBUFS; 4981 } 4982 4983 /* 4984 * TCP/IP headers are in the first mbuf; we can do 4985 * this the easy way. 4986 */ 4987 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4988 hlen = iphl + offset; 4989 if (__predict_false(m0->m_len < 4990 (hlen + sizeof(struct tcphdr)))) { 4991 4992 aprint_debug_dev(sc->bge_dev, 4993 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4994 "not handled yet\n", 4995 m0->m_len, hlen+ sizeof(struct tcphdr)); 4996 #ifdef NOTYET 4997 /* 4998 * XXX jonathan (at) NetBSD.org: untested. 4999 * how to force this branch to be taken? 5000 */ 5001 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 5002 5003 m_copydata(m0, offset, sizeof(ip), &ip); 5004 m_copydata(m0, hlen, sizeof(th), &th); 5005 5006 ip.ip_len = 0; 5007 5008 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5009 sizeof(ip.ip_len), &ip.ip_len); 5010 5011 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5012 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5013 5014 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5015 sizeof(th.th_sum), &th.th_sum); 5016 5017 hlen += th.th_off << 2; 5018 iptcp_opt_words = hlen; 5019 #else 5020 /* 5021 * if_wm "hard" case not yet supported, can we not 5022 * mandate it out of existence? 5023 */ 5024 (void) ip; (void)th; (void) ip_tcp_hlen; 5025 5026 return ENOBUFS; 5027 #endif 5028 } else { 5029 ip = (struct ip *) (mtod(m0, char *) + offset); 5030 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5031 ip_tcp_hlen = iphl + (th->th_off << 2); 5032 5033 /* Total IP/TCP options, in 32-bit words */ 5034 iptcp_opt_words = (ip_tcp_hlen 5035 - sizeof(struct tcphdr) 5036 - sizeof(struct ip)) >> 2; 5037 } 5038 if (BGE_IS_575X_PLUS(sc)) { 5039 th->th_sum = 0; 5040 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5041 } else { 5042 /* 5043 * XXX jonathan (at) NetBSD.org: 5705 untested. 5044 * Requires TSO firmware patch for 5701/5703/5704. 5045 */ 5046 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5047 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5048 } 5049 5050 mss = m_head->m_pkthdr.segsz; 5051 txbd_tso_flags |= 5052 BGE_TXBDFLAG_CPU_PRE_DMA | 5053 BGE_TXBDFLAG_CPU_POST_DMA; 5054 5055 /* 5056 * Our NIC TSO-assist assumes TSO has standard, optionless 5057 * IPv4 and TCP headers, which total 40 bytes. By default, 5058 * the NIC copies 40 bytes of IP/TCP header from the 5059 * supplied header into the IP/TCP header portion of 5060 * each post-TSO-segment. If the supplied packet has IP or 5061 * TCP options, we need to tell the NIC to copy those extra 5062 * bytes into each post-TSO header, in addition to the normal 5063 * 40-byte IP/TCP header (and to leave space accordingly). 5064 * Unfortunately, the driver encoding of option length 5065 * varies across different ASIC families. 5066 */ 5067 tcp_seg_flags = 0; 5068 if (iptcp_opt_words) { 5069 if (BGE_IS_5705_PLUS(sc)) { 5070 tcp_seg_flags = 5071 iptcp_opt_words << 11; 5072 } else { 5073 txbd_tso_flags |= 5074 iptcp_opt_words << 12; 5075 } 5076 } 5077 maxsegsize = mss | tcp_seg_flags; 5078 ip->ip_len = htons(mss + ip_tcp_hlen); 5079 5080 } /* TSO setup */ 5081 5082 /* 5083 * Start packing the mbufs in this chain into 5084 * the fragment pointers. Stop when we run out 5085 * of fragments or hit the end of the mbuf chain. 5086 */ 5087 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5088 BUS_DMA_NOWAIT); 5089 if (error) 5090 return ENOBUFS; 5091 /* 5092 * Sanity check: avoid coming within 16 descriptors 5093 * of the end of the ring. 5094 */ 5095 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5096 BGE_TSO_PRINTF(("%s: " 5097 " dmamap_load_mbuf too close to ring wrap\n", 5098 device_xname(sc->bge_dev))); 5099 goto fail_unload; 5100 } 5101 5102 mtag = sc->ethercom.ec_nvlans ? 5103 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5104 5105 5106 /* Iterate over dmap-map fragments. */ 5107 for (i = 0; i < dmamap->dm_nsegs; i++) { 5108 f = &sc->bge_rdata->bge_tx_ring[frag]; 5109 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5110 break; 5111 5112 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5113 f->bge_len = dmamap->dm_segs[i].ds_len; 5114 5115 /* 5116 * For 5751 and follow-ons, for TSO we must turn 5117 * off checksum-assist flag in the tx-descr, and 5118 * supply the ASIC-revision-specific encoding 5119 * of TSO flags and segsize. 5120 */ 5121 if (use_tso) { 5122 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5123 f->bge_rsvd = maxsegsize; 5124 f->bge_flags = csum_flags | txbd_tso_flags; 5125 } else { 5126 f->bge_rsvd = 0; 5127 f->bge_flags = 5128 (csum_flags | txbd_tso_flags) & 0x0fff; 5129 } 5130 } else { 5131 f->bge_rsvd = 0; 5132 f->bge_flags = csum_flags; 5133 } 5134 5135 if (mtag != NULL) { 5136 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5137 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5138 } else { 5139 f->bge_vlan_tag = 0; 5140 } 5141 cur = frag; 5142 BGE_INC(frag, BGE_TX_RING_CNT); 5143 } 5144 5145 if (i < dmamap->dm_nsegs) { 5146 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5147 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5148 goto fail_unload; 5149 } 5150 5151 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5152 BUS_DMASYNC_PREWRITE); 5153 5154 if (frag == sc->bge_tx_saved_considx) { 5155 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5156 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5157 5158 goto fail_unload; 5159 } 5160 5161 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5162 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5163 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5164 sc->txdma[cur] = dma; 5165 sc->bge_txcnt += dmamap->dm_nsegs; 5166 5167 *txidx = frag; 5168 5169 return 0; 5170 5171 fail_unload: 5172 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5173 5174 return ENOBUFS; 5175 } 5176 5177 /* 5178 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5179 * to the mbuf data regions directly in the transmit descriptors. 5180 */ 5181 static void 5182 bge_start(struct ifnet *ifp) 5183 { 5184 struct bge_softc *sc; 5185 struct mbuf *m_head = NULL; 5186 uint32_t prodidx; 5187 int pkts = 0; 5188 5189 sc = ifp->if_softc; 5190 5191 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5192 return; 5193 5194 prodidx = sc->bge_tx_prodidx; 5195 5196 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5197 IFQ_POLL(&ifp->if_snd, m_head); 5198 if (m_head == NULL) 5199 break; 5200 5201 #if 0 5202 /* 5203 * XXX 5204 * safety overkill. If this is a fragmented packet chain 5205 * with delayed TCP/UDP checksums, then only encapsulate 5206 * it if we have enough descriptors to handle the entire 5207 * chain at once. 5208 * (paranoia -- may not actually be needed) 5209 */ 5210 if (m_head->m_flags & M_FIRSTFRAG && 5211 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5212 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5213 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5214 ifp->if_flags |= IFF_OACTIVE; 5215 break; 5216 } 5217 } 5218 #endif 5219 5220 /* 5221 * Pack the data into the transmit ring. If we 5222 * don't have room, set the OACTIVE flag and wait 5223 * for the NIC to drain the ring. 5224 */ 5225 if (bge_encap(sc, m_head, &prodidx)) { 5226 ifp->if_flags |= IFF_OACTIVE; 5227 break; 5228 } 5229 5230 /* now we are committed to transmit the packet */ 5231 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5232 pkts++; 5233 5234 /* 5235 * If there's a BPF listener, bounce a copy of this frame 5236 * to him. 5237 */ 5238 bpf_mtap(ifp, m_head); 5239 } 5240 if (pkts == 0) 5241 return; 5242 5243 /* Transmit */ 5244 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5245 /* 5700 b2 errata */ 5246 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5247 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5248 5249 sc->bge_tx_prodidx = prodidx; 5250 5251 /* 5252 * Set a timeout in case the chip goes out to lunch. 5253 */ 5254 ifp->if_timer = 5; 5255 } 5256 5257 static int 5258 bge_init(struct ifnet *ifp) 5259 { 5260 struct bge_softc *sc = ifp->if_softc; 5261 const uint16_t *m; 5262 uint32_t mode, reg; 5263 int s, error = 0; 5264 5265 s = splnet(); 5266 5267 ifp = &sc->ethercom.ec_if; 5268 5269 /* Cancel pending I/O and flush buffers. */ 5270 bge_stop(ifp, 0); 5271 5272 bge_stop_fw(sc); 5273 bge_sig_pre_reset(sc, BGE_RESET_START); 5274 bge_reset(sc); 5275 bge_sig_legacy(sc, BGE_RESET_START); 5276 bge_sig_post_reset(sc, BGE_RESET_START); 5277 5278 bge_chipinit(sc); 5279 5280 /* 5281 * Init the various state machines, ring 5282 * control blocks and firmware. 5283 */ 5284 error = bge_blockinit(sc); 5285 if (error != 0) { 5286 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5287 error); 5288 splx(s); 5289 return error; 5290 } 5291 5292 ifp = &sc->ethercom.ec_if; 5293 5294 /* 5718 step 25, 57XX step 54 */ 5295 /* Specify MTU. */ 5296 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5297 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5298 5299 /* 5718 step 23 */ 5300 /* Load our MAC address. */ 5301 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5302 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5303 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5304 5305 /* Enable or disable promiscuous mode as needed. */ 5306 if (ifp->if_flags & IFF_PROMISC) 5307 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5308 else 5309 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5310 5311 /* Program multicast filter. */ 5312 bge_setmulti(sc); 5313 5314 /* Init RX ring. */ 5315 bge_init_rx_ring_std(sc); 5316 5317 /* 5318 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5319 * memory to insure that the chip has in fact read the first 5320 * entry of the ring. 5321 */ 5322 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5323 uint32_t v, i; 5324 for (i = 0; i < 10; i++) { 5325 DELAY(20); 5326 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5327 if (v == (MCLBYTES - ETHER_ALIGN)) 5328 break; 5329 } 5330 if (i == 10) 5331 aprint_error_dev(sc->bge_dev, 5332 "5705 A0 chip failed to load RX ring\n"); 5333 } 5334 5335 /* Init jumbo RX ring. */ 5336 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5337 bge_init_rx_ring_jumbo(sc); 5338 5339 /* Init our RX return ring index */ 5340 sc->bge_rx_saved_considx = 0; 5341 5342 /* Init TX ring. */ 5343 bge_init_tx_ring(sc); 5344 5345 /* 5718 step 63, 57XX step 94 */ 5346 /* Enable TX MAC state machine lockup fix. */ 5347 mode = CSR_READ_4(sc, BGE_TX_MODE); 5348 if (BGE_IS_5755_PLUS(sc) || 5349 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5350 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5351 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5352 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5353 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5354 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5355 } 5356 5357 /* Turn on transmitter */ 5358 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5359 /* 5718 step 64 */ 5360 DELAY(100); 5361 5362 /* 5718 step 65, 57XX step 95 */ 5363 /* Turn on receiver */ 5364 mode = CSR_READ_4(sc, BGE_RX_MODE); 5365 if (BGE_IS_5755_PLUS(sc)) 5366 mode |= BGE_RXMODE_IPV6_ENABLE; 5367 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5368 /* 5718 step 66 */ 5369 DELAY(10); 5370 5371 /* 5718 step 12, 57XX step 37 */ 5372 /* 5373 * XXX Doucments of 5718 series and 577xx say the recommended value 5374 * is 1, but tg3 set 1 only on 57765 series. 5375 */ 5376 if (BGE_IS_57765_PLUS(sc)) 5377 reg = 1; 5378 else 5379 reg = 2; 5380 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5381 5382 /* Tell firmware we're alive. */ 5383 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5384 5385 /* Enable host interrupts. */ 5386 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5387 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5388 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5389 5390 if ((error = bge_ifmedia_upd(ifp)) != 0) 5391 goto out; 5392 5393 ifp->if_flags |= IFF_RUNNING; 5394 ifp->if_flags &= ~IFF_OACTIVE; 5395 5396 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5397 5398 out: 5399 sc->bge_if_flags = ifp->if_flags; 5400 splx(s); 5401 5402 return error; 5403 } 5404 5405 /* 5406 * Set media options. 5407 */ 5408 static int 5409 bge_ifmedia_upd(struct ifnet *ifp) 5410 { 5411 struct bge_softc *sc = ifp->if_softc; 5412 struct mii_data *mii = &sc->bge_mii; 5413 struct ifmedia *ifm = &sc->bge_ifmedia; 5414 int rc; 5415 5416 /* If this is a 1000baseX NIC, enable the TBI port. */ 5417 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5418 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5419 return EINVAL; 5420 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5421 case IFM_AUTO: 5422 /* 5423 * The BCM5704 ASIC appears to have a special 5424 * mechanism for programming the autoneg 5425 * advertisement registers in TBI mode. 5426 */ 5427 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5428 uint32_t sgdig; 5429 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5430 if (sgdig & BGE_SGDIGSTS_DONE) { 5431 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5432 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5433 sgdig |= BGE_SGDIGCFG_AUTO | 5434 BGE_SGDIGCFG_PAUSE_CAP | 5435 BGE_SGDIGCFG_ASYM_PAUSE; 5436 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5437 sgdig | BGE_SGDIGCFG_SEND); 5438 DELAY(5); 5439 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5440 sgdig); 5441 } 5442 } 5443 break; 5444 case IFM_1000_SX: 5445 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5446 BGE_CLRBIT(sc, BGE_MAC_MODE, 5447 BGE_MACMODE_HALF_DUPLEX); 5448 } else { 5449 BGE_SETBIT(sc, BGE_MAC_MODE, 5450 BGE_MACMODE_HALF_DUPLEX); 5451 } 5452 DELAY(40); 5453 break; 5454 default: 5455 return EINVAL; 5456 } 5457 /* XXX 802.3x flow control for 1000BASE-SX */ 5458 return 0; 5459 } 5460 5461 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5462 if ((rc = mii_mediachg(mii)) == ENXIO) 5463 return 0; 5464 5465 /* 5466 * Force an interrupt so that we will call bge_link_upd 5467 * if needed and clear any pending link state attention. 5468 * Without this we are not getting any further interrupts 5469 * for link state changes and thus will not UP the link and 5470 * not be able to send in bge_start. The only way to get 5471 * things working was to receive a packet and get a RX intr. 5472 */ 5473 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5474 sc->bge_flags & BGE_IS_5788) 5475 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5476 else 5477 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5478 5479 return rc; 5480 } 5481 5482 /* 5483 * Report current media status. 5484 */ 5485 static void 5486 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5487 { 5488 struct bge_softc *sc = ifp->if_softc; 5489 struct mii_data *mii = &sc->bge_mii; 5490 5491 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5492 ifmr->ifm_status = IFM_AVALID; 5493 ifmr->ifm_active = IFM_ETHER; 5494 if (CSR_READ_4(sc, BGE_MAC_STS) & 5495 BGE_MACSTAT_TBI_PCS_SYNCHED) 5496 ifmr->ifm_status |= IFM_ACTIVE; 5497 ifmr->ifm_active |= IFM_1000_SX; 5498 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5499 ifmr->ifm_active |= IFM_HDX; 5500 else 5501 ifmr->ifm_active |= IFM_FDX; 5502 return; 5503 } 5504 5505 mii_pollstat(mii); 5506 ifmr->ifm_status = mii->mii_media_status; 5507 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5508 sc->bge_flowflags; 5509 } 5510 5511 static int 5512 bge_ifflags_cb(struct ethercom *ec) 5513 { 5514 struct ifnet *ifp = &ec->ec_if; 5515 struct bge_softc *sc = ifp->if_softc; 5516 int change = ifp->if_flags ^ sc->bge_if_flags; 5517 5518 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5519 return ENETRESET; 5520 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5521 return 0; 5522 5523 if ((ifp->if_flags & IFF_PROMISC) == 0) 5524 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5525 else 5526 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5527 5528 bge_setmulti(sc); 5529 5530 sc->bge_if_flags = ifp->if_flags; 5531 return 0; 5532 } 5533 5534 static int 5535 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5536 { 5537 struct bge_softc *sc = ifp->if_softc; 5538 struct ifreq *ifr = (struct ifreq *) data; 5539 int s, error = 0; 5540 struct mii_data *mii; 5541 5542 s = splnet(); 5543 5544 switch (command) { 5545 case SIOCSIFMEDIA: 5546 /* XXX Flow control is not supported for 1000BASE-SX */ 5547 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5548 ifr->ifr_media &= ~IFM_ETH_FMASK; 5549 sc->bge_flowflags = 0; 5550 } 5551 5552 /* Flow control requires full-duplex mode. */ 5553 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5554 (ifr->ifr_media & IFM_FDX) == 0) { 5555 ifr->ifr_media &= ~IFM_ETH_FMASK; 5556 } 5557 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5558 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5559 /* We can do both TXPAUSE and RXPAUSE. */ 5560 ifr->ifr_media |= 5561 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5562 } 5563 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5564 } 5565 /* FALLTHROUGH */ 5566 case SIOCGIFMEDIA: 5567 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5568 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5569 command); 5570 } else { 5571 mii = &sc->bge_mii; 5572 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5573 command); 5574 } 5575 break; 5576 default: 5577 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5578 break; 5579 5580 error = 0; 5581 5582 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5583 ; 5584 else if (ifp->if_flags & IFF_RUNNING) 5585 bge_setmulti(sc); 5586 break; 5587 } 5588 5589 splx(s); 5590 5591 return error; 5592 } 5593 5594 static void 5595 bge_watchdog(struct ifnet *ifp) 5596 { 5597 struct bge_softc *sc; 5598 5599 sc = ifp->if_softc; 5600 5601 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5602 5603 ifp->if_flags &= ~IFF_RUNNING; 5604 bge_init(ifp); 5605 5606 ifp->if_oerrors++; 5607 } 5608 5609 static void 5610 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5611 { 5612 int i; 5613 5614 BGE_CLRBIT_FLUSH(sc, reg, bit); 5615 5616 for (i = 0; i < 1000; i++) { 5617 delay(100); 5618 if ((CSR_READ_4(sc, reg) & bit) == 0) 5619 return; 5620 } 5621 5622 /* 5623 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5624 * on some environment (and once after boot?) 5625 */ 5626 if (reg != BGE_SRS_MODE) 5627 aprint_error_dev(sc->bge_dev, 5628 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5629 (u_long)reg, bit); 5630 } 5631 5632 /* 5633 * Stop the adapter and free any mbufs allocated to the 5634 * RX and TX lists. 5635 */ 5636 static void 5637 bge_stop(struct ifnet *ifp, int disable) 5638 { 5639 struct bge_softc *sc = ifp->if_softc; 5640 5641 callout_stop(&sc->bge_timeout); 5642 5643 /* Disable host interrupts. */ 5644 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5645 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5646 5647 /* 5648 * Tell firmware we're shutting down. 5649 */ 5650 bge_stop_fw(sc); 5651 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5652 5653 /* 5654 * Disable all of the receiver blocks. 5655 */ 5656 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5657 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5658 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5659 if (BGE_IS_5700_FAMILY(sc)) 5660 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5661 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5662 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5663 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5664 5665 /* 5666 * Disable all of the transmit blocks. 5667 */ 5668 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5669 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5670 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5671 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5672 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5673 if (BGE_IS_5700_FAMILY(sc)) 5674 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5675 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5676 5677 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5678 delay(40); 5679 5680 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5681 5682 /* 5683 * Shut down all of the memory managers and related 5684 * state machines. 5685 */ 5686 /* 5718 step 5a,5b */ 5687 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5688 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5689 if (BGE_IS_5700_FAMILY(sc)) 5690 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5691 5692 /* 5718 step 5c,5d */ 5693 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5694 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5695 5696 if (BGE_IS_5700_FAMILY(sc)) { 5697 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5698 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5699 } 5700 5701 bge_reset(sc); 5702 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5703 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5704 5705 /* 5706 * Keep the ASF firmware running if up. 5707 */ 5708 if (sc->bge_asf_mode & ASF_STACKUP) 5709 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5710 else 5711 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5712 5713 /* Free the RX lists. */ 5714 bge_free_rx_ring_std(sc); 5715 5716 /* Free jumbo RX list. */ 5717 if (BGE_IS_JUMBO_CAPABLE(sc)) 5718 bge_free_rx_ring_jumbo(sc); 5719 5720 /* Free TX buffers. */ 5721 bge_free_tx_ring(sc); 5722 5723 /* 5724 * Isolate/power down the PHY. 5725 */ 5726 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 5727 mii_down(&sc->bge_mii); 5728 5729 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5730 5731 /* Clear MAC's link state (PHY may still have link UP). */ 5732 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5733 5734 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5735 } 5736 5737 static void 5738 bge_link_upd(struct bge_softc *sc) 5739 { 5740 struct ifnet *ifp = &sc->ethercom.ec_if; 5741 struct mii_data *mii = &sc->bge_mii; 5742 uint32_t status; 5743 int link; 5744 5745 /* Clear 'pending link event' flag */ 5746 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5747 5748 /* 5749 * Process link state changes. 5750 * Grrr. The link status word in the status block does 5751 * not work correctly on the BCM5700 rev AX and BX chips, 5752 * according to all available information. Hence, we have 5753 * to enable MII interrupts in order to properly obtain 5754 * async link changes. Unfortunately, this also means that 5755 * we have to read the MAC status register to detect link 5756 * changes, thereby adding an additional register access to 5757 * the interrupt handler. 5758 */ 5759 5760 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5761 status = CSR_READ_4(sc, BGE_MAC_STS); 5762 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5763 mii_pollstat(mii); 5764 5765 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5766 mii->mii_media_status & IFM_ACTIVE && 5767 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5768 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5769 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5770 (!(mii->mii_media_status & IFM_ACTIVE) || 5771 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5772 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5773 5774 /* Clear the interrupt */ 5775 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5776 BGE_EVTENB_MI_INTERRUPT); 5777 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5778 BRGPHY_MII_ISR); 5779 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5780 BRGPHY_MII_IMR, BRGPHY_INTRS); 5781 } 5782 return; 5783 } 5784 5785 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 5786 status = CSR_READ_4(sc, BGE_MAC_STS); 5787 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5788 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5789 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5790 if (BGE_ASICREV(sc->bge_chipid) 5791 == BGE_ASICREV_BCM5704) { 5792 BGE_CLRBIT(sc, BGE_MAC_MODE, 5793 BGE_MACMODE_TBI_SEND_CFGS); 5794 DELAY(40); 5795 } 5796 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5797 if_link_state_change(ifp, LINK_STATE_UP); 5798 } 5799 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5800 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5801 if_link_state_change(ifp, LINK_STATE_DOWN); 5802 } 5803 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5804 /* 5805 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5806 * bit in status word always set. Workaround this bug by 5807 * reading PHY link status directly. 5808 */ 5809 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5810 BGE_STS_LINK : 0; 5811 5812 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5813 mii_pollstat(mii); 5814 5815 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5816 mii->mii_media_status & IFM_ACTIVE && 5817 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5818 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5819 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5820 (!(mii->mii_media_status & IFM_ACTIVE) || 5821 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5822 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5823 } 5824 } else { 5825 /* 5826 * For controllers that call mii_tick, we have to poll 5827 * link status. 5828 */ 5829 mii_pollstat(mii); 5830 } 5831 5832 /* Clear the attention */ 5833 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5834 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5835 BGE_MACSTAT_LINK_CHANGED); 5836 } 5837 5838 static int 5839 bge_sysctl_verify(SYSCTLFN_ARGS) 5840 { 5841 int error, t; 5842 struct sysctlnode node; 5843 5844 node = *rnode; 5845 t = *(int*)rnode->sysctl_data; 5846 node.sysctl_data = &t; 5847 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5848 if (error || newp == NULL) 5849 return error; 5850 5851 #if 0 5852 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5853 node.sysctl_num, rnode->sysctl_num)); 5854 #endif 5855 5856 if (node.sysctl_num == bge_rxthresh_nodenum) { 5857 if (t < 0 || t >= NBGE_RX_THRESH) 5858 return EINVAL; 5859 bge_update_all_threshes(t); 5860 } else 5861 return EINVAL; 5862 5863 *(int*)rnode->sysctl_data = t; 5864 5865 return 0; 5866 } 5867 5868 /* 5869 * Set up sysctl(3) MIB, hw.bge.*. 5870 */ 5871 static void 5872 bge_sysctl_init(struct bge_softc *sc) 5873 { 5874 int rc, bge_root_num; 5875 const struct sysctlnode *node; 5876 5877 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5878 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5879 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5880 goto out; 5881 } 5882 5883 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5884 0, CTLTYPE_NODE, "bge", 5885 SYSCTL_DESCR("BGE interface controls"), 5886 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5887 goto out; 5888 } 5889 5890 bge_root_num = node->sysctl_num; 5891 5892 /* BGE Rx interrupt mitigation level */ 5893 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5894 CTLFLAG_READWRITE, 5895 CTLTYPE_INT, "rx_lvl", 5896 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5897 bge_sysctl_verify, 0, 5898 &bge_rx_thresh_lvl, 5899 0, CTL_HW, bge_root_num, CTL_CREATE, 5900 CTL_EOL)) != 0) { 5901 goto out; 5902 } 5903 5904 bge_rxthresh_nodenum = node->sysctl_num; 5905 5906 return; 5907 5908 out: 5909 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5910 } 5911 5912 #ifdef BGE_DEBUG 5913 void 5914 bge_debug_info(struct bge_softc *sc) 5915 { 5916 5917 printf("Hardware Flags:\n"); 5918 if (BGE_IS_57765_PLUS(sc)) 5919 printf(" - 57765 Plus\n"); 5920 if (BGE_IS_5717_PLUS(sc)) 5921 printf(" - 5717 Plus\n"); 5922 if (BGE_IS_5755_PLUS(sc)) 5923 printf(" - 5755 Plus\n"); 5924 if (BGE_IS_575X_PLUS(sc)) 5925 printf(" - 575X Plus\n"); 5926 if (BGE_IS_5705_PLUS(sc)) 5927 printf(" - 5705 Plus\n"); 5928 if (BGE_IS_5714_FAMILY(sc)) 5929 printf(" - 5714 Family\n"); 5930 if (BGE_IS_5700_FAMILY(sc)) 5931 printf(" - 5700 Family\n"); 5932 if (sc->bge_flags & BGE_IS_5788) 5933 printf(" - 5788\n"); 5934 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 5935 printf(" - Supports Jumbo Frames\n"); 5936 if (sc->bge_flags & BGE_NO_EEPROM) 5937 printf(" - No EEPROM\n"); 5938 if (sc->bge_flags & BGE_PCIX) 5939 printf(" - PCI-X Bus\n"); 5940 if (sc->bge_flags & BGE_PCIE) 5941 printf(" - PCI Express Bus\n"); 5942 if (sc->bge_flags & BGE_RX_ALIGNBUG) 5943 printf(" - RX Alignment Bug\n"); 5944 if (sc->bge_flags & BGE_APE) 5945 printf(" - APE\n"); 5946 if (sc->bge_flags & BGE_CPMU_PRESENT) 5947 printf(" - CPMU\n"); 5948 if (sc->bge_flags & BGE_TSO) 5949 printf(" - TSO\n"); 5950 5951 if (sc->bge_flags & BGE_PHY_NO_3LED) 5952 printf(" - No 3 LEDs\n"); 5953 if (sc->bge_flags & BGE_PHY_CRC_BUG) 5954 printf(" - CRC bug\n"); 5955 if (sc->bge_flags & BGE_PHY_ADC_BUG) 5956 printf(" - ADC bug\n"); 5957 if (sc->bge_flags & BGE_PHY_5704_A0_BUG) 5958 printf(" - 5704 A0 bug\n"); 5959 if (sc->bge_flags & BGE_PHY_JITTER_BUG) 5960 printf(" - jitter bug\n"); 5961 if (sc->bge_flags & BGE_PHY_BER_BUG) 5962 printf(" - BER bug\n"); 5963 if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) 5964 printf(" - adjust trim\n"); 5965 if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) 5966 printf(" - no wirespeed\n"); 5967 } 5968 #endif /* BGE_DEBUG */ 5969 5970 static int 5971 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5972 { 5973 prop_dictionary_t dict; 5974 prop_data_t ea; 5975 5976 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 5977 return 1; 5978 5979 dict = device_properties(sc->bge_dev); 5980 ea = prop_dictionary_get(dict, "mac-address"); 5981 if (ea != NULL) { 5982 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 5983 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 5984 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 5985 return 0; 5986 } 5987 5988 return 1; 5989 } 5990 5991 static int 5992 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5993 { 5994 uint32_t mac_addr; 5995 5996 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 5997 if ((mac_addr >> 16) == 0x484b) { 5998 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5999 ether_addr[1] = (uint8_t)mac_addr; 6000 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6001 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6002 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6003 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6004 ether_addr[5] = (uint8_t)mac_addr; 6005 return 0; 6006 } 6007 return 1; 6008 } 6009 6010 static int 6011 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6012 { 6013 int mac_offset = BGE_EE_MAC_OFFSET; 6014 6015 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6016 mac_offset = BGE_EE_MAC_OFFSET_5906; 6017 6018 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6019 ETHER_ADDR_LEN)); 6020 } 6021 6022 static int 6023 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6024 { 6025 6026 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6027 return 1; 6028 6029 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6030 ETHER_ADDR_LEN)); 6031 } 6032 6033 static int 6034 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6035 { 6036 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6037 /* NOTE: Order is critical */ 6038 bge_get_eaddr_fw, 6039 bge_get_eaddr_mem, 6040 bge_get_eaddr_nvram, 6041 bge_get_eaddr_eeprom, 6042 NULL 6043 }; 6044 const bge_eaddr_fcn_t *func; 6045 6046 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6047 if ((*func)(sc, eaddr) == 0) 6048 break; 6049 } 6050 return (*func == NULL ? ENXIO : 0); 6051 } 6052
Indexes created Tue Sep 23 07:09:52 GMT 2025