if_bge.c revision 1.261
1 /* $NetBSD: if_bge.c,v 1.261 2013/10/31 04:26:40 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.261 2013/10/31 04:26:40 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rnd.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 680 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 683 684 static const struct bge_revision { 685 uint32_t br_chipid; 686 const char *br_name; 687 } bge_revisions[] = { 688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 743 /* 5754 and 5787 share the same ASIC ID */ 744 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 745 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 746 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 747 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 748 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 749 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 750 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 751 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 752 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 753 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 754 755 { 0, NULL } 756 }; 757 758 /* 759 * Some defaults for major revisions, so that newer steppings 760 * that we don't know about have a shot at working. 761 */ 762 static const struct bge_revision bge_majorrevs[] = { 763 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 764 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 765 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 766 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 767 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 768 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 769 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 772 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 773 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 774 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 775 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 776 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 777 /* 5754 and 5787 share the same ASIC ID */ 778 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 779 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 780 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 781 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 782 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 783 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 784 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 785 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 786 787 { 0, NULL } 788 }; 789 790 static int bge_allow_asf = 1; 791 792 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 793 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 794 795 static uint32_t 796 bge_readmem_ind(struct bge_softc *sc, int off) 797 { 798 pcireg_t val; 799 800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 801 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 802 return 0; 803 804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 805 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 806 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 807 return val; 808 } 809 810 static void 811 bge_writemem_ind(struct bge_softc *sc, int off, int val) 812 { 813 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 817 } 818 819 /* 820 * PCI Express only 821 */ 822 static void 823 bge_set_max_readrq(struct bge_softc *sc) 824 { 825 pcireg_t val; 826 827 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 828 + PCIE_DCSR); 829 val &= ~PCIE_DCSR_MAX_READ_REQ; 830 switch (sc->bge_expmrq) { 831 case 2048: 832 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 833 break; 834 case 4096: 835 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 836 break; 837 default: 838 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 839 break; 840 } 841 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 842 + PCIE_DCSR, val); 843 } 844 845 #ifdef notdef 846 static uint32_t 847 bge_readreg_ind(struct bge_softc *sc, int off) 848 { 849 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 850 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 851 } 852 #endif 853 854 static void 855 bge_writereg_ind(struct bge_softc *sc, int off, int val) 856 { 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 859 } 860 861 static void 862 bge_writemem_direct(struct bge_softc *sc, int off, int val) 863 { 864 CSR_WRITE_4(sc, off, val); 865 } 866 867 static void 868 bge_writembx(struct bge_softc *sc, int off, int val) 869 { 870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 871 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 872 873 CSR_WRITE_4(sc, off, val); 874 } 875 876 static void 877 bge_writembx_flush(struct bge_softc *sc, int off, int val) 878 { 879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 880 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 881 882 CSR_WRITE_4_FLUSH(sc, off, val); 883 } 884 885 /* 886 * Clear all stale locks and select the lock for this driver instance. 887 */ 888 void 889 bge_ape_lock_init(struct bge_softc *sc) 890 { 891 struct pci_attach_args *pa = &(sc->bge_pa); 892 uint32_t bit, regbase; 893 int i; 894 895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 896 regbase = BGE_APE_LOCK_GRANT; 897 else 898 regbase = BGE_APE_PER_LOCK_GRANT; 899 900 /* Clear any stale locks. */ 901 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 902 switch (i) { 903 case BGE_APE_LOCK_PHY0: 904 case BGE_APE_LOCK_PHY1: 905 case BGE_APE_LOCK_PHY2: 906 case BGE_APE_LOCK_PHY3: 907 bit = BGE_APE_LOCK_GRANT_DRIVER0; 908 break; 909 default: 910 if (pa->pa_function == 0) 911 bit = BGE_APE_LOCK_GRANT_DRIVER0; 912 else 913 bit = (1 << pa->pa_function); 914 } 915 APE_WRITE_4(sc, regbase + 4 * i, bit); 916 } 917 918 /* Select the PHY lock based on the device's function number. */ 919 switch (pa->pa_function) { 920 case 0: 921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 922 break; 923 case 1: 924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 925 break; 926 case 2: 927 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 928 break; 929 case 3: 930 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 931 break; 932 default: 933 printf("%s: PHY lock not supported on function\n", 934 device_xname(sc->bge_dev)); 935 break; 936 } 937 } 938 939 /* 940 * Check for APE firmware, set flags, and print version info. 941 */ 942 void 943 bge_ape_read_fw_ver(struct bge_softc *sc) 944 { 945 const char *fwtype; 946 uint32_t apedata, features; 947 948 /* Check for a valid APE signature in shared memory. */ 949 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 950 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 951 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 952 return; 953 } 954 955 /* Check if APE firmware is running. */ 956 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 957 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 958 printf("%s: APE signature found but FW status not ready! " 959 "0x%08x\n", device_xname(sc->bge_dev), apedata); 960 return; 961 } 962 963 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 964 965 /* Fetch the APE firwmare type and version. */ 966 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 967 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 968 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 969 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 970 fwtype = "NCSI"; 971 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 972 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 973 fwtype = "DASH"; 974 } else 975 fwtype = "UNKN"; 976 977 /* Print the APE firmware version. */ 978 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 979 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 980 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 981 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 982 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 983 } 984 985 int 986 bge_ape_lock(struct bge_softc *sc, int locknum) 987 { 988 struct pci_attach_args *pa = &(sc->bge_pa); 989 uint32_t bit, gnt, req, status; 990 int i, off; 991 992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 993 return (0); 994 995 /* Lock request/grant registers have different bases. */ 996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 997 req = BGE_APE_LOCK_REQ; 998 gnt = BGE_APE_LOCK_GRANT; 999 } else { 1000 req = BGE_APE_PER_LOCK_REQ; 1001 gnt = BGE_APE_PER_LOCK_GRANT; 1002 } 1003 1004 off = 4 * locknum; 1005 1006 switch (locknum) { 1007 case BGE_APE_LOCK_GPIO: 1008 /* Lock required when using GPIO. */ 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1010 return (0); 1011 if (pa->pa_function == 0) 1012 bit = BGE_APE_LOCK_REQ_DRIVER0; 1013 else 1014 bit = (1 << pa->pa_function); 1015 break; 1016 case BGE_APE_LOCK_GRC: 1017 /* Lock required to reset the device. */ 1018 if (pa->pa_function == 0) 1019 bit = BGE_APE_LOCK_REQ_DRIVER0; 1020 else 1021 bit = (1 << pa->pa_function); 1022 break; 1023 case BGE_APE_LOCK_MEM: 1024 /* Lock required when accessing certain APE memory. */ 1025 if (pa->pa_function == 0) 1026 bit = BGE_APE_LOCK_REQ_DRIVER0; 1027 else 1028 bit = (1 << pa->pa_function); 1029 break; 1030 case BGE_APE_LOCK_PHY0: 1031 case BGE_APE_LOCK_PHY1: 1032 case BGE_APE_LOCK_PHY2: 1033 case BGE_APE_LOCK_PHY3: 1034 /* Lock required when accessing PHYs. */ 1035 bit = BGE_APE_LOCK_REQ_DRIVER0; 1036 break; 1037 default: 1038 return (EINVAL); 1039 } 1040 1041 /* Request a lock. */ 1042 APE_WRITE_4_FLUSH(sc, req + off, bit); 1043 1044 /* Wait up to 1 second to acquire lock. */ 1045 for (i = 0; i < 20000; i++) { 1046 status = APE_READ_4(sc, gnt + off); 1047 if (status == bit) 1048 break; 1049 DELAY(50); 1050 } 1051 1052 /* Handle any errors. */ 1053 if (status != bit) { 1054 printf("%s: APE lock %d request failed! " 1055 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1056 device_xname(sc->bge_dev), 1057 locknum, req + off, bit & 0xFFFF, gnt + off, 1058 status & 0xFFFF); 1059 /* Revoke the lock request. */ 1060 APE_WRITE_4(sc, gnt + off, bit); 1061 return (EBUSY); 1062 } 1063 1064 return (0); 1065 } 1066 1067 void 1068 bge_ape_unlock(struct bge_softc *sc, int locknum) 1069 { 1070 struct pci_attach_args *pa = &(sc->bge_pa); 1071 uint32_t bit, gnt; 1072 int off; 1073 1074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1075 return; 1076 1077 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1078 gnt = BGE_APE_LOCK_GRANT; 1079 else 1080 gnt = BGE_APE_PER_LOCK_GRANT; 1081 1082 off = 4 * locknum; 1083 1084 switch (locknum) { 1085 case BGE_APE_LOCK_GPIO: 1086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1087 return; 1088 if (pa->pa_function == 0) 1089 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1090 else 1091 bit = (1 << pa->pa_function); 1092 break; 1093 case BGE_APE_LOCK_GRC: 1094 if (pa->pa_function == 0) 1095 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1096 else 1097 bit = (1 << pa->pa_function); 1098 break; 1099 case BGE_APE_LOCK_MEM: 1100 if (pa->pa_function == 0) 1101 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1102 else 1103 bit = (1 << pa->pa_function); 1104 break; 1105 case BGE_APE_LOCK_PHY0: 1106 case BGE_APE_LOCK_PHY1: 1107 case BGE_APE_LOCK_PHY2: 1108 case BGE_APE_LOCK_PHY3: 1109 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1110 break; 1111 default: 1112 return; 1113 } 1114 1115 /* Write and flush for consecutive bge_ape_lock() */ 1116 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1117 } 1118 1119 /* 1120 * Send an event to the APE firmware. 1121 */ 1122 void 1123 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1124 { 1125 uint32_t apedata; 1126 int i; 1127 1128 /* NCSI does not support APE events. */ 1129 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1130 return; 1131 1132 /* Wait up to 1ms for APE to service previous event. */ 1133 for (i = 10; i > 0; i--) { 1134 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1135 break; 1136 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1137 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1138 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1139 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1141 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1142 break; 1143 } 1144 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1145 DELAY(100); 1146 } 1147 if (i == 0) { 1148 printf("%s: APE event 0x%08x send timed out\n", 1149 device_xname(sc->bge_dev), event); 1150 } 1151 } 1152 1153 void 1154 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1155 { 1156 uint32_t apedata, event; 1157 1158 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1159 return; 1160 1161 switch (kind) { 1162 case BGE_RESET_START: 1163 /* If this is the first load, clear the load counter. */ 1164 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1165 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1166 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1167 else { 1168 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1169 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1170 } 1171 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1172 BGE_APE_HOST_SEG_SIG_MAGIC); 1173 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1174 BGE_APE_HOST_SEG_LEN_MAGIC); 1175 1176 /* Add some version info if bge(4) supports it. */ 1177 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1178 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1179 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1180 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1181 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1182 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_START); 1185 event = BGE_APE_EVENT_STATUS_STATE_START; 1186 break; 1187 case BGE_RESET_SHUTDOWN: 1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1189 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1190 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1191 break; 1192 case BGE_RESET_SUSPEND: 1193 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1194 break; 1195 default: 1196 return; 1197 } 1198 1199 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1200 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1201 } 1202 1203 static uint8_t 1204 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1205 { 1206 uint32_t access, byte = 0; 1207 int i; 1208 1209 /* Lock. */ 1210 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1211 for (i = 0; i < 8000; i++) { 1212 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1213 break; 1214 DELAY(20); 1215 } 1216 if (i == 8000) 1217 return 1; 1218 1219 /* Enable access. */ 1220 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1221 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1222 1223 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1224 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1225 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1226 DELAY(10); 1227 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1228 DELAY(10); 1229 break; 1230 } 1231 } 1232 1233 if (i == BGE_TIMEOUT * 10) { 1234 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1235 return 1; 1236 } 1237 1238 /* Get result. */ 1239 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1240 1241 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1242 1243 /* Disable access. */ 1244 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1245 1246 /* Unlock. */ 1247 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Read a sequence of bytes from NVRAM. 1254 */ 1255 static int 1256 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1257 { 1258 int error = 0, i; 1259 uint8_t byte = 0; 1260 1261 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1262 return 1; 1263 1264 for (i = 0; i < cnt; i++) { 1265 error = bge_nvram_getbyte(sc, off + i, &byte); 1266 if (error) 1267 break; 1268 *(dest + i) = byte; 1269 } 1270 1271 return (error ? 1 : 0); 1272 } 1273 1274 /* 1275 * Read a byte of data stored in the EEPROM at address 'addr.' The 1276 * BCM570x supports both the traditional bitbang interface and an 1277 * auto access interface for reading the EEPROM. We use the auto 1278 * access method. 1279 */ 1280 static uint8_t 1281 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1282 { 1283 int i; 1284 uint32_t byte = 0; 1285 1286 /* 1287 * Enable use of auto EEPROM access so we can avoid 1288 * having to use the bitbang method. 1289 */ 1290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1291 1292 /* Reset the EEPROM, load the clock period. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, 1294 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1295 DELAY(20); 1296 1297 /* Issue the read EEPROM command. */ 1298 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1299 1300 /* Wait for completion */ 1301 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1302 DELAY(10); 1303 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1304 break; 1305 } 1306 1307 if (i == BGE_TIMEOUT * 10) { 1308 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1309 return 1; 1310 } 1311 1312 /* Get result. */ 1313 byte = CSR_READ_4(sc, BGE_EE_DATA); 1314 1315 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1316 1317 return 0; 1318 } 1319 1320 /* 1321 * Read a sequence of bytes from the EEPROM. 1322 */ 1323 static int 1324 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1325 { 1326 int error = 0, i; 1327 uint8_t byte = 0; 1328 char *dest = destv; 1329 1330 for (i = 0; i < cnt; i++) { 1331 error = bge_eeprom_getbyte(sc, off + i, &byte); 1332 if (error) 1333 break; 1334 *(dest + i) = byte; 1335 } 1336 1337 return (error ? 1 : 0); 1338 } 1339 1340 static int 1341 bge_miibus_readreg(device_t dev, int phy, int reg) 1342 { 1343 struct bge_softc *sc = device_private(dev); 1344 uint32_t val; 1345 uint32_t autopoll; 1346 int i; 1347 1348 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1349 return 0; 1350 1351 /* Reading with autopolling on may trigger PCI errors */ 1352 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1353 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1354 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1355 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1356 DELAY(80); 1357 } 1358 1359 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1360 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1361 1362 for (i = 0; i < BGE_TIMEOUT; i++) { 1363 delay(10); 1364 val = CSR_READ_4(sc, BGE_MI_COMM); 1365 if (!(val & BGE_MICOMM_BUSY)) { 1366 DELAY(5); 1367 val = CSR_READ_4(sc, BGE_MI_COMM); 1368 break; 1369 } 1370 } 1371 1372 if (i == BGE_TIMEOUT) { 1373 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1374 val = 0; 1375 goto done; 1376 } 1377 1378 done: 1379 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1380 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1381 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1382 DELAY(80); 1383 } 1384 1385 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1386 1387 if (val & BGE_MICOMM_READFAIL) 1388 return 0; 1389 1390 return (val & 0xFFFF); 1391 } 1392 1393 static void 1394 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1395 { 1396 struct bge_softc *sc = device_private(dev); 1397 uint32_t autopoll; 1398 int i; 1399 1400 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1401 return; 1402 1403 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1404 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1405 return; 1406 1407 /* Reading with autopolling on may trigger PCI errors */ 1408 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1409 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1410 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1411 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1412 DELAY(80); 1413 } 1414 1415 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1416 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1417 1418 for (i = 0; i < BGE_TIMEOUT; i++) { 1419 delay(10); 1420 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1421 delay(5); 1422 CSR_READ_4(sc, BGE_MI_COMM); 1423 break; 1424 } 1425 } 1426 1427 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1428 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1429 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1430 delay(80); 1431 } 1432 1433 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1434 1435 if (i == BGE_TIMEOUT) 1436 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1437 } 1438 1439 static void 1440 bge_miibus_statchg(struct ifnet *ifp) 1441 { 1442 struct bge_softc *sc = ifp->if_softc; 1443 struct mii_data *mii = &sc->bge_mii; 1444 uint32_t mac_mode, rx_mode, tx_mode; 1445 1446 /* 1447 * Get flow control negotiation result. 1448 */ 1449 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1450 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1451 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1452 1453 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1454 mii->mii_media_status & IFM_ACTIVE && 1455 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1456 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1457 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1458 (!(mii->mii_media_status & IFM_ACTIVE) || 1459 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1460 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1461 1462 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1463 return; 1464 1465 /* Set the port mode (MII/GMII) to match the link speed. */ 1466 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1467 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1468 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1469 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1470 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1471 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1472 mac_mode |= BGE_PORTMODE_GMII; 1473 else 1474 mac_mode |= BGE_PORTMODE_MII; 1475 1476 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1477 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1478 if ((mii->mii_media_active & IFM_FDX) != 0) { 1479 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1480 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1481 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1482 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1483 } else 1484 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1485 1486 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1487 DELAY(40); 1488 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1489 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1490 } 1491 1492 /* 1493 * Update rx threshold levels to values in a particular slot 1494 * of the interrupt-mitigation table bge_rx_threshes. 1495 */ 1496 static void 1497 bge_set_thresh(struct ifnet *ifp, int lvl) 1498 { 1499 struct bge_softc *sc = ifp->if_softc; 1500 int s; 1501 1502 /* For now, just save the new Rx-intr thresholds and record 1503 * that a threshold update is pending. Updating the hardware 1504 * registers here (even at splhigh()) is observed to 1505 * occasionaly cause glitches where Rx-interrupts are not 1506 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1507 */ 1508 s = splnet(); 1509 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1510 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1511 sc->bge_pending_rxintr_change = 1; 1512 splx(s); 1513 } 1514 1515 1516 /* 1517 * Update Rx thresholds of all bge devices 1518 */ 1519 static void 1520 bge_update_all_threshes(int lvl) 1521 { 1522 struct ifnet *ifp; 1523 const char * const namebuf = "bge"; 1524 int namelen; 1525 1526 if (lvl < 0) 1527 lvl = 0; 1528 else if (lvl >= NBGE_RX_THRESH) 1529 lvl = NBGE_RX_THRESH - 1; 1530 1531 namelen = strlen(namebuf); 1532 /* 1533 * Now search all the interfaces for this name/number 1534 */ 1535 IFNET_FOREACH(ifp) { 1536 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1537 continue; 1538 /* We got a match: update if doing auto-threshold-tuning */ 1539 if (bge_auto_thresh) 1540 bge_set_thresh(ifp, lvl); 1541 } 1542 } 1543 1544 /* 1545 * Handle events that have triggered interrupts. 1546 */ 1547 static void 1548 bge_handle_events(struct bge_softc *sc) 1549 { 1550 1551 return; 1552 } 1553 1554 /* 1555 * Memory management for jumbo frames. 1556 */ 1557 1558 static int 1559 bge_alloc_jumbo_mem(struct bge_softc *sc) 1560 { 1561 char *ptr, *kva; 1562 bus_dma_segment_t seg; 1563 int i, rseg, state, error; 1564 struct bge_jpool_entry *entry; 1565 1566 state = error = 0; 1567 1568 /* Grab a big chunk o' storage. */ 1569 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1570 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1571 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1572 return ENOBUFS; 1573 } 1574 1575 state = 1; 1576 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1577 BUS_DMA_NOWAIT)) { 1578 aprint_error_dev(sc->bge_dev, 1579 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1580 error = ENOBUFS; 1581 goto out; 1582 } 1583 1584 state = 2; 1585 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1586 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1587 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1588 error = ENOBUFS; 1589 goto out; 1590 } 1591 1592 state = 3; 1593 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1594 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1595 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1596 error = ENOBUFS; 1597 goto out; 1598 } 1599 1600 state = 4; 1601 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1602 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1603 1604 SLIST_INIT(&sc->bge_jfree_listhead); 1605 SLIST_INIT(&sc->bge_jinuse_listhead); 1606 1607 /* 1608 * Now divide it up into 9K pieces and save the addresses 1609 * in an array. 1610 */ 1611 ptr = sc->bge_cdata.bge_jumbo_buf; 1612 for (i = 0; i < BGE_JSLOTS; i++) { 1613 sc->bge_cdata.bge_jslots[i] = ptr; 1614 ptr += BGE_JLEN; 1615 entry = malloc(sizeof(struct bge_jpool_entry), 1616 M_DEVBUF, M_NOWAIT); 1617 if (entry == NULL) { 1618 aprint_error_dev(sc->bge_dev, 1619 "no memory for jumbo buffer queue!\n"); 1620 error = ENOBUFS; 1621 goto out; 1622 } 1623 entry->slot = i; 1624 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1625 entry, jpool_entries); 1626 } 1627 out: 1628 if (error != 0) { 1629 switch (state) { 1630 case 4: 1631 bus_dmamap_unload(sc->bge_dmatag, 1632 sc->bge_cdata.bge_rx_jumbo_map); 1633 case 3: 1634 bus_dmamap_destroy(sc->bge_dmatag, 1635 sc->bge_cdata.bge_rx_jumbo_map); 1636 case 2: 1637 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1638 case 1: 1639 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1640 break; 1641 default: 1642 break; 1643 } 1644 } 1645 1646 return error; 1647 } 1648 1649 /* 1650 * Allocate a jumbo buffer. 1651 */ 1652 static void * 1653 bge_jalloc(struct bge_softc *sc) 1654 { 1655 struct bge_jpool_entry *entry; 1656 1657 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1658 1659 if (entry == NULL) { 1660 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1661 return NULL; 1662 } 1663 1664 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1665 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1666 return (sc->bge_cdata.bge_jslots[entry->slot]); 1667 } 1668 1669 /* 1670 * Release a jumbo buffer. 1671 */ 1672 static void 1673 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1674 { 1675 struct bge_jpool_entry *entry; 1676 struct bge_softc *sc; 1677 int i, s; 1678 1679 /* Extract the softc struct pointer. */ 1680 sc = (struct bge_softc *)arg; 1681 1682 if (sc == NULL) 1683 panic("bge_jfree: can't find softc pointer!"); 1684 1685 /* calculate the slot this buffer belongs to */ 1686 1687 i = ((char *)buf 1688 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1689 1690 if ((i < 0) || (i >= BGE_JSLOTS)) 1691 panic("bge_jfree: asked to free buffer that we don't manage!"); 1692 1693 s = splvm(); 1694 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1695 if (entry == NULL) 1696 panic("bge_jfree: buffer not in use!"); 1697 entry->slot = i; 1698 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1699 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1700 1701 if (__predict_true(m != NULL)) 1702 pool_cache_put(mb_cache, m); 1703 splx(s); 1704 } 1705 1706 1707 /* 1708 * Initialize a standard receive ring descriptor. 1709 */ 1710 static int 1711 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1712 bus_dmamap_t dmamap) 1713 { 1714 struct mbuf *m_new = NULL; 1715 struct bge_rx_bd *r; 1716 int error; 1717 1718 if (dmamap == NULL) { 1719 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1720 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1721 if (error != 0) 1722 return error; 1723 } 1724 1725 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1726 1727 if (m == NULL) { 1728 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1729 if (m_new == NULL) 1730 return ENOBUFS; 1731 1732 MCLGET(m_new, M_DONTWAIT); 1733 if (!(m_new->m_flags & M_EXT)) { 1734 m_freem(m_new); 1735 return ENOBUFS; 1736 } 1737 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1738 1739 } else { 1740 m_new = m; 1741 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1742 m_new->m_data = m_new->m_ext.ext_buf; 1743 } 1744 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1745 m_adj(m_new, ETHER_ALIGN); 1746 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1747 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1748 return ENOBUFS; 1749 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1750 BUS_DMASYNC_PREREAD); 1751 1752 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1753 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1754 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1755 r->bge_flags = BGE_RXBDFLAG_END; 1756 r->bge_len = m_new->m_len; 1757 r->bge_idx = i; 1758 1759 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1760 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1761 i * sizeof (struct bge_rx_bd), 1762 sizeof (struct bge_rx_bd), 1763 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1764 1765 return 0; 1766 } 1767 1768 /* 1769 * Initialize a jumbo receive ring descriptor. This allocates 1770 * a jumbo buffer from the pool managed internally by the driver. 1771 */ 1772 static int 1773 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1774 { 1775 struct mbuf *m_new = NULL; 1776 struct bge_rx_bd *r; 1777 void *buf = NULL; 1778 1779 if (m == NULL) { 1780 1781 /* Allocate the mbuf. */ 1782 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1783 if (m_new == NULL) 1784 return ENOBUFS; 1785 1786 /* Allocate the jumbo buffer */ 1787 buf = bge_jalloc(sc); 1788 if (buf == NULL) { 1789 m_freem(m_new); 1790 aprint_error_dev(sc->bge_dev, 1791 "jumbo allocation failed -- packet dropped!\n"); 1792 return ENOBUFS; 1793 } 1794 1795 /* Attach the buffer to the mbuf. */ 1796 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1797 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1798 bge_jfree, sc); 1799 m_new->m_flags |= M_EXT_RW; 1800 } else { 1801 m_new = m; 1802 buf = m_new->m_data = m_new->m_ext.ext_buf; 1803 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1804 } 1805 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1806 m_adj(m_new, ETHER_ALIGN); 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1808 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1809 BUS_DMASYNC_PREREAD); 1810 /* Set up the descriptor. */ 1811 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1812 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1813 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1814 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1815 r->bge_len = m_new->m_len; 1816 r->bge_idx = i; 1817 1818 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1819 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1820 i * sizeof (struct bge_rx_bd), 1821 sizeof (struct bge_rx_bd), 1822 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1823 1824 return 0; 1825 } 1826 1827 /* 1828 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1829 * that's 1MB or memory, which is a lot. For now, we fill only the first 1830 * 256 ring entries and hope that our CPU is fast enough to keep up with 1831 * the NIC. 1832 */ 1833 static int 1834 bge_init_rx_ring_std(struct bge_softc *sc) 1835 { 1836 int i; 1837 1838 if (sc->bge_flags & BGEF_RXRING_VALID) 1839 return 0; 1840 1841 for (i = 0; i < BGE_SSLOTS; i++) { 1842 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1843 return ENOBUFS; 1844 } 1845 1846 sc->bge_std = i - 1; 1847 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1848 1849 sc->bge_flags |= BGEF_RXRING_VALID; 1850 1851 return 0; 1852 } 1853 1854 static void 1855 bge_free_rx_ring_std(struct bge_softc *sc) 1856 { 1857 int i; 1858 1859 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1860 return; 1861 1862 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1863 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1864 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1865 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1866 bus_dmamap_destroy(sc->bge_dmatag, 1867 sc->bge_cdata.bge_rx_std_map[i]); 1868 } 1869 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1870 sizeof(struct bge_rx_bd)); 1871 } 1872 1873 sc->bge_flags &= ~BGEF_RXRING_VALID; 1874 } 1875 1876 static int 1877 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1878 { 1879 int i; 1880 volatile struct bge_rcb *rcb; 1881 1882 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1883 return 0; 1884 1885 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1886 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1887 return ENOBUFS; 1888 } 1889 1890 sc->bge_jumbo = i - 1; 1891 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1892 1893 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1894 rcb->bge_maxlen_flags = 0; 1895 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1896 1897 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1898 1899 return 0; 1900 } 1901 1902 static void 1903 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1904 { 1905 int i; 1906 1907 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1908 return; 1909 1910 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1911 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1912 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1913 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1914 } 1915 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1916 sizeof(struct bge_rx_bd)); 1917 } 1918 1919 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1920 } 1921 1922 static void 1923 bge_free_tx_ring(struct bge_softc *sc) 1924 { 1925 int i; 1926 struct txdmamap_pool_entry *dma; 1927 1928 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1929 return; 1930 1931 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1932 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1933 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1934 sc->bge_cdata.bge_tx_chain[i] = NULL; 1935 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1936 link); 1937 sc->txdma[i] = 0; 1938 } 1939 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1940 sizeof(struct bge_tx_bd)); 1941 } 1942 1943 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1944 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1945 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1946 free(dma, M_DEVBUF); 1947 } 1948 1949 sc->bge_flags &= ~BGEF_TXRING_VALID; 1950 } 1951 1952 static int 1953 bge_init_tx_ring(struct bge_softc *sc) 1954 { 1955 struct ifnet *ifp = &sc->ethercom.ec_if; 1956 int i; 1957 bus_dmamap_t dmamap; 1958 bus_size_t maxsegsz; 1959 struct txdmamap_pool_entry *dma; 1960 1961 if (sc->bge_flags & BGEF_TXRING_VALID) 1962 return 0; 1963 1964 sc->bge_txcnt = 0; 1965 sc->bge_tx_saved_considx = 0; 1966 1967 /* Initialize transmit producer index for host-memory send ring. */ 1968 sc->bge_tx_prodidx = 0; 1969 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1970 /* 5700 b2 errata */ 1971 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1972 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1973 1974 /* NIC-memory send ring not used; initialize to zero. */ 1975 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1976 /* 5700 b2 errata */ 1977 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1978 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1979 1980 /* Limit DMA segment size for some chips */ 1981 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1982 (ifp->if_mtu <= ETHERMTU)) 1983 maxsegsz = 2048; 1984 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1985 maxsegsz = 4096; 1986 else 1987 maxsegsz = ETHER_MAX_LEN_JUMBO; 1988 SLIST_INIT(&sc->txdma_list); 1989 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1990 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1991 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, 1992 &dmamap)) 1993 return ENOBUFS; 1994 if (dmamap == NULL) 1995 panic("dmamap NULL in bge_init_tx_ring"); 1996 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1997 if (dma == NULL) { 1998 aprint_error_dev(sc->bge_dev, 1999 "can't alloc txdmamap_pool_entry\n"); 2000 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2001 return ENOMEM; 2002 } 2003 dma->dmamap = dmamap; 2004 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2005 } 2006 2007 sc->bge_flags |= BGEF_TXRING_VALID; 2008 2009 return 0; 2010 } 2011 2012 static void 2013 bge_setmulti(struct bge_softc *sc) 2014 { 2015 struct ethercom *ac = &sc->ethercom; 2016 struct ifnet *ifp = &ac->ec_if; 2017 struct ether_multi *enm; 2018 struct ether_multistep step; 2019 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2020 uint32_t h; 2021 int i; 2022 2023 if (ifp->if_flags & IFF_PROMISC) 2024 goto allmulti; 2025 2026 /* Now program new ones. */ 2027 ETHER_FIRST_MULTI(step, ac, enm); 2028 while (enm != NULL) { 2029 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2030 /* 2031 * We must listen to a range of multicast addresses. 2032 * For now, just accept all multicasts, rather than 2033 * trying to set only those filter bits needed to match 2034 * the range. (At this time, the only use of address 2035 * ranges is for IP multicast routing, for which the 2036 * range is big enough to require all bits set.) 2037 */ 2038 goto allmulti; 2039 } 2040 2041 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2042 2043 /* Just want the 7 least-significant bits. */ 2044 h &= 0x7f; 2045 2046 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2047 ETHER_NEXT_MULTI(step, enm); 2048 } 2049 2050 ifp->if_flags &= ~IFF_ALLMULTI; 2051 goto setit; 2052 2053 allmulti: 2054 ifp->if_flags |= IFF_ALLMULTI; 2055 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2056 2057 setit: 2058 for (i = 0; i < 4; i++) 2059 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2060 } 2061 2062 static void 2063 bge_sig_pre_reset(struct bge_softc *sc, int type) 2064 { 2065 2066 /* 2067 * Some chips don't like this so only do this if ASF is enabled 2068 */ 2069 if (sc->bge_asf_mode) 2070 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2071 2072 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2073 switch (type) { 2074 case BGE_RESET_START: 2075 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2076 BGE_FW_DRV_STATE_START); 2077 break; 2078 case BGE_RESET_SHUTDOWN: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_UNLOAD); 2081 break; 2082 case BGE_RESET_SUSPEND: 2083 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2084 BGE_FW_DRV_STATE_SUSPEND); 2085 break; 2086 } 2087 } 2088 2089 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2090 bge_ape_driver_state_change(sc, type); 2091 } 2092 2093 static void 2094 bge_sig_post_reset(struct bge_softc *sc, int type) 2095 { 2096 2097 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2098 switch (type) { 2099 case BGE_RESET_START: 2100 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2101 BGE_FW_DRV_STATE_START_DONE); 2102 /* START DONE */ 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD_DONE); 2107 break; 2108 } 2109 } 2110 2111 if (type == BGE_RESET_SHUTDOWN) 2112 bge_ape_driver_state_change(sc, type); 2113 } 2114 2115 static void 2116 bge_sig_legacy(struct bge_softc *sc, int type) 2117 { 2118 2119 if (sc->bge_asf_mode) { 2120 switch (type) { 2121 case BGE_RESET_START: 2122 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2123 BGE_FW_DRV_STATE_START); 2124 break; 2125 case BGE_RESET_SHUTDOWN: 2126 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2127 BGE_FW_DRV_STATE_UNLOAD); 2128 break; 2129 } 2130 } 2131 } 2132 2133 static void 2134 bge_wait_for_event_ack(struct bge_softc *sc) 2135 { 2136 int i; 2137 2138 /* wait up to 2500usec */ 2139 for (i = 0; i < 250; i++) { 2140 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2141 BGE_RX_CPU_DRV_EVENT)) 2142 break; 2143 DELAY(10); 2144 } 2145 } 2146 2147 static void 2148 bge_stop_fw(struct bge_softc *sc) 2149 { 2150 2151 if (sc->bge_asf_mode) { 2152 bge_wait_for_event_ack(sc); 2153 2154 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2155 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2156 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2157 2158 bge_wait_for_event_ack(sc); 2159 } 2160 } 2161 2162 static int 2163 bge_poll_fw(struct bge_softc *sc) 2164 { 2165 uint32_t val; 2166 int i; 2167 2168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2169 for (i = 0; i < BGE_TIMEOUT; i++) { 2170 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2171 if (val & BGE_VCPU_STATUS_INIT_DONE) 2172 break; 2173 DELAY(100); 2174 } 2175 if (i >= BGE_TIMEOUT) { 2176 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2177 return -1; 2178 } 2179 } else if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) { 2180 /* 2181 * Poll the value location we just wrote until 2182 * we see the 1's complement of the magic number. 2183 * This indicates that the firmware initialization 2184 * is complete. 2185 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2186 */ 2187 for (i = 0; i < BGE_TIMEOUT; i++) { 2188 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2189 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2190 break; 2191 DELAY(10); 2192 } 2193 2194 if (i >= BGE_TIMEOUT) { 2195 aprint_error_dev(sc->bge_dev, 2196 "firmware handshake timed out, val = %x\n", val); 2197 return -1; 2198 } 2199 } 2200 2201 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2202 /* tg3 says we have to wait extra time */ 2203 delay(10 * 1000); 2204 } 2205 2206 return 0; 2207 } 2208 2209 int 2210 bge_phy_addr(struct bge_softc *sc) 2211 { 2212 struct pci_attach_args *pa = &(sc->bge_pa); 2213 int phy_addr = 1; 2214 2215 /* 2216 * PHY address mapping for various devices. 2217 * 2218 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2219 * ---------+-------+-------+-------+-------+ 2220 * BCM57XX | 1 | X | X | X | 2221 * BCM5704 | 1 | X | 1 | X | 2222 * BCM5717 | 1 | 8 | 2 | 9 | 2223 * BCM5719 | 1 | 8 | 2 | 9 | 2224 * BCM5720 | 1 | 8 | 2 | 9 | 2225 * 2226 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2227 * ---------+-------+-------+-------+-------+ 2228 * BCM57XX | X | X | X | X | 2229 * BCM5704 | X | X | X | X | 2230 * BCM5717 | X | X | X | X | 2231 * BCM5719 | 3 | 10 | 4 | 11 | 2232 * BCM5720 | X | X | X | X | 2233 * 2234 * Other addresses may respond but they are not 2235 * IEEE compliant PHYs and should be ignored. 2236 */ 2237 switch (BGE_ASICREV(sc->bge_chipid)) { 2238 case BGE_ASICREV_BCM5717: 2239 case BGE_ASICREV_BCM5719: 2240 case BGE_ASICREV_BCM5720: 2241 phy_addr = pa->pa_function; 2242 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2243 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2244 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2245 } else { 2246 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2247 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2248 } 2249 } 2250 2251 return phy_addr; 2252 } 2253 2254 /* 2255 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2256 * self-test results. 2257 */ 2258 static int 2259 bge_chipinit(struct bge_softc *sc) 2260 { 2261 uint32_t dma_rw_ctl, mode_ctl, reg; 2262 int i; 2263 2264 /* Set endianness before we access any non-PCI registers. */ 2265 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2266 BGE_INIT); 2267 2268 /* 2269 * Clear the MAC statistics block in the NIC's 2270 * internal memory. 2271 */ 2272 for (i = BGE_STATS_BLOCK; 2273 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2274 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2275 2276 for (i = BGE_STATUS_BLOCK; 2277 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2278 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2279 2280 /* 5717 workaround from tg3 */ 2281 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2282 /* Save */ 2283 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2284 2285 /* Temporary modify MODE_CTL to control TLP */ 2286 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2287 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2288 2289 /* Control TLP */ 2290 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2291 BGE_TLP_PHYCTL1); 2292 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2293 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2294 2295 /* Restore */ 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2297 } 2298 2299 if (BGE_IS_57765_FAMILY(sc)) { 2300 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2301 /* Save */ 2302 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2303 2304 /* Temporary modify MODE_CTL to control TLP */ 2305 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2306 CSR_WRITE_4(sc, BGE_MODE_CTL, 2307 reg | BGE_MODECTL_PCIE_TLPADDR1); 2308 2309 /* Control TLP */ 2310 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2311 BGE_TLP_PHYCTL5); 2312 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2313 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2314 2315 /* Restore */ 2316 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2317 } 2318 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2319 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2320 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2321 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2322 2323 /* Save */ 2324 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2325 2326 /* Temporary modify MODE_CTL to control TLP */ 2327 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2328 CSR_WRITE_4(sc, BGE_MODE_CTL, 2329 reg | BGE_MODECTL_PCIE_TLPADDR0); 2330 2331 /* Control TLP */ 2332 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2333 BGE_TLP_FTSMAX); 2334 reg &= ~BGE_TLP_FTSMAX_MSK; 2335 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2336 reg | BGE_TLP_FTSMAX_VAL); 2337 2338 /* Restore */ 2339 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2340 } 2341 2342 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2343 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2344 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2345 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2346 } 2347 2348 /* Set up the PCI DMA control register. */ 2349 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2350 if (sc->bge_flags & BGEF_PCIE) { 2351 /* Read watermark not used, 128 bytes for write. */ 2352 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2353 device_xname(sc->bge_dev))); 2354 if (sc->bge_mps >= 256) 2355 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2356 else 2357 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2358 } else if (sc->bge_flags & BGEF_PCIX) { 2359 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2360 device_xname(sc->bge_dev))); 2361 /* PCI-X bus */ 2362 if (BGE_IS_5714_FAMILY(sc)) { 2363 /* 256 bytes for read and write. */ 2364 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2365 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2366 2367 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2368 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2369 else 2370 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2371 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2372 /* 1536 bytes for read, 384 bytes for write. */ 2373 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2374 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2375 } else { 2376 /* 384 bytes for read and write. */ 2377 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2378 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2379 (0x0F); 2380 } 2381 2382 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2383 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2384 uint32_t tmp; 2385 2386 /* Set ONEDMA_ATONCE for hardware workaround. */ 2387 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2388 if (tmp == 6 || tmp == 7) 2389 dma_rw_ctl |= 2390 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2391 2392 /* Set PCI-X DMA write workaround. */ 2393 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2394 } 2395 } else { 2396 /* Conventional PCI bus: 256 bytes for read and write. */ 2397 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2398 device_xname(sc->bge_dev))); 2399 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2400 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2401 2402 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2403 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2404 dma_rw_ctl |= 0x0F; 2405 } 2406 2407 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2408 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2409 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2410 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2411 2412 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2413 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2414 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2415 2416 if (BGE_IS_57765_PLUS(sc)) { 2417 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2418 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2419 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2420 2421 /* 2422 * Enable HW workaround for controllers that misinterpret 2423 * a status tag update and leave interrupts permanently 2424 * disabled. 2425 */ 2426 if (!BGE_IS_57765_FAMILY(sc) && 2427 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2428 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2429 } 2430 2431 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2432 dma_rw_ctl); 2433 2434 /* 2435 * Set up general mode register. 2436 */ 2437 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2438 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2439 /* Retain Host-2-BMC settings written by APE firmware. */ 2440 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2441 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2442 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2443 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2444 } 2445 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2446 BGE_MODECTL_TX_NO_PHDR_CSUM; 2447 2448 /* 2449 * BCM5701 B5 have a bug causing data corruption when using 2450 * 64-bit DMA reads, which can be terminated early and then 2451 * completed later as 32-bit accesses, in combination with 2452 * certain bridges. 2453 */ 2454 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2455 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2456 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2457 2458 /* 2459 * Tell the firmware the driver is running 2460 */ 2461 if (sc->bge_asf_mode & ASF_STACKUP) 2462 mode_ctl |= BGE_MODECTL_STACKUP; 2463 2464 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2465 2466 /* 2467 * Disable memory write invalidate. Apparently it is not supported 2468 * properly by these devices. 2469 */ 2470 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2471 PCI_COMMAND_INVALIDATE_ENABLE); 2472 2473 #ifdef __brokenalpha__ 2474 /* 2475 * Must insure that we do not cross an 8K (bytes) boundary 2476 * for DMA reads. Our highest limit is 1K bytes. This is a 2477 * restriction on some ALPHA platforms with early revision 2478 * 21174 PCI chipsets, such as the AlphaPC 164lx 2479 */ 2480 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2481 #endif 2482 2483 /* Set the timer prescaler (always 66MHz) */ 2484 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2485 2486 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2487 DELAY(40); /* XXX */ 2488 2489 /* Put PHY into ready state */ 2490 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2491 DELAY(40); 2492 } 2493 2494 return 0; 2495 } 2496 2497 static int 2498 bge_blockinit(struct bge_softc *sc) 2499 { 2500 volatile struct bge_rcb *rcb; 2501 bus_size_t rcb_addr; 2502 struct ifnet *ifp = &sc->ethercom.ec_if; 2503 bge_hostaddr taddr; 2504 uint32_t dmactl, val; 2505 int i, limit; 2506 2507 /* 2508 * Initialize the memory window pointer register so that 2509 * we can access the first 32K of internal NIC RAM. This will 2510 * allow us to set up the TX send ring RCBs and the RX return 2511 * ring RCBs, plus other things which live in NIC memory. 2512 */ 2513 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2514 2515 if (!BGE_IS_5705_PLUS(sc)) { 2516 /* 57XX step 33 */ 2517 /* Configure mbuf memory pool */ 2518 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2519 BGE_BUFFPOOL_1); 2520 2521 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2522 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2523 else 2524 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2525 2526 /* 57XX step 34 */ 2527 /* Configure DMA resource pool */ 2528 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2529 BGE_DMA_DESCRIPTORS); 2530 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2531 } 2532 2533 /* 5718 step 11, 57XX step 35 */ 2534 /* 2535 * Configure mbuf pool watermarks. New broadcom docs strongly 2536 * recommend these. 2537 */ 2538 if (BGE_IS_5717_PLUS(sc)) { 2539 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2540 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2541 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2542 } else if (BGE_IS_5705_PLUS(sc)) { 2543 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2544 2545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2546 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2547 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2548 } else { 2549 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2550 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2551 } 2552 } else { 2553 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2554 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2555 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2556 } 2557 2558 /* 57XX step 36 */ 2559 /* Configure DMA resource watermarks */ 2560 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2561 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2562 2563 /* 5718 step 13, 57XX step 38 */ 2564 /* Enable buffer manager */ 2565 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2566 /* 2567 * Change the arbitration algorithm of TXMBUF read request to 2568 * round-robin instead of priority based for BCM5719. When 2569 * TXFIFO is almost empty, RDMA will hold its request until 2570 * TXFIFO is not almost empty. 2571 */ 2572 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2573 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2574 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2575 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2576 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2577 val |= BGE_BMANMODE_LOMBUF_ATTN; 2578 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2579 2580 /* 57XX step 39 */ 2581 /* Poll for buffer manager start indication */ 2582 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2583 DELAY(10); 2584 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2585 break; 2586 } 2587 2588 if (i == BGE_TIMEOUT * 2) { 2589 aprint_error_dev(sc->bge_dev, 2590 "buffer manager failed to start\n"); 2591 return ENXIO; 2592 } 2593 2594 /* 57XX step 40 */ 2595 /* Enable flow-through queues */ 2596 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2597 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2598 2599 /* Wait until queue initialization is complete */ 2600 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2601 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2602 break; 2603 DELAY(10); 2604 } 2605 2606 if (i == BGE_TIMEOUT * 2) { 2607 aprint_error_dev(sc->bge_dev, 2608 "flow-through queue init failed\n"); 2609 return ENXIO; 2610 } 2611 2612 /* 2613 * Summary of rings supported by the controller: 2614 * 2615 * Standard Receive Producer Ring 2616 * - This ring is used to feed receive buffers for "standard" 2617 * sized frames (typically 1536 bytes) to the controller. 2618 * 2619 * Jumbo Receive Producer Ring 2620 * - This ring is used to feed receive buffers for jumbo sized 2621 * frames (i.e. anything bigger than the "standard" frames) 2622 * to the controller. 2623 * 2624 * Mini Receive Producer Ring 2625 * - This ring is used to feed receive buffers for "mini" 2626 * sized frames to the controller. 2627 * - This feature required external memory for the controller 2628 * but was never used in a production system. Should always 2629 * be disabled. 2630 * 2631 * Receive Return Ring 2632 * - After the controller has placed an incoming frame into a 2633 * receive buffer that buffer is moved into a receive return 2634 * ring. The driver is then responsible to passing the 2635 * buffer up to the stack. Many versions of the controller 2636 * support multiple RR rings. 2637 * 2638 * Send Ring 2639 * - This ring is used for outgoing frames. Many versions of 2640 * the controller support multiple send rings. 2641 */ 2642 2643 /* 5718 step 15, 57XX step 41 */ 2644 /* Initialize the standard RX ring control block */ 2645 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2646 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2647 /* 5718 step 16 */ 2648 if (BGE_IS_57765_PLUS(sc)) { 2649 /* 2650 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2651 * Bits 15-2 : Maximum RX frame size 2652 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2653 * Bit 0 : Reserved 2654 */ 2655 rcb->bge_maxlen_flags = 2656 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2657 } else if (BGE_IS_5705_PLUS(sc)) { 2658 /* 2659 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2660 * Bits 15-2 : Reserved (should be 0) 2661 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2662 * Bit 0 : Reserved 2663 */ 2664 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2665 } else { 2666 /* 2667 * Ring size is always XXX entries 2668 * Bits 31-16: Maximum RX frame size 2669 * Bits 15-2 : Reserved (should be 0) 2670 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2671 * Bit 0 : Reserved 2672 */ 2673 rcb->bge_maxlen_flags = 2674 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2675 } 2676 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2677 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2678 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2679 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2680 else 2681 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2682 /* Write the standard receive producer ring control block. */ 2683 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2684 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2685 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2686 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2687 2688 /* Reset the standard receive producer ring producer index. */ 2689 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2690 2691 /* 57XX step 42 */ 2692 /* 2693 * Initialize the jumbo RX ring control block 2694 * We set the 'ring disabled' bit in the flags 2695 * field until we're actually ready to start 2696 * using this ring (i.e. once we set the MTU 2697 * high enough to require it). 2698 */ 2699 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2700 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2701 BGE_HOSTADDR(rcb->bge_hostaddr, 2702 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2703 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2704 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2705 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2706 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2707 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2708 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2709 else 2710 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2711 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2712 rcb->bge_hostaddr.bge_addr_hi); 2713 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2714 rcb->bge_hostaddr.bge_addr_lo); 2715 /* Program the jumbo receive producer ring RCB parameters. */ 2716 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2717 rcb->bge_maxlen_flags); 2718 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2719 /* Reset the jumbo receive producer ring producer index. */ 2720 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2721 } 2722 2723 /* 57XX step 43 */ 2724 /* Disable the mini receive producer ring RCB. */ 2725 if (BGE_IS_5700_FAMILY(sc)) { 2726 /* Set up dummy disabled mini ring RCB */ 2727 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2728 rcb->bge_maxlen_flags = 2729 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2730 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2731 rcb->bge_maxlen_flags); 2732 /* Reset the mini receive producer ring producer index. */ 2733 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2734 2735 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2736 offsetof(struct bge_ring_data, bge_info), 2737 sizeof (struct bge_gib), 2738 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2739 } 2740 2741 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2742 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2743 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2744 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2745 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2746 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2747 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2748 } 2749 /* 5718 step 14, 57XX step 44 */ 2750 /* 2751 * The BD ring replenish thresholds control how often the 2752 * hardware fetches new BD's from the producer rings in host 2753 * memory. Setting the value too low on a busy system can 2754 * starve the hardware and recue the throughpout. 2755 * 2756 * Set the BD ring replenish thresholds. The recommended 2757 * values are 1/8th the number of descriptors allocated to 2758 * each ring, but since we try to avoid filling the entire 2759 * ring we set these to the minimal value of 8. This needs to 2760 * be done on several of the supported chip revisions anyway, 2761 * to work around HW bugs. 2762 */ 2763 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2764 if (BGE_IS_JUMBO_CAPABLE(sc)) 2765 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2766 2767 /* 5718 step 18 */ 2768 if (BGE_IS_5717_PLUS(sc)) { 2769 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2770 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2771 } 2772 2773 /* 57XX step 45 */ 2774 /* 2775 * Disable all send rings by setting the 'ring disabled' bit 2776 * in the flags field of all the TX send ring control blocks, 2777 * located in NIC memory. 2778 */ 2779 if (BGE_IS_5700_FAMILY(sc)) { 2780 /* 5700 to 5704 had 16 send rings. */ 2781 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2782 } else if (BGE_IS_5717_PLUS(sc)) { 2783 limit = BGE_TX_RINGS_5717_MAX; 2784 } else if (BGE_IS_57765_FAMILY(sc)) { 2785 limit = BGE_TX_RINGS_57765_MAX; 2786 } else 2787 limit = 1; 2788 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2789 for (i = 0; i < limit; i++) { 2790 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2791 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2792 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2793 rcb_addr += sizeof(struct bge_rcb); 2794 } 2795 2796 /* 57XX step 46 and 47 */ 2797 /* Configure send ring RCB 0 (we use only the first ring) */ 2798 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2799 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2800 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2801 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2802 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2803 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2804 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2805 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2806 else 2807 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2808 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2809 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2810 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2811 2812 /* 57XX step 48 */ 2813 /* 2814 * Disable all receive return rings by setting the 2815 * 'ring diabled' bit in the flags field of all the receive 2816 * return ring control blocks, located in NIC memory. 2817 */ 2818 if (BGE_IS_5717_PLUS(sc)) { 2819 /* Should be 17, use 16 until we get an SRAM map. */ 2820 limit = 16; 2821 } else if (BGE_IS_5700_FAMILY(sc)) 2822 limit = BGE_RX_RINGS_MAX; 2823 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2824 BGE_IS_57765_FAMILY(sc)) 2825 limit = 4; 2826 else 2827 limit = 1; 2828 /* Disable all receive return rings */ 2829 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2830 for (i = 0; i < limit; i++) { 2831 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2832 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2833 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2834 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2835 BGE_RCB_FLAG_RING_DISABLED)); 2836 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2837 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2838 (i * (sizeof(uint64_t))), 0); 2839 rcb_addr += sizeof(struct bge_rcb); 2840 } 2841 2842 /* 57XX step 49 */ 2843 /* 2844 * Set up receive return ring 0. Note that the NIC address 2845 * for RX return rings is 0x0. The return rings live entirely 2846 * within the host, so the nicaddr field in the RCB isn't used. 2847 */ 2848 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2849 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2850 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2851 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2852 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2853 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2854 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2855 2856 /* 5718 step 24, 57XX step 53 */ 2857 /* Set random backoff seed for TX */ 2858 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2859 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2860 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2861 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2862 BGE_TX_BACKOFF_SEED_MASK); 2863 2864 /* 5718 step 26, 57XX step 55 */ 2865 /* Set inter-packet gap */ 2866 val = 0x2620; 2867 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2868 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2869 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2870 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2871 2872 /* 5718 step 27, 57XX step 56 */ 2873 /* 2874 * Specify which ring to use for packets that don't match 2875 * any RX rules. 2876 */ 2877 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2878 2879 /* 5718 step 28, 57XX step 57 */ 2880 /* 2881 * Configure number of RX lists. One interrupt distribution 2882 * list, sixteen active lists, one bad frames class. 2883 */ 2884 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2885 2886 /* 5718 step 29, 57XX step 58 */ 2887 /* Inialize RX list placement stats mask. */ 2888 if (BGE_IS_575X_PLUS(sc)) { 2889 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2890 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2891 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2892 } else 2893 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2894 2895 /* 5718 step 30, 57XX step 59 */ 2896 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2897 2898 /* 5718 step 33, 57XX step 62 */ 2899 /* Disable host coalescing until we get it set up */ 2900 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2901 2902 /* 5718 step 34, 57XX step 63 */ 2903 /* Poll to make sure it's shut down. */ 2904 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2905 DELAY(10); 2906 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2907 break; 2908 } 2909 2910 if (i == BGE_TIMEOUT * 2) { 2911 aprint_error_dev(sc->bge_dev, 2912 "host coalescing engine failed to idle\n"); 2913 return ENXIO; 2914 } 2915 2916 /* 5718 step 35, 36, 37 */ 2917 /* Set up host coalescing defaults */ 2918 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2919 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2920 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2921 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2922 if (!(BGE_IS_5705_PLUS(sc))) { 2923 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2924 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2925 } 2926 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2927 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2928 2929 /* Set up address of statistics block */ 2930 if (BGE_IS_5700_FAMILY(sc)) { 2931 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2932 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2933 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2934 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2935 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2936 } 2937 2938 /* 5718 step 38 */ 2939 /* Set up address of status block */ 2940 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2941 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2942 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2943 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2944 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2945 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2946 2947 /* Set up status block size. */ 2948 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2949 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2950 val = BGE_STATBLKSZ_FULL; 2951 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2952 } else { 2953 val = BGE_STATBLKSZ_32BYTE; 2954 bzero(&sc->bge_rdata->bge_status_block, 32); 2955 } 2956 2957 /* 5718 step 39, 57XX step 73 */ 2958 /* Turn on host coalescing state machine */ 2959 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2960 2961 /* 5718 step 40, 57XX step 74 */ 2962 /* Turn on RX BD completion state machine and enable attentions */ 2963 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2964 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2965 2966 /* 5718 step 41, 57XX step 75 */ 2967 /* Turn on RX list placement state machine */ 2968 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2969 2970 /* 57XX step 76 */ 2971 /* Turn on RX list selector state machine. */ 2972 if (!(BGE_IS_5705_PLUS(sc))) 2973 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2974 2975 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2976 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2977 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2978 BGE_MACMODE_FRMHDR_DMA_ENB; 2979 2980 if (sc->bge_flags & BGEF_FIBER_TBI) 2981 val |= BGE_PORTMODE_TBI; 2982 else if (sc->bge_flags & BGEF_FIBER_MII) 2983 val |= BGE_PORTMODE_GMII; 2984 else 2985 val |= BGE_PORTMODE_MII; 2986 2987 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2988 /* Allow APE to send/receive frames. */ 2989 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2990 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2991 2992 /* Turn on DMA, clear stats */ 2993 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2994 /* 5718 step 44 */ 2995 DELAY(40); 2996 2997 /* 5718 step 45, 57XX step 79 */ 2998 /* Set misc. local control, enable interrupts on attentions */ 2999 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3000 if (BGE_IS_5717_PLUS(sc)) { 3001 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3002 /* 5718 step 46 */ 3003 DELAY(100); 3004 } 3005 3006 /* 57XX step 81 */ 3007 /* Turn on DMA completion state machine */ 3008 if (!(BGE_IS_5705_PLUS(sc))) 3009 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3010 3011 /* 5718 step 47, 57XX step 82 */ 3012 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3013 3014 /* 5718 step 48 */ 3015 /* Enable host coalescing bug fix. */ 3016 if (BGE_IS_5755_PLUS(sc)) 3017 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3018 3019 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3020 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3021 3022 /* Turn on write DMA state machine */ 3023 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3024 /* 5718 step 49 */ 3025 DELAY(40); 3026 3027 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3028 3029 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3030 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3031 3032 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3033 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3034 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3035 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3036 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3037 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3038 3039 if (sc->bge_flags & BGEF_PCIE) 3040 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3041 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3042 if (ifp->if_mtu <= ETHERMTU) 3043 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3044 } 3045 if (sc->bge_flags & BGEF_TSO) 3046 val |= BGE_RDMAMODE_TSO4_ENABLE; 3047 3048 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3049 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3050 BGE_RDMAMODE_H2BNC_VLAN_DET; 3051 /* 3052 * Allow multiple outstanding read requests from 3053 * non-LSO read DMA engine. 3054 */ 3055 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3056 } 3057 3058 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3059 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3060 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3061 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3062 BGE_IS_57765_PLUS(sc)) { 3063 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3064 /* 3065 * Adjust tx margin to prevent TX data corruption and 3066 * fix internal FIFO overflow. 3067 */ 3068 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3069 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3070 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3071 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3072 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3073 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3074 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3075 } 3076 /* 3077 * Enable fix for read DMA FIFO overruns. 3078 * The fix is to limit the number of RX BDs 3079 * the hardware would fetch at a fime. 3080 */ 3081 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3082 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3083 } 3084 3085 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3086 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3087 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3088 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3089 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3090 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3091 /* 3092 * Allow 4KB burst length reads for non-LSO frames. 3093 * Enable 512B burst length reads for buffer descriptors. 3094 */ 3095 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3096 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3097 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3098 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3099 } 3100 3101 /* Turn on read DMA state machine */ 3102 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3103 /* 5718 step 52 */ 3104 delay(40); 3105 3106 /* 5718 step 56, 57XX step 84 */ 3107 /* Turn on RX data completion state machine */ 3108 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3109 3110 /* Turn on RX data and RX BD initiator state machine */ 3111 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3112 3113 /* 57XX step 85 */ 3114 /* Turn on Mbuf cluster free state machine */ 3115 if (!BGE_IS_5705_PLUS(sc)) 3116 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3117 3118 /* 5718 step 57, 57XX step 86 */ 3119 /* Turn on send data completion state machine */ 3120 val = BGE_SDCMODE_ENABLE; 3121 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3122 val |= BGE_SDCMODE_CDELAY; 3123 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3124 3125 /* 5718 step 58 */ 3126 /* Turn on send BD completion state machine */ 3127 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3128 3129 /* 57XX step 88 */ 3130 /* Turn on RX BD initiator state machine */ 3131 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3132 3133 /* 5718 step 60, 57XX step 90 */ 3134 /* Turn on send data initiator state machine */ 3135 if (sc->bge_flags & BGEF_TSO) { 3136 /* XXX: magic value from Linux driver */ 3137 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3138 BGE_SDIMODE_HW_LSO_PRE_DMA); 3139 } else 3140 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3141 3142 /* 5718 step 61, 57XX step 91 */ 3143 /* Turn on send BD initiator state machine */ 3144 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3145 3146 /* 5718 step 62, 57XX step 92 */ 3147 /* Turn on send BD selector state machine */ 3148 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3149 3150 /* 5718 step 31, 57XX step 60 */ 3151 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3152 /* 5718 step 32, 57XX step 61 */ 3153 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3154 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3155 3156 /* ack/clear link change events */ 3157 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3158 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3159 BGE_MACSTAT_LINK_CHANGED); 3160 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3161 3162 /* 3163 * Enable attention when the link has changed state for 3164 * devices that use auto polling. 3165 */ 3166 if (sc->bge_flags & BGEF_FIBER_TBI) { 3167 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3168 } else { 3169 /* 5718 step 68 */ 3170 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3171 /* 5718 step 69 (optionally) */ 3172 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 3173 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3174 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3175 BGE_EVTENB_MI_INTERRUPT); 3176 } 3177 3178 /* 3179 * Clear any pending link state attention. 3180 * Otherwise some link state change events may be lost until attention 3181 * is cleared by bge_intr() -> bge_link_upd() sequence. 3182 * It's not necessary on newer BCM chips - perhaps enabling link 3183 * state change attentions implies clearing pending attention. 3184 */ 3185 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3186 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3187 BGE_MACSTAT_LINK_CHANGED); 3188 3189 /* Enable link state change attentions. */ 3190 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3191 3192 return 0; 3193 } 3194 3195 static const struct bge_revision * 3196 bge_lookup_rev(uint32_t chipid) 3197 { 3198 const struct bge_revision *br; 3199 3200 for (br = bge_revisions; br->br_name != NULL; br++) { 3201 if (br->br_chipid == chipid) 3202 return br; 3203 } 3204 3205 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3206 if (br->br_chipid == BGE_ASICREV(chipid)) 3207 return br; 3208 } 3209 3210 return NULL; 3211 } 3212 3213 static const struct bge_product * 3214 bge_lookup(const struct pci_attach_args *pa) 3215 { 3216 const struct bge_product *bp; 3217 3218 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3219 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3220 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3221 return bp; 3222 } 3223 3224 return NULL; 3225 } 3226 3227 static uint32_t 3228 bge_chipid(const struct pci_attach_args *pa) 3229 { 3230 uint32_t id; 3231 3232 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3233 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3234 3235 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3236 switch (PCI_PRODUCT(pa->pa_id)) { 3237 case PCI_PRODUCT_BROADCOM_BCM5717: 3238 case PCI_PRODUCT_BROADCOM_BCM5718: 3239 case PCI_PRODUCT_BROADCOM_BCM5719: 3240 case PCI_PRODUCT_BROADCOM_BCM5720: 3241 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3242 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3243 BGE_PCI_GEN2_PRODID_ASICREV); 3244 break; 3245 case PCI_PRODUCT_BROADCOM_BCM57761: 3246 case PCI_PRODUCT_BROADCOM_BCM57762: 3247 case PCI_PRODUCT_BROADCOM_BCM57765: 3248 case PCI_PRODUCT_BROADCOM_BCM57766: 3249 case PCI_PRODUCT_BROADCOM_BCM57781: 3250 case PCI_PRODUCT_BROADCOM_BCM57785: 3251 case PCI_PRODUCT_BROADCOM_BCM57791: 3252 case PCI_PRODUCT_BROADCOM_BCM57795: 3253 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3254 BGE_PCI_GEN15_PRODID_ASICREV); 3255 break; 3256 default: 3257 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3258 BGE_PCI_PRODID_ASICREV); 3259 break; 3260 } 3261 } 3262 3263 return id; 3264 } 3265 3266 /* 3267 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3268 * against our list and return its name if we find a match. Note 3269 * that since the Broadcom controller contains VPD support, we 3270 * can get the device name string from the controller itself instead 3271 * of the compiled-in string. This is a little slow, but it guarantees 3272 * we'll always announce the right product name. 3273 */ 3274 static int 3275 bge_probe(device_t parent, cfdata_t match, void *aux) 3276 { 3277 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3278 3279 if (bge_lookup(pa) != NULL) 3280 return 1; 3281 3282 return 0; 3283 } 3284 3285 static void 3286 bge_attach(device_t parent, device_t self, void *aux) 3287 { 3288 struct bge_softc *sc = device_private(self); 3289 struct pci_attach_args *pa = aux; 3290 prop_dictionary_t dict; 3291 const struct bge_product *bp; 3292 const struct bge_revision *br; 3293 pci_chipset_tag_t pc; 3294 pci_intr_handle_t ih; 3295 const char *intrstr = NULL; 3296 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4; 3297 uint32_t command; 3298 struct ifnet *ifp; 3299 uint32_t misccfg, mimode; 3300 void * kva; 3301 u_char eaddr[ETHER_ADDR_LEN]; 3302 pcireg_t memtype, subid, reg; 3303 bus_addr_t memaddr; 3304 uint32_t pm_ctl; 3305 bool no_seeprom; 3306 int capmask; 3307 3308 bp = bge_lookup(pa); 3309 KASSERT(bp != NULL); 3310 3311 sc->sc_pc = pa->pa_pc; 3312 sc->sc_pcitag = pa->pa_tag; 3313 sc->bge_dev = self; 3314 3315 sc->bge_pa = *pa; 3316 pc = sc->sc_pc; 3317 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3318 3319 aprint_naive(": Ethernet controller\n"); 3320 aprint_normal(": %s\n", bp->bp_name); 3321 3322 /* 3323 * Map control/status registers. 3324 */ 3325 DPRINTFN(5, ("Map control/status regs\n")); 3326 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3327 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3328 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3329 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3330 3331 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3332 aprint_error_dev(sc->bge_dev, 3333 "failed to enable memory mapping!\n"); 3334 return; 3335 } 3336 3337 DPRINTFN(5, ("pci_mem_find\n")); 3338 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3339 switch (memtype) { 3340 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3341 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3342 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3343 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3344 &memaddr, &sc->bge_bsize) == 0) 3345 break; 3346 default: 3347 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3348 return; 3349 } 3350 3351 DPRINTFN(5, ("pci_intr_map\n")); 3352 if (pci_intr_map(pa, &ih)) { 3353 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3354 return; 3355 } 3356 3357 DPRINTFN(5, ("pci_intr_string\n")); 3358 intrstr = pci_intr_string(pc, ih); 3359 3360 DPRINTFN(5, ("pci_intr_establish\n")); 3361 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3362 3363 if (sc->bge_intrhand == NULL) { 3364 aprint_error_dev(sc->bge_dev, 3365 "couldn't establish interrupt%s%s\n", 3366 intrstr ? " at " : "", intrstr ? intrstr : ""); 3367 return; 3368 } 3369 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3370 3371 /* Save various chip information. */ 3372 sc->bge_chipid = bge_chipid(pa); 3373 sc->bge_phy_addr = bge_phy_addr(sc); 3374 3375 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3376 &sc->bge_pciecap, NULL) != 0) 3377 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3378 /* PCIe */ 3379 sc->bge_flags |= BGEF_PCIE; 3380 /* Extract supported maximum payload size. */ 3381 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3382 sc->bge_pciecap + PCIE_DCAP); 3383 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3384 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3385 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3386 sc->bge_expmrq = 2048; 3387 else 3388 sc->bge_expmrq = 4096; 3389 bge_set_max_readrq(sc); 3390 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3391 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3392 /* PCI-X */ 3393 sc->bge_flags |= BGEF_PCIX; 3394 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3395 &sc->bge_pcixcap, NULL) == 0) 3396 aprint_error_dev(sc->bge_dev, 3397 "unable to find PCIX capability\n"); 3398 } 3399 3400 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3401 /* 3402 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3403 * can clobber the chip's PCI config-space power control 3404 * registers, leaving the card in D3 powersave state. We do 3405 * not have memory-mapped registers in this state, so force 3406 * device into D0 state before starting initialization. 3407 */ 3408 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3409 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3410 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3411 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3412 DELAY(1000); /* 27 usec is allegedly sufficent */ 3413 } 3414 3415 /* Save chipset family. */ 3416 switch (BGE_ASICREV(sc->bge_chipid)) { 3417 case BGE_ASICREV_BCM5717: 3418 case BGE_ASICREV_BCM5719: 3419 case BGE_ASICREV_BCM5720: 3420 sc->bge_flags |= BGEF_5717_PLUS; 3421 /* FALLTHROUGH */ 3422 case BGE_ASICREV_BCM57765: 3423 case BGE_ASICREV_BCM57766: 3424 if (!BGE_IS_5717_PLUS(sc)) 3425 sc->bge_flags |= BGEF_57765_FAMILY; 3426 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3427 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3428 /* Jumbo frame on BCM5719 A0 does not work. */ 3429 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3430 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3431 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3432 break; 3433 case BGE_ASICREV_BCM5755: 3434 case BGE_ASICREV_BCM5761: 3435 case BGE_ASICREV_BCM5784: 3436 case BGE_ASICREV_BCM5785: 3437 case BGE_ASICREV_BCM5787: 3438 case BGE_ASICREV_BCM57780: 3439 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3440 break; 3441 case BGE_ASICREV_BCM5700: 3442 case BGE_ASICREV_BCM5701: 3443 case BGE_ASICREV_BCM5703: 3444 case BGE_ASICREV_BCM5704: 3445 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3446 break; 3447 case BGE_ASICREV_BCM5714_A0: 3448 case BGE_ASICREV_BCM5780: 3449 case BGE_ASICREV_BCM5714: 3450 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3451 /* FALLTHROUGH */ 3452 case BGE_ASICREV_BCM5750: 3453 case BGE_ASICREV_BCM5752: 3454 case BGE_ASICREV_BCM5906: 3455 sc->bge_flags |= BGEF_575X_PLUS; 3456 /* FALLTHROUGH */ 3457 case BGE_ASICREV_BCM5705: 3458 sc->bge_flags |= BGEF_5705_PLUS; 3459 break; 3460 } 3461 3462 /* Identify chips with APE processor. */ 3463 switch (BGE_ASICREV(sc->bge_chipid)) { 3464 case BGE_ASICREV_BCM5717: 3465 case BGE_ASICREV_BCM5719: 3466 case BGE_ASICREV_BCM5720: 3467 case BGE_ASICREV_BCM5761: 3468 sc->bge_flags |= BGEF_APE; 3469 break; 3470 } 3471 3472 /* Chips with APE need BAR2 access for APE registers/memory. */ 3473 if ((sc->bge_flags & BGEF_APE) != 0) { 3474 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3475 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3476 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3477 &sc->bge_apesize)) { 3478 aprint_error_dev(sc->bge_dev, 3479 "couldn't map BAR2 memory\n"); 3480 return; 3481 } 3482 3483 /* Enable APE register/memory access by host driver. */ 3484 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3485 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3486 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3487 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3488 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3489 3490 bge_ape_lock_init(sc); 3491 bge_ape_read_fw_ver(sc); 3492 } 3493 3494 /* Identify the chips that use an CPMU. */ 3495 if (BGE_IS_5717_PLUS(sc) || 3496 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3497 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3498 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3499 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3500 sc->bge_flags |= BGEF_CPMU_PRESENT; 3501 3502 /* Set MI_MODE */ 3503 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3504 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3505 mimode |= BGE_MIMODE_500KHZ_CONST; 3506 else 3507 mimode |= BGE_MIMODE_BASE; 3508 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3509 3510 /* 3511 * When using the BCM5701 in PCI-X mode, data corruption has 3512 * been observed in the first few bytes of some received packets. 3513 * Aligning the packet buffer in memory eliminates the corruption. 3514 * Unfortunately, this misaligns the packet payloads. On platforms 3515 * which do not support unaligned accesses, we will realign the 3516 * payloads by copying the received packets. 3517 */ 3518 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3519 sc->bge_flags & BGEF_PCIX) 3520 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3521 3522 if (BGE_IS_5700_FAMILY(sc)) 3523 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3524 3525 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3526 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3527 3528 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3529 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3530 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3531 sc->bge_flags |= BGEF_IS_5788; 3532 3533 /* 3534 * Some controllers seem to require a special firmware to use 3535 * TSO. But the firmware is not available to FreeBSD and Linux 3536 * claims that the TSO performed by the firmware is slower than 3537 * hardware based TSO. Moreover the firmware based TSO has one 3538 * known bug which can't handle TSO if ethernet header + IP/TCP 3539 * header is greater than 80 bytes. The workaround for the TSO 3540 * bug exist but it seems it's too expensive than not using 3541 * TSO at all. Some hardwares also have the TSO bug so limit 3542 * the TSO to the controllers that are not affected TSO issues 3543 * (e.g. 5755 or higher). 3544 */ 3545 if (BGE_IS_5755_PLUS(sc)) { 3546 /* 3547 * BCM5754 and BCM5787 shares the same ASIC id so 3548 * explicit device id check is required. 3549 */ 3550 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3551 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3552 sc->bge_flags |= BGEF_TSO; 3553 } 3554 3555 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3556 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3557 (misccfg == 0x4000 || misccfg == 0x8000)) || 3558 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3559 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3560 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3561 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3562 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3563 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3564 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3565 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3566 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3567 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3568 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3569 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3570 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3571 capmask &= ~BMSR_EXTSTAT; 3572 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3573 } 3574 3575 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3576 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3577 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3578 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3579 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3580 3581 /* Set various PHY bug flags. */ 3582 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3583 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3584 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3585 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3586 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3587 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3588 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3589 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3590 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3591 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3592 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3593 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3594 if (BGE_IS_5705_PLUS(sc) && 3595 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3596 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3597 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3598 !BGE_IS_57765_PLUS(sc)) { 3599 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3600 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3601 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3602 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3603 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3604 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3605 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3606 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3607 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3608 } else 3609 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3610 } 3611 3612 /* 3613 * SEEPROM check. 3614 * First check if firmware knows we do not have SEEPROM. 3615 */ 3616 if (prop_dictionary_get_bool(device_properties(self), 3617 "without-seeprom", &no_seeprom) && no_seeprom) 3618 sc->bge_flags |= BGEF_NO_EEPROM; 3619 3620 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3621 sc->bge_flags |= BGEF_NO_EEPROM; 3622 3623 /* Now check the 'ROM failed' bit on the RX CPU */ 3624 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3625 sc->bge_flags |= BGEF_NO_EEPROM; 3626 3627 sc->bge_asf_mode = 0; 3628 /* No ASF if APE present. */ 3629 if ((sc->bge_flags & BGEF_APE) == 0) { 3630 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3631 BGE_SRAM_DATA_SIG_MAGIC)) { 3632 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3633 BGE_HWCFG_ASF) { 3634 sc->bge_asf_mode |= ASF_ENABLE; 3635 sc->bge_asf_mode |= ASF_STACKUP; 3636 if (BGE_IS_575X_PLUS(sc)) 3637 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3638 } 3639 } 3640 } 3641 3642 /* 3643 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3644 * lock in bge_reset(). 3645 */ 3646 CSR_WRITE_4(sc, BGE_EE_ADDR, 3647 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3648 delay(1000); 3649 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3650 3651 bge_stop_fw(sc); 3652 bge_sig_pre_reset(sc, BGE_RESET_START); 3653 if (bge_reset(sc)) 3654 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3655 3656 /* 3657 * Read the hardware config word in the first 32k of NIC internal 3658 * memory, or fall back to the config word in the EEPROM. 3659 * Note: on some BCM5700 cards, this value appears to be unset. 3660 */ 3661 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = 0; 3662 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3663 BGE_SRAM_DATA_SIG_MAGIC) { 3664 uint32_t tmp; 3665 3666 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3667 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3668 BGE_SRAM_DATA_VER_SHIFT; 3669 if ((0 < tmp) && (tmp < 0x100)) 3670 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3671 if (sc->bge_flags & BGEF_PCIE) 3672 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3673 if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) 3674 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3675 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3676 bge_read_eeprom(sc, (void *)&hwcfg, 3677 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3678 hwcfg = be32toh(hwcfg); 3679 } 3680 aprint_normal_dev(sc->bge_dev, "HW config %08x, %08x, %08x, %08x\n", 3681 hwcfg, hwcfg2, hwcfg3, hwcfg4); 3682 3683 bge_sig_legacy(sc, BGE_RESET_START); 3684 bge_sig_post_reset(sc, BGE_RESET_START); 3685 3686 if (bge_chipinit(sc)) { 3687 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3688 bge_release_resources(sc); 3689 return; 3690 } 3691 3692 /* 3693 * Get station address from the EEPROM. 3694 */ 3695 if (bge_get_eaddr(sc, eaddr)) { 3696 aprint_error_dev(sc->bge_dev, 3697 "failed to read station address\n"); 3698 bge_release_resources(sc); 3699 return; 3700 } 3701 3702 br = bge_lookup_rev(sc->bge_chipid); 3703 3704 if (br == NULL) { 3705 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3706 sc->bge_chipid); 3707 } else { 3708 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3709 br->br_name, sc->bge_chipid); 3710 } 3711 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3712 3713 /* Allocate the general information block and ring buffers. */ 3714 if (pci_dma64_available(pa)) 3715 sc->bge_dmatag = pa->pa_dmat64; 3716 else 3717 sc->bge_dmatag = pa->pa_dmat; 3718 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3719 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3720 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3721 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3722 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3723 return; 3724 } 3725 DPRINTFN(5, ("bus_dmamem_map\n")); 3726 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3727 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3728 BUS_DMA_NOWAIT)) { 3729 aprint_error_dev(sc->bge_dev, 3730 "can't map DMA buffers (%zu bytes)\n", 3731 sizeof(struct bge_ring_data)); 3732 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3733 sc->bge_ring_rseg); 3734 return; 3735 } 3736 DPRINTFN(5, ("bus_dmamem_create\n")); 3737 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3738 sizeof(struct bge_ring_data), 0, 3739 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3740 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3741 bus_dmamem_unmap(sc->bge_dmatag, kva, 3742 sizeof(struct bge_ring_data)); 3743 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3744 sc->bge_ring_rseg); 3745 return; 3746 } 3747 DPRINTFN(5, ("bus_dmamem_load\n")); 3748 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3749 sizeof(struct bge_ring_data), NULL, 3750 BUS_DMA_NOWAIT)) { 3751 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3752 bus_dmamem_unmap(sc->bge_dmatag, kva, 3753 sizeof(struct bge_ring_data)); 3754 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3755 sc->bge_ring_rseg); 3756 return; 3757 } 3758 3759 DPRINTFN(5, ("bzero\n")); 3760 sc->bge_rdata = (struct bge_ring_data *)kva; 3761 3762 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3763 3764 /* Try to allocate memory for jumbo buffers. */ 3765 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3766 if (bge_alloc_jumbo_mem(sc)) { 3767 aprint_error_dev(sc->bge_dev, 3768 "jumbo buffer allocation failed\n"); 3769 } else 3770 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3771 } 3772 3773 /* Set default tuneable values. */ 3774 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3775 sc->bge_rx_coal_ticks = 150; 3776 sc->bge_rx_max_coal_bds = 64; 3777 sc->bge_tx_coal_ticks = 300; 3778 sc->bge_tx_max_coal_bds = 400; 3779 if (BGE_IS_5705_PLUS(sc)) { 3780 sc->bge_tx_coal_ticks = (12 * 5); 3781 sc->bge_tx_max_coal_bds = (12 * 5); 3782 aprint_verbose_dev(sc->bge_dev, 3783 "setting short Tx thresholds\n"); 3784 } 3785 3786 if (BGE_IS_5717_PLUS(sc)) 3787 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3788 else if (BGE_IS_5705_PLUS(sc)) 3789 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3790 else 3791 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3792 3793 /* Set up ifnet structure */ 3794 ifp = &sc->ethercom.ec_if; 3795 ifp->if_softc = sc; 3796 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3797 ifp->if_ioctl = bge_ioctl; 3798 ifp->if_stop = bge_stop; 3799 ifp->if_start = bge_start; 3800 ifp->if_init = bge_init; 3801 ifp->if_watchdog = bge_watchdog; 3802 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3803 IFQ_SET_READY(&ifp->if_snd); 3804 DPRINTFN(5, ("strcpy if_xname\n")); 3805 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3806 3807 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3808 sc->ethercom.ec_if.if_capabilities |= 3809 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3810 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3811 sc->ethercom.ec_if.if_capabilities |= 3812 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3813 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3814 #endif 3815 sc->ethercom.ec_capabilities |= 3816 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3817 3818 if (sc->bge_flags & BGEF_TSO) 3819 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3820 3821 /* 3822 * Do MII setup. 3823 */ 3824 DPRINTFN(5, ("mii setup\n")); 3825 sc->bge_mii.mii_ifp = ifp; 3826 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3827 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3828 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3829 3830 /* 3831 * Figure out what sort of media we have by checking the hardware 3832 * config word. Note: on some BCM5700 cards, this value appears to be 3833 * unset. If that's the case, we have to rely on identifying the NIC 3834 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3835 * The SysKonnect SK-9D41 is a 1000baseSX card. 3836 */ 3837 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3838 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3839 if (BGE_IS_5714_FAMILY(sc)) 3840 sc->bge_flags |= BGEF_FIBER_MII; 3841 else 3842 sc->bge_flags |= BGEF_FIBER_TBI; 3843 } 3844 3845 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3846 if (BGE_IS_JUMBO_CAPABLE(sc)) 3847 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3848 3849 /* set phyflags and chipid before mii_attach() */ 3850 dict = device_properties(self); 3851 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3852 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3853 3854 if (sc->bge_flags & BGEF_FIBER_TBI) { 3855 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3856 bge_ifmedia_sts); 3857 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3858 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3859 0, NULL); 3860 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3861 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3862 /* Pretend the user requested this setting */ 3863 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3864 } else { 3865 /* 3866 * Do transceiver setup and tell the firmware the 3867 * driver is down so we can try to get access the 3868 * probe if ASF is running. Retry a couple of times 3869 * if we get a conflict with the ASF firmware accessing 3870 * the PHY. 3871 */ 3872 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3873 bge_asf_driver_up(sc); 3874 3875 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3876 bge_ifmedia_sts); 3877 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, 3878 sc->bge_phy_addr, MII_OFFSET_ANY, 3879 MIIF_DOPAUSE); 3880 3881 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3882 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3883 ifmedia_add(&sc->bge_mii.mii_media, 3884 IFM_ETHER|IFM_MANUAL, 0, NULL); 3885 ifmedia_set(&sc->bge_mii.mii_media, 3886 IFM_ETHER|IFM_MANUAL); 3887 } else 3888 ifmedia_set(&sc->bge_mii.mii_media, 3889 IFM_ETHER|IFM_AUTO); 3890 3891 /* 3892 * Now tell the firmware we are going up after probing the PHY 3893 */ 3894 if (sc->bge_asf_mode & ASF_STACKUP) 3895 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3896 } 3897 3898 /* 3899 * Call MI attach routine. 3900 */ 3901 DPRINTFN(5, ("if_attach\n")); 3902 if_attach(ifp); 3903 DPRINTFN(5, ("ether_ifattach\n")); 3904 ether_ifattach(ifp, eaddr); 3905 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3906 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3907 RND_TYPE_NET, 0); 3908 #ifdef BGE_EVENT_COUNTERS 3909 /* 3910 * Attach event counters. 3911 */ 3912 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3913 NULL, device_xname(sc->bge_dev), "intr"); 3914 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3915 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3916 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3917 NULL, device_xname(sc->bge_dev), "tx_xon"); 3918 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3919 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3920 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3921 NULL, device_xname(sc->bge_dev), "rx_xon"); 3922 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3923 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3924 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3925 NULL, device_xname(sc->bge_dev), "xoffentered"); 3926 #endif /* BGE_EVENT_COUNTERS */ 3927 DPRINTFN(5, ("callout_init\n")); 3928 callout_init(&sc->bge_timeout, 0); 3929 3930 if (pmf_device_register(self, NULL, NULL)) 3931 pmf_class_network_register(self, ifp); 3932 else 3933 aprint_error_dev(self, "couldn't establish power handler\n"); 3934 3935 bge_sysctl_init(sc); 3936 3937 #ifdef BGE_DEBUG 3938 bge_debug_info(sc); 3939 #endif 3940 } 3941 3942 /* 3943 * Stop all chip I/O so that the kernel's probe routines don't 3944 * get confused by errant DMAs when rebooting. 3945 */ 3946 static int 3947 bge_detach(device_t self, int flags __unused) 3948 { 3949 struct bge_softc *sc = device_private(self); 3950 struct ifnet *ifp = &sc->ethercom.ec_if; 3951 int s; 3952 3953 s = splnet(); 3954 /* Stop the interface. Callouts are stopped in it. */ 3955 bge_stop(ifp, 1); 3956 splx(s); 3957 3958 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3959 3960 /* Delete all remaining media. */ 3961 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3962 3963 ether_ifdetach(ifp); 3964 if_detach(ifp); 3965 3966 bge_release_resources(sc); 3967 3968 return 0; 3969 } 3970 3971 static void 3972 bge_release_resources(struct bge_softc *sc) 3973 { 3974 3975 /* Disestablish the interrupt handler */ 3976 if (sc->bge_intrhand != NULL) { 3977 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3978 sc->bge_intrhand = NULL; 3979 } 3980 3981 if (sc->bge_dmatag != NULL) { 3982 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3983 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3984 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3985 sizeof(struct bge_ring_data)); 3986 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 3987 } 3988 3989 /* Unmap the device registers */ 3990 if (sc->bge_bsize != 0) { 3991 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3992 sc->bge_bsize = 0; 3993 } 3994 3995 /* Unmap the APE registers */ 3996 if (sc->bge_apesize != 0) { 3997 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3998 sc->bge_apesize); 3999 sc->bge_apesize = 0; 4000 } 4001 } 4002 4003 static int 4004 bge_reset(struct bge_softc *sc) 4005 { 4006 uint32_t cachesize, command; 4007 uint32_t reset, mac_mode, mac_mode_mask; 4008 pcireg_t devctl, reg; 4009 int i, val; 4010 void (*write_op)(struct bge_softc *, int, int); 4011 4012 /* Make mask for BGE_MAC_MODE register. */ 4013 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4014 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4015 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4016 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4017 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4018 4019 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4020 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4021 if (sc->bge_flags & BGEF_PCIE) 4022 write_op = bge_writemem_direct; 4023 else 4024 write_op = bge_writemem_ind; 4025 } else 4026 write_op = bge_writereg_ind; 4027 4028 /* 57XX step 4 */ 4029 /* Acquire the NVM lock */ 4030 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4031 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4032 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4033 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4034 for (i = 0; i < 8000; i++) { 4035 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4036 BGE_NVRAMSWARB_GNT1) 4037 break; 4038 DELAY(20); 4039 } 4040 if (i == 8000) { 4041 printf("%s: NVRAM lock timedout!\n", 4042 device_xname(sc->bge_dev)); 4043 } 4044 } 4045 4046 /* Take APE lock when performing reset. */ 4047 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4048 4049 /* 57XX step 3 */ 4050 /* Save some important PCI state. */ 4051 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4052 /* 5718 reset step 3 */ 4053 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4054 4055 /* 5718 reset step 5, 57XX step 5b-5d */ 4056 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4057 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4058 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4059 4060 /* XXX ???: Disable fastboot on controllers that support it. */ 4061 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4062 BGE_IS_5755_PLUS(sc)) 4063 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4064 4065 /* 5718 reset step 2, 57XX step 6 */ 4066 /* 4067 * Write the magic number to SRAM at offset 0xB50. 4068 * When firmware finishes its initialization it will 4069 * write ~BGE_MAGIC_NUMBER to the same location. 4070 */ 4071 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4072 4073 /* 5718 reset step 6, 57XX step 7 */ 4074 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4075 /* 4076 * XXX: from FreeBSD/Linux; no documentation 4077 */ 4078 if (sc->bge_flags & BGEF_PCIE) { 4079 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 4080 !BGE_IS_57765_PLUS(sc) && 4081 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4082 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4083 /* PCI Express 1.0 system */ 4084 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4085 BGE_PHY_PCIE_SCRAM_MODE); 4086 } 4087 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4088 /* 4089 * Prevent PCI Express link training 4090 * during global reset. 4091 */ 4092 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4093 reset |= (1 << 29); 4094 } 4095 } 4096 4097 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4098 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4099 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4100 i | BGE_VCPU_STATUS_DRV_RESET); 4101 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4102 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4103 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4104 } 4105 4106 /* 4107 * Set GPHY Power Down Override to leave GPHY 4108 * powered up in D0 uninitialized. 4109 */ 4110 if (BGE_IS_5705_PLUS(sc) && 4111 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4112 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4113 4114 /* Issue global reset */ 4115 write_op(sc, BGE_MISC_CFG, reset); 4116 4117 /* 5718 reset step 7, 57XX step 8 */ 4118 if (sc->bge_flags & BGEF_PCIE) 4119 delay(100*1000); /* too big */ 4120 else 4121 delay(1000); 4122 4123 if (sc->bge_flags & BGEF_PCIE) { 4124 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4125 DELAY(500000); 4126 /* XXX: Magic Numbers */ 4127 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4128 BGE_PCI_UNKNOWN0); 4129 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4130 BGE_PCI_UNKNOWN0, 4131 reg | (1 << 15)); 4132 } 4133 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4134 sc->bge_pciecap + PCIE_DCSR); 4135 /* Clear enable no snoop and disable relaxed ordering. */ 4136 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4137 PCIE_DCSR_ENA_NO_SNOOP); 4138 4139 /* Set PCIE max payload size to 128 for older PCIe devices */ 4140 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4141 devctl &= ~(0x00e0); 4142 /* Clear device status register. Write 1b to clear */ 4143 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4144 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4145 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4146 sc->bge_pciecap + PCIE_DCSR, devctl); 4147 bge_set_max_readrq(sc); 4148 } 4149 4150 /* From Linux: dummy read to flush PCI posted writes */ 4151 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4152 4153 /* 4154 * Reset some of the PCI state that got zapped by reset 4155 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4156 * set, too. 4157 */ 4158 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4159 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4160 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4161 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4162 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4163 (sc->bge_flags & BGEF_PCIX) != 0) 4164 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4165 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4166 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4167 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4168 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4169 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4170 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4171 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4172 4173 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4174 if (sc->bge_flags & BGEF_PCIX) { 4175 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4176 + PCIX_CMD); 4177 /* Set max memory read byte count to 2K */ 4178 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4179 reg &= ~PCIX_CMD_BYTECNT_MASK; 4180 reg |= PCIX_CMD_BCNT_2048; 4181 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4182 /* 4183 * For 5704, set max outstanding split transaction 4184 * field to 0 (0 means it supports 1 request) 4185 */ 4186 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4187 | PCIX_CMD_BYTECNT_MASK); 4188 reg |= PCIX_CMD_BCNT_2048; 4189 } 4190 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4191 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4192 } 4193 4194 /* 5718 reset step 10, 57XX step 12 */ 4195 /* Enable memory arbiter. */ 4196 if (BGE_IS_5714_FAMILY(sc)) { 4197 val = CSR_READ_4(sc, BGE_MARB_MODE); 4198 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4199 } else 4200 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4201 4202 /* XXX 5721, 5751 and 5752 */ 4203 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4204 /* Step 19: */ 4205 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4206 /* Step 20: */ 4207 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4208 } 4209 4210 /* 5718 reset step 13, 57XX step 17 */ 4211 /* Poll until the firmware initialization is complete */ 4212 bge_poll_fw(sc); 4213 4214 /* 5718 reset step 12, 57XX step 15 and 16 */ 4215 /* Fix up byte swapping */ 4216 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4217 4218 /* 57XX step 21 */ 4219 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4220 pcireg_t msidata; 4221 4222 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4223 BGE_PCI_MSI_DATA); 4224 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4225 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4226 msidata); 4227 } 4228 4229 /* 57XX step 18 */ 4230 /* Write mac mode. */ 4231 val = CSR_READ_4(sc, BGE_MAC_MODE); 4232 /* Restore mac_mode_mask's bits using mac_mode */ 4233 val = (val & ~mac_mode_mask) | mac_mode; 4234 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4235 DELAY(40); 4236 4237 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4238 4239 /* 4240 * The 5704 in TBI mode apparently needs some special 4241 * adjustment to insure the SERDES drive level is set 4242 * to 1.2V. 4243 */ 4244 if (sc->bge_flags & BGEF_FIBER_TBI && 4245 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4246 uint32_t serdescfg; 4247 4248 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4249 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4250 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4251 } 4252 4253 if (sc->bge_flags & BGEF_PCIE && 4254 !BGE_IS_57765_PLUS(sc) && 4255 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4256 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4257 uint32_t v; 4258 4259 /* Enable PCI Express bug fix */ 4260 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4261 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4262 v | BGE_TLP_DATA_FIFO_PROTECT); 4263 } 4264 4265 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4266 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4267 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4268 4269 return 0; 4270 } 4271 4272 /* 4273 * Frame reception handling. This is called if there's a frame 4274 * on the receive return list. 4275 * 4276 * Note: we have to be able to handle two possibilities here: 4277 * 1) the frame is from the jumbo receive ring 4278 * 2) the frame is from the standard receive ring 4279 */ 4280 4281 static void 4282 bge_rxeof(struct bge_softc *sc) 4283 { 4284 struct ifnet *ifp; 4285 uint16_t rx_prod, rx_cons; 4286 int stdcnt = 0, jumbocnt = 0; 4287 bus_dmamap_t dmamap; 4288 bus_addr_t offset, toff; 4289 bus_size_t tlen; 4290 int tosync; 4291 4292 rx_cons = sc->bge_rx_saved_considx; 4293 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4294 4295 /* Nothing to do */ 4296 if (rx_cons == rx_prod) 4297 return; 4298 4299 ifp = &sc->ethercom.ec_if; 4300 4301 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4302 offsetof(struct bge_ring_data, bge_status_block), 4303 sizeof (struct bge_status_block), 4304 BUS_DMASYNC_POSTREAD); 4305 4306 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4307 tosync = rx_prod - rx_cons; 4308 4309 if (tosync != 0) 4310 rnd_add_uint32(&sc->rnd_source, tosync); 4311 4312 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4313 4314 if (tosync < 0) { 4315 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4316 sizeof (struct bge_rx_bd); 4317 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4318 toff, tlen, BUS_DMASYNC_POSTREAD); 4319 tosync = -tosync; 4320 } 4321 4322 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4323 offset, tosync * sizeof (struct bge_rx_bd), 4324 BUS_DMASYNC_POSTREAD); 4325 4326 while (rx_cons != rx_prod) { 4327 struct bge_rx_bd *cur_rx; 4328 uint32_t rxidx; 4329 struct mbuf *m = NULL; 4330 4331 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4332 4333 rxidx = cur_rx->bge_idx; 4334 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4335 4336 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4337 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4338 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4339 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4340 jumbocnt++; 4341 bus_dmamap_sync(sc->bge_dmatag, 4342 sc->bge_cdata.bge_rx_jumbo_map, 4343 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4344 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4345 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4346 ifp->if_ierrors++; 4347 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4348 continue; 4349 } 4350 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4351 NULL)== ENOBUFS) { 4352 ifp->if_ierrors++; 4353 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4354 continue; 4355 } 4356 } else { 4357 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4358 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4359 4360 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4361 stdcnt++; 4362 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4363 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4364 if (dmamap == NULL) { 4365 ifp->if_ierrors++; 4366 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4367 continue; 4368 } 4369 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4370 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4371 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4372 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4373 ifp->if_ierrors++; 4374 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4375 continue; 4376 } 4377 if (bge_newbuf_std(sc, sc->bge_std, 4378 NULL, dmamap) == ENOBUFS) { 4379 ifp->if_ierrors++; 4380 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4381 continue; 4382 } 4383 } 4384 4385 ifp->if_ipackets++; 4386 #ifndef __NO_STRICT_ALIGNMENT 4387 /* 4388 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4389 * the Rx buffer has the layer-2 header unaligned. 4390 * If our CPU requires alignment, re-align by copying. 4391 */ 4392 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4393 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4394 cur_rx->bge_len); 4395 m->m_data += ETHER_ALIGN; 4396 } 4397 #endif 4398 4399 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4400 m->m_pkthdr.rcvif = ifp; 4401 4402 /* 4403 * Handle BPF listeners. Let the BPF user see the packet. 4404 */ 4405 bpf_mtap(ifp, m); 4406 4407 bge_rxcsum(sc, cur_rx, m); 4408 4409 /* 4410 * If we received a packet with a vlan tag, pass it 4411 * to vlan_input() instead of ether_input(). 4412 */ 4413 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4414 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4415 } 4416 4417 (*ifp->if_input)(ifp, m); 4418 } 4419 4420 sc->bge_rx_saved_considx = rx_cons; 4421 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4422 if (stdcnt) 4423 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4424 if (jumbocnt) 4425 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4426 } 4427 4428 static void 4429 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4430 { 4431 4432 if (BGE_IS_57765_PLUS(sc)) { 4433 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4434 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4435 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4436 if ((cur_rx->bge_error_flag & 4437 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4438 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4439 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4440 m->m_pkthdr.csum_data = 4441 cur_rx->bge_tcp_udp_csum; 4442 m->m_pkthdr.csum_flags |= 4443 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4444 M_CSUM_DATA); 4445 } 4446 } 4447 } else { 4448 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4449 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4450 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4451 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4452 /* 4453 * Rx transport checksum-offload may also 4454 * have bugs with packets which, when transmitted, 4455 * were `runts' requiring padding. 4456 */ 4457 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4458 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4459 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4460 m->m_pkthdr.csum_data = 4461 cur_rx->bge_tcp_udp_csum; 4462 m->m_pkthdr.csum_flags |= 4463 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4464 M_CSUM_DATA); 4465 } 4466 } 4467 } 4468 4469 static void 4470 bge_txeof(struct bge_softc *sc) 4471 { 4472 struct bge_tx_bd *cur_tx = NULL; 4473 struct ifnet *ifp; 4474 struct txdmamap_pool_entry *dma; 4475 bus_addr_t offset, toff; 4476 bus_size_t tlen; 4477 int tosync; 4478 struct mbuf *m; 4479 4480 ifp = &sc->ethercom.ec_if; 4481 4482 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4483 offsetof(struct bge_ring_data, bge_status_block), 4484 sizeof (struct bge_status_block), 4485 BUS_DMASYNC_POSTREAD); 4486 4487 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4488 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4489 sc->bge_tx_saved_considx; 4490 4491 if (tosync != 0) 4492 rnd_add_uint32(&sc->rnd_source, tosync); 4493 4494 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4495 4496 if (tosync < 0) { 4497 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4498 sizeof (struct bge_tx_bd); 4499 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4500 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4501 tosync = -tosync; 4502 } 4503 4504 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4505 offset, tosync * sizeof (struct bge_tx_bd), 4506 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4507 4508 /* 4509 * Go through our tx ring and free mbufs for those 4510 * frames that have been sent. 4511 */ 4512 while (sc->bge_tx_saved_considx != 4513 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4514 uint32_t idx = 0; 4515 4516 idx = sc->bge_tx_saved_considx; 4517 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4518 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4519 ifp->if_opackets++; 4520 m = sc->bge_cdata.bge_tx_chain[idx]; 4521 if (m != NULL) { 4522 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4523 dma = sc->txdma[idx]; 4524 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4525 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4526 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4527 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4528 sc->txdma[idx] = NULL; 4529 4530 m_freem(m); 4531 } 4532 sc->bge_txcnt--; 4533 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4534 ifp->if_timer = 0; 4535 } 4536 4537 if (cur_tx != NULL) 4538 ifp->if_flags &= ~IFF_OACTIVE; 4539 } 4540 4541 static int 4542 bge_intr(void *xsc) 4543 { 4544 struct bge_softc *sc; 4545 struct ifnet *ifp; 4546 uint32_t statusword; 4547 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4548 4549 sc = xsc; 4550 ifp = &sc->ethercom.ec_if; 4551 4552 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4553 if (BGE_IS_5717_PLUS(sc)) 4554 intrmask = 0; 4555 4556 /* It is possible for the interrupt to arrive before 4557 * the status block is updated prior to the interrupt. 4558 * Reading the PCI State register will confirm whether the 4559 * interrupt is ours and will flush the status block. 4560 */ 4561 4562 /* read status word from status block */ 4563 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4564 offsetof(struct bge_ring_data, bge_status_block), 4565 sizeof (struct bge_status_block), 4566 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4567 statusword = sc->bge_rdata->bge_status_block.bge_status; 4568 4569 if ((statusword & BGE_STATFLAG_UPDATED) || 4570 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) { 4571 /* Ack interrupt and stop others from occuring. */ 4572 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4573 4574 BGE_EVCNT_INCR(sc->bge_ev_intr); 4575 4576 /* clear status word */ 4577 sc->bge_rdata->bge_status_block.bge_status = 0; 4578 4579 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4580 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4581 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4582 bge_link_upd(sc); 4583 4584 if (ifp->if_flags & IFF_RUNNING) { 4585 /* Check RX return ring producer/consumer */ 4586 bge_rxeof(sc); 4587 4588 /* Check TX ring producer/consumer */ 4589 bge_txeof(sc); 4590 } 4591 4592 if (sc->bge_pending_rxintr_change) { 4593 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4594 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4595 4596 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4597 DELAY(10); 4598 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4599 4600 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4601 DELAY(10); 4602 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4603 4604 sc->bge_pending_rxintr_change = 0; 4605 } 4606 bge_handle_events(sc); 4607 4608 /* Re-enable interrupts. */ 4609 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4610 4611 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4612 bge_start(ifp); 4613 4614 return 1; 4615 } else 4616 return 0; 4617 } 4618 4619 static void 4620 bge_asf_driver_up(struct bge_softc *sc) 4621 { 4622 if (sc->bge_asf_mode & ASF_STACKUP) { 4623 /* Send ASF heartbeat aprox. every 2s */ 4624 if (sc->bge_asf_count) 4625 sc->bge_asf_count --; 4626 else { 4627 sc->bge_asf_count = 2; 4628 4629 bge_wait_for_event_ack(sc); 4630 4631 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4632 BGE_FW_CMD_DRV_ALIVE); 4633 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4634 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4635 BGE_FW_HB_TIMEOUT_SEC); 4636 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4637 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4638 BGE_RX_CPU_DRV_EVENT); 4639 } 4640 } 4641 } 4642 4643 static void 4644 bge_tick(void *xsc) 4645 { 4646 struct bge_softc *sc = xsc; 4647 struct mii_data *mii = &sc->bge_mii; 4648 int s; 4649 4650 s = splnet(); 4651 4652 if (BGE_IS_5705_PLUS(sc)) 4653 bge_stats_update_regs(sc); 4654 else 4655 bge_stats_update(sc); 4656 4657 if (sc->bge_flags & BGEF_FIBER_TBI) { 4658 /* 4659 * Since in TBI mode auto-polling can't be used we should poll 4660 * link status manually. Here we register pending link event 4661 * and trigger interrupt. 4662 */ 4663 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4664 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4665 } else { 4666 /* 4667 * Do not touch PHY if we have link up. This could break 4668 * IPMI/ASF mode or produce extra input errors. 4669 * (extra input errors was reported for bcm5701 & bcm5704). 4670 */ 4671 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4672 mii_tick(mii); 4673 } 4674 4675 bge_asf_driver_up(sc); 4676 4677 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4678 4679 splx(s); 4680 } 4681 4682 static void 4683 bge_stats_update_regs(struct bge_softc *sc) 4684 { 4685 struct ifnet *ifp = &sc->ethercom.ec_if; 4686 4687 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4688 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4689 4690 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4691 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4692 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4693 } 4694 4695 static void 4696 bge_stats_update(struct bge_softc *sc) 4697 { 4698 struct ifnet *ifp = &sc->ethercom.ec_if; 4699 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4700 4701 #define READ_STAT(sc, stats, stat) \ 4702 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4703 4704 ifp->if_collisions += 4705 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4706 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4707 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4708 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4709 ifp->if_collisions; 4710 4711 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4712 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4713 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4714 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4715 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4716 READ_STAT(sc, stats, 4717 xoffPauseFramesReceived.bge_addr_lo)); 4718 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4719 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4720 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4721 READ_STAT(sc, stats, 4722 macControlFramesReceived.bge_addr_lo)); 4723 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4724 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4725 4726 #undef READ_STAT 4727 4728 #ifdef notdef 4729 ifp->if_collisions += 4730 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4731 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4732 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4733 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4734 ifp->if_collisions; 4735 #endif 4736 } 4737 4738 /* 4739 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4740 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4741 * but when such padded frames employ the bge IP/TCP checksum offload, 4742 * the hardware checksum assist gives incorrect results (possibly 4743 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4744 * If we pad such runts with zeros, the onboard checksum comes out correct. 4745 */ 4746 static inline int 4747 bge_cksum_pad(struct mbuf *pkt) 4748 { 4749 struct mbuf *last = NULL; 4750 int padlen; 4751 4752 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4753 4754 /* if there's only the packet-header and we can pad there, use it. */ 4755 if (pkt->m_pkthdr.len == pkt->m_len && 4756 M_TRAILINGSPACE(pkt) >= padlen) { 4757 last = pkt; 4758 } else { 4759 /* 4760 * Walk packet chain to find last mbuf. We will either 4761 * pad there, or append a new mbuf and pad it 4762 * (thus perhaps avoiding the bcm5700 dma-min bug). 4763 */ 4764 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4765 continue; /* do nothing */ 4766 } 4767 4768 /* `last' now points to last in chain. */ 4769 if (M_TRAILINGSPACE(last) < padlen) { 4770 /* Allocate new empty mbuf, pad it. Compact later. */ 4771 struct mbuf *n; 4772 MGET(n, M_DONTWAIT, MT_DATA); 4773 if (n == NULL) 4774 return ENOBUFS; 4775 n->m_len = 0; 4776 last->m_next = n; 4777 last = n; 4778 } 4779 } 4780 4781 KDASSERT(!M_READONLY(last)); 4782 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4783 4784 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4785 memset(mtod(last, char *) + last->m_len, 0, padlen); 4786 last->m_len += padlen; 4787 pkt->m_pkthdr.len += padlen; 4788 return 0; 4789 } 4790 4791 /* 4792 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4793 */ 4794 static inline int 4795 bge_compact_dma_runt(struct mbuf *pkt) 4796 { 4797 struct mbuf *m, *prev; 4798 int totlen; 4799 4800 prev = NULL; 4801 totlen = 0; 4802 4803 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4804 int mlen = m->m_len; 4805 int shortfall = 8 - mlen ; 4806 4807 totlen += mlen; 4808 if (mlen == 0) 4809 continue; 4810 if (mlen >= 8) 4811 continue; 4812 4813 /* If we get here, mbuf data is too small for DMA engine. 4814 * Try to fix by shuffling data to prev or next in chain. 4815 * If that fails, do a compacting deep-copy of the whole chain. 4816 */ 4817 4818 /* Internal frag. If fits in prev, copy it there. */ 4819 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4820 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4821 prev->m_len += mlen; 4822 m->m_len = 0; 4823 /* XXX stitch chain */ 4824 prev->m_next = m_free(m); 4825 m = prev; 4826 continue; 4827 } 4828 else if (m->m_next != NULL && 4829 M_TRAILINGSPACE(m) >= shortfall && 4830 m->m_next->m_len >= (8 + shortfall)) { 4831 /* m is writable and have enough data in next, pull up. */ 4832 4833 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4834 shortfall); 4835 m->m_len += shortfall; 4836 m->m_next->m_len -= shortfall; 4837 m->m_next->m_data += shortfall; 4838 } 4839 else if (m->m_next == NULL || 1) { 4840 /* Got a runt at the very end of the packet. 4841 * borrow data from the tail of the preceding mbuf and 4842 * update its length in-place. (The original data is still 4843 * valid, so we can do this even if prev is not writable.) 4844 */ 4845 4846 /* if we'd make prev a runt, just move all of its data. */ 4847 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4848 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4849 4850 if ((prev->m_len - shortfall) < 8) 4851 shortfall = prev->m_len; 4852 4853 #ifdef notyet /* just do the safe slow thing for now */ 4854 if (!M_READONLY(m)) { 4855 if (M_LEADINGSPACE(m) < shorfall) { 4856 void *m_dat; 4857 m_dat = (m->m_flags & M_PKTHDR) ? 4858 m->m_pktdat : m->dat; 4859 memmove(m_dat, mtod(m, void*), m->m_len); 4860 m->m_data = m_dat; 4861 } 4862 } else 4863 #endif /* just do the safe slow thing */ 4864 { 4865 struct mbuf * n = NULL; 4866 int newprevlen = prev->m_len - shortfall; 4867 4868 MGET(n, M_NOWAIT, MT_DATA); 4869 if (n == NULL) 4870 return ENOBUFS; 4871 KASSERT(m->m_len + shortfall < MLEN 4872 /*, 4873 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4874 4875 /* first copy the data we're stealing from prev */ 4876 memcpy(n->m_data, prev->m_data + newprevlen, 4877 shortfall); 4878 4879 /* update prev->m_len accordingly */ 4880 prev->m_len -= shortfall; 4881 4882 /* copy data from runt m */ 4883 memcpy(n->m_data + shortfall, m->m_data, 4884 m->m_len); 4885 4886 /* n holds what we stole from prev, plus m */ 4887 n->m_len = shortfall + m->m_len; 4888 4889 /* stitch n into chain and free m */ 4890 n->m_next = m->m_next; 4891 prev->m_next = n; 4892 /* KASSERT(m->m_next == NULL); */ 4893 m->m_next = NULL; 4894 m_free(m); 4895 m = n; /* for continuing loop */ 4896 } 4897 } 4898 } 4899 return 0; 4900 } 4901 4902 /* 4903 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4904 * pointers to descriptors. 4905 */ 4906 static int 4907 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4908 { 4909 struct bge_tx_bd *f = NULL; 4910 uint32_t frag, cur; 4911 uint16_t csum_flags = 0; 4912 uint16_t txbd_tso_flags = 0; 4913 struct txdmamap_pool_entry *dma; 4914 bus_dmamap_t dmamap; 4915 int i = 0; 4916 struct m_tag *mtag; 4917 int use_tso, maxsegsize, error; 4918 4919 cur = frag = *txidx; 4920 4921 if (m_head->m_pkthdr.csum_flags) { 4922 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4923 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4924 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4925 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4926 } 4927 4928 /* 4929 * If we were asked to do an outboard checksum, and the NIC 4930 * has the bug where it sometimes adds in the Ethernet padding, 4931 * explicitly pad with zeros so the cksum will be correct either way. 4932 * (For now, do this for all chip versions, until newer 4933 * are confirmed to not require the workaround.) 4934 */ 4935 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4936 #ifdef notyet 4937 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4938 #endif 4939 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4940 goto check_dma_bug; 4941 4942 if (bge_cksum_pad(m_head) != 0) 4943 return ENOBUFS; 4944 4945 check_dma_bug: 4946 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4947 goto doit; 4948 4949 /* 4950 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4951 * less than eight bytes. If we encounter a teeny mbuf 4952 * at the end of a chain, we can pad. Otherwise, copy. 4953 */ 4954 if (bge_compact_dma_runt(m_head) != 0) 4955 return ENOBUFS; 4956 4957 doit: 4958 dma = SLIST_FIRST(&sc->txdma_list); 4959 if (dma == NULL) 4960 return ENOBUFS; 4961 dmamap = dma->dmamap; 4962 4963 /* 4964 * Set up any necessary TSO state before we start packing... 4965 */ 4966 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 4967 if (!use_tso) { 4968 maxsegsize = 0; 4969 } else { /* TSO setup */ 4970 unsigned mss; 4971 struct ether_header *eh; 4972 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 4973 struct mbuf * m0 = m_head; 4974 struct ip *ip; 4975 struct tcphdr *th; 4976 int iphl, hlen; 4977 4978 /* 4979 * XXX It would be nice if the mbuf pkthdr had offset 4980 * fields for the protocol headers. 4981 */ 4982 4983 eh = mtod(m0, struct ether_header *); 4984 switch (htons(eh->ether_type)) { 4985 case ETHERTYPE_IP: 4986 offset = ETHER_HDR_LEN; 4987 break; 4988 4989 case ETHERTYPE_VLAN: 4990 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4991 break; 4992 4993 default: 4994 /* 4995 * Don't support this protocol or encapsulation. 4996 */ 4997 return ENOBUFS; 4998 } 4999 5000 /* 5001 * TCP/IP headers are in the first mbuf; we can do 5002 * this the easy way. 5003 */ 5004 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5005 hlen = iphl + offset; 5006 if (__predict_false(m0->m_len < 5007 (hlen + sizeof(struct tcphdr)))) { 5008 5009 aprint_debug_dev(sc->bge_dev, 5010 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5011 "not handled yet\n", 5012 m0->m_len, hlen+ sizeof(struct tcphdr)); 5013 #ifdef NOTYET 5014 /* 5015 * XXX jonathan (at) NetBSD.org: untested. 5016 * how to force this branch to be taken? 5017 */ 5018 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 5019 5020 m_copydata(m0, offset, sizeof(ip), &ip); 5021 m_copydata(m0, hlen, sizeof(th), &th); 5022 5023 ip.ip_len = 0; 5024 5025 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5026 sizeof(ip.ip_len), &ip.ip_len); 5027 5028 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5029 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5030 5031 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5032 sizeof(th.th_sum), &th.th_sum); 5033 5034 hlen += th.th_off << 2; 5035 iptcp_opt_words = hlen; 5036 #else 5037 /* 5038 * if_wm "hard" case not yet supported, can we not 5039 * mandate it out of existence? 5040 */ 5041 (void) ip; (void)th; (void) ip_tcp_hlen; 5042 5043 return ENOBUFS; 5044 #endif 5045 } else { 5046 ip = (struct ip *) (mtod(m0, char *) + offset); 5047 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5048 ip_tcp_hlen = iphl + (th->th_off << 2); 5049 5050 /* Total IP/TCP options, in 32-bit words */ 5051 iptcp_opt_words = (ip_tcp_hlen 5052 - sizeof(struct tcphdr) 5053 - sizeof(struct ip)) >> 2; 5054 } 5055 if (BGE_IS_575X_PLUS(sc)) { 5056 th->th_sum = 0; 5057 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5058 } else { 5059 /* 5060 * XXX jonathan (at) NetBSD.org: 5705 untested. 5061 * Requires TSO firmware patch for 5701/5703/5704. 5062 */ 5063 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5064 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5065 } 5066 5067 mss = m_head->m_pkthdr.segsz; 5068 txbd_tso_flags |= 5069 BGE_TXBDFLAG_CPU_PRE_DMA | 5070 BGE_TXBDFLAG_CPU_POST_DMA; 5071 5072 /* 5073 * Our NIC TSO-assist assumes TSO has standard, optionless 5074 * IPv4 and TCP headers, which total 40 bytes. By default, 5075 * the NIC copies 40 bytes of IP/TCP header from the 5076 * supplied header into the IP/TCP header portion of 5077 * each post-TSO-segment. If the supplied packet has IP or 5078 * TCP options, we need to tell the NIC to copy those extra 5079 * bytes into each post-TSO header, in addition to the normal 5080 * 40-byte IP/TCP header (and to leave space accordingly). 5081 * Unfortunately, the driver encoding of option length 5082 * varies across different ASIC families. 5083 */ 5084 tcp_seg_flags = 0; 5085 if (iptcp_opt_words) { 5086 if (BGE_IS_5705_PLUS(sc)) { 5087 tcp_seg_flags = 5088 iptcp_opt_words << 11; 5089 } else { 5090 txbd_tso_flags |= 5091 iptcp_opt_words << 12; 5092 } 5093 } 5094 maxsegsize = mss | tcp_seg_flags; 5095 ip->ip_len = htons(mss + ip_tcp_hlen); 5096 5097 } /* TSO setup */ 5098 5099 /* 5100 * Start packing the mbufs in this chain into 5101 * the fragment pointers. Stop when we run out 5102 * of fragments or hit the end of the mbuf chain. 5103 */ 5104 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5105 BUS_DMA_NOWAIT); 5106 if (error) 5107 return ENOBUFS; 5108 /* 5109 * Sanity check: avoid coming within 16 descriptors 5110 * of the end of the ring. 5111 */ 5112 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5113 BGE_TSO_PRINTF(("%s: " 5114 " dmamap_load_mbuf too close to ring wrap\n", 5115 device_xname(sc->bge_dev))); 5116 goto fail_unload; 5117 } 5118 5119 mtag = sc->ethercom.ec_nvlans ? 5120 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5121 5122 5123 /* Iterate over dmap-map fragments. */ 5124 for (i = 0; i < dmamap->dm_nsegs; i++) { 5125 f = &sc->bge_rdata->bge_tx_ring[frag]; 5126 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5127 break; 5128 5129 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5130 f->bge_len = dmamap->dm_segs[i].ds_len; 5131 5132 /* 5133 * For 5751 and follow-ons, for TSO we must turn 5134 * off checksum-assist flag in the tx-descr, and 5135 * supply the ASIC-revision-specific encoding 5136 * of TSO flags and segsize. 5137 */ 5138 if (use_tso) { 5139 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5140 f->bge_rsvd = maxsegsize; 5141 f->bge_flags = csum_flags | txbd_tso_flags; 5142 } else { 5143 f->bge_rsvd = 0; 5144 f->bge_flags = 5145 (csum_flags | txbd_tso_flags) & 0x0fff; 5146 } 5147 } else { 5148 f->bge_rsvd = 0; 5149 f->bge_flags = csum_flags; 5150 } 5151 5152 if (mtag != NULL) { 5153 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5154 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5155 } else { 5156 f->bge_vlan_tag = 0; 5157 } 5158 cur = frag; 5159 BGE_INC(frag, BGE_TX_RING_CNT); 5160 } 5161 5162 if (i < dmamap->dm_nsegs) { 5163 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5164 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5165 goto fail_unload; 5166 } 5167 5168 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5169 BUS_DMASYNC_PREWRITE); 5170 5171 if (frag == sc->bge_tx_saved_considx) { 5172 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5173 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5174 5175 goto fail_unload; 5176 } 5177 5178 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5179 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5180 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5181 sc->txdma[cur] = dma; 5182 sc->bge_txcnt += dmamap->dm_nsegs; 5183 5184 *txidx = frag; 5185 5186 return 0; 5187 5188 fail_unload: 5189 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5190 5191 return ENOBUFS; 5192 } 5193 5194 /* 5195 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5196 * to the mbuf data regions directly in the transmit descriptors. 5197 */ 5198 static void 5199 bge_start(struct ifnet *ifp) 5200 { 5201 struct bge_softc *sc; 5202 struct mbuf *m_head = NULL; 5203 uint32_t prodidx; 5204 int pkts = 0; 5205 5206 sc = ifp->if_softc; 5207 5208 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5209 return; 5210 5211 prodidx = sc->bge_tx_prodidx; 5212 5213 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5214 IFQ_POLL(&ifp->if_snd, m_head); 5215 if (m_head == NULL) 5216 break; 5217 5218 #if 0 5219 /* 5220 * XXX 5221 * safety overkill. If this is a fragmented packet chain 5222 * with delayed TCP/UDP checksums, then only encapsulate 5223 * it if we have enough descriptors to handle the entire 5224 * chain at once. 5225 * (paranoia -- may not actually be needed) 5226 */ 5227 if (m_head->m_flags & M_FIRSTFRAG && 5228 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5229 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5230 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5231 ifp->if_flags |= IFF_OACTIVE; 5232 break; 5233 } 5234 } 5235 #endif 5236 5237 /* 5238 * Pack the data into the transmit ring. If we 5239 * don't have room, set the OACTIVE flag and wait 5240 * for the NIC to drain the ring. 5241 */ 5242 if (bge_encap(sc, m_head, &prodidx)) { 5243 ifp->if_flags |= IFF_OACTIVE; 5244 break; 5245 } 5246 5247 /* now we are committed to transmit the packet */ 5248 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5249 pkts++; 5250 5251 /* 5252 * If there's a BPF listener, bounce a copy of this frame 5253 * to him. 5254 */ 5255 bpf_mtap(ifp, m_head); 5256 } 5257 if (pkts == 0) 5258 return; 5259 5260 /* Transmit */ 5261 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5262 /* 5700 b2 errata */ 5263 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5264 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5265 5266 sc->bge_tx_prodidx = prodidx; 5267 5268 /* 5269 * Set a timeout in case the chip goes out to lunch. 5270 */ 5271 ifp->if_timer = 5; 5272 } 5273 5274 static int 5275 bge_init(struct ifnet *ifp) 5276 { 5277 struct bge_softc *sc = ifp->if_softc; 5278 const uint16_t *m; 5279 uint32_t mode, reg; 5280 int s, error = 0; 5281 5282 s = splnet(); 5283 5284 ifp = &sc->ethercom.ec_if; 5285 5286 /* Cancel pending I/O and flush buffers. */ 5287 bge_stop(ifp, 0); 5288 5289 bge_stop_fw(sc); 5290 bge_sig_pre_reset(sc, BGE_RESET_START); 5291 bge_reset(sc); 5292 bge_sig_legacy(sc, BGE_RESET_START); 5293 bge_sig_post_reset(sc, BGE_RESET_START); 5294 5295 bge_chipinit(sc); 5296 5297 /* 5298 * Init the various state machines, ring 5299 * control blocks and firmware. 5300 */ 5301 error = bge_blockinit(sc); 5302 if (error != 0) { 5303 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5304 error); 5305 splx(s); 5306 return error; 5307 } 5308 5309 ifp = &sc->ethercom.ec_if; 5310 5311 /* 5718 step 25, 57XX step 54 */ 5312 /* Specify MTU. */ 5313 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5314 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5315 5316 /* 5718 step 23 */ 5317 /* Load our MAC address. */ 5318 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5319 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5320 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5321 5322 /* Enable or disable promiscuous mode as needed. */ 5323 if (ifp->if_flags & IFF_PROMISC) 5324 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5325 else 5326 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5327 5328 /* Program multicast filter. */ 5329 bge_setmulti(sc); 5330 5331 /* Init RX ring. */ 5332 bge_init_rx_ring_std(sc); 5333 5334 /* 5335 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5336 * memory to insure that the chip has in fact read the first 5337 * entry of the ring. 5338 */ 5339 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5340 uint32_t v, i; 5341 for (i = 0; i < 10; i++) { 5342 DELAY(20); 5343 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5344 if (v == (MCLBYTES - ETHER_ALIGN)) 5345 break; 5346 } 5347 if (i == 10) 5348 aprint_error_dev(sc->bge_dev, 5349 "5705 A0 chip failed to load RX ring\n"); 5350 } 5351 5352 /* Init jumbo RX ring. */ 5353 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5354 bge_init_rx_ring_jumbo(sc); 5355 5356 /* Init our RX return ring index */ 5357 sc->bge_rx_saved_considx = 0; 5358 5359 /* Init TX ring. */ 5360 bge_init_tx_ring(sc); 5361 5362 /* 5718 step 63, 57XX step 94 */ 5363 /* Enable TX MAC state machine lockup fix. */ 5364 mode = CSR_READ_4(sc, BGE_TX_MODE); 5365 if (BGE_IS_5755_PLUS(sc) || 5366 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5367 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5369 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5370 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5371 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5372 } 5373 5374 /* Turn on transmitter */ 5375 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5376 /* 5718 step 64 */ 5377 DELAY(100); 5378 5379 /* 5718 step 65, 57XX step 95 */ 5380 /* Turn on receiver */ 5381 mode = CSR_READ_4(sc, BGE_RX_MODE); 5382 if (BGE_IS_5755_PLUS(sc)) 5383 mode |= BGE_RXMODE_IPV6_ENABLE; 5384 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5385 /* 5718 step 66 */ 5386 DELAY(10); 5387 5388 /* 5718 step 12, 57XX step 37 */ 5389 /* 5390 * XXX Doucments of 5718 series and 577xx say the recommended value 5391 * is 1, but tg3 set 1 only on 57765 series. 5392 */ 5393 if (BGE_IS_57765_PLUS(sc)) 5394 reg = 1; 5395 else 5396 reg = 2; 5397 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5398 5399 /* Tell firmware we're alive. */ 5400 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5401 5402 /* Enable host interrupts. */ 5403 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5404 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5405 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5406 5407 if ((error = bge_ifmedia_upd(ifp)) != 0) 5408 goto out; 5409 5410 ifp->if_flags |= IFF_RUNNING; 5411 ifp->if_flags &= ~IFF_OACTIVE; 5412 5413 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5414 5415 out: 5416 sc->bge_if_flags = ifp->if_flags; 5417 splx(s); 5418 5419 return error; 5420 } 5421 5422 /* 5423 * Set media options. 5424 */ 5425 static int 5426 bge_ifmedia_upd(struct ifnet *ifp) 5427 { 5428 struct bge_softc *sc = ifp->if_softc; 5429 struct mii_data *mii = &sc->bge_mii; 5430 struct ifmedia *ifm = &sc->bge_ifmedia; 5431 int rc; 5432 5433 /* If this is a 1000baseX NIC, enable the TBI port. */ 5434 if (sc->bge_flags & BGEF_FIBER_TBI) { 5435 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5436 return EINVAL; 5437 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5438 case IFM_AUTO: 5439 /* 5440 * The BCM5704 ASIC appears to have a special 5441 * mechanism for programming the autoneg 5442 * advertisement registers in TBI mode. 5443 */ 5444 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5445 uint32_t sgdig; 5446 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5447 if (sgdig & BGE_SGDIGSTS_DONE) { 5448 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5449 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5450 sgdig |= BGE_SGDIGCFG_AUTO | 5451 BGE_SGDIGCFG_PAUSE_CAP | 5452 BGE_SGDIGCFG_ASYM_PAUSE; 5453 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5454 sgdig | BGE_SGDIGCFG_SEND); 5455 DELAY(5); 5456 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5457 sgdig); 5458 } 5459 } 5460 break; 5461 case IFM_1000_SX: 5462 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5463 BGE_CLRBIT(sc, BGE_MAC_MODE, 5464 BGE_MACMODE_HALF_DUPLEX); 5465 } else { 5466 BGE_SETBIT(sc, BGE_MAC_MODE, 5467 BGE_MACMODE_HALF_DUPLEX); 5468 } 5469 DELAY(40); 5470 break; 5471 default: 5472 return EINVAL; 5473 } 5474 /* XXX 802.3x flow control for 1000BASE-SX */ 5475 return 0; 5476 } 5477 5478 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5479 if ((rc = mii_mediachg(mii)) == ENXIO) 5480 return 0; 5481 5482 /* 5483 * Force an interrupt so that we will call bge_link_upd 5484 * if needed and clear any pending link state attention. 5485 * Without this we are not getting any further interrupts 5486 * for link state changes and thus will not UP the link and 5487 * not be able to send in bge_start. The only way to get 5488 * things working was to receive a packet and get a RX intr. 5489 */ 5490 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5491 sc->bge_flags & BGEF_IS_5788) 5492 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5493 else 5494 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5495 5496 return rc; 5497 } 5498 5499 /* 5500 * Report current media status. 5501 */ 5502 static void 5503 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5504 { 5505 struct bge_softc *sc = ifp->if_softc; 5506 struct mii_data *mii = &sc->bge_mii; 5507 5508 if (sc->bge_flags & BGEF_FIBER_TBI) { 5509 ifmr->ifm_status = IFM_AVALID; 5510 ifmr->ifm_active = IFM_ETHER; 5511 if (CSR_READ_4(sc, BGE_MAC_STS) & 5512 BGE_MACSTAT_TBI_PCS_SYNCHED) 5513 ifmr->ifm_status |= IFM_ACTIVE; 5514 ifmr->ifm_active |= IFM_1000_SX; 5515 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5516 ifmr->ifm_active |= IFM_HDX; 5517 else 5518 ifmr->ifm_active |= IFM_FDX; 5519 return; 5520 } 5521 5522 mii_pollstat(mii); 5523 ifmr->ifm_status = mii->mii_media_status; 5524 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5525 sc->bge_flowflags; 5526 } 5527 5528 static int 5529 bge_ifflags_cb(struct ethercom *ec) 5530 { 5531 struct ifnet *ifp = &ec->ec_if; 5532 struct bge_softc *sc = ifp->if_softc; 5533 int change = ifp->if_flags ^ sc->bge_if_flags; 5534 5535 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5536 return ENETRESET; 5537 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5538 return 0; 5539 5540 if ((ifp->if_flags & IFF_PROMISC) == 0) 5541 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5542 else 5543 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5544 5545 bge_setmulti(sc); 5546 5547 sc->bge_if_flags = ifp->if_flags; 5548 return 0; 5549 } 5550 5551 static int 5552 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5553 { 5554 struct bge_softc *sc = ifp->if_softc; 5555 struct ifreq *ifr = (struct ifreq *) data; 5556 int s, error = 0; 5557 struct mii_data *mii; 5558 5559 s = splnet(); 5560 5561 switch (command) { 5562 case SIOCSIFMEDIA: 5563 /* XXX Flow control is not supported for 1000BASE-SX */ 5564 if (sc->bge_flags & BGEF_FIBER_TBI) { 5565 ifr->ifr_media &= ~IFM_ETH_FMASK; 5566 sc->bge_flowflags = 0; 5567 } 5568 5569 /* Flow control requires full-duplex mode. */ 5570 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5571 (ifr->ifr_media & IFM_FDX) == 0) { 5572 ifr->ifr_media &= ~IFM_ETH_FMASK; 5573 } 5574 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5575 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5576 /* We can do both TXPAUSE and RXPAUSE. */ 5577 ifr->ifr_media |= 5578 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5579 } 5580 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5581 } 5582 /* FALLTHROUGH */ 5583 case SIOCGIFMEDIA: 5584 if (sc->bge_flags & BGEF_FIBER_TBI) { 5585 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5586 command); 5587 } else { 5588 mii = &sc->bge_mii; 5589 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5590 command); 5591 } 5592 break; 5593 default: 5594 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5595 break; 5596 5597 error = 0; 5598 5599 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5600 ; 5601 else if (ifp->if_flags & IFF_RUNNING) 5602 bge_setmulti(sc); 5603 break; 5604 } 5605 5606 splx(s); 5607 5608 return error; 5609 } 5610 5611 static void 5612 bge_watchdog(struct ifnet *ifp) 5613 { 5614 struct bge_softc *sc; 5615 5616 sc = ifp->if_softc; 5617 5618 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5619 5620 ifp->if_flags &= ~IFF_RUNNING; 5621 bge_init(ifp); 5622 5623 ifp->if_oerrors++; 5624 } 5625 5626 static void 5627 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5628 { 5629 int i; 5630 5631 BGE_CLRBIT_FLUSH(sc, reg, bit); 5632 5633 for (i = 0; i < 1000; i++) { 5634 delay(100); 5635 if ((CSR_READ_4(sc, reg) & bit) == 0) 5636 return; 5637 } 5638 5639 /* 5640 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5641 * on some environment (and once after boot?) 5642 */ 5643 if (reg != BGE_SRS_MODE) 5644 aprint_error_dev(sc->bge_dev, 5645 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5646 (u_long)reg, bit); 5647 } 5648 5649 /* 5650 * Stop the adapter and free any mbufs allocated to the 5651 * RX and TX lists. 5652 */ 5653 static void 5654 bge_stop(struct ifnet *ifp, int disable) 5655 { 5656 struct bge_softc *sc = ifp->if_softc; 5657 5658 callout_stop(&sc->bge_timeout); 5659 5660 /* Disable host interrupts. */ 5661 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5662 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5663 5664 /* 5665 * Tell firmware we're shutting down. 5666 */ 5667 bge_stop_fw(sc); 5668 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5669 5670 /* 5671 * Disable all of the receiver blocks. 5672 */ 5673 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5674 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5675 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5676 if (BGE_IS_5700_FAMILY(sc)) 5677 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5678 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5679 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5680 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5681 5682 /* 5683 * Disable all of the transmit blocks. 5684 */ 5685 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5686 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5687 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5688 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5689 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5690 if (BGE_IS_5700_FAMILY(sc)) 5691 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5692 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5693 5694 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5695 delay(40); 5696 5697 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5698 5699 /* 5700 * Shut down all of the memory managers and related 5701 * state machines. 5702 */ 5703 /* 5718 step 5a,5b */ 5704 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5705 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5706 if (BGE_IS_5700_FAMILY(sc)) 5707 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5708 5709 /* 5718 step 5c,5d */ 5710 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5711 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5712 5713 if (BGE_IS_5700_FAMILY(sc)) { 5714 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5715 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5716 } 5717 5718 bge_reset(sc); 5719 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5720 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5721 5722 /* 5723 * Keep the ASF firmware running if up. 5724 */ 5725 if (sc->bge_asf_mode & ASF_STACKUP) 5726 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5727 else 5728 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5729 5730 /* Free the RX lists. */ 5731 bge_free_rx_ring_std(sc); 5732 5733 /* Free jumbo RX list. */ 5734 if (BGE_IS_JUMBO_CAPABLE(sc)) 5735 bge_free_rx_ring_jumbo(sc); 5736 5737 /* Free TX buffers. */ 5738 bge_free_tx_ring(sc); 5739 5740 /* 5741 * Isolate/power down the PHY. 5742 */ 5743 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 5744 mii_down(&sc->bge_mii); 5745 5746 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5747 5748 /* Clear MAC's link state (PHY may still have link UP). */ 5749 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5750 5751 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5752 } 5753 5754 static void 5755 bge_link_upd(struct bge_softc *sc) 5756 { 5757 struct ifnet *ifp = &sc->ethercom.ec_if; 5758 struct mii_data *mii = &sc->bge_mii; 5759 uint32_t status; 5760 int link; 5761 5762 /* Clear 'pending link event' flag */ 5763 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5764 5765 /* 5766 * Process link state changes. 5767 * Grrr. The link status word in the status block does 5768 * not work correctly on the BCM5700 rev AX and BX chips, 5769 * according to all available information. Hence, we have 5770 * to enable MII interrupts in order to properly obtain 5771 * async link changes. Unfortunately, this also means that 5772 * we have to read the MAC status register to detect link 5773 * changes, thereby adding an additional register access to 5774 * the interrupt handler. 5775 */ 5776 5777 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5778 status = CSR_READ_4(sc, BGE_MAC_STS); 5779 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5780 mii_pollstat(mii); 5781 5782 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5783 mii->mii_media_status & IFM_ACTIVE && 5784 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5785 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5786 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5787 (!(mii->mii_media_status & IFM_ACTIVE) || 5788 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5789 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5790 5791 /* Clear the interrupt */ 5792 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5793 BGE_EVTENB_MI_INTERRUPT); 5794 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5795 BRGPHY_MII_ISR); 5796 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5797 BRGPHY_MII_IMR, BRGPHY_INTRS); 5798 } 5799 return; 5800 } 5801 5802 if (sc->bge_flags & BGEF_FIBER_TBI) { 5803 status = CSR_READ_4(sc, BGE_MAC_STS); 5804 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5805 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5806 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5807 if (BGE_ASICREV(sc->bge_chipid) 5808 == BGE_ASICREV_BCM5704) { 5809 BGE_CLRBIT(sc, BGE_MAC_MODE, 5810 BGE_MACMODE_TBI_SEND_CFGS); 5811 DELAY(40); 5812 } 5813 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5814 if_link_state_change(ifp, LINK_STATE_UP); 5815 } 5816 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5817 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5818 if_link_state_change(ifp, LINK_STATE_DOWN); 5819 } 5820 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5821 /* 5822 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5823 * bit in status word always set. Workaround this bug by 5824 * reading PHY link status directly. 5825 */ 5826 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5827 BGE_STS_LINK : 0; 5828 5829 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5830 mii_pollstat(mii); 5831 5832 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5833 mii->mii_media_status & IFM_ACTIVE && 5834 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5835 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5836 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5837 (!(mii->mii_media_status & IFM_ACTIVE) || 5838 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5839 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5840 } 5841 } else { 5842 /* 5843 * For controllers that call mii_tick, we have to poll 5844 * link status. 5845 */ 5846 mii_pollstat(mii); 5847 } 5848 5849 /* Clear the attention */ 5850 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5851 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5852 BGE_MACSTAT_LINK_CHANGED); 5853 } 5854 5855 static int 5856 bge_sysctl_verify(SYSCTLFN_ARGS) 5857 { 5858 int error, t; 5859 struct sysctlnode node; 5860 5861 node = *rnode; 5862 t = *(int*)rnode->sysctl_data; 5863 node.sysctl_data = &t; 5864 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5865 if (error || newp == NULL) 5866 return error; 5867 5868 #if 0 5869 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5870 node.sysctl_num, rnode->sysctl_num)); 5871 #endif 5872 5873 if (node.sysctl_num == bge_rxthresh_nodenum) { 5874 if (t < 0 || t >= NBGE_RX_THRESH) 5875 return EINVAL; 5876 bge_update_all_threshes(t); 5877 } else 5878 return EINVAL; 5879 5880 *(int*)rnode->sysctl_data = t; 5881 5882 return 0; 5883 } 5884 5885 /* 5886 * Set up sysctl(3) MIB, hw.bge.*. 5887 */ 5888 static void 5889 bge_sysctl_init(struct bge_softc *sc) 5890 { 5891 int rc, bge_root_num; 5892 const struct sysctlnode *node; 5893 5894 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 5895 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 5896 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 5897 goto out; 5898 } 5899 5900 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5901 0, CTLTYPE_NODE, "bge", 5902 SYSCTL_DESCR("BGE interface controls"), 5903 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5904 goto out; 5905 } 5906 5907 bge_root_num = node->sysctl_num; 5908 5909 /* BGE Rx interrupt mitigation level */ 5910 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5911 CTLFLAG_READWRITE, 5912 CTLTYPE_INT, "rx_lvl", 5913 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5914 bge_sysctl_verify, 0, 5915 &bge_rx_thresh_lvl, 5916 0, CTL_HW, bge_root_num, CTL_CREATE, 5917 CTL_EOL)) != 0) { 5918 goto out; 5919 } 5920 5921 bge_rxthresh_nodenum = node->sysctl_num; 5922 5923 return; 5924 5925 out: 5926 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5927 } 5928 5929 #ifdef BGE_DEBUG 5930 void 5931 bge_debug_info(struct bge_softc *sc) 5932 { 5933 5934 printf("Hardware Flags:\n"); 5935 if (BGE_IS_57765_PLUS(sc)) 5936 printf(" - 57765 Plus\n"); 5937 if (BGE_IS_5717_PLUS(sc)) 5938 printf(" - 5717 Plus\n"); 5939 if (BGE_IS_5755_PLUS(sc)) 5940 printf(" - 5755 Plus\n"); 5941 if (BGE_IS_575X_PLUS(sc)) 5942 printf(" - 575X Plus\n"); 5943 if (BGE_IS_5705_PLUS(sc)) 5944 printf(" - 5705 Plus\n"); 5945 if (BGE_IS_5714_FAMILY(sc)) 5946 printf(" - 5714 Family\n"); 5947 if (BGE_IS_5700_FAMILY(sc)) 5948 printf(" - 5700 Family\n"); 5949 if (sc->bge_flags & BGEF_IS_5788) 5950 printf(" - 5788\n"); 5951 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 5952 printf(" - Supports Jumbo Frames\n"); 5953 if (sc->bge_flags & BGEF_NO_EEPROM) 5954 printf(" - No EEPROM\n"); 5955 if (sc->bge_flags & BGEF_PCIX) 5956 printf(" - PCI-X Bus\n"); 5957 if (sc->bge_flags & BGEF_PCIE) 5958 printf(" - PCI Express Bus\n"); 5959 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 5960 printf(" - RX Alignment Bug\n"); 5961 if (sc->bge_flags & BGEF_APE) 5962 printf(" - APE\n"); 5963 if (sc->bge_flags & BGEF_CPMU_PRESENT) 5964 printf(" - CPMU\n"); 5965 if (sc->bge_flags & BGEF_TSO) 5966 printf(" - TSO\n"); 5967 5968 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 5969 printf(" - No 3 LEDs\n"); 5970 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 5971 printf(" - CRC bug\n"); 5972 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 5973 printf(" - ADC bug\n"); 5974 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 5975 printf(" - 5704 A0 bug\n"); 5976 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 5977 printf(" - jitter bug\n"); 5978 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 5979 printf(" - BER bug\n"); 5980 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 5981 printf(" - adjust trim\n"); 5982 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 5983 printf(" - no wirespeed\n"); 5984 } 5985 #endif /* BGE_DEBUG */ 5986 5987 static int 5988 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5989 { 5990 prop_dictionary_t dict; 5991 prop_data_t ea; 5992 5993 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 5994 return 1; 5995 5996 dict = device_properties(sc->bge_dev); 5997 ea = prop_dictionary_get(dict, "mac-address"); 5998 if (ea != NULL) { 5999 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6000 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6001 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6002 return 0; 6003 } 6004 6005 return 1; 6006 } 6007 6008 static int 6009 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6010 { 6011 uint32_t mac_addr; 6012 6013 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6014 if ((mac_addr >> 16) == 0x484b) { 6015 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6016 ether_addr[1] = (uint8_t)mac_addr; 6017 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6018 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6019 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6020 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6021 ether_addr[5] = (uint8_t)mac_addr; 6022 return 0; 6023 } 6024 return 1; 6025 } 6026 6027 static int 6028 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6029 { 6030 int mac_offset = BGE_EE_MAC_OFFSET; 6031 6032 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6033 mac_offset = BGE_EE_MAC_OFFSET_5906; 6034 6035 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6036 ETHER_ADDR_LEN)); 6037 } 6038 6039 static int 6040 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6041 { 6042 6043 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6044 return 1; 6045 6046 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6047 ETHER_ADDR_LEN)); 6048 } 6049 6050 static int 6051 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6052 { 6053 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6054 /* NOTE: Order is critical */ 6055 bge_get_eaddr_fw, 6056 bge_get_eaddr_mem, 6057 bge_get_eaddr_nvram, 6058 bge_get_eaddr_eeprom, 6059 NULL 6060 }; 6061 const bge_eaddr_fcn_t *func; 6062 6063 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6064 if ((*func)(sc, eaddr) == 0) 6065 break; 6066 } 6067 return (*func == NULL ? ENXIO : 0); 6068 } 6069
Indexes created Mon Sep 22 13:09:51 GMT 2025