if_bge.c revision 1.274
1 /* $NetBSD: if_bge.c,v 1.274 2014/07/24 07:33:24 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.274 2014/07/24 07:33:24 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rnd.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 680 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 683 684 static const struct bge_revision { 685 uint32_t br_chipid; 686 const char *br_name; 687 } bge_revisions[] = { 688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 743 /* 5754 and 5787 share the same ASIC ID */ 744 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 745 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 746 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 747 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 748 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 749 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 750 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 751 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 752 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 753 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 754 755 { 0, NULL } 756 }; 757 758 /* 759 * Some defaults for major revisions, so that newer steppings 760 * that we don't know about have a shot at working. 761 */ 762 static const struct bge_revision bge_majorrevs[] = { 763 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 764 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 765 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 766 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 767 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 768 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 769 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 770 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 772 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 773 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 774 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 775 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 776 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 777 /* 5754 and 5787 share the same ASIC ID */ 778 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 779 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 780 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 781 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 782 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 783 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 784 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 785 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 786 787 { 0, NULL } 788 }; 789 790 static int bge_allow_asf = 1; 791 792 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 793 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 794 795 static uint32_t 796 bge_readmem_ind(struct bge_softc *sc, int off) 797 { 798 pcireg_t val; 799 800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 801 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 802 return 0; 803 804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 805 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 806 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 807 return val; 808 } 809 810 static void 811 bge_writemem_ind(struct bge_softc *sc, int off, int val) 812 { 813 814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 817 } 818 819 /* 820 * PCI Express only 821 */ 822 static void 823 bge_set_max_readrq(struct bge_softc *sc) 824 { 825 pcireg_t val; 826 827 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 828 + PCIE_DCSR); 829 val &= ~PCIE_DCSR_MAX_READ_REQ; 830 switch (sc->bge_expmrq) { 831 case 2048: 832 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 833 break; 834 case 4096: 835 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 836 break; 837 default: 838 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 839 break; 840 } 841 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 842 + PCIE_DCSR, val); 843 } 844 845 #ifdef notdef 846 static uint32_t 847 bge_readreg_ind(struct bge_softc *sc, int off) 848 { 849 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 850 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 851 } 852 #endif 853 854 static void 855 bge_writereg_ind(struct bge_softc *sc, int off, int val) 856 { 857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 859 } 860 861 static void 862 bge_writemem_direct(struct bge_softc *sc, int off, int val) 863 { 864 CSR_WRITE_4(sc, off, val); 865 } 866 867 static void 868 bge_writembx(struct bge_softc *sc, int off, int val) 869 { 870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 871 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 872 873 CSR_WRITE_4(sc, off, val); 874 } 875 876 static void 877 bge_writembx_flush(struct bge_softc *sc, int off, int val) 878 { 879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 880 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 881 882 CSR_WRITE_4_FLUSH(sc, off, val); 883 } 884 885 /* 886 * Clear all stale locks and select the lock for this driver instance. 887 */ 888 void 889 bge_ape_lock_init(struct bge_softc *sc) 890 { 891 struct pci_attach_args *pa = &(sc->bge_pa); 892 uint32_t bit, regbase; 893 int i; 894 895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 896 regbase = BGE_APE_LOCK_GRANT; 897 else 898 regbase = BGE_APE_PER_LOCK_GRANT; 899 900 /* Clear any stale locks. */ 901 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 902 switch (i) { 903 case BGE_APE_LOCK_PHY0: 904 case BGE_APE_LOCK_PHY1: 905 case BGE_APE_LOCK_PHY2: 906 case BGE_APE_LOCK_PHY3: 907 bit = BGE_APE_LOCK_GRANT_DRIVER0; 908 break; 909 default: 910 if (pa->pa_function == 0) 911 bit = BGE_APE_LOCK_GRANT_DRIVER0; 912 else 913 bit = (1 << pa->pa_function); 914 } 915 APE_WRITE_4(sc, regbase + 4 * i, bit); 916 } 917 918 /* Select the PHY lock based on the device's function number. */ 919 switch (pa->pa_function) { 920 case 0: 921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 922 break; 923 case 1: 924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 925 break; 926 case 2: 927 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 928 break; 929 case 3: 930 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 931 break; 932 default: 933 printf("%s: PHY lock not supported on function\n", 934 device_xname(sc->bge_dev)); 935 break; 936 } 937 } 938 939 /* 940 * Check for APE firmware, set flags, and print version info. 941 */ 942 void 943 bge_ape_read_fw_ver(struct bge_softc *sc) 944 { 945 const char *fwtype; 946 uint32_t apedata, features; 947 948 /* Check for a valid APE signature in shared memory. */ 949 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 950 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 951 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 952 return; 953 } 954 955 /* Check if APE firmware is running. */ 956 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 957 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 958 printf("%s: APE signature found but FW status not ready! " 959 "0x%08x\n", device_xname(sc->bge_dev), apedata); 960 return; 961 } 962 963 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 964 965 /* Fetch the APE firwmare type and version. */ 966 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 967 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 968 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 969 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 970 fwtype = "NCSI"; 971 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 972 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 973 fwtype = "DASH"; 974 } else 975 fwtype = "UNKN"; 976 977 /* Print the APE firmware version. */ 978 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 979 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 980 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 981 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 982 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 983 } 984 985 int 986 bge_ape_lock(struct bge_softc *sc, int locknum) 987 { 988 struct pci_attach_args *pa = &(sc->bge_pa); 989 uint32_t bit, gnt, req, status; 990 int i, off; 991 992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 993 return (0); 994 995 /* Lock request/grant registers have different bases. */ 996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 997 req = BGE_APE_LOCK_REQ; 998 gnt = BGE_APE_LOCK_GRANT; 999 } else { 1000 req = BGE_APE_PER_LOCK_REQ; 1001 gnt = BGE_APE_PER_LOCK_GRANT; 1002 } 1003 1004 off = 4 * locknum; 1005 1006 switch (locknum) { 1007 case BGE_APE_LOCK_GPIO: 1008 /* Lock required when using GPIO. */ 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1010 return (0); 1011 if (pa->pa_function == 0) 1012 bit = BGE_APE_LOCK_REQ_DRIVER0; 1013 else 1014 bit = (1 << pa->pa_function); 1015 break; 1016 case BGE_APE_LOCK_GRC: 1017 /* Lock required to reset the device. */ 1018 if (pa->pa_function == 0) 1019 bit = BGE_APE_LOCK_REQ_DRIVER0; 1020 else 1021 bit = (1 << pa->pa_function); 1022 break; 1023 case BGE_APE_LOCK_MEM: 1024 /* Lock required when accessing certain APE memory. */ 1025 if (pa->pa_function == 0) 1026 bit = BGE_APE_LOCK_REQ_DRIVER0; 1027 else 1028 bit = (1 << pa->pa_function); 1029 break; 1030 case BGE_APE_LOCK_PHY0: 1031 case BGE_APE_LOCK_PHY1: 1032 case BGE_APE_LOCK_PHY2: 1033 case BGE_APE_LOCK_PHY3: 1034 /* Lock required when accessing PHYs. */ 1035 bit = BGE_APE_LOCK_REQ_DRIVER0; 1036 break; 1037 default: 1038 return (EINVAL); 1039 } 1040 1041 /* Request a lock. */ 1042 APE_WRITE_4_FLUSH(sc, req + off, bit); 1043 1044 /* Wait up to 1 second to acquire lock. */ 1045 for (i = 0; i < 20000; i++) { 1046 status = APE_READ_4(sc, gnt + off); 1047 if (status == bit) 1048 break; 1049 DELAY(50); 1050 } 1051 1052 /* Handle any errors. */ 1053 if (status != bit) { 1054 printf("%s: APE lock %d request failed! " 1055 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1056 device_xname(sc->bge_dev), 1057 locknum, req + off, bit & 0xFFFF, gnt + off, 1058 status & 0xFFFF); 1059 /* Revoke the lock request. */ 1060 APE_WRITE_4(sc, gnt + off, bit); 1061 return (EBUSY); 1062 } 1063 1064 return (0); 1065 } 1066 1067 void 1068 bge_ape_unlock(struct bge_softc *sc, int locknum) 1069 { 1070 struct pci_attach_args *pa = &(sc->bge_pa); 1071 uint32_t bit, gnt; 1072 int off; 1073 1074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1075 return; 1076 1077 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1078 gnt = BGE_APE_LOCK_GRANT; 1079 else 1080 gnt = BGE_APE_PER_LOCK_GRANT; 1081 1082 off = 4 * locknum; 1083 1084 switch (locknum) { 1085 case BGE_APE_LOCK_GPIO: 1086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1087 return; 1088 if (pa->pa_function == 0) 1089 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1090 else 1091 bit = (1 << pa->pa_function); 1092 break; 1093 case BGE_APE_LOCK_GRC: 1094 if (pa->pa_function == 0) 1095 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1096 else 1097 bit = (1 << pa->pa_function); 1098 break; 1099 case BGE_APE_LOCK_MEM: 1100 if (pa->pa_function == 0) 1101 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1102 else 1103 bit = (1 << pa->pa_function); 1104 break; 1105 case BGE_APE_LOCK_PHY0: 1106 case BGE_APE_LOCK_PHY1: 1107 case BGE_APE_LOCK_PHY2: 1108 case BGE_APE_LOCK_PHY3: 1109 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1110 break; 1111 default: 1112 return; 1113 } 1114 1115 /* Write and flush for consecutive bge_ape_lock() */ 1116 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1117 } 1118 1119 /* 1120 * Send an event to the APE firmware. 1121 */ 1122 void 1123 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1124 { 1125 uint32_t apedata; 1126 int i; 1127 1128 /* NCSI does not support APE events. */ 1129 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1130 return; 1131 1132 /* Wait up to 1ms for APE to service previous event. */ 1133 for (i = 10; i > 0; i--) { 1134 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1135 break; 1136 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1137 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1138 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1139 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1141 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1142 break; 1143 } 1144 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1145 DELAY(100); 1146 } 1147 if (i == 0) { 1148 printf("%s: APE event 0x%08x send timed out\n", 1149 device_xname(sc->bge_dev), event); 1150 } 1151 } 1152 1153 void 1154 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1155 { 1156 uint32_t apedata, event; 1157 1158 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1159 return; 1160 1161 switch (kind) { 1162 case BGE_RESET_START: 1163 /* If this is the first load, clear the load counter. */ 1164 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1165 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1166 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1167 else { 1168 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1169 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1170 } 1171 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1172 BGE_APE_HOST_SEG_SIG_MAGIC); 1173 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1174 BGE_APE_HOST_SEG_LEN_MAGIC); 1175 1176 /* Add some version info if bge(4) supports it. */ 1177 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1178 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1179 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1180 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1181 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1182 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_START); 1185 event = BGE_APE_EVENT_STATUS_STATE_START; 1186 break; 1187 case BGE_RESET_SHUTDOWN: 1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1189 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1190 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1191 break; 1192 case BGE_RESET_SUSPEND: 1193 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1194 break; 1195 default: 1196 return; 1197 } 1198 1199 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1200 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1201 } 1202 1203 static uint8_t 1204 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1205 { 1206 uint32_t access, byte = 0; 1207 int i; 1208 1209 /* Lock. */ 1210 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1211 for (i = 0; i < 8000; i++) { 1212 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1213 break; 1214 DELAY(20); 1215 } 1216 if (i == 8000) 1217 return 1; 1218 1219 /* Enable access. */ 1220 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1221 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1222 1223 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1224 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1225 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1226 DELAY(10); 1227 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1228 DELAY(10); 1229 break; 1230 } 1231 } 1232 1233 if (i == BGE_TIMEOUT * 10) { 1234 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1235 return 1; 1236 } 1237 1238 /* Get result. */ 1239 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1240 1241 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1242 1243 /* Disable access. */ 1244 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1245 1246 /* Unlock. */ 1247 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * Read a sequence of bytes from NVRAM. 1254 */ 1255 static int 1256 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1257 { 1258 int error = 0, i; 1259 uint8_t byte = 0; 1260 1261 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1262 return 1; 1263 1264 for (i = 0; i < cnt; i++) { 1265 error = bge_nvram_getbyte(sc, off + i, &byte); 1266 if (error) 1267 break; 1268 *(dest + i) = byte; 1269 } 1270 1271 return (error ? 1 : 0); 1272 } 1273 1274 /* 1275 * Read a byte of data stored in the EEPROM at address 'addr.' The 1276 * BCM570x supports both the traditional bitbang interface and an 1277 * auto access interface for reading the EEPROM. We use the auto 1278 * access method. 1279 */ 1280 static uint8_t 1281 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1282 { 1283 int i; 1284 uint32_t byte = 0; 1285 1286 /* 1287 * Enable use of auto EEPROM access so we can avoid 1288 * having to use the bitbang method. 1289 */ 1290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1291 1292 /* Reset the EEPROM, load the clock period. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, 1294 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1295 DELAY(20); 1296 1297 /* Issue the read EEPROM command. */ 1298 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1299 1300 /* Wait for completion */ 1301 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1302 DELAY(10); 1303 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1304 break; 1305 } 1306 1307 if (i == BGE_TIMEOUT * 10) { 1308 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1309 return 1; 1310 } 1311 1312 /* Get result. */ 1313 byte = CSR_READ_4(sc, BGE_EE_DATA); 1314 1315 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1316 1317 return 0; 1318 } 1319 1320 /* 1321 * Read a sequence of bytes from the EEPROM. 1322 */ 1323 static int 1324 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1325 { 1326 int error = 0, i; 1327 uint8_t byte = 0; 1328 char *dest = destv; 1329 1330 for (i = 0; i < cnt; i++) { 1331 error = bge_eeprom_getbyte(sc, off + i, &byte); 1332 if (error) 1333 break; 1334 *(dest + i) = byte; 1335 } 1336 1337 return (error ? 1 : 0); 1338 } 1339 1340 static int 1341 bge_miibus_readreg(device_t dev, int phy, int reg) 1342 { 1343 struct bge_softc *sc = device_private(dev); 1344 uint32_t val; 1345 uint32_t autopoll; 1346 int i; 1347 1348 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1349 return 0; 1350 1351 /* Reading with autopolling on may trigger PCI errors */ 1352 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1353 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1354 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1355 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1356 DELAY(80); 1357 } 1358 1359 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1360 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1361 1362 for (i = 0; i < BGE_TIMEOUT; i++) { 1363 delay(10); 1364 val = CSR_READ_4(sc, BGE_MI_COMM); 1365 if (!(val & BGE_MICOMM_BUSY)) { 1366 DELAY(5); 1367 val = CSR_READ_4(sc, BGE_MI_COMM); 1368 break; 1369 } 1370 } 1371 1372 if (i == BGE_TIMEOUT) { 1373 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1374 val = 0; 1375 goto done; 1376 } 1377 1378 done: 1379 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1380 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1381 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1382 DELAY(80); 1383 } 1384 1385 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1386 1387 if (val & BGE_MICOMM_READFAIL) 1388 return 0; 1389 1390 return (val & 0xFFFF); 1391 } 1392 1393 static void 1394 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1395 { 1396 struct bge_softc *sc = device_private(dev); 1397 uint32_t autopoll; 1398 int i; 1399 1400 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1401 return; 1402 1403 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1404 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1405 return; 1406 1407 /* Reading with autopolling on may trigger PCI errors */ 1408 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1409 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1410 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1411 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1412 DELAY(80); 1413 } 1414 1415 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1416 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1417 1418 for (i = 0; i < BGE_TIMEOUT; i++) { 1419 delay(10); 1420 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1421 delay(5); 1422 CSR_READ_4(sc, BGE_MI_COMM); 1423 break; 1424 } 1425 } 1426 1427 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1428 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1429 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1430 delay(80); 1431 } 1432 1433 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1434 1435 if (i == BGE_TIMEOUT) 1436 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1437 } 1438 1439 static void 1440 bge_miibus_statchg(struct ifnet *ifp) 1441 { 1442 struct bge_softc *sc = ifp->if_softc; 1443 struct mii_data *mii = &sc->bge_mii; 1444 uint32_t mac_mode, rx_mode, tx_mode; 1445 1446 /* 1447 * Get flow control negotiation result. 1448 */ 1449 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1450 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1451 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1452 1453 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1454 mii->mii_media_status & IFM_ACTIVE && 1455 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1456 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1457 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1458 (!(mii->mii_media_status & IFM_ACTIVE) || 1459 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1460 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1461 1462 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1463 return; 1464 1465 /* Set the port mode (MII/GMII) to match the link speed. */ 1466 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1467 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1468 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1469 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1470 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1471 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1472 mac_mode |= BGE_PORTMODE_GMII; 1473 else 1474 mac_mode |= BGE_PORTMODE_MII; 1475 1476 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1477 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1478 if ((mii->mii_media_active & IFM_FDX) != 0) { 1479 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1480 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1481 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1482 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1483 } else 1484 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1485 1486 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1487 DELAY(40); 1488 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1489 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1490 } 1491 1492 /* 1493 * Update rx threshold levels to values in a particular slot 1494 * of the interrupt-mitigation table bge_rx_threshes. 1495 */ 1496 static void 1497 bge_set_thresh(struct ifnet *ifp, int lvl) 1498 { 1499 struct bge_softc *sc = ifp->if_softc; 1500 int s; 1501 1502 /* For now, just save the new Rx-intr thresholds and record 1503 * that a threshold update is pending. Updating the hardware 1504 * registers here (even at splhigh()) is observed to 1505 * occasionaly cause glitches where Rx-interrupts are not 1506 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1507 */ 1508 s = splnet(); 1509 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1510 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1511 sc->bge_pending_rxintr_change = 1; 1512 splx(s); 1513 } 1514 1515 1516 /* 1517 * Update Rx thresholds of all bge devices 1518 */ 1519 static void 1520 bge_update_all_threshes(int lvl) 1521 { 1522 struct ifnet *ifp; 1523 const char * const namebuf = "bge"; 1524 int namelen; 1525 1526 if (lvl < 0) 1527 lvl = 0; 1528 else if (lvl >= NBGE_RX_THRESH) 1529 lvl = NBGE_RX_THRESH - 1; 1530 1531 namelen = strlen(namebuf); 1532 /* 1533 * Now search all the interfaces for this name/number 1534 */ 1535 IFNET_FOREACH(ifp) { 1536 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1537 continue; 1538 /* We got a match: update if doing auto-threshold-tuning */ 1539 if (bge_auto_thresh) 1540 bge_set_thresh(ifp, lvl); 1541 } 1542 } 1543 1544 /* 1545 * Handle events that have triggered interrupts. 1546 */ 1547 static void 1548 bge_handle_events(struct bge_softc *sc) 1549 { 1550 1551 return; 1552 } 1553 1554 /* 1555 * Memory management for jumbo frames. 1556 */ 1557 1558 static int 1559 bge_alloc_jumbo_mem(struct bge_softc *sc) 1560 { 1561 char *ptr, *kva; 1562 bus_dma_segment_t seg; 1563 int i, rseg, state, error; 1564 struct bge_jpool_entry *entry; 1565 1566 state = error = 0; 1567 1568 /* Grab a big chunk o' storage. */ 1569 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1570 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1571 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1572 return ENOBUFS; 1573 } 1574 1575 state = 1; 1576 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1577 BUS_DMA_NOWAIT)) { 1578 aprint_error_dev(sc->bge_dev, 1579 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1580 error = ENOBUFS; 1581 goto out; 1582 } 1583 1584 state = 2; 1585 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1586 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1587 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1588 error = ENOBUFS; 1589 goto out; 1590 } 1591 1592 state = 3; 1593 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1594 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1595 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1596 error = ENOBUFS; 1597 goto out; 1598 } 1599 1600 state = 4; 1601 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1602 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1603 1604 SLIST_INIT(&sc->bge_jfree_listhead); 1605 SLIST_INIT(&sc->bge_jinuse_listhead); 1606 1607 /* 1608 * Now divide it up into 9K pieces and save the addresses 1609 * in an array. 1610 */ 1611 ptr = sc->bge_cdata.bge_jumbo_buf; 1612 for (i = 0; i < BGE_JSLOTS; i++) { 1613 sc->bge_cdata.bge_jslots[i] = ptr; 1614 ptr += BGE_JLEN; 1615 entry = malloc(sizeof(struct bge_jpool_entry), 1616 M_DEVBUF, M_NOWAIT); 1617 if (entry == NULL) { 1618 aprint_error_dev(sc->bge_dev, 1619 "no memory for jumbo buffer queue!\n"); 1620 error = ENOBUFS; 1621 goto out; 1622 } 1623 entry->slot = i; 1624 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1625 entry, jpool_entries); 1626 } 1627 out: 1628 if (error != 0) { 1629 switch (state) { 1630 case 4: 1631 bus_dmamap_unload(sc->bge_dmatag, 1632 sc->bge_cdata.bge_rx_jumbo_map); 1633 case 3: 1634 bus_dmamap_destroy(sc->bge_dmatag, 1635 sc->bge_cdata.bge_rx_jumbo_map); 1636 case 2: 1637 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1638 case 1: 1639 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1640 break; 1641 default: 1642 break; 1643 } 1644 } 1645 1646 return error; 1647 } 1648 1649 /* 1650 * Allocate a jumbo buffer. 1651 */ 1652 static void * 1653 bge_jalloc(struct bge_softc *sc) 1654 { 1655 struct bge_jpool_entry *entry; 1656 1657 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1658 1659 if (entry == NULL) { 1660 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1661 return NULL; 1662 } 1663 1664 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1665 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1666 return (sc->bge_cdata.bge_jslots[entry->slot]); 1667 } 1668 1669 /* 1670 * Release a jumbo buffer. 1671 */ 1672 static void 1673 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1674 { 1675 struct bge_jpool_entry *entry; 1676 struct bge_softc *sc; 1677 int i, s; 1678 1679 /* Extract the softc struct pointer. */ 1680 sc = (struct bge_softc *)arg; 1681 1682 if (sc == NULL) 1683 panic("bge_jfree: can't find softc pointer!"); 1684 1685 /* calculate the slot this buffer belongs to */ 1686 1687 i = ((char *)buf 1688 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1689 1690 if ((i < 0) || (i >= BGE_JSLOTS)) 1691 panic("bge_jfree: asked to free buffer that we don't manage!"); 1692 1693 s = splvm(); 1694 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1695 if (entry == NULL) 1696 panic("bge_jfree: buffer not in use!"); 1697 entry->slot = i; 1698 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1699 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1700 1701 if (__predict_true(m != NULL)) 1702 pool_cache_put(mb_cache, m); 1703 splx(s); 1704 } 1705 1706 1707 /* 1708 * Initialize a standard receive ring descriptor. 1709 */ 1710 static int 1711 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1712 bus_dmamap_t dmamap) 1713 { 1714 struct mbuf *m_new = NULL; 1715 struct bge_rx_bd *r; 1716 int error; 1717 1718 if (dmamap == NULL) { 1719 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1720 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1721 if (error != 0) 1722 return error; 1723 } 1724 1725 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1726 1727 if (m == NULL) { 1728 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1729 if (m_new == NULL) 1730 return ENOBUFS; 1731 1732 MCLGET(m_new, M_DONTWAIT); 1733 if (!(m_new->m_flags & M_EXT)) { 1734 m_freem(m_new); 1735 return ENOBUFS; 1736 } 1737 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1738 1739 } else { 1740 m_new = m; 1741 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1742 m_new->m_data = m_new->m_ext.ext_buf; 1743 } 1744 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1745 m_adj(m_new, ETHER_ALIGN); 1746 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1747 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1748 return ENOBUFS; 1749 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1750 BUS_DMASYNC_PREREAD); 1751 1752 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1753 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1754 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1755 r->bge_flags = BGE_RXBDFLAG_END; 1756 r->bge_len = m_new->m_len; 1757 r->bge_idx = i; 1758 1759 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1760 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1761 i * sizeof (struct bge_rx_bd), 1762 sizeof (struct bge_rx_bd), 1763 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1764 1765 return 0; 1766 } 1767 1768 /* 1769 * Initialize a jumbo receive ring descriptor. This allocates 1770 * a jumbo buffer from the pool managed internally by the driver. 1771 */ 1772 static int 1773 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1774 { 1775 struct mbuf *m_new = NULL; 1776 struct bge_rx_bd *r; 1777 void *buf = NULL; 1778 1779 if (m == NULL) { 1780 1781 /* Allocate the mbuf. */ 1782 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1783 if (m_new == NULL) 1784 return ENOBUFS; 1785 1786 /* Allocate the jumbo buffer */ 1787 buf = bge_jalloc(sc); 1788 if (buf == NULL) { 1789 m_freem(m_new); 1790 aprint_error_dev(sc->bge_dev, 1791 "jumbo allocation failed -- packet dropped!\n"); 1792 return ENOBUFS; 1793 } 1794 1795 /* Attach the buffer to the mbuf. */ 1796 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1797 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1798 bge_jfree, sc); 1799 m_new->m_flags |= M_EXT_RW; 1800 } else { 1801 m_new = m; 1802 buf = m_new->m_data = m_new->m_ext.ext_buf; 1803 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1804 } 1805 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1806 m_adj(m_new, ETHER_ALIGN); 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1808 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1809 BUS_DMASYNC_PREREAD); 1810 /* Set up the descriptor. */ 1811 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1812 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1813 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1814 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1815 r->bge_len = m_new->m_len; 1816 r->bge_idx = i; 1817 1818 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1819 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1820 i * sizeof (struct bge_rx_bd), 1821 sizeof (struct bge_rx_bd), 1822 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1823 1824 return 0; 1825 } 1826 1827 /* 1828 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1829 * that's 1MB or memory, which is a lot. For now, we fill only the first 1830 * 256 ring entries and hope that our CPU is fast enough to keep up with 1831 * the NIC. 1832 */ 1833 static int 1834 bge_init_rx_ring_std(struct bge_softc *sc) 1835 { 1836 int i; 1837 1838 if (sc->bge_flags & BGEF_RXRING_VALID) 1839 return 0; 1840 1841 for (i = 0; i < BGE_SSLOTS; i++) { 1842 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1843 return ENOBUFS; 1844 } 1845 1846 sc->bge_std = i - 1; 1847 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1848 1849 sc->bge_flags |= BGEF_RXRING_VALID; 1850 1851 return 0; 1852 } 1853 1854 static void 1855 bge_free_rx_ring_std(struct bge_softc *sc) 1856 { 1857 int i; 1858 1859 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1860 return; 1861 1862 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1863 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1864 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1865 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1866 bus_dmamap_destroy(sc->bge_dmatag, 1867 sc->bge_cdata.bge_rx_std_map[i]); 1868 } 1869 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1870 sizeof(struct bge_rx_bd)); 1871 } 1872 1873 sc->bge_flags &= ~BGEF_RXRING_VALID; 1874 } 1875 1876 static int 1877 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1878 { 1879 int i; 1880 volatile struct bge_rcb *rcb; 1881 1882 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1883 return 0; 1884 1885 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1886 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1887 return ENOBUFS; 1888 } 1889 1890 sc->bge_jumbo = i - 1; 1891 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1892 1893 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1894 rcb->bge_maxlen_flags = 0; 1895 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1896 1897 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1898 1899 return 0; 1900 } 1901 1902 static void 1903 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1904 { 1905 int i; 1906 1907 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1908 return; 1909 1910 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1911 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1912 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1913 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1914 } 1915 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1916 sizeof(struct bge_rx_bd)); 1917 } 1918 1919 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1920 } 1921 1922 static void 1923 bge_free_tx_ring(struct bge_softc *sc) 1924 { 1925 int i; 1926 struct txdmamap_pool_entry *dma; 1927 1928 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1929 return; 1930 1931 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1932 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1933 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1934 sc->bge_cdata.bge_tx_chain[i] = NULL; 1935 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1936 link); 1937 sc->txdma[i] = 0; 1938 } 1939 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1940 sizeof(struct bge_tx_bd)); 1941 } 1942 1943 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1944 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1945 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1946 free(dma, M_DEVBUF); 1947 } 1948 1949 sc->bge_flags &= ~BGEF_TXRING_VALID; 1950 } 1951 1952 static int 1953 bge_init_tx_ring(struct bge_softc *sc) 1954 { 1955 struct ifnet *ifp = &sc->ethercom.ec_if; 1956 int i; 1957 bus_dmamap_t dmamap; 1958 bus_size_t maxsegsz; 1959 struct txdmamap_pool_entry *dma; 1960 1961 if (sc->bge_flags & BGEF_TXRING_VALID) 1962 return 0; 1963 1964 sc->bge_txcnt = 0; 1965 sc->bge_tx_saved_considx = 0; 1966 1967 /* Initialize transmit producer index for host-memory send ring. */ 1968 sc->bge_tx_prodidx = 0; 1969 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1970 /* 5700 b2 errata */ 1971 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1972 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1973 1974 /* NIC-memory send ring not used; initialize to zero. */ 1975 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1976 /* 5700 b2 errata */ 1977 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1978 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1979 1980 /* Limit DMA segment size for some chips */ 1981 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1982 (ifp->if_mtu <= ETHERMTU)) 1983 maxsegsz = 2048; 1984 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1985 maxsegsz = 4096; 1986 else 1987 maxsegsz = ETHER_MAX_LEN_JUMBO; 1988 SLIST_INIT(&sc->txdma_list); 1989 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1990 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1991 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, 1992 &dmamap)) 1993 return ENOBUFS; 1994 if (dmamap == NULL) 1995 panic("dmamap NULL in bge_init_tx_ring"); 1996 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1997 if (dma == NULL) { 1998 aprint_error_dev(sc->bge_dev, 1999 "can't alloc txdmamap_pool_entry\n"); 2000 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2001 return ENOMEM; 2002 } 2003 dma->dmamap = dmamap; 2004 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2005 } 2006 2007 sc->bge_flags |= BGEF_TXRING_VALID; 2008 2009 return 0; 2010 } 2011 2012 static void 2013 bge_setmulti(struct bge_softc *sc) 2014 { 2015 struct ethercom *ac = &sc->ethercom; 2016 struct ifnet *ifp = &ac->ec_if; 2017 struct ether_multi *enm; 2018 struct ether_multistep step; 2019 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2020 uint32_t h; 2021 int i; 2022 2023 if (ifp->if_flags & IFF_PROMISC) 2024 goto allmulti; 2025 2026 /* Now program new ones. */ 2027 ETHER_FIRST_MULTI(step, ac, enm); 2028 while (enm != NULL) { 2029 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2030 /* 2031 * We must listen to a range of multicast addresses. 2032 * For now, just accept all multicasts, rather than 2033 * trying to set only those filter bits needed to match 2034 * the range. (At this time, the only use of address 2035 * ranges is for IP multicast routing, for which the 2036 * range is big enough to require all bits set.) 2037 */ 2038 goto allmulti; 2039 } 2040 2041 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2042 2043 /* Just want the 7 least-significant bits. */ 2044 h &= 0x7f; 2045 2046 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2047 ETHER_NEXT_MULTI(step, enm); 2048 } 2049 2050 ifp->if_flags &= ~IFF_ALLMULTI; 2051 goto setit; 2052 2053 allmulti: 2054 ifp->if_flags |= IFF_ALLMULTI; 2055 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2056 2057 setit: 2058 for (i = 0; i < 4; i++) 2059 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2060 } 2061 2062 static void 2063 bge_sig_pre_reset(struct bge_softc *sc, int type) 2064 { 2065 2066 /* 2067 * Some chips don't like this so only do this if ASF is enabled 2068 */ 2069 if (sc->bge_asf_mode) 2070 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2071 2072 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2073 switch (type) { 2074 case BGE_RESET_START: 2075 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2076 BGE_FW_DRV_STATE_START); 2077 break; 2078 case BGE_RESET_SHUTDOWN: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_UNLOAD); 2081 break; 2082 case BGE_RESET_SUSPEND: 2083 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2084 BGE_FW_DRV_STATE_SUSPEND); 2085 break; 2086 } 2087 } 2088 2089 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2090 bge_ape_driver_state_change(sc, type); 2091 } 2092 2093 static void 2094 bge_sig_post_reset(struct bge_softc *sc, int type) 2095 { 2096 2097 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2098 switch (type) { 2099 case BGE_RESET_START: 2100 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2101 BGE_FW_DRV_STATE_START_DONE); 2102 /* START DONE */ 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD_DONE); 2107 break; 2108 } 2109 } 2110 2111 if (type == BGE_RESET_SHUTDOWN) 2112 bge_ape_driver_state_change(sc, type); 2113 } 2114 2115 static void 2116 bge_sig_legacy(struct bge_softc *sc, int type) 2117 { 2118 2119 if (sc->bge_asf_mode) { 2120 switch (type) { 2121 case BGE_RESET_START: 2122 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2123 BGE_FW_DRV_STATE_START); 2124 break; 2125 case BGE_RESET_SHUTDOWN: 2126 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2127 BGE_FW_DRV_STATE_UNLOAD); 2128 break; 2129 } 2130 } 2131 } 2132 2133 static void 2134 bge_wait_for_event_ack(struct bge_softc *sc) 2135 { 2136 int i; 2137 2138 /* wait up to 2500usec */ 2139 for (i = 0; i < 250; i++) { 2140 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2141 BGE_RX_CPU_DRV_EVENT)) 2142 break; 2143 DELAY(10); 2144 } 2145 } 2146 2147 static void 2148 bge_stop_fw(struct bge_softc *sc) 2149 { 2150 2151 if (sc->bge_asf_mode) { 2152 bge_wait_for_event_ack(sc); 2153 2154 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2155 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2156 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2157 2158 bge_wait_for_event_ack(sc); 2159 } 2160 } 2161 2162 static int 2163 bge_poll_fw(struct bge_softc *sc) 2164 { 2165 uint32_t val; 2166 int i; 2167 2168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2169 for (i = 0; i < BGE_TIMEOUT; i++) { 2170 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2171 if (val & BGE_VCPU_STATUS_INIT_DONE) 2172 break; 2173 DELAY(100); 2174 } 2175 if (i >= BGE_TIMEOUT) { 2176 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2177 return -1; 2178 } 2179 } else { 2180 /* 2181 * Poll the value location we just wrote until 2182 * we see the 1's complement of the magic number. 2183 * This indicates that the firmware initialization 2184 * is complete. 2185 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2186 */ 2187 for (i = 0; i < BGE_TIMEOUT; i++) { 2188 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2189 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2190 break; 2191 DELAY(10); 2192 } 2193 2194 if ((i >= BGE_TIMEOUT) 2195 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2196 aprint_error_dev(sc->bge_dev, 2197 "firmware handshake timed out, val = %x\n", val); 2198 return -1; 2199 } 2200 } 2201 2202 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2203 /* tg3 says we have to wait extra time */ 2204 delay(10 * 1000); 2205 } 2206 2207 return 0; 2208 } 2209 2210 int 2211 bge_phy_addr(struct bge_softc *sc) 2212 { 2213 struct pci_attach_args *pa = &(sc->bge_pa); 2214 int phy_addr = 1; 2215 2216 /* 2217 * PHY address mapping for various devices. 2218 * 2219 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2220 * ---------+-------+-------+-------+-------+ 2221 * BCM57XX | 1 | X | X | X | 2222 * BCM5704 | 1 | X | 1 | X | 2223 * BCM5717 | 1 | 8 | 2 | 9 | 2224 * BCM5719 | 1 | 8 | 2 | 9 | 2225 * BCM5720 | 1 | 8 | 2 | 9 | 2226 * 2227 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2228 * ---------+-------+-------+-------+-------+ 2229 * BCM57XX | X | X | X | X | 2230 * BCM5704 | X | X | X | X | 2231 * BCM5717 | X | X | X | X | 2232 * BCM5719 | 3 | 10 | 4 | 11 | 2233 * BCM5720 | X | X | X | X | 2234 * 2235 * Other addresses may respond but they are not 2236 * IEEE compliant PHYs and should be ignored. 2237 */ 2238 switch (BGE_ASICREV(sc->bge_chipid)) { 2239 case BGE_ASICREV_BCM5717: 2240 case BGE_ASICREV_BCM5719: 2241 case BGE_ASICREV_BCM5720: 2242 phy_addr = pa->pa_function; 2243 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2244 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2245 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2246 } else { 2247 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2248 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2249 } 2250 } 2251 2252 return phy_addr; 2253 } 2254 2255 /* 2256 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2257 * self-test results. 2258 */ 2259 static int 2260 bge_chipinit(struct bge_softc *sc) 2261 { 2262 uint32_t dma_rw_ctl, mode_ctl, reg; 2263 int i; 2264 2265 /* Set endianness before we access any non-PCI registers. */ 2266 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2267 BGE_INIT); 2268 2269 /* 2270 * Clear the MAC statistics block in the NIC's 2271 * internal memory. 2272 */ 2273 for (i = BGE_STATS_BLOCK; 2274 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2275 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2276 2277 for (i = BGE_STATUS_BLOCK; 2278 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2279 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2280 2281 /* 5717 workaround from tg3 */ 2282 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2283 /* Save */ 2284 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2285 2286 /* Temporary modify MODE_CTL to control TLP */ 2287 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2288 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2289 2290 /* Control TLP */ 2291 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2292 BGE_TLP_PHYCTL1); 2293 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2294 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2295 2296 /* Restore */ 2297 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2298 } 2299 2300 if (BGE_IS_57765_FAMILY(sc)) { 2301 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2302 /* Save */ 2303 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2304 2305 /* Temporary modify MODE_CTL to control TLP */ 2306 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2307 CSR_WRITE_4(sc, BGE_MODE_CTL, 2308 reg | BGE_MODECTL_PCIE_TLPADDR1); 2309 2310 /* Control TLP */ 2311 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2312 BGE_TLP_PHYCTL5); 2313 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2314 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2315 2316 /* Restore */ 2317 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2318 } 2319 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2320 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2321 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2322 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2323 2324 /* Save */ 2325 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2326 2327 /* Temporary modify MODE_CTL to control TLP */ 2328 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2329 CSR_WRITE_4(sc, BGE_MODE_CTL, 2330 reg | BGE_MODECTL_PCIE_TLPADDR0); 2331 2332 /* Control TLP */ 2333 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2334 BGE_TLP_FTSMAX); 2335 reg &= ~BGE_TLP_FTSMAX_MSK; 2336 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2337 reg | BGE_TLP_FTSMAX_VAL); 2338 2339 /* Restore */ 2340 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2341 } 2342 2343 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2344 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2345 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2346 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2347 } 2348 2349 /* Set up the PCI DMA control register. */ 2350 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2351 if (sc->bge_flags & BGEF_PCIE) { 2352 /* Read watermark not used, 128 bytes for write. */ 2353 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2354 device_xname(sc->bge_dev))); 2355 if (sc->bge_mps >= 256) 2356 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2357 else 2358 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2359 } else if (sc->bge_flags & BGEF_PCIX) { 2360 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2361 device_xname(sc->bge_dev))); 2362 /* PCI-X bus */ 2363 if (BGE_IS_5714_FAMILY(sc)) { 2364 /* 256 bytes for read and write. */ 2365 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2366 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2367 2368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2369 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2370 else 2371 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2372 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2373 /* 1536 bytes for read, 384 bytes for write. */ 2374 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2375 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2376 } else { 2377 /* 384 bytes for read and write. */ 2378 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2379 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2380 (0x0F); 2381 } 2382 2383 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2384 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2385 uint32_t tmp; 2386 2387 /* Set ONEDMA_ATONCE for hardware workaround. */ 2388 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2389 if (tmp == 6 || tmp == 7) 2390 dma_rw_ctl |= 2391 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2392 2393 /* Set PCI-X DMA write workaround. */ 2394 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2395 } 2396 } else { 2397 /* Conventional PCI bus: 256 bytes for read and write. */ 2398 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2399 device_xname(sc->bge_dev))); 2400 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2401 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2402 2403 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2404 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2405 dma_rw_ctl |= 0x0F; 2406 } 2407 2408 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2409 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2410 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2411 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2412 2413 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2414 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2415 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2416 2417 if (BGE_IS_57765_PLUS(sc)) { 2418 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2419 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2420 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2421 2422 /* 2423 * Enable HW workaround for controllers that misinterpret 2424 * a status tag update and leave interrupts permanently 2425 * disabled. 2426 */ 2427 if (!BGE_IS_57765_FAMILY(sc) && 2428 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2429 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2430 } 2431 2432 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2433 dma_rw_ctl); 2434 2435 /* 2436 * Set up general mode register. 2437 */ 2438 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2439 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2440 /* Retain Host-2-BMC settings written by APE firmware. */ 2441 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2442 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2443 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2444 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2445 } 2446 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2447 BGE_MODECTL_TX_NO_PHDR_CSUM; 2448 2449 /* 2450 * BCM5701 B5 have a bug causing data corruption when using 2451 * 64-bit DMA reads, which can be terminated early and then 2452 * completed later as 32-bit accesses, in combination with 2453 * certain bridges. 2454 */ 2455 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2456 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2457 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2458 2459 /* 2460 * Tell the firmware the driver is running 2461 */ 2462 if (sc->bge_asf_mode & ASF_STACKUP) 2463 mode_ctl |= BGE_MODECTL_STACKUP; 2464 2465 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2466 2467 /* 2468 * Disable memory write invalidate. Apparently it is not supported 2469 * properly by these devices. 2470 */ 2471 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2472 PCI_COMMAND_INVALIDATE_ENABLE); 2473 2474 #ifdef __brokenalpha__ 2475 /* 2476 * Must insure that we do not cross an 8K (bytes) boundary 2477 * for DMA reads. Our highest limit is 1K bytes. This is a 2478 * restriction on some ALPHA platforms with early revision 2479 * 21174 PCI chipsets, such as the AlphaPC 164lx 2480 */ 2481 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2482 #endif 2483 2484 /* Set the timer prescaler (always 66MHz) */ 2485 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2486 2487 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2488 DELAY(40); /* XXX */ 2489 2490 /* Put PHY into ready state */ 2491 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2492 DELAY(40); 2493 } 2494 2495 return 0; 2496 } 2497 2498 static int 2499 bge_blockinit(struct bge_softc *sc) 2500 { 2501 volatile struct bge_rcb *rcb; 2502 bus_size_t rcb_addr; 2503 struct ifnet *ifp = &sc->ethercom.ec_if; 2504 bge_hostaddr taddr; 2505 uint32_t dmactl, mimode, val; 2506 int i, limit; 2507 2508 /* 2509 * Initialize the memory window pointer register so that 2510 * we can access the first 32K of internal NIC RAM. This will 2511 * allow us to set up the TX send ring RCBs and the RX return 2512 * ring RCBs, plus other things which live in NIC memory. 2513 */ 2514 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2515 2516 if (!BGE_IS_5705_PLUS(sc)) { 2517 /* 57XX step 33 */ 2518 /* Configure mbuf memory pool */ 2519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2520 BGE_BUFFPOOL_1); 2521 2522 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2523 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2524 else 2525 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2526 2527 /* 57XX step 34 */ 2528 /* Configure DMA resource pool */ 2529 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2530 BGE_DMA_DESCRIPTORS); 2531 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2532 } 2533 2534 /* 5718 step 11, 57XX step 35 */ 2535 /* 2536 * Configure mbuf pool watermarks. New broadcom docs strongly 2537 * recommend these. 2538 */ 2539 if (BGE_IS_5717_PLUS(sc)) { 2540 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2541 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2542 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2543 } else if (BGE_IS_5705_PLUS(sc)) { 2544 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2545 2546 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2547 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2548 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2549 } else { 2550 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2551 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2552 } 2553 } else { 2554 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2555 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2556 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2557 } 2558 2559 /* 57XX step 36 */ 2560 /* Configure DMA resource watermarks */ 2561 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2562 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2563 2564 /* 5718 step 13, 57XX step 38 */ 2565 /* Enable buffer manager */ 2566 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2567 /* 2568 * Change the arbitration algorithm of TXMBUF read request to 2569 * round-robin instead of priority based for BCM5719. When 2570 * TXFIFO is almost empty, RDMA will hold its request until 2571 * TXFIFO is not almost empty. 2572 */ 2573 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2574 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2575 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2576 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2577 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2578 val |= BGE_BMANMODE_LOMBUF_ATTN; 2579 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2580 2581 /* 57XX step 39 */ 2582 /* Poll for buffer manager start indication */ 2583 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2584 DELAY(10); 2585 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2586 break; 2587 } 2588 2589 if (i == BGE_TIMEOUT * 2) { 2590 aprint_error_dev(sc->bge_dev, 2591 "buffer manager failed to start\n"); 2592 return ENXIO; 2593 } 2594 2595 /* 57XX step 40 */ 2596 /* Enable flow-through queues */ 2597 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2598 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2599 2600 /* Wait until queue initialization is complete */ 2601 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2602 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2603 break; 2604 DELAY(10); 2605 } 2606 2607 if (i == BGE_TIMEOUT * 2) { 2608 aprint_error_dev(sc->bge_dev, 2609 "flow-through queue init failed\n"); 2610 return ENXIO; 2611 } 2612 2613 /* 2614 * Summary of rings supported by the controller: 2615 * 2616 * Standard Receive Producer Ring 2617 * - This ring is used to feed receive buffers for "standard" 2618 * sized frames (typically 1536 bytes) to the controller. 2619 * 2620 * Jumbo Receive Producer Ring 2621 * - This ring is used to feed receive buffers for jumbo sized 2622 * frames (i.e. anything bigger than the "standard" frames) 2623 * to the controller. 2624 * 2625 * Mini Receive Producer Ring 2626 * - This ring is used to feed receive buffers for "mini" 2627 * sized frames to the controller. 2628 * - This feature required external memory for the controller 2629 * but was never used in a production system. Should always 2630 * be disabled. 2631 * 2632 * Receive Return Ring 2633 * - After the controller has placed an incoming frame into a 2634 * receive buffer that buffer is moved into a receive return 2635 * ring. The driver is then responsible to passing the 2636 * buffer up to the stack. Many versions of the controller 2637 * support multiple RR rings. 2638 * 2639 * Send Ring 2640 * - This ring is used for outgoing frames. Many versions of 2641 * the controller support multiple send rings. 2642 */ 2643 2644 /* 5718 step 15, 57XX step 41 */ 2645 /* Initialize the standard RX ring control block */ 2646 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2647 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2648 /* 5718 step 16 */ 2649 if (BGE_IS_57765_PLUS(sc)) { 2650 /* 2651 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2652 * Bits 15-2 : Maximum RX frame size 2653 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2654 * Bit 0 : Reserved 2655 */ 2656 rcb->bge_maxlen_flags = 2657 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2658 } else if (BGE_IS_5705_PLUS(sc)) { 2659 /* 2660 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2661 * Bits 15-2 : Reserved (should be 0) 2662 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2663 * Bit 0 : Reserved 2664 */ 2665 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2666 } else { 2667 /* 2668 * Ring size is always XXX entries 2669 * Bits 31-16: Maximum RX frame size 2670 * Bits 15-2 : Reserved (should be 0) 2671 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2672 * Bit 0 : Reserved 2673 */ 2674 rcb->bge_maxlen_flags = 2675 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2676 } 2677 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2678 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2679 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2680 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2681 else 2682 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2683 /* Write the standard receive producer ring control block. */ 2684 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2685 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2686 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2687 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2688 2689 /* Reset the standard receive producer ring producer index. */ 2690 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2691 2692 /* 57XX step 42 */ 2693 /* 2694 * Initialize the jumbo RX ring control block 2695 * We set the 'ring disabled' bit in the flags 2696 * field until we're actually ready to start 2697 * using this ring (i.e. once we set the MTU 2698 * high enough to require it). 2699 */ 2700 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2701 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2702 BGE_HOSTADDR(rcb->bge_hostaddr, 2703 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2704 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2705 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2706 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2707 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2708 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2709 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2710 else 2711 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2712 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2713 rcb->bge_hostaddr.bge_addr_hi); 2714 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2715 rcb->bge_hostaddr.bge_addr_lo); 2716 /* Program the jumbo receive producer ring RCB parameters. */ 2717 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2718 rcb->bge_maxlen_flags); 2719 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2720 /* Reset the jumbo receive producer ring producer index. */ 2721 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2722 } 2723 2724 /* 57XX step 43 */ 2725 /* Disable the mini receive producer ring RCB. */ 2726 if (BGE_IS_5700_FAMILY(sc)) { 2727 /* Set up dummy disabled mini ring RCB */ 2728 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2729 rcb->bge_maxlen_flags = 2730 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2731 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2732 rcb->bge_maxlen_flags); 2733 /* Reset the mini receive producer ring producer index. */ 2734 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2735 2736 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2737 offsetof(struct bge_ring_data, bge_info), 2738 sizeof (struct bge_gib), 2739 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2740 } 2741 2742 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2743 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2744 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2745 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2746 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2747 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2748 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2749 } 2750 /* 5718 step 14, 57XX step 44 */ 2751 /* 2752 * The BD ring replenish thresholds control how often the 2753 * hardware fetches new BD's from the producer rings in host 2754 * memory. Setting the value too low on a busy system can 2755 * starve the hardware and recue the throughpout. 2756 * 2757 * Set the BD ring replenish thresholds. The recommended 2758 * values are 1/8th the number of descriptors allocated to 2759 * each ring, but since we try to avoid filling the entire 2760 * ring we set these to the minimal value of 8. This needs to 2761 * be done on several of the supported chip revisions anyway, 2762 * to work around HW bugs. 2763 */ 2764 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2765 if (BGE_IS_JUMBO_CAPABLE(sc)) 2766 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2767 2768 /* 5718 step 18 */ 2769 if (BGE_IS_5717_PLUS(sc)) { 2770 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2771 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2772 } 2773 2774 /* 57XX step 45 */ 2775 /* 2776 * Disable all send rings by setting the 'ring disabled' bit 2777 * in the flags field of all the TX send ring control blocks, 2778 * located in NIC memory. 2779 */ 2780 if (BGE_IS_5700_FAMILY(sc)) { 2781 /* 5700 to 5704 had 16 send rings. */ 2782 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2783 } else if (BGE_IS_5717_PLUS(sc)) { 2784 limit = BGE_TX_RINGS_5717_MAX; 2785 } else if (BGE_IS_57765_FAMILY(sc)) { 2786 limit = BGE_TX_RINGS_57765_MAX; 2787 } else 2788 limit = 1; 2789 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2790 for (i = 0; i < limit; i++) { 2791 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2792 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2793 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2794 rcb_addr += sizeof(struct bge_rcb); 2795 } 2796 2797 /* 57XX step 46 and 47 */ 2798 /* Configure send ring RCB 0 (we use only the first ring) */ 2799 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2800 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2801 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2802 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2803 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2804 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2805 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2806 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2807 else 2808 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2809 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2810 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2811 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2812 2813 /* 57XX step 48 */ 2814 /* 2815 * Disable all receive return rings by setting the 2816 * 'ring diabled' bit in the flags field of all the receive 2817 * return ring control blocks, located in NIC memory. 2818 */ 2819 if (BGE_IS_5717_PLUS(sc)) { 2820 /* Should be 17, use 16 until we get an SRAM map. */ 2821 limit = 16; 2822 } else if (BGE_IS_5700_FAMILY(sc)) 2823 limit = BGE_RX_RINGS_MAX; 2824 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2825 BGE_IS_57765_FAMILY(sc)) 2826 limit = 4; 2827 else 2828 limit = 1; 2829 /* Disable all receive return rings */ 2830 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2831 for (i = 0; i < limit; i++) { 2832 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2833 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2834 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2835 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2836 BGE_RCB_FLAG_RING_DISABLED)); 2837 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2838 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2839 (i * (sizeof(uint64_t))), 0); 2840 rcb_addr += sizeof(struct bge_rcb); 2841 } 2842 2843 /* 57XX step 49 */ 2844 /* 2845 * Set up receive return ring 0. Note that the NIC address 2846 * for RX return rings is 0x0. The return rings live entirely 2847 * within the host, so the nicaddr field in the RCB isn't used. 2848 */ 2849 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2850 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2851 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2852 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2853 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2854 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2855 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2856 2857 /* 5718 step 24, 57XX step 53 */ 2858 /* Set random backoff seed for TX */ 2859 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2860 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2861 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2862 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2863 BGE_TX_BACKOFF_SEED_MASK); 2864 2865 /* 5718 step 26, 57XX step 55 */ 2866 /* Set inter-packet gap */ 2867 val = 0x2620; 2868 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2869 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2870 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2871 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2872 2873 /* 5718 step 27, 57XX step 56 */ 2874 /* 2875 * Specify which ring to use for packets that don't match 2876 * any RX rules. 2877 */ 2878 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2879 2880 /* 5718 step 28, 57XX step 57 */ 2881 /* 2882 * Configure number of RX lists. One interrupt distribution 2883 * list, sixteen active lists, one bad frames class. 2884 */ 2885 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2886 2887 /* 5718 step 29, 57XX step 58 */ 2888 /* Inialize RX list placement stats mask. */ 2889 if (BGE_IS_575X_PLUS(sc)) { 2890 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2891 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2892 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2893 } else 2894 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2895 2896 /* 5718 step 30, 57XX step 59 */ 2897 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2898 2899 /* 5718 step 33, 57XX step 62 */ 2900 /* Disable host coalescing until we get it set up */ 2901 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2902 2903 /* 5718 step 34, 57XX step 63 */ 2904 /* Poll to make sure it's shut down. */ 2905 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2906 DELAY(10); 2907 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2908 break; 2909 } 2910 2911 if (i == BGE_TIMEOUT * 2) { 2912 aprint_error_dev(sc->bge_dev, 2913 "host coalescing engine failed to idle\n"); 2914 return ENXIO; 2915 } 2916 2917 /* 5718 step 35, 36, 37 */ 2918 /* Set up host coalescing defaults */ 2919 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2920 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2921 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2922 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2923 if (!(BGE_IS_5705_PLUS(sc))) { 2924 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2925 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2926 } 2927 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2928 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2929 2930 /* Set up address of statistics block */ 2931 if (BGE_IS_5700_FAMILY(sc)) { 2932 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2933 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2934 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2935 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2936 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2937 } 2938 2939 /* 5718 step 38 */ 2940 /* Set up address of status block */ 2941 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2942 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2943 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2944 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2945 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2946 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2947 2948 /* Set up status block size. */ 2949 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2950 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2951 val = BGE_STATBLKSZ_FULL; 2952 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2953 } else { 2954 val = BGE_STATBLKSZ_32BYTE; 2955 bzero(&sc->bge_rdata->bge_status_block, 32); 2956 } 2957 2958 /* 5718 step 39, 57XX step 73 */ 2959 /* Turn on host coalescing state machine */ 2960 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2961 2962 /* 5718 step 40, 57XX step 74 */ 2963 /* Turn on RX BD completion state machine and enable attentions */ 2964 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2965 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2966 2967 /* 5718 step 41, 57XX step 75 */ 2968 /* Turn on RX list placement state machine */ 2969 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2970 2971 /* 57XX step 76 */ 2972 /* Turn on RX list selector state machine. */ 2973 if (!(BGE_IS_5705_PLUS(sc))) 2974 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2975 2976 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2977 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2978 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2979 BGE_MACMODE_FRMHDR_DMA_ENB; 2980 2981 if (sc->bge_flags & BGEF_FIBER_TBI) 2982 val |= BGE_PORTMODE_TBI; 2983 else if (sc->bge_flags & BGEF_FIBER_MII) 2984 val |= BGE_PORTMODE_GMII; 2985 else 2986 val |= BGE_PORTMODE_MII; 2987 2988 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2989 /* Allow APE to send/receive frames. */ 2990 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2991 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2992 2993 /* Turn on DMA, clear stats */ 2994 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2995 /* 5718 step 44 */ 2996 DELAY(40); 2997 2998 /* 5718 step 45, 57XX step 79 */ 2999 /* Set misc. local control, enable interrupts on attentions */ 3000 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3001 if (BGE_IS_5717_PLUS(sc)) { 3002 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3003 /* 5718 step 46 */ 3004 DELAY(100); 3005 } 3006 3007 /* 57XX step 81 */ 3008 /* Turn on DMA completion state machine */ 3009 if (!(BGE_IS_5705_PLUS(sc))) 3010 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3011 3012 /* 5718 step 47, 57XX step 82 */ 3013 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3014 3015 /* 5718 step 48 */ 3016 /* Enable host coalescing bug fix. */ 3017 if (BGE_IS_5755_PLUS(sc)) 3018 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3019 3020 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3021 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3022 3023 /* Turn on write DMA state machine */ 3024 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3025 /* 5718 step 49 */ 3026 DELAY(40); 3027 3028 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3029 3030 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3031 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3032 3033 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3034 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3035 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3036 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3037 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3038 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3039 3040 if (sc->bge_flags & BGEF_PCIE) 3041 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3042 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3043 if (ifp->if_mtu <= ETHERMTU) 3044 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3045 } 3046 if (sc->bge_flags & BGEF_TSO) 3047 val |= BGE_RDMAMODE_TSO4_ENABLE; 3048 3049 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3050 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3051 BGE_RDMAMODE_H2BNC_VLAN_DET; 3052 /* 3053 * Allow multiple outstanding read requests from 3054 * non-LSO read DMA engine. 3055 */ 3056 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3057 } 3058 3059 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3060 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3061 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3062 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3063 BGE_IS_57765_PLUS(sc)) { 3064 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3065 /* 3066 * Adjust tx margin to prevent TX data corruption and 3067 * fix internal FIFO overflow. 3068 */ 3069 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3070 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3071 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3072 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3073 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3074 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3075 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3076 } 3077 /* 3078 * Enable fix for read DMA FIFO overruns. 3079 * The fix is to limit the number of RX BDs 3080 * the hardware would fetch at a fime. 3081 */ 3082 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3083 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3084 } 3085 3086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3087 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3088 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3089 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3090 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3091 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3092 /* 3093 * Allow 4KB burst length reads for non-LSO frames. 3094 * Enable 512B burst length reads for buffer descriptors. 3095 */ 3096 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3097 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3098 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3099 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3100 } 3101 3102 /* Turn on read DMA state machine */ 3103 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3104 /* 5718 step 52 */ 3105 delay(40); 3106 3107 /* 5718 step 56, 57XX step 84 */ 3108 /* Turn on RX data completion state machine */ 3109 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3110 3111 /* Turn on RX data and RX BD initiator state machine */ 3112 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3113 3114 /* 57XX step 85 */ 3115 /* Turn on Mbuf cluster free state machine */ 3116 if (!BGE_IS_5705_PLUS(sc)) 3117 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3118 3119 /* 5718 step 57, 57XX step 86 */ 3120 /* Turn on send data completion state machine */ 3121 val = BGE_SDCMODE_ENABLE; 3122 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3123 val |= BGE_SDCMODE_CDELAY; 3124 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3125 3126 /* 5718 step 58 */ 3127 /* Turn on send BD completion state machine */ 3128 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3129 3130 /* 57XX step 88 */ 3131 /* Turn on RX BD initiator state machine */ 3132 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3133 3134 /* 5718 step 60, 57XX step 90 */ 3135 /* Turn on send data initiator state machine */ 3136 if (sc->bge_flags & BGEF_TSO) { 3137 /* XXX: magic value from Linux driver */ 3138 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3139 BGE_SDIMODE_HW_LSO_PRE_DMA); 3140 } else 3141 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3142 3143 /* 5718 step 61, 57XX step 91 */ 3144 /* Turn on send BD initiator state machine */ 3145 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3146 3147 /* 5718 step 62, 57XX step 92 */ 3148 /* Turn on send BD selector state machine */ 3149 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3150 3151 /* 5718 step 31, 57XX step 60 */ 3152 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3153 /* 5718 step 32, 57XX step 61 */ 3154 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3155 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3156 3157 /* ack/clear link change events */ 3158 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3159 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3160 BGE_MACSTAT_LINK_CHANGED); 3161 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3162 3163 /* 3164 * Enable attention when the link has changed state for 3165 * devices that use auto polling. 3166 */ 3167 if (sc->bge_flags & BGEF_FIBER_TBI) { 3168 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3169 } else { 3170 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3171 mimode = BGE_MIMODE_500KHZ_CONST; 3172 else 3173 mimode = BGE_MIMODE_BASE; 3174 /* 5718 step 68. 5718 step 69 (optionally). */ 3175 if (BGE_IS_5700_FAMILY(sc) || 3176 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3177 mimode |= BGE_MIMODE_AUTOPOLL; 3178 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3179 } 3180 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3181 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3182 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3183 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3184 BGE_EVTENB_MI_INTERRUPT); 3185 } 3186 3187 /* 3188 * Clear any pending link state attention. 3189 * Otherwise some link state change events may be lost until attention 3190 * is cleared by bge_intr() -> bge_link_upd() sequence. 3191 * It's not necessary on newer BCM chips - perhaps enabling link 3192 * state change attentions implies clearing pending attention. 3193 */ 3194 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3195 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3196 BGE_MACSTAT_LINK_CHANGED); 3197 3198 /* Enable link state change attentions. */ 3199 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3200 3201 return 0; 3202 } 3203 3204 static const struct bge_revision * 3205 bge_lookup_rev(uint32_t chipid) 3206 { 3207 const struct bge_revision *br; 3208 3209 for (br = bge_revisions; br->br_name != NULL; br++) { 3210 if (br->br_chipid == chipid) 3211 return br; 3212 } 3213 3214 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3215 if (br->br_chipid == BGE_ASICREV(chipid)) 3216 return br; 3217 } 3218 3219 return NULL; 3220 } 3221 3222 static const struct bge_product * 3223 bge_lookup(const struct pci_attach_args *pa) 3224 { 3225 const struct bge_product *bp; 3226 3227 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3228 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3229 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3230 return bp; 3231 } 3232 3233 return NULL; 3234 } 3235 3236 static uint32_t 3237 bge_chipid(const struct pci_attach_args *pa) 3238 { 3239 uint32_t id; 3240 3241 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3242 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3243 3244 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3245 switch (PCI_PRODUCT(pa->pa_id)) { 3246 case PCI_PRODUCT_BROADCOM_BCM5717: 3247 case PCI_PRODUCT_BROADCOM_BCM5718: 3248 case PCI_PRODUCT_BROADCOM_BCM5719: 3249 case PCI_PRODUCT_BROADCOM_BCM5720: 3250 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3251 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3252 BGE_PCI_GEN2_PRODID_ASICREV); 3253 break; 3254 case PCI_PRODUCT_BROADCOM_BCM57761: 3255 case PCI_PRODUCT_BROADCOM_BCM57762: 3256 case PCI_PRODUCT_BROADCOM_BCM57765: 3257 case PCI_PRODUCT_BROADCOM_BCM57766: 3258 case PCI_PRODUCT_BROADCOM_BCM57781: 3259 case PCI_PRODUCT_BROADCOM_BCM57785: 3260 case PCI_PRODUCT_BROADCOM_BCM57791: 3261 case PCI_PRODUCT_BROADCOM_BCM57795: 3262 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3263 BGE_PCI_GEN15_PRODID_ASICREV); 3264 break; 3265 default: 3266 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3267 BGE_PCI_PRODID_ASICREV); 3268 break; 3269 } 3270 } 3271 3272 return id; 3273 } 3274 3275 /* 3276 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3277 * against our list and return its name if we find a match. Note 3278 * that since the Broadcom controller contains VPD support, we 3279 * can get the device name string from the controller itself instead 3280 * of the compiled-in string. This is a little slow, but it guarantees 3281 * we'll always announce the right product name. 3282 */ 3283 static int 3284 bge_probe(device_t parent, cfdata_t match, void *aux) 3285 { 3286 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3287 3288 if (bge_lookup(pa) != NULL) 3289 return 1; 3290 3291 return 0; 3292 } 3293 3294 static void 3295 bge_attach(device_t parent, device_t self, void *aux) 3296 { 3297 struct bge_softc *sc = device_private(self); 3298 struct pci_attach_args *pa = aux; 3299 prop_dictionary_t dict; 3300 const struct bge_product *bp; 3301 const struct bge_revision *br; 3302 pci_chipset_tag_t pc; 3303 pci_intr_handle_t ih; 3304 const char *intrstr = NULL; 3305 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3306 uint32_t command; 3307 struct ifnet *ifp; 3308 uint32_t misccfg, mimode; 3309 void * kva; 3310 u_char eaddr[ETHER_ADDR_LEN]; 3311 pcireg_t memtype, subid, reg; 3312 bus_addr_t memaddr; 3313 uint32_t pm_ctl; 3314 bool no_seeprom; 3315 int capmask; 3316 int mii_flags; 3317 int map_flags; 3318 char intrbuf[PCI_INTRSTR_LEN]; 3319 3320 bp = bge_lookup(pa); 3321 KASSERT(bp != NULL); 3322 3323 sc->sc_pc = pa->pa_pc; 3324 sc->sc_pcitag = pa->pa_tag; 3325 sc->bge_dev = self; 3326 3327 sc->bge_pa = *pa; 3328 pc = sc->sc_pc; 3329 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3330 3331 aprint_naive(": Ethernet controller\n"); 3332 aprint_normal(": %s\n", bp->bp_name); 3333 3334 /* 3335 * Map control/status registers. 3336 */ 3337 DPRINTFN(5, ("Map control/status regs\n")); 3338 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3339 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3340 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3341 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3342 3343 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3344 aprint_error_dev(sc->bge_dev, 3345 "failed to enable memory mapping!\n"); 3346 return; 3347 } 3348 3349 DPRINTFN(5, ("pci_mem_find\n")); 3350 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3351 switch (memtype) { 3352 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3353 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3354 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3355 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3356 &memaddr, &sc->bge_bsize) == 0) 3357 break; 3358 default: 3359 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3360 return; 3361 } 3362 3363 DPRINTFN(5, ("pci_intr_map\n")); 3364 if (pci_intr_map(pa, &ih)) { 3365 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3366 return; 3367 } 3368 3369 DPRINTFN(5, ("pci_intr_string\n")); 3370 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 3371 3372 DPRINTFN(5, ("pci_intr_establish\n")); 3373 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3374 3375 if (sc->bge_intrhand == NULL) { 3376 aprint_error_dev(sc->bge_dev, 3377 "couldn't establish interrupt%s%s\n", 3378 intrstr ? " at " : "", intrstr ? intrstr : ""); 3379 return; 3380 } 3381 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3382 3383 /* Save various chip information. */ 3384 sc->bge_chipid = bge_chipid(pa); 3385 sc->bge_phy_addr = bge_phy_addr(sc); 3386 3387 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3388 &sc->bge_pciecap, NULL) != 0) 3389 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3390 /* PCIe */ 3391 sc->bge_flags |= BGEF_PCIE; 3392 /* Extract supported maximum payload size. */ 3393 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3394 sc->bge_pciecap + PCIE_DCAP); 3395 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3396 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3397 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3398 sc->bge_expmrq = 2048; 3399 else 3400 sc->bge_expmrq = 4096; 3401 bge_set_max_readrq(sc); 3402 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3403 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3404 /* PCI-X */ 3405 sc->bge_flags |= BGEF_PCIX; 3406 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3407 &sc->bge_pcixcap, NULL) == 0) 3408 aprint_error_dev(sc->bge_dev, 3409 "unable to find PCIX capability\n"); 3410 } 3411 3412 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3413 /* 3414 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3415 * can clobber the chip's PCI config-space power control 3416 * registers, leaving the card in D3 powersave state. We do 3417 * not have memory-mapped registers in this state, so force 3418 * device into D0 state before starting initialization. 3419 */ 3420 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3421 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3422 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3423 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3424 DELAY(1000); /* 27 usec is allegedly sufficent */ 3425 } 3426 3427 /* Save chipset family. */ 3428 switch (BGE_ASICREV(sc->bge_chipid)) { 3429 case BGE_ASICREV_BCM5717: 3430 case BGE_ASICREV_BCM5719: 3431 case BGE_ASICREV_BCM5720: 3432 sc->bge_flags |= BGEF_5717_PLUS; 3433 /* FALLTHROUGH */ 3434 case BGE_ASICREV_BCM57765: 3435 case BGE_ASICREV_BCM57766: 3436 if (!BGE_IS_5717_PLUS(sc)) 3437 sc->bge_flags |= BGEF_57765_FAMILY; 3438 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3439 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3440 /* Jumbo frame on BCM5719 A0 does not work. */ 3441 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3442 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3443 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3444 break; 3445 case BGE_ASICREV_BCM5755: 3446 case BGE_ASICREV_BCM5761: 3447 case BGE_ASICREV_BCM5784: 3448 case BGE_ASICREV_BCM5785: 3449 case BGE_ASICREV_BCM5787: 3450 case BGE_ASICREV_BCM57780: 3451 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3452 break; 3453 case BGE_ASICREV_BCM5700: 3454 case BGE_ASICREV_BCM5701: 3455 case BGE_ASICREV_BCM5703: 3456 case BGE_ASICREV_BCM5704: 3457 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3458 break; 3459 case BGE_ASICREV_BCM5714_A0: 3460 case BGE_ASICREV_BCM5780: 3461 case BGE_ASICREV_BCM5714: 3462 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3463 /* FALLTHROUGH */ 3464 case BGE_ASICREV_BCM5750: 3465 case BGE_ASICREV_BCM5752: 3466 case BGE_ASICREV_BCM5906: 3467 sc->bge_flags |= BGEF_575X_PLUS; 3468 /* FALLTHROUGH */ 3469 case BGE_ASICREV_BCM5705: 3470 sc->bge_flags |= BGEF_5705_PLUS; 3471 break; 3472 } 3473 3474 /* Identify chips with APE processor. */ 3475 switch (BGE_ASICREV(sc->bge_chipid)) { 3476 case BGE_ASICREV_BCM5717: 3477 case BGE_ASICREV_BCM5719: 3478 case BGE_ASICREV_BCM5720: 3479 case BGE_ASICREV_BCM5761: 3480 sc->bge_flags |= BGEF_APE; 3481 break; 3482 } 3483 3484 /* 3485 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3486 * not actually a MAC controller bug but an issue with the embedded 3487 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3488 */ 3489 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3490 sc->bge_flags |= BGEF_40BIT_BUG; 3491 3492 /* Chips with APE need BAR2 access for APE registers/memory. */ 3493 if ((sc->bge_flags & BGEF_APE) != 0) { 3494 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3495 #if 0 3496 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3497 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3498 &sc->bge_apesize)) { 3499 aprint_error_dev(sc->bge_dev, 3500 "couldn't map BAR2 memory\n"); 3501 return; 3502 } 3503 #else 3504 /* 3505 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3506 * system get NMI on boot (PR#48451). This problem might not be 3507 * the driver's bug but our PCI common part's bug. Until we 3508 * find a real reason, we ignore the prefetchable bit. 3509 */ 3510 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3511 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3512 aprint_error_dev(sc->bge_dev, 3513 "couldn't map BAR2 memory\n"); 3514 return; 3515 } 3516 3517 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3518 if (bus_space_map(pa->pa_memt, memaddr, 3519 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3520 aprint_error_dev(sc->bge_dev, 3521 "couldn't map BAR2 memory\n"); 3522 return; 3523 } 3524 sc->bge_apetag = pa->pa_memt; 3525 #endif 3526 3527 /* Enable APE register/memory access by host driver. */ 3528 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3529 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3530 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3531 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3532 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3533 3534 bge_ape_lock_init(sc); 3535 bge_ape_read_fw_ver(sc); 3536 } 3537 3538 /* Identify the chips that use an CPMU. */ 3539 if (BGE_IS_5717_PLUS(sc) || 3540 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3541 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3542 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3543 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3544 sc->bge_flags |= BGEF_CPMU_PRESENT; 3545 3546 /* Set MI_MODE */ 3547 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3548 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3549 mimode |= BGE_MIMODE_500KHZ_CONST; 3550 else 3551 mimode |= BGE_MIMODE_BASE; 3552 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3553 3554 /* 3555 * When using the BCM5701 in PCI-X mode, data corruption has 3556 * been observed in the first few bytes of some received packets. 3557 * Aligning the packet buffer in memory eliminates the corruption. 3558 * Unfortunately, this misaligns the packet payloads. On platforms 3559 * which do not support unaligned accesses, we will realign the 3560 * payloads by copying the received packets. 3561 */ 3562 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3563 sc->bge_flags & BGEF_PCIX) 3564 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3565 3566 if (BGE_IS_5700_FAMILY(sc)) 3567 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3568 3569 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3570 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3571 3572 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3573 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3574 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3575 sc->bge_flags |= BGEF_IS_5788; 3576 3577 /* 3578 * Some controllers seem to require a special firmware to use 3579 * TSO. But the firmware is not available to FreeBSD and Linux 3580 * claims that the TSO performed by the firmware is slower than 3581 * hardware based TSO. Moreover the firmware based TSO has one 3582 * known bug which can't handle TSO if ethernet header + IP/TCP 3583 * header is greater than 80 bytes. The workaround for the TSO 3584 * bug exist but it seems it's too expensive than not using 3585 * TSO at all. Some hardwares also have the TSO bug so limit 3586 * the TSO to the controllers that are not affected TSO issues 3587 * (e.g. 5755 or higher). 3588 */ 3589 if (BGE_IS_5755_PLUS(sc)) { 3590 /* 3591 * BCM5754 and BCM5787 shares the same ASIC id so 3592 * explicit device id check is required. 3593 */ 3594 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3595 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3596 sc->bge_flags |= BGEF_TSO; 3597 } 3598 3599 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3600 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3601 (misccfg == 0x4000 || misccfg == 0x8000)) || 3602 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3603 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3604 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3605 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3606 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3607 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3608 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3609 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3610 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3611 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3612 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3613 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3614 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3615 /* These chips are 10/100 only. */ 3616 capmask &= ~BMSR_EXTSTAT; 3617 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3618 } 3619 3620 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3621 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3622 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3623 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3624 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3625 3626 /* Set various PHY bug flags. */ 3627 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3628 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3629 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3630 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3631 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3632 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3633 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3634 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3635 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3636 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3637 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3638 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3639 if (BGE_IS_5705_PLUS(sc) && 3640 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3641 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3642 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3643 !BGE_IS_57765_PLUS(sc)) { 3644 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3646 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3647 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3648 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3649 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3650 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3651 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3652 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3653 } else 3654 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3655 } 3656 3657 /* 3658 * SEEPROM check. 3659 * First check if firmware knows we do not have SEEPROM. 3660 */ 3661 if (prop_dictionary_get_bool(device_properties(self), 3662 "without-seeprom", &no_seeprom) && no_seeprom) 3663 sc->bge_flags |= BGEF_NO_EEPROM; 3664 3665 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3666 sc->bge_flags |= BGEF_NO_EEPROM; 3667 3668 /* Now check the 'ROM failed' bit on the RX CPU */ 3669 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3670 sc->bge_flags |= BGEF_NO_EEPROM; 3671 3672 sc->bge_asf_mode = 0; 3673 /* No ASF if APE present. */ 3674 if ((sc->bge_flags & BGEF_APE) == 0) { 3675 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3676 BGE_SRAM_DATA_SIG_MAGIC)) { 3677 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3678 BGE_HWCFG_ASF) { 3679 sc->bge_asf_mode |= ASF_ENABLE; 3680 sc->bge_asf_mode |= ASF_STACKUP; 3681 if (BGE_IS_575X_PLUS(sc)) 3682 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3683 } 3684 } 3685 } 3686 3687 /* 3688 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3689 * lock in bge_reset(). 3690 */ 3691 CSR_WRITE_4(sc, BGE_EE_ADDR, 3692 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3693 delay(1000); 3694 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3695 3696 bge_stop_fw(sc); 3697 bge_sig_pre_reset(sc, BGE_RESET_START); 3698 if (bge_reset(sc)) 3699 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3700 3701 /* 3702 * Read the hardware config word in the first 32k of NIC internal 3703 * memory, or fall back to the config word in the EEPROM. 3704 * Note: on some BCM5700 cards, this value appears to be unset. 3705 */ 3706 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3707 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3708 BGE_SRAM_DATA_SIG_MAGIC) { 3709 uint32_t tmp; 3710 3711 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3712 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3713 BGE_SRAM_DATA_VER_SHIFT; 3714 if ((0 < tmp) && (tmp < 0x100)) 3715 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3716 if (sc->bge_flags & BGEF_PCIE) 3717 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3718 if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) 3719 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3720 if (BGE_IS_5717_PLUS(sc)) 3721 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3722 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3723 bge_read_eeprom(sc, (void *)&hwcfg, 3724 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3725 hwcfg = be32toh(hwcfg); 3726 } 3727 aprint_normal_dev(sc->bge_dev, 3728 "HW config %08x, %08x, %08x, %08x %08x\n", 3729 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3730 3731 bge_sig_legacy(sc, BGE_RESET_START); 3732 bge_sig_post_reset(sc, BGE_RESET_START); 3733 3734 if (bge_chipinit(sc)) { 3735 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3736 bge_release_resources(sc); 3737 return; 3738 } 3739 3740 /* 3741 * Get station address from the EEPROM. 3742 */ 3743 if (bge_get_eaddr(sc, eaddr)) { 3744 aprint_error_dev(sc->bge_dev, 3745 "failed to read station address\n"); 3746 bge_release_resources(sc); 3747 return; 3748 } 3749 3750 br = bge_lookup_rev(sc->bge_chipid); 3751 3752 if (br == NULL) { 3753 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3754 sc->bge_chipid); 3755 } else { 3756 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3757 br->br_name, sc->bge_chipid); 3758 } 3759 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3760 3761 /* Allocate the general information block and ring buffers. */ 3762 if (pci_dma64_available(pa)) 3763 sc->bge_dmatag = pa->pa_dmat64; 3764 else 3765 sc->bge_dmatag = pa->pa_dmat; 3766 3767 /* 40bit DMA workaround */ 3768 if (sizeof(bus_addr_t) > 4) { 3769 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3770 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3771 3772 if (bus_dmatag_subregion(olddmatag, 0, 3773 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3774 BUS_DMA_NOWAIT) != 0) { 3775 aprint_error_dev(self, 3776 "WARNING: failed to restrict dma range," 3777 " falling back to parent bus dma range\n"); 3778 sc->bge_dmatag = olddmatag; 3779 } 3780 } 3781 } 3782 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3783 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3784 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3785 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3786 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3787 return; 3788 } 3789 DPRINTFN(5, ("bus_dmamem_map\n")); 3790 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3791 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3792 BUS_DMA_NOWAIT)) { 3793 aprint_error_dev(sc->bge_dev, 3794 "can't map DMA buffers (%zu bytes)\n", 3795 sizeof(struct bge_ring_data)); 3796 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3797 sc->bge_ring_rseg); 3798 return; 3799 } 3800 DPRINTFN(5, ("bus_dmamem_create\n")); 3801 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3802 sizeof(struct bge_ring_data), 0, 3803 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3804 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3805 bus_dmamem_unmap(sc->bge_dmatag, kva, 3806 sizeof(struct bge_ring_data)); 3807 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3808 sc->bge_ring_rseg); 3809 return; 3810 } 3811 DPRINTFN(5, ("bus_dmamem_load\n")); 3812 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3813 sizeof(struct bge_ring_data), NULL, 3814 BUS_DMA_NOWAIT)) { 3815 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3816 bus_dmamem_unmap(sc->bge_dmatag, kva, 3817 sizeof(struct bge_ring_data)); 3818 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3819 sc->bge_ring_rseg); 3820 return; 3821 } 3822 3823 DPRINTFN(5, ("bzero\n")); 3824 sc->bge_rdata = (struct bge_ring_data *)kva; 3825 3826 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3827 3828 /* Try to allocate memory for jumbo buffers. */ 3829 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3830 if (bge_alloc_jumbo_mem(sc)) { 3831 aprint_error_dev(sc->bge_dev, 3832 "jumbo buffer allocation failed\n"); 3833 } else 3834 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3835 } 3836 3837 /* Set default tuneable values. */ 3838 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3839 sc->bge_rx_coal_ticks = 150; 3840 sc->bge_rx_max_coal_bds = 64; 3841 sc->bge_tx_coal_ticks = 300; 3842 sc->bge_tx_max_coal_bds = 400; 3843 if (BGE_IS_5705_PLUS(sc)) { 3844 sc->bge_tx_coal_ticks = (12 * 5); 3845 sc->bge_tx_max_coal_bds = (12 * 5); 3846 aprint_verbose_dev(sc->bge_dev, 3847 "setting short Tx thresholds\n"); 3848 } 3849 3850 if (BGE_IS_5717_PLUS(sc)) 3851 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3852 else if (BGE_IS_5705_PLUS(sc)) 3853 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3854 else 3855 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3856 3857 /* Set up ifnet structure */ 3858 ifp = &sc->ethercom.ec_if; 3859 ifp->if_softc = sc; 3860 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3861 ifp->if_ioctl = bge_ioctl; 3862 ifp->if_stop = bge_stop; 3863 ifp->if_start = bge_start; 3864 ifp->if_init = bge_init; 3865 ifp->if_watchdog = bge_watchdog; 3866 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3867 IFQ_SET_READY(&ifp->if_snd); 3868 DPRINTFN(5, ("strcpy if_xname\n")); 3869 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3870 3871 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3872 sc->ethercom.ec_if.if_capabilities |= 3873 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3874 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3875 sc->ethercom.ec_if.if_capabilities |= 3876 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3877 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3878 #endif 3879 sc->ethercom.ec_capabilities |= 3880 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3881 3882 if (sc->bge_flags & BGEF_TSO) 3883 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3884 3885 /* 3886 * Do MII setup. 3887 */ 3888 DPRINTFN(5, ("mii setup\n")); 3889 sc->bge_mii.mii_ifp = ifp; 3890 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3891 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3892 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3893 3894 /* 3895 * Figure out what sort of media we have by checking the hardware 3896 * config word. Note: on some BCM5700 cards, this value appears to be 3897 * unset. If that's the case, we have to rely on identifying the NIC 3898 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3899 * The SysKonnect SK-9D41 is a 1000baseSX card. 3900 */ 3901 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3902 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3903 if (BGE_IS_5705_PLUS(sc)) { 3904 sc->bge_flags |= BGEF_FIBER_MII; 3905 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3906 } else 3907 sc->bge_flags |= BGEF_FIBER_TBI; 3908 } 3909 3910 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3911 if (BGE_IS_JUMBO_CAPABLE(sc)) 3912 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3913 3914 /* set phyflags and chipid before mii_attach() */ 3915 dict = device_properties(self); 3916 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3917 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3918 3919 if (sc->bge_flags & BGEF_FIBER_TBI) { 3920 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3921 bge_ifmedia_sts); 3922 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3923 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3924 0, NULL); 3925 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3926 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3927 /* Pretend the user requested this setting */ 3928 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3929 } else { 3930 /* 3931 * Do transceiver setup and tell the firmware the 3932 * driver is down so we can try to get access the 3933 * probe if ASF is running. Retry a couple of times 3934 * if we get a conflict with the ASF firmware accessing 3935 * the PHY. 3936 */ 3937 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3938 bge_asf_driver_up(sc); 3939 3940 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3941 bge_ifmedia_sts); 3942 mii_flags = MIIF_DOPAUSE; 3943 if (sc->bge_flags & BGEF_FIBER_MII) 3944 mii_flags |= MIIF_HAVEFIBER; 3945 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 3946 MII_OFFSET_ANY, mii_flags); 3947 3948 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3949 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3950 ifmedia_add(&sc->bge_mii.mii_media, 3951 IFM_ETHER|IFM_MANUAL, 0, NULL); 3952 ifmedia_set(&sc->bge_mii.mii_media, 3953 IFM_ETHER|IFM_MANUAL); 3954 } else 3955 ifmedia_set(&sc->bge_mii.mii_media, 3956 IFM_ETHER|IFM_AUTO); 3957 3958 /* 3959 * Now tell the firmware we are going up after probing the PHY 3960 */ 3961 if (sc->bge_asf_mode & ASF_STACKUP) 3962 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3963 } 3964 3965 /* 3966 * Call MI attach routine. 3967 */ 3968 DPRINTFN(5, ("if_attach\n")); 3969 if_attach(ifp); 3970 DPRINTFN(5, ("ether_ifattach\n")); 3971 ether_ifattach(ifp, eaddr); 3972 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3973 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3974 RND_TYPE_NET, 0); 3975 #ifdef BGE_EVENT_COUNTERS 3976 /* 3977 * Attach event counters. 3978 */ 3979 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3980 NULL, device_xname(sc->bge_dev), "intr"); 3981 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3982 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3983 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3984 NULL, device_xname(sc->bge_dev), "tx_xon"); 3985 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3986 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3987 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3988 NULL, device_xname(sc->bge_dev), "rx_xon"); 3989 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3990 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3991 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3992 NULL, device_xname(sc->bge_dev), "xoffentered"); 3993 #endif /* BGE_EVENT_COUNTERS */ 3994 DPRINTFN(5, ("callout_init\n")); 3995 callout_init(&sc->bge_timeout, 0); 3996 3997 if (pmf_device_register(self, NULL, NULL)) 3998 pmf_class_network_register(self, ifp); 3999 else 4000 aprint_error_dev(self, "couldn't establish power handler\n"); 4001 4002 bge_sysctl_init(sc); 4003 4004 #ifdef BGE_DEBUG 4005 bge_debug_info(sc); 4006 #endif 4007 } 4008 4009 /* 4010 * Stop all chip I/O so that the kernel's probe routines don't 4011 * get confused by errant DMAs when rebooting. 4012 */ 4013 static int 4014 bge_detach(device_t self, int flags __unused) 4015 { 4016 struct bge_softc *sc = device_private(self); 4017 struct ifnet *ifp = &sc->ethercom.ec_if; 4018 int s; 4019 4020 s = splnet(); 4021 /* Stop the interface. Callouts are stopped in it. */ 4022 bge_stop(ifp, 1); 4023 splx(s); 4024 4025 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4026 4027 /* Delete all remaining media. */ 4028 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4029 4030 ether_ifdetach(ifp); 4031 if_detach(ifp); 4032 4033 bge_release_resources(sc); 4034 4035 return 0; 4036 } 4037 4038 static void 4039 bge_release_resources(struct bge_softc *sc) 4040 { 4041 4042 /* Disestablish the interrupt handler */ 4043 if (sc->bge_intrhand != NULL) { 4044 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4045 sc->bge_intrhand = NULL; 4046 } 4047 4048 if (sc->bge_dmatag != NULL) { 4049 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4050 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4051 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4052 sizeof(struct bge_ring_data)); 4053 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 4054 } 4055 4056 /* Unmap the device registers */ 4057 if (sc->bge_bsize != 0) { 4058 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4059 sc->bge_bsize = 0; 4060 } 4061 4062 /* Unmap the APE registers */ 4063 if (sc->bge_apesize != 0) { 4064 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4065 sc->bge_apesize); 4066 sc->bge_apesize = 0; 4067 } 4068 } 4069 4070 static int 4071 bge_reset(struct bge_softc *sc) 4072 { 4073 uint32_t cachesize, command; 4074 uint32_t reset, mac_mode, mac_mode_mask; 4075 pcireg_t devctl, reg; 4076 int i, val; 4077 void (*write_op)(struct bge_softc *, int, int); 4078 4079 /* Make mask for BGE_MAC_MODE register. */ 4080 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4081 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4082 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4083 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4084 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4085 4086 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4087 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4088 if (sc->bge_flags & BGEF_PCIE) 4089 write_op = bge_writemem_direct; 4090 else 4091 write_op = bge_writemem_ind; 4092 } else 4093 write_op = bge_writereg_ind; 4094 4095 /* 57XX step 4 */ 4096 /* Acquire the NVM lock */ 4097 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4098 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4099 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4100 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4101 for (i = 0; i < 8000; i++) { 4102 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4103 BGE_NVRAMSWARB_GNT1) 4104 break; 4105 DELAY(20); 4106 } 4107 if (i == 8000) { 4108 printf("%s: NVRAM lock timedout!\n", 4109 device_xname(sc->bge_dev)); 4110 } 4111 } 4112 4113 /* Take APE lock when performing reset. */ 4114 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4115 4116 /* 57XX step 3 */ 4117 /* Save some important PCI state. */ 4118 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4119 /* 5718 reset step 3 */ 4120 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4121 4122 /* 5718 reset step 5, 57XX step 5b-5d */ 4123 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4124 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4125 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4126 4127 /* XXX ???: Disable fastboot on controllers that support it. */ 4128 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4129 BGE_IS_5755_PLUS(sc)) 4130 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4131 4132 /* 5718 reset step 2, 57XX step 6 */ 4133 /* 4134 * Write the magic number to SRAM at offset 0xB50. 4135 * When firmware finishes its initialization it will 4136 * write ~BGE_MAGIC_NUMBER to the same location. 4137 */ 4138 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4139 4140 /* 5718 reset step 6, 57XX step 7 */ 4141 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4142 /* 4143 * XXX: from FreeBSD/Linux; no documentation 4144 */ 4145 if (sc->bge_flags & BGEF_PCIE) { 4146 if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && 4147 !BGE_IS_57765_PLUS(sc) && 4148 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4149 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4150 /* PCI Express 1.0 system */ 4151 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4152 BGE_PHY_PCIE_SCRAM_MODE); 4153 } 4154 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4155 /* 4156 * Prevent PCI Express link training 4157 * during global reset. 4158 */ 4159 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4160 reset |= (1 << 29); 4161 } 4162 } 4163 4164 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4165 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4166 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4167 i | BGE_VCPU_STATUS_DRV_RESET); 4168 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4169 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4170 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4171 } 4172 4173 /* 4174 * Set GPHY Power Down Override to leave GPHY 4175 * powered up in D0 uninitialized. 4176 */ 4177 if (BGE_IS_5705_PLUS(sc) && 4178 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4179 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4180 4181 /* Issue global reset */ 4182 write_op(sc, BGE_MISC_CFG, reset); 4183 4184 /* 5718 reset step 7, 57XX step 8 */ 4185 if (sc->bge_flags & BGEF_PCIE) 4186 delay(100*1000); /* too big */ 4187 else 4188 delay(1000); 4189 4190 if (sc->bge_flags & BGEF_PCIE) { 4191 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4192 DELAY(500000); 4193 /* XXX: Magic Numbers */ 4194 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4195 BGE_PCI_UNKNOWN0); 4196 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4197 BGE_PCI_UNKNOWN0, 4198 reg | (1 << 15)); 4199 } 4200 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4201 sc->bge_pciecap + PCIE_DCSR); 4202 /* Clear enable no snoop and disable relaxed ordering. */ 4203 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4204 PCIE_DCSR_ENA_NO_SNOOP); 4205 4206 /* Set PCIE max payload size to 128 for older PCIe devices */ 4207 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4208 devctl &= ~(0x00e0); 4209 /* Clear device status register. Write 1b to clear */ 4210 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4211 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4212 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4213 sc->bge_pciecap + PCIE_DCSR, devctl); 4214 bge_set_max_readrq(sc); 4215 } 4216 4217 /* From Linux: dummy read to flush PCI posted writes */ 4218 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4219 4220 /* 4221 * Reset some of the PCI state that got zapped by reset 4222 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4223 * set, too. 4224 */ 4225 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4226 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4227 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4228 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4229 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4230 (sc->bge_flags & BGEF_PCIX) != 0) 4231 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4232 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4233 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4234 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4235 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4236 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4237 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4238 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4239 4240 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4241 if (sc->bge_flags & BGEF_PCIX) { 4242 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4243 + PCIX_CMD); 4244 /* Set max memory read byte count to 2K */ 4245 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4246 reg &= ~PCIX_CMD_BYTECNT_MASK; 4247 reg |= PCIX_CMD_BCNT_2048; 4248 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4249 /* 4250 * For 5704, set max outstanding split transaction 4251 * field to 0 (0 means it supports 1 request) 4252 */ 4253 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4254 | PCIX_CMD_BYTECNT_MASK); 4255 reg |= PCIX_CMD_BCNT_2048; 4256 } 4257 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4258 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4259 } 4260 4261 /* 5718 reset step 10, 57XX step 12 */ 4262 /* Enable memory arbiter. */ 4263 if (BGE_IS_5714_FAMILY(sc)) { 4264 val = CSR_READ_4(sc, BGE_MARB_MODE); 4265 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4266 } else 4267 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4268 4269 /* XXX 5721, 5751 and 5752 */ 4270 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4271 /* Step 19: */ 4272 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4273 /* Step 20: */ 4274 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4275 } 4276 4277 /* 5718 reset step 12, 57XX step 15 and 16 */ 4278 /* Fix up byte swapping */ 4279 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4280 4281 /* 5718 reset step 13, 57XX step 17 */ 4282 /* Poll until the firmware initialization is complete */ 4283 bge_poll_fw(sc); 4284 4285 /* 57XX step 21 */ 4286 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4287 pcireg_t msidata; 4288 4289 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4290 BGE_PCI_MSI_DATA); 4291 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4292 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4293 msidata); 4294 } 4295 4296 /* 57XX step 18 */ 4297 /* Write mac mode. */ 4298 val = CSR_READ_4(sc, BGE_MAC_MODE); 4299 /* Restore mac_mode_mask's bits using mac_mode */ 4300 val = (val & ~mac_mode_mask) | mac_mode; 4301 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4302 DELAY(40); 4303 4304 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4305 4306 /* 4307 * The 5704 in TBI mode apparently needs some special 4308 * adjustment to insure the SERDES drive level is set 4309 * to 1.2V. 4310 */ 4311 if (sc->bge_flags & BGEF_FIBER_TBI && 4312 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4313 uint32_t serdescfg; 4314 4315 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4316 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4317 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4318 } 4319 4320 if (sc->bge_flags & BGEF_PCIE && 4321 !BGE_IS_57765_PLUS(sc) && 4322 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4323 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4324 uint32_t v; 4325 4326 /* Enable PCI Express bug fix */ 4327 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4328 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4329 v | BGE_TLP_DATA_FIFO_PROTECT); 4330 } 4331 4332 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4333 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4334 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4335 4336 return 0; 4337 } 4338 4339 /* 4340 * Frame reception handling. This is called if there's a frame 4341 * on the receive return list. 4342 * 4343 * Note: we have to be able to handle two possibilities here: 4344 * 1) the frame is from the jumbo receive ring 4345 * 2) the frame is from the standard receive ring 4346 */ 4347 4348 static void 4349 bge_rxeof(struct bge_softc *sc) 4350 { 4351 struct ifnet *ifp; 4352 uint16_t rx_prod, rx_cons; 4353 int stdcnt = 0, jumbocnt = 0; 4354 bus_dmamap_t dmamap; 4355 bus_addr_t offset, toff; 4356 bus_size_t tlen; 4357 int tosync; 4358 4359 rx_cons = sc->bge_rx_saved_considx; 4360 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4361 4362 /* Nothing to do */ 4363 if (rx_cons == rx_prod) 4364 return; 4365 4366 ifp = &sc->ethercom.ec_if; 4367 4368 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4369 offsetof(struct bge_ring_data, bge_status_block), 4370 sizeof (struct bge_status_block), 4371 BUS_DMASYNC_POSTREAD); 4372 4373 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4374 tosync = rx_prod - rx_cons; 4375 4376 if (tosync != 0) 4377 rnd_add_uint32(&sc->rnd_source, tosync); 4378 4379 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4380 4381 if (tosync < 0) { 4382 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4383 sizeof (struct bge_rx_bd); 4384 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4385 toff, tlen, BUS_DMASYNC_POSTREAD); 4386 tosync = -tosync; 4387 } 4388 4389 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4390 offset, tosync * sizeof (struct bge_rx_bd), 4391 BUS_DMASYNC_POSTREAD); 4392 4393 while (rx_cons != rx_prod) { 4394 struct bge_rx_bd *cur_rx; 4395 uint32_t rxidx; 4396 struct mbuf *m = NULL; 4397 4398 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4399 4400 rxidx = cur_rx->bge_idx; 4401 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4402 4403 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4404 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4405 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4406 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4407 jumbocnt++; 4408 bus_dmamap_sync(sc->bge_dmatag, 4409 sc->bge_cdata.bge_rx_jumbo_map, 4410 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4411 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4412 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4413 ifp->if_ierrors++; 4414 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4415 continue; 4416 } 4417 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4418 NULL)== ENOBUFS) { 4419 ifp->if_ierrors++; 4420 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4421 continue; 4422 } 4423 } else { 4424 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4425 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4426 4427 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4428 stdcnt++; 4429 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4430 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4431 if (dmamap == NULL) { 4432 ifp->if_ierrors++; 4433 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4434 continue; 4435 } 4436 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4437 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4438 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4439 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4440 ifp->if_ierrors++; 4441 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4442 continue; 4443 } 4444 if (bge_newbuf_std(sc, sc->bge_std, 4445 NULL, dmamap) == ENOBUFS) { 4446 ifp->if_ierrors++; 4447 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4448 continue; 4449 } 4450 } 4451 4452 ifp->if_ipackets++; 4453 #ifndef __NO_STRICT_ALIGNMENT 4454 /* 4455 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4456 * the Rx buffer has the layer-2 header unaligned. 4457 * If our CPU requires alignment, re-align by copying. 4458 */ 4459 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4460 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4461 cur_rx->bge_len); 4462 m->m_data += ETHER_ALIGN; 4463 } 4464 #endif 4465 4466 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4467 m->m_pkthdr.rcvif = ifp; 4468 4469 /* 4470 * Handle BPF listeners. Let the BPF user see the packet. 4471 */ 4472 bpf_mtap(ifp, m); 4473 4474 bge_rxcsum(sc, cur_rx, m); 4475 4476 /* 4477 * If we received a packet with a vlan tag, pass it 4478 * to vlan_input() instead of ether_input(). 4479 */ 4480 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4481 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4482 } 4483 4484 (*ifp->if_input)(ifp, m); 4485 } 4486 4487 sc->bge_rx_saved_considx = rx_cons; 4488 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4489 if (stdcnt) 4490 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4491 if (jumbocnt) 4492 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4493 } 4494 4495 static void 4496 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4497 { 4498 4499 if (BGE_IS_57765_PLUS(sc)) { 4500 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4501 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4502 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4503 if ((cur_rx->bge_error_flag & 4504 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4505 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4506 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4507 m->m_pkthdr.csum_data = 4508 cur_rx->bge_tcp_udp_csum; 4509 m->m_pkthdr.csum_flags |= 4510 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4511 M_CSUM_DATA); 4512 } 4513 } 4514 } else { 4515 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4516 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4517 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4518 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4519 /* 4520 * Rx transport checksum-offload may also 4521 * have bugs with packets which, when transmitted, 4522 * were `runts' requiring padding. 4523 */ 4524 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4525 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4526 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4527 m->m_pkthdr.csum_data = 4528 cur_rx->bge_tcp_udp_csum; 4529 m->m_pkthdr.csum_flags |= 4530 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4531 M_CSUM_DATA); 4532 } 4533 } 4534 } 4535 4536 static void 4537 bge_txeof(struct bge_softc *sc) 4538 { 4539 struct bge_tx_bd *cur_tx = NULL; 4540 struct ifnet *ifp; 4541 struct txdmamap_pool_entry *dma; 4542 bus_addr_t offset, toff; 4543 bus_size_t tlen; 4544 int tosync; 4545 struct mbuf *m; 4546 4547 ifp = &sc->ethercom.ec_if; 4548 4549 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4550 offsetof(struct bge_ring_data, bge_status_block), 4551 sizeof (struct bge_status_block), 4552 BUS_DMASYNC_POSTREAD); 4553 4554 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4555 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4556 sc->bge_tx_saved_considx; 4557 4558 if (tosync != 0) 4559 rnd_add_uint32(&sc->rnd_source, tosync); 4560 4561 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4562 4563 if (tosync < 0) { 4564 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4565 sizeof (struct bge_tx_bd); 4566 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4567 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4568 tosync = -tosync; 4569 } 4570 4571 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4572 offset, tosync * sizeof (struct bge_tx_bd), 4573 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4574 4575 /* 4576 * Go through our tx ring and free mbufs for those 4577 * frames that have been sent. 4578 */ 4579 while (sc->bge_tx_saved_considx != 4580 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4581 uint32_t idx = 0; 4582 4583 idx = sc->bge_tx_saved_considx; 4584 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4585 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4586 ifp->if_opackets++; 4587 m = sc->bge_cdata.bge_tx_chain[idx]; 4588 if (m != NULL) { 4589 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4590 dma = sc->txdma[idx]; 4591 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4592 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4593 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4594 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4595 sc->txdma[idx] = NULL; 4596 4597 m_freem(m); 4598 } 4599 sc->bge_txcnt--; 4600 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4601 ifp->if_timer = 0; 4602 } 4603 4604 if (cur_tx != NULL) 4605 ifp->if_flags &= ~IFF_OACTIVE; 4606 } 4607 4608 static int 4609 bge_intr(void *xsc) 4610 { 4611 struct bge_softc *sc; 4612 struct ifnet *ifp; 4613 uint32_t statusword; 4614 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4615 4616 sc = xsc; 4617 ifp = &sc->ethercom.ec_if; 4618 4619 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4620 if (BGE_IS_5717_PLUS(sc)) 4621 intrmask = 0; 4622 4623 /* It is possible for the interrupt to arrive before 4624 * the status block is updated prior to the interrupt. 4625 * Reading the PCI State register will confirm whether the 4626 * interrupt is ours and will flush the status block. 4627 */ 4628 4629 /* read status word from status block */ 4630 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4631 offsetof(struct bge_ring_data, bge_status_block), 4632 sizeof (struct bge_status_block), 4633 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4634 statusword = sc->bge_rdata->bge_status_block.bge_status; 4635 4636 if ((statusword & BGE_STATFLAG_UPDATED) || 4637 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) { 4638 /* Ack interrupt and stop others from occuring. */ 4639 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4640 4641 BGE_EVCNT_INCR(sc->bge_ev_intr); 4642 4643 /* clear status word */ 4644 sc->bge_rdata->bge_status_block.bge_status = 0; 4645 4646 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4647 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4648 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4649 bge_link_upd(sc); 4650 4651 if (ifp->if_flags & IFF_RUNNING) { 4652 /* Check RX return ring producer/consumer */ 4653 bge_rxeof(sc); 4654 4655 /* Check TX ring producer/consumer */ 4656 bge_txeof(sc); 4657 } 4658 4659 if (sc->bge_pending_rxintr_change) { 4660 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4661 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4662 4663 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4664 DELAY(10); 4665 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4666 4667 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4668 DELAY(10); 4669 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4670 4671 sc->bge_pending_rxintr_change = 0; 4672 } 4673 bge_handle_events(sc); 4674 4675 /* Re-enable interrupts. */ 4676 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4677 4678 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4679 bge_start(ifp); 4680 4681 return 1; 4682 } else 4683 return 0; 4684 } 4685 4686 static void 4687 bge_asf_driver_up(struct bge_softc *sc) 4688 { 4689 if (sc->bge_asf_mode & ASF_STACKUP) { 4690 /* Send ASF heartbeat aprox. every 2s */ 4691 if (sc->bge_asf_count) 4692 sc->bge_asf_count --; 4693 else { 4694 sc->bge_asf_count = 2; 4695 4696 bge_wait_for_event_ack(sc); 4697 4698 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4699 BGE_FW_CMD_DRV_ALIVE); 4700 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4701 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4702 BGE_FW_HB_TIMEOUT_SEC); 4703 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4704 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4705 BGE_RX_CPU_DRV_EVENT); 4706 } 4707 } 4708 } 4709 4710 static void 4711 bge_tick(void *xsc) 4712 { 4713 struct bge_softc *sc = xsc; 4714 struct mii_data *mii = &sc->bge_mii; 4715 int s; 4716 4717 s = splnet(); 4718 4719 if (BGE_IS_5705_PLUS(sc)) 4720 bge_stats_update_regs(sc); 4721 else 4722 bge_stats_update(sc); 4723 4724 if (sc->bge_flags & BGEF_FIBER_TBI) { 4725 /* 4726 * Since in TBI mode auto-polling can't be used we should poll 4727 * link status manually. Here we register pending link event 4728 * and trigger interrupt. 4729 */ 4730 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4731 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4732 } else { 4733 /* 4734 * Do not touch PHY if we have link up. This could break 4735 * IPMI/ASF mode or produce extra input errors. 4736 * (extra input errors was reported for bcm5701 & bcm5704). 4737 */ 4738 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4739 mii_tick(mii); 4740 } 4741 4742 bge_asf_driver_up(sc); 4743 4744 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4745 4746 splx(s); 4747 } 4748 4749 static void 4750 bge_stats_update_regs(struct bge_softc *sc) 4751 { 4752 struct ifnet *ifp = &sc->ethercom.ec_if; 4753 4754 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4755 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4756 4757 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4758 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4759 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4760 } 4761 4762 static void 4763 bge_stats_update(struct bge_softc *sc) 4764 { 4765 struct ifnet *ifp = &sc->ethercom.ec_if; 4766 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4767 4768 #define READ_STAT(sc, stats, stat) \ 4769 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4770 4771 ifp->if_collisions += 4772 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4773 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4774 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4775 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4776 ifp->if_collisions; 4777 4778 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4779 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4780 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4781 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4782 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4783 READ_STAT(sc, stats, 4784 xoffPauseFramesReceived.bge_addr_lo)); 4785 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4786 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4787 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4788 READ_STAT(sc, stats, 4789 macControlFramesReceived.bge_addr_lo)); 4790 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4791 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4792 4793 #undef READ_STAT 4794 4795 #ifdef notdef 4796 ifp->if_collisions += 4797 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4798 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4799 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4800 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4801 ifp->if_collisions; 4802 #endif 4803 } 4804 4805 /* 4806 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4807 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4808 * but when such padded frames employ the bge IP/TCP checksum offload, 4809 * the hardware checksum assist gives incorrect results (possibly 4810 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4811 * If we pad such runts with zeros, the onboard checksum comes out correct. 4812 */ 4813 static inline int 4814 bge_cksum_pad(struct mbuf *pkt) 4815 { 4816 struct mbuf *last = NULL; 4817 int padlen; 4818 4819 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4820 4821 /* if there's only the packet-header and we can pad there, use it. */ 4822 if (pkt->m_pkthdr.len == pkt->m_len && 4823 M_TRAILINGSPACE(pkt) >= padlen) { 4824 last = pkt; 4825 } else { 4826 /* 4827 * Walk packet chain to find last mbuf. We will either 4828 * pad there, or append a new mbuf and pad it 4829 * (thus perhaps avoiding the bcm5700 dma-min bug). 4830 */ 4831 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4832 continue; /* do nothing */ 4833 } 4834 4835 /* `last' now points to last in chain. */ 4836 if (M_TRAILINGSPACE(last) < padlen) { 4837 /* Allocate new empty mbuf, pad it. Compact later. */ 4838 struct mbuf *n; 4839 MGET(n, M_DONTWAIT, MT_DATA); 4840 if (n == NULL) 4841 return ENOBUFS; 4842 n->m_len = 0; 4843 last->m_next = n; 4844 last = n; 4845 } 4846 } 4847 4848 KDASSERT(!M_READONLY(last)); 4849 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4850 4851 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4852 memset(mtod(last, char *) + last->m_len, 0, padlen); 4853 last->m_len += padlen; 4854 pkt->m_pkthdr.len += padlen; 4855 return 0; 4856 } 4857 4858 /* 4859 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4860 */ 4861 static inline int 4862 bge_compact_dma_runt(struct mbuf *pkt) 4863 { 4864 struct mbuf *m, *prev; 4865 int totlen; 4866 4867 prev = NULL; 4868 totlen = 0; 4869 4870 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4871 int mlen = m->m_len; 4872 int shortfall = 8 - mlen ; 4873 4874 totlen += mlen; 4875 if (mlen == 0) 4876 continue; 4877 if (mlen >= 8) 4878 continue; 4879 4880 /* If we get here, mbuf data is too small for DMA engine. 4881 * Try to fix by shuffling data to prev or next in chain. 4882 * If that fails, do a compacting deep-copy of the whole chain. 4883 */ 4884 4885 /* Internal frag. If fits in prev, copy it there. */ 4886 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4887 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4888 prev->m_len += mlen; 4889 m->m_len = 0; 4890 /* XXX stitch chain */ 4891 prev->m_next = m_free(m); 4892 m = prev; 4893 continue; 4894 } 4895 else if (m->m_next != NULL && 4896 M_TRAILINGSPACE(m) >= shortfall && 4897 m->m_next->m_len >= (8 + shortfall)) { 4898 /* m is writable and have enough data in next, pull up. */ 4899 4900 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4901 shortfall); 4902 m->m_len += shortfall; 4903 m->m_next->m_len -= shortfall; 4904 m->m_next->m_data += shortfall; 4905 } 4906 else if (m->m_next == NULL || 1) { 4907 /* Got a runt at the very end of the packet. 4908 * borrow data from the tail of the preceding mbuf and 4909 * update its length in-place. (The original data is still 4910 * valid, so we can do this even if prev is not writable.) 4911 */ 4912 4913 /* if we'd make prev a runt, just move all of its data. */ 4914 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4915 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4916 4917 if ((prev->m_len - shortfall) < 8) 4918 shortfall = prev->m_len; 4919 4920 #ifdef notyet /* just do the safe slow thing for now */ 4921 if (!M_READONLY(m)) { 4922 if (M_LEADINGSPACE(m) < shorfall) { 4923 void *m_dat; 4924 m_dat = (m->m_flags & M_PKTHDR) ? 4925 m->m_pktdat : m->dat; 4926 memmove(m_dat, mtod(m, void*), m->m_len); 4927 m->m_data = m_dat; 4928 } 4929 } else 4930 #endif /* just do the safe slow thing */ 4931 { 4932 struct mbuf * n = NULL; 4933 int newprevlen = prev->m_len - shortfall; 4934 4935 MGET(n, M_NOWAIT, MT_DATA); 4936 if (n == NULL) 4937 return ENOBUFS; 4938 KASSERT(m->m_len + shortfall < MLEN 4939 /*, 4940 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4941 4942 /* first copy the data we're stealing from prev */ 4943 memcpy(n->m_data, prev->m_data + newprevlen, 4944 shortfall); 4945 4946 /* update prev->m_len accordingly */ 4947 prev->m_len -= shortfall; 4948 4949 /* copy data from runt m */ 4950 memcpy(n->m_data + shortfall, m->m_data, 4951 m->m_len); 4952 4953 /* n holds what we stole from prev, plus m */ 4954 n->m_len = shortfall + m->m_len; 4955 4956 /* stitch n into chain and free m */ 4957 n->m_next = m->m_next; 4958 prev->m_next = n; 4959 /* KASSERT(m->m_next == NULL); */ 4960 m->m_next = NULL; 4961 m_free(m); 4962 m = n; /* for continuing loop */ 4963 } 4964 } 4965 } 4966 return 0; 4967 } 4968 4969 /* 4970 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4971 * pointers to descriptors. 4972 */ 4973 static int 4974 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4975 { 4976 struct bge_tx_bd *f = NULL; 4977 uint32_t frag, cur; 4978 uint16_t csum_flags = 0; 4979 uint16_t txbd_tso_flags = 0; 4980 struct txdmamap_pool_entry *dma; 4981 bus_dmamap_t dmamap; 4982 int i = 0; 4983 struct m_tag *mtag; 4984 int use_tso, maxsegsize, error; 4985 4986 cur = frag = *txidx; 4987 4988 if (m_head->m_pkthdr.csum_flags) { 4989 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4990 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4991 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4992 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4993 } 4994 4995 /* 4996 * If we were asked to do an outboard checksum, and the NIC 4997 * has the bug where it sometimes adds in the Ethernet padding, 4998 * explicitly pad with zeros so the cksum will be correct either way. 4999 * (For now, do this for all chip versions, until newer 5000 * are confirmed to not require the workaround.) 5001 */ 5002 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5003 #ifdef notyet 5004 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5005 #endif 5006 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5007 goto check_dma_bug; 5008 5009 if (bge_cksum_pad(m_head) != 0) 5010 return ENOBUFS; 5011 5012 check_dma_bug: 5013 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5014 goto doit; 5015 5016 /* 5017 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5018 * less than eight bytes. If we encounter a teeny mbuf 5019 * at the end of a chain, we can pad. Otherwise, copy. 5020 */ 5021 if (bge_compact_dma_runt(m_head) != 0) 5022 return ENOBUFS; 5023 5024 doit: 5025 dma = SLIST_FIRST(&sc->txdma_list); 5026 if (dma == NULL) 5027 return ENOBUFS; 5028 dmamap = dma->dmamap; 5029 5030 /* 5031 * Set up any necessary TSO state before we start packing... 5032 */ 5033 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5034 if (!use_tso) { 5035 maxsegsize = 0; 5036 } else { /* TSO setup */ 5037 unsigned mss; 5038 struct ether_header *eh; 5039 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5040 struct mbuf * m0 = m_head; 5041 struct ip *ip; 5042 struct tcphdr *th; 5043 int iphl, hlen; 5044 5045 /* 5046 * XXX It would be nice if the mbuf pkthdr had offset 5047 * fields for the protocol headers. 5048 */ 5049 5050 eh = mtod(m0, struct ether_header *); 5051 switch (htons(eh->ether_type)) { 5052 case ETHERTYPE_IP: 5053 offset = ETHER_HDR_LEN; 5054 break; 5055 5056 case ETHERTYPE_VLAN: 5057 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5058 break; 5059 5060 default: 5061 /* 5062 * Don't support this protocol or encapsulation. 5063 */ 5064 return ENOBUFS; 5065 } 5066 5067 /* 5068 * TCP/IP headers are in the first mbuf; we can do 5069 * this the easy way. 5070 */ 5071 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5072 hlen = iphl + offset; 5073 if (__predict_false(m0->m_len < 5074 (hlen + sizeof(struct tcphdr)))) { 5075 5076 aprint_debug_dev(sc->bge_dev, 5077 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5078 "not handled yet\n", 5079 m0->m_len, hlen+ sizeof(struct tcphdr)); 5080 #ifdef NOTYET 5081 /* 5082 * XXX jonathan (at) NetBSD.org: untested. 5083 * how to force this branch to be taken? 5084 */ 5085 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5086 5087 m_copydata(m0, offset, sizeof(ip), &ip); 5088 m_copydata(m0, hlen, sizeof(th), &th); 5089 5090 ip.ip_len = 0; 5091 5092 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5093 sizeof(ip.ip_len), &ip.ip_len); 5094 5095 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5096 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5097 5098 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5099 sizeof(th.th_sum), &th.th_sum); 5100 5101 hlen += th.th_off << 2; 5102 iptcp_opt_words = hlen; 5103 #else 5104 /* 5105 * if_wm "hard" case not yet supported, can we not 5106 * mandate it out of existence? 5107 */ 5108 (void) ip; (void)th; (void) ip_tcp_hlen; 5109 5110 return ENOBUFS; 5111 #endif 5112 } else { 5113 ip = (struct ip *) (mtod(m0, char *) + offset); 5114 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5115 ip_tcp_hlen = iphl + (th->th_off << 2); 5116 5117 /* Total IP/TCP options, in 32-bit words */ 5118 iptcp_opt_words = (ip_tcp_hlen 5119 - sizeof(struct tcphdr) 5120 - sizeof(struct ip)) >> 2; 5121 } 5122 if (BGE_IS_575X_PLUS(sc)) { 5123 th->th_sum = 0; 5124 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5125 } else { 5126 /* 5127 * XXX jonathan (at) NetBSD.org: 5705 untested. 5128 * Requires TSO firmware patch for 5701/5703/5704. 5129 */ 5130 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5131 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5132 } 5133 5134 mss = m_head->m_pkthdr.segsz; 5135 txbd_tso_flags |= 5136 BGE_TXBDFLAG_CPU_PRE_DMA | 5137 BGE_TXBDFLAG_CPU_POST_DMA; 5138 5139 /* 5140 * Our NIC TSO-assist assumes TSO has standard, optionless 5141 * IPv4 and TCP headers, which total 40 bytes. By default, 5142 * the NIC copies 40 bytes of IP/TCP header from the 5143 * supplied header into the IP/TCP header portion of 5144 * each post-TSO-segment. If the supplied packet has IP or 5145 * TCP options, we need to tell the NIC to copy those extra 5146 * bytes into each post-TSO header, in addition to the normal 5147 * 40-byte IP/TCP header (and to leave space accordingly). 5148 * Unfortunately, the driver encoding of option length 5149 * varies across different ASIC families. 5150 */ 5151 tcp_seg_flags = 0; 5152 if (iptcp_opt_words) { 5153 if (BGE_IS_5705_PLUS(sc)) { 5154 tcp_seg_flags = 5155 iptcp_opt_words << 11; 5156 } else { 5157 txbd_tso_flags |= 5158 iptcp_opt_words << 12; 5159 } 5160 } 5161 maxsegsize = mss | tcp_seg_flags; 5162 ip->ip_len = htons(mss + ip_tcp_hlen); 5163 5164 } /* TSO setup */ 5165 5166 /* 5167 * Start packing the mbufs in this chain into 5168 * the fragment pointers. Stop when we run out 5169 * of fragments or hit the end of the mbuf chain. 5170 */ 5171 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5172 BUS_DMA_NOWAIT); 5173 if (error) 5174 return ENOBUFS; 5175 /* 5176 * Sanity check: avoid coming within 16 descriptors 5177 * of the end of the ring. 5178 */ 5179 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5180 BGE_TSO_PRINTF(("%s: " 5181 " dmamap_load_mbuf too close to ring wrap\n", 5182 device_xname(sc->bge_dev))); 5183 goto fail_unload; 5184 } 5185 5186 mtag = sc->ethercom.ec_nvlans ? 5187 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5188 5189 5190 /* Iterate over dmap-map fragments. */ 5191 for (i = 0; i < dmamap->dm_nsegs; i++) { 5192 f = &sc->bge_rdata->bge_tx_ring[frag]; 5193 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5194 break; 5195 5196 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5197 f->bge_len = dmamap->dm_segs[i].ds_len; 5198 5199 /* 5200 * For 5751 and follow-ons, for TSO we must turn 5201 * off checksum-assist flag in the tx-descr, and 5202 * supply the ASIC-revision-specific encoding 5203 * of TSO flags and segsize. 5204 */ 5205 if (use_tso) { 5206 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5207 f->bge_rsvd = maxsegsize; 5208 f->bge_flags = csum_flags | txbd_tso_flags; 5209 } else { 5210 f->bge_rsvd = 0; 5211 f->bge_flags = 5212 (csum_flags | txbd_tso_flags) & 0x0fff; 5213 } 5214 } else { 5215 f->bge_rsvd = 0; 5216 f->bge_flags = csum_flags; 5217 } 5218 5219 if (mtag != NULL) { 5220 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5221 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5222 } else { 5223 f->bge_vlan_tag = 0; 5224 } 5225 cur = frag; 5226 BGE_INC(frag, BGE_TX_RING_CNT); 5227 } 5228 5229 if (i < dmamap->dm_nsegs) { 5230 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5231 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5232 goto fail_unload; 5233 } 5234 5235 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5236 BUS_DMASYNC_PREWRITE); 5237 5238 if (frag == sc->bge_tx_saved_considx) { 5239 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5240 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5241 5242 goto fail_unload; 5243 } 5244 5245 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5246 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5247 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5248 sc->txdma[cur] = dma; 5249 sc->bge_txcnt += dmamap->dm_nsegs; 5250 5251 *txidx = frag; 5252 5253 return 0; 5254 5255 fail_unload: 5256 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5257 5258 return ENOBUFS; 5259 } 5260 5261 /* 5262 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5263 * to the mbuf data regions directly in the transmit descriptors. 5264 */ 5265 static void 5266 bge_start(struct ifnet *ifp) 5267 { 5268 struct bge_softc *sc; 5269 struct mbuf *m_head = NULL; 5270 uint32_t prodidx; 5271 int pkts = 0; 5272 5273 sc = ifp->if_softc; 5274 5275 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5276 return; 5277 5278 prodidx = sc->bge_tx_prodidx; 5279 5280 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5281 IFQ_POLL(&ifp->if_snd, m_head); 5282 if (m_head == NULL) 5283 break; 5284 5285 #if 0 5286 /* 5287 * XXX 5288 * safety overkill. If this is a fragmented packet chain 5289 * with delayed TCP/UDP checksums, then only encapsulate 5290 * it if we have enough descriptors to handle the entire 5291 * chain at once. 5292 * (paranoia -- may not actually be needed) 5293 */ 5294 if (m_head->m_flags & M_FIRSTFRAG && 5295 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5296 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5297 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5298 ifp->if_flags |= IFF_OACTIVE; 5299 break; 5300 } 5301 } 5302 #endif 5303 5304 /* 5305 * Pack the data into the transmit ring. If we 5306 * don't have room, set the OACTIVE flag and wait 5307 * for the NIC to drain the ring. 5308 */ 5309 if (bge_encap(sc, m_head, &prodidx)) { 5310 ifp->if_flags |= IFF_OACTIVE; 5311 break; 5312 } 5313 5314 /* now we are committed to transmit the packet */ 5315 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5316 pkts++; 5317 5318 /* 5319 * If there's a BPF listener, bounce a copy of this frame 5320 * to him. 5321 */ 5322 bpf_mtap(ifp, m_head); 5323 } 5324 if (pkts == 0) 5325 return; 5326 5327 /* Transmit */ 5328 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5329 /* 5700 b2 errata */ 5330 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5331 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5332 5333 sc->bge_tx_prodidx = prodidx; 5334 5335 /* 5336 * Set a timeout in case the chip goes out to lunch. 5337 */ 5338 ifp->if_timer = 5; 5339 } 5340 5341 static int 5342 bge_init(struct ifnet *ifp) 5343 { 5344 struct bge_softc *sc = ifp->if_softc; 5345 const uint16_t *m; 5346 uint32_t mode, reg; 5347 int s, error = 0; 5348 5349 s = splnet(); 5350 5351 ifp = &sc->ethercom.ec_if; 5352 5353 /* Cancel pending I/O and flush buffers. */ 5354 bge_stop(ifp, 0); 5355 5356 bge_stop_fw(sc); 5357 bge_sig_pre_reset(sc, BGE_RESET_START); 5358 bge_reset(sc); 5359 bge_sig_legacy(sc, BGE_RESET_START); 5360 bge_sig_post_reset(sc, BGE_RESET_START); 5361 5362 bge_chipinit(sc); 5363 5364 /* 5365 * Init the various state machines, ring 5366 * control blocks and firmware. 5367 */ 5368 error = bge_blockinit(sc); 5369 if (error != 0) { 5370 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5371 error); 5372 splx(s); 5373 return error; 5374 } 5375 5376 ifp = &sc->ethercom.ec_if; 5377 5378 /* 5718 step 25, 57XX step 54 */ 5379 /* Specify MTU. */ 5380 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5381 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5382 5383 /* 5718 step 23 */ 5384 /* Load our MAC address. */ 5385 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5386 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5387 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5388 5389 /* Enable or disable promiscuous mode as needed. */ 5390 if (ifp->if_flags & IFF_PROMISC) 5391 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5392 else 5393 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5394 5395 /* Program multicast filter. */ 5396 bge_setmulti(sc); 5397 5398 /* Init RX ring. */ 5399 bge_init_rx_ring_std(sc); 5400 5401 /* 5402 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5403 * memory to insure that the chip has in fact read the first 5404 * entry of the ring. 5405 */ 5406 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5407 uint32_t v, i; 5408 for (i = 0; i < 10; i++) { 5409 DELAY(20); 5410 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5411 if (v == (MCLBYTES - ETHER_ALIGN)) 5412 break; 5413 } 5414 if (i == 10) 5415 aprint_error_dev(sc->bge_dev, 5416 "5705 A0 chip failed to load RX ring\n"); 5417 } 5418 5419 /* Init jumbo RX ring. */ 5420 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5421 bge_init_rx_ring_jumbo(sc); 5422 5423 /* Init our RX return ring index */ 5424 sc->bge_rx_saved_considx = 0; 5425 5426 /* Init TX ring. */ 5427 bge_init_tx_ring(sc); 5428 5429 /* 5718 step 63, 57XX step 94 */ 5430 /* Enable TX MAC state machine lockup fix. */ 5431 mode = CSR_READ_4(sc, BGE_TX_MODE); 5432 if (BGE_IS_5755_PLUS(sc) || 5433 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5434 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5435 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5436 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5437 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5438 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5439 } 5440 5441 /* Turn on transmitter */ 5442 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5443 /* 5718 step 64 */ 5444 DELAY(100); 5445 5446 /* 5718 step 65, 57XX step 95 */ 5447 /* Turn on receiver */ 5448 mode = CSR_READ_4(sc, BGE_RX_MODE); 5449 if (BGE_IS_5755_PLUS(sc)) 5450 mode |= BGE_RXMODE_IPV6_ENABLE; 5451 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5452 /* 5718 step 66 */ 5453 DELAY(10); 5454 5455 /* 5718 step 12, 57XX step 37 */ 5456 /* 5457 * XXX Doucments of 5718 series and 577xx say the recommended value 5458 * is 1, but tg3 set 1 only on 57765 series. 5459 */ 5460 if (BGE_IS_57765_PLUS(sc)) 5461 reg = 1; 5462 else 5463 reg = 2; 5464 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5465 5466 /* Tell firmware we're alive. */ 5467 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5468 5469 /* Enable host interrupts. */ 5470 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5471 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5472 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5473 5474 if ((error = bge_ifmedia_upd(ifp)) != 0) 5475 goto out; 5476 5477 ifp->if_flags |= IFF_RUNNING; 5478 ifp->if_flags &= ~IFF_OACTIVE; 5479 5480 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5481 5482 out: 5483 sc->bge_if_flags = ifp->if_flags; 5484 splx(s); 5485 5486 return error; 5487 } 5488 5489 /* 5490 * Set media options. 5491 */ 5492 static int 5493 bge_ifmedia_upd(struct ifnet *ifp) 5494 { 5495 struct bge_softc *sc = ifp->if_softc; 5496 struct mii_data *mii = &sc->bge_mii; 5497 struct ifmedia *ifm = &sc->bge_ifmedia; 5498 int rc; 5499 5500 /* If this is a 1000baseX NIC, enable the TBI port. */ 5501 if (sc->bge_flags & BGEF_FIBER_TBI) { 5502 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5503 return EINVAL; 5504 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5505 case IFM_AUTO: 5506 /* 5507 * The BCM5704 ASIC appears to have a special 5508 * mechanism for programming the autoneg 5509 * advertisement registers in TBI mode. 5510 */ 5511 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5512 uint32_t sgdig; 5513 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5514 if (sgdig & BGE_SGDIGSTS_DONE) { 5515 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5516 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5517 sgdig |= BGE_SGDIGCFG_AUTO | 5518 BGE_SGDIGCFG_PAUSE_CAP | 5519 BGE_SGDIGCFG_ASYM_PAUSE; 5520 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5521 sgdig | BGE_SGDIGCFG_SEND); 5522 DELAY(5); 5523 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5524 sgdig); 5525 } 5526 } 5527 break; 5528 case IFM_1000_SX: 5529 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5530 BGE_CLRBIT(sc, BGE_MAC_MODE, 5531 BGE_MACMODE_HALF_DUPLEX); 5532 } else { 5533 BGE_SETBIT(sc, BGE_MAC_MODE, 5534 BGE_MACMODE_HALF_DUPLEX); 5535 } 5536 DELAY(40); 5537 break; 5538 default: 5539 return EINVAL; 5540 } 5541 /* XXX 802.3x flow control for 1000BASE-SX */ 5542 return 0; 5543 } 5544 5545 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5546 if ((rc = mii_mediachg(mii)) == ENXIO) 5547 return 0; 5548 5549 /* 5550 * Force an interrupt so that we will call bge_link_upd 5551 * if needed and clear any pending link state attention. 5552 * Without this we are not getting any further interrupts 5553 * for link state changes and thus will not UP the link and 5554 * not be able to send in bge_start. The only way to get 5555 * things working was to receive a packet and get a RX intr. 5556 */ 5557 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5558 sc->bge_flags & BGEF_IS_5788) 5559 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5560 else 5561 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5562 5563 return rc; 5564 } 5565 5566 /* 5567 * Report current media status. 5568 */ 5569 static void 5570 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5571 { 5572 struct bge_softc *sc = ifp->if_softc; 5573 struct mii_data *mii = &sc->bge_mii; 5574 5575 if (sc->bge_flags & BGEF_FIBER_TBI) { 5576 ifmr->ifm_status = IFM_AVALID; 5577 ifmr->ifm_active = IFM_ETHER; 5578 if (CSR_READ_4(sc, BGE_MAC_STS) & 5579 BGE_MACSTAT_TBI_PCS_SYNCHED) 5580 ifmr->ifm_status |= IFM_ACTIVE; 5581 ifmr->ifm_active |= IFM_1000_SX; 5582 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5583 ifmr->ifm_active |= IFM_HDX; 5584 else 5585 ifmr->ifm_active |= IFM_FDX; 5586 return; 5587 } 5588 5589 mii_pollstat(mii); 5590 ifmr->ifm_status = mii->mii_media_status; 5591 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5592 sc->bge_flowflags; 5593 } 5594 5595 static int 5596 bge_ifflags_cb(struct ethercom *ec) 5597 { 5598 struct ifnet *ifp = &ec->ec_if; 5599 struct bge_softc *sc = ifp->if_softc; 5600 int change = ifp->if_flags ^ sc->bge_if_flags; 5601 5602 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5603 return ENETRESET; 5604 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5605 return 0; 5606 5607 if ((ifp->if_flags & IFF_PROMISC) == 0) 5608 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5609 else 5610 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5611 5612 bge_setmulti(sc); 5613 5614 sc->bge_if_flags = ifp->if_flags; 5615 return 0; 5616 } 5617 5618 static int 5619 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5620 { 5621 struct bge_softc *sc = ifp->if_softc; 5622 struct ifreq *ifr = (struct ifreq *) data; 5623 int s, error = 0; 5624 struct mii_data *mii; 5625 5626 s = splnet(); 5627 5628 switch (command) { 5629 case SIOCSIFMEDIA: 5630 /* XXX Flow control is not supported for 1000BASE-SX */ 5631 if (sc->bge_flags & BGEF_FIBER_TBI) { 5632 ifr->ifr_media &= ~IFM_ETH_FMASK; 5633 sc->bge_flowflags = 0; 5634 } 5635 5636 /* Flow control requires full-duplex mode. */ 5637 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5638 (ifr->ifr_media & IFM_FDX) == 0) { 5639 ifr->ifr_media &= ~IFM_ETH_FMASK; 5640 } 5641 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5642 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5643 /* We can do both TXPAUSE and RXPAUSE. */ 5644 ifr->ifr_media |= 5645 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5646 } 5647 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5648 } 5649 /* FALLTHROUGH */ 5650 case SIOCGIFMEDIA: 5651 if (sc->bge_flags & BGEF_FIBER_TBI) { 5652 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5653 command); 5654 } else { 5655 mii = &sc->bge_mii; 5656 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5657 command); 5658 } 5659 break; 5660 default: 5661 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5662 break; 5663 5664 error = 0; 5665 5666 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5667 ; 5668 else if (ifp->if_flags & IFF_RUNNING) 5669 bge_setmulti(sc); 5670 break; 5671 } 5672 5673 splx(s); 5674 5675 return error; 5676 } 5677 5678 static void 5679 bge_watchdog(struct ifnet *ifp) 5680 { 5681 struct bge_softc *sc; 5682 5683 sc = ifp->if_softc; 5684 5685 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5686 5687 ifp->if_flags &= ~IFF_RUNNING; 5688 bge_init(ifp); 5689 5690 ifp->if_oerrors++; 5691 } 5692 5693 static void 5694 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5695 { 5696 int i; 5697 5698 BGE_CLRBIT_FLUSH(sc, reg, bit); 5699 5700 for (i = 0; i < 1000; i++) { 5701 delay(100); 5702 if ((CSR_READ_4(sc, reg) & bit) == 0) 5703 return; 5704 } 5705 5706 /* 5707 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5708 * on some environment (and once after boot?) 5709 */ 5710 if (reg != BGE_SRS_MODE) 5711 aprint_error_dev(sc->bge_dev, 5712 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5713 (u_long)reg, bit); 5714 } 5715 5716 /* 5717 * Stop the adapter and free any mbufs allocated to the 5718 * RX and TX lists. 5719 */ 5720 static void 5721 bge_stop(struct ifnet *ifp, int disable) 5722 { 5723 struct bge_softc *sc = ifp->if_softc; 5724 5725 callout_stop(&sc->bge_timeout); 5726 5727 /* Disable host interrupts. */ 5728 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5729 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5730 5731 /* 5732 * Tell firmware we're shutting down. 5733 */ 5734 bge_stop_fw(sc); 5735 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5736 5737 /* 5738 * Disable all of the receiver blocks. 5739 */ 5740 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5741 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5742 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5743 if (BGE_IS_5700_FAMILY(sc)) 5744 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5745 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5746 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5747 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5748 5749 /* 5750 * Disable all of the transmit blocks. 5751 */ 5752 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5753 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5754 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5755 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5756 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5757 if (BGE_IS_5700_FAMILY(sc)) 5758 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5759 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5760 5761 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5762 delay(40); 5763 5764 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5765 5766 /* 5767 * Shut down all of the memory managers and related 5768 * state machines. 5769 */ 5770 /* 5718 step 5a,5b */ 5771 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5772 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5773 if (BGE_IS_5700_FAMILY(sc)) 5774 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5775 5776 /* 5718 step 5c,5d */ 5777 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5778 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5779 5780 if (BGE_IS_5700_FAMILY(sc)) { 5781 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5782 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5783 } 5784 5785 bge_reset(sc); 5786 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5787 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5788 5789 /* 5790 * Keep the ASF firmware running if up. 5791 */ 5792 if (sc->bge_asf_mode & ASF_STACKUP) 5793 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5794 else 5795 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5796 5797 /* Free the RX lists. */ 5798 bge_free_rx_ring_std(sc); 5799 5800 /* Free jumbo RX list. */ 5801 if (BGE_IS_JUMBO_CAPABLE(sc)) 5802 bge_free_rx_ring_jumbo(sc); 5803 5804 /* Free TX buffers. */ 5805 bge_free_tx_ring(sc); 5806 5807 /* 5808 * Isolate/power down the PHY. 5809 */ 5810 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 5811 mii_down(&sc->bge_mii); 5812 5813 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5814 5815 /* Clear MAC's link state (PHY may still have link UP). */ 5816 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5817 5818 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5819 } 5820 5821 static void 5822 bge_link_upd(struct bge_softc *sc) 5823 { 5824 struct ifnet *ifp = &sc->ethercom.ec_if; 5825 struct mii_data *mii = &sc->bge_mii; 5826 uint32_t status; 5827 int link; 5828 5829 /* Clear 'pending link event' flag */ 5830 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5831 5832 /* 5833 * Process link state changes. 5834 * Grrr. The link status word in the status block does 5835 * not work correctly on the BCM5700 rev AX and BX chips, 5836 * according to all available information. Hence, we have 5837 * to enable MII interrupts in order to properly obtain 5838 * async link changes. Unfortunately, this also means that 5839 * we have to read the MAC status register to detect link 5840 * changes, thereby adding an additional register access to 5841 * the interrupt handler. 5842 */ 5843 5844 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5845 status = CSR_READ_4(sc, BGE_MAC_STS); 5846 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5847 mii_pollstat(mii); 5848 5849 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5850 mii->mii_media_status & IFM_ACTIVE && 5851 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5852 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5853 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5854 (!(mii->mii_media_status & IFM_ACTIVE) || 5855 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5856 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5857 5858 /* Clear the interrupt */ 5859 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5860 BGE_EVTENB_MI_INTERRUPT); 5861 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5862 BRGPHY_MII_ISR); 5863 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5864 BRGPHY_MII_IMR, BRGPHY_INTRS); 5865 } 5866 return; 5867 } 5868 5869 if (sc->bge_flags & BGEF_FIBER_TBI) { 5870 status = CSR_READ_4(sc, BGE_MAC_STS); 5871 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5872 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5873 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5874 if (BGE_ASICREV(sc->bge_chipid) 5875 == BGE_ASICREV_BCM5704) { 5876 BGE_CLRBIT(sc, BGE_MAC_MODE, 5877 BGE_MACMODE_TBI_SEND_CFGS); 5878 DELAY(40); 5879 } 5880 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5881 if_link_state_change(ifp, LINK_STATE_UP); 5882 } 5883 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5884 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5885 if_link_state_change(ifp, LINK_STATE_DOWN); 5886 } 5887 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5888 /* 5889 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5890 * bit in status word always set. Workaround this bug by 5891 * reading PHY link status directly. 5892 */ 5893 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5894 BGE_STS_LINK : 0; 5895 5896 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5897 mii_pollstat(mii); 5898 5899 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5900 mii->mii_media_status & IFM_ACTIVE && 5901 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5902 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5903 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5904 (!(mii->mii_media_status & IFM_ACTIVE) || 5905 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5906 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5907 } 5908 } else { 5909 /* 5910 * For controllers that call mii_tick, we have to poll 5911 * link status. 5912 */ 5913 mii_pollstat(mii); 5914 } 5915 5916 /* Clear the attention */ 5917 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5918 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5919 BGE_MACSTAT_LINK_CHANGED); 5920 } 5921 5922 static int 5923 bge_sysctl_verify(SYSCTLFN_ARGS) 5924 { 5925 int error, t; 5926 struct sysctlnode node; 5927 5928 node = *rnode; 5929 t = *(int*)rnode->sysctl_data; 5930 node.sysctl_data = &t; 5931 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5932 if (error || newp == NULL) 5933 return error; 5934 5935 #if 0 5936 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5937 node.sysctl_num, rnode->sysctl_num)); 5938 #endif 5939 5940 if (node.sysctl_num == bge_rxthresh_nodenum) { 5941 if (t < 0 || t >= NBGE_RX_THRESH) 5942 return EINVAL; 5943 bge_update_all_threshes(t); 5944 } else 5945 return EINVAL; 5946 5947 *(int*)rnode->sysctl_data = t; 5948 5949 return 0; 5950 } 5951 5952 /* 5953 * Set up sysctl(3) MIB, hw.bge.*. 5954 */ 5955 static void 5956 bge_sysctl_init(struct bge_softc *sc) 5957 { 5958 int rc, bge_root_num; 5959 const struct sysctlnode *node; 5960 5961 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5962 0, CTLTYPE_NODE, "bge", 5963 SYSCTL_DESCR("BGE interface controls"), 5964 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5965 goto out; 5966 } 5967 5968 bge_root_num = node->sysctl_num; 5969 5970 /* BGE Rx interrupt mitigation level */ 5971 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5972 CTLFLAG_READWRITE, 5973 CTLTYPE_INT, "rx_lvl", 5974 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 5975 bge_sysctl_verify, 0, 5976 &bge_rx_thresh_lvl, 5977 0, CTL_HW, bge_root_num, CTL_CREATE, 5978 CTL_EOL)) != 0) { 5979 goto out; 5980 } 5981 5982 bge_rxthresh_nodenum = node->sysctl_num; 5983 5984 return; 5985 5986 out: 5987 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 5988 } 5989 5990 #ifdef BGE_DEBUG 5991 void 5992 bge_debug_info(struct bge_softc *sc) 5993 { 5994 5995 printf("Hardware Flags:\n"); 5996 if (BGE_IS_57765_PLUS(sc)) 5997 printf(" - 57765 Plus\n"); 5998 if (BGE_IS_5717_PLUS(sc)) 5999 printf(" - 5717 Plus\n"); 6000 if (BGE_IS_5755_PLUS(sc)) 6001 printf(" - 5755 Plus\n"); 6002 if (BGE_IS_575X_PLUS(sc)) 6003 printf(" - 575X Plus\n"); 6004 if (BGE_IS_5705_PLUS(sc)) 6005 printf(" - 5705 Plus\n"); 6006 if (BGE_IS_5714_FAMILY(sc)) 6007 printf(" - 5714 Family\n"); 6008 if (BGE_IS_5700_FAMILY(sc)) 6009 printf(" - 5700 Family\n"); 6010 if (sc->bge_flags & BGEF_IS_5788) 6011 printf(" - 5788\n"); 6012 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6013 printf(" - Supports Jumbo Frames\n"); 6014 if (sc->bge_flags & BGEF_NO_EEPROM) 6015 printf(" - No EEPROM\n"); 6016 if (sc->bge_flags & BGEF_PCIX) 6017 printf(" - PCI-X Bus\n"); 6018 if (sc->bge_flags & BGEF_PCIE) 6019 printf(" - PCI Express Bus\n"); 6020 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6021 printf(" - RX Alignment Bug\n"); 6022 if (sc->bge_flags & BGEF_APE) 6023 printf(" - APE\n"); 6024 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6025 printf(" - CPMU\n"); 6026 if (sc->bge_flags & BGEF_TSO) 6027 printf(" - TSO\n"); 6028 6029 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6030 printf(" - No 3 LEDs\n"); 6031 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6032 printf(" - CRC bug\n"); 6033 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6034 printf(" - ADC bug\n"); 6035 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6036 printf(" - 5704 A0 bug\n"); 6037 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6038 printf(" - jitter bug\n"); 6039 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6040 printf(" - BER bug\n"); 6041 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6042 printf(" - adjust trim\n"); 6043 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6044 printf(" - no wirespeed\n"); 6045 } 6046 #endif /* BGE_DEBUG */ 6047 6048 static int 6049 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6050 { 6051 prop_dictionary_t dict; 6052 prop_data_t ea; 6053 6054 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6055 return 1; 6056 6057 dict = device_properties(sc->bge_dev); 6058 ea = prop_dictionary_get(dict, "mac-address"); 6059 if (ea != NULL) { 6060 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6061 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6062 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6063 return 0; 6064 } 6065 6066 return 1; 6067 } 6068 6069 static int 6070 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6071 { 6072 uint32_t mac_addr; 6073 6074 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6075 if ((mac_addr >> 16) == 0x484b) { 6076 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6077 ether_addr[1] = (uint8_t)mac_addr; 6078 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6079 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6080 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6081 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6082 ether_addr[5] = (uint8_t)mac_addr; 6083 return 0; 6084 } 6085 return 1; 6086 } 6087 6088 static int 6089 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6090 { 6091 int mac_offset = BGE_EE_MAC_OFFSET; 6092 6093 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6094 mac_offset = BGE_EE_MAC_OFFSET_5906; 6095 6096 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6097 ETHER_ADDR_LEN)); 6098 } 6099 6100 static int 6101 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6102 { 6103 6104 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6105 return 1; 6106 6107 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6108 ETHER_ADDR_LEN)); 6109 } 6110 6111 static int 6112 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6113 { 6114 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6115 /* NOTE: Order is critical */ 6116 bge_get_eaddr_fw, 6117 bge_get_eaddr_mem, 6118 bge_get_eaddr_nvram, 6119 bge_get_eaddr_eeprom, 6120 NULL 6121 }; 6122 const bge_eaddr_fcn_t *func; 6123 6124 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6125 if ((*func)(sc, eaddr) == 0) 6126 break; 6127 } 6128 return (*func == NULL ? ENXIO : 0); 6129 } 6130
Indexes created Tue Sep 23 02:09:52 GMT 2025