if_bge.c revision 1.279 1 /* $NetBSD: if_bge.c,v 1.279 2015/02/17 10:11:24 msaitoh Exp $ */
2
3 /*
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2001
6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $
36 */
37
38 /*
39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD.
40 *
41 * NetBSD version by:
42 *
43 * Frank van der Linden <fvdl (at) wasabisystems.com>
44 * Jason Thorpe <thorpej (at) wasabisystems.com>
45 * Jonathan Stone <jonathan (at) dsg.stanford.edu>
46 *
47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com>
48 * Senior Engineer, Wind River Systems
49 */
50
51 /*
52 * The Broadcom BCM5700 is based on technology originally developed by
53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
57 * frames, highly configurable RX filtering, and 16 RX and TX queues
58 * (which, along with RX filter rules, can be used for QOS applications).
59 * Other features, such as TCP segmentation, may be available as part
60 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
61 * firmware images can be stored in hardware and need not be compiled
62 * into the driver.
63 *
64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
66 *
67 * The BCM5701 is a single-chip solution incorporating both the BCM5700
68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
69 * does not support external SSRAM.
70 *
71 * Broadcom also produces a variation of the BCM5700 under the "Altima"
72 * brand name, which is functionally similar but lacks PCI-X support.
73 *
74 * Without external SSRAM, you can only have at most 4 TX rings,
75 * and the use of the mini RX ring is disabled. This seems to imply
76 * that these features are simply not available on the BCM5701. As a
77 * result, this driver does not implement any support for the mini RX
78 * ring.
79 */
80
81 #include <sys/cdefs.h>
82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.279 2015/02/17 10:11:24 msaitoh Exp $");
83
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/callout.h>
87 #include <sys/sockio.h>
88 #include <sys/mbuf.h>
89 #include <sys/malloc.h>
90 #include <sys/kernel.h>
91 #include <sys/device.h>
92 #include <sys/socket.h>
93 #include <sys/sysctl.h>
94
95 #include <net/if.h>
96 #include <net/if_dl.h>
97 #include <net/if_media.h>
98 #include <net/if_ether.h>
99
100 #include <sys/rnd.h>
101
102 #ifdef INET
103 #include <netinet/in.h>
104 #include <netinet/in_systm.h>
105 #include <netinet/in_var.h>
106 #include <netinet/ip.h>
107 #endif
108
109 /* Headers for TCP Segmentation Offload (TSO) */
110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */
111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */
112 #include <netinet/ip.h> /* for struct ip */
113 #include <netinet/tcp.h> /* for struct tcphdr */
114
115
116 #include <net/bpf.h>
117
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
120 #include <dev/pci/pcidevs.h>
121
122 #include <dev/mii/mii.h>
123 #include <dev/mii/miivar.h>
124 #include <dev/mii/miidevs.h>
125 #include <dev/mii/brgphyreg.h>
126
127 #include <dev/pci/if_bgereg.h>
128 #include <dev/pci/if_bgevar.h>
129
130 #include <prop/proplib.h>
131
132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
133
134
135 /*
136 * Tunable thresholds for rx-side bge interrupt mitigation.
137 */
138
139 /*
140 * The pairs of values below were obtained from empirical measurement
141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive
142 * interrupt for every N packets received, where N is, approximately,
143 * the second value (rx_max_bds) in each pair. The values are chosen
144 * such that moving from one pair to the succeeding pair was observed
145 * to roughly halve interrupt rate under sustained input packet load.
146 * The values were empirically chosen to avoid overflowing internal
147 * limits on the bcm5700: increasing rx_ticks much beyond 600
148 * results in internal wrapping and higher interrupt rates.
149 * The limit of 46 frames was chosen to match NFS workloads.
150 *
151 * These values also work well on bcm5701, bcm5704C, and (less
152 * tested) bcm5703. On other chipsets, (including the Altima chip
153 * family), the larger values may overflow internal chip limits,
154 * leading to increasing interrupt rates rather than lower interrupt
155 * rates.
156 *
157 * Applications using heavy interrupt mitigation (interrupting every
158 * 32 or 46 frames) in both directions may need to increase the TCP
159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain
160 * full link bandwidth, due to ACKs and window updates lingering
161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window.
162 */
163 static const struct bge_load_rx_thresh {
164 int rx_ticks;
165 int rx_max_bds; }
166 bge_rx_threshes[] = {
167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */
168 { 32, 2 },
169 { 50, 4 },
170 { 100, 8 },
171 { 192, 16 },
172 { 416, 32 },
173 { 598, 46 }
174 };
175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0]))
176
177 /* XXX patchable; should be sysctl'able */
178 static int bge_auto_thresh = 1;
179 static int bge_rx_thresh_lvl;
180
181 static int bge_rxthresh_nodenum;
182
183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
184
185 static uint32_t bge_chipid(const struct pci_attach_args *);
186 static int bge_probe(device_t, cfdata_t, void *);
187 static void bge_attach(device_t, device_t, void *);
188 static int bge_detach(device_t, int);
189 static void bge_release_resources(struct bge_softc *);
190
191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]);
192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
196
197 static void bge_txeof(struct bge_softc *);
198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
199 static void bge_rxeof(struct bge_softc *);
200
201 static void bge_asf_driver_up (struct bge_softc *);
202 static void bge_tick(void *);
203 static void bge_stats_update(struct bge_softc *);
204 static void bge_stats_update_regs(struct bge_softc *);
205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
206
207 static int bge_intr(void *);
208 static void bge_start(struct ifnet *);
209 static int bge_ifflags_cb(struct ethercom *);
210 static int bge_ioctl(struct ifnet *, u_long, void *);
211 static int bge_init(struct ifnet *);
212 static void bge_stop(struct ifnet *, int);
213 static void bge_watchdog(struct ifnet *);
214 static int bge_ifmedia_upd(struct ifnet *);
215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
216
217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int);
219
220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
221 static int bge_read_eeprom(struct bge_softc *, void *, int, int);
222 static void bge_setmulti(struct bge_softc *);
223
224 static void bge_handle_events(struct bge_softc *);
225 static int bge_alloc_jumbo_mem(struct bge_softc *);
226 #if 0 /* XXX */
227 static void bge_free_jumbo_mem(struct bge_softc *);
228 #endif
229 static void *bge_jalloc(struct bge_softc *);
230 static void bge_jfree(struct mbuf *, void *, size_t, void *);
231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *,
232 bus_dmamap_t);
233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
234 static int bge_init_rx_ring_std(struct bge_softc *);
235 static void bge_free_rx_ring_std(struct bge_softc *);
236 static int bge_init_rx_ring_jumbo(struct bge_softc *);
237 static void bge_free_rx_ring_jumbo(struct bge_softc *);
238 static void bge_free_tx_ring(struct bge_softc *);
239 static int bge_init_tx_ring(struct bge_softc *);
240
241 static int bge_chipinit(struct bge_softc *);
242 static int bge_blockinit(struct bge_softc *);
243 static int bge_phy_addr(struct bge_softc *);
244 static uint32_t bge_readmem_ind(struct bge_softc *, int);
245 static void bge_writemem_ind(struct bge_softc *, int, int);
246 static void bge_writembx(struct bge_softc *, int, int);
247 static void bge_writembx_flush(struct bge_softc *, int, int);
248 static void bge_writemem_direct(struct bge_softc *, int, int);
249 static void bge_writereg_ind(struct bge_softc *, int, int);
250 static void bge_set_max_readrq(struct bge_softc *);
251
252 static int bge_miibus_readreg(device_t, int, int);
253 static void bge_miibus_writereg(device_t, int, int, int);
254 static void bge_miibus_statchg(struct ifnet *);
255
256 #define BGE_RESET_SHUTDOWN 0
257 #define BGE_RESET_START 1
258 #define BGE_RESET_SUSPEND 2
259 static void bge_sig_post_reset(struct bge_softc *, int);
260 static void bge_sig_legacy(struct bge_softc *, int);
261 static void bge_sig_pre_reset(struct bge_softc *, int);
262 static void bge_wait_for_event_ack(struct bge_softc *);
263 static void bge_stop_fw(struct bge_softc *);
264 static int bge_reset(struct bge_softc *);
265 static void bge_link_upd(struct bge_softc *);
266 static void bge_sysctl_init(struct bge_softc *);
267 static int bge_sysctl_verify(SYSCTLFN_PROTO);
268
269 static void bge_ape_lock_init(struct bge_softc *);
270 static void bge_ape_read_fw_ver(struct bge_softc *);
271 static int bge_ape_lock(struct bge_softc *, int);
272 static void bge_ape_unlock(struct bge_softc *, int);
273 static void bge_ape_send_event(struct bge_softc *, uint32_t);
274 static void bge_ape_driver_state_change(struct bge_softc *, int);
275
276 #ifdef BGE_DEBUG
277 #define DPRINTF(x) if (bgedebug) printf x
278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x
279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0)
280 int bgedebug = 0;
281 int bge_tso_debug = 0;
282 void bge_debug_info(struct bge_softc *);
283 #else
284 #define DPRINTF(x)
285 #define DPRINTFN(n,x)
286 #define BGE_TSO_PRINTF(x)
287 #endif
288
289 #ifdef BGE_EVENT_COUNTERS
290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++
291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val)
292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val)
293 #else
294 #define BGE_EVCNT_INCR(ev) /* nothing */
295 #define BGE_EVCNT_ADD(ev, val) /* nothing */
296 #define BGE_EVCNT_UPD(ev, val) /* nothing */
297 #endif
298
299 static const struct bge_product {
300 pci_vendor_id_t bp_vendor;
301 pci_product_id_t bp_product;
302 const char *bp_name;
303 } bge_products[] = {
304 /*
305 * The BCM5700 documentation seems to indicate that the hardware
306 * still has the Alteon vendor ID burned into it, though it
307 * should always be overridden by the value in the EEPROM. We'll
308 * check for it anyway.
309 */
310 { PCI_VENDOR_ALTEON,
311 PCI_PRODUCT_ALTEON_BCM5700,
312 "Broadcom BCM5700 Gigabit Ethernet",
313 },
314 { PCI_VENDOR_ALTEON,
315 PCI_PRODUCT_ALTEON_BCM5701,
316 "Broadcom BCM5701 Gigabit Ethernet",
317 },
318 { PCI_VENDOR_ALTIMA,
319 PCI_PRODUCT_ALTIMA_AC1000,
320 "Altima AC1000 Gigabit Ethernet",
321 },
322 { PCI_VENDOR_ALTIMA,
323 PCI_PRODUCT_ALTIMA_AC1001,
324 "Altima AC1001 Gigabit Ethernet",
325 },
326 { PCI_VENDOR_ALTIMA,
327 PCI_PRODUCT_ALTIMA_AC1003,
328 "Altima AC1003 Gigabit Ethernet",
329 },
330 { PCI_VENDOR_ALTIMA,
331 PCI_PRODUCT_ALTIMA_AC9100,
332 "Altima AC9100 Gigabit Ethernet",
333 },
334 { PCI_VENDOR_APPLE,
335 PCI_PRODUCT_APPLE_BCM5701,
336 "APPLE BCM5701 Gigabit Ethernet",
337 },
338 { PCI_VENDOR_BROADCOM,
339 PCI_PRODUCT_BROADCOM_BCM5700,
340 "Broadcom BCM5700 Gigabit Ethernet",
341 },
342 { PCI_VENDOR_BROADCOM,
343 PCI_PRODUCT_BROADCOM_BCM5701,
344 "Broadcom BCM5701 Gigabit Ethernet",
345 },
346 { PCI_VENDOR_BROADCOM,
347 PCI_PRODUCT_BROADCOM_BCM5702,
348 "Broadcom BCM5702 Gigabit Ethernet",
349 },
350 { PCI_VENDOR_BROADCOM,
351 PCI_PRODUCT_BROADCOM_BCM5702X,
352 "Broadcom BCM5702X Gigabit Ethernet" },
353 { PCI_VENDOR_BROADCOM,
354 PCI_PRODUCT_BROADCOM_BCM5703,
355 "Broadcom BCM5703 Gigabit Ethernet",
356 },
357 { PCI_VENDOR_BROADCOM,
358 PCI_PRODUCT_BROADCOM_BCM5703X,
359 "Broadcom BCM5703X Gigabit Ethernet",
360 },
361 { PCI_VENDOR_BROADCOM,
362 PCI_PRODUCT_BROADCOM_BCM5703_ALT,
363 "Broadcom BCM5703 Gigabit Ethernet",
364 },
365 { PCI_VENDOR_BROADCOM,
366 PCI_PRODUCT_BROADCOM_BCM5704C,
367 "Broadcom BCM5704C Dual Gigabit Ethernet",
368 },
369 { PCI_VENDOR_BROADCOM,
370 PCI_PRODUCT_BROADCOM_BCM5704S,
371 "Broadcom BCM5704S Dual Gigabit Ethernet",
372 },
373 { PCI_VENDOR_BROADCOM,
374 PCI_PRODUCT_BROADCOM_BCM5705,
375 "Broadcom BCM5705 Gigabit Ethernet",
376 },
377 { PCI_VENDOR_BROADCOM,
378 PCI_PRODUCT_BROADCOM_BCM5705F,
379 "Broadcom BCM5705F Gigabit Ethernet",
380 },
381 { PCI_VENDOR_BROADCOM,
382 PCI_PRODUCT_BROADCOM_BCM5705K,
383 "Broadcom BCM5705K Gigabit Ethernet",
384 },
385 { PCI_VENDOR_BROADCOM,
386 PCI_PRODUCT_BROADCOM_BCM5705M,
387 "Broadcom BCM5705M Gigabit Ethernet",
388 },
389 { PCI_VENDOR_BROADCOM,
390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
391 "Broadcom BCM5705M Gigabit Ethernet",
392 },
393 { PCI_VENDOR_BROADCOM,
394 PCI_PRODUCT_BROADCOM_BCM5714,
395 "Broadcom BCM5714 Gigabit Ethernet",
396 },
397 { PCI_VENDOR_BROADCOM,
398 PCI_PRODUCT_BROADCOM_BCM5714S,
399 "Broadcom BCM5714S Gigabit Ethernet",
400 },
401 { PCI_VENDOR_BROADCOM,
402 PCI_PRODUCT_BROADCOM_BCM5715,
403 "Broadcom BCM5715 Gigabit Ethernet",
404 },
405 { PCI_VENDOR_BROADCOM,
406 PCI_PRODUCT_BROADCOM_BCM5715S,
407 "Broadcom BCM5715S Gigabit Ethernet",
408 },
409 { PCI_VENDOR_BROADCOM,
410 PCI_PRODUCT_BROADCOM_BCM5717,
411 "Broadcom BCM5717 Gigabit Ethernet",
412 },
413 { PCI_VENDOR_BROADCOM,
414 PCI_PRODUCT_BROADCOM_BCM5718,
415 "Broadcom BCM5718 Gigabit Ethernet",
416 },
417 { PCI_VENDOR_BROADCOM,
418 PCI_PRODUCT_BROADCOM_BCM5719,
419 "Broadcom BCM5719 Gigabit Ethernet",
420 },
421 { PCI_VENDOR_BROADCOM,
422 PCI_PRODUCT_BROADCOM_BCM5720,
423 "Broadcom BCM5720 Gigabit Ethernet",
424 },
425 { PCI_VENDOR_BROADCOM,
426 PCI_PRODUCT_BROADCOM_BCM5721,
427 "Broadcom BCM5721 Gigabit Ethernet",
428 },
429 { PCI_VENDOR_BROADCOM,
430 PCI_PRODUCT_BROADCOM_BCM5722,
431 "Broadcom BCM5722 Gigabit Ethernet",
432 },
433 { PCI_VENDOR_BROADCOM,
434 PCI_PRODUCT_BROADCOM_BCM5723,
435 "Broadcom BCM5723 Gigabit Ethernet",
436 },
437 { PCI_VENDOR_BROADCOM,
438 PCI_PRODUCT_BROADCOM_BCM5724,
439 "Broadcom BCM5724 Gigabit Ethernet",
440 },
441 { PCI_VENDOR_BROADCOM,
442 PCI_PRODUCT_BROADCOM_BCM5750,
443 "Broadcom BCM5750 Gigabit Ethernet",
444 },
445 { PCI_VENDOR_BROADCOM,
446 PCI_PRODUCT_BROADCOM_BCM5750M,
447 "Broadcom BCM5750M Gigabit Ethernet",
448 },
449 { PCI_VENDOR_BROADCOM,
450 PCI_PRODUCT_BROADCOM_BCM5751,
451 "Broadcom BCM5751 Gigabit Ethernet",
452 },
453 { PCI_VENDOR_BROADCOM,
454 PCI_PRODUCT_BROADCOM_BCM5751F,
455 "Broadcom BCM5751F Gigabit Ethernet",
456 },
457 { PCI_VENDOR_BROADCOM,
458 PCI_PRODUCT_BROADCOM_BCM5751M,
459 "Broadcom BCM5751M Gigabit Ethernet",
460 },
461 { PCI_VENDOR_BROADCOM,
462 PCI_PRODUCT_BROADCOM_BCM5752,
463 "Broadcom BCM5752 Gigabit Ethernet",
464 },
465 { PCI_VENDOR_BROADCOM,
466 PCI_PRODUCT_BROADCOM_BCM5752M,
467 "Broadcom BCM5752M Gigabit Ethernet",
468 },
469 { PCI_VENDOR_BROADCOM,
470 PCI_PRODUCT_BROADCOM_BCM5753,
471 "Broadcom BCM5753 Gigabit Ethernet",
472 },
473 { PCI_VENDOR_BROADCOM,
474 PCI_PRODUCT_BROADCOM_BCM5753F,
475 "Broadcom BCM5753F Gigabit Ethernet",
476 },
477 { PCI_VENDOR_BROADCOM,
478 PCI_PRODUCT_BROADCOM_BCM5753M,
479 "Broadcom BCM5753M Gigabit Ethernet",
480 },
481 { PCI_VENDOR_BROADCOM,
482 PCI_PRODUCT_BROADCOM_BCM5754,
483 "Broadcom BCM5754 Gigabit Ethernet",
484 },
485 { PCI_VENDOR_BROADCOM,
486 PCI_PRODUCT_BROADCOM_BCM5754M,
487 "Broadcom BCM5754M Gigabit Ethernet",
488 },
489 { PCI_VENDOR_BROADCOM,
490 PCI_PRODUCT_BROADCOM_BCM5755,
491 "Broadcom BCM5755 Gigabit Ethernet",
492 },
493 { PCI_VENDOR_BROADCOM,
494 PCI_PRODUCT_BROADCOM_BCM5755M,
495 "Broadcom BCM5755M Gigabit Ethernet",
496 },
497 { PCI_VENDOR_BROADCOM,
498 PCI_PRODUCT_BROADCOM_BCM5756,
499 "Broadcom BCM5756 Gigabit Ethernet",
500 },
501 { PCI_VENDOR_BROADCOM,
502 PCI_PRODUCT_BROADCOM_BCM5761,
503 "Broadcom BCM5761 Gigabit Ethernet",
504 },
505 { PCI_VENDOR_BROADCOM,
506 PCI_PRODUCT_BROADCOM_BCM5761E,
507 "Broadcom BCM5761E Gigabit Ethernet",
508 },
509 { PCI_VENDOR_BROADCOM,
510 PCI_PRODUCT_BROADCOM_BCM5761S,
511 "Broadcom BCM5761S Gigabit Ethernet",
512 },
513 { PCI_VENDOR_BROADCOM,
514 PCI_PRODUCT_BROADCOM_BCM5761SE,
515 "Broadcom BCM5761SE Gigabit Ethernet",
516 },
517 { PCI_VENDOR_BROADCOM,
518 PCI_PRODUCT_BROADCOM_BCM5764,
519 "Broadcom BCM5764 Gigabit Ethernet",
520 },
521 { PCI_VENDOR_BROADCOM,
522 PCI_PRODUCT_BROADCOM_BCM5780,
523 "Broadcom BCM5780 Gigabit Ethernet",
524 },
525 { PCI_VENDOR_BROADCOM,
526 PCI_PRODUCT_BROADCOM_BCM5780S,
527 "Broadcom BCM5780S Gigabit Ethernet",
528 },
529 { PCI_VENDOR_BROADCOM,
530 PCI_PRODUCT_BROADCOM_BCM5781,
531 "Broadcom BCM5781 Gigabit Ethernet",
532 },
533 { PCI_VENDOR_BROADCOM,
534 PCI_PRODUCT_BROADCOM_BCM5782,
535 "Broadcom BCM5782 Gigabit Ethernet",
536 },
537 { PCI_VENDOR_BROADCOM,
538 PCI_PRODUCT_BROADCOM_BCM5784M,
539 "BCM5784M NetLink 1000baseT Ethernet",
540 },
541 { PCI_VENDOR_BROADCOM,
542 PCI_PRODUCT_BROADCOM_BCM5785F,
543 "BCM5785F NetLink 10/100 Ethernet",
544 },
545 { PCI_VENDOR_BROADCOM,
546 PCI_PRODUCT_BROADCOM_BCM5785G,
547 "BCM5785G NetLink 1000baseT Ethernet",
548 },
549 { PCI_VENDOR_BROADCOM,
550 PCI_PRODUCT_BROADCOM_BCM5786,
551 "Broadcom BCM5786 Gigabit Ethernet",
552 },
553 { PCI_VENDOR_BROADCOM,
554 PCI_PRODUCT_BROADCOM_BCM5787,
555 "Broadcom BCM5787 Gigabit Ethernet",
556 },
557 { PCI_VENDOR_BROADCOM,
558 PCI_PRODUCT_BROADCOM_BCM5787F,
559 "Broadcom BCM5787F 10/100 Ethernet",
560 },
561 { PCI_VENDOR_BROADCOM,
562 PCI_PRODUCT_BROADCOM_BCM5787M,
563 "Broadcom BCM5787M Gigabit Ethernet",
564 },
565 { PCI_VENDOR_BROADCOM,
566 PCI_PRODUCT_BROADCOM_BCM5788,
567 "Broadcom BCM5788 Gigabit Ethernet",
568 },
569 { PCI_VENDOR_BROADCOM,
570 PCI_PRODUCT_BROADCOM_BCM5789,
571 "Broadcom BCM5789 Gigabit Ethernet",
572 },
573 { PCI_VENDOR_BROADCOM,
574 PCI_PRODUCT_BROADCOM_BCM5901,
575 "Broadcom BCM5901 Fast Ethernet",
576 },
577 { PCI_VENDOR_BROADCOM,
578 PCI_PRODUCT_BROADCOM_BCM5901A2,
579 "Broadcom BCM5901A2 Fast Ethernet",
580 },
581 { PCI_VENDOR_BROADCOM,
582 PCI_PRODUCT_BROADCOM_BCM5903M,
583 "Broadcom BCM5903M Fast Ethernet",
584 },
585 { PCI_VENDOR_BROADCOM,
586 PCI_PRODUCT_BROADCOM_BCM5906,
587 "Broadcom BCM5906 Fast Ethernet",
588 },
589 { PCI_VENDOR_BROADCOM,
590 PCI_PRODUCT_BROADCOM_BCM5906M,
591 "Broadcom BCM5906M Fast Ethernet",
592 },
593 { PCI_VENDOR_BROADCOM,
594 PCI_PRODUCT_BROADCOM_BCM57760,
595 "Broadcom BCM57760 Fast Ethernet",
596 },
597 { PCI_VENDOR_BROADCOM,
598 PCI_PRODUCT_BROADCOM_BCM57761,
599 "Broadcom BCM57761 Fast Ethernet",
600 },
601 { PCI_VENDOR_BROADCOM,
602 PCI_PRODUCT_BROADCOM_BCM57762,
603 "Broadcom BCM57762 Gigabit Ethernet",
604 },
605 { PCI_VENDOR_BROADCOM,
606 PCI_PRODUCT_BROADCOM_BCM57765,
607 "Broadcom BCM57765 Fast Ethernet",
608 },
609 { PCI_VENDOR_BROADCOM,
610 PCI_PRODUCT_BROADCOM_BCM57766,
611 "Broadcom BCM57766 Fast Ethernet",
612 },
613 { PCI_VENDOR_BROADCOM,
614 PCI_PRODUCT_BROADCOM_BCM57780,
615 "Broadcom BCM57780 Fast Ethernet",
616 },
617 { PCI_VENDOR_BROADCOM,
618 PCI_PRODUCT_BROADCOM_BCM57781,
619 "Broadcom BCM57781 Fast Ethernet",
620 },
621 { PCI_VENDOR_BROADCOM,
622 PCI_PRODUCT_BROADCOM_BCM57782,
623 "Broadcom BCM57782 Fast Ethernet",
624 },
625 { PCI_VENDOR_BROADCOM,
626 PCI_PRODUCT_BROADCOM_BCM57785,
627 "Broadcom BCM57785 Fast Ethernet",
628 },
629 { PCI_VENDOR_BROADCOM,
630 PCI_PRODUCT_BROADCOM_BCM57786,
631 "Broadcom BCM57786 Fast Ethernet",
632 },
633 { PCI_VENDOR_BROADCOM,
634 PCI_PRODUCT_BROADCOM_BCM57788,
635 "Broadcom BCM57788 Fast Ethernet",
636 },
637 { PCI_VENDOR_BROADCOM,
638 PCI_PRODUCT_BROADCOM_BCM57790,
639 "Broadcom BCM57790 Fast Ethernet",
640 },
641 { PCI_VENDOR_BROADCOM,
642 PCI_PRODUCT_BROADCOM_BCM57791,
643 "Broadcom BCM57791 Fast Ethernet",
644 },
645 { PCI_VENDOR_BROADCOM,
646 PCI_PRODUCT_BROADCOM_BCM57795,
647 "Broadcom BCM57795 Fast Ethernet",
648 },
649 { PCI_VENDOR_SCHNEIDERKOCH,
650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
651 "SysKonnect SK-9Dx1 Gigabit Ethernet",
652 },
653 { PCI_VENDOR_3COM,
654 PCI_PRODUCT_3COM_3C996,
655 "3Com 3c996 Gigabit Ethernet",
656 },
657 { PCI_VENDOR_FUJITSU4,
658 PCI_PRODUCT_FUJITSU4_PW008GE4,
659 "Fujitsu PW008GE4 Gigabit Ethernet",
660 },
661 { PCI_VENDOR_FUJITSU4,
662 PCI_PRODUCT_FUJITSU4_PW008GE5,
663 "Fujitsu PW008GE5 Gigabit Ethernet",
664 },
665 { PCI_VENDOR_FUJITSU4,
666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN,
667 "Fujitsu Primepower 250/450 Gigabit Ethernet",
668 },
669 { 0,
670 0,
671 NULL },
672 };
673
674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE)
675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY)
676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS)
677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY)
678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS)
679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS)
680 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY)
681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS)
682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS)
683
684 static const struct bge_revision {
685 uint32_t br_chipid;
686 const char *br_name;
687 } bge_revisions[] = {
688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" },
701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" },
702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" },
703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" },
704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" },
705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" },
739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
743 /* 5754 and 5787 share the same ASIC ID */
744 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
745 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
746 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
747 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" },
748 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
749 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
750 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
751 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
752 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
753 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
754
755 { 0, NULL }
756 };
757
758 /*
759 * Some defaults for major revisions, so that newer steppings
760 * that we don't know about have a shot at working.
761 */
762 static const struct bge_revision bge_majorrevs[] = {
763 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
764 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
765 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
766 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
767 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
768 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
769 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
770 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
771 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
772 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
773 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
774 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
775 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
776 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
777 /* 5754 and 5787 share the same ASIC ID */
778 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
779 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
780 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
781 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
782 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
783 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
784 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
785 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
786
787 { 0, NULL }
788 };
789
790 static int bge_allow_asf = 1;
791
792 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc),
793 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
794
795 static uint32_t
796 bge_readmem_ind(struct bge_softc *sc, int off)
797 {
798 pcireg_t val;
799
800 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
801 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
802 return 0;
803
804 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off);
805 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA);
806 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
807 return val;
808 }
809
810 static void
811 bge_writemem_ind(struct bge_softc *sc, int off, int val)
812 {
813
814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off);
815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val);
816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
817 }
818
819 /*
820 * PCI Express only
821 */
822 static void
823 bge_set_max_readrq(struct bge_softc *sc)
824 {
825 pcireg_t val;
826
827 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap
828 + PCIE_DCSR);
829 val &= ~PCIE_DCSR_MAX_READ_REQ;
830 switch (sc->bge_expmrq) {
831 case 2048:
832 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048;
833 break;
834 case 4096:
835 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
836 break;
837 default:
838 panic("incorrect expmrq value(%d)", sc->bge_expmrq);
839 break;
840 }
841 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap
842 + PCIE_DCSR, val);
843 }
844
845 #ifdef notdef
846 static uint32_t
847 bge_readreg_ind(struct bge_softc *sc, int off)
848 {
849 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off);
850 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA));
851 }
852 #endif
853
854 static void
855 bge_writereg_ind(struct bge_softc *sc, int off, int val)
856 {
857 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off);
858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val);
859 }
860
861 static void
862 bge_writemem_direct(struct bge_softc *sc, int off, int val)
863 {
864 CSR_WRITE_4(sc, off, val);
865 }
866
867 static void
868 bge_writembx(struct bge_softc *sc, int off, int val)
869 {
870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
871 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
872
873 CSR_WRITE_4(sc, off, val);
874 }
875
876 static void
877 bge_writembx_flush(struct bge_softc *sc, int off, int val)
878 {
879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
880 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
881
882 CSR_WRITE_4_FLUSH(sc, off, val);
883 }
884
885 /*
886 * Clear all stale locks and select the lock for this driver instance.
887 */
888 void
889 bge_ape_lock_init(struct bge_softc *sc)
890 {
891 struct pci_attach_args *pa = &(sc->bge_pa);
892 uint32_t bit, regbase;
893 int i;
894
895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
896 regbase = BGE_APE_LOCK_GRANT;
897 else
898 regbase = BGE_APE_PER_LOCK_GRANT;
899
900 /* Clear any stale locks. */
901 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
902 switch (i) {
903 case BGE_APE_LOCK_PHY0:
904 case BGE_APE_LOCK_PHY1:
905 case BGE_APE_LOCK_PHY2:
906 case BGE_APE_LOCK_PHY3:
907 bit = BGE_APE_LOCK_GRANT_DRIVER0;
908 break;
909 default:
910 if (pa->pa_function == 0)
911 bit = BGE_APE_LOCK_GRANT_DRIVER0;
912 else
913 bit = (1 << pa->pa_function);
914 }
915 APE_WRITE_4(sc, regbase + 4 * i, bit);
916 }
917
918 /* Select the PHY lock based on the device's function number. */
919 switch (pa->pa_function) {
920 case 0:
921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
922 break;
923 case 1:
924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
925 break;
926 case 2:
927 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
928 break;
929 case 3:
930 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
931 break;
932 default:
933 printf("%s: PHY lock not supported on function\n",
934 device_xname(sc->bge_dev));
935 break;
936 }
937 }
938
939 /*
940 * Check for APE firmware, set flags, and print version info.
941 */
942 void
943 bge_ape_read_fw_ver(struct bge_softc *sc)
944 {
945 const char *fwtype;
946 uint32_t apedata, features;
947
948 /* Check for a valid APE signature in shared memory. */
949 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
950 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
951 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
952 return;
953 }
954
955 /* Check if APE firmware is running. */
956 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
957 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
958 printf("%s: APE signature found but FW status not ready! "
959 "0x%08x\n", device_xname(sc->bge_dev), apedata);
960 return;
961 }
962
963 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
964
965 /* Fetch the APE firwmare type and version. */
966 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
967 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
968 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
969 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
970 fwtype = "NCSI";
971 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
972 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
973 fwtype = "DASH";
974 } else
975 fwtype = "UNKN";
976
977 /* Print the APE firmware version. */
978 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype,
979 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
980 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
981 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
982 (apedata & BGE_APE_FW_VERSION_BLDMSK));
983 }
984
985 int
986 bge_ape_lock(struct bge_softc *sc, int locknum)
987 {
988 struct pci_attach_args *pa = &(sc->bge_pa);
989 uint32_t bit, gnt, req, status;
990 int i, off;
991
992 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
993 return (0);
994
995 /* Lock request/grant registers have different bases. */
996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) {
997 req = BGE_APE_LOCK_REQ;
998 gnt = BGE_APE_LOCK_GRANT;
999 } else {
1000 req = BGE_APE_PER_LOCK_REQ;
1001 gnt = BGE_APE_PER_LOCK_GRANT;
1002 }
1003
1004 off = 4 * locknum;
1005
1006 switch (locknum) {
1007 case BGE_APE_LOCK_GPIO:
1008 /* Lock required when using GPIO. */
1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
1010 return (0);
1011 if (pa->pa_function == 0)
1012 bit = BGE_APE_LOCK_REQ_DRIVER0;
1013 else
1014 bit = (1 << pa->pa_function);
1015 break;
1016 case BGE_APE_LOCK_GRC:
1017 /* Lock required to reset the device. */
1018 if (pa->pa_function == 0)
1019 bit = BGE_APE_LOCK_REQ_DRIVER0;
1020 else
1021 bit = (1 << pa->pa_function);
1022 break;
1023 case BGE_APE_LOCK_MEM:
1024 /* Lock required when accessing certain APE memory. */
1025 if (pa->pa_function == 0)
1026 bit = BGE_APE_LOCK_REQ_DRIVER0;
1027 else
1028 bit = (1 << pa->pa_function);
1029 break;
1030 case BGE_APE_LOCK_PHY0:
1031 case BGE_APE_LOCK_PHY1:
1032 case BGE_APE_LOCK_PHY2:
1033 case BGE_APE_LOCK_PHY3:
1034 /* Lock required when accessing PHYs. */
1035 bit = BGE_APE_LOCK_REQ_DRIVER0;
1036 break;
1037 default:
1038 return (EINVAL);
1039 }
1040
1041 /* Request a lock. */
1042 APE_WRITE_4_FLUSH(sc, req + off, bit);
1043
1044 /* Wait up to 1 second to acquire lock. */
1045 for (i = 0; i < 20000; i++) {
1046 status = APE_READ_4(sc, gnt + off);
1047 if (status == bit)
1048 break;
1049 DELAY(50);
1050 }
1051
1052 /* Handle any errors. */
1053 if (status != bit) {
1054 printf("%s: APE lock %d request failed! "
1055 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
1056 device_xname(sc->bge_dev),
1057 locknum, req + off, bit & 0xFFFF, gnt + off,
1058 status & 0xFFFF);
1059 /* Revoke the lock request. */
1060 APE_WRITE_4(sc, gnt + off, bit);
1061 return (EBUSY);
1062 }
1063
1064 return (0);
1065 }
1066
1067 void
1068 bge_ape_unlock(struct bge_softc *sc, int locknum)
1069 {
1070 struct pci_attach_args *pa = &(sc->bge_pa);
1071 uint32_t bit, gnt;
1072 int off;
1073
1074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
1075 return;
1076
1077 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
1078 gnt = BGE_APE_LOCK_GRANT;
1079 else
1080 gnt = BGE_APE_PER_LOCK_GRANT;
1081
1082 off = 4 * locknum;
1083
1084 switch (locknum) {
1085 case BGE_APE_LOCK_GPIO:
1086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
1087 return;
1088 if (pa->pa_function == 0)
1089 bit = BGE_APE_LOCK_GRANT_DRIVER0;
1090 else
1091 bit = (1 << pa->pa_function);
1092 break;
1093 case BGE_APE_LOCK_GRC:
1094 if (pa->pa_function == 0)
1095 bit = BGE_APE_LOCK_GRANT_DRIVER0;
1096 else
1097 bit = (1 << pa->pa_function);
1098 break;
1099 case BGE_APE_LOCK_MEM:
1100 if (pa->pa_function == 0)
1101 bit = BGE_APE_LOCK_GRANT_DRIVER0;
1102 else
1103 bit = (1 << pa->pa_function);
1104 break;
1105 case BGE_APE_LOCK_PHY0:
1106 case BGE_APE_LOCK_PHY1:
1107 case BGE_APE_LOCK_PHY2:
1108 case BGE_APE_LOCK_PHY3:
1109 bit = BGE_APE_LOCK_GRANT_DRIVER0;
1110 break;
1111 default:
1112 return;
1113 }
1114
1115 /* Write and flush for consecutive bge_ape_lock() */
1116 APE_WRITE_4_FLUSH(sc, gnt + off, bit);
1117 }
1118
1119 /*
1120 * Send an event to the APE firmware.
1121 */
1122 void
1123 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
1124 {
1125 uint32_t apedata;
1126 int i;
1127
1128 /* NCSI does not support APE events. */
1129 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
1130 return;
1131
1132 /* Wait up to 1ms for APE to service previous event. */
1133 for (i = 10; i > 0; i--) {
1134 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
1135 break;
1136 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
1137 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
1138 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
1139 BGE_APE_EVENT_STATUS_EVENT_PENDING);
1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
1141 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
1142 break;
1143 }
1144 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
1145 DELAY(100);
1146 }
1147 if (i == 0) {
1148 printf("%s: APE event 0x%08x send timed out\n",
1149 device_xname(sc->bge_dev), event);
1150 }
1151 }
1152
1153 void
1154 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
1155 {
1156 uint32_t apedata, event;
1157
1158 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
1159 return;
1160
1161 switch (kind) {
1162 case BGE_RESET_START:
1163 /* If this is the first load, clear the load counter. */
1164 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
1165 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
1166 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
1167 else {
1168 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
1169 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
1170 }
1171 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
1172 BGE_APE_HOST_SEG_SIG_MAGIC);
1173 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
1174 BGE_APE_HOST_SEG_LEN_MAGIC);
1175
1176 /* Add some version info if bge(4) supports it. */
1177 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
1178 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
1179 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
1180 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
1181 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
1182 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
1184 BGE_APE_HOST_DRVR_STATE_START);
1185 event = BGE_APE_EVENT_STATUS_STATE_START;
1186 break;
1187 case BGE_RESET_SHUTDOWN:
1188 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
1189 BGE_APE_HOST_DRVR_STATE_UNLOAD);
1190 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
1191 break;
1192 case BGE_RESET_SUSPEND:
1193 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
1194 break;
1195 default:
1196 return;
1197 }
1198
1199 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
1200 BGE_APE_EVENT_STATUS_STATE_CHNGE);
1201 }
1202
1203 static uint8_t
1204 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1205 {
1206 uint32_t access, byte = 0;
1207 int i;
1208
1209 /* Lock. */
1210 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1211 for (i = 0; i < 8000; i++) {
1212 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1213 break;
1214 DELAY(20);
1215 }
1216 if (i == 8000)
1217 return 1;
1218
1219 /* Enable access. */
1220 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1221 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1222
1223 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1224 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1225 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1226 DELAY(10);
1227 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1228 DELAY(10);
1229 break;
1230 }
1231 }
1232
1233 if (i == BGE_TIMEOUT * 10) {
1234 aprint_error_dev(sc->bge_dev, "nvram read timed out\n");
1235 return 1;
1236 }
1237
1238 /* Get result. */
1239 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1240
1241 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1242
1243 /* Disable access. */
1244 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1245
1246 /* Unlock. */
1247 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1248
1249 return 0;
1250 }
1251
1252 /*
1253 * Read a sequence of bytes from NVRAM.
1254 */
1255 static int
1256 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt)
1257 {
1258 int error = 0, i;
1259 uint8_t byte = 0;
1260
1261 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)
1262 return 1;
1263
1264 for (i = 0; i < cnt; i++) {
1265 error = bge_nvram_getbyte(sc, off + i, &byte);
1266 if (error)
1267 break;
1268 *(dest + i) = byte;
1269 }
1270
1271 return (error ? 1 : 0);
1272 }
1273
1274 /*
1275 * Read a byte of data stored in the EEPROM at address 'addr.' The
1276 * BCM570x supports both the traditional bitbang interface and an
1277 * auto access interface for reading the EEPROM. We use the auto
1278 * access method.
1279 */
1280 static uint8_t
1281 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1282 {
1283 int i;
1284 uint32_t byte = 0;
1285
1286 /*
1287 * Enable use of auto EEPROM access so we can avoid
1288 * having to use the bitbang method.
1289 */
1290 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1291
1292 /* Reset the EEPROM, load the clock period. */
1293 CSR_WRITE_4(sc, BGE_EE_ADDR,
1294 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1295 DELAY(20);
1296
1297 /* Issue the read EEPROM command. */
1298 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1299
1300 /* Wait for completion */
1301 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1302 DELAY(10);
1303 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1304 break;
1305 }
1306
1307 if (i == BGE_TIMEOUT * 10) {
1308 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n");
1309 return 1;
1310 }
1311
1312 /* Get result. */
1313 byte = CSR_READ_4(sc, BGE_EE_DATA);
1314
1315 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1316
1317 return 0;
1318 }
1319
1320 /*
1321 * Read a sequence of bytes from the EEPROM.
1322 */
1323 static int
1324 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt)
1325 {
1326 int error = 0, i;
1327 uint8_t byte = 0;
1328 char *dest = destv;
1329
1330 for (i = 0; i < cnt; i++) {
1331 error = bge_eeprom_getbyte(sc, off + i, &byte);
1332 if (error)
1333 break;
1334 *(dest + i) = byte;
1335 }
1336
1337 return (error ? 1 : 0);
1338 }
1339
1340 static int
1341 bge_miibus_readreg(device_t dev, int phy, int reg)
1342 {
1343 struct bge_softc *sc = device_private(dev);
1344 uint32_t val;
1345 uint32_t autopoll;
1346 int i;
1347
1348 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1349 return 0;
1350
1351 /* Reading with autopolling on may trigger PCI errors */
1352 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
1353 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1354 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
1355 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1356 DELAY(80);
1357 }
1358
1359 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1360 BGE_MIPHY(phy) | BGE_MIREG(reg));
1361
1362 for (i = 0; i < BGE_TIMEOUT; i++) {
1363 delay(10);
1364 val = CSR_READ_4(sc, BGE_MI_COMM);
1365 if (!(val & BGE_MICOMM_BUSY)) {
1366 DELAY(5);
1367 val = CSR_READ_4(sc, BGE_MI_COMM);
1368 break;
1369 }
1370 }
1371
1372 if (i == BGE_TIMEOUT) {
1373 aprint_error_dev(sc->bge_dev, "PHY read timed out\n");
1374 val = 0;
1375 goto done;
1376 }
1377
1378 done:
1379 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1380 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
1381 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1382 DELAY(80);
1383 }
1384
1385 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1386
1387 if (val & BGE_MICOMM_READFAIL)
1388 return 0;
1389
1390 return (val & 0xFFFF);
1391 }
1392
1393 static void
1394 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1395 {
1396 struct bge_softc *sc = device_private(dev);
1397 uint32_t autopoll;
1398 int i;
1399
1400 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 &&
1401 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1402 return;
1403
1404 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1405 return;
1406
1407 /* Reading with autopolling on may trigger PCI errors */
1408 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
1409 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1410 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL);
1411 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1412 DELAY(80);
1413 }
1414
1415 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1416 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1417
1418 for (i = 0; i < BGE_TIMEOUT; i++) {
1419 delay(10);
1420 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1421 delay(5);
1422 CSR_READ_4(sc, BGE_MI_COMM);
1423 break;
1424 }
1425 }
1426
1427 if (autopoll & BGE_MIMODE_AUTOPOLL) {
1428 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
1429 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
1430 delay(80);
1431 }
1432
1433 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1434
1435 if (i == BGE_TIMEOUT)
1436 aprint_error_dev(sc->bge_dev, "PHY read timed out\n");
1437 }
1438
1439 static void
1440 bge_miibus_statchg(struct ifnet *ifp)
1441 {
1442 struct bge_softc *sc = ifp->if_softc;
1443 struct mii_data *mii = &sc->bge_mii;
1444 uint32_t mac_mode, rx_mode, tx_mode;
1445
1446 /*
1447 * Get flow control negotiation result.
1448 */
1449 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
1450 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags)
1451 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
1452
1453 if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
1454 mii->mii_media_status & IFM_ACTIVE &&
1455 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1456 BGE_STS_SETBIT(sc, BGE_STS_LINK);
1457 else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
1458 (!(mii->mii_media_status & IFM_ACTIVE) ||
1459 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
1460 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
1461
1462 if (!BGE_STS_BIT(sc, BGE_STS_LINK))
1463 return;
1464
1465 /* Set the port mode (MII/GMII) to match the link speed. */
1466 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1467 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1468 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1469 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1470 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1471 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1472 mac_mode |= BGE_PORTMODE_GMII;
1473 else
1474 mac_mode |= BGE_PORTMODE_MII;
1475
1476 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1477 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1478 if ((mii->mii_media_active & IFM_FDX) != 0) {
1479 if (sc->bge_flowflags & IFM_ETH_TXPAUSE)
1480 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1481 if (sc->bge_flowflags & IFM_ETH_RXPAUSE)
1482 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1483 } else
1484 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1485
1486 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode);
1487 DELAY(40);
1488 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1489 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1490 }
1491
1492 /*
1493 * Update rx threshold levels to values in a particular slot
1494 * of the interrupt-mitigation table bge_rx_threshes.
1495 */
1496 static void
1497 bge_set_thresh(struct ifnet *ifp, int lvl)
1498 {
1499 struct bge_softc *sc = ifp->if_softc;
1500 int s;
1501
1502 /* For now, just save the new Rx-intr thresholds and record
1503 * that a threshold update is pending. Updating the hardware
1504 * registers here (even at splhigh()) is observed to
1505 * occasionaly cause glitches where Rx-interrupts are not
1506 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05
1507 */
1508 s = splnet();
1509 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks;
1510 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds;
1511 sc->bge_pending_rxintr_change = 1;
1512 splx(s);
1513 }
1514
1515
1516 /*
1517 * Update Rx thresholds of all bge devices
1518 */
1519 static void
1520 bge_update_all_threshes(int lvl)
1521 {
1522 struct ifnet *ifp;
1523 const char * const namebuf = "bge";
1524 int namelen;
1525
1526 if (lvl < 0)
1527 lvl = 0;
1528 else if (lvl >= NBGE_RX_THRESH)
1529 lvl = NBGE_RX_THRESH - 1;
1530
1531 namelen = strlen(namebuf);
1532 /*
1533 * Now search all the interfaces for this name/number
1534 */
1535 IFNET_FOREACH(ifp) {
1536 if (strncmp(ifp->if_xname, namebuf, namelen) != 0)
1537 continue;
1538 /* We got a match: update if doing auto-threshold-tuning */
1539 if (bge_auto_thresh)
1540 bge_set_thresh(ifp, lvl);
1541 }
1542 }
1543
1544 /*
1545 * Handle events that have triggered interrupts.
1546 */
1547 static void
1548 bge_handle_events(struct bge_softc *sc)
1549 {
1550
1551 return;
1552 }
1553
1554 /*
1555 * Memory management for jumbo frames.
1556 */
1557
1558 static int
1559 bge_alloc_jumbo_mem(struct bge_softc *sc)
1560 {
1561 char *ptr, *kva;
1562 bus_dma_segment_t seg;
1563 int i, rseg, state, error;
1564 struct bge_jpool_entry *entry;
1565
1566 state = error = 0;
1567
1568 /* Grab a big chunk o' storage. */
1569 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
1570 &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
1571 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n");
1572 return ENOBUFS;
1573 }
1574
1575 state = 1;
1576 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva,
1577 BUS_DMA_NOWAIT)) {
1578 aprint_error_dev(sc->bge_dev,
1579 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM);
1580 error = ENOBUFS;
1581 goto out;
1582 }
1583
1584 state = 2;
1585 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
1586 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) {
1587 aprint_error_dev(sc->bge_dev, "can't create DMA map\n");
1588 error = ENOBUFS;
1589 goto out;
1590 }
1591
1592 state = 3;
1593 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
1594 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) {
1595 aprint_error_dev(sc->bge_dev, "can't load DMA map\n");
1596 error = ENOBUFS;
1597 goto out;
1598 }
1599
1600 state = 4;
1601 sc->bge_cdata.bge_jumbo_buf = (void *)kva;
1602 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf));
1603
1604 SLIST_INIT(&sc->bge_jfree_listhead);
1605 SLIST_INIT(&sc->bge_jinuse_listhead);
1606
1607 /*
1608 * Now divide it up into 9K pieces and save the addresses
1609 * in an array.
1610 */
1611 ptr = sc->bge_cdata.bge_jumbo_buf;
1612 for (i = 0; i < BGE_JSLOTS; i++) {
1613 sc->bge_cdata.bge_jslots[i] = ptr;
1614 ptr += BGE_JLEN;
1615 entry = malloc(sizeof(struct bge_jpool_entry),
1616 M_DEVBUF, M_NOWAIT);
1617 if (entry == NULL) {
1618 aprint_error_dev(sc->bge_dev,
1619 "no memory for jumbo buffer queue!\n");
1620 error = ENOBUFS;
1621 goto out;
1622 }
1623 entry->slot = i;
1624 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
1625 entry, jpool_entries);
1626 }
1627 out:
1628 if (error != 0) {
1629 switch (state) {
1630 case 4:
1631 bus_dmamap_unload(sc->bge_dmatag,
1632 sc->bge_cdata.bge_rx_jumbo_map);
1633 case 3:
1634 bus_dmamap_destroy(sc->bge_dmatag,
1635 sc->bge_cdata.bge_rx_jumbo_map);
1636 case 2:
1637 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
1638 case 1:
1639 bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
1640 break;
1641 default:
1642 break;
1643 }
1644 }
1645
1646 return error;
1647 }
1648
1649 /*
1650 * Allocate a jumbo buffer.
1651 */
1652 static void *
1653 bge_jalloc(struct bge_softc *sc)
1654 {
1655 struct bge_jpool_entry *entry;
1656
1657 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
1658
1659 if (entry == NULL) {
1660 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n");
1661 return NULL;
1662 }
1663
1664 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
1665 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
1666 return (sc->bge_cdata.bge_jslots[entry->slot]);
1667 }
1668
1669 /*
1670 * Release a jumbo buffer.
1671 */
1672 static void
1673 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
1674 {
1675 struct bge_jpool_entry *entry;
1676 struct bge_softc *sc;
1677 int i, s;
1678
1679 /* Extract the softc struct pointer. */
1680 sc = (struct bge_softc *)arg;
1681
1682 if (sc == NULL)
1683 panic("bge_jfree: can't find softc pointer!");
1684
1685 /* calculate the slot this buffer belongs to */
1686
1687 i = ((char *)buf
1688 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
1689
1690 if ((i < 0) || (i >= BGE_JSLOTS))
1691 panic("bge_jfree: asked to free buffer that we don't manage!");
1692
1693 s = splvm();
1694 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
1695 if (entry == NULL)
1696 panic("bge_jfree: buffer not in use!");
1697 entry->slot = i;
1698 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
1699 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
1700
1701 if (__predict_true(m != NULL))
1702 pool_cache_put(mb_cache, m);
1703 splx(s);
1704 }
1705
1706
1707 /*
1708 * Initialize a standard receive ring descriptor.
1709 */
1710 static int
1711 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m,
1712 bus_dmamap_t dmamap)
1713 {
1714 struct mbuf *m_new = NULL;
1715 struct bge_rx_bd *r;
1716 int error;
1717
1718 if (dmamap == NULL) {
1719 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
1720 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap);
1721 if (error != 0)
1722 return error;
1723 }
1724
1725 sc->bge_cdata.bge_rx_std_map[i] = dmamap;
1726
1727 if (m == NULL) {
1728 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1729 if (m_new == NULL)
1730 return ENOBUFS;
1731
1732 MCLGET(m_new, M_DONTWAIT);
1733 if (!(m_new->m_flags & M_EXT)) {
1734 m_freem(m_new);
1735 return ENOBUFS;
1736 }
1737 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1738
1739 } else {
1740 m_new = m;
1741 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1742 m_new->m_data = m_new->m_ext.ext_buf;
1743 }
1744 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
1745 m_adj(m_new, ETHER_ALIGN);
1746 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new,
1747 BUS_DMA_READ|BUS_DMA_NOWAIT))
1748 return ENOBUFS;
1749 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
1750 BUS_DMASYNC_PREREAD);
1751
1752 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
1753 r = &sc->bge_rdata->bge_rx_std_ring[i];
1754 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr);
1755 r->bge_flags = BGE_RXBDFLAG_END;
1756 r->bge_len = m_new->m_len;
1757 r->bge_idx = i;
1758
1759 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1760 offsetof(struct bge_ring_data, bge_rx_std_ring) +
1761 i * sizeof (struct bge_rx_bd),
1762 sizeof (struct bge_rx_bd),
1763 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1764
1765 return 0;
1766 }
1767
1768 /*
1769 * Initialize a jumbo receive ring descriptor. This allocates
1770 * a jumbo buffer from the pool managed internally by the driver.
1771 */
1772 static int
1773 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
1774 {
1775 struct mbuf *m_new = NULL;
1776 struct bge_rx_bd *r;
1777 void *buf = NULL;
1778
1779 if (m == NULL) {
1780
1781 /* Allocate the mbuf. */
1782 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1783 if (m_new == NULL)
1784 return ENOBUFS;
1785
1786 /* Allocate the jumbo buffer */
1787 buf = bge_jalloc(sc);
1788 if (buf == NULL) {
1789 m_freem(m_new);
1790 aprint_error_dev(sc->bge_dev,
1791 "jumbo allocation failed -- packet dropped!\n");
1792 return ENOBUFS;
1793 }
1794
1795 /* Attach the buffer to the mbuf. */
1796 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
1797 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF,
1798 bge_jfree, sc);
1799 m_new->m_flags |= M_EXT_RW;
1800 } else {
1801 m_new = m;
1802 buf = m_new->m_data = m_new->m_ext.ext_buf;
1803 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1804 }
1805 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
1806 m_adj(m_new, ETHER_ALIGN);
1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
1808 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN,
1809 BUS_DMASYNC_PREREAD);
1810 /* Set up the descriptor. */
1811 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
1812 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
1813 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
1814 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1815 r->bge_len = m_new->m_len;
1816 r->bge_idx = i;
1817
1818 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
1819 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
1820 i * sizeof (struct bge_rx_bd),
1821 sizeof (struct bge_rx_bd),
1822 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1823
1824 return 0;
1825 }
1826
1827 /*
1828 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1829 * that's 1MB or memory, which is a lot. For now, we fill only the first
1830 * 256 ring entries and hope that our CPU is fast enough to keep up with
1831 * the NIC.
1832 */
1833 static int
1834 bge_init_rx_ring_std(struct bge_softc *sc)
1835 {
1836 int i;
1837
1838 if (sc->bge_flags & BGEF_RXRING_VALID)
1839 return 0;
1840
1841 for (i = 0; i < BGE_SSLOTS; i++) {
1842 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
1843 return ENOBUFS;
1844 }
1845
1846 sc->bge_std = i - 1;
1847 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1848
1849 sc->bge_flags |= BGEF_RXRING_VALID;
1850
1851 return 0;
1852 }
1853
1854 static void
1855 bge_free_rx_ring_std(struct bge_softc *sc)
1856 {
1857 int i;
1858
1859 if (!(sc->bge_flags & BGEF_RXRING_VALID))
1860 return;
1861
1862 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1863 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1864 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1865 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1866 bus_dmamap_destroy(sc->bge_dmatag,
1867 sc->bge_cdata.bge_rx_std_map[i]);
1868 }
1869 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0,
1870 sizeof(struct bge_rx_bd));
1871 }
1872
1873 sc->bge_flags &= ~BGEF_RXRING_VALID;
1874 }
1875
1876 static int
1877 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1878 {
1879 int i;
1880 volatile struct bge_rcb *rcb;
1881
1882 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID)
1883 return 0;
1884
1885 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1886 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1887 return ENOBUFS;
1888 }
1889
1890 sc->bge_jumbo = i - 1;
1891 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID;
1892
1893 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1894 rcb->bge_maxlen_flags = 0;
1895 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1896
1897 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1898
1899 return 0;
1900 }
1901
1902 static void
1903 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1904 {
1905 int i;
1906
1907 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID))
1908 return;
1909
1910 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1911 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1912 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1913 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1914 }
1915 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0,
1916 sizeof(struct bge_rx_bd));
1917 }
1918
1919 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID;
1920 }
1921
1922 static void
1923 bge_free_tx_ring(struct bge_softc *sc)
1924 {
1925 int i;
1926 struct txdmamap_pool_entry *dma;
1927
1928 if (!(sc->bge_flags & BGEF_TXRING_VALID))
1929 return;
1930
1931 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1932 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1933 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1934 sc->bge_cdata.bge_tx_chain[i] = NULL;
1935 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
1936 link);
1937 sc->txdma[i] = 0;
1938 }
1939 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0,
1940 sizeof(struct bge_tx_bd));
1941 }
1942
1943 while ((dma = SLIST_FIRST(&sc->txdma_list))) {
1944 SLIST_REMOVE_HEAD(&sc->txdma_list, link);
1945 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
1946 free(dma, M_DEVBUF);
1947 }
1948
1949 sc->bge_flags &= ~BGEF_TXRING_VALID;
1950 }
1951
1952 static int
1953 bge_init_tx_ring(struct bge_softc *sc)
1954 {
1955 struct ifnet *ifp = &sc->ethercom.ec_if;
1956 int i;
1957 bus_dmamap_t dmamap;
1958 bus_size_t maxsegsz;
1959 struct txdmamap_pool_entry *dma;
1960
1961 if (sc->bge_flags & BGEF_TXRING_VALID)
1962 return 0;
1963
1964 sc->bge_txcnt = 0;
1965 sc->bge_tx_saved_considx = 0;
1966
1967 /* Initialize transmit producer index for host-memory send ring. */
1968 sc->bge_tx_prodidx = 0;
1969 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1970 /* 5700 b2 errata */
1971 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
1972 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1973
1974 /* NIC-memory send ring not used; initialize to zero. */
1975 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1976 /* 5700 b2 errata */
1977 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
1978 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1979
1980 /* Limit DMA segment size for some chips */
1981 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) &&
1982 (ifp->if_mtu <= ETHERMTU))
1983 maxsegsz = 2048;
1984 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
1985 maxsegsz = 4096;
1986 else
1987 maxsegsz = ETHER_MAX_LEN_JUMBO;
1988 SLIST_INIT(&sc->txdma_list);
1989 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1990 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX,
1991 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT,
1992 &dmamap))
1993 return ENOBUFS;
1994 if (dmamap == NULL)
1995 panic("dmamap NULL in bge_init_tx_ring");
1996 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
1997 if (dma == NULL) {
1998 aprint_error_dev(sc->bge_dev,
1999 "can't alloc txdmamap_pool_entry\n");
2000 bus_dmamap_destroy(sc->bge_dmatag, dmamap);
2001 return ENOMEM;
2002 }
2003 dma->dmamap = dmamap;
2004 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
2005 }
2006
2007 sc->bge_flags |= BGEF_TXRING_VALID;
2008
2009 return 0;
2010 }
2011
2012 static void
2013 bge_setmulti(struct bge_softc *sc)
2014 {
2015 struct ethercom *ac = &sc->ethercom;
2016 struct ifnet *ifp = &ac->ec_if;
2017 struct ether_multi *enm;
2018 struct ether_multistep step;
2019 uint32_t hashes[4] = { 0, 0, 0, 0 };
2020 uint32_t h;
2021 int i;
2022
2023 if (ifp->if_flags & IFF_PROMISC)
2024 goto allmulti;
2025
2026 /* Now program new ones. */
2027 ETHER_FIRST_MULTI(step, ac, enm);
2028 while (enm != NULL) {
2029 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2030 /*
2031 * We must listen to a range of multicast addresses.
2032 * For now, just accept all multicasts, rather than
2033 * trying to set only those filter bits needed to match
2034 * the range. (At this time, the only use of address
2035 * ranges is for IP multicast routing, for which the
2036 * range is big enough to require all bits set.)
2037 */
2038 goto allmulti;
2039 }
2040
2041 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
2042
2043 /* Just want the 7 least-significant bits. */
2044 h &= 0x7f;
2045
2046 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
2047 ETHER_NEXT_MULTI(step, enm);
2048 }
2049
2050 ifp->if_flags &= ~IFF_ALLMULTI;
2051 goto setit;
2052
2053 allmulti:
2054 ifp->if_flags |= IFF_ALLMULTI;
2055 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff;
2056
2057 setit:
2058 for (i = 0; i < 4; i++)
2059 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
2060 }
2061
2062 static void
2063 bge_sig_pre_reset(struct bge_softc *sc, int type)
2064 {
2065
2066 /*
2067 * Some chips don't like this so only do this if ASF is enabled
2068 */
2069 if (sc->bge_asf_mode)
2070 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
2071
2072 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
2073 switch (type) {
2074 case BGE_RESET_START:
2075 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
2076 BGE_FW_DRV_STATE_START);
2077 break;
2078 case BGE_RESET_SHUTDOWN:
2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
2080 BGE_FW_DRV_STATE_UNLOAD);
2081 break;
2082 case BGE_RESET_SUSPEND:
2083 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
2084 BGE_FW_DRV_STATE_SUSPEND);
2085 break;
2086 }
2087 }
2088
2089 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
2090 bge_ape_driver_state_change(sc, type);
2091 }
2092
2093 static void
2094 bge_sig_post_reset(struct bge_softc *sc, int type)
2095 {
2096
2097 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
2098 switch (type) {
2099 case BGE_RESET_START:
2100 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
2101 BGE_FW_DRV_STATE_START_DONE);
2102 /* START DONE */
2103 break;
2104 case BGE_RESET_SHUTDOWN:
2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
2106 BGE_FW_DRV_STATE_UNLOAD_DONE);
2107 break;
2108 }
2109 }
2110
2111 if (type == BGE_RESET_SHUTDOWN)
2112 bge_ape_driver_state_change(sc, type);
2113 }
2114
2115 static void
2116 bge_sig_legacy(struct bge_softc *sc, int type)
2117 {
2118
2119 if (sc->bge_asf_mode) {
2120 switch (type) {
2121 case BGE_RESET_START:
2122 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
2123 BGE_FW_DRV_STATE_START);
2124 break;
2125 case BGE_RESET_SHUTDOWN:
2126 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
2127 BGE_FW_DRV_STATE_UNLOAD);
2128 break;
2129 }
2130 }
2131 }
2132
2133 static void
2134 bge_wait_for_event_ack(struct bge_softc *sc)
2135 {
2136 int i;
2137
2138 /* wait up to 2500usec */
2139 for (i = 0; i < 250; i++) {
2140 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
2141 BGE_RX_CPU_DRV_EVENT))
2142 break;
2143 DELAY(10);
2144 }
2145 }
2146
2147 static void
2148 bge_stop_fw(struct bge_softc *sc)
2149 {
2150
2151 if (sc->bge_asf_mode) {
2152 bge_wait_for_event_ack(sc);
2153
2154 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
2155 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT,
2156 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
2157
2158 bge_wait_for_event_ack(sc);
2159 }
2160 }
2161
2162 static int
2163 bge_poll_fw(struct bge_softc *sc)
2164 {
2165 uint32_t val;
2166 int i;
2167
2168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
2169 for (i = 0; i < BGE_TIMEOUT; i++) {
2170 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2171 if (val & BGE_VCPU_STATUS_INIT_DONE)
2172 break;
2173 DELAY(100);
2174 }
2175 if (i >= BGE_TIMEOUT) {
2176 aprint_error_dev(sc->bge_dev, "reset timed out\n");
2177 return -1;
2178 }
2179 } else {
2180 /*
2181 * Poll the value location we just wrote until
2182 * we see the 1's complement of the magic number.
2183 * This indicates that the firmware initialization
2184 * is complete.
2185 * XXX 1000ms for Flash and 10000ms for SEEPROM.
2186 */
2187 for (i = 0; i < BGE_TIMEOUT; i++) {
2188 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
2189 if (val == ~BGE_SRAM_FW_MB_MAGIC)
2190 break;
2191 DELAY(10);
2192 }
2193
2194 if ((i >= BGE_TIMEOUT)
2195 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) {
2196 aprint_error_dev(sc->bge_dev,
2197 "firmware handshake timed out, val = %x\n", val);
2198 return -1;
2199 }
2200 }
2201
2202 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) {
2203 /* tg3 says we have to wait extra time */
2204 delay(10 * 1000);
2205 }
2206
2207 return 0;
2208 }
2209
2210 int
2211 bge_phy_addr(struct bge_softc *sc)
2212 {
2213 struct pci_attach_args *pa = &(sc->bge_pa);
2214 int phy_addr = 1;
2215
2216 /*
2217 * PHY address mapping for various devices.
2218 *
2219 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2220 * ---------+-------+-------+-------+-------+
2221 * BCM57XX | 1 | X | X | X |
2222 * BCM5704 | 1 | X | 1 | X |
2223 * BCM5717 | 1 | 8 | 2 | 9 |
2224 * BCM5719 | 1 | 8 | 2 | 9 |
2225 * BCM5720 | 1 | 8 | 2 | 9 |
2226 *
2227 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
2228 * ---------+-------+-------+-------+-------+
2229 * BCM57XX | X | X | X | X |
2230 * BCM5704 | X | X | X | X |
2231 * BCM5717 | X | X | X | X |
2232 * BCM5719 | 3 | 10 | 4 | 11 |
2233 * BCM5720 | X | X | X | X |
2234 *
2235 * Other addresses may respond but they are not
2236 * IEEE compliant PHYs and should be ignored.
2237 */
2238 switch (BGE_ASICREV(sc->bge_chipid)) {
2239 case BGE_ASICREV_BCM5717:
2240 case BGE_ASICREV_BCM5719:
2241 case BGE_ASICREV_BCM5720:
2242 phy_addr = pa->pa_function;
2243 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
2244 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) &
2245 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1;
2246 } else {
2247 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2248 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1;
2249 }
2250 }
2251
2252 return phy_addr;
2253 }
2254
2255 /*
2256 * Do endian, PCI and DMA initialization. Also check the on-board ROM
2257 * self-test results.
2258 */
2259 static int
2260 bge_chipinit(struct bge_softc *sc)
2261 {
2262 uint32_t dma_rw_ctl, mode_ctl, reg;
2263 int i;
2264
2265 /* Set endianness before we access any non-PCI registers. */
2266 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
2267 BGE_INIT);
2268
2269 /*
2270 * Clear the MAC statistics block in the NIC's
2271 * internal memory.
2272 */
2273 for (i = BGE_STATS_BLOCK;
2274 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
2275 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0);
2276
2277 for (i = BGE_STATUS_BLOCK;
2278 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
2279 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0);
2280
2281 /* 5717 workaround from tg3 */
2282 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2283 /* Save */
2284 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2285
2286 /* Temporary modify MODE_CTL to control TLP */
2287 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
2288 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1);
2289
2290 /* Control TLP */
2291 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2292 BGE_TLP_PHYCTL1);
2293 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1,
2294 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD);
2295
2296 /* Restore */
2297 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2298 }
2299
2300 if (BGE_IS_57765_FAMILY(sc)) {
2301 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) {
2302 /* Save */
2303 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2304
2305 /* Temporary modify MODE_CTL to control TLP */
2306 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
2307 CSR_WRITE_4(sc, BGE_MODE_CTL,
2308 reg | BGE_MODECTL_PCIE_TLPADDR1);
2309
2310 /* Control TLP */
2311 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2312 BGE_TLP_PHYCTL5);
2313 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5,
2314 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ);
2315
2316 /* Restore */
2317 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2318 }
2319 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) {
2320 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
2321 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
2322 reg | BGE_CPMU_PADRNG_CTL_RDIV2);
2323
2324 /* Save */
2325 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2326
2327 /* Temporary modify MODE_CTL to control TLP */
2328 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;
2329 CSR_WRITE_4(sc, BGE_MODE_CTL,
2330 reg | BGE_MODECTL_PCIE_TLPADDR0);
2331
2332 /* Control TLP */
2333 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2334 BGE_TLP_FTSMAX);
2335 reg &= ~BGE_TLP_FTSMAX_MSK;
2336 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX,
2337 reg | BGE_TLP_FTSMAX_VAL);
2338
2339 /* Restore */
2340 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2341 }
2342
2343 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
2344 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
2345 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
2346 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);
2347 }
2348
2349 /* Set up the PCI DMA control register. */
2350 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
2351 if (sc->bge_flags & BGEF_PCIE) {
2352 /* Read watermark not used, 128 bytes for write. */
2353 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n",
2354 device_xname(sc->bge_dev)));
2355 if (sc->bge_mps >= 256)
2356 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
2357 else
2358 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
2359 } else if (sc->bge_flags & BGEF_PCIX) {
2360 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n",
2361 device_xname(sc->bge_dev)));
2362 /* PCI-X bus */
2363 if (BGE_IS_5714_FAMILY(sc)) {
2364 /* 256 bytes for read and write. */
2365 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
2366 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
2367
2368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780)
2369 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
2370 else
2371 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
2372 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
2373 /*
2374 * In the BCM5703, the DMA read watermark should
2375 * be set to less than or equal to the maximum
2376 * memory read byte count of the PCI-X command
2377 * register.
2378 */
2379 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
2380 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
2381 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
2382 /* 1536 bytes for read, 384 bytes for write. */
2383 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
2384 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
2385 } else {
2386 /* 384 bytes for read and write. */
2387 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
2388 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
2389 (0x0F);
2390 }
2391
2392 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
2393 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
2394 uint32_t tmp;
2395
2396 /* Set ONEDMA_ATONCE for hardware workaround. */
2397 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
2398 if (tmp == 6 || tmp == 7)
2399 dma_rw_ctl |=
2400 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
2401
2402 /* Set PCI-X DMA write workaround. */
2403 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
2404 }
2405 } else {
2406 /* Conventional PCI bus: 256 bytes for read and write. */
2407 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n",
2408 device_xname(sc->bge_dev)));
2409 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
2410 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
2411
2412 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 &&
2413 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750)
2414 dma_rw_ctl |= 0x0F;
2415 }
2416
2417 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
2418 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701)
2419 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
2420 BGE_PCIDMARWCTL_ASRT_ALL_BE;
2421
2422 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
2423 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
2424 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
2425
2426 if (BGE_IS_57765_PLUS(sc)) {
2427 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
2428 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
2429 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
2430
2431 /*
2432 * Enable HW workaround for controllers that misinterpret
2433 * a status tag update and leave interrupts permanently
2434 * disabled.
2435 */
2436 if (!BGE_IS_57765_FAMILY(sc) &&
2437 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717)
2438 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
2439 }
2440
2441 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL,
2442 dma_rw_ctl);
2443
2444 /*
2445 * Set up general mode register.
2446 */
2447 mode_ctl = BGE_DMA_SWAP_OPTIONS;
2448 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
2449 /* Retain Host-2-BMC settings written by APE firmware. */
2450 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
2451 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
2452 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
2453 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
2454 }
2455 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
2456 BGE_MODECTL_TX_NO_PHDR_CSUM;
2457
2458 /*
2459 * BCM5701 B5 have a bug causing data corruption when using
2460 * 64-bit DMA reads, which can be terminated early and then
2461 * completed later as 32-bit accesses, in combination with
2462 * certain bridges.
2463 */
2464 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
2465 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
2466 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
2467
2468 /*
2469 * Tell the firmware the driver is running
2470 */
2471 if (sc->bge_asf_mode & ASF_STACKUP)
2472 mode_ctl |= BGE_MODECTL_STACKUP;
2473
2474 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2475
2476 /*
2477 * Disable memory write invalidate. Apparently it is not supported
2478 * properly by these devices.
2479 */
2480 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG,
2481 PCI_COMMAND_INVALIDATE_ENABLE);
2482
2483 #ifdef __brokenalpha__
2484 /*
2485 * Must insure that we do not cross an 8K (bytes) boundary
2486 * for DMA reads. Our highest limit is 1K bytes. This is a
2487 * restriction on some ALPHA platforms with early revision
2488 * 21174 PCI chipsets, such as the AlphaPC 164lx
2489 */
2490 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
2491 #endif
2492
2493 /* Set the timer prescaler (always 66MHz) */
2494 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
2495
2496 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
2497 DELAY(40); /* XXX */
2498
2499 /* Put PHY into ready state */
2500 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
2501 DELAY(40);
2502 }
2503
2504 return 0;
2505 }
2506
2507 static int
2508 bge_blockinit(struct bge_softc *sc)
2509 {
2510 volatile struct bge_rcb *rcb;
2511 bus_size_t rcb_addr;
2512 struct ifnet *ifp = &sc->ethercom.ec_if;
2513 bge_hostaddr taddr;
2514 uint32_t dmactl, mimode, val;
2515 int i, limit;
2516
2517 /*
2518 * Initialize the memory window pointer register so that
2519 * we can access the first 32K of internal NIC RAM. This will
2520 * allow us to set up the TX send ring RCBs and the RX return
2521 * ring RCBs, plus other things which live in NIC memory.
2522 */
2523 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0);
2524
2525 if (!BGE_IS_5705_PLUS(sc)) {
2526 /* 57XX step 33 */
2527 /* Configure mbuf memory pool */
2528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
2529 BGE_BUFFPOOL_1);
2530
2531 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
2532 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
2533 else
2534 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
2535
2536 /* 57XX step 34 */
2537 /* Configure DMA resource pool */
2538 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
2539 BGE_DMA_DESCRIPTORS);
2540 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2541 }
2542
2543 /* 5718 step 11, 57XX step 35 */
2544 /*
2545 * Configure mbuf pool watermarks. New broadcom docs strongly
2546 * recommend these.
2547 */
2548 if (BGE_IS_5717_PLUS(sc)) {
2549 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2550 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2551 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2552 } else if (BGE_IS_5705_PLUS(sc)) {
2553 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2554
2555 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
2556 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2557 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2558 } else {
2559 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2560 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2561 }
2562 } else {
2563 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2564 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2565 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2566 }
2567
2568 /* 57XX step 36 */
2569 /* Configure DMA resource watermarks */
2570 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2571 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2572
2573 /* 5718 step 13, 57XX step 38 */
2574 /* Enable buffer manager */
2575 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN;
2576 /*
2577 * Change the arbitration algorithm of TXMBUF read request to
2578 * round-robin instead of priority based for BCM5719. When
2579 * TXFIFO is almost empty, RDMA will hold its request until
2580 * TXFIFO is not almost empty.
2581 */
2582 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
2583 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2584 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2585 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2586 sc->bge_chipid == BGE_CHIPID_BCM5720_A0)
2587 val |= BGE_BMANMODE_LOMBUF_ATTN;
2588 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2589
2590 /* 57XX step 39 */
2591 /* Poll for buffer manager start indication */
2592 for (i = 0; i < BGE_TIMEOUT * 2; i++) {
2593 DELAY(10);
2594 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2595 break;
2596 }
2597
2598 if (i == BGE_TIMEOUT * 2) {
2599 aprint_error_dev(sc->bge_dev,
2600 "buffer manager failed to start\n");
2601 return ENXIO;
2602 }
2603
2604 /* 57XX step 40 */
2605 /* Enable flow-through queues */
2606 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2607 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2608
2609 /* Wait until queue initialization is complete */
2610 for (i = 0; i < BGE_TIMEOUT * 2; i++) {
2611 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2612 break;
2613 DELAY(10);
2614 }
2615
2616 if (i == BGE_TIMEOUT * 2) {
2617 aprint_error_dev(sc->bge_dev,
2618 "flow-through queue init failed\n");
2619 return ENXIO;
2620 }
2621
2622 /*
2623 * Summary of rings supported by the controller:
2624 *
2625 * Standard Receive Producer Ring
2626 * - This ring is used to feed receive buffers for "standard"
2627 * sized frames (typically 1536 bytes) to the controller.
2628 *
2629 * Jumbo Receive Producer Ring
2630 * - This ring is used to feed receive buffers for jumbo sized
2631 * frames (i.e. anything bigger than the "standard" frames)
2632 * to the controller.
2633 *
2634 * Mini Receive Producer Ring
2635 * - This ring is used to feed receive buffers for "mini"
2636 * sized frames to the controller.
2637 * - This feature required external memory for the controller
2638 * but was never used in a production system. Should always
2639 * be disabled.
2640 *
2641 * Receive Return Ring
2642 * - After the controller has placed an incoming frame into a
2643 * receive buffer that buffer is moved into a receive return
2644 * ring. The driver is then responsible to passing the
2645 * buffer up to the stack. Many versions of the controller
2646 * support multiple RR rings.
2647 *
2648 * Send Ring
2649 * - This ring is used for outgoing frames. Many versions of
2650 * the controller support multiple send rings.
2651 */
2652
2653 /* 5718 step 15, 57XX step 41 */
2654 /* Initialize the standard RX ring control block */
2655 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
2656 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
2657 /* 5718 step 16 */
2658 if (BGE_IS_57765_PLUS(sc)) {
2659 /*
2660 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2661 * Bits 15-2 : Maximum RX frame size
2662 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2663 * Bit 0 : Reserved
2664 */
2665 rcb->bge_maxlen_flags =
2666 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2667 } else if (BGE_IS_5705_PLUS(sc)) {
2668 /*
2669 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2670 * Bits 15-2 : Reserved (should be 0)
2671 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2672 * Bit 0 : Reserved
2673 */
2674 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2675 } else {
2676 /*
2677 * Ring size is always XXX entries
2678 * Bits 31-16: Maximum RX frame size
2679 * Bits 15-2 : Reserved (should be 0)
2680 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2681 * Bit 0 : Reserved
2682 */
2683 rcb->bge_maxlen_flags =
2684 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2685 }
2686 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2687 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
2688 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
2689 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2690 else
2691 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2692 /* Write the standard receive producer ring control block. */
2693 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2694 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2695 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2696 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2697
2698 /* Reset the standard receive producer ring producer index. */
2699 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2700
2701 /* 57XX step 42 */
2702 /*
2703 * Initialize the jumbo RX ring control block
2704 * We set the 'ring disabled' bit in the flags
2705 * field until we're actually ready to start
2706 * using this ring (i.e. once we set the MTU
2707 * high enough to require it).
2708 */
2709 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2710 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
2711 BGE_HOSTADDR(rcb->bge_hostaddr,
2712 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
2713 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2714 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2715 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2716 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
2717 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
2718 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2719 else
2720 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2721 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2722 rcb->bge_hostaddr.bge_addr_hi);
2723 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2724 rcb->bge_hostaddr.bge_addr_lo);
2725 /* Program the jumbo receive producer ring RCB parameters. */
2726 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2727 rcb->bge_maxlen_flags);
2728 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2729 /* Reset the jumbo receive producer ring producer index. */
2730 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2731 }
2732
2733 /* 57XX step 43 */
2734 /* Disable the mini receive producer ring RCB. */
2735 if (BGE_IS_5700_FAMILY(sc)) {
2736 /* Set up dummy disabled mini ring RCB */
2737 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
2738 rcb->bge_maxlen_flags =
2739 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2740 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2741 rcb->bge_maxlen_flags);
2742 /* Reset the mini receive producer ring producer index. */
2743 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2744
2745 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
2746 offsetof(struct bge_ring_data, bge_info),
2747 sizeof (struct bge_gib),
2748 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2749 }
2750
2751 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2752 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
2753 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2754 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2755 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2756 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2757 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2758 }
2759 /* 5718 step 14, 57XX step 44 */
2760 /*
2761 * The BD ring replenish thresholds control how often the
2762 * hardware fetches new BD's from the producer rings in host
2763 * memory. Setting the value too low on a busy system can
2764 * starve the hardware and recue the throughpout.
2765 *
2766 * Set the BD ring replenish thresholds. The recommended
2767 * values are 1/8th the number of descriptors allocated to
2768 * each ring, but since we try to avoid filling the entire
2769 * ring we set these to the minimal value of 8. This needs to
2770 * be done on several of the supported chip revisions anyway,
2771 * to work around HW bugs.
2772 */
2773 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8);
2774 if (BGE_IS_JUMBO_CAPABLE(sc))
2775 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8);
2776
2777 /* 5718 step 18 */
2778 if (BGE_IS_5717_PLUS(sc)) {
2779 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4);
2780 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4);
2781 }
2782
2783 /* 57XX step 45 */
2784 /*
2785 * Disable all send rings by setting the 'ring disabled' bit
2786 * in the flags field of all the TX send ring control blocks,
2787 * located in NIC memory.
2788 */
2789 if (BGE_IS_5700_FAMILY(sc)) {
2790 /* 5700 to 5704 had 16 send rings. */
2791 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2792 } else if (BGE_IS_5717_PLUS(sc)) {
2793 limit = BGE_TX_RINGS_5717_MAX;
2794 } else if (BGE_IS_57765_FAMILY(sc)) {
2795 limit = BGE_TX_RINGS_57765_MAX;
2796 } else
2797 limit = 1;
2798 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2799 for (i = 0; i < limit; i++) {
2800 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2801 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2802 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
2803 rcb_addr += sizeof(struct bge_rcb);
2804 }
2805
2806 /* 57XX step 46 and 47 */
2807 /* Configure send ring RCB 0 (we use only the first ring) */
2808 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2809 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
2810 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2811 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2812 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
2813 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
2814 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
2815 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717);
2816 else
2817 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
2818 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2819 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2820 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2821
2822 /* 57XX step 48 */
2823 /*
2824 * Disable all receive return rings by setting the
2825 * 'ring diabled' bit in the flags field of all the receive
2826 * return ring control blocks, located in NIC memory.
2827 */
2828 if (BGE_IS_5717_PLUS(sc)) {
2829 /* Should be 17, use 16 until we get an SRAM map. */
2830 limit = 16;
2831 } else if (BGE_IS_5700_FAMILY(sc))
2832 limit = BGE_RX_RINGS_MAX;
2833 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
2834 BGE_IS_57765_FAMILY(sc))
2835 limit = 4;
2836 else
2837 limit = 1;
2838 /* Disable all receive return rings */
2839 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2840 for (i = 0; i < limit; i++) {
2841 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
2842 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
2843 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2844 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
2845 BGE_RCB_FLAG_RING_DISABLED));
2846 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
2847 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2848 (i * (sizeof(uint64_t))), 0);
2849 rcb_addr += sizeof(struct bge_rcb);
2850 }
2851
2852 /* 57XX step 49 */
2853 /*
2854 * Set up receive return ring 0. Note that the NIC address
2855 * for RX return rings is 0x0. The return rings live entirely
2856 * within the host, so the nicaddr field in the RCB isn't used.
2857 */
2858 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2859 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
2860 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2861 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2862 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
2863 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
2864 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2865
2866 /* 5718 step 24, 57XX step 53 */
2867 /* Set random backoff seed for TX */
2868 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2869 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] +
2870 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] +
2871 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) &
2872 BGE_TX_BACKOFF_SEED_MASK);
2873
2874 /* 5718 step 26, 57XX step 55 */
2875 /* Set inter-packet gap */
2876 val = 0x2620;
2877 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
2878 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2879 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2880 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2881
2882 /* 5718 step 27, 57XX step 56 */
2883 /*
2884 * Specify which ring to use for packets that don't match
2885 * any RX rules.
2886 */
2887 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2888
2889 /* 5718 step 28, 57XX step 57 */
2890 /*
2891 * Configure number of RX lists. One interrupt distribution
2892 * list, sixteen active lists, one bad frames class.
2893 */
2894 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2895
2896 /* 5718 step 29, 57XX step 58 */
2897 /* Inialize RX list placement stats mask. */
2898 if (BGE_IS_575X_PLUS(sc)) {
2899 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK);
2900 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX;
2901 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val);
2902 } else
2903 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2904
2905 /* 5718 step 30, 57XX step 59 */
2906 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2907
2908 /* 5718 step 33, 57XX step 62 */
2909 /* Disable host coalescing until we get it set up */
2910 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2911
2912 /* 5718 step 34, 57XX step 63 */
2913 /* Poll to make sure it's shut down. */
2914 for (i = 0; i < BGE_TIMEOUT * 2; i++) {
2915 DELAY(10);
2916 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2917 break;
2918 }
2919
2920 if (i == BGE_TIMEOUT * 2) {
2921 aprint_error_dev(sc->bge_dev,
2922 "host coalescing engine failed to idle\n");
2923 return ENXIO;
2924 }
2925
2926 /* 5718 step 35, 36, 37 */
2927 /* Set up host coalescing defaults */
2928 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2929 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2930 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2931 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2932 if (!(BGE_IS_5705_PLUS(sc))) {
2933 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2934 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2935 }
2936 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
2937 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
2938
2939 /* Set up address of statistics block */
2940 if (BGE_IS_5700_FAMILY(sc)) {
2941 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
2942 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2943 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2944 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
2945 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
2946 }
2947
2948 /* 5718 step 38 */
2949 /* Set up address of status block */
2950 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
2951 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2952 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
2953 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
2954 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
2955 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
2956
2957 /* Set up status block size. */
2958 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 &&
2959 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2960 val = BGE_STATBLKSZ_FULL;
2961 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ);
2962 } else {
2963 val = BGE_STATBLKSZ_32BYTE;
2964 bzero(&sc->bge_rdata->bge_status_block, 32);
2965 }
2966
2967 /* 5718 step 39, 57XX step 73 */
2968 /* Turn on host coalescing state machine */
2969 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2970
2971 /* 5718 step 40, 57XX step 74 */
2972 /* Turn on RX BD completion state machine and enable attentions */
2973 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2974 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2975
2976 /* 5718 step 41, 57XX step 75 */
2977 /* Turn on RX list placement state machine */
2978 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2979
2980 /* 57XX step 76 */
2981 /* Turn on RX list selector state machine. */
2982 if (!(BGE_IS_5705_PLUS(sc)))
2983 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2984
2985 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2986 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2987 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2988 BGE_MACMODE_FRMHDR_DMA_ENB;
2989
2990 if (sc->bge_flags & BGEF_FIBER_TBI)
2991 val |= BGE_PORTMODE_TBI;
2992 else if (sc->bge_flags & BGEF_FIBER_MII)
2993 val |= BGE_PORTMODE_GMII;
2994 else
2995 val |= BGE_PORTMODE_MII;
2996
2997 /* 5718 step 42 and 43, 57XX step 77 and 78 */
2998 /* Allow APE to send/receive frames. */
2999 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
3000 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
3001
3002 /* Turn on DMA, clear stats */
3003 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val);
3004 /* 5718 step 44 */
3005 DELAY(40);
3006
3007 /* 5718 step 45, 57XX step 79 */
3008 /* Set misc. local control, enable interrupts on attentions */
3009 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
3010 if (BGE_IS_5717_PLUS(sc)) {
3011 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */
3012 /* 5718 step 46 */
3013 DELAY(100);
3014 }
3015
3016 /* 57XX step 81 */
3017 /* Turn on DMA completion state machine */
3018 if (!(BGE_IS_5705_PLUS(sc)))
3019 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3020
3021 /* 5718 step 47, 57XX step 82 */
3022 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
3023
3024 /* 5718 step 48 */
3025 /* Enable host coalescing bug fix. */
3026 if (BGE_IS_5755_PLUS(sc))
3027 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
3028
3029 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)
3030 val |= BGE_WDMAMODE_BURST_ALL_DATA;
3031
3032 /* Turn on write DMA state machine */
3033 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val);
3034 /* 5718 step 49 */
3035 DELAY(40);
3036
3037 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
3038
3039 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717)
3040 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
3041
3042 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
3043 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
3044 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
3045 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
3046 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
3047 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
3048
3049 if (sc->bge_flags & BGEF_PCIE)
3050 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
3051 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) {
3052 if (ifp->if_mtu <= ETHERMTU)
3053 val |= BGE_RDMAMODE_JMB_2K_MMRR;
3054 }
3055 if (sc->bge_flags & BGEF_TSO)
3056 val |= BGE_RDMAMODE_TSO4_ENABLE;
3057
3058 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
3059 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
3060 BGE_RDMAMODE_H2BNC_VLAN_DET;
3061 /*
3062 * Allow multiple outstanding read requests from
3063 * non-LSO read DMA engine.
3064 */
3065 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
3066 }
3067
3068 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
3069 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
3070 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
3071 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 ||
3072 BGE_IS_57765_PLUS(sc)) {
3073 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
3074 /*
3075 * Adjust tx margin to prevent TX data corruption and
3076 * fix internal FIFO overflow.
3077 */
3078 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3079 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
3080 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
3081 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
3082 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
3083 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
3084 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
3085 }
3086 /*
3087 * Enable fix for read DMA FIFO overruns.
3088 * The fix is to limit the number of RX BDs
3089 * the hardware would fetch at a fime.
3090 */
3091 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
3092 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
3093 }
3094
3095 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) {
3096 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
3097 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
3098 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
3099 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
3100 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
3101 /*
3102 * Allow 4KB burst length reads for non-LSO frames.
3103 * Enable 512B burst length reads for buffer descriptors.
3104 */
3105 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
3106 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
3107 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
3108 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
3109 }
3110
3111 /* Turn on read DMA state machine */
3112 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val);
3113 /* 5718 step 52 */
3114 delay(40);
3115
3116 /* 5718 step 56, 57XX step 84 */
3117 /* Turn on RX data completion state machine */
3118 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3119
3120 /* Turn on RX data and RX BD initiator state machine */
3121 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
3122
3123 /* 57XX step 85 */
3124 /* Turn on Mbuf cluster free state machine */
3125 if (!BGE_IS_5705_PLUS(sc))
3126 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3127
3128 /* 5718 step 57, 57XX step 86 */
3129 /* Turn on send data completion state machine */
3130 val = BGE_SDCMODE_ENABLE;
3131 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761)
3132 val |= BGE_SDCMODE_CDELAY;
3133 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
3134
3135 /* 5718 step 58 */
3136 /* Turn on send BD completion state machine */
3137 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3138
3139 /* 57XX step 88 */
3140 /* Turn on RX BD initiator state machine */
3141 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3142
3143 /* 5718 step 60, 57XX step 90 */
3144 /* Turn on send data initiator state machine */
3145 if (sc->bge_flags & BGEF_TSO) {
3146 /* XXX: magic value from Linux driver */
3147 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
3148 BGE_SDIMODE_HW_LSO_PRE_DMA);
3149 } else
3150 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3151
3152 /* 5718 step 61, 57XX step 91 */
3153 /* Turn on send BD initiator state machine */
3154 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3155
3156 /* 5718 step 62, 57XX step 92 */
3157 /* Turn on send BD selector state machine */
3158 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3159
3160 /* 5718 step 31, 57XX step 60 */
3161 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
3162 /* 5718 step 32, 57XX step 61 */
3163 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
3164 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
3165
3166 /* ack/clear link change events */
3167 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3168 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3169 BGE_MACSTAT_LINK_CHANGED);
3170 CSR_WRITE_4(sc, BGE_MI_STS, 0);
3171
3172 /*
3173 * Enable attention when the link has changed state for
3174 * devices that use auto polling.
3175 */
3176 if (sc->bge_flags & BGEF_FIBER_TBI) {
3177 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
3178 } else {
3179 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0)
3180 mimode = BGE_MIMODE_500KHZ_CONST;
3181 else
3182 mimode = BGE_MIMODE_BASE;
3183 /* 5718 step 68. 5718 step 69 (optionally). */
3184 if (BGE_IS_5700_FAMILY(sc) ||
3185 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) {
3186 mimode |= BGE_MIMODE_AUTOPOLL;
3187 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL);
3188 }
3189 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr);
3190 CSR_WRITE_4(sc, BGE_MI_MODE, mimode);
3191 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700)
3192 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
3193 BGE_EVTENB_MI_INTERRUPT);
3194 }
3195
3196 /*
3197 * Clear any pending link state attention.
3198 * Otherwise some link state change events may be lost until attention
3199 * is cleared by bge_intr() -> bge_link_upd() sequence.
3200 * It's not necessary on newer BCM chips - perhaps enabling link
3201 * state change attentions implies clearing pending attention.
3202 */
3203 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3204 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3205 BGE_MACSTAT_LINK_CHANGED);
3206
3207 /* Enable link state change attentions. */
3208 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
3209
3210 return 0;
3211 }
3212
3213 static const struct bge_revision *
3214 bge_lookup_rev(uint32_t chipid)
3215 {
3216 const struct bge_revision *br;
3217
3218 for (br = bge_revisions; br->br_name != NULL; br++) {
3219 if (br->br_chipid == chipid)
3220 return br;
3221 }
3222
3223 for (br = bge_majorrevs; br->br_name != NULL; br++) {
3224 if (br->br_chipid == BGE_ASICREV(chipid))
3225 return br;
3226 }
3227
3228 return NULL;
3229 }
3230
3231 static const struct bge_product *
3232 bge_lookup(const struct pci_attach_args *pa)
3233 {
3234 const struct bge_product *bp;
3235
3236 for (bp = bge_products; bp->bp_name != NULL; bp++) {
3237 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor &&
3238 PCI_PRODUCT(pa->pa_id) == bp->bp_product)
3239 return bp;
3240 }
3241
3242 return NULL;
3243 }
3244
3245 static uint32_t
3246 bge_chipid(const struct pci_attach_args *pa)
3247 {
3248 uint32_t id;
3249
3250 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL)
3251 >> BGE_PCIMISCCTL_ASICREV_SHIFT;
3252
3253 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
3254 switch (PCI_PRODUCT(pa->pa_id)) {
3255 case PCI_PRODUCT_BROADCOM_BCM5717:
3256 case PCI_PRODUCT_BROADCOM_BCM5718:
3257 case PCI_PRODUCT_BROADCOM_BCM5719:
3258 case PCI_PRODUCT_BROADCOM_BCM5720:
3259 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */
3260 id = pci_conf_read(pa->pa_pc, pa->pa_tag,
3261 BGE_PCI_GEN2_PRODID_ASICREV);
3262 break;
3263 case PCI_PRODUCT_BROADCOM_BCM57761:
3264 case PCI_PRODUCT_BROADCOM_BCM57762:
3265 case PCI_PRODUCT_BROADCOM_BCM57765:
3266 case PCI_PRODUCT_BROADCOM_BCM57766:
3267 case PCI_PRODUCT_BROADCOM_BCM57781:
3268 case PCI_PRODUCT_BROADCOM_BCM57785:
3269 case PCI_PRODUCT_BROADCOM_BCM57791:
3270 case PCI_PRODUCT_BROADCOM_BCM57795:
3271 id = pci_conf_read(pa->pa_pc, pa->pa_tag,
3272 BGE_PCI_GEN15_PRODID_ASICREV);
3273 break;
3274 default:
3275 id = pci_conf_read(pa->pa_pc, pa->pa_tag,
3276 BGE_PCI_PRODID_ASICREV);
3277 break;
3278 }
3279 }
3280
3281 return id;
3282 }
3283
3284 /*
3285 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
3286 * against our list and return its name if we find a match. Note
3287 * that since the Broadcom controller contains VPD support, we
3288 * can get the device name string from the controller itself instead
3289 * of the compiled-in string. This is a little slow, but it guarantees
3290 * we'll always announce the right product name.
3291 */
3292 static int
3293 bge_probe(device_t parent, cfdata_t match, void *aux)
3294 {
3295 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
3296
3297 if (bge_lookup(pa) != NULL)
3298 return 1;
3299
3300 return 0;
3301 }
3302
3303 static void
3304 bge_attach(device_t parent, device_t self, void *aux)
3305 {
3306 struct bge_softc *sc = device_private(self);
3307 struct pci_attach_args *pa = aux;
3308 prop_dictionary_t dict;
3309 const struct bge_product *bp;
3310 const struct bge_revision *br;
3311 pci_chipset_tag_t pc;
3312 pci_intr_handle_t ih;
3313 const char *intrstr = NULL;
3314 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5;
3315 uint32_t command;
3316 struct ifnet *ifp;
3317 uint32_t misccfg, mimode;
3318 void * kva;
3319 u_char eaddr[ETHER_ADDR_LEN];
3320 pcireg_t memtype, subid, reg;
3321 bus_addr_t memaddr;
3322 uint32_t pm_ctl;
3323 bool no_seeprom;
3324 int capmask;
3325 int mii_flags;
3326 int map_flags;
3327 char intrbuf[PCI_INTRSTR_LEN];
3328
3329 bp = bge_lookup(pa);
3330 KASSERT(bp != NULL);
3331
3332 sc->sc_pc = pa->pa_pc;
3333 sc->sc_pcitag = pa->pa_tag;
3334 sc->bge_dev = self;
3335
3336 sc->bge_pa = *pa;
3337 pc = sc->sc_pc;
3338 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG);
3339
3340 aprint_naive(": Ethernet controller\n");
3341 aprint_normal(": %s\n", bp->bp_name);
3342
3343 /*
3344 * Map control/status registers.
3345 */
3346 DPRINTFN(5, ("Map control/status regs\n"));
3347 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
3348 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
3349 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command);
3350 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
3351
3352 if (!(command & PCI_COMMAND_MEM_ENABLE)) {
3353 aprint_error_dev(sc->bge_dev,
3354 "failed to enable memory mapping!\n");
3355 return;
3356 }
3357
3358 DPRINTFN(5, ("pci_mem_find\n"));
3359 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0);
3360 switch (memtype) {
3361 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
3362 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
3363 #if 0
3364 if (pci_mapreg_map(pa, BGE_PCI_BAR0,
3365 memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
3366 &memaddr, &sc->bge_bsize) == 0)
3367 break;
3368 #else
3369 /*
3370 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based
3371 * system get NMI on boot (PR#48451). This problem might not be
3372 * the driver's bug but our PCI common part's bug. Until we
3373 * find a real reason, we ignore the prefetchable bit.
3374 */
3375 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0,
3376 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) {
3377 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
3378 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize,
3379 map_flags, &sc->bge_bhandle) == 0) {
3380 sc->bge_btag = pa->pa_memt;
3381 break;
3382 }
3383 }
3384 #endif
3385 default:
3386 aprint_error_dev(sc->bge_dev, "can't find mem space\n");
3387 return;
3388 }
3389
3390 DPRINTFN(5, ("pci_intr_map\n"));
3391 if (pci_intr_map(pa, &ih)) {
3392 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n");
3393 return;
3394 }
3395
3396 DPRINTFN(5, ("pci_intr_string\n"));
3397 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
3398
3399 DPRINTFN(5, ("pci_intr_establish\n"));
3400 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc);
3401
3402 if (sc->bge_intrhand == NULL) {
3403 aprint_error_dev(sc->bge_dev,
3404 "couldn't establish interrupt%s%s\n",
3405 intrstr ? " at " : "", intrstr ? intrstr : "");
3406 return;
3407 }
3408 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr);
3409
3410 /* Save various chip information. */
3411 sc->bge_chipid = bge_chipid(pa);
3412 sc->bge_phy_addr = bge_phy_addr(sc);
3413
3414 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS,
3415 &sc->bge_pciecap, NULL) != 0)
3416 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) {
3417 /* PCIe */
3418 sc->bge_flags |= BGEF_PCIE;
3419 /* Extract supported maximum payload size. */
3420 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
3421 sc->bge_pciecap + PCIE_DCAP);
3422 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD);
3423 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
3424 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
3425 sc->bge_expmrq = 2048;
3426 else
3427 sc->bge_expmrq = 4096;
3428 bge_set_max_readrq(sc);
3429 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) &
3430 BGE_PCISTATE_PCI_BUSMODE) == 0) {
3431 /* PCI-X */
3432 sc->bge_flags |= BGEF_PCIX;
3433 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX,
3434 &sc->bge_pcixcap, NULL) == 0)
3435 aprint_error_dev(sc->bge_dev,
3436 "unable to find PCIX capability\n");
3437 }
3438
3439 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) {
3440 /*
3441 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
3442 * can clobber the chip's PCI config-space power control
3443 * registers, leaving the card in D3 powersave state. We do
3444 * not have memory-mapped registers in this state, so force
3445 * device into D0 state before starting initialization.
3446 */
3447 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD);
3448 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3);
3449 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
3450 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
3451 DELAY(1000); /* 27 usec is allegedly sufficent */
3452 }
3453
3454 /* Save chipset family. */
3455 switch (BGE_ASICREV(sc->bge_chipid)) {
3456 case BGE_ASICREV_BCM5717:
3457 case BGE_ASICREV_BCM5719:
3458 case BGE_ASICREV_BCM5720:
3459 sc->bge_flags |= BGEF_5717_PLUS;
3460 /* FALLTHROUGH */
3461 case BGE_ASICREV_BCM57765:
3462 case BGE_ASICREV_BCM57766:
3463 if (!BGE_IS_5717_PLUS(sc))
3464 sc->bge_flags |= BGEF_57765_FAMILY;
3465 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS |
3466 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE;
3467 /* Jumbo frame on BCM5719 A0 does not work. */
3468 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) &&
3469 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0))
3470 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE;
3471 break;
3472 case BGE_ASICREV_BCM5755:
3473 case BGE_ASICREV_BCM5761:
3474 case BGE_ASICREV_BCM5784:
3475 case BGE_ASICREV_BCM5785:
3476 case BGE_ASICREV_BCM5787:
3477 case BGE_ASICREV_BCM57780:
3478 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS;
3479 break;
3480 case BGE_ASICREV_BCM5700:
3481 case BGE_ASICREV_BCM5701:
3482 case BGE_ASICREV_BCM5703:
3483 case BGE_ASICREV_BCM5704:
3484 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE;
3485 break;
3486 case BGE_ASICREV_BCM5714_A0:
3487 case BGE_ASICREV_BCM5780:
3488 case BGE_ASICREV_BCM5714:
3489 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE;
3490 /* FALLTHROUGH */
3491 case BGE_ASICREV_BCM5750:
3492 case BGE_ASICREV_BCM5752:
3493 case BGE_ASICREV_BCM5906:
3494 sc->bge_flags |= BGEF_575X_PLUS;
3495 /* FALLTHROUGH */
3496 case BGE_ASICREV_BCM5705:
3497 sc->bge_flags |= BGEF_5705_PLUS;
3498 break;
3499 }
3500
3501 /* Identify chips with APE processor. */
3502 switch (BGE_ASICREV(sc->bge_chipid)) {
3503 case BGE_ASICREV_BCM5717:
3504 case BGE_ASICREV_BCM5719:
3505 case BGE_ASICREV_BCM5720:
3506 case BGE_ASICREV_BCM5761:
3507 sc->bge_flags |= BGEF_APE;
3508 break;
3509 }
3510
3511 /*
3512 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3513 * not actually a MAC controller bug but an issue with the embedded
3514 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3515 */
3516 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0))
3517 sc->bge_flags |= BGEF_40BIT_BUG;
3518
3519 /* Chips with APE need BAR2 access for APE registers/memory. */
3520 if ((sc->bge_flags & BGEF_APE) != 0) {
3521 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2);
3522 #if 0
3523 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0,
3524 &sc->bge_apetag, &sc->bge_apehandle, NULL,
3525 &sc->bge_apesize)) {
3526 aprint_error_dev(sc->bge_dev,
3527 "couldn't map BAR2 memory\n");
3528 return;
3529 }
3530 #else
3531 /*
3532 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based
3533 * system get NMI on boot (PR#48451). This problem might not be
3534 * the driver's bug but our PCI common part's bug. Until we
3535 * find a real reason, we ignore the prefetchable bit.
3536 */
3537 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2,
3538 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) {
3539 aprint_error_dev(sc->bge_dev,
3540 "couldn't map BAR2 memory\n");
3541 return;
3542 }
3543
3544 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
3545 if (bus_space_map(pa->pa_memt, memaddr,
3546 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) {
3547 aprint_error_dev(sc->bge_dev,
3548 "couldn't map BAR2 memory\n");
3549 return;
3550 }
3551 sc->bge_apetag = pa->pa_memt;
3552 #endif
3553
3554 /* Enable APE register/memory access by host driver. */
3555 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
3556 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3557 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3558 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3559 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg);
3560
3561 bge_ape_lock_init(sc);
3562 bge_ape_read_fw_ver(sc);
3563 }
3564
3565 /* Identify the chips that use an CPMU. */
3566 if (BGE_IS_5717_PLUS(sc) ||
3567 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
3568 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
3569 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
3570 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
3571 sc->bge_flags |= BGEF_CPMU_PRESENT;
3572
3573 /* Set MI_MODE */
3574 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr);
3575 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0)
3576 mimode |= BGE_MIMODE_500KHZ_CONST;
3577 else
3578 mimode |= BGE_MIMODE_BASE;
3579 CSR_WRITE_4(sc, BGE_MI_MODE, mimode);
3580
3581 /*
3582 * When using the BCM5701 in PCI-X mode, data corruption has
3583 * been observed in the first few bytes of some received packets.
3584 * Aligning the packet buffer in memory eliminates the corruption.
3585 * Unfortunately, this misaligns the packet payloads. On platforms
3586 * which do not support unaligned accesses, we will realign the
3587 * payloads by copying the received packets.
3588 */
3589 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
3590 sc->bge_flags & BGEF_PCIX)
3591 sc->bge_flags |= BGEF_RX_ALIGNBUG;
3592
3593 if (BGE_IS_5700_FAMILY(sc))
3594 sc->bge_flags |= BGEF_JUMBO_CAPABLE;
3595
3596 misccfg = CSR_READ_4(sc, BGE_MISC_CFG);
3597 misccfg &= BGE_MISCCFG_BOARD_ID_MASK;
3598
3599 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
3600 (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3601 misccfg == BGE_MISCCFG_BOARD_ID_5788M))
3602 sc->bge_flags |= BGEF_IS_5788;
3603
3604 /*
3605 * Some controllers seem to require a special firmware to use
3606 * TSO. But the firmware is not available to FreeBSD and Linux
3607 * claims that the TSO performed by the firmware is slower than
3608 * hardware based TSO. Moreover the firmware based TSO has one
3609 * known bug which can't handle TSO if ethernet header + IP/TCP
3610 * header is greater than 80 bytes. The workaround for the TSO
3611 * bug exist but it seems it's too expensive than not using
3612 * TSO at all. Some hardwares also have the TSO bug so limit
3613 * the TSO to the controllers that are not affected TSO issues
3614 * (e.g. 5755 or higher).
3615 */
3616 if (BGE_IS_5755_PLUS(sc)) {
3617 /*
3618 * BCM5754 and BCM5787 shares the same ASIC id so
3619 * explicit device id check is required.
3620 */
3621 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) &&
3622 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M))
3623 sc->bge_flags |= BGEF_TSO;
3624 }
3625
3626 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */
3627 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 &&
3628 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3629 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
3630 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
3631 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 ||
3632 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
3633 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
3634 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
3635 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F ||
3636 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F ||
3637 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
3638 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 ||
3639 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 ||
3640 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 ||
3641 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
3642 /* These chips are 10/100 only. */
3643 capmask &= ~BMSR_EXTSTAT;
3644 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
3645 }
3646
3647 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
3648 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
3649 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3650 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3651 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
3652
3653 /* Set various PHY bug flags. */
3654 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3655 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3656 sc->bge_phy_flags |= BGEPHYF_CRC_BUG;
3657 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX ||
3658 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX)
3659 sc->bge_phy_flags |= BGEPHYF_ADC_BUG;
3660 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3661 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG;
3662 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
3663 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) &&
3664 PCI_VENDOR(subid) == PCI_VENDOR_DELL)
3665 sc->bge_phy_flags |= BGEPHYF_NO_3LED;
3666 if (BGE_IS_5705_PLUS(sc) &&
3667 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 &&
3668 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 &&
3669 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 &&
3670 !BGE_IS_57765_PLUS(sc)) {
3671 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
3672 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 ||
3673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
3674 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) {
3675 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 &&
3676 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756)
3677 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG;
3678 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M)
3679 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM;
3680 } else
3681 sc->bge_phy_flags |= BGEPHYF_BER_BUG;
3682 }
3683
3684 /*
3685 * SEEPROM check.
3686 * First check if firmware knows we do not have SEEPROM.
3687 */
3688 if (prop_dictionary_get_bool(device_properties(self),
3689 "without-seeprom", &no_seeprom) && no_seeprom)
3690 sc->bge_flags |= BGEF_NO_EEPROM;
3691
3692 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
3693 sc->bge_flags |= BGEF_NO_EEPROM;
3694
3695 /* Now check the 'ROM failed' bit on the RX CPU */
3696 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL)
3697 sc->bge_flags |= BGEF_NO_EEPROM;
3698
3699 sc->bge_asf_mode = 0;
3700 /* No ASF if APE present. */
3701 if ((sc->bge_flags & BGEF_APE) == 0) {
3702 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3703 BGE_SRAM_DATA_SIG_MAGIC)) {
3704 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3705 BGE_HWCFG_ASF) {
3706 sc->bge_asf_mode |= ASF_ENABLE;
3707 sc->bge_asf_mode |= ASF_STACKUP;
3708 if (BGE_IS_575X_PLUS(sc))
3709 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3710 }
3711 }
3712 }
3713
3714 /*
3715 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM
3716 * lock in bge_reset().
3717 */
3718 CSR_WRITE_4(sc, BGE_EE_ADDR,
3719 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
3720 delay(1000);
3721 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
3722
3723 bge_stop_fw(sc);
3724 bge_sig_pre_reset(sc, BGE_RESET_START);
3725 if (bge_reset(sc))
3726 aprint_error_dev(sc->bge_dev, "chip reset failed\n");
3727
3728 /*
3729 * Read the hardware config word in the first 32k of NIC internal
3730 * memory, or fall back to the config word in the EEPROM.
3731 * Note: on some BCM5700 cards, this value appears to be unset.
3732 */
3733 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0;
3734 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3735 BGE_SRAM_DATA_SIG_MAGIC) {
3736 uint32_t tmp;
3737
3738 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3739 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >>
3740 BGE_SRAM_DATA_VER_SHIFT;
3741 if ((0 < tmp) && (tmp < 0x100))
3742 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2);
3743 if (sc->bge_flags & BGEF_PCIE)
3744 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3);
3745 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)
3746 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4);
3747 if (BGE_IS_5717_PLUS(sc))
3748 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5);
3749 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) {
3750 bge_read_eeprom(sc, (void *)&hwcfg,
3751 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
3752 hwcfg = be32toh(hwcfg);
3753 }
3754 aprint_normal_dev(sc->bge_dev,
3755 "HW config %08x, %08x, %08x, %08x %08x\n",
3756 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5);
3757
3758 bge_sig_legacy(sc, BGE_RESET_START);
3759 bge_sig_post_reset(sc, BGE_RESET_START);
3760
3761 if (bge_chipinit(sc)) {
3762 aprint_error_dev(sc->bge_dev, "chip initialization failed\n");
3763 bge_release_resources(sc);
3764 return;
3765 }
3766
3767 /*
3768 * Get station address from the EEPROM.
3769 */
3770 if (bge_get_eaddr(sc, eaddr)) {
3771 aprint_error_dev(sc->bge_dev,
3772 "failed to read station address\n");
3773 bge_release_resources(sc);
3774 return;
3775 }
3776
3777 br = bge_lookup_rev(sc->bge_chipid);
3778
3779 if (br == NULL) {
3780 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)",
3781 sc->bge_chipid);
3782 } else {
3783 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)",
3784 br->br_name, sc->bge_chipid);
3785 }
3786 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr));
3787
3788 /* Allocate the general information block and ring buffers. */
3789 if (pci_dma64_available(pa))
3790 sc->bge_dmatag = pa->pa_dmat64;
3791 else
3792 sc->bge_dmatag = pa->pa_dmat;
3793
3794 /* 40bit DMA workaround */
3795 if (sizeof(bus_addr_t) > 4) {
3796 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) {
3797 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */
3798
3799 if (bus_dmatag_subregion(olddmatag, 0,
3800 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag),
3801 BUS_DMA_NOWAIT) != 0) {
3802 aprint_error_dev(self,
3803 "WARNING: failed to restrict dma range,"
3804 " falling back to parent bus dma range\n");
3805 sc->bge_dmatag = olddmatag;
3806 }
3807 }
3808 }
3809 DPRINTFN(5, ("bus_dmamem_alloc\n"));
3810 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
3811 PAGE_SIZE, 0, &sc->bge_ring_seg, 1,
3812 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) {
3813 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n");
3814 return;
3815 }
3816 DPRINTFN(5, ("bus_dmamem_map\n"));
3817 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg,
3818 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva,
3819 BUS_DMA_NOWAIT)) {
3820 aprint_error_dev(sc->bge_dev,
3821 "can't map DMA buffers (%zu bytes)\n",
3822 sizeof(struct bge_ring_data));
3823 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
3824 sc->bge_ring_rseg);
3825 return;
3826 }
3827 DPRINTFN(5, ("bus_dmamem_create\n"));
3828 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
3829 sizeof(struct bge_ring_data), 0,
3830 BUS_DMA_NOWAIT, &sc->bge_ring_map)) {
3831 aprint_error_dev(sc->bge_dev, "can't create DMA map\n");
3832 bus_dmamem_unmap(sc->bge_dmatag, kva,
3833 sizeof(struct bge_ring_data));
3834 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
3835 sc->bge_ring_rseg);
3836 return;
3837 }
3838 DPRINTFN(5, ("bus_dmamem_load\n"));
3839 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
3840 sizeof(struct bge_ring_data), NULL,
3841 BUS_DMA_NOWAIT)) {
3842 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
3843 bus_dmamem_unmap(sc->bge_dmatag, kva,
3844 sizeof(struct bge_ring_data));
3845 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg,
3846 sc->bge_ring_rseg);
3847 return;
3848 }
3849
3850 DPRINTFN(5, ("bzero\n"));
3851 sc->bge_rdata = (struct bge_ring_data *)kva;
3852
3853 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data));
3854
3855 /* Try to allocate memory for jumbo buffers. */
3856 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3857 if (bge_alloc_jumbo_mem(sc)) {
3858 aprint_error_dev(sc->bge_dev,
3859 "jumbo buffer allocation failed\n");
3860 } else
3861 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
3862 }
3863
3864 /* Set default tuneable values. */
3865 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3866 sc->bge_rx_coal_ticks = 150;
3867 sc->bge_rx_max_coal_bds = 64;
3868 sc->bge_tx_coal_ticks = 300;
3869 sc->bge_tx_max_coal_bds = 400;
3870 if (BGE_IS_5705_PLUS(sc)) {
3871 sc->bge_tx_coal_ticks = (12 * 5);
3872 sc->bge_tx_max_coal_bds = (12 * 5);
3873 aprint_verbose_dev(sc->bge_dev,
3874 "setting short Tx thresholds\n");
3875 }
3876
3877 if (BGE_IS_5717_PLUS(sc))
3878 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3879 else if (BGE_IS_5705_PLUS(sc))
3880 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3881 else
3882 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3883
3884 /* Set up ifnet structure */
3885 ifp = &sc->ethercom.ec_if;
3886 ifp->if_softc = sc;
3887 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3888 ifp->if_ioctl = bge_ioctl;
3889 ifp->if_stop = bge_stop;
3890 ifp->if_start = bge_start;
3891 ifp->if_init = bge_init;
3892 ifp->if_watchdog = bge_watchdog;
3893 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN));
3894 IFQ_SET_READY(&ifp->if_snd);
3895 DPRINTFN(5, ("strcpy if_xname\n"));
3896 strcpy(ifp->if_xname, device_xname(sc->bge_dev));
3897
3898 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0)
3899 sc->ethercom.ec_if.if_capabilities |=
3900 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx;
3901 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */
3902 sc->ethercom.ec_if.if_capabilities |=
3903 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
3904 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
3905 #endif
3906 sc->ethercom.ec_capabilities |=
3907 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU;
3908
3909 if (sc->bge_flags & BGEF_TSO)
3910 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4;
3911
3912 /*
3913 * Do MII setup.
3914 */
3915 DPRINTFN(5, ("mii setup\n"));
3916 sc->bge_mii.mii_ifp = ifp;
3917 sc->bge_mii.mii_readreg = bge_miibus_readreg;
3918 sc->bge_mii.mii_writereg = bge_miibus_writereg;
3919 sc->bge_mii.mii_statchg = bge_miibus_statchg;
3920
3921 /*
3922 * Figure out what sort of media we have by checking the hardware
3923 * config word. Note: on some BCM5700 cards, this value appears to be
3924 * unset. If that's the case, we have to rely on identifying the NIC
3925 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41.
3926 * The SysKonnect SK-9D41 is a 1000baseSX card.
3927 */
3928 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 ||
3929 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3930 if (BGE_IS_5705_PLUS(sc)) {
3931 sc->bge_flags |= BGEF_FIBER_MII;
3932 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED;
3933 } else
3934 sc->bge_flags |= BGEF_FIBER_TBI;
3935 }
3936
3937 /* Set bge_phy_flags before prop_dictionary_set_uint32() */
3938 if (BGE_IS_JUMBO_CAPABLE(sc))
3939 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE;
3940
3941 /* set phyflags and chipid before mii_attach() */
3942 dict = device_properties(self);
3943 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags);
3944 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid);
3945
3946 if (sc->bge_flags & BGEF_FIBER_TBI) {
3947 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3948 bge_ifmedia_sts);
3949 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL);
3950 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX,
3951 0, NULL);
3952 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3953 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3954 /* Pretend the user requested this setting */
3955 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3956 } else {
3957 /*
3958 * Do transceiver setup and tell the firmware the
3959 * driver is down so we can try to get access the
3960 * probe if ASF is running. Retry a couple of times
3961 * if we get a conflict with the ASF firmware accessing
3962 * the PHY.
3963 */
3964 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3965 bge_asf_driver_up(sc);
3966
3967 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
3968 bge_ifmedia_sts);
3969 mii_flags = MIIF_DOPAUSE;
3970 if (sc->bge_flags & BGEF_FIBER_MII)
3971 mii_flags |= MIIF_HAVEFIBER;
3972 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr,
3973 MII_OFFSET_ANY, mii_flags);
3974
3975 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) {
3976 aprint_error_dev(sc->bge_dev, "no PHY found!\n");
3977 ifmedia_add(&sc->bge_mii.mii_media,
3978 IFM_ETHER|IFM_MANUAL, 0, NULL);
3979 ifmedia_set(&sc->bge_mii.mii_media,
3980 IFM_ETHER|IFM_MANUAL);
3981 } else
3982 ifmedia_set(&sc->bge_mii.mii_media,
3983 IFM_ETHER|IFM_AUTO);
3984
3985 /*
3986 * Now tell the firmware we are going up after probing the PHY
3987 */
3988 if (sc->bge_asf_mode & ASF_STACKUP)
3989 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3990 }
3991
3992 /*
3993 * Call MI attach routine.
3994 */
3995 DPRINTFN(5, ("if_attach\n"));
3996 if_attach(ifp);
3997 DPRINTFN(5, ("ether_ifattach\n"));
3998 ether_ifattach(ifp, eaddr);
3999 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb);
4000 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev),
4001 RND_TYPE_NET, RND_FLAG_DEFAULT);
4002 #ifdef BGE_EVENT_COUNTERS
4003 /*
4004 * Attach event counters.
4005 */
4006 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR,
4007 NULL, device_xname(sc->bge_dev), "intr");
4008 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC,
4009 NULL, device_xname(sc->bge_dev), "tx_xoff");
4010 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC,
4011 NULL, device_xname(sc->bge_dev), "tx_xon");
4012 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC,
4013 NULL, device_xname(sc->bge_dev), "rx_xoff");
4014 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC,
4015 NULL, device_xname(sc->bge_dev), "rx_xon");
4016 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC,
4017 NULL, device_xname(sc->bge_dev), "rx_macctl");
4018 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC,
4019 NULL, device_xname(sc->bge_dev), "xoffentered");
4020 #endif /* BGE_EVENT_COUNTERS */
4021 DPRINTFN(5, ("callout_init\n"));
4022 callout_init(&sc->bge_timeout, 0);
4023
4024 if (pmf_device_register(self, NULL, NULL))
4025 pmf_class_network_register(self, ifp);
4026 else
4027 aprint_error_dev(self, "couldn't establish power handler\n");
4028
4029 bge_sysctl_init(sc);
4030
4031 #ifdef BGE_DEBUG
4032 bge_debug_info(sc);
4033 #endif
4034 }
4035
4036 /*
4037 * Stop all chip I/O so that the kernel's probe routines don't
4038 * get confused by errant DMAs when rebooting.
4039 */
4040 static int
4041 bge_detach(device_t self, int flags __unused)
4042 {
4043 struct bge_softc *sc = device_private(self);
4044 struct ifnet *ifp = &sc->ethercom.ec_if;
4045 int s;
4046
4047 s = splnet();
4048 /* Stop the interface. Callouts are stopped in it. */
4049 bge_stop(ifp, 1);
4050 splx(s);
4051
4052 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY);
4053
4054 /* Delete all remaining media. */
4055 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY);
4056
4057 ether_ifdetach(ifp);
4058 if_detach(ifp);
4059
4060 bge_release_resources(sc);
4061
4062 return 0;
4063 }
4064
4065 static void
4066 bge_release_resources(struct bge_softc *sc)
4067 {
4068
4069 /* Disestablish the interrupt handler */
4070 if (sc->bge_intrhand != NULL) {
4071 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand);
4072 sc->bge_intrhand = NULL;
4073 }
4074
4075 if (sc->bge_dmatag != NULL) {
4076 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map);
4077 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
4078 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata,
4079 sizeof(struct bge_ring_data));
4080 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg);
4081 }
4082
4083 /* Unmap the device registers */
4084 if (sc->bge_bsize != 0) {
4085 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize);
4086 sc->bge_bsize = 0;
4087 }
4088
4089 /* Unmap the APE registers */
4090 if (sc->bge_apesize != 0) {
4091 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle,
4092 sc->bge_apesize);
4093 sc->bge_apesize = 0;
4094 }
4095 }
4096
4097 static int
4098 bge_reset(struct bge_softc *sc)
4099 {
4100 uint32_t cachesize, command;
4101 uint32_t reset, mac_mode, mac_mode_mask;
4102 pcireg_t devctl, reg;
4103 int i, val;
4104 void (*write_op)(struct bge_softc *, int, int);
4105
4106 /* Make mask for BGE_MAC_MODE register. */
4107 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4108 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4109 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4110 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */
4111 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4112
4113 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4114 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) {
4115 if (sc->bge_flags & BGEF_PCIE)
4116 write_op = bge_writemem_direct;
4117 else
4118 write_op = bge_writemem_ind;
4119 } else
4120 write_op = bge_writereg_ind;
4121
4122 /* 57XX step 4 */
4123 /* Acquire the NVM lock */
4124 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 &&
4125 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 &&
4126 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) {
4127 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4128 for (i = 0; i < 8000; i++) {
4129 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4130 BGE_NVRAMSWARB_GNT1)
4131 break;
4132 DELAY(20);
4133 }
4134 if (i == 8000) {
4135 printf("%s: NVRAM lock timedout!\n",
4136 device_xname(sc->bge_dev));
4137 }
4138 }
4139
4140 /* Take APE lock when performing reset. */
4141 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4142
4143 /* 57XX step 3 */
4144 /* Save some important PCI state. */
4145 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ);
4146 /* 5718 reset step 3 */
4147 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD);
4148
4149 /* 5718 reset step 5, 57XX step 5b-5d */
4150 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
4151 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4152 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW);
4153
4154 /* XXX ???: Disable fastboot on controllers that support it. */
4155 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
4156 BGE_IS_5755_PLUS(sc))
4157 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
4158
4159 /* 5718 reset step 2, 57XX step 6 */
4160 /*
4161 * Write the magic number to SRAM at offset 0xB50.
4162 * When firmware finishes its initialization it will
4163 * write ~BGE_MAGIC_NUMBER to the same location.
4164 */
4165 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4166
4167 /* 5718 reset step 6, 57XX step 7 */
4168 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4169 /*
4170 * XXX: from FreeBSD/Linux; no documentation
4171 */
4172 if (sc->bge_flags & BGEF_PCIE) {
4173 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) &&
4174 !BGE_IS_57765_PLUS(sc) &&
4175 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) ==
4176 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) {
4177 /* PCI Express 1.0 system */
4178 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG,
4179 BGE_PHY_PCIE_SCRAM_MODE);
4180 }
4181 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4182 /*
4183 * Prevent PCI Express link training
4184 * during global reset.
4185 */
4186 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4187 reset |= (1 << 29);
4188 }
4189 }
4190
4191 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
4192 i = CSR_READ_4(sc, BGE_VCPU_STATUS);
4193 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4194 i | BGE_VCPU_STATUS_DRV_RESET);
4195 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4196 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4197 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4198 }
4199
4200 /*
4201 * Set GPHY Power Down Override to leave GPHY
4202 * powered up in D0 uninitialized.
4203 */
4204 if (BGE_IS_5705_PLUS(sc) &&
4205 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0)
4206 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4207
4208 /* Issue global reset */
4209 write_op(sc, BGE_MISC_CFG, reset);
4210
4211 /* 5718 reset step 7, 57XX step 8 */
4212 if (sc->bge_flags & BGEF_PCIE)
4213 delay(100*1000); /* too big */
4214 else
4215 delay(1000);
4216
4217 if (sc->bge_flags & BGEF_PCIE) {
4218 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4219 DELAY(500000);
4220 /* XXX: Magic Numbers */
4221 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
4222 BGE_PCI_UNKNOWN0);
4223 pci_conf_write(sc->sc_pc, sc->sc_pcitag,
4224 BGE_PCI_UNKNOWN0,
4225 reg | (1 << 15));
4226 }
4227 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
4228 sc->bge_pciecap + PCIE_DCSR);
4229 /* Clear enable no snoop and disable relaxed ordering. */
4230 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD |
4231 PCIE_DCSR_ENA_NO_SNOOP);
4232
4233 /* Set PCIE max payload size to 128 for older PCIe devices */
4234 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0)
4235 devctl &= ~(0x00e0);
4236 /* Clear device status register. Write 1b to clear */
4237 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED
4238 | PCIE_DCSR_NFED | PCIE_DCSR_CED;
4239 pci_conf_write(sc->sc_pc, sc->sc_pcitag,
4240 sc->bge_pciecap + PCIE_DCSR, devctl);
4241 bge_set_max_readrq(sc);
4242 }
4243
4244 /* From Linux: dummy read to flush PCI posted writes */
4245 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD);
4246
4247 /*
4248 * Reset some of the PCI state that got zapped by reset
4249 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be
4250 * set, too.
4251 */
4252 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL,
4253 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4254 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW);
4255 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4256 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4257 (sc->bge_flags & BGEF_PCIX) != 0)
4258 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4259 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4260 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4261 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4262 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4263 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val);
4264 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize);
4265 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command);
4266
4267 /* 57xx step 11: disable PCI-X Relaxed Ordering. */
4268 if (sc->bge_flags & BGEF_PCIX) {
4269 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap
4270 + PCIX_CMD);
4271 /* Set max memory read byte count to 2K */
4272 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) {
4273 reg &= ~PCIX_CMD_BYTECNT_MASK;
4274 reg |= PCIX_CMD_BCNT_2048;
4275 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){
4276 /*
4277 * For 5704, set max outstanding split transaction
4278 * field to 0 (0 means it supports 1 request)
4279 */
4280 reg &= ~(PCIX_CMD_SPLTRANS_MASK
4281 | PCIX_CMD_BYTECNT_MASK);
4282 reg |= PCIX_CMD_BCNT_2048;
4283 }
4284 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap
4285 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER);
4286 }
4287
4288 /* 5718 reset step 10, 57XX step 12 */
4289 /* Enable memory arbiter. */
4290 if (BGE_IS_5714_FAMILY(sc)) {
4291 val = CSR_READ_4(sc, BGE_MARB_MODE);
4292 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4293 } else
4294 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4295
4296 /* XXX 5721, 5751 and 5752 */
4297 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) {
4298 /* Step 19: */
4299 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25);
4300 /* Step 20: */
4301 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT);
4302 }
4303
4304 /* 5718 reset step 12, 57XX step 15 and 16 */
4305 /* Fix up byte swapping */
4306 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
4307
4308 /* 5718 reset step 13, 57XX step 17 */
4309 /* Poll until the firmware initialization is complete */
4310 bge_poll_fw(sc);
4311
4312 /* 57XX step 21 */
4313 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) {
4314 pcireg_t msidata;
4315
4316 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
4317 BGE_PCI_MSI_DATA);
4318 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16);
4319 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA,
4320 msidata);
4321 }
4322
4323 /* 57XX step 18 */
4324 /* Write mac mode. */
4325 val = CSR_READ_4(sc, BGE_MAC_MODE);
4326 /* Restore mac_mode_mask's bits using mac_mode */
4327 val = (val & ~mac_mode_mask) | mac_mode;
4328 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val);
4329 DELAY(40);
4330
4331 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4332
4333 /*
4334 * The 5704 in TBI mode apparently needs some special
4335 * adjustment to insure the SERDES drive level is set
4336 * to 1.2V.
4337 */
4338 if (sc->bge_flags & BGEF_FIBER_TBI &&
4339 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
4340 uint32_t serdescfg;
4341
4342 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
4343 serdescfg = (serdescfg & ~0xFFF) | 0x880;
4344 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
4345 }
4346
4347 if (sc->bge_flags & BGEF_PCIE &&
4348 !BGE_IS_57765_PLUS(sc) &&
4349 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4350 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) {
4351 uint32_t v;
4352
4353 /* Enable PCI Express bug fix */
4354 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG);
4355 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG,
4356 v | BGE_TLP_DATA_FIFO_PROTECT);
4357 }
4358
4359 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720)
4360 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4361 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4362
4363 return 0;
4364 }
4365
4366 /*
4367 * Frame reception handling. This is called if there's a frame
4368 * on the receive return list.
4369 *
4370 * Note: we have to be able to handle two possibilities here:
4371 * 1) the frame is from the jumbo receive ring
4372 * 2) the frame is from the standard receive ring
4373 */
4374
4375 static void
4376 bge_rxeof(struct bge_softc *sc)
4377 {
4378 struct ifnet *ifp;
4379 uint16_t rx_prod, rx_cons;
4380 int stdcnt = 0, jumbocnt = 0;
4381 bus_dmamap_t dmamap;
4382 bus_addr_t offset, toff;
4383 bus_size_t tlen;
4384 int tosync;
4385
4386 rx_cons = sc->bge_rx_saved_considx;
4387 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx;
4388
4389 /* Nothing to do */
4390 if (rx_cons == rx_prod)
4391 return;
4392
4393 ifp = &sc->ethercom.ec_if;
4394
4395 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4396 offsetof(struct bge_ring_data, bge_status_block),
4397 sizeof (struct bge_status_block),
4398 BUS_DMASYNC_POSTREAD);
4399
4400 offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
4401 tosync = rx_prod - rx_cons;
4402
4403 if (tosync != 0)
4404 rnd_add_uint32(&sc->rnd_source, tosync);
4405
4406 toff = offset + (rx_cons * sizeof (struct bge_rx_bd));
4407
4408 if (tosync < 0) {
4409 tlen = (sc->bge_return_ring_cnt - rx_cons) *
4410 sizeof (struct bge_rx_bd);
4411 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4412 toff, tlen, BUS_DMASYNC_POSTREAD);
4413 tosync = -tosync;
4414 }
4415
4416 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4417 offset, tosync * sizeof (struct bge_rx_bd),
4418 BUS_DMASYNC_POSTREAD);
4419
4420 while (rx_cons != rx_prod) {
4421 struct bge_rx_bd *cur_rx;
4422 uint32_t rxidx;
4423 struct mbuf *m = NULL;
4424
4425 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons];
4426
4427 rxidx = cur_rx->bge_idx;
4428 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4429
4430 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4431 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4432 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4433 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
4434 jumbocnt++;
4435 bus_dmamap_sync(sc->bge_dmatag,
4436 sc->bge_cdata.bge_rx_jumbo_map,
4437 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf,
4438 BGE_JLEN, BUS_DMASYNC_POSTREAD);
4439 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4440 ifp->if_ierrors++;
4441 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
4442 continue;
4443 }
4444 if (bge_newbuf_jumbo(sc, sc->bge_jumbo,
4445 NULL)== ENOBUFS) {
4446 ifp->if_ierrors++;
4447 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
4448 continue;
4449 }
4450 } else {
4451 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4452 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4453
4454 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
4455 stdcnt++;
4456 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
4457 sc->bge_cdata.bge_rx_std_map[rxidx] = 0;
4458 if (dmamap == NULL) {
4459 ifp->if_ierrors++;
4460 bge_newbuf_std(sc, sc->bge_std, m, dmamap);
4461 continue;
4462 }
4463 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0,
4464 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
4465 bus_dmamap_unload(sc->bge_dmatag, dmamap);
4466 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4467 ifp->if_ierrors++;
4468 bge_newbuf_std(sc, sc->bge_std, m, dmamap);
4469 continue;
4470 }
4471 if (bge_newbuf_std(sc, sc->bge_std,
4472 NULL, dmamap) == ENOBUFS) {
4473 ifp->if_ierrors++;
4474 bge_newbuf_std(sc, sc->bge_std, m, dmamap);
4475 continue;
4476 }
4477 }
4478
4479 ifp->if_ipackets++;
4480 #ifndef __NO_STRICT_ALIGNMENT
4481 /*
4482 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect,
4483 * the Rx buffer has the layer-2 header unaligned.
4484 * If our CPU requires alignment, re-align by copying.
4485 */
4486 if (sc->bge_flags & BGEF_RX_ALIGNBUG) {
4487 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data,
4488 cur_rx->bge_len);
4489 m->m_data += ETHER_ALIGN;
4490 }
4491 #endif
4492
4493 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4494 m->m_pkthdr.rcvif = ifp;
4495
4496 /*
4497 * Handle BPF listeners. Let the BPF user see the packet.
4498 */
4499 bpf_mtap(ifp, m);
4500
4501 bge_rxcsum(sc, cur_rx, m);
4502
4503 /*
4504 * If we received a packet with a vlan tag, pass it
4505 * to vlan_input() instead of ether_input().
4506 */
4507 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4508 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue);
4509 }
4510
4511 (*ifp->if_input)(ifp, m);
4512 }
4513
4514 sc->bge_rx_saved_considx = rx_cons;
4515 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4516 if (stdcnt)
4517 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
4518 if (jumbocnt)
4519 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
4520 }
4521
4522 static void
4523 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4524 {
4525
4526 if (BGE_IS_57765_PLUS(sc)) {
4527 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4528 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0)
4529 m->m_pkthdr.csum_flags = M_CSUM_IPv4;
4530 if ((cur_rx->bge_error_flag &
4531 BGE_RXERRFLAG_IP_CSUM_NOK) != 0)
4532 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
4533 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4534 m->m_pkthdr.csum_data =
4535 cur_rx->bge_tcp_udp_csum;
4536 m->m_pkthdr.csum_flags |=
4537 (M_CSUM_TCPv4|M_CSUM_UDPv4|
4538 M_CSUM_DATA);
4539 }
4540 }
4541 } else {
4542 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0)
4543 m->m_pkthdr.csum_flags = M_CSUM_IPv4;
4544 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0)
4545 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
4546 /*
4547 * Rx transport checksum-offload may also
4548 * have bugs with packets which, when transmitted,
4549 * were `runts' requiring padding.
4550 */
4551 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4552 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/
4553 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) {
4554 m->m_pkthdr.csum_data =
4555 cur_rx->bge_tcp_udp_csum;
4556 m->m_pkthdr.csum_flags |=
4557 (M_CSUM_TCPv4|M_CSUM_UDPv4|
4558 M_CSUM_DATA);
4559 }
4560 }
4561 }
4562
4563 static void
4564 bge_txeof(struct bge_softc *sc)
4565 {
4566 struct bge_tx_bd *cur_tx = NULL;
4567 struct ifnet *ifp;
4568 struct txdmamap_pool_entry *dma;
4569 bus_addr_t offset, toff;
4570 bus_size_t tlen;
4571 int tosync;
4572 struct mbuf *m;
4573
4574 ifp = &sc->ethercom.ec_if;
4575
4576 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4577 offsetof(struct bge_ring_data, bge_status_block),
4578 sizeof (struct bge_status_block),
4579 BUS_DMASYNC_POSTREAD);
4580
4581 offset = offsetof(struct bge_ring_data, bge_tx_ring);
4582 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx -
4583 sc->bge_tx_saved_considx;
4584
4585 if (tosync != 0)
4586 rnd_add_uint32(&sc->rnd_source, tosync);
4587
4588 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd));
4589
4590 if (tosync < 0) {
4591 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
4592 sizeof (struct bge_tx_bd);
4593 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4594 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
4595 tosync = -tosync;
4596 }
4597
4598 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4599 offset, tosync * sizeof (struct bge_tx_bd),
4600 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
4601
4602 /*
4603 * Go through our tx ring and free mbufs for those
4604 * frames that have been sent.
4605 */
4606 while (sc->bge_tx_saved_considx !=
4607 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
4608 uint32_t idx = 0;
4609
4610 idx = sc->bge_tx_saved_considx;
4611 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
4612 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4613 ifp->if_opackets++;
4614 m = sc->bge_cdata.bge_tx_chain[idx];
4615 if (m != NULL) {
4616 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4617 dma = sc->txdma[idx];
4618 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0,
4619 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
4620 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
4621 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
4622 sc->txdma[idx] = NULL;
4623
4624 m_freem(m);
4625 }
4626 sc->bge_txcnt--;
4627 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4628 ifp->if_timer = 0;
4629 }
4630
4631 if (cur_tx != NULL)
4632 ifp->if_flags &= ~IFF_OACTIVE;
4633 }
4634
4635 static int
4636 bge_intr(void *xsc)
4637 {
4638 struct bge_softc *sc;
4639 struct ifnet *ifp;
4640 uint32_t statusword;
4641 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE;
4642
4643 sc = xsc;
4644 ifp = &sc->ethercom.ec_if;
4645
4646 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */
4647 if (BGE_IS_5717_PLUS(sc))
4648 intrmask = 0;
4649
4650 /* It is possible for the interrupt to arrive before
4651 * the status block is updated prior to the interrupt.
4652 * Reading the PCI State register will confirm whether the
4653 * interrupt is ours and will flush the status block.
4654 */
4655
4656 /* read status word from status block */
4657 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
4658 offsetof(struct bge_ring_data, bge_status_block),
4659 sizeof (struct bge_status_block),
4660 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4661 statusword = sc->bge_rdata->bge_status_block.bge_status;
4662
4663 if ((statusword & BGE_STATFLAG_UPDATED) ||
4664 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) {
4665 /* Ack interrupt and stop others from occuring. */
4666 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1);
4667
4668 BGE_EVCNT_INCR(sc->bge_ev_intr);
4669
4670 /* clear status word */
4671 sc->bge_rdata->bge_status_block.bge_status = 0;
4672
4673 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
4674 statusword & BGE_STATFLAG_LINKSTATE_CHANGED ||
4675 BGE_STS_BIT(sc, BGE_STS_LINK_EVT))
4676 bge_link_upd(sc);
4677
4678 if (ifp->if_flags & IFF_RUNNING) {
4679 /* Check RX return ring producer/consumer */
4680 bge_rxeof(sc);
4681
4682 /* Check TX ring producer/consumer */
4683 bge_txeof(sc);
4684 }
4685
4686 if (sc->bge_pending_rxintr_change) {
4687 uint32_t rx_ticks = sc->bge_rx_coal_ticks;
4688 uint32_t rx_bds = sc->bge_rx_max_coal_bds;
4689
4690 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks);
4691 DELAY(10);
4692 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4693
4694 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds);
4695 DELAY(10);
4696 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4697
4698 sc->bge_pending_rxintr_change = 0;
4699 }
4700 bge_handle_events(sc);
4701
4702 /* Re-enable interrupts. */
4703 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0);
4704
4705 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
4706 bge_start(ifp);
4707
4708 return 1;
4709 } else
4710 return 0;
4711 }
4712
4713 static void
4714 bge_asf_driver_up(struct bge_softc *sc)
4715 {
4716 if (sc->bge_asf_mode & ASF_STACKUP) {
4717 /* Send ASF heartbeat aprox. every 2s */
4718 if (sc->bge_asf_count)
4719 sc->bge_asf_count --;
4720 else {
4721 sc->bge_asf_count = 2;
4722
4723 bge_wait_for_event_ack(sc);
4724
4725 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4726 BGE_FW_CMD_DRV_ALIVE);
4727 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4728 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4729 BGE_FW_HB_TIMEOUT_SEC);
4730 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT,
4731 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4732 BGE_RX_CPU_DRV_EVENT);
4733 }
4734 }
4735 }
4736
4737 static void
4738 bge_tick(void *xsc)
4739 {
4740 struct bge_softc *sc = xsc;
4741 struct mii_data *mii = &sc->bge_mii;
4742 int s;
4743
4744 s = splnet();
4745
4746 if (BGE_IS_5705_PLUS(sc))
4747 bge_stats_update_regs(sc);
4748 else
4749 bge_stats_update(sc);
4750
4751 if (sc->bge_flags & BGEF_FIBER_TBI) {
4752 /*
4753 * Since in TBI mode auto-polling can't be used we should poll
4754 * link status manually. Here we register pending link event
4755 * and trigger interrupt.
4756 */
4757 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT);
4758 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4759 } else {
4760 /*
4761 * Do not touch PHY if we have link up. This could break
4762 * IPMI/ASF mode or produce extra input errors.
4763 * (extra input errors was reported for bcm5701 & bcm5704).
4764 */
4765 if (!BGE_STS_BIT(sc, BGE_STS_LINK))
4766 mii_tick(mii);
4767 }
4768
4769 bge_asf_driver_up(sc);
4770
4771 callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
4772
4773 splx(s);
4774 }
4775
4776 static void
4777 bge_stats_update_regs(struct bge_softc *sc)
4778 {
4779 struct ifnet *ifp = &sc->ethercom.ec_if;
4780
4781 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
4782 offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
4783
4784 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4785 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4786 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4787 }
4788
4789 static void
4790 bge_stats_update(struct bge_softc *sc)
4791 {
4792 struct ifnet *ifp = &sc->ethercom.ec_if;
4793 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4794
4795 #define READ_STAT(sc, stats, stat) \
4796 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4797
4798 ifp->if_collisions +=
4799 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) +
4800 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) +
4801 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) +
4802 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) -
4803 ifp->if_collisions;
4804
4805 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff,
4806 READ_STAT(sc, stats, outXoffSent.bge_addr_lo));
4807 BGE_EVCNT_UPD(sc->bge_ev_tx_xon,
4808 READ_STAT(sc, stats, outXonSent.bge_addr_lo));
4809 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff,
4810 READ_STAT(sc, stats,
4811 xoffPauseFramesReceived.bge_addr_lo));
4812 BGE_EVCNT_UPD(sc->bge_ev_rx_xon,
4813 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo));
4814 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl,
4815 READ_STAT(sc, stats,
4816 macControlFramesReceived.bge_addr_lo));
4817 BGE_EVCNT_UPD(sc->bge_ev_xoffentered,
4818 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo));
4819
4820 #undef READ_STAT
4821
4822 #ifdef notdef
4823 ifp->if_collisions +=
4824 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
4825 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
4826 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
4827 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
4828 ifp->if_collisions;
4829 #endif
4830 }
4831
4832 /*
4833 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4834 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4835 * but when such padded frames employ the bge IP/TCP checksum offload,
4836 * the hardware checksum assist gives incorrect results (possibly
4837 * from incorporating its own padding into the UDP/TCP checksum; who knows).
4838 * If we pad such runts with zeros, the onboard checksum comes out correct.
4839 */
4840 static inline int
4841 bge_cksum_pad(struct mbuf *pkt)
4842 {
4843 struct mbuf *last = NULL;
4844 int padlen;
4845
4846 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len;
4847
4848 /* if there's only the packet-header and we can pad there, use it. */
4849 if (pkt->m_pkthdr.len == pkt->m_len &&
4850 M_TRAILINGSPACE(pkt) >= padlen) {
4851 last = pkt;
4852 } else {
4853 /*
4854 * Walk packet chain to find last mbuf. We will either
4855 * pad there, or append a new mbuf and pad it
4856 * (thus perhaps avoiding the bcm5700 dma-min bug).
4857 */
4858 for (last = pkt; last->m_next != NULL; last = last->m_next) {
4859 continue; /* do nothing */
4860 }
4861
4862 /* `last' now points to last in chain. */
4863 if (M_TRAILINGSPACE(last) < padlen) {
4864 /* Allocate new empty mbuf, pad it. Compact later. */
4865 struct mbuf *n;
4866 MGET(n, M_DONTWAIT, MT_DATA);
4867 if (n == NULL)
4868 return ENOBUFS;
4869 n->m_len = 0;
4870 last->m_next = n;
4871 last = n;
4872 }
4873 }
4874
4875 KDASSERT(!M_READONLY(last));
4876 KDASSERT(M_TRAILINGSPACE(last) >= padlen);
4877
4878 /* Now zero the pad area, to avoid the bge cksum-assist bug */
4879 memset(mtod(last, char *) + last->m_len, 0, padlen);
4880 last->m_len += padlen;
4881 pkt->m_pkthdr.len += padlen;
4882 return 0;
4883 }
4884
4885 /*
4886 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
4887 */
4888 static inline int
4889 bge_compact_dma_runt(struct mbuf *pkt)
4890 {
4891 struct mbuf *m, *prev;
4892 int totlen;
4893
4894 prev = NULL;
4895 totlen = 0;
4896
4897 for (m = pkt; m != NULL; prev = m,m = m->m_next) {
4898 int mlen = m->m_len;
4899 int shortfall = 8 - mlen ;
4900
4901 totlen += mlen;
4902 if (mlen == 0)
4903 continue;
4904 if (mlen >= 8)
4905 continue;
4906
4907 /* If we get here, mbuf data is too small for DMA engine.
4908 * Try to fix by shuffling data to prev or next in chain.
4909 * If that fails, do a compacting deep-copy of the whole chain.
4910 */
4911
4912 /* Internal frag. If fits in prev, copy it there. */
4913 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) {
4914 memcpy(prev->m_data + prev->m_len, m->m_data, mlen);
4915 prev->m_len += mlen;
4916 m->m_len = 0;
4917 /* XXX stitch chain */
4918 prev->m_next = m_free(m);
4919 m = prev;
4920 continue;
4921 }
4922 else if (m->m_next != NULL &&
4923 M_TRAILINGSPACE(m) >= shortfall &&
4924 m->m_next->m_len >= (8 + shortfall)) {
4925 /* m is writable and have enough data in next, pull up. */
4926
4927 memcpy(m->m_data + m->m_len, m->m_next->m_data,
4928 shortfall);
4929 m->m_len += shortfall;
4930 m->m_next->m_len -= shortfall;
4931 m->m_next->m_data += shortfall;
4932 }
4933 else if (m->m_next == NULL || 1) {
4934 /* Got a runt at the very end of the packet.
4935 * borrow data from the tail of the preceding mbuf and
4936 * update its length in-place. (The original data is still
4937 * valid, so we can do this even if prev is not writable.)
4938 */
4939
4940 /* if we'd make prev a runt, just move all of its data. */
4941 KASSERT(prev != NULL /*, ("runt but null PREV")*/);
4942 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/);
4943
4944 if ((prev->m_len - shortfall) < 8)
4945 shortfall = prev->m_len;
4946
4947 #ifdef notyet /* just do the safe slow thing for now */
4948 if (!M_READONLY(m)) {
4949 if (M_LEADINGSPACE(m) < shorfall) {
4950 void *m_dat;
4951 m_dat = (m->m_flags & M_PKTHDR) ?
4952 m->m_pktdat : m->dat;
4953 memmove(m_dat, mtod(m, void*), m->m_len);
4954 m->m_data = m_dat;
4955 }
4956 } else
4957 #endif /* just do the safe slow thing */
4958 {
4959 struct mbuf * n = NULL;
4960 int newprevlen = prev->m_len - shortfall;
4961
4962 MGET(n, M_NOWAIT, MT_DATA);
4963 if (n == NULL)
4964 return ENOBUFS;
4965 KASSERT(m->m_len + shortfall < MLEN
4966 /*,
4967 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/);
4968
4969 /* first copy the data we're stealing from prev */
4970 memcpy(n->m_data, prev->m_data + newprevlen,
4971 shortfall);
4972
4973 /* update prev->m_len accordingly */
4974 prev->m_len -= shortfall;
4975
4976 /* copy data from runt m */
4977 memcpy(n->m_data + shortfall, m->m_data,
4978 m->m_len);
4979
4980 /* n holds what we stole from prev, plus m */
4981 n->m_len = shortfall + m->m_len;
4982
4983 /* stitch n into chain and free m */
4984 n->m_next = m->m_next;
4985 prev->m_next = n;
4986 /* KASSERT(m->m_next == NULL); */
4987 m->m_next = NULL;
4988 m_free(m);
4989 m = n; /* for continuing loop */
4990 }
4991 }
4992 }
4993 return 0;
4994 }
4995
4996 /*
4997 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
4998 * pointers to descriptors.
4999 */
5000 static int
5001 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
5002 {
5003 struct bge_tx_bd *f = NULL;
5004 uint32_t frag, cur;
5005 uint16_t csum_flags = 0;
5006 uint16_t txbd_tso_flags = 0;
5007 struct txdmamap_pool_entry *dma;
5008 bus_dmamap_t dmamap;
5009 int i = 0;
5010 struct m_tag *mtag;
5011 int use_tso, maxsegsize, error;
5012
5013 cur = frag = *txidx;
5014
5015 if (m_head->m_pkthdr.csum_flags) {
5016 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
5017 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5018 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4))
5019 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5020 }
5021
5022 /*
5023 * If we were asked to do an outboard checksum, and the NIC
5024 * has the bug where it sometimes adds in the Ethernet padding,
5025 * explicitly pad with zeros so the cksum will be correct either way.
5026 * (For now, do this for all chip versions, until newer
5027 * are confirmed to not require the workaround.)
5028 */
5029 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 ||
5030 #ifdef notyet
5031 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||
5032 #endif
5033 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD)
5034 goto check_dma_bug;
5035
5036 if (bge_cksum_pad(m_head) != 0)
5037 return ENOBUFS;
5038
5039 check_dma_bug:
5040 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX))
5041 goto doit;
5042
5043 /*
5044 * bcm5700 Revision B silicon cannot handle DMA descriptors with
5045 * less than eight bytes. If we encounter a teeny mbuf
5046 * at the end of a chain, we can pad. Otherwise, copy.
5047 */
5048 if (bge_compact_dma_runt(m_head) != 0)
5049 return ENOBUFS;
5050
5051 doit:
5052 dma = SLIST_FIRST(&sc->txdma_list);
5053 if (dma == NULL)
5054 return ENOBUFS;
5055 dmamap = dma->dmamap;
5056
5057 /*
5058 * Set up any necessary TSO state before we start packing...
5059 */
5060 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
5061 if (!use_tso) {
5062 maxsegsize = 0;
5063 } else { /* TSO setup */
5064 unsigned mss;
5065 struct ether_header *eh;
5066 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset;
5067 struct mbuf * m0 = m_head;
5068 struct ip *ip;
5069 struct tcphdr *th;
5070 int iphl, hlen;
5071
5072 /*
5073 * XXX It would be nice if the mbuf pkthdr had offset
5074 * fields for the protocol headers.
5075 */
5076
5077 eh = mtod(m0, struct ether_header *);
5078 switch (htons(eh->ether_type)) {
5079 case ETHERTYPE_IP:
5080 offset = ETHER_HDR_LEN;
5081 break;
5082
5083 case ETHERTYPE_VLAN:
5084 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
5085 break;
5086
5087 default:
5088 /*
5089 * Don't support this protocol or encapsulation.
5090 */
5091 return ENOBUFS;
5092 }
5093
5094 /*
5095 * TCP/IP headers are in the first mbuf; we can do
5096 * this the easy way.
5097 */
5098 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
5099 hlen = iphl + offset;
5100 if (__predict_false(m0->m_len <
5101 (hlen + sizeof(struct tcphdr)))) {
5102
5103 aprint_debug_dev(sc->bge_dev,
5104 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd,"
5105 "not handled yet\n",
5106 m0->m_len, hlen+ sizeof(struct tcphdr));
5107 #ifdef NOTYET
5108 /*
5109 * XXX jonathan (at) NetBSD.org: untested.
5110 * how to force this branch to be taken?
5111 */
5112 BGE_EVCNT_INCR(sc->bge_ev_txtsopain);
5113
5114 m_copydata(m0, offset, sizeof(ip), &ip);
5115 m_copydata(m0, hlen, sizeof(th), &th);
5116
5117 ip.ip_len = 0;
5118
5119 m_copyback(m0, hlen + offsetof(struct ip, ip_len),
5120 sizeof(ip.ip_len), &ip.ip_len);
5121
5122 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
5123 ip.ip_dst.s_addr, htons(IPPROTO_TCP));
5124
5125 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
5126 sizeof(th.th_sum), &th.th_sum);
5127
5128 hlen += th.th_off << 2;
5129 iptcp_opt_words = hlen;
5130 #else
5131 /*
5132 * if_wm "hard" case not yet supported, can we not
5133 * mandate it out of existence?
5134 */
5135 (void) ip; (void)th; (void) ip_tcp_hlen;
5136
5137 return ENOBUFS;
5138 #endif
5139 } else {
5140 ip = (struct ip *) (mtod(m0, char *) + offset);
5141 th = (struct tcphdr *) (mtod(m0, char *) + hlen);
5142 ip_tcp_hlen = iphl + (th->th_off << 2);
5143
5144 /* Total IP/TCP options, in 32-bit words */
5145 iptcp_opt_words = (ip_tcp_hlen
5146 - sizeof(struct tcphdr)
5147 - sizeof(struct ip)) >> 2;
5148 }
5149 if (BGE_IS_575X_PLUS(sc)) {
5150 th->th_sum = 0;
5151 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM);
5152 } else {
5153 /*
5154 * XXX jonathan (at) NetBSD.org: 5705 untested.
5155 * Requires TSO firmware patch for 5701/5703/5704.
5156 */
5157 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
5158 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
5159 }
5160
5161 mss = m_head->m_pkthdr.segsz;
5162 txbd_tso_flags |=
5163 BGE_TXBDFLAG_CPU_PRE_DMA |
5164 BGE_TXBDFLAG_CPU_POST_DMA;
5165
5166 /*
5167 * Our NIC TSO-assist assumes TSO has standard, optionless
5168 * IPv4 and TCP headers, which total 40 bytes. By default,
5169 * the NIC copies 40 bytes of IP/TCP header from the
5170 * supplied header into the IP/TCP header portion of
5171 * each post-TSO-segment. If the supplied packet has IP or
5172 * TCP options, we need to tell the NIC to copy those extra
5173 * bytes into each post-TSO header, in addition to the normal
5174 * 40-byte IP/TCP header (and to leave space accordingly).
5175 * Unfortunately, the driver encoding of option length
5176 * varies across different ASIC families.
5177 */
5178 tcp_seg_flags = 0;
5179 if (iptcp_opt_words) {
5180 if (BGE_IS_5705_PLUS(sc)) {
5181 tcp_seg_flags =
5182 iptcp_opt_words << 11;
5183 } else {
5184 txbd_tso_flags |=
5185 iptcp_opt_words << 12;
5186 }
5187 }
5188 maxsegsize = mss | tcp_seg_flags;
5189 ip->ip_len = htons(mss + ip_tcp_hlen);
5190
5191 } /* TSO setup */
5192
5193 /*
5194 * Start packing the mbufs in this chain into
5195 * the fragment pointers. Stop when we run out
5196 * of fragments or hit the end of the mbuf chain.
5197 */
5198 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head,
5199 BUS_DMA_NOWAIT);
5200 if (error)
5201 return ENOBUFS;
5202 /*
5203 * Sanity check: avoid coming within 16 descriptors
5204 * of the end of the ring.
5205 */
5206 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
5207 BGE_TSO_PRINTF(("%s: "
5208 " dmamap_load_mbuf too close to ring wrap\n",
5209 device_xname(sc->bge_dev)));
5210 goto fail_unload;
5211 }
5212
5213 mtag = sc->ethercom.ec_nvlans ?
5214 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL;
5215
5216
5217 /* Iterate over dmap-map fragments. */
5218 for (i = 0; i < dmamap->dm_nsegs; i++) {
5219 f = &sc->bge_rdata->bge_tx_ring[frag];
5220 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
5221 break;
5222
5223 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr);
5224 f->bge_len = dmamap->dm_segs[i].ds_len;
5225
5226 /*
5227 * For 5751 and follow-ons, for TSO we must turn
5228 * off checksum-assist flag in the tx-descr, and
5229 * supply the ASIC-revision-specific encoding
5230 * of TSO flags and segsize.
5231 */
5232 if (use_tso) {
5233 if (BGE_IS_575X_PLUS(sc) || i == 0) {
5234 f->bge_rsvd = maxsegsize;
5235 f->bge_flags = csum_flags | txbd_tso_flags;
5236 } else {
5237 f->bge_rsvd = 0;
5238 f->bge_flags =
5239 (csum_flags | txbd_tso_flags) & 0x0fff;
5240 }
5241 } else {
5242 f->bge_rsvd = 0;
5243 f->bge_flags = csum_flags;
5244 }
5245
5246 if (mtag != NULL) {
5247 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
5248 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
5249 } else {
5250 f->bge_vlan_tag = 0;
5251 }
5252 cur = frag;
5253 BGE_INC(frag, BGE_TX_RING_CNT);
5254 }
5255
5256 if (i < dmamap->dm_nsegs) {
5257 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n",
5258 device_xname(sc->bge_dev), i, dmamap->dm_nsegs));
5259 goto fail_unload;
5260 }
5261
5262 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
5263 BUS_DMASYNC_PREWRITE);
5264
5265 if (frag == sc->bge_tx_saved_considx) {
5266 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n",
5267 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx));
5268
5269 goto fail_unload;
5270 }
5271
5272 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
5273 sc->bge_cdata.bge_tx_chain[cur] = m_head;
5274 SLIST_REMOVE_HEAD(&sc->txdma_list, link);
5275 sc->txdma[cur] = dma;
5276 sc->bge_txcnt += dmamap->dm_nsegs;
5277
5278 *txidx = frag;
5279
5280 return 0;
5281
5282 fail_unload:
5283 bus_dmamap_unload(sc->bge_dmatag, dmamap);
5284
5285 return ENOBUFS;
5286 }
5287
5288 /*
5289 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5290 * to the mbuf data regions directly in the transmit descriptors.
5291 */
5292 static void
5293 bge_start(struct ifnet *ifp)
5294 {
5295 struct bge_softc *sc;
5296 struct mbuf *m_head = NULL;
5297 uint32_t prodidx;
5298 int pkts = 0;
5299
5300 sc = ifp->if_softc;
5301
5302 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
5303 return;
5304
5305 prodidx = sc->bge_tx_prodidx;
5306
5307 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
5308 IFQ_POLL(&ifp->if_snd, m_head);
5309 if (m_head == NULL)
5310 break;
5311
5312 #if 0
5313 /*
5314 * XXX
5315 * safety overkill. If this is a fragmented packet chain
5316 * with delayed TCP/UDP checksums, then only encapsulate
5317 * it if we have enough descriptors to handle the entire
5318 * chain at once.
5319 * (paranoia -- may not actually be needed)
5320 */
5321 if (m_head->m_flags & M_FIRSTFRAG &&
5322 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
5323 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
5324 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) {
5325 ifp->if_flags |= IFF_OACTIVE;
5326 break;
5327 }
5328 }
5329 #endif
5330
5331 /*
5332 * Pack the data into the transmit ring. If we
5333 * don't have room, set the OACTIVE flag and wait
5334 * for the NIC to drain the ring.
5335 */
5336 if (bge_encap(sc, m_head, &prodidx)) {
5337 ifp->if_flags |= IFF_OACTIVE;
5338 break;
5339 }
5340
5341 /* now we are committed to transmit the packet */
5342 IFQ_DEQUEUE(&ifp->if_snd, m_head);
5343 pkts++;
5344
5345 /*
5346 * If there's a BPF listener, bounce a copy of this frame
5347 * to him.
5348 */
5349 bpf_mtap(ifp, m_head);
5350 }
5351 if (pkts == 0)
5352 return;
5353
5354 /* Transmit */
5355 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5356 /* 5700 b2 errata */
5357 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
5358 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5359
5360 sc->bge_tx_prodidx = prodidx;
5361
5362 /*
5363 * Set a timeout in case the chip goes out to lunch.
5364 */
5365 ifp->if_timer = 5;
5366 }
5367
5368 static int
5369 bge_init(struct ifnet *ifp)
5370 {
5371 struct bge_softc *sc = ifp->if_softc;
5372 const uint16_t *m;
5373 uint32_t mode, reg;
5374 int s, error = 0;
5375
5376 s = splnet();
5377
5378 ifp = &sc->ethercom.ec_if;
5379
5380 /* Cancel pending I/O and flush buffers. */
5381 bge_stop(ifp, 0);
5382
5383 bge_stop_fw(sc);
5384 bge_sig_pre_reset(sc, BGE_RESET_START);
5385 bge_reset(sc);
5386 bge_sig_legacy(sc, BGE_RESET_START);
5387 bge_sig_post_reset(sc, BGE_RESET_START);
5388
5389 bge_chipinit(sc);
5390
5391 /*
5392 * Init the various state machines, ring
5393 * control blocks and firmware.
5394 */
5395 error = bge_blockinit(sc);
5396 if (error != 0) {
5397 aprint_error_dev(sc->bge_dev, "initialization error %d\n",
5398 error);
5399 splx(s);
5400 return error;
5401 }
5402
5403 ifp = &sc->ethercom.ec_if;
5404
5405 /* 5718 step 25, 57XX step 54 */
5406 /* Specify MTU. */
5407 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5408 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
5409
5410 /* 5718 step 23 */
5411 /* Load our MAC address. */
5412 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]);
5413 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5414 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5415
5416 /* Enable or disable promiscuous mode as needed. */
5417 if (ifp->if_flags & IFF_PROMISC)
5418 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5419 else
5420 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5421
5422 /* Program multicast filter. */
5423 bge_setmulti(sc);
5424
5425 /* Init RX ring. */
5426 bge_init_rx_ring_std(sc);
5427
5428 /*
5429 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5430 * memory to insure that the chip has in fact read the first
5431 * entry of the ring.
5432 */
5433 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5434 uint32_t v, i;
5435 for (i = 0; i < 10; i++) {
5436 DELAY(20);
5437 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5438 if (v == (MCLBYTES - ETHER_ALIGN))
5439 break;
5440 }
5441 if (i == 10)
5442 aprint_error_dev(sc->bge_dev,
5443 "5705 A0 chip failed to load RX ring\n");
5444 }
5445
5446 /* Init jumbo RX ring. */
5447 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
5448 bge_init_rx_ring_jumbo(sc);
5449
5450 /* Init our RX return ring index */
5451 sc->bge_rx_saved_considx = 0;
5452
5453 /* Init TX ring. */
5454 bge_init_tx_ring(sc);
5455
5456 /* 5718 step 63, 57XX step 94 */
5457 /* Enable TX MAC state machine lockup fix. */
5458 mode = CSR_READ_4(sc, BGE_TX_MODE);
5459 if (BGE_IS_5755_PLUS(sc) ||
5460 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
5461 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5462 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
5463 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5464 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5465 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5466 }
5467
5468 /* Turn on transmitter */
5469 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5470 /* 5718 step 64 */
5471 DELAY(100);
5472
5473 /* 5718 step 65, 57XX step 95 */
5474 /* Turn on receiver */
5475 mode = CSR_READ_4(sc, BGE_RX_MODE);
5476 if (BGE_IS_5755_PLUS(sc))
5477 mode |= BGE_RXMODE_IPV6_ENABLE;
5478 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5479 /* 5718 step 66 */
5480 DELAY(10);
5481
5482 /* 5718 step 12, 57XX step 37 */
5483 /*
5484 * XXX Doucments of 5718 series and 577xx say the recommended value
5485 * is 1, but tg3 set 1 only on 57765 series.
5486 */
5487 if (BGE_IS_57765_PLUS(sc))
5488 reg = 1;
5489 else
5490 reg = 2;
5491 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg);
5492
5493 /* Tell firmware we're alive. */
5494 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5495
5496 /* Enable host interrupts. */
5497 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5498 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5499 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0);
5500
5501 if ((error = bge_ifmedia_upd(ifp)) != 0)
5502 goto out;
5503
5504 ifp->if_flags |= IFF_RUNNING;
5505 ifp->if_flags &= ~IFF_OACTIVE;
5506
5507 callout_reset(&sc->bge_timeout, hz, bge_tick, sc);
5508
5509 out:
5510 sc->bge_if_flags = ifp->if_flags;
5511 splx(s);
5512
5513 return error;
5514 }
5515
5516 /*
5517 * Set media options.
5518 */
5519 static int
5520 bge_ifmedia_upd(struct ifnet *ifp)
5521 {
5522 struct bge_softc *sc = ifp->if_softc;
5523 struct mii_data *mii = &sc->bge_mii;
5524 struct ifmedia *ifm = &sc->bge_ifmedia;
5525 int rc;
5526
5527 /* If this is a 1000baseX NIC, enable the TBI port. */
5528 if (sc->bge_flags & BGEF_FIBER_TBI) {
5529 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5530 return EINVAL;
5531 switch (IFM_SUBTYPE(ifm->ifm_media)) {
5532 case IFM_AUTO:
5533 /*
5534 * The BCM5704 ASIC appears to have a special
5535 * mechanism for programming the autoneg
5536 * advertisement registers in TBI mode.
5537 */
5538 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
5539 uint32_t sgdig;
5540 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5541 if (sgdig & BGE_SGDIGSTS_DONE) {
5542 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5543 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5544 sgdig |= BGE_SGDIGCFG_AUTO |
5545 BGE_SGDIGCFG_PAUSE_CAP |
5546 BGE_SGDIGCFG_ASYM_PAUSE;
5547 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG,
5548 sgdig | BGE_SGDIGCFG_SEND);
5549 DELAY(5);
5550 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG,
5551 sgdig);
5552 }
5553 }
5554 break;
5555 case IFM_1000_SX:
5556 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5557 BGE_CLRBIT(sc, BGE_MAC_MODE,
5558 BGE_MACMODE_HALF_DUPLEX);
5559 } else {
5560 BGE_SETBIT(sc, BGE_MAC_MODE,
5561 BGE_MACMODE_HALF_DUPLEX);
5562 }
5563 DELAY(40);
5564 break;
5565 default:
5566 return EINVAL;
5567 }
5568 /* XXX 802.3x flow control for 1000BASE-SX */
5569 return 0;
5570 }
5571
5572 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT);
5573 if ((rc = mii_mediachg(mii)) == ENXIO)
5574 return 0;
5575
5576 /*
5577 * Force an interrupt so that we will call bge_link_upd
5578 * if needed and clear any pending link state attention.
5579 * Without this we are not getting any further interrupts
5580 * for link state changes and thus will not UP the link and
5581 * not be able to send in bge_start. The only way to get
5582 * things working was to receive a packet and get a RX intr.
5583 */
5584 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
5585 sc->bge_flags & BGEF_IS_5788)
5586 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5587 else
5588 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5589
5590 return rc;
5591 }
5592
5593 /*
5594 * Report current media status.
5595 */
5596 static void
5597 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5598 {
5599 struct bge_softc *sc = ifp->if_softc;
5600 struct mii_data *mii = &sc->bge_mii;
5601
5602 if (sc->bge_flags & BGEF_FIBER_TBI) {
5603 ifmr->ifm_status = IFM_AVALID;
5604 ifmr->ifm_active = IFM_ETHER;
5605 if (CSR_READ_4(sc, BGE_MAC_STS) &
5606 BGE_MACSTAT_TBI_PCS_SYNCHED)
5607 ifmr->ifm_status |= IFM_ACTIVE;
5608 ifmr->ifm_active |= IFM_1000_SX;
5609 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5610 ifmr->ifm_active |= IFM_HDX;
5611 else
5612 ifmr->ifm_active |= IFM_FDX;
5613 return;
5614 }
5615
5616 mii_pollstat(mii);
5617 ifmr->ifm_status = mii->mii_media_status;
5618 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) |
5619 sc->bge_flowflags;
5620 }
5621
5622 static int
5623 bge_ifflags_cb(struct ethercom *ec)
5624 {
5625 struct ifnet *ifp = &ec->ec_if;
5626 struct bge_softc *sc = ifp->if_softc;
5627 int change = ifp->if_flags ^ sc->bge_if_flags;
5628
5629 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0)
5630 return ENETRESET;
5631 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0)
5632 return 0;
5633
5634 if ((ifp->if_flags & IFF_PROMISC) == 0)
5635 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5636 else
5637 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
5638
5639 bge_setmulti(sc);
5640
5641 sc->bge_if_flags = ifp->if_flags;
5642 return 0;
5643 }
5644
5645 static int
5646 bge_ioctl(struct ifnet *ifp, u_long command, void *data)
5647 {
5648 struct bge_softc *sc = ifp->if_softc;
5649 struct ifreq *ifr = (struct ifreq *) data;
5650 int s, error = 0;
5651 struct mii_data *mii;
5652
5653 s = splnet();
5654
5655 switch (command) {
5656 case SIOCSIFMEDIA:
5657 /* XXX Flow control is not supported for 1000BASE-SX */
5658 if (sc->bge_flags & BGEF_FIBER_TBI) {
5659 ifr->ifr_media &= ~IFM_ETH_FMASK;
5660 sc->bge_flowflags = 0;
5661 }
5662
5663 /* Flow control requires full-duplex mode. */
5664 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
5665 (ifr->ifr_media & IFM_FDX) == 0) {
5666 ifr->ifr_media &= ~IFM_ETH_FMASK;
5667 }
5668 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
5669 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
5670 /* We can do both TXPAUSE and RXPAUSE. */
5671 ifr->ifr_media |=
5672 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
5673 }
5674 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
5675 }
5676 /* FALLTHROUGH */
5677 case SIOCGIFMEDIA:
5678 if (sc->bge_flags & BGEF_FIBER_TBI) {
5679 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
5680 command);
5681 } else {
5682 mii = &sc->bge_mii;
5683 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
5684 command);
5685 }
5686 break;
5687 default:
5688 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
5689 break;
5690
5691 error = 0;
5692
5693 if (command != SIOCADDMULTI && command != SIOCDELMULTI)
5694 ;
5695 else if (ifp->if_flags & IFF_RUNNING)
5696 bge_setmulti(sc);
5697 break;
5698 }
5699
5700 splx(s);
5701
5702 return error;
5703 }
5704
5705 static void
5706 bge_watchdog(struct ifnet *ifp)
5707 {
5708 struct bge_softc *sc;
5709
5710 sc = ifp->if_softc;
5711
5712 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n");
5713
5714 ifp->if_flags &= ~IFF_RUNNING;
5715 bge_init(ifp);
5716
5717 ifp->if_oerrors++;
5718 }
5719
5720 static void
5721 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)
5722 {
5723 int i;
5724
5725 BGE_CLRBIT_FLUSH(sc, reg, bit);
5726
5727 for (i = 0; i < 1000; i++) {
5728 delay(100);
5729 if ((CSR_READ_4(sc, reg) & bit) == 0)
5730 return;
5731 }
5732
5733 /*
5734 * Doesn't print only when the register is BGE_SRS_MODE. It occurs
5735 * on some environment (and once after boot?)
5736 */
5737 if (reg != BGE_SRS_MODE)
5738 aprint_error_dev(sc->bge_dev,
5739 "block failed to stop: reg 0x%lx, bit 0x%08x\n",
5740 (u_long)reg, bit);
5741 }
5742
5743 /*
5744 * Stop the adapter and free any mbufs allocated to the
5745 * RX and TX lists.
5746 */
5747 static void
5748 bge_stop(struct ifnet *ifp, int disable)
5749 {
5750 struct bge_softc *sc = ifp->if_softc;
5751
5752 callout_stop(&sc->bge_timeout);
5753
5754 /* Disable host interrupts. */
5755 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5756 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1);
5757
5758 /*
5759 * Tell firmware we're shutting down.
5760 */
5761 bge_stop_fw(sc);
5762 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5763
5764 /*
5765 * Disable all of the receiver blocks.
5766 */
5767 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5768 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5769 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5770 if (BGE_IS_5700_FAMILY(sc))
5771 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5772 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5773 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5774 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5775
5776 /*
5777 * Disable all of the transmit blocks.
5778 */
5779 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5780 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5781 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5782 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5783 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5784 if (BGE_IS_5700_FAMILY(sc))
5785 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5786 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5787
5788 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB);
5789 delay(40);
5790
5791 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
5792
5793 /*
5794 * Shut down all of the memory managers and related
5795 * state machines.
5796 */
5797 /* 5718 step 5a,5b */
5798 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5799 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5800 if (BGE_IS_5700_FAMILY(sc))
5801 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5802
5803 /* 5718 step 5c,5d */
5804 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5805 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5806
5807 if (BGE_IS_5700_FAMILY(sc)) {
5808 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5809 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5810 }
5811
5812 bge_reset(sc);
5813 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
5814 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
5815
5816 /*
5817 * Keep the ASF firmware running if up.
5818 */
5819 if (sc->bge_asf_mode & ASF_STACKUP)
5820 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5821 else
5822 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5823
5824 /* Free the RX lists. */
5825 bge_free_rx_ring_std(sc);
5826
5827 /* Free jumbo RX list. */
5828 if (BGE_IS_JUMBO_CAPABLE(sc))
5829 bge_free_rx_ring_jumbo(sc);
5830
5831 /* Free TX buffers. */
5832 bge_free_tx_ring(sc);
5833
5834 /*
5835 * Isolate/power down the PHY.
5836 */
5837 if (!(sc->bge_flags & BGEF_FIBER_TBI))
5838 mii_down(&sc->bge_mii);
5839
5840 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5841
5842 /* Clear MAC's link state (PHY may still have link UP). */
5843 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
5844
5845 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
5846 }
5847
5848 static void
5849 bge_link_upd(struct bge_softc *sc)
5850 {
5851 struct ifnet *ifp = &sc->ethercom.ec_if;
5852 struct mii_data *mii = &sc->bge_mii;
5853 uint32_t status;
5854 int link;
5855
5856 /* Clear 'pending link event' flag */
5857 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT);
5858
5859 /*
5860 * Process link state changes.
5861 * Grrr. The link status word in the status block does
5862 * not work correctly on the BCM5700 rev AX and BX chips,
5863 * according to all available information. Hence, we have
5864 * to enable MII interrupts in order to properly obtain
5865 * async link changes. Unfortunately, this also means that
5866 * we have to read the MAC status register to detect link
5867 * changes, thereby adding an additional register access to
5868 * the interrupt handler.
5869 */
5870
5871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) {
5872 status = CSR_READ_4(sc, BGE_MAC_STS);
5873 if (status & BGE_MACSTAT_MI_INTERRUPT) {
5874 mii_pollstat(mii);
5875
5876 if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
5877 mii->mii_media_status & IFM_ACTIVE &&
5878 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
5879 BGE_STS_SETBIT(sc, BGE_STS_LINK);
5880 else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
5881 (!(mii->mii_media_status & IFM_ACTIVE) ||
5882 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
5883 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
5884
5885 /* Clear the interrupt */
5886 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
5887 BGE_EVTENB_MI_INTERRUPT);
5888 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
5889 BRGPHY_MII_ISR);
5890 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
5891 BRGPHY_MII_IMR, BRGPHY_INTRS);
5892 }
5893 return;
5894 }
5895
5896 if (sc->bge_flags & BGEF_FIBER_TBI) {
5897 status = CSR_READ_4(sc, BGE_MAC_STS);
5898 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
5899 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) {
5900 BGE_STS_SETBIT(sc, BGE_STS_LINK);
5901 if (BGE_ASICREV(sc->bge_chipid)
5902 == BGE_ASICREV_BCM5704) {
5903 BGE_CLRBIT(sc, BGE_MAC_MODE,
5904 BGE_MACMODE_TBI_SEND_CFGS);
5905 DELAY(40);
5906 }
5907 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
5908 if_link_state_change(ifp, LINK_STATE_UP);
5909 }
5910 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) {
5911 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
5912 if_link_state_change(ifp, LINK_STATE_DOWN);
5913 }
5914 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) {
5915 /*
5916 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED
5917 * bit in status word always set. Workaround this bug by
5918 * reading PHY link status directly.
5919 */
5920 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)?
5921 BGE_STS_LINK : 0;
5922
5923 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) {
5924 mii_pollstat(mii);
5925
5926 if (!BGE_STS_BIT(sc, BGE_STS_LINK) &&
5927 mii->mii_media_status & IFM_ACTIVE &&
5928 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
5929 BGE_STS_SETBIT(sc, BGE_STS_LINK);
5930 else if (BGE_STS_BIT(sc, BGE_STS_LINK) &&
5931 (!(mii->mii_media_status & IFM_ACTIVE) ||
5932 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
5933 BGE_STS_CLRBIT(sc, BGE_STS_LINK);
5934 }
5935 } else {
5936 /*
5937 * For controllers that call mii_tick, we have to poll
5938 * link status.
5939 */
5940 mii_pollstat(mii);
5941 }
5942
5943 /* Clear the attention */
5944 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
5945 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
5946 BGE_MACSTAT_LINK_CHANGED);
5947 }
5948
5949 static int
5950 bge_sysctl_verify(SYSCTLFN_ARGS)
5951 {
5952 int error, t;
5953 struct sysctlnode node;
5954
5955 node = *rnode;
5956 t = *(int*)rnode->sysctl_data;
5957 node.sysctl_data = &t;
5958 error = sysctl_lookup(SYSCTLFN_CALL(&node));
5959 if (error || newp == NULL)
5960 return error;
5961
5962 #if 0
5963 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t,
5964 node.sysctl_num, rnode->sysctl_num));
5965 #endif
5966
5967 if (node.sysctl_num == bge_rxthresh_nodenum) {
5968 if (t < 0 || t >= NBGE_RX_THRESH)
5969 return EINVAL;
5970 bge_update_all_threshes(t);
5971 } else
5972 return EINVAL;
5973
5974 *(int*)rnode->sysctl_data = t;
5975
5976 return 0;
5977 }
5978
5979 /*
5980 * Set up sysctl(3) MIB, hw.bge.*.
5981 */
5982 static void
5983 bge_sysctl_init(struct bge_softc *sc)
5984 {
5985 int rc, bge_root_num;
5986 const struct sysctlnode *node;
5987
5988 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
5989 0, CTLTYPE_NODE, "bge",
5990 SYSCTL_DESCR("BGE interface controls"),
5991 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
5992 goto out;
5993 }
5994
5995 bge_root_num = node->sysctl_num;
5996
5997 /* BGE Rx interrupt mitigation level */
5998 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node,
5999 CTLFLAG_READWRITE,
6000 CTLTYPE_INT, "rx_lvl",
6001 SYSCTL_DESCR("BGE receive interrupt mitigation level"),
6002 bge_sysctl_verify, 0,
6003 &bge_rx_thresh_lvl,
6004 0, CTL_HW, bge_root_num, CTL_CREATE,
6005 CTL_EOL)) != 0) {
6006 goto out;
6007 }
6008
6009 bge_rxthresh_nodenum = node->sysctl_num;
6010
6011 return;
6012
6013 out:
6014 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
6015 }
6016
6017 #ifdef BGE_DEBUG
6018 void
6019 bge_debug_info(struct bge_softc *sc)
6020 {
6021
6022 printf("Hardware Flags:\n");
6023 if (BGE_IS_57765_PLUS(sc))
6024 printf(" - 57765 Plus\n");
6025 if (BGE_IS_5717_PLUS(sc))
6026 printf(" - 5717 Plus\n");
6027 if (BGE_IS_5755_PLUS(sc))
6028 printf(" - 5755 Plus\n");
6029 if (BGE_IS_575X_PLUS(sc))
6030 printf(" - 575X Plus\n");
6031 if (BGE_IS_5705_PLUS(sc))
6032 printf(" - 5705 Plus\n");
6033 if (BGE_IS_5714_FAMILY(sc))
6034 printf(" - 5714 Family\n");
6035 if (BGE_IS_5700_FAMILY(sc))
6036 printf(" - 5700 Family\n");
6037 if (sc->bge_flags & BGEF_IS_5788)
6038 printf(" - 5788\n");
6039 if (sc->bge_flags & BGEF_JUMBO_CAPABLE)
6040 printf(" - Supports Jumbo Frames\n");
6041 if (sc->bge_flags & BGEF_NO_EEPROM)
6042 printf(" - No EEPROM\n");
6043 if (sc->bge_flags & BGEF_PCIX)
6044 printf(" - PCI-X Bus\n");
6045 if (sc->bge_flags & BGEF_PCIE)
6046 printf(" - PCI Express Bus\n");
6047 if (sc->bge_flags & BGEF_RX_ALIGNBUG)
6048 printf(" - RX Alignment Bug\n");
6049 if (sc->bge_flags & BGEF_APE)
6050 printf(" - APE\n");
6051 if (sc->bge_flags & BGEF_CPMU_PRESENT)
6052 printf(" - CPMU\n");
6053 if (sc->bge_flags & BGEF_TSO)
6054 printf(" - TSO\n");
6055
6056 /* PHY related */
6057 if (sc->bge_phy_flags & BGEPHYF_NO_3LED)
6058 printf(" - No 3 LEDs\n");
6059 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG)
6060 printf(" - CRC bug\n");
6061 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG)
6062 printf(" - ADC bug\n");
6063 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG)
6064 printf(" - 5704 A0 bug\n");
6065 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG)
6066 printf(" - jitter bug\n");
6067 if (sc->bge_phy_flags & BGEPHYF_BER_BUG)
6068 printf(" - BER bug\n");
6069 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM)
6070 printf(" - adjust trim\n");
6071 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED)
6072 printf(" - no wirespeed\n");
6073
6074 /* ASF related */
6075 if (sc->bge_asf_mode & ASF_ENABLE)
6076 printf(" - ASF enable\n");
6077 if (sc->bge_asf_mode & ASF_NEW_HANDSHARE)
6078 printf(" - ASF new handshake\n");
6079 if (sc->bge_asf_mode & ASF_STACKUP)
6080 printf(" - ASF stackup\n");
6081 }
6082 #endif /* BGE_DEBUG */
6083
6084 static int
6085 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6086 {
6087 prop_dictionary_t dict;
6088 prop_data_t ea;
6089
6090 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0)
6091 return 1;
6092
6093 dict = device_properties(sc->bge_dev);
6094 ea = prop_dictionary_get(dict, "mac-address");
6095 if (ea != NULL) {
6096 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
6097 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
6098 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
6099 return 0;
6100 }
6101
6102 return 1;
6103 }
6104
6105 static int
6106 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6107 {
6108 uint32_t mac_addr;
6109
6110 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6111 if ((mac_addr >> 16) == 0x484b) {
6112 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6113 ether_addr[1] = (uint8_t)mac_addr;
6114 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6115 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6116 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6117 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6118 ether_addr[5] = (uint8_t)mac_addr;
6119 return 0;
6120 }
6121 return 1;
6122 }
6123
6124 static int
6125 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6126 {
6127 int mac_offset = BGE_EE_MAC_OFFSET;
6128
6129 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
6130 mac_offset = BGE_EE_MAC_OFFSET_5906;
6131
6132 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6133 ETHER_ADDR_LEN));
6134 }
6135
6136 static int
6137 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6138 {
6139
6140 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
6141 return 1;
6142
6143 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6144 ETHER_ADDR_LEN));
6145 }
6146
6147 static int
6148 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6149 {
6150 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6151 /* NOTE: Order is critical */
6152 bge_get_eaddr_fw,
6153 bge_get_eaddr_mem,
6154 bge_get_eaddr_nvram,
6155 bge_get_eaddr_eeprom,
6156 NULL
6157 };
6158 const bge_eaddr_fcn_t *func;
6159
6160 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6161 if ((*func)(sc, eaddr) == 0)
6162 break;
6163 }
6164 return (*func == NULL ? ENXIO : 0);
6165 }
6166