if_bge.c revision 1.284
1 /* $NetBSD: if_bge.c,v 1.284 2015/04/30 15:48:46 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.284 2015/04/30 15:48:46 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 #if 0 /* XXX */ 227 static void bge_free_jumbo_mem(struct bge_softc *); 228 #endif 229 static void *bge_jalloc(struct bge_softc *); 230 static void bge_jfree(struct mbuf *, void *, size_t, void *); 231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 232 bus_dmamap_t); 233 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 234 static int bge_init_rx_ring_std(struct bge_softc *); 235 static void bge_free_rx_ring_std(struct bge_softc *); 236 static int bge_init_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_tx_ring(struct bge_softc *); 239 static int bge_init_tx_ring(struct bge_softc *); 240 241 static int bge_chipinit(struct bge_softc *); 242 static int bge_blockinit(struct bge_softc *); 243 static int bge_phy_addr(struct bge_softc *); 244 static uint32_t bge_readmem_ind(struct bge_softc *, int); 245 static void bge_writemem_ind(struct bge_softc *, int, int); 246 static void bge_writembx(struct bge_softc *, int, int); 247 static void bge_writembx_flush(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(struct ifnet *); 255 256 #define BGE_RESET_SHUTDOWN 0 257 #define BGE_RESET_START 1 258 #define BGE_RESET_SUSPEND 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_wait_for_event_ack(struct bge_softc *); 263 static void bge_stop_fw(struct bge_softc *); 264 static int bge_reset(struct bge_softc *); 265 static void bge_link_upd(struct bge_softc *); 266 static void bge_sysctl_init(struct bge_softc *); 267 static int bge_sysctl_verify(SYSCTLFN_PROTO); 268 269 static void bge_ape_lock_init(struct bge_softc *); 270 static void bge_ape_read_fw_ver(struct bge_softc *); 271 static int bge_ape_lock(struct bge_softc *, int); 272 static void bge_ape_unlock(struct bge_softc *, int); 273 static void bge_ape_send_event(struct bge_softc *, uint32_t); 274 static void bge_ape_driver_state_change(struct bge_softc *, int); 275 276 #ifdef BGE_DEBUG 277 #define DPRINTF(x) if (bgedebug) printf x 278 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 279 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 280 int bgedebug = 0; 281 int bge_tso_debug = 0; 282 void bge_debug_info(struct bge_softc *); 283 #else 284 #define DPRINTF(x) 285 #define DPRINTFN(n,x) 286 #define BGE_TSO_PRINTF(x) 287 #endif 288 289 #ifdef BGE_EVENT_COUNTERS 290 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 291 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 292 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 293 #else 294 #define BGE_EVCNT_INCR(ev) /* nothing */ 295 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 296 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 297 #endif 298 299 static const struct bge_product { 300 pci_vendor_id_t bp_vendor; 301 pci_product_id_t bp_product; 302 const char *bp_name; 303 } bge_products[] = { 304 /* 305 * The BCM5700 documentation seems to indicate that the hardware 306 * still has the Alteon vendor ID burned into it, though it 307 * should always be overridden by the value in the EEPROM. We'll 308 * check for it anyway. 309 */ 310 { PCI_VENDOR_ALTEON, 311 PCI_PRODUCT_ALTEON_BCM5700, 312 "Broadcom BCM5700 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTEON, 315 PCI_PRODUCT_ALTEON_BCM5701, 316 "Broadcom BCM5701 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC1000, 320 "Altima AC1000 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_ALTIMA, 323 PCI_PRODUCT_ALTIMA_AC1001, 324 "Altima AC1001 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_ALTIMA, 327 PCI_PRODUCT_ALTIMA_AC1003, 328 "Altima AC1003 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_ALTIMA, 331 PCI_PRODUCT_ALTIMA_AC9100, 332 "Altima AC9100 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_APPLE, 335 PCI_PRODUCT_APPLE_BCM5701, 336 "APPLE BCM5701 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5700, 340 "Broadcom BCM5700 Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5701, 344 "Broadcom BCM5701 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5702, 348 "Broadcom BCM5702 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5702X, 352 "Broadcom BCM5702X Gigabit Ethernet" }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5703, 355 "Broadcom BCM5703 Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5703X, 359 "Broadcom BCM5703X Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 363 "Broadcom BCM5703 Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5704C, 367 "Broadcom BCM5704C Dual Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5704S, 371 "Broadcom BCM5704S Dual Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705, 375 "Broadcom BCM5705 Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5705F, 379 "Broadcom BCM5705F Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5705K, 383 "Broadcom BCM5705K Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5705M, 387 "Broadcom BCM5705M Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 391 "Broadcom BCM5705M Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5714, 395 "Broadcom BCM5714 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5714S, 399 "Broadcom BCM5714S Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5715, 403 "Broadcom BCM5715 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5715S, 407 "Broadcom BCM5715S Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5717, 411 "Broadcom BCM5717 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5718, 415 "Broadcom BCM5718 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5719, 419 "Broadcom BCM5719 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5720, 423 "Broadcom BCM5720 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5721, 427 "Broadcom BCM5721 Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5722, 431 "Broadcom BCM5722 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5723, 435 "Broadcom BCM5723 Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5724, 439 "Broadcom BCM5724 Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5750, 443 "Broadcom BCM5750 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5750M, 447 "Broadcom BCM5750M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5751, 451 "Broadcom BCM5751 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5751F, 455 "Broadcom BCM5751F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5751M, 459 "Broadcom BCM5751M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5752, 463 "Broadcom BCM5752 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5752M, 467 "Broadcom BCM5752M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5753, 471 "Broadcom BCM5753 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5753F, 475 "Broadcom BCM5753F Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5753M, 479 "Broadcom BCM5753M Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5754, 483 "Broadcom BCM5754 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5754M, 487 "Broadcom BCM5754M Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5755, 491 "Broadcom BCM5755 Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5755M, 495 "Broadcom BCM5755M Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5756, 499 "Broadcom BCM5756 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5761, 503 "Broadcom BCM5761 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5761E, 507 "Broadcom BCM5761E Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5761S, 511 "Broadcom BCM5761S Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5761SE, 515 "Broadcom BCM5761SE Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5764, 519 "Broadcom BCM5764 Gigabit Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5780, 523 "Broadcom BCM5780 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5780S, 527 "Broadcom BCM5780S Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5781, 531 "Broadcom BCM5781 Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5782, 535 "Broadcom BCM5782 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5784M, 539 "BCM5784M NetLink 1000baseT Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5785F, 543 "BCM5785F NetLink 10/100 Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5785G, 547 "BCM5785G NetLink 1000baseT Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5786, 551 "Broadcom BCM5786 Gigabit Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5787, 555 "Broadcom BCM5787 Gigabit Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5787F, 559 "Broadcom BCM5787F 10/100 Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM5787M, 563 "Broadcom BCM5787M Gigabit Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM5788, 567 "Broadcom BCM5788 Gigabit Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM5789, 571 "Broadcom BCM5789 Gigabit Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM5901, 575 "Broadcom BCM5901 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM5901A2, 579 "Broadcom BCM5901A2 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM5903M, 583 "Broadcom BCM5903M Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM5906, 587 "Broadcom BCM5906 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM5906M, 591 "Broadcom BCM5906M Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57760, 595 "Broadcom BCM57760 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57761, 599 "Broadcom BCM57761 Fast Ethernet", 600 }, 601 { PCI_VENDOR_BROADCOM, 602 PCI_PRODUCT_BROADCOM_BCM57762, 603 "Broadcom BCM57762 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_BROADCOM, 606 PCI_PRODUCT_BROADCOM_BCM57765, 607 "Broadcom BCM57765 Fast Ethernet", 608 }, 609 { PCI_VENDOR_BROADCOM, 610 PCI_PRODUCT_BROADCOM_BCM57766, 611 "Broadcom BCM57766 Fast Ethernet", 612 }, 613 { PCI_VENDOR_BROADCOM, 614 PCI_PRODUCT_BROADCOM_BCM57780, 615 "Broadcom BCM57780 Fast Ethernet", 616 }, 617 { PCI_VENDOR_BROADCOM, 618 PCI_PRODUCT_BROADCOM_BCM57781, 619 "Broadcom BCM57781 Fast Ethernet", 620 }, 621 { PCI_VENDOR_BROADCOM, 622 PCI_PRODUCT_BROADCOM_BCM57782, 623 "Broadcom BCM57782 Fast Ethernet", 624 }, 625 { PCI_VENDOR_BROADCOM, 626 PCI_PRODUCT_BROADCOM_BCM57785, 627 "Broadcom BCM57785 Fast Ethernet", 628 }, 629 { PCI_VENDOR_BROADCOM, 630 PCI_PRODUCT_BROADCOM_BCM57786, 631 "Broadcom BCM57786 Fast Ethernet", 632 }, 633 { PCI_VENDOR_BROADCOM, 634 PCI_PRODUCT_BROADCOM_BCM57788, 635 "Broadcom BCM57788 Fast Ethernet", 636 }, 637 { PCI_VENDOR_BROADCOM, 638 PCI_PRODUCT_BROADCOM_BCM57790, 639 "Broadcom BCM57790 Fast Ethernet", 640 }, 641 { PCI_VENDOR_BROADCOM, 642 PCI_PRODUCT_BROADCOM_BCM57791, 643 "Broadcom BCM57791 Fast Ethernet", 644 }, 645 { PCI_VENDOR_BROADCOM, 646 PCI_PRODUCT_BROADCOM_BCM57795, 647 "Broadcom BCM57795 Fast Ethernet", 648 }, 649 { PCI_VENDOR_SCHNEIDERKOCH, 650 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 651 "SysKonnect SK-9Dx1 Gigabit Ethernet", 652 }, 653 { PCI_VENDOR_3COM, 654 PCI_PRODUCT_3COM_3C996, 655 "3Com 3c996 Gigabit Ethernet", 656 }, 657 { PCI_VENDOR_FUJITSU4, 658 PCI_PRODUCT_FUJITSU4_PW008GE4, 659 "Fujitsu PW008GE4 Gigabit Ethernet", 660 }, 661 { PCI_VENDOR_FUJITSU4, 662 PCI_PRODUCT_FUJITSU4_PW008GE5, 663 "Fujitsu PW008GE5 Gigabit Ethernet", 664 }, 665 { PCI_VENDOR_FUJITSU4, 666 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 667 "Fujitsu Primepower 250/450 Gigabit Ethernet", 668 }, 669 { 0, 670 0, 671 NULL }, 672 }; 673 674 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 675 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 676 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 677 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 678 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 679 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 680 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 681 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 682 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 683 684 static const struct bge_revision { 685 uint32_t br_chipid; 686 const char *br_name; 687 } bge_revisions[] = { 688 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 689 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 690 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 691 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 692 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 693 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 694 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 695 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 696 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 697 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 698 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 699 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 700 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 701 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 702 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 703 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 704 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 705 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 706 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 707 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 708 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 709 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 710 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 711 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 712 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 713 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 714 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 715 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 716 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 717 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 718 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 719 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 720 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 721 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 722 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 723 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 724 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 725 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 726 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 727 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 728 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 729 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 730 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 731 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 732 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 733 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 734 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 735 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 736 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 737 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 738 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 739 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 740 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 741 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 742 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 743 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 744 /* 5754 and 5787 share the same ASIC ID */ 745 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 746 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 747 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 748 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 749 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 750 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 751 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 752 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 753 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 754 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 755 756 { 0, NULL } 757 }; 758 759 /* 760 * Some defaults for major revisions, so that newer steppings 761 * that we don't know about have a shot at working. 762 */ 763 static const struct bge_revision bge_majorrevs[] = { 764 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 765 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 766 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 767 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 768 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 769 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 770 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 771 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 772 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 773 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 774 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 775 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 776 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 777 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 778 /* 5754 and 5787 share the same ASIC ID */ 779 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 780 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 781 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 782 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 783 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 784 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 785 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 786 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 787 788 { 0, NULL } 789 }; 790 791 static int bge_allow_asf = 1; 792 793 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 794 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 795 796 static uint32_t 797 bge_readmem_ind(struct bge_softc *sc, int off) 798 { 799 pcireg_t val; 800 801 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 802 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 803 return 0; 804 805 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 806 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 807 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 808 return val; 809 } 810 811 static void 812 bge_writemem_ind(struct bge_softc *sc, int off, int val) 813 { 814 815 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 816 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 817 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 818 } 819 820 /* 821 * PCI Express only 822 */ 823 static void 824 bge_set_max_readrq(struct bge_softc *sc) 825 { 826 pcireg_t val; 827 828 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 829 + PCIE_DCSR); 830 val &= ~PCIE_DCSR_MAX_READ_REQ; 831 switch (sc->bge_expmrq) { 832 case 2048: 833 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 834 break; 835 case 4096: 836 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 837 break; 838 default: 839 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 840 break; 841 } 842 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 843 + PCIE_DCSR, val); 844 } 845 846 #ifdef notdef 847 static uint32_t 848 bge_readreg_ind(struct bge_softc *sc, int off) 849 { 850 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 851 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 852 } 853 #endif 854 855 static void 856 bge_writereg_ind(struct bge_softc *sc, int off, int val) 857 { 858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 859 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 860 } 861 862 static void 863 bge_writemem_direct(struct bge_softc *sc, int off, int val) 864 { 865 CSR_WRITE_4(sc, off, val); 866 } 867 868 static void 869 bge_writembx(struct bge_softc *sc, int off, int val) 870 { 871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 872 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 873 874 CSR_WRITE_4(sc, off, val); 875 } 876 877 static void 878 bge_writembx_flush(struct bge_softc *sc, int off, int val) 879 { 880 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 881 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 882 883 CSR_WRITE_4_FLUSH(sc, off, val); 884 } 885 886 /* 887 * Clear all stale locks and select the lock for this driver instance. 888 */ 889 void 890 bge_ape_lock_init(struct bge_softc *sc) 891 { 892 struct pci_attach_args *pa = &(sc->bge_pa); 893 uint32_t bit, regbase; 894 int i; 895 896 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 897 regbase = BGE_APE_LOCK_GRANT; 898 else 899 regbase = BGE_APE_PER_LOCK_GRANT; 900 901 /* Clear any stale locks. */ 902 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 903 switch (i) { 904 case BGE_APE_LOCK_PHY0: 905 case BGE_APE_LOCK_PHY1: 906 case BGE_APE_LOCK_PHY2: 907 case BGE_APE_LOCK_PHY3: 908 bit = BGE_APE_LOCK_GRANT_DRIVER0; 909 break; 910 default: 911 if (pa->pa_function == 0) 912 bit = BGE_APE_LOCK_GRANT_DRIVER0; 913 else 914 bit = (1 << pa->pa_function); 915 } 916 APE_WRITE_4(sc, regbase + 4 * i, bit); 917 } 918 919 /* Select the PHY lock based on the device's function number. */ 920 switch (pa->pa_function) { 921 case 0: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 923 break; 924 case 1: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 926 break; 927 case 2: 928 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 929 break; 930 case 3: 931 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 932 break; 933 default: 934 printf("%s: PHY lock not supported on function\n", 935 device_xname(sc->bge_dev)); 936 break; 937 } 938 } 939 940 /* 941 * Check for APE firmware, set flags, and print version info. 942 */ 943 void 944 bge_ape_read_fw_ver(struct bge_softc *sc) 945 { 946 const char *fwtype; 947 uint32_t apedata, features; 948 949 /* Check for a valid APE signature in shared memory. */ 950 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 951 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 952 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 953 return; 954 } 955 956 /* Check if APE firmware is running. */ 957 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 958 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 959 printf("%s: APE signature found but FW status not ready! " 960 "0x%08x\n", device_xname(sc->bge_dev), apedata); 961 return; 962 } 963 964 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 965 966 /* Fetch the APE firwmare type and version. */ 967 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 968 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 969 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 970 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 971 fwtype = "NCSI"; 972 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 973 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 974 fwtype = "DASH"; 975 } else 976 fwtype = "UNKN"; 977 978 /* Print the APE firmware version. */ 979 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 980 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 981 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 982 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 983 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 984 } 985 986 int 987 bge_ape_lock(struct bge_softc *sc, int locknum) 988 { 989 struct pci_attach_args *pa = &(sc->bge_pa); 990 uint32_t bit, gnt, req, status; 991 int i, off; 992 993 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 994 return (0); 995 996 /* Lock request/grant registers have different bases. */ 997 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 998 req = BGE_APE_LOCK_REQ; 999 gnt = BGE_APE_LOCK_GRANT; 1000 } else { 1001 req = BGE_APE_PER_LOCK_REQ; 1002 gnt = BGE_APE_PER_LOCK_GRANT; 1003 } 1004 1005 off = 4 * locknum; 1006 1007 switch (locknum) { 1008 case BGE_APE_LOCK_GPIO: 1009 /* Lock required when using GPIO. */ 1010 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1011 return (0); 1012 if (pa->pa_function == 0) 1013 bit = BGE_APE_LOCK_REQ_DRIVER0; 1014 else 1015 bit = (1 << pa->pa_function); 1016 break; 1017 case BGE_APE_LOCK_GRC: 1018 /* Lock required to reset the device. */ 1019 if (pa->pa_function == 0) 1020 bit = BGE_APE_LOCK_REQ_DRIVER0; 1021 else 1022 bit = (1 << pa->pa_function); 1023 break; 1024 case BGE_APE_LOCK_MEM: 1025 /* Lock required when accessing certain APE memory. */ 1026 if (pa->pa_function == 0) 1027 bit = BGE_APE_LOCK_REQ_DRIVER0; 1028 else 1029 bit = (1 << pa->pa_function); 1030 break; 1031 case BGE_APE_LOCK_PHY0: 1032 case BGE_APE_LOCK_PHY1: 1033 case BGE_APE_LOCK_PHY2: 1034 case BGE_APE_LOCK_PHY3: 1035 /* Lock required when accessing PHYs. */ 1036 bit = BGE_APE_LOCK_REQ_DRIVER0; 1037 break; 1038 default: 1039 return (EINVAL); 1040 } 1041 1042 /* Request a lock. */ 1043 APE_WRITE_4_FLUSH(sc, req + off, bit); 1044 1045 /* Wait up to 1 second to acquire lock. */ 1046 for (i = 0; i < 20000; i++) { 1047 status = APE_READ_4(sc, gnt + off); 1048 if (status == bit) 1049 break; 1050 DELAY(50); 1051 } 1052 1053 /* Handle any errors. */ 1054 if (status != bit) { 1055 printf("%s: APE lock %d request failed! " 1056 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1057 device_xname(sc->bge_dev), 1058 locknum, req + off, bit & 0xFFFF, gnt + off, 1059 status & 0xFFFF); 1060 /* Revoke the lock request. */ 1061 APE_WRITE_4(sc, gnt + off, bit); 1062 return (EBUSY); 1063 } 1064 1065 return (0); 1066 } 1067 1068 void 1069 bge_ape_unlock(struct bge_softc *sc, int locknum) 1070 { 1071 struct pci_attach_args *pa = &(sc->bge_pa); 1072 uint32_t bit, gnt; 1073 int off; 1074 1075 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1076 return; 1077 1078 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1079 gnt = BGE_APE_LOCK_GRANT; 1080 else 1081 gnt = BGE_APE_PER_LOCK_GRANT; 1082 1083 off = 4 * locknum; 1084 1085 switch (locknum) { 1086 case BGE_APE_LOCK_GPIO: 1087 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1088 return; 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_GRC: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_MEM: 1101 if (pa->pa_function == 0) 1102 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1103 else 1104 bit = (1 << pa->pa_function); 1105 break; 1106 case BGE_APE_LOCK_PHY0: 1107 case BGE_APE_LOCK_PHY1: 1108 case BGE_APE_LOCK_PHY2: 1109 case BGE_APE_LOCK_PHY3: 1110 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1111 break; 1112 default: 1113 return; 1114 } 1115 1116 /* Write and flush for consecutive bge_ape_lock() */ 1117 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1118 } 1119 1120 /* 1121 * Send an event to the APE firmware. 1122 */ 1123 void 1124 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1125 { 1126 uint32_t apedata; 1127 int i; 1128 1129 /* NCSI does not support APE events. */ 1130 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1131 return; 1132 1133 /* Wait up to 1ms for APE to service previous event. */ 1134 for (i = 10; i > 0; i--) { 1135 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1136 break; 1137 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1138 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1139 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1140 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1141 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1142 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1143 break; 1144 } 1145 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1146 DELAY(100); 1147 } 1148 if (i == 0) { 1149 printf("%s: APE event 0x%08x send timed out\n", 1150 device_xname(sc->bge_dev), event); 1151 } 1152 } 1153 1154 void 1155 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1156 { 1157 uint32_t apedata, event; 1158 1159 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1160 return; 1161 1162 switch (kind) { 1163 case BGE_RESET_START: 1164 /* If this is the first load, clear the load counter. */ 1165 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1166 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1167 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1168 else { 1169 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1170 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1171 } 1172 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1173 BGE_APE_HOST_SEG_SIG_MAGIC); 1174 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1175 BGE_APE_HOST_SEG_LEN_MAGIC); 1176 1177 /* Add some version info if bge(4) supports it. */ 1178 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1179 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1180 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1181 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1182 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1183 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1184 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1185 BGE_APE_HOST_DRVR_STATE_START); 1186 event = BGE_APE_EVENT_STATUS_STATE_START; 1187 break; 1188 case BGE_RESET_SHUTDOWN: 1189 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1190 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1191 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1192 break; 1193 case BGE_RESET_SUSPEND: 1194 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1195 break; 1196 default: 1197 return; 1198 } 1199 1200 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1201 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1202 } 1203 1204 static uint8_t 1205 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1206 { 1207 uint32_t access, byte = 0; 1208 int i; 1209 1210 /* Lock. */ 1211 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1212 for (i = 0; i < 8000; i++) { 1213 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1214 break; 1215 DELAY(20); 1216 } 1217 if (i == 8000) 1218 return 1; 1219 1220 /* Enable access. */ 1221 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1222 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1223 1224 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1225 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1226 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1227 DELAY(10); 1228 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1229 DELAY(10); 1230 break; 1231 } 1232 } 1233 1234 if (i == BGE_TIMEOUT * 10) { 1235 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1236 return 1; 1237 } 1238 1239 /* Get result. */ 1240 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1241 1242 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1243 1244 /* Disable access. */ 1245 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1246 1247 /* Unlock. */ 1248 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1249 1250 return 0; 1251 } 1252 1253 /* 1254 * Read a sequence of bytes from NVRAM. 1255 */ 1256 static int 1257 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1258 { 1259 int error = 0, i; 1260 uint8_t byte = 0; 1261 1262 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1263 return 1; 1264 1265 for (i = 0; i < cnt; i++) { 1266 error = bge_nvram_getbyte(sc, off + i, &byte); 1267 if (error) 1268 break; 1269 *(dest + i) = byte; 1270 } 1271 1272 return (error ? 1 : 0); 1273 } 1274 1275 /* 1276 * Read a byte of data stored in the EEPROM at address 'addr.' The 1277 * BCM570x supports both the traditional bitbang interface and an 1278 * auto access interface for reading the EEPROM. We use the auto 1279 * access method. 1280 */ 1281 static uint8_t 1282 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1283 { 1284 int i; 1285 uint32_t byte = 0; 1286 1287 /* 1288 * Enable use of auto EEPROM access so we can avoid 1289 * having to use the bitbang method. 1290 */ 1291 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1292 1293 /* Reset the EEPROM, load the clock period. */ 1294 CSR_WRITE_4(sc, BGE_EE_ADDR, 1295 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1296 DELAY(20); 1297 1298 /* Issue the read EEPROM command. */ 1299 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1300 1301 /* Wait for completion */ 1302 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1303 DELAY(10); 1304 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1305 break; 1306 } 1307 1308 if (i == BGE_TIMEOUT * 10) { 1309 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1310 return 1; 1311 } 1312 1313 /* Get result. */ 1314 byte = CSR_READ_4(sc, BGE_EE_DATA); 1315 1316 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1317 1318 return 0; 1319 } 1320 1321 /* 1322 * Read a sequence of bytes from the EEPROM. 1323 */ 1324 static int 1325 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1326 { 1327 int error = 0, i; 1328 uint8_t byte = 0; 1329 char *dest = destv; 1330 1331 for (i = 0; i < cnt; i++) { 1332 error = bge_eeprom_getbyte(sc, off + i, &byte); 1333 if (error) 1334 break; 1335 *(dest + i) = byte; 1336 } 1337 1338 return (error ? 1 : 0); 1339 } 1340 1341 static int 1342 bge_miibus_readreg(device_t dev, int phy, int reg) 1343 { 1344 struct bge_softc *sc = device_private(dev); 1345 uint32_t val; 1346 uint32_t autopoll; 1347 int i; 1348 1349 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1350 return 0; 1351 1352 /* Reading with autopolling on may trigger PCI errors */ 1353 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1354 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1355 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1356 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1357 DELAY(80); 1358 } 1359 1360 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1361 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1362 1363 for (i = 0; i < BGE_TIMEOUT; i++) { 1364 delay(10); 1365 val = CSR_READ_4(sc, BGE_MI_COMM); 1366 if (!(val & BGE_MICOMM_BUSY)) { 1367 DELAY(5); 1368 val = CSR_READ_4(sc, BGE_MI_COMM); 1369 break; 1370 } 1371 } 1372 1373 if (i == BGE_TIMEOUT) { 1374 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1375 val = 0; 1376 goto done; 1377 } 1378 1379 done: 1380 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1381 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1382 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1383 DELAY(80); 1384 } 1385 1386 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1387 1388 if (val & BGE_MICOMM_READFAIL) 1389 return 0; 1390 1391 return (val & 0xFFFF); 1392 } 1393 1394 static void 1395 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1396 { 1397 struct bge_softc *sc = device_private(dev); 1398 uint32_t autopoll; 1399 int i; 1400 1401 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1402 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1403 return; 1404 1405 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1406 return; 1407 1408 /* Reading with autopolling on may trigger PCI errors */ 1409 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1410 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1411 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1412 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1413 DELAY(80); 1414 } 1415 1416 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1417 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1418 1419 for (i = 0; i < BGE_TIMEOUT; i++) { 1420 delay(10); 1421 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1422 delay(5); 1423 CSR_READ_4(sc, BGE_MI_COMM); 1424 break; 1425 } 1426 } 1427 1428 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1429 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1430 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1431 delay(80); 1432 } 1433 1434 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1435 1436 if (i == BGE_TIMEOUT) 1437 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1438 } 1439 1440 static void 1441 bge_miibus_statchg(struct ifnet *ifp) 1442 { 1443 struct bge_softc *sc = ifp->if_softc; 1444 struct mii_data *mii = &sc->bge_mii; 1445 uint32_t mac_mode, rx_mode, tx_mode; 1446 1447 /* 1448 * Get flow control negotiation result. 1449 */ 1450 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1451 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1452 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1453 1454 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1455 mii->mii_media_status & IFM_ACTIVE && 1456 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1457 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1458 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1459 (!(mii->mii_media_status & IFM_ACTIVE) || 1460 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1461 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1462 1463 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1464 return; 1465 1466 /* Set the port mode (MII/GMII) to match the link speed. */ 1467 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1468 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1469 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1470 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1471 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1472 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1473 mac_mode |= BGE_PORTMODE_GMII; 1474 else 1475 mac_mode |= BGE_PORTMODE_MII; 1476 1477 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1478 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1479 if ((mii->mii_media_active & IFM_FDX) != 0) { 1480 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1481 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1482 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1483 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1484 } else 1485 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1486 1487 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1488 DELAY(40); 1489 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1490 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1491 } 1492 1493 /* 1494 * Update rx threshold levels to values in a particular slot 1495 * of the interrupt-mitigation table bge_rx_threshes. 1496 */ 1497 static void 1498 bge_set_thresh(struct ifnet *ifp, int lvl) 1499 { 1500 struct bge_softc *sc = ifp->if_softc; 1501 int s; 1502 1503 /* For now, just save the new Rx-intr thresholds and record 1504 * that a threshold update is pending. Updating the hardware 1505 * registers here (even at splhigh()) is observed to 1506 * occasionaly cause glitches where Rx-interrupts are not 1507 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1508 */ 1509 s = splnet(); 1510 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1511 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1512 sc->bge_pending_rxintr_change = 1; 1513 splx(s); 1514 } 1515 1516 1517 /* 1518 * Update Rx thresholds of all bge devices 1519 */ 1520 static void 1521 bge_update_all_threshes(int lvl) 1522 { 1523 struct ifnet *ifp; 1524 const char * const namebuf = "bge"; 1525 int namelen; 1526 1527 if (lvl < 0) 1528 lvl = 0; 1529 else if (lvl >= NBGE_RX_THRESH) 1530 lvl = NBGE_RX_THRESH - 1; 1531 1532 namelen = strlen(namebuf); 1533 /* 1534 * Now search all the interfaces for this name/number 1535 */ 1536 IFNET_FOREACH(ifp) { 1537 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1538 continue; 1539 /* We got a match: update if doing auto-threshold-tuning */ 1540 if (bge_auto_thresh) 1541 bge_set_thresh(ifp, lvl); 1542 } 1543 } 1544 1545 /* 1546 * Handle events that have triggered interrupts. 1547 */ 1548 static void 1549 bge_handle_events(struct bge_softc *sc) 1550 { 1551 1552 return; 1553 } 1554 1555 /* 1556 * Memory management for jumbo frames. 1557 */ 1558 1559 static int 1560 bge_alloc_jumbo_mem(struct bge_softc *sc) 1561 { 1562 char *ptr, *kva; 1563 bus_dma_segment_t seg; 1564 int i, rseg, state, error; 1565 struct bge_jpool_entry *entry; 1566 1567 state = error = 0; 1568 1569 /* Grab a big chunk o' storage. */ 1570 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1571 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1572 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1573 return ENOBUFS; 1574 } 1575 1576 state = 1; 1577 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1578 BUS_DMA_NOWAIT)) { 1579 aprint_error_dev(sc->bge_dev, 1580 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1581 error = ENOBUFS; 1582 goto out; 1583 } 1584 1585 state = 2; 1586 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1587 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1588 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1589 error = ENOBUFS; 1590 goto out; 1591 } 1592 1593 state = 3; 1594 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1595 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1596 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1597 error = ENOBUFS; 1598 goto out; 1599 } 1600 1601 state = 4; 1602 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1603 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1604 1605 SLIST_INIT(&sc->bge_jfree_listhead); 1606 SLIST_INIT(&sc->bge_jinuse_listhead); 1607 1608 /* 1609 * Now divide it up into 9K pieces and save the addresses 1610 * in an array. 1611 */ 1612 ptr = sc->bge_cdata.bge_jumbo_buf; 1613 for (i = 0; i < BGE_JSLOTS; i++) { 1614 sc->bge_cdata.bge_jslots[i] = ptr; 1615 ptr += BGE_JLEN; 1616 entry = malloc(sizeof(struct bge_jpool_entry), 1617 M_DEVBUF, M_NOWAIT); 1618 if (entry == NULL) { 1619 aprint_error_dev(sc->bge_dev, 1620 "no memory for jumbo buffer queue!\n"); 1621 error = ENOBUFS; 1622 goto out; 1623 } 1624 entry->slot = i; 1625 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1626 entry, jpool_entries); 1627 } 1628 out: 1629 if (error != 0) { 1630 switch (state) { 1631 case 4: 1632 bus_dmamap_unload(sc->bge_dmatag, 1633 sc->bge_cdata.bge_rx_jumbo_map); 1634 case 3: 1635 bus_dmamap_destroy(sc->bge_dmatag, 1636 sc->bge_cdata.bge_rx_jumbo_map); 1637 case 2: 1638 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1639 case 1: 1640 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1641 break; 1642 default: 1643 break; 1644 } 1645 } 1646 1647 return error; 1648 } 1649 1650 /* 1651 * Allocate a jumbo buffer. 1652 */ 1653 static void * 1654 bge_jalloc(struct bge_softc *sc) 1655 { 1656 struct bge_jpool_entry *entry; 1657 1658 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1659 1660 if (entry == NULL) { 1661 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1662 return NULL; 1663 } 1664 1665 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1666 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1667 return (sc->bge_cdata.bge_jslots[entry->slot]); 1668 } 1669 1670 /* 1671 * Release a jumbo buffer. 1672 */ 1673 static void 1674 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1675 { 1676 struct bge_jpool_entry *entry; 1677 struct bge_softc *sc; 1678 int i, s; 1679 1680 /* Extract the softc struct pointer. */ 1681 sc = (struct bge_softc *)arg; 1682 1683 if (sc == NULL) 1684 panic("bge_jfree: can't find softc pointer!"); 1685 1686 /* calculate the slot this buffer belongs to */ 1687 1688 i = ((char *)buf 1689 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1690 1691 if ((i < 0) || (i >= BGE_JSLOTS)) 1692 panic("bge_jfree: asked to free buffer that we don't manage!"); 1693 1694 s = splvm(); 1695 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1696 if (entry == NULL) 1697 panic("bge_jfree: buffer not in use!"); 1698 entry->slot = i; 1699 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1700 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1701 1702 if (__predict_true(m != NULL)) 1703 pool_cache_put(mb_cache, m); 1704 splx(s); 1705 } 1706 1707 1708 /* 1709 * Initialize a standard receive ring descriptor. 1710 */ 1711 static int 1712 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1713 bus_dmamap_t dmamap) 1714 { 1715 struct mbuf *m_new = NULL; 1716 struct bge_rx_bd *r; 1717 int error; 1718 1719 if (dmamap == NULL) { 1720 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1721 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1722 if (error != 0) 1723 return error; 1724 } 1725 1726 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1727 1728 if (m == NULL) { 1729 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1730 if (m_new == NULL) 1731 return ENOBUFS; 1732 1733 MCLGET(m_new, M_DONTWAIT); 1734 if (!(m_new->m_flags & M_EXT)) { 1735 m_freem(m_new); 1736 return ENOBUFS; 1737 } 1738 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1739 1740 } else { 1741 m_new = m; 1742 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1743 m_new->m_data = m_new->m_ext.ext_buf; 1744 } 1745 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1746 m_adj(m_new, ETHER_ALIGN); 1747 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1748 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1749 m_freem(m_new); 1750 return ENOBUFS; 1751 } 1752 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1753 BUS_DMASYNC_PREREAD); 1754 1755 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1756 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1757 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1758 r->bge_flags = BGE_RXBDFLAG_END; 1759 r->bge_len = m_new->m_len; 1760 r->bge_idx = i; 1761 1762 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1763 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1764 i * sizeof (struct bge_rx_bd), 1765 sizeof (struct bge_rx_bd), 1766 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1767 1768 return 0; 1769 } 1770 1771 /* 1772 * Initialize a jumbo receive ring descriptor. This allocates 1773 * a jumbo buffer from the pool managed internally by the driver. 1774 */ 1775 static int 1776 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1777 { 1778 struct mbuf *m_new = NULL; 1779 struct bge_rx_bd *r; 1780 void *buf = NULL; 1781 1782 if (m == NULL) { 1783 1784 /* Allocate the mbuf. */ 1785 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1786 if (m_new == NULL) 1787 return ENOBUFS; 1788 1789 /* Allocate the jumbo buffer */ 1790 buf = bge_jalloc(sc); 1791 if (buf == NULL) { 1792 m_freem(m_new); 1793 aprint_error_dev(sc->bge_dev, 1794 "jumbo allocation failed -- packet dropped!\n"); 1795 return ENOBUFS; 1796 } 1797 1798 /* Attach the buffer to the mbuf. */ 1799 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1800 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1801 bge_jfree, sc); 1802 m_new->m_flags |= M_EXT_RW; 1803 } else { 1804 m_new = m; 1805 buf = m_new->m_data = m_new->m_ext.ext_buf; 1806 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1807 } 1808 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1809 m_adj(m_new, ETHER_ALIGN); 1810 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1811 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1812 BUS_DMASYNC_PREREAD); 1813 /* Set up the descriptor. */ 1814 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1815 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1816 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1817 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1818 r->bge_len = m_new->m_len; 1819 r->bge_idx = i; 1820 1821 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1822 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1823 i * sizeof (struct bge_rx_bd), 1824 sizeof (struct bge_rx_bd), 1825 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1826 1827 return 0; 1828 } 1829 1830 /* 1831 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1832 * that's 1MB or memory, which is a lot. For now, we fill only the first 1833 * 256 ring entries and hope that our CPU is fast enough to keep up with 1834 * the NIC. 1835 */ 1836 static int 1837 bge_init_rx_ring_std(struct bge_softc *sc) 1838 { 1839 int i; 1840 1841 if (sc->bge_flags & BGEF_RXRING_VALID) 1842 return 0; 1843 1844 for (i = 0; i < BGE_SSLOTS; i++) { 1845 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1846 return ENOBUFS; 1847 } 1848 1849 sc->bge_std = i - 1; 1850 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1851 1852 sc->bge_flags |= BGEF_RXRING_VALID; 1853 1854 return 0; 1855 } 1856 1857 static void 1858 bge_free_rx_ring_std(struct bge_softc *sc) 1859 { 1860 int i; 1861 1862 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1863 return; 1864 1865 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1866 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1867 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1868 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1869 bus_dmamap_destroy(sc->bge_dmatag, 1870 sc->bge_cdata.bge_rx_std_map[i]); 1871 } 1872 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1873 sizeof(struct bge_rx_bd)); 1874 } 1875 1876 sc->bge_flags &= ~BGEF_RXRING_VALID; 1877 } 1878 1879 static int 1880 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1881 { 1882 int i; 1883 volatile struct bge_rcb *rcb; 1884 1885 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1886 return 0; 1887 1888 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1889 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1890 return ENOBUFS; 1891 } 1892 1893 sc->bge_jumbo = i - 1; 1894 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1895 1896 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1897 rcb->bge_maxlen_flags = 0; 1898 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1899 1900 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1901 1902 return 0; 1903 } 1904 1905 static void 1906 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1907 { 1908 int i; 1909 1910 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1911 return; 1912 1913 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1914 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1915 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1916 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1917 } 1918 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1919 sizeof(struct bge_rx_bd)); 1920 } 1921 1922 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1923 } 1924 1925 static void 1926 bge_free_tx_ring(struct bge_softc *sc) 1927 { 1928 int i; 1929 struct txdmamap_pool_entry *dma; 1930 1931 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1932 return; 1933 1934 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1935 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1936 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1937 sc->bge_cdata.bge_tx_chain[i] = NULL; 1938 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1939 link); 1940 sc->txdma[i] = 0; 1941 } 1942 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1943 sizeof(struct bge_tx_bd)); 1944 } 1945 1946 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1947 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1948 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1949 free(dma, M_DEVBUF); 1950 } 1951 1952 sc->bge_flags &= ~BGEF_TXRING_VALID; 1953 } 1954 1955 static int 1956 bge_init_tx_ring(struct bge_softc *sc) 1957 { 1958 struct ifnet *ifp = &sc->ethercom.ec_if; 1959 int i; 1960 bus_dmamap_t dmamap; 1961 bus_size_t maxsegsz; 1962 struct txdmamap_pool_entry *dma; 1963 1964 if (sc->bge_flags & BGEF_TXRING_VALID) 1965 return 0; 1966 1967 sc->bge_txcnt = 0; 1968 sc->bge_tx_saved_considx = 0; 1969 1970 /* Initialize transmit producer index for host-memory send ring. */ 1971 sc->bge_tx_prodidx = 0; 1972 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1973 /* 5700 b2 errata */ 1974 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1975 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1976 1977 /* NIC-memory send ring not used; initialize to zero. */ 1978 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1979 /* 5700 b2 errata */ 1980 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1981 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1982 1983 /* Limit DMA segment size for some chips */ 1984 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1985 (ifp->if_mtu <= ETHERMTU)) 1986 maxsegsz = 2048; 1987 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1988 maxsegsz = 4096; 1989 else 1990 maxsegsz = ETHER_MAX_LEN_JUMBO; 1991 SLIST_INIT(&sc->txdma_list); 1992 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1993 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1994 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, 1995 &dmamap)) 1996 return ENOBUFS; 1997 if (dmamap == NULL) 1998 panic("dmamap NULL in bge_init_tx_ring"); 1999 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 2000 if (dma == NULL) { 2001 aprint_error_dev(sc->bge_dev, 2002 "can't alloc txdmamap_pool_entry\n"); 2003 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2004 return ENOMEM; 2005 } 2006 dma->dmamap = dmamap; 2007 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2008 } 2009 2010 sc->bge_flags |= BGEF_TXRING_VALID; 2011 2012 return 0; 2013 } 2014 2015 static void 2016 bge_setmulti(struct bge_softc *sc) 2017 { 2018 struct ethercom *ac = &sc->ethercom; 2019 struct ifnet *ifp = &ac->ec_if; 2020 struct ether_multi *enm; 2021 struct ether_multistep step; 2022 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2023 uint32_t h; 2024 int i; 2025 2026 if (ifp->if_flags & IFF_PROMISC) 2027 goto allmulti; 2028 2029 /* Now program new ones. */ 2030 ETHER_FIRST_MULTI(step, ac, enm); 2031 while (enm != NULL) { 2032 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2033 /* 2034 * We must listen to a range of multicast addresses. 2035 * For now, just accept all multicasts, rather than 2036 * trying to set only those filter bits needed to match 2037 * the range. (At this time, the only use of address 2038 * ranges is for IP multicast routing, for which the 2039 * range is big enough to require all bits set.) 2040 */ 2041 goto allmulti; 2042 } 2043 2044 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2045 2046 /* Just want the 7 least-significant bits. */ 2047 h &= 0x7f; 2048 2049 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2050 ETHER_NEXT_MULTI(step, enm); 2051 } 2052 2053 ifp->if_flags &= ~IFF_ALLMULTI; 2054 goto setit; 2055 2056 allmulti: 2057 ifp->if_flags |= IFF_ALLMULTI; 2058 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2059 2060 setit: 2061 for (i = 0; i < 4; i++) 2062 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2063 } 2064 2065 static void 2066 bge_sig_pre_reset(struct bge_softc *sc, int type) 2067 { 2068 2069 /* 2070 * Some chips don't like this so only do this if ASF is enabled 2071 */ 2072 if (sc->bge_asf_mode) 2073 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2074 2075 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2076 switch (type) { 2077 case BGE_RESET_START: 2078 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2079 BGE_FW_DRV_STATE_START); 2080 break; 2081 case BGE_RESET_SHUTDOWN: 2082 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2083 BGE_FW_DRV_STATE_UNLOAD); 2084 break; 2085 case BGE_RESET_SUSPEND: 2086 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2087 BGE_FW_DRV_STATE_SUSPEND); 2088 break; 2089 } 2090 } 2091 2092 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2093 bge_ape_driver_state_change(sc, type); 2094 } 2095 2096 static void 2097 bge_sig_post_reset(struct bge_softc *sc, int type) 2098 { 2099 2100 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2101 switch (type) { 2102 case BGE_RESET_START: 2103 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2104 BGE_FW_DRV_STATE_START_DONE); 2105 /* START DONE */ 2106 break; 2107 case BGE_RESET_SHUTDOWN: 2108 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2109 BGE_FW_DRV_STATE_UNLOAD_DONE); 2110 break; 2111 } 2112 } 2113 2114 if (type == BGE_RESET_SHUTDOWN) 2115 bge_ape_driver_state_change(sc, type); 2116 } 2117 2118 static void 2119 bge_sig_legacy(struct bge_softc *sc, int type) 2120 { 2121 2122 if (sc->bge_asf_mode) { 2123 switch (type) { 2124 case BGE_RESET_START: 2125 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2126 BGE_FW_DRV_STATE_START); 2127 break; 2128 case BGE_RESET_SHUTDOWN: 2129 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2130 BGE_FW_DRV_STATE_UNLOAD); 2131 break; 2132 } 2133 } 2134 } 2135 2136 static void 2137 bge_wait_for_event_ack(struct bge_softc *sc) 2138 { 2139 int i; 2140 2141 /* wait up to 2500usec */ 2142 for (i = 0; i < 250; i++) { 2143 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2144 BGE_RX_CPU_DRV_EVENT)) 2145 break; 2146 DELAY(10); 2147 } 2148 } 2149 2150 static void 2151 bge_stop_fw(struct bge_softc *sc) 2152 { 2153 2154 if (sc->bge_asf_mode) { 2155 bge_wait_for_event_ack(sc); 2156 2157 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2158 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2159 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2160 2161 bge_wait_for_event_ack(sc); 2162 } 2163 } 2164 2165 static int 2166 bge_poll_fw(struct bge_softc *sc) 2167 { 2168 uint32_t val; 2169 int i; 2170 2171 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2172 for (i = 0; i < BGE_TIMEOUT; i++) { 2173 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2174 if (val & BGE_VCPU_STATUS_INIT_DONE) 2175 break; 2176 DELAY(100); 2177 } 2178 if (i >= BGE_TIMEOUT) { 2179 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2180 return -1; 2181 } 2182 } else { 2183 /* 2184 * Poll the value location we just wrote until 2185 * we see the 1's complement of the magic number. 2186 * This indicates that the firmware initialization 2187 * is complete. 2188 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2189 */ 2190 for (i = 0; i < BGE_TIMEOUT; i++) { 2191 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2192 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2193 break; 2194 DELAY(10); 2195 } 2196 2197 if ((i >= BGE_TIMEOUT) 2198 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2199 aprint_error_dev(sc->bge_dev, 2200 "firmware handshake timed out, val = %x\n", val); 2201 return -1; 2202 } 2203 } 2204 2205 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2206 /* tg3 says we have to wait extra time */ 2207 delay(10 * 1000); 2208 } 2209 2210 return 0; 2211 } 2212 2213 int 2214 bge_phy_addr(struct bge_softc *sc) 2215 { 2216 struct pci_attach_args *pa = &(sc->bge_pa); 2217 int phy_addr = 1; 2218 2219 /* 2220 * PHY address mapping for various devices. 2221 * 2222 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2223 * ---------+-------+-------+-------+-------+ 2224 * BCM57XX | 1 | X | X | X | 2225 * BCM5704 | 1 | X | 1 | X | 2226 * BCM5717 | 1 | 8 | 2 | 9 | 2227 * BCM5719 | 1 | 8 | 2 | 9 | 2228 * BCM5720 | 1 | 8 | 2 | 9 | 2229 * 2230 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2231 * ---------+-------+-------+-------+-------+ 2232 * BCM57XX | X | X | X | X | 2233 * BCM5704 | X | X | X | X | 2234 * BCM5717 | X | X | X | X | 2235 * BCM5719 | 3 | 10 | 4 | 11 | 2236 * BCM5720 | X | X | X | X | 2237 * 2238 * Other addresses may respond but they are not 2239 * IEEE compliant PHYs and should be ignored. 2240 */ 2241 switch (BGE_ASICREV(sc->bge_chipid)) { 2242 case BGE_ASICREV_BCM5717: 2243 case BGE_ASICREV_BCM5719: 2244 case BGE_ASICREV_BCM5720: 2245 phy_addr = pa->pa_function; 2246 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2247 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2248 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2249 } else { 2250 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2251 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2252 } 2253 } 2254 2255 return phy_addr; 2256 } 2257 2258 /* 2259 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2260 * self-test results. 2261 */ 2262 static int 2263 bge_chipinit(struct bge_softc *sc) 2264 { 2265 uint32_t dma_rw_ctl, mode_ctl, reg; 2266 int i; 2267 2268 /* Set endianness before we access any non-PCI registers. */ 2269 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2270 BGE_INIT); 2271 2272 /* 2273 * Clear the MAC statistics block in the NIC's 2274 * internal memory. 2275 */ 2276 for (i = BGE_STATS_BLOCK; 2277 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2278 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2279 2280 for (i = BGE_STATUS_BLOCK; 2281 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2282 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2283 2284 /* 5717 workaround from tg3 */ 2285 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2286 /* Save */ 2287 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2288 2289 /* Temporary modify MODE_CTL to control TLP */ 2290 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2291 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2292 2293 /* Control TLP */ 2294 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2295 BGE_TLP_PHYCTL1); 2296 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2297 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2298 2299 /* Restore */ 2300 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2301 } 2302 2303 if (BGE_IS_57765_FAMILY(sc)) { 2304 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2305 /* Save */ 2306 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2307 2308 /* Temporary modify MODE_CTL to control TLP */ 2309 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2310 CSR_WRITE_4(sc, BGE_MODE_CTL, 2311 reg | BGE_MODECTL_PCIE_TLPADDR1); 2312 2313 /* Control TLP */ 2314 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2315 BGE_TLP_PHYCTL5); 2316 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2317 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2318 2319 /* Restore */ 2320 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2321 } 2322 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2323 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2324 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2325 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2326 2327 /* Save */ 2328 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2329 2330 /* Temporary modify MODE_CTL to control TLP */ 2331 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2332 CSR_WRITE_4(sc, BGE_MODE_CTL, 2333 reg | BGE_MODECTL_PCIE_TLPADDR0); 2334 2335 /* Control TLP */ 2336 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2337 BGE_TLP_FTSMAX); 2338 reg &= ~BGE_TLP_FTSMAX_MSK; 2339 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2340 reg | BGE_TLP_FTSMAX_VAL); 2341 2342 /* Restore */ 2343 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2344 } 2345 2346 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2347 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2348 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2349 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2350 } 2351 2352 /* Set up the PCI DMA control register. */ 2353 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2354 if (sc->bge_flags & BGEF_PCIE) { 2355 /* Read watermark not used, 128 bytes for write. */ 2356 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2357 device_xname(sc->bge_dev))); 2358 if (sc->bge_mps >= 256) 2359 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2360 else 2361 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2362 } else if (sc->bge_flags & BGEF_PCIX) { 2363 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2364 device_xname(sc->bge_dev))); 2365 /* PCI-X bus */ 2366 if (BGE_IS_5714_FAMILY(sc)) { 2367 /* 256 bytes for read and write. */ 2368 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2369 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2370 2371 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2372 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2373 else 2374 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2375 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2376 /* 2377 * In the BCM5703, the DMA read watermark should 2378 * be set to less than or equal to the maximum 2379 * memory read byte count of the PCI-X command 2380 * register. 2381 */ 2382 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2383 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2384 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2385 /* 1536 bytes for read, 384 bytes for write. */ 2386 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2387 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2388 } else { 2389 /* 384 bytes for read and write. */ 2390 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2391 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2392 (0x0F); 2393 } 2394 2395 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2396 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2397 uint32_t tmp; 2398 2399 /* Set ONEDMA_ATONCE for hardware workaround. */ 2400 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2401 if (tmp == 6 || tmp == 7) 2402 dma_rw_ctl |= 2403 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2404 2405 /* Set PCI-X DMA write workaround. */ 2406 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2407 } 2408 } else { 2409 /* Conventional PCI bus: 256 bytes for read and write. */ 2410 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2411 device_xname(sc->bge_dev))); 2412 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2413 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2414 2415 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2416 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2417 dma_rw_ctl |= 0x0F; 2418 } 2419 2420 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2421 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2422 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2423 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2424 2425 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2426 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2427 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2428 2429 if (BGE_IS_57765_PLUS(sc)) { 2430 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2431 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2432 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2433 2434 /* 2435 * Enable HW workaround for controllers that misinterpret 2436 * a status tag update and leave interrupts permanently 2437 * disabled. 2438 */ 2439 if (!BGE_IS_57765_FAMILY(sc) && 2440 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2441 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2442 } 2443 2444 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2445 dma_rw_ctl); 2446 2447 /* 2448 * Set up general mode register. 2449 */ 2450 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2451 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2452 /* Retain Host-2-BMC settings written by APE firmware. */ 2453 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2454 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2455 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2456 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2457 } 2458 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2459 BGE_MODECTL_TX_NO_PHDR_CSUM; 2460 2461 /* 2462 * BCM5701 B5 have a bug causing data corruption when using 2463 * 64-bit DMA reads, which can be terminated early and then 2464 * completed later as 32-bit accesses, in combination with 2465 * certain bridges. 2466 */ 2467 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2468 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2469 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2470 2471 /* 2472 * Tell the firmware the driver is running 2473 */ 2474 if (sc->bge_asf_mode & ASF_STACKUP) 2475 mode_ctl |= BGE_MODECTL_STACKUP; 2476 2477 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2478 2479 /* 2480 * Disable memory write invalidate. Apparently it is not supported 2481 * properly by these devices. 2482 */ 2483 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2484 PCI_COMMAND_INVALIDATE_ENABLE); 2485 2486 #ifdef __brokenalpha__ 2487 /* 2488 * Must insure that we do not cross an 8K (bytes) boundary 2489 * for DMA reads. Our highest limit is 1K bytes. This is a 2490 * restriction on some ALPHA platforms with early revision 2491 * 21174 PCI chipsets, such as the AlphaPC 164lx 2492 */ 2493 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2494 #endif 2495 2496 /* Set the timer prescaler (always 66MHz) */ 2497 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2498 2499 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2500 DELAY(40); /* XXX */ 2501 2502 /* Put PHY into ready state */ 2503 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2504 DELAY(40); 2505 } 2506 2507 return 0; 2508 } 2509 2510 static int 2511 bge_blockinit(struct bge_softc *sc) 2512 { 2513 volatile struct bge_rcb *rcb; 2514 bus_size_t rcb_addr; 2515 struct ifnet *ifp = &sc->ethercom.ec_if; 2516 bge_hostaddr taddr; 2517 uint32_t dmactl, mimode, val; 2518 int i, limit; 2519 2520 /* 2521 * Initialize the memory window pointer register so that 2522 * we can access the first 32K of internal NIC RAM. This will 2523 * allow us to set up the TX send ring RCBs and the RX return 2524 * ring RCBs, plus other things which live in NIC memory. 2525 */ 2526 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2527 2528 if (!BGE_IS_5705_PLUS(sc)) { 2529 /* 57XX step 33 */ 2530 /* Configure mbuf memory pool */ 2531 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2532 BGE_BUFFPOOL_1); 2533 2534 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2535 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2536 else 2537 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2538 2539 /* 57XX step 34 */ 2540 /* Configure DMA resource pool */ 2541 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2542 BGE_DMA_DESCRIPTORS); 2543 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2544 } 2545 2546 /* 5718 step 11, 57XX step 35 */ 2547 /* 2548 * Configure mbuf pool watermarks. New broadcom docs strongly 2549 * recommend these. 2550 */ 2551 if (BGE_IS_5717_PLUS(sc)) { 2552 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2553 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2554 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2555 } else if (BGE_IS_5705_PLUS(sc)) { 2556 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2557 2558 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2559 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2560 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2561 } else { 2562 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2563 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2564 } 2565 } else { 2566 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2567 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2568 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2569 } 2570 2571 /* 57XX step 36 */ 2572 /* Configure DMA resource watermarks */ 2573 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2574 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2575 2576 /* 5718 step 13, 57XX step 38 */ 2577 /* Enable buffer manager */ 2578 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2579 /* 2580 * Change the arbitration algorithm of TXMBUF read request to 2581 * round-robin instead of priority based for BCM5719. When 2582 * TXFIFO is almost empty, RDMA will hold its request until 2583 * TXFIFO is not almost empty. 2584 */ 2585 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2586 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2587 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2588 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2589 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2590 val |= BGE_BMANMODE_LOMBUF_ATTN; 2591 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2592 2593 /* 57XX step 39 */ 2594 /* Poll for buffer manager start indication */ 2595 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2596 DELAY(10); 2597 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2598 break; 2599 } 2600 2601 if (i == BGE_TIMEOUT * 2) { 2602 aprint_error_dev(sc->bge_dev, 2603 "buffer manager failed to start\n"); 2604 return ENXIO; 2605 } 2606 2607 /* 57XX step 40 */ 2608 /* Enable flow-through queues */ 2609 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2610 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2611 2612 /* Wait until queue initialization is complete */ 2613 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2614 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2615 break; 2616 DELAY(10); 2617 } 2618 2619 if (i == BGE_TIMEOUT * 2) { 2620 aprint_error_dev(sc->bge_dev, 2621 "flow-through queue init failed\n"); 2622 return ENXIO; 2623 } 2624 2625 /* 2626 * Summary of rings supported by the controller: 2627 * 2628 * Standard Receive Producer Ring 2629 * - This ring is used to feed receive buffers for "standard" 2630 * sized frames (typically 1536 bytes) to the controller. 2631 * 2632 * Jumbo Receive Producer Ring 2633 * - This ring is used to feed receive buffers for jumbo sized 2634 * frames (i.e. anything bigger than the "standard" frames) 2635 * to the controller. 2636 * 2637 * Mini Receive Producer Ring 2638 * - This ring is used to feed receive buffers for "mini" 2639 * sized frames to the controller. 2640 * - This feature required external memory for the controller 2641 * but was never used in a production system. Should always 2642 * be disabled. 2643 * 2644 * Receive Return Ring 2645 * - After the controller has placed an incoming frame into a 2646 * receive buffer that buffer is moved into a receive return 2647 * ring. The driver is then responsible to passing the 2648 * buffer up to the stack. Many versions of the controller 2649 * support multiple RR rings. 2650 * 2651 * Send Ring 2652 * - This ring is used for outgoing frames. Many versions of 2653 * the controller support multiple send rings. 2654 */ 2655 2656 /* 5718 step 15, 57XX step 41 */ 2657 /* Initialize the standard RX ring control block */ 2658 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2659 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2660 /* 5718 step 16 */ 2661 if (BGE_IS_57765_PLUS(sc)) { 2662 /* 2663 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2664 * Bits 15-2 : Maximum RX frame size 2665 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2666 * Bit 0 : Reserved 2667 */ 2668 rcb->bge_maxlen_flags = 2669 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2670 } else if (BGE_IS_5705_PLUS(sc)) { 2671 /* 2672 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2673 * Bits 15-2 : Reserved (should be 0) 2674 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2675 * Bit 0 : Reserved 2676 */ 2677 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2678 } else { 2679 /* 2680 * Ring size is always XXX entries 2681 * Bits 31-16: Maximum RX frame size 2682 * Bits 15-2 : Reserved (should be 0) 2683 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2684 * Bit 0 : Reserved 2685 */ 2686 rcb->bge_maxlen_flags = 2687 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2688 } 2689 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2690 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2691 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2692 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2693 else 2694 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2695 /* Write the standard receive producer ring control block. */ 2696 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2697 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2698 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2699 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2700 2701 /* Reset the standard receive producer ring producer index. */ 2702 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2703 2704 /* 57XX step 42 */ 2705 /* 2706 * Initialize the jumbo RX ring control block 2707 * We set the 'ring disabled' bit in the flags 2708 * field until we're actually ready to start 2709 * using this ring (i.e. once we set the MTU 2710 * high enough to require it). 2711 */ 2712 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2713 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2714 BGE_HOSTADDR(rcb->bge_hostaddr, 2715 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2716 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2717 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2718 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2719 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2720 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2721 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2722 else 2723 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2724 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2725 rcb->bge_hostaddr.bge_addr_hi); 2726 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2727 rcb->bge_hostaddr.bge_addr_lo); 2728 /* Program the jumbo receive producer ring RCB parameters. */ 2729 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2730 rcb->bge_maxlen_flags); 2731 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2732 /* Reset the jumbo receive producer ring producer index. */ 2733 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2734 } 2735 2736 /* 57XX step 43 */ 2737 /* Disable the mini receive producer ring RCB. */ 2738 if (BGE_IS_5700_FAMILY(sc)) { 2739 /* Set up dummy disabled mini ring RCB */ 2740 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2741 rcb->bge_maxlen_flags = 2742 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2743 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2744 rcb->bge_maxlen_flags); 2745 /* Reset the mini receive producer ring producer index. */ 2746 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2747 2748 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2749 offsetof(struct bge_ring_data, bge_info), 2750 sizeof (struct bge_gib), 2751 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2752 } 2753 2754 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2755 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2756 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2757 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2758 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2759 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2760 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2761 } 2762 /* 5718 step 14, 57XX step 44 */ 2763 /* 2764 * The BD ring replenish thresholds control how often the 2765 * hardware fetches new BD's from the producer rings in host 2766 * memory. Setting the value too low on a busy system can 2767 * starve the hardware and recue the throughpout. 2768 * 2769 * Set the BD ring replenish thresholds. The recommended 2770 * values are 1/8th the number of descriptors allocated to 2771 * each ring, but since we try to avoid filling the entire 2772 * ring we set these to the minimal value of 8. This needs to 2773 * be done on several of the supported chip revisions anyway, 2774 * to work around HW bugs. 2775 */ 2776 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2777 if (BGE_IS_JUMBO_CAPABLE(sc)) 2778 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2779 2780 /* 5718 step 18 */ 2781 if (BGE_IS_5717_PLUS(sc)) { 2782 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2783 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2784 } 2785 2786 /* 57XX step 45 */ 2787 /* 2788 * Disable all send rings by setting the 'ring disabled' bit 2789 * in the flags field of all the TX send ring control blocks, 2790 * located in NIC memory. 2791 */ 2792 if (BGE_IS_5700_FAMILY(sc)) { 2793 /* 5700 to 5704 had 16 send rings. */ 2794 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2795 } else if (BGE_IS_5717_PLUS(sc)) { 2796 limit = BGE_TX_RINGS_5717_MAX; 2797 } else if (BGE_IS_57765_FAMILY(sc)) { 2798 limit = BGE_TX_RINGS_57765_MAX; 2799 } else 2800 limit = 1; 2801 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2802 for (i = 0; i < limit; i++) { 2803 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2804 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2805 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2806 rcb_addr += sizeof(struct bge_rcb); 2807 } 2808 2809 /* 57XX step 46 and 47 */ 2810 /* Configure send ring RCB 0 (we use only the first ring) */ 2811 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2812 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2813 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2814 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2815 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2816 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2817 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2818 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2819 else 2820 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2821 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2822 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2823 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2824 2825 /* 57XX step 48 */ 2826 /* 2827 * Disable all receive return rings by setting the 2828 * 'ring diabled' bit in the flags field of all the receive 2829 * return ring control blocks, located in NIC memory. 2830 */ 2831 if (BGE_IS_5717_PLUS(sc)) { 2832 /* Should be 17, use 16 until we get an SRAM map. */ 2833 limit = 16; 2834 } else if (BGE_IS_5700_FAMILY(sc)) 2835 limit = BGE_RX_RINGS_MAX; 2836 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2837 BGE_IS_57765_FAMILY(sc)) 2838 limit = 4; 2839 else 2840 limit = 1; 2841 /* Disable all receive return rings */ 2842 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2843 for (i = 0; i < limit; i++) { 2844 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2845 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2846 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2847 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2848 BGE_RCB_FLAG_RING_DISABLED)); 2849 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2850 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2851 (i * (sizeof(uint64_t))), 0); 2852 rcb_addr += sizeof(struct bge_rcb); 2853 } 2854 2855 /* 57XX step 49 */ 2856 /* 2857 * Set up receive return ring 0. Note that the NIC address 2858 * for RX return rings is 0x0. The return rings live entirely 2859 * within the host, so the nicaddr field in the RCB isn't used. 2860 */ 2861 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2862 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2863 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2864 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2865 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2866 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2867 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2868 2869 /* 5718 step 24, 57XX step 53 */ 2870 /* Set random backoff seed for TX */ 2871 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2872 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2873 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2874 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2875 BGE_TX_BACKOFF_SEED_MASK); 2876 2877 /* 5718 step 26, 57XX step 55 */ 2878 /* Set inter-packet gap */ 2879 val = 0x2620; 2880 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2881 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2882 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2883 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2884 2885 /* 5718 step 27, 57XX step 56 */ 2886 /* 2887 * Specify which ring to use for packets that don't match 2888 * any RX rules. 2889 */ 2890 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2891 2892 /* 5718 step 28, 57XX step 57 */ 2893 /* 2894 * Configure number of RX lists. One interrupt distribution 2895 * list, sixteen active lists, one bad frames class. 2896 */ 2897 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2898 2899 /* 5718 step 29, 57XX step 58 */ 2900 /* Inialize RX list placement stats mask. */ 2901 if (BGE_IS_575X_PLUS(sc)) { 2902 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2903 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2904 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2905 } else 2906 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2907 2908 /* 5718 step 30, 57XX step 59 */ 2909 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2910 2911 /* 5718 step 33, 57XX step 62 */ 2912 /* Disable host coalescing until we get it set up */ 2913 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2914 2915 /* 5718 step 34, 57XX step 63 */ 2916 /* Poll to make sure it's shut down. */ 2917 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2918 DELAY(10); 2919 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2920 break; 2921 } 2922 2923 if (i == BGE_TIMEOUT * 2) { 2924 aprint_error_dev(sc->bge_dev, 2925 "host coalescing engine failed to idle\n"); 2926 return ENXIO; 2927 } 2928 2929 /* 5718 step 35, 36, 37 */ 2930 /* Set up host coalescing defaults */ 2931 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2932 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2933 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2934 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2935 if (!(BGE_IS_5705_PLUS(sc))) { 2936 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2937 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2938 } 2939 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2940 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2941 2942 /* Set up address of statistics block */ 2943 if (BGE_IS_5700_FAMILY(sc)) { 2944 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2945 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2946 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2947 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2948 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2949 } 2950 2951 /* 5718 step 38 */ 2952 /* Set up address of status block */ 2953 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2954 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2955 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2956 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2957 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2958 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2959 2960 /* Set up status block size. */ 2961 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2962 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2963 val = BGE_STATBLKSZ_FULL; 2964 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2965 } else { 2966 val = BGE_STATBLKSZ_32BYTE; 2967 bzero(&sc->bge_rdata->bge_status_block, 32); 2968 } 2969 2970 /* 5718 step 39, 57XX step 73 */ 2971 /* Turn on host coalescing state machine */ 2972 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2973 2974 /* 5718 step 40, 57XX step 74 */ 2975 /* Turn on RX BD completion state machine and enable attentions */ 2976 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2977 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2978 2979 /* 5718 step 41, 57XX step 75 */ 2980 /* Turn on RX list placement state machine */ 2981 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2982 2983 /* 57XX step 76 */ 2984 /* Turn on RX list selector state machine. */ 2985 if (!(BGE_IS_5705_PLUS(sc))) 2986 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2987 2988 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2989 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2990 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2991 BGE_MACMODE_FRMHDR_DMA_ENB; 2992 2993 if (sc->bge_flags & BGEF_FIBER_TBI) 2994 val |= BGE_PORTMODE_TBI; 2995 else if (sc->bge_flags & BGEF_FIBER_MII) 2996 val |= BGE_PORTMODE_GMII; 2997 else 2998 val |= BGE_PORTMODE_MII; 2999 3000 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 3001 /* Allow APE to send/receive frames. */ 3002 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3003 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3004 3005 /* Turn on DMA, clear stats */ 3006 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3007 /* 5718 step 44 */ 3008 DELAY(40); 3009 3010 /* 5718 step 45, 57XX step 79 */ 3011 /* Set misc. local control, enable interrupts on attentions */ 3012 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3013 if (BGE_IS_5717_PLUS(sc)) { 3014 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3015 /* 5718 step 46 */ 3016 DELAY(100); 3017 } 3018 3019 /* 57XX step 81 */ 3020 /* Turn on DMA completion state machine */ 3021 if (!(BGE_IS_5705_PLUS(sc))) 3022 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3023 3024 /* 5718 step 47, 57XX step 82 */ 3025 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3026 3027 /* 5718 step 48 */ 3028 /* Enable host coalescing bug fix. */ 3029 if (BGE_IS_5755_PLUS(sc)) 3030 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3031 3032 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3033 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3034 3035 /* Turn on write DMA state machine */ 3036 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3037 /* 5718 step 49 */ 3038 DELAY(40); 3039 3040 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3041 3042 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3043 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3044 3045 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3046 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3047 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3048 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3049 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3050 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3051 3052 if (sc->bge_flags & BGEF_PCIE) 3053 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3054 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3055 if (ifp->if_mtu <= ETHERMTU) 3056 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3057 } 3058 if (sc->bge_flags & BGEF_TSO) 3059 val |= BGE_RDMAMODE_TSO4_ENABLE; 3060 3061 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3062 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3063 BGE_RDMAMODE_H2BNC_VLAN_DET; 3064 /* 3065 * Allow multiple outstanding read requests from 3066 * non-LSO read DMA engine. 3067 */ 3068 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3069 } 3070 3071 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3072 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3073 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3074 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3075 BGE_IS_57765_PLUS(sc)) { 3076 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3077 /* 3078 * Adjust tx margin to prevent TX data corruption and 3079 * fix internal FIFO overflow. 3080 */ 3081 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3082 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3083 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3084 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3085 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3086 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3087 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3088 } 3089 /* 3090 * Enable fix for read DMA FIFO overruns. 3091 * The fix is to limit the number of RX BDs 3092 * the hardware would fetch at a fime. 3093 */ 3094 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3095 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3096 } 3097 3098 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3099 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3100 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3101 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3102 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3103 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3104 /* 3105 * Allow 4KB burst length reads for non-LSO frames. 3106 * Enable 512B burst length reads for buffer descriptors. 3107 */ 3108 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3109 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3110 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3111 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3112 } 3113 3114 /* Turn on read DMA state machine */ 3115 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3116 /* 5718 step 52 */ 3117 delay(40); 3118 3119 /* 5718 step 56, 57XX step 84 */ 3120 /* Turn on RX data completion state machine */ 3121 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3122 3123 /* Turn on RX data and RX BD initiator state machine */ 3124 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3125 3126 /* 57XX step 85 */ 3127 /* Turn on Mbuf cluster free state machine */ 3128 if (!BGE_IS_5705_PLUS(sc)) 3129 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3130 3131 /* 5718 step 57, 57XX step 86 */ 3132 /* Turn on send data completion state machine */ 3133 val = BGE_SDCMODE_ENABLE; 3134 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3135 val |= BGE_SDCMODE_CDELAY; 3136 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3137 3138 /* 5718 step 58 */ 3139 /* Turn on send BD completion state machine */ 3140 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3141 3142 /* 57XX step 88 */ 3143 /* Turn on RX BD initiator state machine */ 3144 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3145 3146 /* 5718 step 60, 57XX step 90 */ 3147 /* Turn on send data initiator state machine */ 3148 if (sc->bge_flags & BGEF_TSO) { 3149 /* XXX: magic value from Linux driver */ 3150 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3151 BGE_SDIMODE_HW_LSO_PRE_DMA); 3152 } else 3153 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3154 3155 /* 5718 step 61, 57XX step 91 */ 3156 /* Turn on send BD initiator state machine */ 3157 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3158 3159 /* 5718 step 62, 57XX step 92 */ 3160 /* Turn on send BD selector state machine */ 3161 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3162 3163 /* 5718 step 31, 57XX step 60 */ 3164 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3165 /* 5718 step 32, 57XX step 61 */ 3166 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3167 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3168 3169 /* ack/clear link change events */ 3170 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3171 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3172 BGE_MACSTAT_LINK_CHANGED); 3173 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3174 3175 /* 3176 * Enable attention when the link has changed state for 3177 * devices that use auto polling. 3178 */ 3179 if (sc->bge_flags & BGEF_FIBER_TBI) { 3180 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3181 } else { 3182 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3183 mimode = BGE_MIMODE_500KHZ_CONST; 3184 else 3185 mimode = BGE_MIMODE_BASE; 3186 /* 5718 step 68. 5718 step 69 (optionally). */ 3187 if (BGE_IS_5700_FAMILY(sc) || 3188 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3189 mimode |= BGE_MIMODE_AUTOPOLL; 3190 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3191 } 3192 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3193 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3194 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3195 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3196 BGE_EVTENB_MI_INTERRUPT); 3197 } 3198 3199 /* 3200 * Clear any pending link state attention. 3201 * Otherwise some link state change events may be lost until attention 3202 * is cleared by bge_intr() -> bge_link_upd() sequence. 3203 * It's not necessary on newer BCM chips - perhaps enabling link 3204 * state change attentions implies clearing pending attention. 3205 */ 3206 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3207 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3208 BGE_MACSTAT_LINK_CHANGED); 3209 3210 /* Enable link state change attentions. */ 3211 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3212 3213 return 0; 3214 } 3215 3216 static const struct bge_revision * 3217 bge_lookup_rev(uint32_t chipid) 3218 { 3219 const struct bge_revision *br; 3220 3221 for (br = bge_revisions; br->br_name != NULL; br++) { 3222 if (br->br_chipid == chipid) 3223 return br; 3224 } 3225 3226 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3227 if (br->br_chipid == BGE_ASICREV(chipid)) 3228 return br; 3229 } 3230 3231 return NULL; 3232 } 3233 3234 static const struct bge_product * 3235 bge_lookup(const struct pci_attach_args *pa) 3236 { 3237 const struct bge_product *bp; 3238 3239 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3240 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3241 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3242 return bp; 3243 } 3244 3245 return NULL; 3246 } 3247 3248 static uint32_t 3249 bge_chipid(const struct pci_attach_args *pa) 3250 { 3251 uint32_t id; 3252 3253 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3254 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3255 3256 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3257 switch (PCI_PRODUCT(pa->pa_id)) { 3258 case PCI_PRODUCT_BROADCOM_BCM5717: 3259 case PCI_PRODUCT_BROADCOM_BCM5718: 3260 case PCI_PRODUCT_BROADCOM_BCM5719: 3261 case PCI_PRODUCT_BROADCOM_BCM5720: 3262 case PCI_PRODUCT_BROADCOM_BCM5724: /* ??? */ 3263 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3264 BGE_PCI_GEN2_PRODID_ASICREV); 3265 break; 3266 case PCI_PRODUCT_BROADCOM_BCM57761: 3267 case PCI_PRODUCT_BROADCOM_BCM57762: 3268 case PCI_PRODUCT_BROADCOM_BCM57765: 3269 case PCI_PRODUCT_BROADCOM_BCM57766: 3270 case PCI_PRODUCT_BROADCOM_BCM57781: 3271 case PCI_PRODUCT_BROADCOM_BCM57785: 3272 case PCI_PRODUCT_BROADCOM_BCM57791: 3273 case PCI_PRODUCT_BROADCOM_BCM57795: 3274 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3275 BGE_PCI_GEN15_PRODID_ASICREV); 3276 break; 3277 default: 3278 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3279 BGE_PCI_PRODID_ASICREV); 3280 break; 3281 } 3282 } 3283 3284 return id; 3285 } 3286 3287 /* 3288 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3289 * against our list and return its name if we find a match. Note 3290 * that since the Broadcom controller contains VPD support, we 3291 * can get the device name string from the controller itself instead 3292 * of the compiled-in string. This is a little slow, but it guarantees 3293 * we'll always announce the right product name. 3294 */ 3295 static int 3296 bge_probe(device_t parent, cfdata_t match, void *aux) 3297 { 3298 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3299 3300 if (bge_lookup(pa) != NULL) 3301 return 1; 3302 3303 return 0; 3304 } 3305 3306 static void 3307 bge_attach(device_t parent, device_t self, void *aux) 3308 { 3309 struct bge_softc *sc = device_private(self); 3310 struct pci_attach_args *pa = aux; 3311 prop_dictionary_t dict; 3312 const struct bge_product *bp; 3313 const struct bge_revision *br; 3314 pci_chipset_tag_t pc; 3315 pci_intr_handle_t ih; 3316 const char *intrstr = NULL; 3317 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3318 uint32_t command; 3319 struct ifnet *ifp; 3320 uint32_t misccfg, mimode; 3321 void * kva; 3322 u_char eaddr[ETHER_ADDR_LEN]; 3323 pcireg_t memtype, subid, reg; 3324 bus_addr_t memaddr; 3325 uint32_t pm_ctl; 3326 bool no_seeprom; 3327 int capmask; 3328 int mii_flags; 3329 int map_flags; 3330 char intrbuf[PCI_INTRSTR_LEN]; 3331 3332 bp = bge_lookup(pa); 3333 KASSERT(bp != NULL); 3334 3335 sc->sc_pc = pa->pa_pc; 3336 sc->sc_pcitag = pa->pa_tag; 3337 sc->bge_dev = self; 3338 3339 sc->bge_pa = *pa; 3340 pc = sc->sc_pc; 3341 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3342 3343 aprint_naive(": Ethernet controller\n"); 3344 aprint_normal(": %s\n", bp->bp_name); 3345 3346 /* 3347 * Map control/status registers. 3348 */ 3349 DPRINTFN(5, ("Map control/status regs\n")); 3350 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3351 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3352 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3353 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3354 3355 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3356 aprint_error_dev(sc->bge_dev, 3357 "failed to enable memory mapping!\n"); 3358 return; 3359 } 3360 3361 DPRINTFN(5, ("pci_mem_find\n")); 3362 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3363 switch (memtype) { 3364 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3365 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3366 #if 0 3367 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3368 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3369 &memaddr, &sc->bge_bsize) == 0) 3370 break; 3371 #else 3372 /* 3373 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3374 * system get NMI on boot (PR#48451). This problem might not be 3375 * the driver's bug but our PCI common part's bug. Until we 3376 * find a real reason, we ignore the prefetchable bit. 3377 */ 3378 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3379 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3380 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3381 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3382 map_flags, &sc->bge_bhandle) == 0) { 3383 sc->bge_btag = pa->pa_memt; 3384 break; 3385 } 3386 } 3387 #endif 3388 default: 3389 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3390 return; 3391 } 3392 3393 DPRINTFN(5, ("pci_intr_map\n")); 3394 if (pci_intr_map(pa, &ih)) { 3395 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3396 return; 3397 } 3398 3399 DPRINTFN(5, ("pci_intr_string\n")); 3400 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 3401 3402 DPRINTFN(5, ("pci_intr_establish\n")); 3403 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3404 3405 if (sc->bge_intrhand == NULL) { 3406 aprint_error_dev(sc->bge_dev, 3407 "couldn't establish interrupt%s%s\n", 3408 intrstr ? " at " : "", intrstr ? intrstr : ""); 3409 return; 3410 } 3411 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3412 3413 /* Save various chip information. */ 3414 sc->bge_chipid = bge_chipid(pa); 3415 sc->bge_phy_addr = bge_phy_addr(sc); 3416 3417 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3418 &sc->bge_pciecap, NULL) != 0) 3419 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3420 /* PCIe */ 3421 sc->bge_flags |= BGEF_PCIE; 3422 /* Extract supported maximum payload size. */ 3423 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3424 sc->bge_pciecap + PCIE_DCAP); 3425 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3426 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3427 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3428 sc->bge_expmrq = 2048; 3429 else 3430 sc->bge_expmrq = 4096; 3431 bge_set_max_readrq(sc); 3432 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3433 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3434 /* PCI-X */ 3435 sc->bge_flags |= BGEF_PCIX; 3436 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3437 &sc->bge_pcixcap, NULL) == 0) 3438 aprint_error_dev(sc->bge_dev, 3439 "unable to find PCIX capability\n"); 3440 } 3441 3442 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3443 /* 3444 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3445 * can clobber the chip's PCI config-space power control 3446 * registers, leaving the card in D3 powersave state. We do 3447 * not have memory-mapped registers in this state, so force 3448 * device into D0 state before starting initialization. 3449 */ 3450 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3451 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3452 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3453 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3454 DELAY(1000); /* 27 usec is allegedly sufficent */ 3455 } 3456 3457 /* Save chipset family. */ 3458 switch (BGE_ASICREV(sc->bge_chipid)) { 3459 case BGE_ASICREV_BCM5717: 3460 case BGE_ASICREV_BCM5719: 3461 case BGE_ASICREV_BCM5720: 3462 sc->bge_flags |= BGEF_5717_PLUS; 3463 /* FALLTHROUGH */ 3464 case BGE_ASICREV_BCM57765: 3465 case BGE_ASICREV_BCM57766: 3466 if (!BGE_IS_5717_PLUS(sc)) 3467 sc->bge_flags |= BGEF_57765_FAMILY; 3468 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3469 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3470 /* Jumbo frame on BCM5719 A0 does not work. */ 3471 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3472 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3473 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3474 break; 3475 case BGE_ASICREV_BCM5755: 3476 case BGE_ASICREV_BCM5761: 3477 case BGE_ASICREV_BCM5784: 3478 case BGE_ASICREV_BCM5785: 3479 case BGE_ASICREV_BCM5787: 3480 case BGE_ASICREV_BCM57780: 3481 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3482 break; 3483 case BGE_ASICREV_BCM5700: 3484 case BGE_ASICREV_BCM5701: 3485 case BGE_ASICREV_BCM5703: 3486 case BGE_ASICREV_BCM5704: 3487 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3488 break; 3489 case BGE_ASICREV_BCM5714_A0: 3490 case BGE_ASICREV_BCM5780: 3491 case BGE_ASICREV_BCM5714: 3492 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3493 /* FALLTHROUGH */ 3494 case BGE_ASICREV_BCM5750: 3495 case BGE_ASICREV_BCM5752: 3496 case BGE_ASICREV_BCM5906: 3497 sc->bge_flags |= BGEF_575X_PLUS; 3498 /* FALLTHROUGH */ 3499 case BGE_ASICREV_BCM5705: 3500 sc->bge_flags |= BGEF_5705_PLUS; 3501 break; 3502 } 3503 3504 /* Identify chips with APE processor. */ 3505 switch (BGE_ASICREV(sc->bge_chipid)) { 3506 case BGE_ASICREV_BCM5717: 3507 case BGE_ASICREV_BCM5719: 3508 case BGE_ASICREV_BCM5720: 3509 case BGE_ASICREV_BCM5761: 3510 sc->bge_flags |= BGEF_APE; 3511 break; 3512 } 3513 3514 /* 3515 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3516 * not actually a MAC controller bug but an issue with the embedded 3517 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3518 */ 3519 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3520 sc->bge_flags |= BGEF_40BIT_BUG; 3521 3522 /* Chips with APE need BAR2 access for APE registers/memory. */ 3523 if ((sc->bge_flags & BGEF_APE) != 0) { 3524 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3525 #if 0 3526 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3527 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3528 &sc->bge_apesize)) { 3529 aprint_error_dev(sc->bge_dev, 3530 "couldn't map BAR2 memory\n"); 3531 return; 3532 } 3533 #else 3534 /* 3535 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3536 * system get NMI on boot (PR#48451). This problem might not be 3537 * the driver's bug but our PCI common part's bug. Until we 3538 * find a real reason, we ignore the prefetchable bit. 3539 */ 3540 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3541 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3542 aprint_error_dev(sc->bge_dev, 3543 "couldn't map BAR2 memory\n"); 3544 return; 3545 } 3546 3547 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3548 if (bus_space_map(pa->pa_memt, memaddr, 3549 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3550 aprint_error_dev(sc->bge_dev, 3551 "couldn't map BAR2 memory\n"); 3552 return; 3553 } 3554 sc->bge_apetag = pa->pa_memt; 3555 #endif 3556 3557 /* Enable APE register/memory access by host driver. */ 3558 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3559 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3560 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3561 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3562 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3563 3564 bge_ape_lock_init(sc); 3565 bge_ape_read_fw_ver(sc); 3566 } 3567 3568 /* Identify the chips that use an CPMU. */ 3569 if (BGE_IS_5717_PLUS(sc) || 3570 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3571 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3572 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3573 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3574 sc->bge_flags |= BGEF_CPMU_PRESENT; 3575 3576 /* Set MI_MODE */ 3577 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3578 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3579 mimode |= BGE_MIMODE_500KHZ_CONST; 3580 else 3581 mimode |= BGE_MIMODE_BASE; 3582 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3583 3584 /* 3585 * When using the BCM5701 in PCI-X mode, data corruption has 3586 * been observed in the first few bytes of some received packets. 3587 * Aligning the packet buffer in memory eliminates the corruption. 3588 * Unfortunately, this misaligns the packet payloads. On platforms 3589 * which do not support unaligned accesses, we will realign the 3590 * payloads by copying the received packets. 3591 */ 3592 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3593 sc->bge_flags & BGEF_PCIX) 3594 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3595 3596 if (BGE_IS_5700_FAMILY(sc)) 3597 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3598 3599 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3600 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3601 3602 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3603 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3604 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3605 sc->bge_flags |= BGEF_IS_5788; 3606 3607 /* 3608 * Some controllers seem to require a special firmware to use 3609 * TSO. But the firmware is not available to FreeBSD and Linux 3610 * claims that the TSO performed by the firmware is slower than 3611 * hardware based TSO. Moreover the firmware based TSO has one 3612 * known bug which can't handle TSO if ethernet header + IP/TCP 3613 * header is greater than 80 bytes. The workaround for the TSO 3614 * bug exist but it seems it's too expensive than not using 3615 * TSO at all. Some hardwares also have the TSO bug so limit 3616 * the TSO to the controllers that are not affected TSO issues 3617 * (e.g. 5755 or higher). 3618 */ 3619 if (BGE_IS_5755_PLUS(sc)) { 3620 /* 3621 * BCM5754 and BCM5787 shares the same ASIC id so 3622 * explicit device id check is required. 3623 */ 3624 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3625 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3626 sc->bge_flags |= BGEF_TSO; 3627 } 3628 3629 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3630 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3631 (misccfg == 0x4000 || misccfg == 0x8000)) || 3632 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3633 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3634 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3635 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3636 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3637 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3638 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3639 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3640 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3641 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3642 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3643 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3644 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3645 /* These chips are 10/100 only. */ 3646 capmask &= ~BMSR_EXTSTAT; 3647 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3648 } 3649 3650 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3651 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3652 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3653 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3654 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3655 3656 /* Set various PHY bug flags. */ 3657 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3658 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3659 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3660 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3661 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3662 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3663 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3664 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3665 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3666 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3667 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3668 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3669 if (BGE_IS_5705_PLUS(sc) && 3670 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3671 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3672 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3673 !BGE_IS_57765_PLUS(sc)) { 3674 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3675 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3676 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3677 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3678 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3679 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3680 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3681 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3682 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3683 } else 3684 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3685 } 3686 3687 /* 3688 * SEEPROM check. 3689 * First check if firmware knows we do not have SEEPROM. 3690 */ 3691 if (prop_dictionary_get_bool(device_properties(self), 3692 "without-seeprom", &no_seeprom) && no_seeprom) 3693 sc->bge_flags |= BGEF_NO_EEPROM; 3694 3695 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3696 sc->bge_flags |= BGEF_NO_EEPROM; 3697 3698 /* Now check the 'ROM failed' bit on the RX CPU */ 3699 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3700 sc->bge_flags |= BGEF_NO_EEPROM; 3701 3702 sc->bge_asf_mode = 0; 3703 /* No ASF if APE present. */ 3704 if ((sc->bge_flags & BGEF_APE) == 0) { 3705 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3706 BGE_SRAM_DATA_SIG_MAGIC)) { 3707 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3708 BGE_HWCFG_ASF) { 3709 sc->bge_asf_mode |= ASF_ENABLE; 3710 sc->bge_asf_mode |= ASF_STACKUP; 3711 if (BGE_IS_575X_PLUS(sc)) 3712 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3713 } 3714 } 3715 } 3716 3717 /* 3718 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3719 * lock in bge_reset(). 3720 */ 3721 CSR_WRITE_4(sc, BGE_EE_ADDR, 3722 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3723 delay(1000); 3724 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3725 3726 bge_stop_fw(sc); 3727 bge_sig_pre_reset(sc, BGE_RESET_START); 3728 if (bge_reset(sc)) 3729 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3730 3731 /* 3732 * Read the hardware config word in the first 32k of NIC internal 3733 * memory, or fall back to the config word in the EEPROM. 3734 * Note: on some BCM5700 cards, this value appears to be unset. 3735 */ 3736 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3737 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3738 BGE_SRAM_DATA_SIG_MAGIC) { 3739 uint32_t tmp; 3740 3741 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3742 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3743 BGE_SRAM_DATA_VER_SHIFT; 3744 if ((0 < tmp) && (tmp < 0x100)) 3745 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3746 if (sc->bge_flags & BGEF_PCIE) 3747 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3748 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3749 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3750 if (BGE_IS_5717_PLUS(sc)) 3751 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3752 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3753 bge_read_eeprom(sc, (void *)&hwcfg, 3754 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3755 hwcfg = be32toh(hwcfg); 3756 } 3757 aprint_normal_dev(sc->bge_dev, 3758 "HW config %08x, %08x, %08x, %08x %08x\n", 3759 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3760 3761 bge_sig_legacy(sc, BGE_RESET_START); 3762 bge_sig_post_reset(sc, BGE_RESET_START); 3763 3764 if (bge_chipinit(sc)) { 3765 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3766 bge_release_resources(sc); 3767 return; 3768 } 3769 3770 /* 3771 * Get station address from the EEPROM. 3772 */ 3773 if (bge_get_eaddr(sc, eaddr)) { 3774 aprint_error_dev(sc->bge_dev, 3775 "failed to read station address\n"); 3776 bge_release_resources(sc); 3777 return; 3778 } 3779 3780 br = bge_lookup_rev(sc->bge_chipid); 3781 3782 if (br == NULL) { 3783 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3784 sc->bge_chipid); 3785 } else { 3786 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3787 br->br_name, sc->bge_chipid); 3788 } 3789 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3790 3791 /* Allocate the general information block and ring buffers. */ 3792 if (pci_dma64_available(pa)) 3793 sc->bge_dmatag = pa->pa_dmat64; 3794 else 3795 sc->bge_dmatag = pa->pa_dmat; 3796 3797 /* 40bit DMA workaround */ 3798 if (sizeof(bus_addr_t) > 4) { 3799 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3800 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3801 3802 if (bus_dmatag_subregion(olddmatag, 0, 3803 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3804 BUS_DMA_NOWAIT) != 0) { 3805 aprint_error_dev(self, 3806 "WARNING: failed to restrict dma range," 3807 " falling back to parent bus dma range\n"); 3808 sc->bge_dmatag = olddmatag; 3809 } 3810 } 3811 } 3812 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3813 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3814 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3815 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3816 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3817 return; 3818 } 3819 DPRINTFN(5, ("bus_dmamem_map\n")); 3820 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3821 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3822 BUS_DMA_NOWAIT)) { 3823 aprint_error_dev(sc->bge_dev, 3824 "can't map DMA buffers (%zu bytes)\n", 3825 sizeof(struct bge_ring_data)); 3826 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3827 sc->bge_ring_rseg); 3828 return; 3829 } 3830 DPRINTFN(5, ("bus_dmamem_create\n")); 3831 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3832 sizeof(struct bge_ring_data), 0, 3833 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3834 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3835 bus_dmamem_unmap(sc->bge_dmatag, kva, 3836 sizeof(struct bge_ring_data)); 3837 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3838 sc->bge_ring_rseg); 3839 return; 3840 } 3841 DPRINTFN(5, ("bus_dmamem_load\n")); 3842 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3843 sizeof(struct bge_ring_data), NULL, 3844 BUS_DMA_NOWAIT)) { 3845 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3846 bus_dmamem_unmap(sc->bge_dmatag, kva, 3847 sizeof(struct bge_ring_data)); 3848 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3849 sc->bge_ring_rseg); 3850 return; 3851 } 3852 3853 DPRINTFN(5, ("bzero\n")); 3854 sc->bge_rdata = (struct bge_ring_data *)kva; 3855 3856 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3857 3858 /* Try to allocate memory for jumbo buffers. */ 3859 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3860 if (bge_alloc_jumbo_mem(sc)) { 3861 aprint_error_dev(sc->bge_dev, 3862 "jumbo buffer allocation failed\n"); 3863 } else 3864 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3865 } 3866 3867 /* Set default tuneable values. */ 3868 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3869 sc->bge_rx_coal_ticks = 150; 3870 sc->bge_rx_max_coal_bds = 64; 3871 sc->bge_tx_coal_ticks = 300; 3872 sc->bge_tx_max_coal_bds = 400; 3873 if (BGE_IS_5705_PLUS(sc)) { 3874 sc->bge_tx_coal_ticks = (12 * 5); 3875 sc->bge_tx_max_coal_bds = (12 * 5); 3876 aprint_verbose_dev(sc->bge_dev, 3877 "setting short Tx thresholds\n"); 3878 } 3879 3880 if (BGE_IS_5717_PLUS(sc)) 3881 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3882 else if (BGE_IS_5705_PLUS(sc)) 3883 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3884 else 3885 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3886 3887 /* Set up ifnet structure */ 3888 ifp = &sc->ethercom.ec_if; 3889 ifp->if_softc = sc; 3890 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3891 ifp->if_ioctl = bge_ioctl; 3892 ifp->if_stop = bge_stop; 3893 ifp->if_start = bge_start; 3894 ifp->if_init = bge_init; 3895 ifp->if_watchdog = bge_watchdog; 3896 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3897 IFQ_SET_READY(&ifp->if_snd); 3898 DPRINTFN(5, ("strcpy if_xname\n")); 3899 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3900 3901 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3902 sc->ethercom.ec_if.if_capabilities |= 3903 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3904 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3905 sc->ethercom.ec_if.if_capabilities |= 3906 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3907 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3908 #endif 3909 sc->ethercom.ec_capabilities |= 3910 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3911 3912 if (sc->bge_flags & BGEF_TSO) 3913 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3914 3915 /* 3916 * Do MII setup. 3917 */ 3918 DPRINTFN(5, ("mii setup\n")); 3919 sc->bge_mii.mii_ifp = ifp; 3920 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3921 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3922 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3923 3924 /* 3925 * Figure out what sort of media we have by checking the hardware 3926 * config word. Note: on some BCM5700 cards, this value appears to be 3927 * unset. If that's the case, we have to rely on identifying the NIC 3928 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3929 * The SysKonnect SK-9D41 is a 1000baseSX card. 3930 */ 3931 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3932 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3933 if (BGE_IS_5705_PLUS(sc)) { 3934 sc->bge_flags |= BGEF_FIBER_MII; 3935 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3936 } else 3937 sc->bge_flags |= BGEF_FIBER_TBI; 3938 } 3939 3940 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3941 if (BGE_IS_JUMBO_CAPABLE(sc)) 3942 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3943 3944 /* set phyflags and chipid before mii_attach() */ 3945 dict = device_properties(self); 3946 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3947 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3948 3949 if (sc->bge_flags & BGEF_FIBER_TBI) { 3950 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3951 bge_ifmedia_sts); 3952 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3953 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3954 0, NULL); 3955 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3956 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3957 /* Pretend the user requested this setting */ 3958 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3959 } else { 3960 /* 3961 * Do transceiver setup and tell the firmware the 3962 * driver is down so we can try to get access the 3963 * probe if ASF is running. Retry a couple of times 3964 * if we get a conflict with the ASF firmware accessing 3965 * the PHY. 3966 */ 3967 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3968 bge_asf_driver_up(sc); 3969 3970 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3971 bge_ifmedia_sts); 3972 mii_flags = MIIF_DOPAUSE; 3973 if (sc->bge_flags & BGEF_FIBER_MII) 3974 mii_flags |= MIIF_HAVEFIBER; 3975 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 3976 MII_OFFSET_ANY, mii_flags); 3977 3978 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3979 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3980 ifmedia_add(&sc->bge_mii.mii_media, 3981 IFM_ETHER|IFM_MANUAL, 0, NULL); 3982 ifmedia_set(&sc->bge_mii.mii_media, 3983 IFM_ETHER|IFM_MANUAL); 3984 } else 3985 ifmedia_set(&sc->bge_mii.mii_media, 3986 IFM_ETHER|IFM_AUTO); 3987 3988 /* 3989 * Now tell the firmware we are going up after probing the PHY 3990 */ 3991 if (sc->bge_asf_mode & ASF_STACKUP) 3992 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3993 } 3994 3995 /* 3996 * Call MI attach routine. 3997 */ 3998 DPRINTFN(5, ("if_attach\n")); 3999 if_attach(ifp); 4000 DPRINTFN(5, ("ether_ifattach\n")); 4001 ether_ifattach(ifp, eaddr); 4002 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4003 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4004 RND_TYPE_NET, RND_FLAG_DEFAULT); 4005 #ifdef BGE_EVENT_COUNTERS 4006 /* 4007 * Attach event counters. 4008 */ 4009 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4010 NULL, device_xname(sc->bge_dev), "intr"); 4011 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4012 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4013 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4014 NULL, device_xname(sc->bge_dev), "tx_xon"); 4015 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4016 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4017 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4018 NULL, device_xname(sc->bge_dev), "rx_xon"); 4019 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4020 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4021 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4022 NULL, device_xname(sc->bge_dev), "xoffentered"); 4023 #endif /* BGE_EVENT_COUNTERS */ 4024 DPRINTFN(5, ("callout_init\n")); 4025 callout_init(&sc->bge_timeout, 0); 4026 4027 if (pmf_device_register(self, NULL, NULL)) 4028 pmf_class_network_register(self, ifp); 4029 else 4030 aprint_error_dev(self, "couldn't establish power handler\n"); 4031 4032 bge_sysctl_init(sc); 4033 4034 #ifdef BGE_DEBUG 4035 bge_debug_info(sc); 4036 #endif 4037 } 4038 4039 /* 4040 * Stop all chip I/O so that the kernel's probe routines don't 4041 * get confused by errant DMAs when rebooting. 4042 */ 4043 static int 4044 bge_detach(device_t self, int flags __unused) 4045 { 4046 struct bge_softc *sc = device_private(self); 4047 struct ifnet *ifp = &sc->ethercom.ec_if; 4048 int s; 4049 4050 s = splnet(); 4051 /* Stop the interface. Callouts are stopped in it. */ 4052 bge_stop(ifp, 1); 4053 splx(s); 4054 4055 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4056 4057 /* Delete all remaining media. */ 4058 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4059 4060 ether_ifdetach(ifp); 4061 if_detach(ifp); 4062 4063 bge_release_resources(sc); 4064 4065 return 0; 4066 } 4067 4068 static void 4069 bge_release_resources(struct bge_softc *sc) 4070 { 4071 4072 /* Disestablish the interrupt handler */ 4073 if (sc->bge_intrhand != NULL) { 4074 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4075 sc->bge_intrhand = NULL; 4076 } 4077 4078 if (sc->bge_dmatag != NULL) { 4079 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4080 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4081 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4082 sizeof(struct bge_ring_data)); 4083 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 4084 } 4085 4086 /* Unmap the device registers */ 4087 if (sc->bge_bsize != 0) { 4088 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4089 sc->bge_bsize = 0; 4090 } 4091 4092 /* Unmap the APE registers */ 4093 if (sc->bge_apesize != 0) { 4094 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4095 sc->bge_apesize); 4096 sc->bge_apesize = 0; 4097 } 4098 } 4099 4100 static int 4101 bge_reset(struct bge_softc *sc) 4102 { 4103 uint32_t cachesize, command; 4104 uint32_t reset, mac_mode, mac_mode_mask; 4105 pcireg_t devctl, reg; 4106 int i, val; 4107 void (*write_op)(struct bge_softc *, int, int); 4108 4109 /* Make mask for BGE_MAC_MODE register. */ 4110 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4111 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4112 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4113 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4114 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4115 4116 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4117 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4118 if (sc->bge_flags & BGEF_PCIE) 4119 write_op = bge_writemem_direct; 4120 else 4121 write_op = bge_writemem_ind; 4122 } else 4123 write_op = bge_writereg_ind; 4124 4125 /* 57XX step 4 */ 4126 /* Acquire the NVM lock */ 4127 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4128 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4129 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4130 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4131 for (i = 0; i < 8000; i++) { 4132 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4133 BGE_NVRAMSWARB_GNT1) 4134 break; 4135 DELAY(20); 4136 } 4137 if (i == 8000) { 4138 printf("%s: NVRAM lock timedout!\n", 4139 device_xname(sc->bge_dev)); 4140 } 4141 } 4142 4143 /* Take APE lock when performing reset. */ 4144 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4145 4146 /* 57XX step 3 */ 4147 /* Save some important PCI state. */ 4148 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4149 /* 5718 reset step 3 */ 4150 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4151 4152 /* 5718 reset step 5, 57XX step 5b-5d */ 4153 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4154 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4155 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4156 4157 /* XXX ???: Disable fastboot on controllers that support it. */ 4158 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4159 BGE_IS_5755_PLUS(sc)) 4160 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4161 4162 /* 5718 reset step 2, 57XX step 6 */ 4163 /* 4164 * Write the magic number to SRAM at offset 0xB50. 4165 * When firmware finishes its initialization it will 4166 * write ~BGE_MAGIC_NUMBER to the same location. 4167 */ 4168 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4169 4170 /* 5718 reset step 6, 57XX step 7 */ 4171 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4172 /* 4173 * XXX: from FreeBSD/Linux; no documentation 4174 */ 4175 if (sc->bge_flags & BGEF_PCIE) { 4176 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4177 !BGE_IS_57765_PLUS(sc) && 4178 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4179 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4180 /* PCI Express 1.0 system */ 4181 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4182 BGE_PHY_PCIE_SCRAM_MODE); 4183 } 4184 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4185 /* 4186 * Prevent PCI Express link training 4187 * during global reset. 4188 */ 4189 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4190 reset |= (1 << 29); 4191 } 4192 } 4193 4194 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4195 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4196 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4197 i | BGE_VCPU_STATUS_DRV_RESET); 4198 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4199 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4200 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4201 } 4202 4203 /* 4204 * Set GPHY Power Down Override to leave GPHY 4205 * powered up in D0 uninitialized. 4206 */ 4207 if (BGE_IS_5705_PLUS(sc) && 4208 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4209 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4210 4211 /* Issue global reset */ 4212 write_op(sc, BGE_MISC_CFG, reset); 4213 4214 /* 5718 reset step 7, 57XX step 8 */ 4215 if (sc->bge_flags & BGEF_PCIE) 4216 delay(100*1000); /* too big */ 4217 else 4218 delay(1000); 4219 4220 if (sc->bge_flags & BGEF_PCIE) { 4221 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4222 DELAY(500000); 4223 /* XXX: Magic Numbers */ 4224 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4225 BGE_PCI_UNKNOWN0); 4226 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4227 BGE_PCI_UNKNOWN0, 4228 reg | (1 << 15)); 4229 } 4230 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4231 sc->bge_pciecap + PCIE_DCSR); 4232 /* Clear enable no snoop and disable relaxed ordering. */ 4233 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4234 PCIE_DCSR_ENA_NO_SNOOP); 4235 4236 /* Set PCIE max payload size to 128 for older PCIe devices */ 4237 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4238 devctl &= ~(0x00e0); 4239 /* Clear device status register. Write 1b to clear */ 4240 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4241 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4242 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4243 sc->bge_pciecap + PCIE_DCSR, devctl); 4244 bge_set_max_readrq(sc); 4245 } 4246 4247 /* From Linux: dummy read to flush PCI posted writes */ 4248 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4249 4250 /* 4251 * Reset some of the PCI state that got zapped by reset 4252 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4253 * set, too. 4254 */ 4255 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4256 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4257 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4258 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4259 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4260 (sc->bge_flags & BGEF_PCIX) != 0) 4261 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4262 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4263 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4264 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4265 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4266 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4267 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4268 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4269 4270 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4271 if (sc->bge_flags & BGEF_PCIX) { 4272 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4273 + PCIX_CMD); 4274 /* Set max memory read byte count to 2K */ 4275 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4276 reg &= ~PCIX_CMD_BYTECNT_MASK; 4277 reg |= PCIX_CMD_BCNT_2048; 4278 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4279 /* 4280 * For 5704, set max outstanding split transaction 4281 * field to 0 (0 means it supports 1 request) 4282 */ 4283 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4284 | PCIX_CMD_BYTECNT_MASK); 4285 reg |= PCIX_CMD_BCNT_2048; 4286 } 4287 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4288 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4289 } 4290 4291 /* 5718 reset step 10, 57XX step 12 */ 4292 /* Enable memory arbiter. */ 4293 if (BGE_IS_5714_FAMILY(sc)) { 4294 val = CSR_READ_4(sc, BGE_MARB_MODE); 4295 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4296 } else 4297 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4298 4299 /* XXX 5721, 5751 and 5752 */ 4300 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4301 /* Step 19: */ 4302 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4303 /* Step 20: */ 4304 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4305 } 4306 4307 /* 5718 reset step 12, 57XX step 15 and 16 */ 4308 /* Fix up byte swapping */ 4309 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4310 4311 /* 5718 reset step 13, 57XX step 17 */ 4312 /* Poll until the firmware initialization is complete */ 4313 bge_poll_fw(sc); 4314 4315 /* 57XX step 21 */ 4316 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4317 pcireg_t msidata; 4318 4319 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4320 BGE_PCI_MSI_DATA); 4321 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4322 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4323 msidata); 4324 } 4325 4326 /* 57XX step 18 */ 4327 /* Write mac mode. */ 4328 val = CSR_READ_4(sc, BGE_MAC_MODE); 4329 /* Restore mac_mode_mask's bits using mac_mode */ 4330 val = (val & ~mac_mode_mask) | mac_mode; 4331 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4332 DELAY(40); 4333 4334 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4335 4336 /* 4337 * The 5704 in TBI mode apparently needs some special 4338 * adjustment to insure the SERDES drive level is set 4339 * to 1.2V. 4340 */ 4341 if (sc->bge_flags & BGEF_FIBER_TBI && 4342 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4343 uint32_t serdescfg; 4344 4345 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4346 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4347 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4348 } 4349 4350 if (sc->bge_flags & BGEF_PCIE && 4351 !BGE_IS_57765_PLUS(sc) && 4352 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4353 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4354 uint32_t v; 4355 4356 /* Enable PCI Express bug fix */ 4357 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4358 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4359 v | BGE_TLP_DATA_FIFO_PROTECT); 4360 } 4361 4362 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4363 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4364 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4365 4366 return 0; 4367 } 4368 4369 /* 4370 * Frame reception handling. This is called if there's a frame 4371 * on the receive return list. 4372 * 4373 * Note: we have to be able to handle two possibilities here: 4374 * 1) the frame is from the jumbo receive ring 4375 * 2) the frame is from the standard receive ring 4376 */ 4377 4378 static void 4379 bge_rxeof(struct bge_softc *sc) 4380 { 4381 struct ifnet *ifp; 4382 uint16_t rx_prod, rx_cons; 4383 int stdcnt = 0, jumbocnt = 0; 4384 bus_dmamap_t dmamap; 4385 bus_addr_t offset, toff; 4386 bus_size_t tlen; 4387 int tosync; 4388 4389 rx_cons = sc->bge_rx_saved_considx; 4390 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4391 4392 /* Nothing to do */ 4393 if (rx_cons == rx_prod) 4394 return; 4395 4396 ifp = &sc->ethercom.ec_if; 4397 4398 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4399 offsetof(struct bge_ring_data, bge_status_block), 4400 sizeof (struct bge_status_block), 4401 BUS_DMASYNC_POSTREAD); 4402 4403 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4404 tosync = rx_prod - rx_cons; 4405 4406 if (tosync != 0) 4407 rnd_add_uint32(&sc->rnd_source, tosync); 4408 4409 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4410 4411 if (tosync < 0) { 4412 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4413 sizeof (struct bge_rx_bd); 4414 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4415 toff, tlen, BUS_DMASYNC_POSTREAD); 4416 tosync = -tosync; 4417 } 4418 4419 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4420 offset, tosync * sizeof (struct bge_rx_bd), 4421 BUS_DMASYNC_POSTREAD); 4422 4423 while (rx_cons != rx_prod) { 4424 struct bge_rx_bd *cur_rx; 4425 uint32_t rxidx; 4426 struct mbuf *m = NULL; 4427 4428 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4429 4430 rxidx = cur_rx->bge_idx; 4431 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4432 4433 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4434 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4435 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4436 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4437 jumbocnt++; 4438 bus_dmamap_sync(sc->bge_dmatag, 4439 sc->bge_cdata.bge_rx_jumbo_map, 4440 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4441 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4442 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4443 ifp->if_ierrors++; 4444 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4445 continue; 4446 } 4447 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4448 NULL)== ENOBUFS) { 4449 ifp->if_ierrors++; 4450 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4451 continue; 4452 } 4453 } else { 4454 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4455 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4456 4457 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4458 stdcnt++; 4459 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4460 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4461 if (dmamap == NULL) { 4462 ifp->if_ierrors++; 4463 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4464 continue; 4465 } 4466 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4467 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4468 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4469 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4470 ifp->if_ierrors++; 4471 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4472 continue; 4473 } 4474 if (bge_newbuf_std(sc, sc->bge_std, 4475 NULL, dmamap) == ENOBUFS) { 4476 ifp->if_ierrors++; 4477 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4478 continue; 4479 } 4480 } 4481 4482 ifp->if_ipackets++; 4483 #ifndef __NO_STRICT_ALIGNMENT 4484 /* 4485 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4486 * the Rx buffer has the layer-2 header unaligned. 4487 * If our CPU requires alignment, re-align by copying. 4488 */ 4489 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4490 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4491 cur_rx->bge_len); 4492 m->m_data += ETHER_ALIGN; 4493 } 4494 #endif 4495 4496 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4497 m->m_pkthdr.rcvif = ifp; 4498 4499 /* 4500 * Handle BPF listeners. Let the BPF user see the packet. 4501 */ 4502 bpf_mtap(ifp, m); 4503 4504 bge_rxcsum(sc, cur_rx, m); 4505 4506 /* 4507 * If we received a packet with a vlan tag, pass it 4508 * to vlan_input() instead of ether_input(). 4509 */ 4510 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4511 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4512 } 4513 4514 (*ifp->if_input)(ifp, m); 4515 } 4516 4517 sc->bge_rx_saved_considx = rx_cons; 4518 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4519 if (stdcnt) 4520 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4521 if (jumbocnt) 4522 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4523 } 4524 4525 static void 4526 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4527 { 4528 4529 if (BGE_IS_57765_PLUS(sc)) { 4530 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4531 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4532 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4533 if ((cur_rx->bge_error_flag & 4534 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4535 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4536 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4537 m->m_pkthdr.csum_data = 4538 cur_rx->bge_tcp_udp_csum; 4539 m->m_pkthdr.csum_flags |= 4540 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4541 M_CSUM_DATA); 4542 } 4543 } 4544 } else { 4545 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4546 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4547 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4548 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4549 /* 4550 * Rx transport checksum-offload may also 4551 * have bugs with packets which, when transmitted, 4552 * were `runts' requiring padding. 4553 */ 4554 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4555 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4556 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4557 m->m_pkthdr.csum_data = 4558 cur_rx->bge_tcp_udp_csum; 4559 m->m_pkthdr.csum_flags |= 4560 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4561 M_CSUM_DATA); 4562 } 4563 } 4564 } 4565 4566 static void 4567 bge_txeof(struct bge_softc *sc) 4568 { 4569 struct bge_tx_bd *cur_tx = NULL; 4570 struct ifnet *ifp; 4571 struct txdmamap_pool_entry *dma; 4572 bus_addr_t offset, toff; 4573 bus_size_t tlen; 4574 int tosync; 4575 struct mbuf *m; 4576 4577 ifp = &sc->ethercom.ec_if; 4578 4579 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4580 offsetof(struct bge_ring_data, bge_status_block), 4581 sizeof (struct bge_status_block), 4582 BUS_DMASYNC_POSTREAD); 4583 4584 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4585 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4586 sc->bge_tx_saved_considx; 4587 4588 if (tosync != 0) 4589 rnd_add_uint32(&sc->rnd_source, tosync); 4590 4591 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4592 4593 if (tosync < 0) { 4594 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4595 sizeof (struct bge_tx_bd); 4596 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4597 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4598 tosync = -tosync; 4599 } 4600 4601 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4602 offset, tosync * sizeof (struct bge_tx_bd), 4603 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4604 4605 /* 4606 * Go through our tx ring and free mbufs for those 4607 * frames that have been sent. 4608 */ 4609 while (sc->bge_tx_saved_considx != 4610 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4611 uint32_t idx = 0; 4612 4613 idx = sc->bge_tx_saved_considx; 4614 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4615 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4616 ifp->if_opackets++; 4617 m = sc->bge_cdata.bge_tx_chain[idx]; 4618 if (m != NULL) { 4619 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4620 dma = sc->txdma[idx]; 4621 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4622 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4623 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4624 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4625 sc->txdma[idx] = NULL; 4626 4627 m_freem(m); 4628 } 4629 sc->bge_txcnt--; 4630 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4631 ifp->if_timer = 0; 4632 } 4633 4634 if (cur_tx != NULL) 4635 ifp->if_flags &= ~IFF_OACTIVE; 4636 } 4637 4638 static int 4639 bge_intr(void *xsc) 4640 { 4641 struct bge_softc *sc; 4642 struct ifnet *ifp; 4643 uint32_t statusword; 4644 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4645 4646 sc = xsc; 4647 ifp = &sc->ethercom.ec_if; 4648 4649 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4650 if (BGE_IS_5717_PLUS(sc)) 4651 intrmask = 0; 4652 4653 /* It is possible for the interrupt to arrive before 4654 * the status block is updated prior to the interrupt. 4655 * Reading the PCI State register will confirm whether the 4656 * interrupt is ours and will flush the status block. 4657 */ 4658 4659 /* read status word from status block */ 4660 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4661 offsetof(struct bge_ring_data, bge_status_block), 4662 sizeof (struct bge_status_block), 4663 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4664 statusword = sc->bge_rdata->bge_status_block.bge_status; 4665 4666 if ((statusword & BGE_STATFLAG_UPDATED) || 4667 (~CSR_READ_4(sc, BGE_PCI_PCISTATE) & intrmask)) { 4668 /* Ack interrupt and stop others from occuring. */ 4669 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4670 4671 BGE_EVCNT_INCR(sc->bge_ev_intr); 4672 4673 /* clear status word */ 4674 sc->bge_rdata->bge_status_block.bge_status = 0; 4675 4676 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4677 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4678 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4679 bge_link_upd(sc); 4680 4681 if (ifp->if_flags & IFF_RUNNING) { 4682 /* Check RX return ring producer/consumer */ 4683 bge_rxeof(sc); 4684 4685 /* Check TX ring producer/consumer */ 4686 bge_txeof(sc); 4687 } 4688 4689 if (sc->bge_pending_rxintr_change) { 4690 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4691 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4692 4693 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4694 DELAY(10); 4695 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4696 4697 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4698 DELAY(10); 4699 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4700 4701 sc->bge_pending_rxintr_change = 0; 4702 } 4703 bge_handle_events(sc); 4704 4705 /* Re-enable interrupts. */ 4706 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 4707 4708 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4709 bge_start(ifp); 4710 4711 return 1; 4712 } else 4713 return 0; 4714 } 4715 4716 static void 4717 bge_asf_driver_up(struct bge_softc *sc) 4718 { 4719 if (sc->bge_asf_mode & ASF_STACKUP) { 4720 /* Send ASF heartbeat aprox. every 2s */ 4721 if (sc->bge_asf_count) 4722 sc->bge_asf_count --; 4723 else { 4724 sc->bge_asf_count = 2; 4725 4726 bge_wait_for_event_ack(sc); 4727 4728 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4729 BGE_FW_CMD_DRV_ALIVE); 4730 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4731 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4732 BGE_FW_HB_TIMEOUT_SEC); 4733 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4734 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4735 BGE_RX_CPU_DRV_EVENT); 4736 } 4737 } 4738 } 4739 4740 static void 4741 bge_tick(void *xsc) 4742 { 4743 struct bge_softc *sc = xsc; 4744 struct mii_data *mii = &sc->bge_mii; 4745 int s; 4746 4747 s = splnet(); 4748 4749 if (BGE_IS_5705_PLUS(sc)) 4750 bge_stats_update_regs(sc); 4751 else 4752 bge_stats_update(sc); 4753 4754 if (sc->bge_flags & BGEF_FIBER_TBI) { 4755 /* 4756 * Since in TBI mode auto-polling can't be used we should poll 4757 * link status manually. Here we register pending link event 4758 * and trigger interrupt. 4759 */ 4760 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4761 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4762 } else { 4763 /* 4764 * Do not touch PHY if we have link up. This could break 4765 * IPMI/ASF mode or produce extra input errors. 4766 * (extra input errors was reported for bcm5701 & bcm5704). 4767 */ 4768 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4769 mii_tick(mii); 4770 } 4771 4772 bge_asf_driver_up(sc); 4773 4774 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4775 4776 splx(s); 4777 } 4778 4779 static void 4780 bge_stats_update_regs(struct bge_softc *sc) 4781 { 4782 struct ifnet *ifp = &sc->ethercom.ec_if; 4783 4784 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4785 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4786 4787 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4788 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4789 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4790 } 4791 4792 static void 4793 bge_stats_update(struct bge_softc *sc) 4794 { 4795 struct ifnet *ifp = &sc->ethercom.ec_if; 4796 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4797 4798 #define READ_STAT(sc, stats, stat) \ 4799 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4800 4801 ifp->if_collisions += 4802 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4803 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4804 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4805 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4806 ifp->if_collisions; 4807 4808 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4809 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4810 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4811 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4812 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4813 READ_STAT(sc, stats, 4814 xoffPauseFramesReceived.bge_addr_lo)); 4815 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4816 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4817 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4818 READ_STAT(sc, stats, 4819 macControlFramesReceived.bge_addr_lo)); 4820 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4821 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4822 4823 #undef READ_STAT 4824 4825 #ifdef notdef 4826 ifp->if_collisions += 4827 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4828 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4829 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4830 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4831 ifp->if_collisions; 4832 #endif 4833 } 4834 4835 /* 4836 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4837 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4838 * but when such padded frames employ the bge IP/TCP checksum offload, 4839 * the hardware checksum assist gives incorrect results (possibly 4840 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4841 * If we pad such runts with zeros, the onboard checksum comes out correct. 4842 */ 4843 static inline int 4844 bge_cksum_pad(struct mbuf *pkt) 4845 { 4846 struct mbuf *last = NULL; 4847 int padlen; 4848 4849 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4850 4851 /* if there's only the packet-header and we can pad there, use it. */ 4852 if (pkt->m_pkthdr.len == pkt->m_len && 4853 M_TRAILINGSPACE(pkt) >= padlen) { 4854 last = pkt; 4855 } else { 4856 /* 4857 * Walk packet chain to find last mbuf. We will either 4858 * pad there, or append a new mbuf and pad it 4859 * (thus perhaps avoiding the bcm5700 dma-min bug). 4860 */ 4861 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4862 continue; /* do nothing */ 4863 } 4864 4865 /* `last' now points to last in chain. */ 4866 if (M_TRAILINGSPACE(last) < padlen) { 4867 /* Allocate new empty mbuf, pad it. Compact later. */ 4868 struct mbuf *n; 4869 MGET(n, M_DONTWAIT, MT_DATA); 4870 if (n == NULL) 4871 return ENOBUFS; 4872 n->m_len = 0; 4873 last->m_next = n; 4874 last = n; 4875 } 4876 } 4877 4878 KDASSERT(!M_READONLY(last)); 4879 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4880 4881 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4882 memset(mtod(last, char *) + last->m_len, 0, padlen); 4883 last->m_len += padlen; 4884 pkt->m_pkthdr.len += padlen; 4885 return 0; 4886 } 4887 4888 /* 4889 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4890 */ 4891 static inline int 4892 bge_compact_dma_runt(struct mbuf *pkt) 4893 { 4894 struct mbuf *m, *prev; 4895 int totlen; 4896 4897 prev = NULL; 4898 totlen = 0; 4899 4900 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4901 int mlen = m->m_len; 4902 int shortfall = 8 - mlen ; 4903 4904 totlen += mlen; 4905 if (mlen == 0) 4906 continue; 4907 if (mlen >= 8) 4908 continue; 4909 4910 /* If we get here, mbuf data is too small for DMA engine. 4911 * Try to fix by shuffling data to prev or next in chain. 4912 * If that fails, do a compacting deep-copy of the whole chain. 4913 */ 4914 4915 /* Internal frag. If fits in prev, copy it there. */ 4916 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4917 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4918 prev->m_len += mlen; 4919 m->m_len = 0; 4920 /* XXX stitch chain */ 4921 prev->m_next = m_free(m); 4922 m = prev; 4923 continue; 4924 } 4925 else if (m->m_next != NULL && 4926 M_TRAILINGSPACE(m) >= shortfall && 4927 m->m_next->m_len >= (8 + shortfall)) { 4928 /* m is writable and have enough data in next, pull up. */ 4929 4930 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4931 shortfall); 4932 m->m_len += shortfall; 4933 m->m_next->m_len -= shortfall; 4934 m->m_next->m_data += shortfall; 4935 } 4936 else if (m->m_next == NULL || 1) { 4937 /* Got a runt at the very end of the packet. 4938 * borrow data from the tail of the preceding mbuf and 4939 * update its length in-place. (The original data is still 4940 * valid, so we can do this even if prev is not writable.) 4941 */ 4942 4943 /* if we'd make prev a runt, just move all of its data. */ 4944 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4945 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4946 4947 if ((prev->m_len - shortfall) < 8) 4948 shortfall = prev->m_len; 4949 4950 #ifdef notyet /* just do the safe slow thing for now */ 4951 if (!M_READONLY(m)) { 4952 if (M_LEADINGSPACE(m) < shorfall) { 4953 void *m_dat; 4954 m_dat = (m->m_flags & M_PKTHDR) ? 4955 m->m_pktdat : m->dat; 4956 memmove(m_dat, mtod(m, void*), m->m_len); 4957 m->m_data = m_dat; 4958 } 4959 } else 4960 #endif /* just do the safe slow thing */ 4961 { 4962 struct mbuf * n = NULL; 4963 int newprevlen = prev->m_len - shortfall; 4964 4965 MGET(n, M_NOWAIT, MT_DATA); 4966 if (n == NULL) 4967 return ENOBUFS; 4968 KASSERT(m->m_len + shortfall < MLEN 4969 /*, 4970 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4971 4972 /* first copy the data we're stealing from prev */ 4973 memcpy(n->m_data, prev->m_data + newprevlen, 4974 shortfall); 4975 4976 /* update prev->m_len accordingly */ 4977 prev->m_len -= shortfall; 4978 4979 /* copy data from runt m */ 4980 memcpy(n->m_data + shortfall, m->m_data, 4981 m->m_len); 4982 4983 /* n holds what we stole from prev, plus m */ 4984 n->m_len = shortfall + m->m_len; 4985 4986 /* stitch n into chain and free m */ 4987 n->m_next = m->m_next; 4988 prev->m_next = n; 4989 /* KASSERT(m->m_next == NULL); */ 4990 m->m_next = NULL; 4991 m_free(m); 4992 m = n; /* for continuing loop */ 4993 } 4994 } 4995 } 4996 return 0; 4997 } 4998 4999 /* 5000 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5001 * pointers to descriptors. 5002 */ 5003 static int 5004 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5005 { 5006 struct bge_tx_bd *f = NULL; 5007 uint32_t frag, cur; 5008 uint16_t csum_flags = 0; 5009 uint16_t txbd_tso_flags = 0; 5010 struct txdmamap_pool_entry *dma; 5011 bus_dmamap_t dmamap; 5012 int i = 0; 5013 struct m_tag *mtag; 5014 int use_tso, maxsegsize, error; 5015 5016 cur = frag = *txidx; 5017 5018 if (m_head->m_pkthdr.csum_flags) { 5019 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5020 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5021 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 5022 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5023 } 5024 5025 /* 5026 * If we were asked to do an outboard checksum, and the NIC 5027 * has the bug where it sometimes adds in the Ethernet padding, 5028 * explicitly pad with zeros so the cksum will be correct either way. 5029 * (For now, do this for all chip versions, until newer 5030 * are confirmed to not require the workaround.) 5031 */ 5032 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5033 #ifdef notyet 5034 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5035 #endif 5036 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5037 goto check_dma_bug; 5038 5039 if (bge_cksum_pad(m_head) != 0) 5040 return ENOBUFS; 5041 5042 check_dma_bug: 5043 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5044 goto doit; 5045 5046 /* 5047 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5048 * less than eight bytes. If we encounter a teeny mbuf 5049 * at the end of a chain, we can pad. Otherwise, copy. 5050 */ 5051 if (bge_compact_dma_runt(m_head) != 0) 5052 return ENOBUFS; 5053 5054 doit: 5055 dma = SLIST_FIRST(&sc->txdma_list); 5056 if (dma == NULL) 5057 return ENOBUFS; 5058 dmamap = dma->dmamap; 5059 5060 /* 5061 * Set up any necessary TSO state before we start packing... 5062 */ 5063 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5064 if (!use_tso) { 5065 maxsegsize = 0; 5066 } else { /* TSO setup */ 5067 unsigned mss; 5068 struct ether_header *eh; 5069 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5070 struct mbuf * m0 = m_head; 5071 struct ip *ip; 5072 struct tcphdr *th; 5073 int iphl, hlen; 5074 5075 /* 5076 * XXX It would be nice if the mbuf pkthdr had offset 5077 * fields for the protocol headers. 5078 */ 5079 5080 eh = mtod(m0, struct ether_header *); 5081 switch (htons(eh->ether_type)) { 5082 case ETHERTYPE_IP: 5083 offset = ETHER_HDR_LEN; 5084 break; 5085 5086 case ETHERTYPE_VLAN: 5087 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5088 break; 5089 5090 default: 5091 /* 5092 * Don't support this protocol or encapsulation. 5093 */ 5094 return ENOBUFS; 5095 } 5096 5097 /* 5098 * TCP/IP headers are in the first mbuf; we can do 5099 * this the easy way. 5100 */ 5101 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5102 hlen = iphl + offset; 5103 if (__predict_false(m0->m_len < 5104 (hlen + sizeof(struct tcphdr)))) { 5105 5106 aprint_debug_dev(sc->bge_dev, 5107 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5108 "not handled yet\n", 5109 m0->m_len, hlen+ sizeof(struct tcphdr)); 5110 #ifdef NOTYET 5111 /* 5112 * XXX jonathan (at) NetBSD.org: untested. 5113 * how to force this branch to be taken? 5114 */ 5115 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5116 5117 m_copydata(m0, offset, sizeof(ip), &ip); 5118 m_copydata(m0, hlen, sizeof(th), &th); 5119 5120 ip.ip_len = 0; 5121 5122 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5123 sizeof(ip.ip_len), &ip.ip_len); 5124 5125 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5126 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5127 5128 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5129 sizeof(th.th_sum), &th.th_sum); 5130 5131 hlen += th.th_off << 2; 5132 iptcp_opt_words = hlen; 5133 #else 5134 /* 5135 * if_wm "hard" case not yet supported, can we not 5136 * mandate it out of existence? 5137 */ 5138 (void) ip; (void)th; (void) ip_tcp_hlen; 5139 5140 return ENOBUFS; 5141 #endif 5142 } else { 5143 ip = (struct ip *) (mtod(m0, char *) + offset); 5144 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5145 ip_tcp_hlen = iphl + (th->th_off << 2); 5146 5147 /* Total IP/TCP options, in 32-bit words */ 5148 iptcp_opt_words = (ip_tcp_hlen 5149 - sizeof(struct tcphdr) 5150 - sizeof(struct ip)) >> 2; 5151 } 5152 if (BGE_IS_575X_PLUS(sc)) { 5153 th->th_sum = 0; 5154 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5155 } else { 5156 /* 5157 * XXX jonathan (at) NetBSD.org: 5705 untested. 5158 * Requires TSO firmware patch for 5701/5703/5704. 5159 */ 5160 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5161 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5162 } 5163 5164 mss = m_head->m_pkthdr.segsz; 5165 txbd_tso_flags |= 5166 BGE_TXBDFLAG_CPU_PRE_DMA | 5167 BGE_TXBDFLAG_CPU_POST_DMA; 5168 5169 /* 5170 * Our NIC TSO-assist assumes TSO has standard, optionless 5171 * IPv4 and TCP headers, which total 40 bytes. By default, 5172 * the NIC copies 40 bytes of IP/TCP header from the 5173 * supplied header into the IP/TCP header portion of 5174 * each post-TSO-segment. If the supplied packet has IP or 5175 * TCP options, we need to tell the NIC to copy those extra 5176 * bytes into each post-TSO header, in addition to the normal 5177 * 40-byte IP/TCP header (and to leave space accordingly). 5178 * Unfortunately, the driver encoding of option length 5179 * varies across different ASIC families. 5180 */ 5181 tcp_seg_flags = 0; 5182 if (iptcp_opt_words) { 5183 if (BGE_IS_5705_PLUS(sc)) { 5184 tcp_seg_flags = 5185 iptcp_opt_words << 11; 5186 } else { 5187 txbd_tso_flags |= 5188 iptcp_opt_words << 12; 5189 } 5190 } 5191 maxsegsize = mss | tcp_seg_flags; 5192 ip->ip_len = htons(mss + ip_tcp_hlen); 5193 5194 } /* TSO setup */ 5195 5196 /* 5197 * Start packing the mbufs in this chain into 5198 * the fragment pointers. Stop when we run out 5199 * of fragments or hit the end of the mbuf chain. 5200 */ 5201 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5202 BUS_DMA_NOWAIT); 5203 if (error) 5204 return ENOBUFS; 5205 /* 5206 * Sanity check: avoid coming within 16 descriptors 5207 * of the end of the ring. 5208 */ 5209 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5210 BGE_TSO_PRINTF(("%s: " 5211 " dmamap_load_mbuf too close to ring wrap\n", 5212 device_xname(sc->bge_dev))); 5213 goto fail_unload; 5214 } 5215 5216 mtag = sc->ethercom.ec_nvlans ? 5217 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5218 5219 5220 /* Iterate over dmap-map fragments. */ 5221 for (i = 0; i < dmamap->dm_nsegs; i++) { 5222 f = &sc->bge_rdata->bge_tx_ring[frag]; 5223 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5224 break; 5225 5226 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5227 f->bge_len = dmamap->dm_segs[i].ds_len; 5228 5229 /* 5230 * For 5751 and follow-ons, for TSO we must turn 5231 * off checksum-assist flag in the tx-descr, and 5232 * supply the ASIC-revision-specific encoding 5233 * of TSO flags and segsize. 5234 */ 5235 if (use_tso) { 5236 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5237 f->bge_rsvd = maxsegsize; 5238 f->bge_flags = csum_flags | txbd_tso_flags; 5239 } else { 5240 f->bge_rsvd = 0; 5241 f->bge_flags = 5242 (csum_flags | txbd_tso_flags) & 0x0fff; 5243 } 5244 } else { 5245 f->bge_rsvd = 0; 5246 f->bge_flags = csum_flags; 5247 } 5248 5249 if (mtag != NULL) { 5250 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5251 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5252 } else { 5253 f->bge_vlan_tag = 0; 5254 } 5255 cur = frag; 5256 BGE_INC(frag, BGE_TX_RING_CNT); 5257 } 5258 5259 if (i < dmamap->dm_nsegs) { 5260 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5261 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5262 goto fail_unload; 5263 } 5264 5265 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5266 BUS_DMASYNC_PREWRITE); 5267 5268 if (frag == sc->bge_tx_saved_considx) { 5269 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5270 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5271 5272 goto fail_unload; 5273 } 5274 5275 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5276 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5277 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5278 sc->txdma[cur] = dma; 5279 sc->bge_txcnt += dmamap->dm_nsegs; 5280 5281 *txidx = frag; 5282 5283 return 0; 5284 5285 fail_unload: 5286 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5287 5288 return ENOBUFS; 5289 } 5290 5291 /* 5292 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5293 * to the mbuf data regions directly in the transmit descriptors. 5294 */ 5295 static void 5296 bge_start(struct ifnet *ifp) 5297 { 5298 struct bge_softc *sc; 5299 struct mbuf *m_head = NULL; 5300 uint32_t prodidx; 5301 int pkts = 0; 5302 5303 sc = ifp->if_softc; 5304 5305 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5306 return; 5307 5308 prodidx = sc->bge_tx_prodidx; 5309 5310 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5311 IFQ_POLL(&ifp->if_snd, m_head); 5312 if (m_head == NULL) 5313 break; 5314 5315 #if 0 5316 /* 5317 * XXX 5318 * safety overkill. If this is a fragmented packet chain 5319 * with delayed TCP/UDP checksums, then only encapsulate 5320 * it if we have enough descriptors to handle the entire 5321 * chain at once. 5322 * (paranoia -- may not actually be needed) 5323 */ 5324 if (m_head->m_flags & M_FIRSTFRAG && 5325 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5326 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5327 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5328 ifp->if_flags |= IFF_OACTIVE; 5329 break; 5330 } 5331 } 5332 #endif 5333 5334 /* 5335 * Pack the data into the transmit ring. If we 5336 * don't have room, set the OACTIVE flag and wait 5337 * for the NIC to drain the ring. 5338 */ 5339 if (bge_encap(sc, m_head, &prodidx)) { 5340 ifp->if_flags |= IFF_OACTIVE; 5341 break; 5342 } 5343 5344 /* now we are committed to transmit the packet */ 5345 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5346 pkts++; 5347 5348 /* 5349 * If there's a BPF listener, bounce a copy of this frame 5350 * to him. 5351 */ 5352 bpf_mtap(ifp, m_head); 5353 } 5354 if (pkts == 0) 5355 return; 5356 5357 /* Transmit */ 5358 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5359 /* 5700 b2 errata */ 5360 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5361 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5362 5363 sc->bge_tx_prodidx = prodidx; 5364 5365 /* 5366 * Set a timeout in case the chip goes out to lunch. 5367 */ 5368 ifp->if_timer = 5; 5369 } 5370 5371 static int 5372 bge_init(struct ifnet *ifp) 5373 { 5374 struct bge_softc *sc = ifp->if_softc; 5375 const uint16_t *m; 5376 uint32_t mode, reg; 5377 int s, error = 0; 5378 5379 s = splnet(); 5380 5381 ifp = &sc->ethercom.ec_if; 5382 5383 /* Cancel pending I/O and flush buffers. */ 5384 bge_stop(ifp, 0); 5385 5386 bge_stop_fw(sc); 5387 bge_sig_pre_reset(sc, BGE_RESET_START); 5388 bge_reset(sc); 5389 bge_sig_legacy(sc, BGE_RESET_START); 5390 bge_sig_post_reset(sc, BGE_RESET_START); 5391 5392 bge_chipinit(sc); 5393 5394 /* 5395 * Init the various state machines, ring 5396 * control blocks and firmware. 5397 */ 5398 error = bge_blockinit(sc); 5399 if (error != 0) { 5400 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5401 error); 5402 splx(s); 5403 return error; 5404 } 5405 5406 ifp = &sc->ethercom.ec_if; 5407 5408 /* 5718 step 25, 57XX step 54 */ 5409 /* Specify MTU. */ 5410 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5411 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5412 5413 /* 5718 step 23 */ 5414 /* Load our MAC address. */ 5415 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5416 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5417 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5418 5419 /* Enable or disable promiscuous mode as needed. */ 5420 if (ifp->if_flags & IFF_PROMISC) 5421 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5422 else 5423 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5424 5425 /* Program multicast filter. */ 5426 bge_setmulti(sc); 5427 5428 /* Init RX ring. */ 5429 bge_init_rx_ring_std(sc); 5430 5431 /* 5432 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5433 * memory to insure that the chip has in fact read the first 5434 * entry of the ring. 5435 */ 5436 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5437 uint32_t v, i; 5438 for (i = 0; i < 10; i++) { 5439 DELAY(20); 5440 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5441 if (v == (MCLBYTES - ETHER_ALIGN)) 5442 break; 5443 } 5444 if (i == 10) 5445 aprint_error_dev(sc->bge_dev, 5446 "5705 A0 chip failed to load RX ring\n"); 5447 } 5448 5449 /* Init jumbo RX ring. */ 5450 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5451 bge_init_rx_ring_jumbo(sc); 5452 5453 /* Init our RX return ring index */ 5454 sc->bge_rx_saved_considx = 0; 5455 5456 /* Init TX ring. */ 5457 bge_init_tx_ring(sc); 5458 5459 /* 5718 step 63, 57XX step 94 */ 5460 /* Enable TX MAC state machine lockup fix. */ 5461 mode = CSR_READ_4(sc, BGE_TX_MODE); 5462 if (BGE_IS_5755_PLUS(sc) || 5463 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5464 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5466 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5467 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5468 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5469 } 5470 5471 /* Turn on transmitter */ 5472 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5473 /* 5718 step 64 */ 5474 DELAY(100); 5475 5476 /* 5718 step 65, 57XX step 95 */ 5477 /* Turn on receiver */ 5478 mode = CSR_READ_4(sc, BGE_RX_MODE); 5479 if (BGE_IS_5755_PLUS(sc)) 5480 mode |= BGE_RXMODE_IPV6_ENABLE; 5481 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5482 /* 5718 step 66 */ 5483 DELAY(10); 5484 5485 /* 5718 step 12, 57XX step 37 */ 5486 /* 5487 * XXX Doucments of 5718 series and 577xx say the recommended value 5488 * is 1, but tg3 set 1 only on 57765 series. 5489 */ 5490 if (BGE_IS_57765_PLUS(sc)) 5491 reg = 1; 5492 else 5493 reg = 2; 5494 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5495 5496 /* Tell firmware we're alive. */ 5497 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5498 5499 /* Enable host interrupts. */ 5500 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5501 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5502 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5503 5504 if ((error = bge_ifmedia_upd(ifp)) != 0) 5505 goto out; 5506 5507 ifp->if_flags |= IFF_RUNNING; 5508 ifp->if_flags &= ~IFF_OACTIVE; 5509 5510 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5511 5512 out: 5513 sc->bge_if_flags = ifp->if_flags; 5514 splx(s); 5515 5516 return error; 5517 } 5518 5519 /* 5520 * Set media options. 5521 */ 5522 static int 5523 bge_ifmedia_upd(struct ifnet *ifp) 5524 { 5525 struct bge_softc *sc = ifp->if_softc; 5526 struct mii_data *mii = &sc->bge_mii; 5527 struct ifmedia *ifm = &sc->bge_ifmedia; 5528 int rc; 5529 5530 /* If this is a 1000baseX NIC, enable the TBI port. */ 5531 if (sc->bge_flags & BGEF_FIBER_TBI) { 5532 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5533 return EINVAL; 5534 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5535 case IFM_AUTO: 5536 /* 5537 * The BCM5704 ASIC appears to have a special 5538 * mechanism for programming the autoneg 5539 * advertisement registers in TBI mode. 5540 */ 5541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5542 uint32_t sgdig; 5543 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5544 if (sgdig & BGE_SGDIGSTS_DONE) { 5545 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5546 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5547 sgdig |= BGE_SGDIGCFG_AUTO | 5548 BGE_SGDIGCFG_PAUSE_CAP | 5549 BGE_SGDIGCFG_ASYM_PAUSE; 5550 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5551 sgdig | BGE_SGDIGCFG_SEND); 5552 DELAY(5); 5553 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5554 sgdig); 5555 } 5556 } 5557 break; 5558 case IFM_1000_SX: 5559 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5560 BGE_CLRBIT(sc, BGE_MAC_MODE, 5561 BGE_MACMODE_HALF_DUPLEX); 5562 } else { 5563 BGE_SETBIT(sc, BGE_MAC_MODE, 5564 BGE_MACMODE_HALF_DUPLEX); 5565 } 5566 DELAY(40); 5567 break; 5568 default: 5569 return EINVAL; 5570 } 5571 /* XXX 802.3x flow control for 1000BASE-SX */ 5572 return 0; 5573 } 5574 5575 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5576 if ((rc = mii_mediachg(mii)) == ENXIO) 5577 return 0; 5578 5579 /* 5580 * Force an interrupt so that we will call bge_link_upd 5581 * if needed and clear any pending link state attention. 5582 * Without this we are not getting any further interrupts 5583 * for link state changes and thus will not UP the link and 5584 * not be able to send in bge_start. The only way to get 5585 * things working was to receive a packet and get a RX intr. 5586 */ 5587 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5588 sc->bge_flags & BGEF_IS_5788) 5589 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5590 else 5591 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5592 5593 return rc; 5594 } 5595 5596 /* 5597 * Report current media status. 5598 */ 5599 static void 5600 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5601 { 5602 struct bge_softc *sc = ifp->if_softc; 5603 struct mii_data *mii = &sc->bge_mii; 5604 5605 if (sc->bge_flags & BGEF_FIBER_TBI) { 5606 ifmr->ifm_status = IFM_AVALID; 5607 ifmr->ifm_active = IFM_ETHER; 5608 if (CSR_READ_4(sc, BGE_MAC_STS) & 5609 BGE_MACSTAT_TBI_PCS_SYNCHED) 5610 ifmr->ifm_status |= IFM_ACTIVE; 5611 ifmr->ifm_active |= IFM_1000_SX; 5612 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5613 ifmr->ifm_active |= IFM_HDX; 5614 else 5615 ifmr->ifm_active |= IFM_FDX; 5616 return; 5617 } 5618 5619 mii_pollstat(mii); 5620 ifmr->ifm_status = mii->mii_media_status; 5621 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5622 sc->bge_flowflags; 5623 } 5624 5625 static int 5626 bge_ifflags_cb(struct ethercom *ec) 5627 { 5628 struct ifnet *ifp = &ec->ec_if; 5629 struct bge_softc *sc = ifp->if_softc; 5630 int change = ifp->if_flags ^ sc->bge_if_flags; 5631 5632 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5633 return ENETRESET; 5634 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5635 return 0; 5636 5637 if ((ifp->if_flags & IFF_PROMISC) == 0) 5638 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5639 else 5640 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5641 5642 bge_setmulti(sc); 5643 5644 sc->bge_if_flags = ifp->if_flags; 5645 return 0; 5646 } 5647 5648 static int 5649 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5650 { 5651 struct bge_softc *sc = ifp->if_softc; 5652 struct ifreq *ifr = (struct ifreq *) data; 5653 int s, error = 0; 5654 struct mii_data *mii; 5655 5656 s = splnet(); 5657 5658 switch (command) { 5659 case SIOCSIFMEDIA: 5660 /* XXX Flow control is not supported for 1000BASE-SX */ 5661 if (sc->bge_flags & BGEF_FIBER_TBI) { 5662 ifr->ifr_media &= ~IFM_ETH_FMASK; 5663 sc->bge_flowflags = 0; 5664 } 5665 5666 /* Flow control requires full-duplex mode. */ 5667 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5668 (ifr->ifr_media & IFM_FDX) == 0) { 5669 ifr->ifr_media &= ~IFM_ETH_FMASK; 5670 } 5671 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5672 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5673 /* We can do both TXPAUSE and RXPAUSE. */ 5674 ifr->ifr_media |= 5675 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5676 } 5677 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5678 } 5679 /* FALLTHROUGH */ 5680 case SIOCGIFMEDIA: 5681 if (sc->bge_flags & BGEF_FIBER_TBI) { 5682 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5683 command); 5684 } else { 5685 mii = &sc->bge_mii; 5686 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5687 command); 5688 } 5689 break; 5690 default: 5691 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5692 break; 5693 5694 error = 0; 5695 5696 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5697 ; 5698 else if (ifp->if_flags & IFF_RUNNING) 5699 bge_setmulti(sc); 5700 break; 5701 } 5702 5703 splx(s); 5704 5705 return error; 5706 } 5707 5708 static void 5709 bge_watchdog(struct ifnet *ifp) 5710 { 5711 struct bge_softc *sc; 5712 5713 sc = ifp->if_softc; 5714 5715 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5716 5717 ifp->if_flags &= ~IFF_RUNNING; 5718 bge_init(ifp); 5719 5720 ifp->if_oerrors++; 5721 } 5722 5723 static void 5724 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5725 { 5726 int i; 5727 5728 BGE_CLRBIT_FLUSH(sc, reg, bit); 5729 5730 for (i = 0; i < 1000; i++) { 5731 delay(100); 5732 if ((CSR_READ_4(sc, reg) & bit) == 0) 5733 return; 5734 } 5735 5736 /* 5737 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5738 * on some environment (and once after boot?) 5739 */ 5740 if (reg != BGE_SRS_MODE) 5741 aprint_error_dev(sc->bge_dev, 5742 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5743 (u_long)reg, bit); 5744 } 5745 5746 /* 5747 * Stop the adapter and free any mbufs allocated to the 5748 * RX and TX lists. 5749 */ 5750 static void 5751 bge_stop(struct ifnet *ifp, int disable) 5752 { 5753 struct bge_softc *sc = ifp->if_softc; 5754 5755 if (disable) 5756 callout_halt(&sc->bge_timeout, NULL); 5757 else 5758 callout_stop(&sc->bge_timeout); 5759 5760 /* Disable host interrupts. */ 5761 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5762 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5763 5764 /* 5765 * Tell firmware we're shutting down. 5766 */ 5767 bge_stop_fw(sc); 5768 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5769 5770 /* 5771 * Disable all of the receiver blocks. 5772 */ 5773 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5774 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5775 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5776 if (BGE_IS_5700_FAMILY(sc)) 5777 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5778 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5779 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5780 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5781 5782 /* 5783 * Disable all of the transmit blocks. 5784 */ 5785 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5786 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5787 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5788 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5789 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5790 if (BGE_IS_5700_FAMILY(sc)) 5791 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5792 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5793 5794 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5795 delay(40); 5796 5797 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5798 5799 /* 5800 * Shut down all of the memory managers and related 5801 * state machines. 5802 */ 5803 /* 5718 step 5a,5b */ 5804 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5805 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5806 if (BGE_IS_5700_FAMILY(sc)) 5807 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5808 5809 /* 5718 step 5c,5d */ 5810 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5811 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5812 5813 if (BGE_IS_5700_FAMILY(sc)) { 5814 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5815 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5816 } 5817 5818 bge_reset(sc); 5819 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5820 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5821 5822 /* 5823 * Keep the ASF firmware running if up. 5824 */ 5825 if (sc->bge_asf_mode & ASF_STACKUP) 5826 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5827 else 5828 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5829 5830 /* Free the RX lists. */ 5831 bge_free_rx_ring_std(sc); 5832 5833 /* Free jumbo RX list. */ 5834 if (BGE_IS_JUMBO_CAPABLE(sc)) 5835 bge_free_rx_ring_jumbo(sc); 5836 5837 /* Free TX buffers. */ 5838 bge_free_tx_ring(sc); 5839 5840 /* 5841 * Isolate/power down the PHY. 5842 */ 5843 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 5844 mii_down(&sc->bge_mii); 5845 5846 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5847 5848 /* Clear MAC's link state (PHY may still have link UP). */ 5849 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5850 5851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5852 } 5853 5854 static void 5855 bge_link_upd(struct bge_softc *sc) 5856 { 5857 struct ifnet *ifp = &sc->ethercom.ec_if; 5858 struct mii_data *mii = &sc->bge_mii; 5859 uint32_t status; 5860 int link; 5861 5862 /* Clear 'pending link event' flag */ 5863 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5864 5865 /* 5866 * Process link state changes. 5867 * Grrr. The link status word in the status block does 5868 * not work correctly on the BCM5700 rev AX and BX chips, 5869 * according to all available information. Hence, we have 5870 * to enable MII interrupts in order to properly obtain 5871 * async link changes. Unfortunately, this also means that 5872 * we have to read the MAC status register to detect link 5873 * changes, thereby adding an additional register access to 5874 * the interrupt handler. 5875 */ 5876 5877 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5878 status = CSR_READ_4(sc, BGE_MAC_STS); 5879 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5880 mii_pollstat(mii); 5881 5882 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5883 mii->mii_media_status & IFM_ACTIVE && 5884 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5885 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5886 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5887 (!(mii->mii_media_status & IFM_ACTIVE) || 5888 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5889 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5890 5891 /* Clear the interrupt */ 5892 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5893 BGE_EVTENB_MI_INTERRUPT); 5894 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5895 BRGPHY_MII_ISR); 5896 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5897 BRGPHY_MII_IMR, BRGPHY_INTRS); 5898 } 5899 return; 5900 } 5901 5902 if (sc->bge_flags & BGEF_FIBER_TBI) { 5903 status = CSR_READ_4(sc, BGE_MAC_STS); 5904 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5905 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 5906 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5907 if (BGE_ASICREV(sc->bge_chipid) 5908 == BGE_ASICREV_BCM5704) { 5909 BGE_CLRBIT(sc, BGE_MAC_MODE, 5910 BGE_MACMODE_TBI_SEND_CFGS); 5911 DELAY(40); 5912 } 5913 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5914 if_link_state_change(ifp, LINK_STATE_UP); 5915 } 5916 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 5917 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5918 if_link_state_change(ifp, LINK_STATE_DOWN); 5919 } 5920 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 5921 /* 5922 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 5923 * bit in status word always set. Workaround this bug by 5924 * reading PHY link status directly. 5925 */ 5926 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 5927 BGE_STS_LINK : 0; 5928 5929 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 5930 mii_pollstat(mii); 5931 5932 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5933 mii->mii_media_status & IFM_ACTIVE && 5934 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5935 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5936 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5937 (!(mii->mii_media_status & IFM_ACTIVE) || 5938 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5939 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5940 } 5941 } else { 5942 /* 5943 * For controllers that call mii_tick, we have to poll 5944 * link status. 5945 */ 5946 mii_pollstat(mii); 5947 } 5948 5949 /* Clear the attention */ 5950 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 5951 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 5952 BGE_MACSTAT_LINK_CHANGED); 5953 } 5954 5955 static int 5956 bge_sysctl_verify(SYSCTLFN_ARGS) 5957 { 5958 int error, t; 5959 struct sysctlnode node; 5960 5961 node = *rnode; 5962 t = *(int*)rnode->sysctl_data; 5963 node.sysctl_data = &t; 5964 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 5965 if (error || newp == NULL) 5966 return error; 5967 5968 #if 0 5969 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 5970 node.sysctl_num, rnode->sysctl_num)); 5971 #endif 5972 5973 if (node.sysctl_num == bge_rxthresh_nodenum) { 5974 if (t < 0 || t >= NBGE_RX_THRESH) 5975 return EINVAL; 5976 bge_update_all_threshes(t); 5977 } else 5978 return EINVAL; 5979 5980 *(int*)rnode->sysctl_data = t; 5981 5982 return 0; 5983 } 5984 5985 /* 5986 * Set up sysctl(3) MIB, hw.bge.*. 5987 */ 5988 static void 5989 bge_sysctl_init(struct bge_softc *sc) 5990 { 5991 int rc, bge_root_num; 5992 const struct sysctlnode *node; 5993 5994 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 5995 0, CTLTYPE_NODE, "bge", 5996 SYSCTL_DESCR("BGE interface controls"), 5997 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 5998 goto out; 5999 } 6000 6001 bge_root_num = node->sysctl_num; 6002 6003 /* BGE Rx interrupt mitigation level */ 6004 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6005 CTLFLAG_READWRITE, 6006 CTLTYPE_INT, "rx_lvl", 6007 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6008 bge_sysctl_verify, 0, 6009 &bge_rx_thresh_lvl, 6010 0, CTL_HW, bge_root_num, CTL_CREATE, 6011 CTL_EOL)) != 0) { 6012 goto out; 6013 } 6014 6015 bge_rxthresh_nodenum = node->sysctl_num; 6016 6017 return; 6018 6019 out: 6020 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6021 } 6022 6023 #ifdef BGE_DEBUG 6024 void 6025 bge_debug_info(struct bge_softc *sc) 6026 { 6027 6028 printf("Hardware Flags:\n"); 6029 if (BGE_IS_57765_PLUS(sc)) 6030 printf(" - 57765 Plus\n"); 6031 if (BGE_IS_5717_PLUS(sc)) 6032 printf(" - 5717 Plus\n"); 6033 if (BGE_IS_5755_PLUS(sc)) 6034 printf(" - 5755 Plus\n"); 6035 if (BGE_IS_575X_PLUS(sc)) 6036 printf(" - 575X Plus\n"); 6037 if (BGE_IS_5705_PLUS(sc)) 6038 printf(" - 5705 Plus\n"); 6039 if (BGE_IS_5714_FAMILY(sc)) 6040 printf(" - 5714 Family\n"); 6041 if (BGE_IS_5700_FAMILY(sc)) 6042 printf(" - 5700 Family\n"); 6043 if (sc->bge_flags & BGEF_IS_5788) 6044 printf(" - 5788\n"); 6045 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6046 printf(" - Supports Jumbo Frames\n"); 6047 if (sc->bge_flags & BGEF_NO_EEPROM) 6048 printf(" - No EEPROM\n"); 6049 if (sc->bge_flags & BGEF_PCIX) 6050 printf(" - PCI-X Bus\n"); 6051 if (sc->bge_flags & BGEF_PCIE) 6052 printf(" - PCI Express Bus\n"); 6053 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6054 printf(" - RX Alignment Bug\n"); 6055 if (sc->bge_flags & BGEF_APE) 6056 printf(" - APE\n"); 6057 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6058 printf(" - CPMU\n"); 6059 if (sc->bge_flags & BGEF_TSO) 6060 printf(" - TSO\n"); 6061 6062 /* PHY related */ 6063 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6064 printf(" - No 3 LEDs\n"); 6065 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6066 printf(" - CRC bug\n"); 6067 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6068 printf(" - ADC bug\n"); 6069 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6070 printf(" - 5704 A0 bug\n"); 6071 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6072 printf(" - jitter bug\n"); 6073 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6074 printf(" - BER bug\n"); 6075 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6076 printf(" - adjust trim\n"); 6077 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6078 printf(" - no wirespeed\n"); 6079 6080 /* ASF related */ 6081 if (sc->bge_asf_mode & ASF_ENABLE) 6082 printf(" - ASF enable\n"); 6083 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6084 printf(" - ASF new handshake\n"); 6085 if (sc->bge_asf_mode & ASF_STACKUP) 6086 printf(" - ASF stackup\n"); 6087 } 6088 #endif /* BGE_DEBUG */ 6089 6090 static int 6091 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6092 { 6093 prop_dictionary_t dict; 6094 prop_data_t ea; 6095 6096 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6097 return 1; 6098 6099 dict = device_properties(sc->bge_dev); 6100 ea = prop_dictionary_get(dict, "mac-address"); 6101 if (ea != NULL) { 6102 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6103 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6104 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6105 return 0; 6106 } 6107 6108 return 1; 6109 } 6110 6111 static int 6112 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6113 { 6114 uint32_t mac_addr; 6115 6116 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6117 if ((mac_addr >> 16) == 0x484b) { 6118 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6119 ether_addr[1] = (uint8_t)mac_addr; 6120 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6121 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6122 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6123 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6124 ether_addr[5] = (uint8_t)mac_addr; 6125 return 0; 6126 } 6127 return 1; 6128 } 6129 6130 static int 6131 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6132 { 6133 int mac_offset = BGE_EE_MAC_OFFSET; 6134 6135 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6136 mac_offset = BGE_EE_MAC_OFFSET_5906; 6137 6138 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6139 ETHER_ADDR_LEN)); 6140 } 6141 6142 static int 6143 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6144 { 6145 6146 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6147 return 1; 6148 6149 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6150 ETHER_ADDR_LEN)); 6151 } 6152 6153 static int 6154 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6155 { 6156 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6157 /* NOTE: Order is critical */ 6158 bge_get_eaddr_fw, 6159 bge_get_eaddr_mem, 6160 bge_get_eaddr_nvram, 6161 bge_get_eaddr_eeprom, 6162 NULL 6163 }; 6164 const bge_eaddr_fcn_t *func; 6165 6166 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6167 if ((*func)(sc, eaddr) == 0) 6168 break; 6169 } 6170 return (*func == NULL ? ENXIO : 0); 6171 } 6172
Indexes created Tue Sep 23 02:09:52 GMT 2025