if_bge.c revision 1.288
1 /* $NetBSD: if_bge.c,v 1.288 2015/05/17 12:06:26 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.288 2015/05/17 12:06:26 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_can_use_msi(struct bge_softc *); 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static int bge_detach(device_t, int); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int); 254 static void bge_miibus_writereg(device_t, int, int, int); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5750, 440 "Broadcom BCM5750 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5751, 444 "Broadcom BCM5751 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5751F, 448 "Broadcom BCM5751F Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751M, 452 "Broadcom BCM5751M Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5752, 456 "Broadcom BCM5752 Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5752M, 460 "Broadcom BCM5752M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5753, 464 "Broadcom BCM5753 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5753F, 468 "Broadcom BCM5753F Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753M, 472 "Broadcom BCM5753M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5754, 476 "Broadcom BCM5754 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5754M, 480 "Broadcom BCM5754M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5755, 484 "Broadcom BCM5755 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5755M, 488 "Broadcom BCM5755M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5756, 492 "Broadcom BCM5756 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5761, 496 "Broadcom BCM5761 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5761E, 500 "Broadcom BCM5761E Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761S, 504 "Broadcom BCM5761S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761SE, 508 "Broadcom BCM5761SE Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5764, 512 "Broadcom BCM5764 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5780, 516 "Broadcom BCM5780 Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5780S, 520 "Broadcom BCM5780S Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5781, 524 "Broadcom BCM5781 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5782, 528 "Broadcom BCM5782 Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5784M, 532 "BCM5784M NetLink 1000baseT Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5785F, 536 "BCM5785F NetLink 10/100 Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5785G, 540 "BCM5785G NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5786, 544 "Broadcom BCM5786 Gigabit Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5787, 548 "Broadcom BCM5787 Gigabit Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5787F, 552 "Broadcom BCM5787F 10/100 Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787M, 556 "Broadcom BCM5787M Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5788, 560 "Broadcom BCM5788 Gigabit Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5789, 564 "Broadcom BCM5789 Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5901, 568 "Broadcom BCM5901 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5901A2, 572 "Broadcom BCM5901A2 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5903M, 576 "Broadcom BCM5903M Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5906, 580 "Broadcom BCM5906 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5906M, 584 "Broadcom BCM5906M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57760, 588 "Broadcom BCM57760 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57761, 592 "Broadcom BCM57761 Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57762, 596 "Broadcom BCM57762 Gigabit Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57765, 600 "Broadcom BCM57765 Fast Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57766, 604 "Broadcom BCM57766 Fast Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57780, 608 "Broadcom BCM57780 Fast Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57781, 612 "Broadcom BCM57781 Fast Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57782, 616 "Broadcom BCM57782 Fast Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57785, 620 "Broadcom BCM57785 Fast Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57786, 624 "Broadcom BCM57786 Fast Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57788, 628 "Broadcom BCM57788 Fast Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57790, 632 "Broadcom BCM57790 Fast Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57791, 636 "Broadcom BCM57791 Fast Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57795, 640 "Broadcom BCM57795 Fast Ethernet", 641 }, 642 { PCI_VENDOR_SCHNEIDERKOCH, 643 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 644 "SysKonnect SK-9Dx1 Gigabit Ethernet", 645 }, 646 { PCI_VENDOR_3COM, 647 PCI_PRODUCT_3COM_3C996, 648 "3Com 3c996 Gigabit Ethernet", 649 }, 650 { PCI_VENDOR_FUJITSU4, 651 PCI_PRODUCT_FUJITSU4_PW008GE4, 652 "Fujitsu PW008GE4 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_FUJITSU4, 655 PCI_PRODUCT_FUJITSU4_PW008GE5, 656 "Fujitsu PW008GE5 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 660 "Fujitsu Primepower 250/450 Gigabit Ethernet", 661 }, 662 { 0, 663 0, 664 NULL }, 665 }; 666 667 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 668 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 669 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 670 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 671 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 672 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 673 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 674 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 675 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 676 677 static const struct bge_revision { 678 uint32_t br_chipid; 679 const char *br_name; 680 } bge_revisions[] = { 681 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 682 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 683 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 684 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 685 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 686 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 687 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 688 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 689 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 690 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 691 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 692 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 693 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 694 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 695 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 696 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 697 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 698 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 699 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 700 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 701 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 702 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 703 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 704 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 705 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 706 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 707 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 708 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 709 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 710 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 711 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 712 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 713 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 714 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 715 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 716 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 717 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 718 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 719 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 720 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 721 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 722 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 723 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 724 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 725 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 726 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 727 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 728 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 729 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 730 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 731 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 732 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 733 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 734 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 735 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 736 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 737 /* 5754 and 5787 share the same ASIC ID */ 738 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 739 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 740 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 741 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 742 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 743 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 744 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 745 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 746 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 747 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 748 749 { 0, NULL } 750 }; 751 752 /* 753 * Some defaults for major revisions, so that newer steppings 754 * that we don't know about have a shot at working. 755 */ 756 static const struct bge_revision bge_majorrevs[] = { 757 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 758 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 759 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 760 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 761 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 762 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 763 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 764 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 765 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 766 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 767 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 768 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 769 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 770 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 771 /* 5754 and 5787 share the same ASIC ID */ 772 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 773 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 774 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 775 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 776 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 777 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 778 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 779 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 780 781 { 0, NULL } 782 }; 783 784 static int bge_allow_asf = 1; 785 786 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 787 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 788 789 static uint32_t 790 bge_readmem_ind(struct bge_softc *sc, int off) 791 { 792 pcireg_t val; 793 794 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 795 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 796 return 0; 797 798 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 799 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 800 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 801 return val; 802 } 803 804 static void 805 bge_writemem_ind(struct bge_softc *sc, int off, int val) 806 { 807 808 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 811 } 812 813 /* 814 * PCI Express only 815 */ 816 static void 817 bge_set_max_readrq(struct bge_softc *sc) 818 { 819 pcireg_t val; 820 821 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 822 + PCIE_DCSR); 823 val &= ~PCIE_DCSR_MAX_READ_REQ; 824 switch (sc->bge_expmrq) { 825 case 2048: 826 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 827 break; 828 case 4096: 829 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 830 break; 831 default: 832 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 833 break; 834 } 835 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 836 + PCIE_DCSR, val); 837 } 838 839 #ifdef notdef 840 static uint32_t 841 bge_readreg_ind(struct bge_softc *sc, int off) 842 { 843 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 844 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 845 } 846 #endif 847 848 static void 849 bge_writereg_ind(struct bge_softc *sc, int off, int val) 850 { 851 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 852 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 853 } 854 855 static void 856 bge_writemem_direct(struct bge_softc *sc, int off, int val) 857 { 858 CSR_WRITE_4(sc, off, val); 859 } 860 861 static void 862 bge_writembx(struct bge_softc *sc, int off, int val) 863 { 864 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 865 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 866 867 CSR_WRITE_4(sc, off, val); 868 } 869 870 static void 871 bge_writembx_flush(struct bge_softc *sc, int off, int val) 872 { 873 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 874 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 875 876 CSR_WRITE_4_FLUSH(sc, off, val); 877 } 878 879 /* 880 * Clear all stale locks and select the lock for this driver instance. 881 */ 882 void 883 bge_ape_lock_init(struct bge_softc *sc) 884 { 885 struct pci_attach_args *pa = &(sc->bge_pa); 886 uint32_t bit, regbase; 887 int i; 888 889 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 890 regbase = BGE_APE_LOCK_GRANT; 891 else 892 regbase = BGE_APE_PER_LOCK_GRANT; 893 894 /* Clear any stale locks. */ 895 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 896 switch (i) { 897 case BGE_APE_LOCK_PHY0: 898 case BGE_APE_LOCK_PHY1: 899 case BGE_APE_LOCK_PHY2: 900 case BGE_APE_LOCK_PHY3: 901 bit = BGE_APE_LOCK_GRANT_DRIVER0; 902 break; 903 default: 904 if (pa->pa_function == 0) 905 bit = BGE_APE_LOCK_GRANT_DRIVER0; 906 else 907 bit = (1 << pa->pa_function); 908 } 909 APE_WRITE_4(sc, regbase + 4 * i, bit); 910 } 911 912 /* Select the PHY lock based on the device's function number. */ 913 switch (pa->pa_function) { 914 case 0: 915 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 916 break; 917 case 1: 918 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 919 break; 920 case 2: 921 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 922 break; 923 case 3: 924 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 925 break; 926 default: 927 printf("%s: PHY lock not supported on function\n", 928 device_xname(sc->bge_dev)); 929 break; 930 } 931 } 932 933 /* 934 * Check for APE firmware, set flags, and print version info. 935 */ 936 void 937 bge_ape_read_fw_ver(struct bge_softc *sc) 938 { 939 const char *fwtype; 940 uint32_t apedata, features; 941 942 /* Check for a valid APE signature in shared memory. */ 943 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 944 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 945 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 946 return; 947 } 948 949 /* Check if APE firmware is running. */ 950 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 951 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 952 printf("%s: APE signature found but FW status not ready! " 953 "0x%08x\n", device_xname(sc->bge_dev), apedata); 954 return; 955 } 956 957 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 958 959 /* Fetch the APE firwmare type and version. */ 960 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 961 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 962 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 963 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 964 fwtype = "NCSI"; 965 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 966 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 967 fwtype = "DASH"; 968 } else 969 fwtype = "UNKN"; 970 971 /* Print the APE firmware version. */ 972 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 973 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 974 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 975 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 976 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 977 } 978 979 int 980 bge_ape_lock(struct bge_softc *sc, int locknum) 981 { 982 struct pci_attach_args *pa = &(sc->bge_pa); 983 uint32_t bit, gnt, req, status; 984 int i, off; 985 986 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 987 return (0); 988 989 /* Lock request/grant registers have different bases. */ 990 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 991 req = BGE_APE_LOCK_REQ; 992 gnt = BGE_APE_LOCK_GRANT; 993 } else { 994 req = BGE_APE_PER_LOCK_REQ; 995 gnt = BGE_APE_PER_LOCK_GRANT; 996 } 997 998 off = 4 * locknum; 999 1000 switch (locknum) { 1001 case BGE_APE_LOCK_GPIO: 1002 /* Lock required when using GPIO. */ 1003 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1004 return (0); 1005 if (pa->pa_function == 0) 1006 bit = BGE_APE_LOCK_REQ_DRIVER0; 1007 else 1008 bit = (1 << pa->pa_function); 1009 break; 1010 case BGE_APE_LOCK_GRC: 1011 /* Lock required to reset the device. */ 1012 if (pa->pa_function == 0) 1013 bit = BGE_APE_LOCK_REQ_DRIVER0; 1014 else 1015 bit = (1 << pa->pa_function); 1016 break; 1017 case BGE_APE_LOCK_MEM: 1018 /* Lock required when accessing certain APE memory. */ 1019 if (pa->pa_function == 0) 1020 bit = BGE_APE_LOCK_REQ_DRIVER0; 1021 else 1022 bit = (1 << pa->pa_function); 1023 break; 1024 case BGE_APE_LOCK_PHY0: 1025 case BGE_APE_LOCK_PHY1: 1026 case BGE_APE_LOCK_PHY2: 1027 case BGE_APE_LOCK_PHY3: 1028 /* Lock required when accessing PHYs. */ 1029 bit = BGE_APE_LOCK_REQ_DRIVER0; 1030 break; 1031 default: 1032 return (EINVAL); 1033 } 1034 1035 /* Request a lock. */ 1036 APE_WRITE_4_FLUSH(sc, req + off, bit); 1037 1038 /* Wait up to 1 second to acquire lock. */ 1039 for (i = 0; i < 20000; i++) { 1040 status = APE_READ_4(sc, gnt + off); 1041 if (status == bit) 1042 break; 1043 DELAY(50); 1044 } 1045 1046 /* Handle any errors. */ 1047 if (status != bit) { 1048 printf("%s: APE lock %d request failed! " 1049 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1050 device_xname(sc->bge_dev), 1051 locknum, req + off, bit & 0xFFFF, gnt + off, 1052 status & 0xFFFF); 1053 /* Revoke the lock request. */ 1054 APE_WRITE_4(sc, gnt + off, bit); 1055 return (EBUSY); 1056 } 1057 1058 return (0); 1059 } 1060 1061 void 1062 bge_ape_unlock(struct bge_softc *sc, int locknum) 1063 { 1064 struct pci_attach_args *pa = &(sc->bge_pa); 1065 uint32_t bit, gnt; 1066 int off; 1067 1068 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1069 return; 1070 1071 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1072 gnt = BGE_APE_LOCK_GRANT; 1073 else 1074 gnt = BGE_APE_PER_LOCK_GRANT; 1075 1076 off = 4 * locknum; 1077 1078 switch (locknum) { 1079 case BGE_APE_LOCK_GPIO: 1080 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1081 return; 1082 if (pa->pa_function == 0) 1083 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1084 else 1085 bit = (1 << pa->pa_function); 1086 break; 1087 case BGE_APE_LOCK_GRC: 1088 if (pa->pa_function == 0) 1089 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1090 else 1091 bit = (1 << pa->pa_function); 1092 break; 1093 case BGE_APE_LOCK_MEM: 1094 if (pa->pa_function == 0) 1095 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1096 else 1097 bit = (1 << pa->pa_function); 1098 break; 1099 case BGE_APE_LOCK_PHY0: 1100 case BGE_APE_LOCK_PHY1: 1101 case BGE_APE_LOCK_PHY2: 1102 case BGE_APE_LOCK_PHY3: 1103 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1104 break; 1105 default: 1106 return; 1107 } 1108 1109 /* Write and flush for consecutive bge_ape_lock() */ 1110 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1111 } 1112 1113 /* 1114 * Send an event to the APE firmware. 1115 */ 1116 void 1117 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1118 { 1119 uint32_t apedata; 1120 int i; 1121 1122 /* NCSI does not support APE events. */ 1123 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1124 return; 1125 1126 /* Wait up to 1ms for APE to service previous event. */ 1127 for (i = 10; i > 0; i--) { 1128 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1129 break; 1130 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1131 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1132 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1133 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1134 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1135 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1136 break; 1137 } 1138 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1139 DELAY(100); 1140 } 1141 if (i == 0) { 1142 printf("%s: APE event 0x%08x send timed out\n", 1143 device_xname(sc->bge_dev), event); 1144 } 1145 } 1146 1147 void 1148 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1149 { 1150 uint32_t apedata, event; 1151 1152 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1153 return; 1154 1155 switch (kind) { 1156 case BGE_RESET_START: 1157 /* If this is the first load, clear the load counter. */ 1158 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1159 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1160 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1161 else { 1162 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1163 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1164 } 1165 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1166 BGE_APE_HOST_SEG_SIG_MAGIC); 1167 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1168 BGE_APE_HOST_SEG_LEN_MAGIC); 1169 1170 /* Add some version info if bge(4) supports it. */ 1171 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1172 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1173 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1174 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1175 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1176 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1177 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1178 BGE_APE_HOST_DRVR_STATE_START); 1179 event = BGE_APE_EVENT_STATUS_STATE_START; 1180 break; 1181 case BGE_RESET_SHUTDOWN: 1182 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1183 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1184 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1185 break; 1186 case BGE_RESET_SUSPEND: 1187 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1188 break; 1189 default: 1190 return; 1191 } 1192 1193 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1194 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1195 } 1196 1197 static uint8_t 1198 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1199 { 1200 uint32_t access, byte = 0; 1201 int i; 1202 1203 /* Lock. */ 1204 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1205 for (i = 0; i < 8000; i++) { 1206 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1207 break; 1208 DELAY(20); 1209 } 1210 if (i == 8000) 1211 return 1; 1212 1213 /* Enable access. */ 1214 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1215 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1216 1217 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1218 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1219 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1220 DELAY(10); 1221 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1222 DELAY(10); 1223 break; 1224 } 1225 } 1226 1227 if (i == BGE_TIMEOUT * 10) { 1228 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1229 return 1; 1230 } 1231 1232 /* Get result. */ 1233 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1234 1235 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1236 1237 /* Disable access. */ 1238 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1239 1240 /* Unlock. */ 1241 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1242 1243 return 0; 1244 } 1245 1246 /* 1247 * Read a sequence of bytes from NVRAM. 1248 */ 1249 static int 1250 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1251 { 1252 int error = 0, i; 1253 uint8_t byte = 0; 1254 1255 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1256 return 1; 1257 1258 for (i = 0; i < cnt; i++) { 1259 error = bge_nvram_getbyte(sc, off + i, &byte); 1260 if (error) 1261 break; 1262 *(dest + i) = byte; 1263 } 1264 1265 return (error ? 1 : 0); 1266 } 1267 1268 /* 1269 * Read a byte of data stored in the EEPROM at address 'addr.' The 1270 * BCM570x supports both the traditional bitbang interface and an 1271 * auto access interface for reading the EEPROM. We use the auto 1272 * access method. 1273 */ 1274 static uint8_t 1275 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1276 { 1277 int i; 1278 uint32_t byte = 0; 1279 1280 /* 1281 * Enable use of auto EEPROM access so we can avoid 1282 * having to use the bitbang method. 1283 */ 1284 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1285 1286 /* Reset the EEPROM, load the clock period. */ 1287 CSR_WRITE_4(sc, BGE_EE_ADDR, 1288 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1289 DELAY(20); 1290 1291 /* Issue the read EEPROM command. */ 1292 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1293 1294 /* Wait for completion */ 1295 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1296 DELAY(10); 1297 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1298 break; 1299 } 1300 1301 if (i == BGE_TIMEOUT * 10) { 1302 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1303 return 1; 1304 } 1305 1306 /* Get result. */ 1307 byte = CSR_READ_4(sc, BGE_EE_DATA); 1308 1309 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1310 1311 return 0; 1312 } 1313 1314 /* 1315 * Read a sequence of bytes from the EEPROM. 1316 */ 1317 static int 1318 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1319 { 1320 int error = 0, i; 1321 uint8_t byte = 0; 1322 char *dest = destv; 1323 1324 for (i = 0; i < cnt; i++) { 1325 error = bge_eeprom_getbyte(sc, off + i, &byte); 1326 if (error) 1327 break; 1328 *(dest + i) = byte; 1329 } 1330 1331 return (error ? 1 : 0); 1332 } 1333 1334 static int 1335 bge_miibus_readreg(device_t dev, int phy, int reg) 1336 { 1337 struct bge_softc *sc = device_private(dev); 1338 uint32_t val; 1339 uint32_t autopoll; 1340 int i; 1341 1342 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1343 return 0; 1344 1345 /* Reading with autopolling on may trigger PCI errors */ 1346 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1347 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1348 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1349 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1350 DELAY(80); 1351 } 1352 1353 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1354 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1355 1356 for (i = 0; i < BGE_TIMEOUT; i++) { 1357 delay(10); 1358 val = CSR_READ_4(sc, BGE_MI_COMM); 1359 if (!(val & BGE_MICOMM_BUSY)) { 1360 DELAY(5); 1361 val = CSR_READ_4(sc, BGE_MI_COMM); 1362 break; 1363 } 1364 } 1365 1366 if (i == BGE_TIMEOUT) { 1367 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1368 val = 0; 1369 goto done; 1370 } 1371 1372 done: 1373 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1374 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1375 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1376 DELAY(80); 1377 } 1378 1379 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1380 1381 if (val & BGE_MICOMM_READFAIL) 1382 return 0; 1383 1384 return (val & 0xFFFF); 1385 } 1386 1387 static void 1388 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1389 { 1390 struct bge_softc *sc = device_private(dev); 1391 uint32_t autopoll; 1392 int i; 1393 1394 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1395 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1396 return; 1397 1398 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1399 return; 1400 1401 /* Reading with autopolling on may trigger PCI errors */ 1402 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1403 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1404 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1405 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1406 DELAY(80); 1407 } 1408 1409 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1410 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1411 1412 for (i = 0; i < BGE_TIMEOUT; i++) { 1413 delay(10); 1414 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1415 delay(5); 1416 CSR_READ_4(sc, BGE_MI_COMM); 1417 break; 1418 } 1419 } 1420 1421 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1422 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1423 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1424 delay(80); 1425 } 1426 1427 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1428 1429 if (i == BGE_TIMEOUT) 1430 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1431 } 1432 1433 static void 1434 bge_miibus_statchg(struct ifnet *ifp) 1435 { 1436 struct bge_softc *sc = ifp->if_softc; 1437 struct mii_data *mii = &sc->bge_mii; 1438 uint32_t mac_mode, rx_mode, tx_mode; 1439 1440 /* 1441 * Get flow control negotiation result. 1442 */ 1443 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1444 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1445 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1446 1447 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1448 mii->mii_media_status & IFM_ACTIVE && 1449 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1450 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1451 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1452 (!(mii->mii_media_status & IFM_ACTIVE) || 1453 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1454 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1455 1456 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1457 return; 1458 1459 /* Set the port mode (MII/GMII) to match the link speed. */ 1460 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1461 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1462 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1463 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1464 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1465 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1466 mac_mode |= BGE_PORTMODE_GMII; 1467 else 1468 mac_mode |= BGE_PORTMODE_MII; 1469 1470 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1471 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1472 if ((mii->mii_media_active & IFM_FDX) != 0) { 1473 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1474 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1475 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1476 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1477 } else 1478 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1479 1480 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1481 DELAY(40); 1482 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1483 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1484 } 1485 1486 /* 1487 * Update rx threshold levels to values in a particular slot 1488 * of the interrupt-mitigation table bge_rx_threshes. 1489 */ 1490 static void 1491 bge_set_thresh(struct ifnet *ifp, int lvl) 1492 { 1493 struct bge_softc *sc = ifp->if_softc; 1494 int s; 1495 1496 /* For now, just save the new Rx-intr thresholds and record 1497 * that a threshold update is pending. Updating the hardware 1498 * registers here (even at splhigh()) is observed to 1499 * occasionaly cause glitches where Rx-interrupts are not 1500 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1501 */ 1502 s = splnet(); 1503 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1504 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1505 sc->bge_pending_rxintr_change = 1; 1506 splx(s); 1507 } 1508 1509 1510 /* 1511 * Update Rx thresholds of all bge devices 1512 */ 1513 static void 1514 bge_update_all_threshes(int lvl) 1515 { 1516 struct ifnet *ifp; 1517 const char * const namebuf = "bge"; 1518 int namelen; 1519 1520 if (lvl < 0) 1521 lvl = 0; 1522 else if (lvl >= NBGE_RX_THRESH) 1523 lvl = NBGE_RX_THRESH - 1; 1524 1525 namelen = strlen(namebuf); 1526 /* 1527 * Now search all the interfaces for this name/number 1528 */ 1529 IFNET_FOREACH(ifp) { 1530 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1531 continue; 1532 /* We got a match: update if doing auto-threshold-tuning */ 1533 if (bge_auto_thresh) 1534 bge_set_thresh(ifp, lvl); 1535 } 1536 } 1537 1538 /* 1539 * Handle events that have triggered interrupts. 1540 */ 1541 static void 1542 bge_handle_events(struct bge_softc *sc) 1543 { 1544 1545 return; 1546 } 1547 1548 /* 1549 * Memory management for jumbo frames. 1550 */ 1551 1552 static int 1553 bge_alloc_jumbo_mem(struct bge_softc *sc) 1554 { 1555 char *ptr, *kva; 1556 bus_dma_segment_t seg; 1557 int i, rseg, state, error; 1558 struct bge_jpool_entry *entry; 1559 1560 state = error = 0; 1561 1562 /* Grab a big chunk o' storage. */ 1563 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1564 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1565 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1566 return ENOBUFS; 1567 } 1568 1569 state = 1; 1570 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1571 BUS_DMA_NOWAIT)) { 1572 aprint_error_dev(sc->bge_dev, 1573 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1574 error = ENOBUFS; 1575 goto out; 1576 } 1577 1578 state = 2; 1579 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1580 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1581 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1582 error = ENOBUFS; 1583 goto out; 1584 } 1585 1586 state = 3; 1587 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1588 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1589 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1590 error = ENOBUFS; 1591 goto out; 1592 } 1593 1594 state = 4; 1595 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1596 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1597 1598 SLIST_INIT(&sc->bge_jfree_listhead); 1599 SLIST_INIT(&sc->bge_jinuse_listhead); 1600 1601 /* 1602 * Now divide it up into 9K pieces and save the addresses 1603 * in an array. 1604 */ 1605 ptr = sc->bge_cdata.bge_jumbo_buf; 1606 for (i = 0; i < BGE_JSLOTS; i++) { 1607 sc->bge_cdata.bge_jslots[i] = ptr; 1608 ptr += BGE_JLEN; 1609 entry = malloc(sizeof(struct bge_jpool_entry), 1610 M_DEVBUF, M_NOWAIT); 1611 if (entry == NULL) { 1612 aprint_error_dev(sc->bge_dev, 1613 "no memory for jumbo buffer queue!\n"); 1614 error = ENOBUFS; 1615 goto out; 1616 } 1617 entry->slot = i; 1618 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1619 entry, jpool_entries); 1620 } 1621 out: 1622 if (error != 0) { 1623 switch (state) { 1624 case 4: 1625 bus_dmamap_unload(sc->bge_dmatag, 1626 sc->bge_cdata.bge_rx_jumbo_map); 1627 case 3: 1628 bus_dmamap_destroy(sc->bge_dmatag, 1629 sc->bge_cdata.bge_rx_jumbo_map); 1630 case 2: 1631 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1632 case 1: 1633 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1634 break; 1635 default: 1636 break; 1637 } 1638 } 1639 1640 return error; 1641 } 1642 1643 /* 1644 * Allocate a jumbo buffer. 1645 */ 1646 static void * 1647 bge_jalloc(struct bge_softc *sc) 1648 { 1649 struct bge_jpool_entry *entry; 1650 1651 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1652 1653 if (entry == NULL) { 1654 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1655 return NULL; 1656 } 1657 1658 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1659 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1660 return (sc->bge_cdata.bge_jslots[entry->slot]); 1661 } 1662 1663 /* 1664 * Release a jumbo buffer. 1665 */ 1666 static void 1667 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1668 { 1669 struct bge_jpool_entry *entry; 1670 struct bge_softc *sc; 1671 int i, s; 1672 1673 /* Extract the softc struct pointer. */ 1674 sc = (struct bge_softc *)arg; 1675 1676 if (sc == NULL) 1677 panic("bge_jfree: can't find softc pointer!"); 1678 1679 /* calculate the slot this buffer belongs to */ 1680 1681 i = ((char *)buf 1682 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1683 1684 if ((i < 0) || (i >= BGE_JSLOTS)) 1685 panic("bge_jfree: asked to free buffer that we don't manage!"); 1686 1687 s = splvm(); 1688 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1689 if (entry == NULL) 1690 panic("bge_jfree: buffer not in use!"); 1691 entry->slot = i; 1692 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1693 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1694 1695 if (__predict_true(m != NULL)) 1696 pool_cache_put(mb_cache, m); 1697 splx(s); 1698 } 1699 1700 1701 /* 1702 * Initialize a standard receive ring descriptor. 1703 */ 1704 static int 1705 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1706 bus_dmamap_t dmamap) 1707 { 1708 struct mbuf *m_new = NULL; 1709 struct bge_rx_bd *r; 1710 int error; 1711 1712 if (dmamap == NULL) { 1713 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1714 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1715 if (error != 0) 1716 return error; 1717 } 1718 1719 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1720 1721 if (m == NULL) { 1722 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1723 if (m_new == NULL) 1724 return ENOBUFS; 1725 1726 MCLGET(m_new, M_DONTWAIT); 1727 if (!(m_new->m_flags & M_EXT)) { 1728 m_freem(m_new); 1729 return ENOBUFS; 1730 } 1731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1732 1733 } else { 1734 m_new = m; 1735 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1736 m_new->m_data = m_new->m_ext.ext_buf; 1737 } 1738 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1739 m_adj(m_new, ETHER_ALIGN); 1740 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1741 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1742 m_freem(m_new); 1743 return ENOBUFS; 1744 } 1745 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1746 BUS_DMASYNC_PREREAD); 1747 1748 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1749 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1750 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1751 r->bge_flags = BGE_RXBDFLAG_END; 1752 r->bge_len = m_new->m_len; 1753 r->bge_idx = i; 1754 1755 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1756 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1757 i * sizeof (struct bge_rx_bd), 1758 sizeof (struct bge_rx_bd), 1759 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1760 1761 return 0; 1762 } 1763 1764 /* 1765 * Initialize a jumbo receive ring descriptor. This allocates 1766 * a jumbo buffer from the pool managed internally by the driver. 1767 */ 1768 static int 1769 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1770 { 1771 struct mbuf *m_new = NULL; 1772 struct bge_rx_bd *r; 1773 void *buf = NULL; 1774 1775 if (m == NULL) { 1776 1777 /* Allocate the mbuf. */ 1778 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1779 if (m_new == NULL) 1780 return ENOBUFS; 1781 1782 /* Allocate the jumbo buffer */ 1783 buf = bge_jalloc(sc); 1784 if (buf == NULL) { 1785 m_freem(m_new); 1786 aprint_error_dev(sc->bge_dev, 1787 "jumbo allocation failed -- packet dropped!\n"); 1788 return ENOBUFS; 1789 } 1790 1791 /* Attach the buffer to the mbuf. */ 1792 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1793 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1794 bge_jfree, sc); 1795 m_new->m_flags |= M_EXT_RW; 1796 } else { 1797 m_new = m; 1798 buf = m_new->m_data = m_new->m_ext.ext_buf; 1799 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1800 } 1801 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1802 m_adj(m_new, ETHER_ALIGN); 1803 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1804 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1805 BUS_DMASYNC_PREREAD); 1806 /* Set up the descriptor. */ 1807 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1808 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1809 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1810 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1811 r->bge_len = m_new->m_len; 1812 r->bge_idx = i; 1813 1814 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1815 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1816 i * sizeof (struct bge_rx_bd), 1817 sizeof (struct bge_rx_bd), 1818 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1819 1820 return 0; 1821 } 1822 1823 /* 1824 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1825 * that's 1MB or memory, which is a lot. For now, we fill only the first 1826 * 256 ring entries and hope that our CPU is fast enough to keep up with 1827 * the NIC. 1828 */ 1829 static int 1830 bge_init_rx_ring_std(struct bge_softc *sc) 1831 { 1832 int i; 1833 1834 if (sc->bge_flags & BGEF_RXRING_VALID) 1835 return 0; 1836 1837 for (i = 0; i < BGE_SSLOTS; i++) { 1838 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1839 return ENOBUFS; 1840 } 1841 1842 sc->bge_std = i - 1; 1843 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1844 1845 sc->bge_flags |= BGEF_RXRING_VALID; 1846 1847 return 0; 1848 } 1849 1850 static void 1851 bge_free_rx_ring_std(struct bge_softc *sc) 1852 { 1853 int i; 1854 1855 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1856 return; 1857 1858 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1859 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1860 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1861 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1862 bus_dmamap_destroy(sc->bge_dmatag, 1863 sc->bge_cdata.bge_rx_std_map[i]); 1864 } 1865 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1866 sizeof(struct bge_rx_bd)); 1867 } 1868 1869 sc->bge_flags &= ~BGEF_RXRING_VALID; 1870 } 1871 1872 static int 1873 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1874 { 1875 int i; 1876 volatile struct bge_rcb *rcb; 1877 1878 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1879 return 0; 1880 1881 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1882 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1883 return ENOBUFS; 1884 } 1885 1886 sc->bge_jumbo = i - 1; 1887 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1888 1889 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1890 rcb->bge_maxlen_flags = 0; 1891 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1892 1893 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1894 1895 return 0; 1896 } 1897 1898 static void 1899 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1900 { 1901 int i; 1902 1903 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1904 return; 1905 1906 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1907 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1908 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1909 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1910 } 1911 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1912 sizeof(struct bge_rx_bd)); 1913 } 1914 1915 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1916 } 1917 1918 static void 1919 bge_free_tx_ring(struct bge_softc *sc) 1920 { 1921 int i; 1922 struct txdmamap_pool_entry *dma; 1923 1924 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1925 return; 1926 1927 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1928 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1929 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1930 sc->bge_cdata.bge_tx_chain[i] = NULL; 1931 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1932 link); 1933 sc->txdma[i] = 0; 1934 } 1935 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1936 sizeof(struct bge_tx_bd)); 1937 } 1938 1939 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1940 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1941 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1942 free(dma, M_DEVBUF); 1943 } 1944 1945 sc->bge_flags &= ~BGEF_TXRING_VALID; 1946 } 1947 1948 static int 1949 bge_init_tx_ring(struct bge_softc *sc) 1950 { 1951 struct ifnet *ifp = &sc->ethercom.ec_if; 1952 int i; 1953 bus_dmamap_t dmamap; 1954 bus_size_t maxsegsz; 1955 struct txdmamap_pool_entry *dma; 1956 1957 if (sc->bge_flags & BGEF_TXRING_VALID) 1958 return 0; 1959 1960 sc->bge_txcnt = 0; 1961 sc->bge_tx_saved_considx = 0; 1962 1963 /* Initialize transmit producer index for host-memory send ring. */ 1964 sc->bge_tx_prodidx = 0; 1965 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1966 /* 5700 b2 errata */ 1967 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1968 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1969 1970 /* NIC-memory send ring not used; initialize to zero. */ 1971 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1972 /* 5700 b2 errata */ 1973 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1974 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1975 1976 /* Limit DMA segment size for some chips */ 1977 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1978 (ifp->if_mtu <= ETHERMTU)) 1979 maxsegsz = 2048; 1980 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1981 maxsegsz = 4096; 1982 else 1983 maxsegsz = ETHER_MAX_LEN_JUMBO; 1984 SLIST_INIT(&sc->txdma_list); 1985 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1986 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1987 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, 1988 &dmamap)) 1989 return ENOBUFS; 1990 if (dmamap == NULL) 1991 panic("dmamap NULL in bge_init_tx_ring"); 1992 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1993 if (dma == NULL) { 1994 aprint_error_dev(sc->bge_dev, 1995 "can't alloc txdmamap_pool_entry\n"); 1996 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1997 return ENOMEM; 1998 } 1999 dma->dmamap = dmamap; 2000 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2001 } 2002 2003 sc->bge_flags |= BGEF_TXRING_VALID; 2004 2005 return 0; 2006 } 2007 2008 static void 2009 bge_setmulti(struct bge_softc *sc) 2010 { 2011 struct ethercom *ac = &sc->ethercom; 2012 struct ifnet *ifp = &ac->ec_if; 2013 struct ether_multi *enm; 2014 struct ether_multistep step; 2015 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2016 uint32_t h; 2017 int i; 2018 2019 if (ifp->if_flags & IFF_PROMISC) 2020 goto allmulti; 2021 2022 /* Now program new ones. */ 2023 ETHER_FIRST_MULTI(step, ac, enm); 2024 while (enm != NULL) { 2025 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2026 /* 2027 * We must listen to a range of multicast addresses. 2028 * For now, just accept all multicasts, rather than 2029 * trying to set only those filter bits needed to match 2030 * the range. (At this time, the only use of address 2031 * ranges is for IP multicast routing, for which the 2032 * range is big enough to require all bits set.) 2033 */ 2034 goto allmulti; 2035 } 2036 2037 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2038 2039 /* Just want the 7 least-significant bits. */ 2040 h &= 0x7f; 2041 2042 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2043 ETHER_NEXT_MULTI(step, enm); 2044 } 2045 2046 ifp->if_flags &= ~IFF_ALLMULTI; 2047 goto setit; 2048 2049 allmulti: 2050 ifp->if_flags |= IFF_ALLMULTI; 2051 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2052 2053 setit: 2054 for (i = 0; i < 4; i++) 2055 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2056 } 2057 2058 static void 2059 bge_sig_pre_reset(struct bge_softc *sc, int type) 2060 { 2061 2062 /* 2063 * Some chips don't like this so only do this if ASF is enabled 2064 */ 2065 if (sc->bge_asf_mode) 2066 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2067 2068 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2069 switch (type) { 2070 case BGE_RESET_START: 2071 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2072 BGE_FW_DRV_STATE_START); 2073 break; 2074 case BGE_RESET_SHUTDOWN: 2075 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2076 BGE_FW_DRV_STATE_UNLOAD); 2077 break; 2078 case BGE_RESET_SUSPEND: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_SUSPEND); 2081 break; 2082 } 2083 } 2084 2085 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2086 bge_ape_driver_state_change(sc, type); 2087 } 2088 2089 static void 2090 bge_sig_post_reset(struct bge_softc *sc, int type) 2091 { 2092 2093 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2094 switch (type) { 2095 case BGE_RESET_START: 2096 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2097 BGE_FW_DRV_STATE_START_DONE); 2098 /* START DONE */ 2099 break; 2100 case BGE_RESET_SHUTDOWN: 2101 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2102 BGE_FW_DRV_STATE_UNLOAD_DONE); 2103 break; 2104 } 2105 } 2106 2107 if (type == BGE_RESET_SHUTDOWN) 2108 bge_ape_driver_state_change(sc, type); 2109 } 2110 2111 static void 2112 bge_sig_legacy(struct bge_softc *sc, int type) 2113 { 2114 2115 if (sc->bge_asf_mode) { 2116 switch (type) { 2117 case BGE_RESET_START: 2118 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2119 BGE_FW_DRV_STATE_START); 2120 break; 2121 case BGE_RESET_SHUTDOWN: 2122 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2123 BGE_FW_DRV_STATE_UNLOAD); 2124 break; 2125 } 2126 } 2127 } 2128 2129 static void 2130 bge_wait_for_event_ack(struct bge_softc *sc) 2131 { 2132 int i; 2133 2134 /* wait up to 2500usec */ 2135 for (i = 0; i < 250; i++) { 2136 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2137 BGE_RX_CPU_DRV_EVENT)) 2138 break; 2139 DELAY(10); 2140 } 2141 } 2142 2143 static void 2144 bge_stop_fw(struct bge_softc *sc) 2145 { 2146 2147 if (sc->bge_asf_mode) { 2148 bge_wait_for_event_ack(sc); 2149 2150 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2151 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2152 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2153 2154 bge_wait_for_event_ack(sc); 2155 } 2156 } 2157 2158 static int 2159 bge_poll_fw(struct bge_softc *sc) 2160 { 2161 uint32_t val; 2162 int i; 2163 2164 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2165 for (i = 0; i < BGE_TIMEOUT; i++) { 2166 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2167 if (val & BGE_VCPU_STATUS_INIT_DONE) 2168 break; 2169 DELAY(100); 2170 } 2171 if (i >= BGE_TIMEOUT) { 2172 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2173 return -1; 2174 } 2175 } else { 2176 /* 2177 * Poll the value location we just wrote until 2178 * we see the 1's complement of the magic number. 2179 * This indicates that the firmware initialization 2180 * is complete. 2181 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2182 */ 2183 for (i = 0; i < BGE_TIMEOUT; i++) { 2184 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2185 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2186 break; 2187 DELAY(10); 2188 } 2189 2190 if ((i >= BGE_TIMEOUT) 2191 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2192 aprint_error_dev(sc->bge_dev, 2193 "firmware handshake timed out, val = %x\n", val); 2194 return -1; 2195 } 2196 } 2197 2198 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2199 /* tg3 says we have to wait extra time */ 2200 delay(10 * 1000); 2201 } 2202 2203 return 0; 2204 } 2205 2206 int 2207 bge_phy_addr(struct bge_softc *sc) 2208 { 2209 struct pci_attach_args *pa = &(sc->bge_pa); 2210 int phy_addr = 1; 2211 2212 /* 2213 * PHY address mapping for various devices. 2214 * 2215 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2216 * ---------+-------+-------+-------+-------+ 2217 * BCM57XX | 1 | X | X | X | 2218 * BCM5704 | 1 | X | 1 | X | 2219 * BCM5717 | 1 | 8 | 2 | 9 | 2220 * BCM5719 | 1 | 8 | 2 | 9 | 2221 * BCM5720 | 1 | 8 | 2 | 9 | 2222 * 2223 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2224 * ---------+-------+-------+-------+-------+ 2225 * BCM57XX | X | X | X | X | 2226 * BCM5704 | X | X | X | X | 2227 * BCM5717 | X | X | X | X | 2228 * BCM5719 | 3 | 10 | 4 | 11 | 2229 * BCM5720 | X | X | X | X | 2230 * 2231 * Other addresses may respond but they are not 2232 * IEEE compliant PHYs and should be ignored. 2233 */ 2234 switch (BGE_ASICREV(sc->bge_chipid)) { 2235 case BGE_ASICREV_BCM5717: 2236 case BGE_ASICREV_BCM5719: 2237 case BGE_ASICREV_BCM5720: 2238 phy_addr = pa->pa_function; 2239 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2240 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2241 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2242 } else { 2243 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2244 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2245 } 2246 } 2247 2248 return phy_addr; 2249 } 2250 2251 /* 2252 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2253 * self-test results. 2254 */ 2255 static int 2256 bge_chipinit(struct bge_softc *sc) 2257 { 2258 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2259 int i; 2260 2261 /* Set endianness before we access any non-PCI registers. */ 2262 misc_ctl = BGE_INIT; 2263 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2264 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2265 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2266 misc_ctl); 2267 2268 /* 2269 * Clear the MAC statistics block in the NIC's 2270 * internal memory. 2271 */ 2272 for (i = BGE_STATS_BLOCK; 2273 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2274 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2275 2276 for (i = BGE_STATUS_BLOCK; 2277 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2278 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2279 2280 /* 5717 workaround from tg3 */ 2281 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2282 /* Save */ 2283 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2284 2285 /* Temporary modify MODE_CTL to control TLP */ 2286 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2287 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2288 2289 /* Control TLP */ 2290 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2291 BGE_TLP_PHYCTL1); 2292 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2293 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2294 2295 /* Restore */ 2296 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2297 } 2298 2299 if (BGE_IS_57765_FAMILY(sc)) { 2300 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2301 /* Save */ 2302 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2303 2304 /* Temporary modify MODE_CTL to control TLP */ 2305 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2306 CSR_WRITE_4(sc, BGE_MODE_CTL, 2307 reg | BGE_MODECTL_PCIE_TLPADDR1); 2308 2309 /* Control TLP */ 2310 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2311 BGE_TLP_PHYCTL5); 2312 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2313 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2314 2315 /* Restore */ 2316 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2317 } 2318 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2319 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2320 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2321 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2322 2323 /* Save */ 2324 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2325 2326 /* Temporary modify MODE_CTL to control TLP */ 2327 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2328 CSR_WRITE_4(sc, BGE_MODE_CTL, 2329 reg | BGE_MODECTL_PCIE_TLPADDR0); 2330 2331 /* Control TLP */ 2332 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2333 BGE_TLP_FTSMAX); 2334 reg &= ~BGE_TLP_FTSMAX_MSK; 2335 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2336 reg | BGE_TLP_FTSMAX_VAL); 2337 2338 /* Restore */ 2339 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2340 } 2341 2342 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2343 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2344 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2345 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2346 } 2347 2348 /* Set up the PCI DMA control register. */ 2349 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2350 if (sc->bge_flags & BGEF_PCIE) { 2351 /* Read watermark not used, 128 bytes for write. */ 2352 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2353 device_xname(sc->bge_dev))); 2354 if (sc->bge_mps >= 256) 2355 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2356 else 2357 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2358 } else if (sc->bge_flags & BGEF_PCIX) { 2359 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2360 device_xname(sc->bge_dev))); 2361 /* PCI-X bus */ 2362 if (BGE_IS_5714_FAMILY(sc)) { 2363 /* 256 bytes for read and write. */ 2364 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2365 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2366 2367 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2368 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2369 else 2370 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2371 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2372 /* 2373 * In the BCM5703, the DMA read watermark should 2374 * be set to less than or equal to the maximum 2375 * memory read byte count of the PCI-X command 2376 * register. 2377 */ 2378 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2379 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2380 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2381 /* 1536 bytes for read, 384 bytes for write. */ 2382 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2383 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2384 } else { 2385 /* 384 bytes for read and write. */ 2386 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2387 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2388 (0x0F); 2389 } 2390 2391 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2392 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2393 uint32_t tmp; 2394 2395 /* Set ONEDMA_ATONCE for hardware workaround. */ 2396 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2397 if (tmp == 6 || tmp == 7) 2398 dma_rw_ctl |= 2399 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2400 2401 /* Set PCI-X DMA write workaround. */ 2402 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2403 } 2404 } else { 2405 /* Conventional PCI bus: 256 bytes for read and write. */ 2406 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2407 device_xname(sc->bge_dev))); 2408 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2409 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2410 2411 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2412 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2413 dma_rw_ctl |= 0x0F; 2414 } 2415 2416 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2417 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2418 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2419 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2420 2421 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2422 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2423 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2424 2425 if (BGE_IS_57765_PLUS(sc)) { 2426 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2427 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2428 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2429 2430 /* 2431 * Enable HW workaround for controllers that misinterpret 2432 * a status tag update and leave interrupts permanently 2433 * disabled. 2434 */ 2435 if (!BGE_IS_57765_FAMILY(sc) && 2436 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2437 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2438 } 2439 2440 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2441 dma_rw_ctl); 2442 2443 /* 2444 * Set up general mode register. 2445 */ 2446 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2447 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2448 /* Retain Host-2-BMC settings written by APE firmware. */ 2449 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2450 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2451 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2452 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2453 } 2454 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2455 BGE_MODECTL_TX_NO_PHDR_CSUM; 2456 2457 /* 2458 * BCM5701 B5 have a bug causing data corruption when using 2459 * 64-bit DMA reads, which can be terminated early and then 2460 * completed later as 32-bit accesses, in combination with 2461 * certain bridges. 2462 */ 2463 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2464 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2465 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2466 2467 /* 2468 * Tell the firmware the driver is running 2469 */ 2470 if (sc->bge_asf_mode & ASF_STACKUP) 2471 mode_ctl |= BGE_MODECTL_STACKUP; 2472 2473 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2474 2475 /* 2476 * Disable memory write invalidate. Apparently it is not supported 2477 * properly by these devices. 2478 */ 2479 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2480 PCI_COMMAND_INVALIDATE_ENABLE); 2481 2482 #ifdef __brokenalpha__ 2483 /* 2484 * Must insure that we do not cross an 8K (bytes) boundary 2485 * for DMA reads. Our highest limit is 1K bytes. This is a 2486 * restriction on some ALPHA platforms with early revision 2487 * 21174 PCI chipsets, such as the AlphaPC 164lx 2488 */ 2489 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2490 #endif 2491 2492 /* Set the timer prescaler (always 66MHz) */ 2493 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2494 2495 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2496 DELAY(40); /* XXX */ 2497 2498 /* Put PHY into ready state */ 2499 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2500 DELAY(40); 2501 } 2502 2503 return 0; 2504 } 2505 2506 static int 2507 bge_blockinit(struct bge_softc *sc) 2508 { 2509 volatile struct bge_rcb *rcb; 2510 bus_size_t rcb_addr; 2511 struct ifnet *ifp = &sc->ethercom.ec_if; 2512 bge_hostaddr taddr; 2513 uint32_t dmactl, mimode, val; 2514 int i, limit; 2515 2516 /* 2517 * Initialize the memory window pointer register so that 2518 * we can access the first 32K of internal NIC RAM. This will 2519 * allow us to set up the TX send ring RCBs and the RX return 2520 * ring RCBs, plus other things which live in NIC memory. 2521 */ 2522 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2523 2524 if (!BGE_IS_5705_PLUS(sc)) { 2525 /* 57XX step 33 */ 2526 /* Configure mbuf memory pool */ 2527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2528 BGE_BUFFPOOL_1); 2529 2530 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2531 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2532 else 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2534 2535 /* 57XX step 34 */ 2536 /* Configure DMA resource pool */ 2537 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2538 BGE_DMA_DESCRIPTORS); 2539 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2540 } 2541 2542 /* 5718 step 11, 57XX step 35 */ 2543 /* 2544 * Configure mbuf pool watermarks. New broadcom docs strongly 2545 * recommend these. 2546 */ 2547 if (BGE_IS_5717_PLUS(sc)) { 2548 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2549 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2550 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2551 } else if (BGE_IS_5705_PLUS(sc)) { 2552 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2553 2554 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2555 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2556 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2557 } else { 2558 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2559 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2560 } 2561 } else { 2562 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2563 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2564 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2565 } 2566 2567 /* 57XX step 36 */ 2568 /* Configure DMA resource watermarks */ 2569 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2570 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2571 2572 /* 5718 step 13, 57XX step 38 */ 2573 /* Enable buffer manager */ 2574 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2575 /* 2576 * Change the arbitration algorithm of TXMBUF read request to 2577 * round-robin instead of priority based for BCM5719. When 2578 * TXFIFO is almost empty, RDMA will hold its request until 2579 * TXFIFO is not almost empty. 2580 */ 2581 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2582 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2583 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2584 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2585 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2586 val |= BGE_BMANMODE_LOMBUF_ATTN; 2587 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2588 2589 /* 57XX step 39 */ 2590 /* Poll for buffer manager start indication */ 2591 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2592 DELAY(10); 2593 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2594 break; 2595 } 2596 2597 if (i == BGE_TIMEOUT * 2) { 2598 aprint_error_dev(sc->bge_dev, 2599 "buffer manager failed to start\n"); 2600 return ENXIO; 2601 } 2602 2603 /* 57XX step 40 */ 2604 /* Enable flow-through queues */ 2605 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2606 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2607 2608 /* Wait until queue initialization is complete */ 2609 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2610 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2611 break; 2612 DELAY(10); 2613 } 2614 2615 if (i == BGE_TIMEOUT * 2) { 2616 aprint_error_dev(sc->bge_dev, 2617 "flow-through queue init failed\n"); 2618 return ENXIO; 2619 } 2620 2621 /* 2622 * Summary of rings supported by the controller: 2623 * 2624 * Standard Receive Producer Ring 2625 * - This ring is used to feed receive buffers for "standard" 2626 * sized frames (typically 1536 bytes) to the controller. 2627 * 2628 * Jumbo Receive Producer Ring 2629 * - This ring is used to feed receive buffers for jumbo sized 2630 * frames (i.e. anything bigger than the "standard" frames) 2631 * to the controller. 2632 * 2633 * Mini Receive Producer Ring 2634 * - This ring is used to feed receive buffers for "mini" 2635 * sized frames to the controller. 2636 * - This feature required external memory for the controller 2637 * but was never used in a production system. Should always 2638 * be disabled. 2639 * 2640 * Receive Return Ring 2641 * - After the controller has placed an incoming frame into a 2642 * receive buffer that buffer is moved into a receive return 2643 * ring. The driver is then responsible to passing the 2644 * buffer up to the stack. Many versions of the controller 2645 * support multiple RR rings. 2646 * 2647 * Send Ring 2648 * - This ring is used for outgoing frames. Many versions of 2649 * the controller support multiple send rings. 2650 */ 2651 2652 /* 5718 step 15, 57XX step 41 */ 2653 /* Initialize the standard RX ring control block */ 2654 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2655 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2656 /* 5718 step 16 */ 2657 if (BGE_IS_57765_PLUS(sc)) { 2658 /* 2659 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2660 * Bits 15-2 : Maximum RX frame size 2661 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2662 * Bit 0 : Reserved 2663 */ 2664 rcb->bge_maxlen_flags = 2665 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2666 } else if (BGE_IS_5705_PLUS(sc)) { 2667 /* 2668 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2669 * Bits 15-2 : Reserved (should be 0) 2670 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2671 * Bit 0 : Reserved 2672 */ 2673 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2674 } else { 2675 /* 2676 * Ring size is always XXX entries 2677 * Bits 31-16: Maximum RX frame size 2678 * Bits 15-2 : Reserved (should be 0) 2679 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2680 * Bit 0 : Reserved 2681 */ 2682 rcb->bge_maxlen_flags = 2683 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2684 } 2685 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2686 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2687 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2688 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2689 else 2690 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2691 /* Write the standard receive producer ring control block. */ 2692 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2693 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2694 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2695 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2696 2697 /* Reset the standard receive producer ring producer index. */ 2698 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2699 2700 /* 57XX step 42 */ 2701 /* 2702 * Initialize the jumbo RX ring control block 2703 * We set the 'ring disabled' bit in the flags 2704 * field until we're actually ready to start 2705 * using this ring (i.e. once we set the MTU 2706 * high enough to require it). 2707 */ 2708 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2709 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2710 BGE_HOSTADDR(rcb->bge_hostaddr, 2711 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2712 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2713 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2714 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2715 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2716 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2717 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2718 else 2719 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2720 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2721 rcb->bge_hostaddr.bge_addr_hi); 2722 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2723 rcb->bge_hostaddr.bge_addr_lo); 2724 /* Program the jumbo receive producer ring RCB parameters. */ 2725 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2726 rcb->bge_maxlen_flags); 2727 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2728 /* Reset the jumbo receive producer ring producer index. */ 2729 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2730 } 2731 2732 /* 57XX step 43 */ 2733 /* Disable the mini receive producer ring RCB. */ 2734 if (BGE_IS_5700_FAMILY(sc)) { 2735 /* Set up dummy disabled mini ring RCB */ 2736 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2737 rcb->bge_maxlen_flags = 2738 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2739 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2740 rcb->bge_maxlen_flags); 2741 /* Reset the mini receive producer ring producer index. */ 2742 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2743 2744 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2745 offsetof(struct bge_ring_data, bge_info), 2746 sizeof (struct bge_gib), 2747 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2748 } 2749 2750 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2751 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2752 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2753 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2754 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2755 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2756 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2757 } 2758 /* 5718 step 14, 57XX step 44 */ 2759 /* 2760 * The BD ring replenish thresholds control how often the 2761 * hardware fetches new BD's from the producer rings in host 2762 * memory. Setting the value too low on a busy system can 2763 * starve the hardware and recue the throughpout. 2764 * 2765 * Set the BD ring replenish thresholds. The recommended 2766 * values are 1/8th the number of descriptors allocated to 2767 * each ring, but since we try to avoid filling the entire 2768 * ring we set these to the minimal value of 8. This needs to 2769 * be done on several of the supported chip revisions anyway, 2770 * to work around HW bugs. 2771 */ 2772 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2773 if (BGE_IS_JUMBO_CAPABLE(sc)) 2774 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2775 2776 /* 5718 step 18 */ 2777 if (BGE_IS_5717_PLUS(sc)) { 2778 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2779 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2780 } 2781 2782 /* 57XX step 45 */ 2783 /* 2784 * Disable all send rings by setting the 'ring disabled' bit 2785 * in the flags field of all the TX send ring control blocks, 2786 * located in NIC memory. 2787 */ 2788 if (BGE_IS_5700_FAMILY(sc)) { 2789 /* 5700 to 5704 had 16 send rings. */ 2790 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2791 } else if (BGE_IS_5717_PLUS(sc)) { 2792 limit = BGE_TX_RINGS_5717_MAX; 2793 } else if (BGE_IS_57765_FAMILY(sc)) { 2794 limit = BGE_TX_RINGS_57765_MAX; 2795 } else 2796 limit = 1; 2797 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2798 for (i = 0; i < limit; i++) { 2799 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2800 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2801 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2802 rcb_addr += sizeof(struct bge_rcb); 2803 } 2804 2805 /* 57XX step 46 and 47 */ 2806 /* Configure send ring RCB 0 (we use only the first ring) */ 2807 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2808 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2809 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2810 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2811 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2812 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2813 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2814 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2815 else 2816 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2817 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2818 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2819 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2820 2821 /* 57XX step 48 */ 2822 /* 2823 * Disable all receive return rings by setting the 2824 * 'ring diabled' bit in the flags field of all the receive 2825 * return ring control blocks, located in NIC memory. 2826 */ 2827 if (BGE_IS_5717_PLUS(sc)) { 2828 /* Should be 17, use 16 until we get an SRAM map. */ 2829 limit = 16; 2830 } else if (BGE_IS_5700_FAMILY(sc)) 2831 limit = BGE_RX_RINGS_MAX; 2832 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2833 BGE_IS_57765_FAMILY(sc)) 2834 limit = 4; 2835 else 2836 limit = 1; 2837 /* Disable all receive return rings */ 2838 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2839 for (i = 0; i < limit; i++) { 2840 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2841 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2842 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2843 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2844 BGE_RCB_FLAG_RING_DISABLED)); 2845 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2846 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2847 (i * (sizeof(uint64_t))), 0); 2848 rcb_addr += sizeof(struct bge_rcb); 2849 } 2850 2851 /* 57XX step 49 */ 2852 /* 2853 * Set up receive return ring 0. Note that the NIC address 2854 * for RX return rings is 0x0. The return rings live entirely 2855 * within the host, so the nicaddr field in the RCB isn't used. 2856 */ 2857 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2858 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2859 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2860 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2861 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2862 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2863 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2864 2865 /* 5718 step 24, 57XX step 53 */ 2866 /* Set random backoff seed for TX */ 2867 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2868 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2869 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2870 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2871 BGE_TX_BACKOFF_SEED_MASK); 2872 2873 /* 5718 step 26, 57XX step 55 */ 2874 /* Set inter-packet gap */ 2875 val = 0x2620; 2876 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2877 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2878 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2879 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2880 2881 /* 5718 step 27, 57XX step 56 */ 2882 /* 2883 * Specify which ring to use for packets that don't match 2884 * any RX rules. 2885 */ 2886 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2887 2888 /* 5718 step 28, 57XX step 57 */ 2889 /* 2890 * Configure number of RX lists. One interrupt distribution 2891 * list, sixteen active lists, one bad frames class. 2892 */ 2893 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2894 2895 /* 5718 step 29, 57XX step 58 */ 2896 /* Inialize RX list placement stats mask. */ 2897 if (BGE_IS_575X_PLUS(sc)) { 2898 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2899 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2900 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2901 } else 2902 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2903 2904 /* 5718 step 30, 57XX step 59 */ 2905 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2906 2907 /* 5718 step 33, 57XX step 62 */ 2908 /* Disable host coalescing until we get it set up */ 2909 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2910 2911 /* 5718 step 34, 57XX step 63 */ 2912 /* Poll to make sure it's shut down. */ 2913 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2914 DELAY(10); 2915 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2916 break; 2917 } 2918 2919 if (i == BGE_TIMEOUT * 2) { 2920 aprint_error_dev(sc->bge_dev, 2921 "host coalescing engine failed to idle\n"); 2922 return ENXIO; 2923 } 2924 2925 /* 5718 step 35, 36, 37 */ 2926 /* Set up host coalescing defaults */ 2927 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2928 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2929 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2930 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2931 if (!(BGE_IS_5705_PLUS(sc))) { 2932 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2933 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2934 } 2935 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2936 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2937 2938 /* Set up address of statistics block */ 2939 if (BGE_IS_5700_FAMILY(sc)) { 2940 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2941 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2942 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2943 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2944 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2945 } 2946 2947 /* 5718 step 38 */ 2948 /* Set up address of status block */ 2949 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2950 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2951 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2952 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2953 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2954 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2955 2956 /* Set up status block size. */ 2957 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2958 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2959 val = BGE_STATBLKSZ_FULL; 2960 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2961 } else { 2962 val = BGE_STATBLKSZ_32BYTE; 2963 bzero(&sc->bge_rdata->bge_status_block, 32); 2964 } 2965 2966 /* 5718 step 39, 57XX step 73 */ 2967 /* Turn on host coalescing state machine */ 2968 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2969 2970 /* 5718 step 40, 57XX step 74 */ 2971 /* Turn on RX BD completion state machine and enable attentions */ 2972 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2973 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2974 2975 /* 5718 step 41, 57XX step 75 */ 2976 /* Turn on RX list placement state machine */ 2977 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2978 2979 /* 57XX step 76 */ 2980 /* Turn on RX list selector state machine. */ 2981 if (!(BGE_IS_5705_PLUS(sc))) 2982 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2983 2984 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2985 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2986 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2987 BGE_MACMODE_FRMHDR_DMA_ENB; 2988 2989 if (sc->bge_flags & BGEF_FIBER_TBI) 2990 val |= BGE_PORTMODE_TBI; 2991 else if (sc->bge_flags & BGEF_FIBER_MII) 2992 val |= BGE_PORTMODE_GMII; 2993 else 2994 val |= BGE_PORTMODE_MII; 2995 2996 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2997 /* Allow APE to send/receive frames. */ 2998 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2999 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3000 3001 /* Turn on DMA, clear stats */ 3002 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3003 /* 5718 step 44 */ 3004 DELAY(40); 3005 3006 /* 5718 step 45, 57XX step 79 */ 3007 /* Set misc. local control, enable interrupts on attentions */ 3008 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3009 if (BGE_IS_5717_PLUS(sc)) { 3010 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3011 /* 5718 step 46 */ 3012 DELAY(100); 3013 } 3014 3015 /* 57XX step 81 */ 3016 /* Turn on DMA completion state machine */ 3017 if (!(BGE_IS_5705_PLUS(sc))) 3018 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3019 3020 /* 5718 step 47, 57XX step 82 */ 3021 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3022 3023 /* 5718 step 48 */ 3024 /* Enable host coalescing bug fix. */ 3025 if (BGE_IS_5755_PLUS(sc)) 3026 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3027 3028 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3029 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3030 3031 /* Turn on write DMA state machine */ 3032 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3033 /* 5718 step 49 */ 3034 DELAY(40); 3035 3036 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3037 3038 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3039 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3040 3041 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3042 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3043 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3044 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3045 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3046 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3047 3048 if (sc->bge_flags & BGEF_PCIE) 3049 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3050 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3051 if (ifp->if_mtu <= ETHERMTU) 3052 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3053 } 3054 if (sc->bge_flags & BGEF_TSO) 3055 val |= BGE_RDMAMODE_TSO4_ENABLE; 3056 3057 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3058 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3059 BGE_RDMAMODE_H2BNC_VLAN_DET; 3060 /* 3061 * Allow multiple outstanding read requests from 3062 * non-LSO read DMA engine. 3063 */ 3064 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3065 } 3066 3067 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3068 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3069 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3070 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3071 BGE_IS_57765_PLUS(sc)) { 3072 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3073 /* 3074 * Adjust tx margin to prevent TX data corruption and 3075 * fix internal FIFO overflow. 3076 */ 3077 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3078 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3079 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3080 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3081 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3082 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3083 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3084 } 3085 /* 3086 * Enable fix for read DMA FIFO overruns. 3087 * The fix is to limit the number of RX BDs 3088 * the hardware would fetch at a fime. 3089 */ 3090 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3091 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3092 } 3093 3094 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3095 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3096 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3097 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3098 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3099 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3100 /* 3101 * Allow 4KB burst length reads for non-LSO frames. 3102 * Enable 512B burst length reads for buffer descriptors. 3103 */ 3104 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3105 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3106 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3107 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3108 } 3109 3110 /* Turn on read DMA state machine */ 3111 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3112 /* 5718 step 52 */ 3113 delay(40); 3114 3115 /* 5718 step 56, 57XX step 84 */ 3116 /* Turn on RX data completion state machine */ 3117 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3118 3119 /* Turn on RX data and RX BD initiator state machine */ 3120 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3121 3122 /* 57XX step 85 */ 3123 /* Turn on Mbuf cluster free state machine */ 3124 if (!BGE_IS_5705_PLUS(sc)) 3125 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3126 3127 /* 5718 step 57, 57XX step 86 */ 3128 /* Turn on send data completion state machine */ 3129 val = BGE_SDCMODE_ENABLE; 3130 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3131 val |= BGE_SDCMODE_CDELAY; 3132 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3133 3134 /* 5718 step 58 */ 3135 /* Turn on send BD completion state machine */ 3136 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3137 3138 /* 57XX step 88 */ 3139 /* Turn on RX BD initiator state machine */ 3140 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3141 3142 /* 5718 step 60, 57XX step 90 */ 3143 /* Turn on send data initiator state machine */ 3144 if (sc->bge_flags & BGEF_TSO) { 3145 /* XXX: magic value from Linux driver */ 3146 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3147 BGE_SDIMODE_HW_LSO_PRE_DMA); 3148 } else 3149 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3150 3151 /* 5718 step 61, 57XX step 91 */ 3152 /* Turn on send BD initiator state machine */ 3153 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3154 3155 /* 5718 step 62, 57XX step 92 */ 3156 /* Turn on send BD selector state machine */ 3157 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3158 3159 /* 5718 step 31, 57XX step 60 */ 3160 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3161 /* 5718 step 32, 57XX step 61 */ 3162 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3163 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3164 3165 /* ack/clear link change events */ 3166 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3167 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3168 BGE_MACSTAT_LINK_CHANGED); 3169 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3170 3171 /* 3172 * Enable attention when the link has changed state for 3173 * devices that use auto polling. 3174 */ 3175 if (sc->bge_flags & BGEF_FIBER_TBI) { 3176 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3177 } else { 3178 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3179 mimode = BGE_MIMODE_500KHZ_CONST; 3180 else 3181 mimode = BGE_MIMODE_BASE; 3182 /* 5718 step 68. 5718 step 69 (optionally). */ 3183 if (BGE_IS_5700_FAMILY(sc) || 3184 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3185 mimode |= BGE_MIMODE_AUTOPOLL; 3186 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3187 } 3188 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3189 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3190 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3191 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3192 BGE_EVTENB_MI_INTERRUPT); 3193 } 3194 3195 /* 3196 * Clear any pending link state attention. 3197 * Otherwise some link state change events may be lost until attention 3198 * is cleared by bge_intr() -> bge_link_upd() sequence. 3199 * It's not necessary on newer BCM chips - perhaps enabling link 3200 * state change attentions implies clearing pending attention. 3201 */ 3202 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3203 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3204 BGE_MACSTAT_LINK_CHANGED); 3205 3206 /* Enable link state change attentions. */ 3207 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3208 3209 return 0; 3210 } 3211 3212 static const struct bge_revision * 3213 bge_lookup_rev(uint32_t chipid) 3214 { 3215 const struct bge_revision *br; 3216 3217 for (br = bge_revisions; br->br_name != NULL; br++) { 3218 if (br->br_chipid == chipid) 3219 return br; 3220 } 3221 3222 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3223 if (br->br_chipid == BGE_ASICREV(chipid)) 3224 return br; 3225 } 3226 3227 return NULL; 3228 } 3229 3230 static const struct bge_product * 3231 bge_lookup(const struct pci_attach_args *pa) 3232 { 3233 const struct bge_product *bp; 3234 3235 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3236 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3237 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3238 return bp; 3239 } 3240 3241 return NULL; 3242 } 3243 3244 static uint32_t 3245 bge_chipid(const struct pci_attach_args *pa) 3246 { 3247 uint32_t id; 3248 3249 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3250 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3251 3252 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3253 switch (PCI_PRODUCT(pa->pa_id)) { 3254 case PCI_PRODUCT_BROADCOM_BCM5717: 3255 case PCI_PRODUCT_BROADCOM_BCM5718: 3256 case PCI_PRODUCT_BROADCOM_BCM5719: 3257 case PCI_PRODUCT_BROADCOM_BCM5720: 3258 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3259 BGE_PCI_GEN2_PRODID_ASICREV); 3260 break; 3261 case PCI_PRODUCT_BROADCOM_BCM57761: 3262 case PCI_PRODUCT_BROADCOM_BCM57762: 3263 case PCI_PRODUCT_BROADCOM_BCM57765: 3264 case PCI_PRODUCT_BROADCOM_BCM57766: 3265 case PCI_PRODUCT_BROADCOM_BCM57781: 3266 case PCI_PRODUCT_BROADCOM_BCM57785: 3267 case PCI_PRODUCT_BROADCOM_BCM57791: 3268 case PCI_PRODUCT_BROADCOM_BCM57795: 3269 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3270 BGE_PCI_GEN15_PRODID_ASICREV); 3271 break; 3272 default: 3273 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3274 BGE_PCI_PRODID_ASICREV); 3275 break; 3276 } 3277 } 3278 3279 return id; 3280 } 3281 3282 /* 3283 * Return true if MSI can be used with this device. 3284 */ 3285 static int 3286 bge_can_use_msi(struct bge_softc *sc) 3287 { 3288 int can_use_msi = 0; 3289 3290 switch (BGE_ASICREV(sc->bge_chipid)) { 3291 case BGE_ASICREV_BCM5714_A0: 3292 case BGE_ASICREV_BCM5714: 3293 /* 3294 * Apparently, MSI doesn't work when these chips are 3295 * configured in single-port mode. 3296 */ 3297 break; 3298 case BGE_ASICREV_BCM5750: 3299 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3300 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3301 can_use_msi = 1; 3302 break; 3303 default: 3304 if (BGE_IS_575X_PLUS(sc)) 3305 can_use_msi = 1; 3306 } 3307 return (can_use_msi); 3308 } 3309 3310 /* 3311 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3312 * against our list and return its name if we find a match. Note 3313 * that since the Broadcom controller contains VPD support, we 3314 * can get the device name string from the controller itself instead 3315 * of the compiled-in string. This is a little slow, but it guarantees 3316 * we'll always announce the right product name. 3317 */ 3318 static int 3319 bge_probe(device_t parent, cfdata_t match, void *aux) 3320 { 3321 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3322 3323 if (bge_lookup(pa) != NULL) 3324 return 1; 3325 3326 return 0; 3327 } 3328 3329 static void 3330 bge_attach(device_t parent, device_t self, void *aux) 3331 { 3332 struct bge_softc *sc = device_private(self); 3333 struct pci_attach_args *pa = aux; 3334 prop_dictionary_t dict; 3335 const struct bge_product *bp; 3336 const struct bge_revision *br; 3337 pci_chipset_tag_t pc; 3338 #ifndef __HAVE_PCI_MSI_MSIX 3339 pci_intr_handle_t ih; 3340 #endif 3341 const char *intrstr = NULL; 3342 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3343 uint32_t command; 3344 struct ifnet *ifp; 3345 uint32_t misccfg, mimode; 3346 void * kva; 3347 u_char eaddr[ETHER_ADDR_LEN]; 3348 pcireg_t memtype, subid, reg; 3349 bus_addr_t memaddr; 3350 uint32_t pm_ctl; 3351 bool no_seeprom; 3352 int capmask; 3353 int mii_flags; 3354 int map_flags; 3355 int rv; 3356 char intrbuf[PCI_INTRSTR_LEN]; 3357 3358 bp = bge_lookup(pa); 3359 KASSERT(bp != NULL); 3360 3361 sc->sc_pc = pa->pa_pc; 3362 sc->sc_pcitag = pa->pa_tag; 3363 sc->bge_dev = self; 3364 3365 sc->bge_pa = *pa; 3366 pc = sc->sc_pc; 3367 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3368 3369 aprint_naive(": Ethernet controller\n"); 3370 aprint_normal(": %s\n", bp->bp_name); 3371 3372 /* 3373 * Map control/status registers. 3374 */ 3375 DPRINTFN(5, ("Map control/status regs\n")); 3376 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3377 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3378 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3379 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3380 3381 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3382 aprint_error_dev(sc->bge_dev, 3383 "failed to enable memory mapping!\n"); 3384 return; 3385 } 3386 3387 DPRINTFN(5, ("pci_mem_find\n")); 3388 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3389 switch (memtype) { 3390 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3391 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3392 #if 0 3393 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3394 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3395 &memaddr, &sc->bge_bsize) == 0) 3396 break; 3397 #else 3398 /* 3399 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3400 * system get NMI on boot (PR#48451). This problem might not be 3401 * the driver's bug but our PCI common part's bug. Until we 3402 * find a real reason, we ignore the prefetchable bit. 3403 */ 3404 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3405 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3406 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3407 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3408 map_flags, &sc->bge_bhandle) == 0) { 3409 sc->bge_btag = pa->pa_memt; 3410 break; 3411 } 3412 } 3413 #endif 3414 default: 3415 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3416 return; 3417 } 3418 3419 /* Save various chip information. */ 3420 sc->bge_chipid = bge_chipid(pa); 3421 sc->bge_phy_addr = bge_phy_addr(sc); 3422 3423 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3424 &sc->bge_pciecap, NULL) != 0) 3425 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3426 /* PCIe */ 3427 sc->bge_flags |= BGEF_PCIE; 3428 /* Extract supported maximum payload size. */ 3429 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3430 sc->bge_pciecap + PCIE_DCAP); 3431 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3432 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3433 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3434 sc->bge_expmrq = 2048; 3435 else 3436 sc->bge_expmrq = 4096; 3437 bge_set_max_readrq(sc); 3438 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3439 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3440 /* PCI-X */ 3441 sc->bge_flags |= BGEF_PCIX; 3442 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3443 &sc->bge_pcixcap, NULL) == 0) 3444 aprint_error_dev(sc->bge_dev, 3445 "unable to find PCIX capability\n"); 3446 } 3447 3448 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3449 /* 3450 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3451 * can clobber the chip's PCI config-space power control 3452 * registers, leaving the card in D3 powersave state. We do 3453 * not have memory-mapped registers in this state, so force 3454 * device into D0 state before starting initialization. 3455 */ 3456 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3457 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3458 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3459 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3460 DELAY(1000); /* 27 usec is allegedly sufficent */ 3461 } 3462 3463 /* Save chipset family. */ 3464 switch (BGE_ASICREV(sc->bge_chipid)) { 3465 case BGE_ASICREV_BCM5717: 3466 case BGE_ASICREV_BCM5719: 3467 case BGE_ASICREV_BCM5720: 3468 sc->bge_flags |= BGEF_5717_PLUS; 3469 /* FALLTHROUGH */ 3470 case BGE_ASICREV_BCM57765: 3471 case BGE_ASICREV_BCM57766: 3472 if (!BGE_IS_5717_PLUS(sc)) 3473 sc->bge_flags |= BGEF_57765_FAMILY; 3474 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3475 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3476 /* Jumbo frame on BCM5719 A0 does not work. */ 3477 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3478 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3479 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3480 break; 3481 case BGE_ASICREV_BCM5755: 3482 case BGE_ASICREV_BCM5761: 3483 case BGE_ASICREV_BCM5784: 3484 case BGE_ASICREV_BCM5785: 3485 case BGE_ASICREV_BCM5787: 3486 case BGE_ASICREV_BCM57780: 3487 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3488 break; 3489 case BGE_ASICREV_BCM5700: 3490 case BGE_ASICREV_BCM5701: 3491 case BGE_ASICREV_BCM5703: 3492 case BGE_ASICREV_BCM5704: 3493 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3494 break; 3495 case BGE_ASICREV_BCM5714_A0: 3496 case BGE_ASICREV_BCM5780: 3497 case BGE_ASICREV_BCM5714: 3498 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3499 /* FALLTHROUGH */ 3500 case BGE_ASICREV_BCM5750: 3501 case BGE_ASICREV_BCM5752: 3502 case BGE_ASICREV_BCM5906: 3503 sc->bge_flags |= BGEF_575X_PLUS; 3504 /* FALLTHROUGH */ 3505 case BGE_ASICREV_BCM5705: 3506 sc->bge_flags |= BGEF_5705_PLUS; 3507 break; 3508 } 3509 3510 /* Identify chips with APE processor. */ 3511 switch (BGE_ASICREV(sc->bge_chipid)) { 3512 case BGE_ASICREV_BCM5717: 3513 case BGE_ASICREV_BCM5719: 3514 case BGE_ASICREV_BCM5720: 3515 case BGE_ASICREV_BCM5761: 3516 sc->bge_flags |= BGEF_APE; 3517 break; 3518 } 3519 3520 /* 3521 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3522 * not actually a MAC controller bug but an issue with the embedded 3523 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3524 */ 3525 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3526 sc->bge_flags |= BGEF_40BIT_BUG; 3527 3528 /* Chips with APE need BAR2 access for APE registers/memory. */ 3529 if ((sc->bge_flags & BGEF_APE) != 0) { 3530 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3531 #if 0 3532 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3533 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3534 &sc->bge_apesize)) { 3535 aprint_error_dev(sc->bge_dev, 3536 "couldn't map BAR2 memory\n"); 3537 return; 3538 } 3539 #else 3540 /* 3541 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3542 * system get NMI on boot (PR#48451). This problem might not be 3543 * the driver's bug but our PCI common part's bug. Until we 3544 * find a real reason, we ignore the prefetchable bit. 3545 */ 3546 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3547 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3548 aprint_error_dev(sc->bge_dev, 3549 "couldn't map BAR2 memory\n"); 3550 return; 3551 } 3552 3553 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3554 if (bus_space_map(pa->pa_memt, memaddr, 3555 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3556 aprint_error_dev(sc->bge_dev, 3557 "couldn't map BAR2 memory\n"); 3558 return; 3559 } 3560 sc->bge_apetag = pa->pa_memt; 3561 #endif 3562 3563 /* Enable APE register/memory access by host driver. */ 3564 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3565 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3566 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3567 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3568 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3569 3570 bge_ape_lock_init(sc); 3571 bge_ape_read_fw_ver(sc); 3572 } 3573 3574 /* Identify the chips that use an CPMU. */ 3575 if (BGE_IS_5717_PLUS(sc) || 3576 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3577 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3578 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3579 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3580 sc->bge_flags |= BGEF_CPMU_PRESENT; 3581 3582 /* Set MI_MODE */ 3583 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3584 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3585 mimode |= BGE_MIMODE_500KHZ_CONST; 3586 else 3587 mimode |= BGE_MIMODE_BASE; 3588 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3589 3590 /* 3591 * When using the BCM5701 in PCI-X mode, data corruption has 3592 * been observed in the first few bytes of some received packets. 3593 * Aligning the packet buffer in memory eliminates the corruption. 3594 * Unfortunately, this misaligns the packet payloads. On platforms 3595 * which do not support unaligned accesses, we will realign the 3596 * payloads by copying the received packets. 3597 */ 3598 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3599 sc->bge_flags & BGEF_PCIX) 3600 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3601 3602 if (BGE_IS_5700_FAMILY(sc)) 3603 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3604 3605 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3606 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3607 3608 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3609 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3610 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3611 sc->bge_flags |= BGEF_IS_5788; 3612 3613 /* 3614 * Some controllers seem to require a special firmware to use 3615 * TSO. But the firmware is not available to FreeBSD and Linux 3616 * claims that the TSO performed by the firmware is slower than 3617 * hardware based TSO. Moreover the firmware based TSO has one 3618 * known bug which can't handle TSO if ethernet header + IP/TCP 3619 * header is greater than 80 bytes. The workaround for the TSO 3620 * bug exist but it seems it's too expensive than not using 3621 * TSO at all. Some hardwares also have the TSO bug so limit 3622 * the TSO to the controllers that are not affected TSO issues 3623 * (e.g. 5755 or higher). 3624 */ 3625 if (BGE_IS_5755_PLUS(sc)) { 3626 /* 3627 * BCM5754 and BCM5787 shares the same ASIC id so 3628 * explicit device id check is required. 3629 */ 3630 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3631 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3632 sc->bge_flags |= BGEF_TSO; 3633 } 3634 3635 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3636 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3637 (misccfg == 0x4000 || misccfg == 0x8000)) || 3638 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3639 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3640 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3641 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3642 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3643 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3644 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3645 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3646 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3647 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3648 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3649 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3650 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3651 /* These chips are 10/100 only. */ 3652 capmask &= ~BMSR_EXTSTAT; 3653 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3654 } 3655 3656 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3657 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3658 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3659 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3660 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3661 3662 /* Set various PHY bug flags. */ 3663 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3664 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3665 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3666 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3667 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3668 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3669 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3670 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3671 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3672 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3673 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3674 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3675 if (BGE_IS_5705_PLUS(sc) && 3676 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3677 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3678 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3679 !BGE_IS_57765_PLUS(sc)) { 3680 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3681 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3682 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3683 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3684 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3685 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3686 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3687 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3688 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3689 } else 3690 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3691 } 3692 3693 /* 3694 * SEEPROM check. 3695 * First check if firmware knows we do not have SEEPROM. 3696 */ 3697 if (prop_dictionary_get_bool(device_properties(self), 3698 "without-seeprom", &no_seeprom) && no_seeprom) 3699 sc->bge_flags |= BGEF_NO_EEPROM; 3700 3701 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3702 sc->bge_flags |= BGEF_NO_EEPROM; 3703 3704 /* Now check the 'ROM failed' bit on the RX CPU */ 3705 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3706 sc->bge_flags |= BGEF_NO_EEPROM; 3707 3708 sc->bge_asf_mode = 0; 3709 /* No ASF if APE present. */ 3710 if ((sc->bge_flags & BGEF_APE) == 0) { 3711 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3712 BGE_SRAM_DATA_SIG_MAGIC)) { 3713 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3714 BGE_HWCFG_ASF) { 3715 sc->bge_asf_mode |= ASF_ENABLE; 3716 sc->bge_asf_mode |= ASF_STACKUP; 3717 if (BGE_IS_575X_PLUS(sc)) 3718 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3719 } 3720 } 3721 } 3722 3723 #ifdef __HAVE_PCI_MSI_MSIX 3724 DPRINTFN(5, ("pci_get_capability\n")); 3725 /* Check MSI capability */ 3726 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, 3727 &sc->bge_msicap, NULL) != 0) { 3728 if (bge_can_use_msi(sc) != 0) 3729 sc->bge_flags |= BGEF_MSI; 3730 } 3731 rv = -1; 3732 if (((sc->bge_flags & BGEF_MSI) != 0) && (pci_msi_count(pa) > 0)) { 3733 DPRINTFN(5, ("pci_msi_alloc\n")); 3734 rv = pci_msi_alloc_exact(pa, &sc->bge_pihp, 1); 3735 if (rv != 0) 3736 sc->bge_flags &= ~BGEF_MSI; 3737 } 3738 if (rv != 0) { 3739 DPRINTFN(5, ("pci_intx_alloc\n")); 3740 if (pci_intx_alloc(pa, &sc->bge_pihp)) { 3741 aprint_error_dev(self, "can't map interrupt\n"); 3742 return; 3743 } 3744 sc->bge_flags &= ~BGEF_MSI; 3745 } 3746 #else /* !__HAVE_PCI_MSI_MSIX */ 3747 DPRINTFN(5, ("pci_intr_map\n")); 3748 if (pci_intr_map(pa, &ih)) { 3749 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3750 return; 3751 } 3752 #endif 3753 3754 #ifdef __HAVE_PCI_MSI_MSIX 3755 DPRINTFN(5, ("pci_intr_string\n")); 3756 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3757 sizeof(intrbuf)); 3758 DPRINTFN(5, ("pci_intr_establish\n")); 3759 sc->bge_intrhand = pci_intr_establish(pc, sc->bge_pihp[0], IPL_NET, 3760 bge_intr, sc); 3761 #else /* !__HAVE_PCI_MSI_MSIX */ 3762 DPRINTFN(5, ("pci_intr_string\n")); 3763 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 3764 3765 DPRINTFN(5, ("pci_intr_establish\n")); 3766 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3767 #endif 3768 3769 if (sc->bge_intrhand == NULL) { 3770 aprint_error_dev(sc->bge_dev, 3771 "couldn't establish interrupt%s%s\n", 3772 intrstr ? " at " : "", intrstr ? intrstr : ""); 3773 return; 3774 } 3775 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3776 3777 /* 3778 * All controllers except BCM5700 supports tagged status but 3779 * we use tagged status only for MSI case on BCM5717. Otherwise 3780 * MSI on BCM5717 does not work. 3781 */ 3782 if (BGE_IS_5717_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3783 sc->bge_flags |= BGEF_TAGGED_STATUS; 3784 3785 /* 3786 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3787 * lock in bge_reset(). 3788 */ 3789 CSR_WRITE_4(sc, BGE_EE_ADDR, 3790 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3791 delay(1000); 3792 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3793 3794 bge_stop_fw(sc); 3795 bge_sig_pre_reset(sc, BGE_RESET_START); 3796 if (bge_reset(sc)) 3797 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3798 3799 /* 3800 * Read the hardware config word in the first 32k of NIC internal 3801 * memory, or fall back to the config word in the EEPROM. 3802 * Note: on some BCM5700 cards, this value appears to be unset. 3803 */ 3804 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3805 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3806 BGE_SRAM_DATA_SIG_MAGIC) { 3807 uint32_t tmp; 3808 3809 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3810 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3811 BGE_SRAM_DATA_VER_SHIFT; 3812 if ((0 < tmp) && (tmp < 0x100)) 3813 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3814 if (sc->bge_flags & BGEF_PCIE) 3815 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3816 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3817 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3818 if (BGE_IS_5717_PLUS(sc)) 3819 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3820 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3821 bge_read_eeprom(sc, (void *)&hwcfg, 3822 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3823 hwcfg = be32toh(hwcfg); 3824 } 3825 aprint_normal_dev(sc->bge_dev, 3826 "HW config %08x, %08x, %08x, %08x %08x\n", 3827 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3828 3829 bge_sig_legacy(sc, BGE_RESET_START); 3830 bge_sig_post_reset(sc, BGE_RESET_START); 3831 3832 if (bge_chipinit(sc)) { 3833 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3834 bge_release_resources(sc); 3835 return; 3836 } 3837 3838 /* 3839 * Get station address from the EEPROM. 3840 */ 3841 if (bge_get_eaddr(sc, eaddr)) { 3842 aprint_error_dev(sc->bge_dev, 3843 "failed to read station address\n"); 3844 bge_release_resources(sc); 3845 return; 3846 } 3847 3848 br = bge_lookup_rev(sc->bge_chipid); 3849 3850 if (br == NULL) { 3851 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3852 sc->bge_chipid); 3853 } else { 3854 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3855 br->br_name, sc->bge_chipid); 3856 } 3857 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3858 3859 /* Allocate the general information block and ring buffers. */ 3860 if (pci_dma64_available(pa)) 3861 sc->bge_dmatag = pa->pa_dmat64; 3862 else 3863 sc->bge_dmatag = pa->pa_dmat; 3864 3865 /* 40bit DMA workaround */ 3866 if (sizeof(bus_addr_t) > 4) { 3867 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3868 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3869 3870 if (bus_dmatag_subregion(olddmatag, 0, 3871 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3872 BUS_DMA_NOWAIT) != 0) { 3873 aprint_error_dev(self, 3874 "WARNING: failed to restrict dma range," 3875 " falling back to parent bus dma range\n"); 3876 sc->bge_dmatag = olddmatag; 3877 } 3878 } 3879 } 3880 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3881 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3882 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3883 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3884 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3885 return; 3886 } 3887 DPRINTFN(5, ("bus_dmamem_map\n")); 3888 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3889 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3890 BUS_DMA_NOWAIT)) { 3891 aprint_error_dev(sc->bge_dev, 3892 "can't map DMA buffers (%zu bytes)\n", 3893 sizeof(struct bge_ring_data)); 3894 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3895 sc->bge_ring_rseg); 3896 return; 3897 } 3898 DPRINTFN(5, ("bus_dmamem_create\n")); 3899 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3900 sizeof(struct bge_ring_data), 0, 3901 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3902 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3903 bus_dmamem_unmap(sc->bge_dmatag, kva, 3904 sizeof(struct bge_ring_data)); 3905 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3906 sc->bge_ring_rseg); 3907 return; 3908 } 3909 DPRINTFN(5, ("bus_dmamem_load\n")); 3910 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3911 sizeof(struct bge_ring_data), NULL, 3912 BUS_DMA_NOWAIT)) { 3913 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3914 bus_dmamem_unmap(sc->bge_dmatag, kva, 3915 sizeof(struct bge_ring_data)); 3916 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3917 sc->bge_ring_rseg); 3918 return; 3919 } 3920 3921 DPRINTFN(5, ("bzero\n")); 3922 sc->bge_rdata = (struct bge_ring_data *)kva; 3923 3924 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3925 3926 /* Try to allocate memory for jumbo buffers. */ 3927 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3928 if (bge_alloc_jumbo_mem(sc)) { 3929 aprint_error_dev(sc->bge_dev, 3930 "jumbo buffer allocation failed\n"); 3931 } else 3932 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3933 } 3934 3935 /* Set default tuneable values. */ 3936 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3937 sc->bge_rx_coal_ticks = 150; 3938 sc->bge_rx_max_coal_bds = 64; 3939 sc->bge_tx_coal_ticks = 300; 3940 sc->bge_tx_max_coal_bds = 400; 3941 if (BGE_IS_5705_PLUS(sc)) { 3942 sc->bge_tx_coal_ticks = (12 * 5); 3943 sc->bge_tx_max_coal_bds = (12 * 5); 3944 aprint_verbose_dev(sc->bge_dev, 3945 "setting short Tx thresholds\n"); 3946 } 3947 3948 if (BGE_IS_5717_PLUS(sc)) 3949 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3950 else if (BGE_IS_5705_PLUS(sc)) 3951 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3952 else 3953 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3954 3955 /* Set up ifnet structure */ 3956 ifp = &sc->ethercom.ec_if; 3957 ifp->if_softc = sc; 3958 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3959 ifp->if_ioctl = bge_ioctl; 3960 ifp->if_stop = bge_stop; 3961 ifp->if_start = bge_start; 3962 ifp->if_init = bge_init; 3963 ifp->if_watchdog = bge_watchdog; 3964 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3965 IFQ_SET_READY(&ifp->if_snd); 3966 DPRINTFN(5, ("strcpy if_xname\n")); 3967 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3968 3969 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3970 sc->ethercom.ec_if.if_capabilities |= 3971 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3972 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3973 sc->ethercom.ec_if.if_capabilities |= 3974 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3975 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3976 #endif 3977 sc->ethercom.ec_capabilities |= 3978 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3979 3980 if (sc->bge_flags & BGEF_TSO) 3981 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3982 3983 /* 3984 * Do MII setup. 3985 */ 3986 DPRINTFN(5, ("mii setup\n")); 3987 sc->bge_mii.mii_ifp = ifp; 3988 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3989 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3990 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3991 3992 /* 3993 * Figure out what sort of media we have by checking the hardware 3994 * config word. Note: on some BCM5700 cards, this value appears to be 3995 * unset. If that's the case, we have to rely on identifying the NIC 3996 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3997 * The SysKonnect SK-9D41 is a 1000baseSX card. 3998 */ 3999 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 4000 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 4001 if (BGE_IS_5705_PLUS(sc)) { 4002 sc->bge_flags |= BGEF_FIBER_MII; 4003 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 4004 } else 4005 sc->bge_flags |= BGEF_FIBER_TBI; 4006 } 4007 4008 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 4009 if (BGE_IS_JUMBO_CAPABLE(sc)) 4010 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 4011 4012 /* set phyflags and chipid before mii_attach() */ 4013 dict = device_properties(self); 4014 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 4015 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 4016 4017 if (sc->bge_flags & BGEF_FIBER_TBI) { 4018 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 4019 bge_ifmedia_sts); 4020 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 4021 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 4022 0, NULL); 4023 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 4024 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 4025 /* Pretend the user requested this setting */ 4026 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 4027 } else { 4028 /* 4029 * Do transceiver setup and tell the firmware the 4030 * driver is down so we can try to get access the 4031 * probe if ASF is running. Retry a couple of times 4032 * if we get a conflict with the ASF firmware accessing 4033 * the PHY. 4034 */ 4035 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4036 bge_asf_driver_up(sc); 4037 4038 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 4039 bge_ifmedia_sts); 4040 mii_flags = MIIF_DOPAUSE; 4041 if (sc->bge_flags & BGEF_FIBER_MII) 4042 mii_flags |= MIIF_HAVEFIBER; 4043 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 4044 MII_OFFSET_ANY, mii_flags); 4045 4046 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 4047 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4048 ifmedia_add(&sc->bge_mii.mii_media, 4049 IFM_ETHER|IFM_MANUAL, 0, NULL); 4050 ifmedia_set(&sc->bge_mii.mii_media, 4051 IFM_ETHER|IFM_MANUAL); 4052 } else 4053 ifmedia_set(&sc->bge_mii.mii_media, 4054 IFM_ETHER|IFM_AUTO); 4055 4056 /* 4057 * Now tell the firmware we are going up after probing the PHY 4058 */ 4059 if (sc->bge_asf_mode & ASF_STACKUP) 4060 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4061 } 4062 4063 /* 4064 * Call MI attach routine. 4065 */ 4066 DPRINTFN(5, ("if_attach\n")); 4067 if_attach(ifp); 4068 DPRINTFN(5, ("ether_ifattach\n")); 4069 ether_ifattach(ifp, eaddr); 4070 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4071 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4072 RND_TYPE_NET, RND_FLAG_DEFAULT); 4073 #ifdef BGE_EVENT_COUNTERS 4074 /* 4075 * Attach event counters. 4076 */ 4077 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4078 NULL, device_xname(sc->bge_dev), "intr"); 4079 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4080 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4081 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4082 NULL, device_xname(sc->bge_dev), "tx_xon"); 4083 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4084 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4085 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4086 NULL, device_xname(sc->bge_dev), "rx_xon"); 4087 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4088 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4089 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4090 NULL, device_xname(sc->bge_dev), "xoffentered"); 4091 #endif /* BGE_EVENT_COUNTERS */ 4092 DPRINTFN(5, ("callout_init\n")); 4093 callout_init(&sc->bge_timeout, 0); 4094 4095 if (pmf_device_register(self, NULL, NULL)) 4096 pmf_class_network_register(self, ifp); 4097 else 4098 aprint_error_dev(self, "couldn't establish power handler\n"); 4099 4100 bge_sysctl_init(sc); 4101 4102 #ifdef BGE_DEBUG 4103 bge_debug_info(sc); 4104 #endif 4105 } 4106 4107 /* 4108 * Stop all chip I/O so that the kernel's probe routines don't 4109 * get confused by errant DMAs when rebooting. 4110 */ 4111 static int 4112 bge_detach(device_t self, int flags __unused) 4113 { 4114 struct bge_softc *sc = device_private(self); 4115 struct ifnet *ifp = &sc->ethercom.ec_if; 4116 int s; 4117 4118 s = splnet(); 4119 /* Stop the interface. Callouts are stopped in it. */ 4120 bge_stop(ifp, 1); 4121 splx(s); 4122 4123 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4124 4125 /* Delete all remaining media. */ 4126 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4127 4128 ether_ifdetach(ifp); 4129 if_detach(ifp); 4130 4131 bge_release_resources(sc); 4132 4133 return 0; 4134 } 4135 4136 static void 4137 bge_release_resources(struct bge_softc *sc) 4138 { 4139 4140 /* Disestablish the interrupt handler */ 4141 if (sc->bge_intrhand != NULL) { 4142 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4143 sc->bge_intrhand = NULL; 4144 } 4145 4146 if (sc->bge_dmatag != NULL) { 4147 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4148 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4149 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4150 sizeof(struct bge_ring_data)); 4151 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 4152 } 4153 4154 /* Unmap the device registers */ 4155 if (sc->bge_bsize != 0) { 4156 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4157 sc->bge_bsize = 0; 4158 } 4159 4160 /* Unmap the APE registers */ 4161 if (sc->bge_apesize != 0) { 4162 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4163 sc->bge_apesize); 4164 sc->bge_apesize = 0; 4165 } 4166 } 4167 4168 static int 4169 bge_reset(struct bge_softc *sc) 4170 { 4171 uint32_t cachesize, command; 4172 uint32_t reset, mac_mode, mac_mode_mask; 4173 pcireg_t devctl, reg; 4174 int i, val; 4175 void (*write_op)(struct bge_softc *, int, int); 4176 4177 /* Make mask for BGE_MAC_MODE register. */ 4178 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4179 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4180 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4181 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4182 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4183 4184 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4185 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4186 if (sc->bge_flags & BGEF_PCIE) 4187 write_op = bge_writemem_direct; 4188 else 4189 write_op = bge_writemem_ind; 4190 } else 4191 write_op = bge_writereg_ind; 4192 4193 /* 57XX step 4 */ 4194 /* Acquire the NVM lock */ 4195 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4196 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4197 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4198 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4199 for (i = 0; i < 8000; i++) { 4200 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4201 BGE_NVRAMSWARB_GNT1) 4202 break; 4203 DELAY(20); 4204 } 4205 if (i == 8000) { 4206 printf("%s: NVRAM lock timedout!\n", 4207 device_xname(sc->bge_dev)); 4208 } 4209 } 4210 4211 /* Take APE lock when performing reset. */ 4212 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4213 4214 /* 57XX step 3 */ 4215 /* Save some important PCI state. */ 4216 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4217 /* 5718 reset step 3 */ 4218 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4219 4220 /* 5718 reset step 5, 57XX step 5b-5d */ 4221 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4222 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4223 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4224 4225 /* XXX ???: Disable fastboot on controllers that support it. */ 4226 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4227 BGE_IS_5755_PLUS(sc)) 4228 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4229 4230 /* 5718 reset step 2, 57XX step 6 */ 4231 /* 4232 * Write the magic number to SRAM at offset 0xB50. 4233 * When firmware finishes its initialization it will 4234 * write ~BGE_MAGIC_NUMBER to the same location. 4235 */ 4236 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4237 4238 /* 5718 reset step 6, 57XX step 7 */ 4239 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4240 /* 4241 * XXX: from FreeBSD/Linux; no documentation 4242 */ 4243 if (sc->bge_flags & BGEF_PCIE) { 4244 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4245 !BGE_IS_57765_PLUS(sc) && 4246 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4247 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4248 /* PCI Express 1.0 system */ 4249 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4250 BGE_PHY_PCIE_SCRAM_MODE); 4251 } 4252 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4253 /* 4254 * Prevent PCI Express link training 4255 * during global reset. 4256 */ 4257 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4258 reset |= (1 << 29); 4259 } 4260 } 4261 4262 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4263 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4264 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4265 i | BGE_VCPU_STATUS_DRV_RESET); 4266 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4267 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4268 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4269 } 4270 4271 /* 4272 * Set GPHY Power Down Override to leave GPHY 4273 * powered up in D0 uninitialized. 4274 */ 4275 if (BGE_IS_5705_PLUS(sc) && 4276 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4277 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4278 4279 /* Issue global reset */ 4280 write_op(sc, BGE_MISC_CFG, reset); 4281 4282 /* 5718 reset step 7, 57XX step 8 */ 4283 if (sc->bge_flags & BGEF_PCIE) 4284 delay(100*1000); /* too big */ 4285 else 4286 delay(1000); 4287 4288 if (sc->bge_flags & BGEF_PCIE) { 4289 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4290 DELAY(500000); 4291 /* XXX: Magic Numbers */ 4292 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4293 BGE_PCI_UNKNOWN0); 4294 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4295 BGE_PCI_UNKNOWN0, 4296 reg | (1 << 15)); 4297 } 4298 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4299 sc->bge_pciecap + PCIE_DCSR); 4300 /* Clear enable no snoop and disable relaxed ordering. */ 4301 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4302 PCIE_DCSR_ENA_NO_SNOOP); 4303 4304 /* Set PCIE max payload size to 128 for older PCIe devices */ 4305 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4306 devctl &= ~(0x00e0); 4307 /* Clear device status register. Write 1b to clear */ 4308 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4309 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4310 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4311 sc->bge_pciecap + PCIE_DCSR, devctl); 4312 bge_set_max_readrq(sc); 4313 } 4314 4315 /* From Linux: dummy read to flush PCI posted writes */ 4316 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4317 4318 /* 4319 * Reset some of the PCI state that got zapped by reset 4320 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4321 * set, too. 4322 */ 4323 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4324 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4325 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4326 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4327 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4328 (sc->bge_flags & BGEF_PCIX) != 0) 4329 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4330 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4331 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4332 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4333 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4334 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4335 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4336 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4337 4338 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4339 if (sc->bge_flags & BGEF_PCIX) { 4340 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4341 + PCIX_CMD); 4342 /* Set max memory read byte count to 2K */ 4343 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4344 reg &= ~PCIX_CMD_BYTECNT_MASK; 4345 reg |= PCIX_CMD_BCNT_2048; 4346 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4347 /* 4348 * For 5704, set max outstanding split transaction 4349 * field to 0 (0 means it supports 1 request) 4350 */ 4351 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4352 | PCIX_CMD_BYTECNT_MASK); 4353 reg |= PCIX_CMD_BCNT_2048; 4354 } 4355 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4356 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4357 } 4358 4359 /* 5718 reset step 10, 57XX step 12 */ 4360 /* Enable memory arbiter. */ 4361 if (BGE_IS_5714_FAMILY(sc)) { 4362 val = CSR_READ_4(sc, BGE_MARB_MODE); 4363 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4364 } else 4365 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4366 4367 /* XXX 5721, 5751 and 5752 */ 4368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4369 /* Step 19: */ 4370 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4371 /* Step 20: */ 4372 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4373 } 4374 4375 /* 5718 reset step 12, 57XX step 15 and 16 */ 4376 /* Fix up byte swapping */ 4377 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4378 4379 /* 5718 reset step 13, 57XX step 17 */ 4380 /* Poll until the firmware initialization is complete */ 4381 bge_poll_fw(sc); 4382 4383 /* 57XX step 21 */ 4384 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4385 pcireg_t msidata; 4386 4387 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4388 BGE_PCI_MSI_DATA); 4389 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4390 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4391 msidata); 4392 } 4393 4394 /* 57XX step 18 */ 4395 /* Write mac mode. */ 4396 val = CSR_READ_4(sc, BGE_MAC_MODE); 4397 /* Restore mac_mode_mask's bits using mac_mode */ 4398 val = (val & ~mac_mode_mask) | mac_mode; 4399 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4400 DELAY(40); 4401 4402 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4403 4404 /* 4405 * The 5704 in TBI mode apparently needs some special 4406 * adjustment to insure the SERDES drive level is set 4407 * to 1.2V. 4408 */ 4409 if (sc->bge_flags & BGEF_FIBER_TBI && 4410 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4411 uint32_t serdescfg; 4412 4413 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4414 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4415 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4416 } 4417 4418 if (sc->bge_flags & BGEF_PCIE && 4419 !BGE_IS_57765_PLUS(sc) && 4420 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4421 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4422 uint32_t v; 4423 4424 /* Enable PCI Express bug fix */ 4425 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4426 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4427 v | BGE_TLP_DATA_FIFO_PROTECT); 4428 } 4429 4430 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4431 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4432 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4433 4434 return 0; 4435 } 4436 4437 /* 4438 * Frame reception handling. This is called if there's a frame 4439 * on the receive return list. 4440 * 4441 * Note: we have to be able to handle two possibilities here: 4442 * 1) the frame is from the jumbo receive ring 4443 * 2) the frame is from the standard receive ring 4444 */ 4445 4446 static void 4447 bge_rxeof(struct bge_softc *sc) 4448 { 4449 struct ifnet *ifp; 4450 uint16_t rx_prod, rx_cons; 4451 int stdcnt = 0, jumbocnt = 0; 4452 bus_dmamap_t dmamap; 4453 bus_addr_t offset, toff; 4454 bus_size_t tlen; 4455 int tosync; 4456 4457 rx_cons = sc->bge_rx_saved_considx; 4458 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4459 4460 /* Nothing to do */ 4461 if (rx_cons == rx_prod) 4462 return; 4463 4464 ifp = &sc->ethercom.ec_if; 4465 4466 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4467 offsetof(struct bge_ring_data, bge_status_block), 4468 sizeof (struct bge_status_block), 4469 BUS_DMASYNC_POSTREAD); 4470 4471 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4472 tosync = rx_prod - rx_cons; 4473 4474 if (tosync != 0) 4475 rnd_add_uint32(&sc->rnd_source, tosync); 4476 4477 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4478 4479 if (tosync < 0) { 4480 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4481 sizeof (struct bge_rx_bd); 4482 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4483 toff, tlen, BUS_DMASYNC_POSTREAD); 4484 tosync = -tosync; 4485 } 4486 4487 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4488 offset, tosync * sizeof (struct bge_rx_bd), 4489 BUS_DMASYNC_POSTREAD); 4490 4491 while (rx_cons != rx_prod) { 4492 struct bge_rx_bd *cur_rx; 4493 uint32_t rxidx; 4494 struct mbuf *m = NULL; 4495 4496 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4497 4498 rxidx = cur_rx->bge_idx; 4499 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4500 4501 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4502 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4503 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4504 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4505 jumbocnt++; 4506 bus_dmamap_sync(sc->bge_dmatag, 4507 sc->bge_cdata.bge_rx_jumbo_map, 4508 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4509 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4510 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4511 ifp->if_ierrors++; 4512 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4513 continue; 4514 } 4515 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4516 NULL)== ENOBUFS) { 4517 ifp->if_ierrors++; 4518 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4519 continue; 4520 } 4521 } else { 4522 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4523 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4524 4525 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4526 stdcnt++; 4527 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4528 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4529 if (dmamap == NULL) { 4530 ifp->if_ierrors++; 4531 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4532 continue; 4533 } 4534 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4535 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4536 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4537 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4538 ifp->if_ierrors++; 4539 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4540 continue; 4541 } 4542 if (bge_newbuf_std(sc, sc->bge_std, 4543 NULL, dmamap) == ENOBUFS) { 4544 ifp->if_ierrors++; 4545 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4546 continue; 4547 } 4548 } 4549 4550 ifp->if_ipackets++; 4551 #ifndef __NO_STRICT_ALIGNMENT 4552 /* 4553 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4554 * the Rx buffer has the layer-2 header unaligned. 4555 * If our CPU requires alignment, re-align by copying. 4556 */ 4557 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4558 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4559 cur_rx->bge_len); 4560 m->m_data += ETHER_ALIGN; 4561 } 4562 #endif 4563 4564 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4565 m->m_pkthdr.rcvif = ifp; 4566 4567 /* 4568 * Handle BPF listeners. Let the BPF user see the packet. 4569 */ 4570 bpf_mtap(ifp, m); 4571 4572 bge_rxcsum(sc, cur_rx, m); 4573 4574 /* 4575 * If we received a packet with a vlan tag, pass it 4576 * to vlan_input() instead of ether_input(). 4577 */ 4578 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4579 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4580 } 4581 4582 (*ifp->if_input)(ifp, m); 4583 } 4584 4585 sc->bge_rx_saved_considx = rx_cons; 4586 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4587 if (stdcnt) 4588 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4589 if (jumbocnt) 4590 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4591 } 4592 4593 static void 4594 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4595 { 4596 4597 if (BGE_IS_57765_PLUS(sc)) { 4598 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4599 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4600 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4601 if ((cur_rx->bge_error_flag & 4602 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4603 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4604 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4605 m->m_pkthdr.csum_data = 4606 cur_rx->bge_tcp_udp_csum; 4607 m->m_pkthdr.csum_flags |= 4608 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4609 M_CSUM_DATA); 4610 } 4611 } 4612 } else { 4613 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4614 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4615 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4616 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4617 /* 4618 * Rx transport checksum-offload may also 4619 * have bugs with packets which, when transmitted, 4620 * were `runts' requiring padding. 4621 */ 4622 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4623 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4624 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4625 m->m_pkthdr.csum_data = 4626 cur_rx->bge_tcp_udp_csum; 4627 m->m_pkthdr.csum_flags |= 4628 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4629 M_CSUM_DATA); 4630 } 4631 } 4632 } 4633 4634 static void 4635 bge_txeof(struct bge_softc *sc) 4636 { 4637 struct bge_tx_bd *cur_tx = NULL; 4638 struct ifnet *ifp; 4639 struct txdmamap_pool_entry *dma; 4640 bus_addr_t offset, toff; 4641 bus_size_t tlen; 4642 int tosync; 4643 struct mbuf *m; 4644 4645 ifp = &sc->ethercom.ec_if; 4646 4647 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4648 offsetof(struct bge_ring_data, bge_status_block), 4649 sizeof (struct bge_status_block), 4650 BUS_DMASYNC_POSTREAD); 4651 4652 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4653 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4654 sc->bge_tx_saved_considx; 4655 4656 if (tosync != 0) 4657 rnd_add_uint32(&sc->rnd_source, tosync); 4658 4659 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4660 4661 if (tosync < 0) { 4662 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4663 sizeof (struct bge_tx_bd); 4664 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4665 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4666 tosync = -tosync; 4667 } 4668 4669 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4670 offset, tosync * sizeof (struct bge_tx_bd), 4671 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4672 4673 /* 4674 * Go through our tx ring and free mbufs for those 4675 * frames that have been sent. 4676 */ 4677 while (sc->bge_tx_saved_considx != 4678 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4679 uint32_t idx = 0; 4680 4681 idx = sc->bge_tx_saved_considx; 4682 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4683 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4684 ifp->if_opackets++; 4685 m = sc->bge_cdata.bge_tx_chain[idx]; 4686 if (m != NULL) { 4687 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4688 dma = sc->txdma[idx]; 4689 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4690 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4691 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4692 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4693 sc->txdma[idx] = NULL; 4694 4695 m_freem(m); 4696 } 4697 sc->bge_txcnt--; 4698 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4699 ifp->if_timer = 0; 4700 } 4701 4702 if (cur_tx != NULL) 4703 ifp->if_flags &= ~IFF_OACTIVE; 4704 } 4705 4706 static int 4707 bge_intr(void *xsc) 4708 { 4709 struct bge_softc *sc; 4710 struct ifnet *ifp; 4711 uint32_t pcistate, statusword, statustag; 4712 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4713 4714 sc = xsc; 4715 ifp = &sc->ethercom.ec_if; 4716 4717 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4718 if (BGE_IS_5717_PLUS(sc)) 4719 intrmask = 0; 4720 4721 /* It is possible for the interrupt to arrive before 4722 * the status block is updated prior to the interrupt. 4723 * Reading the PCI State register will confirm whether the 4724 * interrupt is ours and will flush the status block. 4725 */ 4726 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4727 4728 /* read status word from status block */ 4729 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4730 offsetof(struct bge_ring_data, bge_status_block), 4731 sizeof (struct bge_status_block), 4732 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4733 statusword = sc->bge_rdata->bge_status_block.bge_status; 4734 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4735 4736 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4737 if (sc->bge_lasttag == statustag && 4738 (~pcistate & intrmask)) { 4739 printf("[SP]"); 4740 return (0); 4741 } 4742 sc->bge_lasttag = statustag; 4743 } else { 4744 if (!(statusword & BGE_STATFLAG_UPDATED) && 4745 !(~pcistate & intrmask)) { 4746 return (0); 4747 } 4748 statustag = 0; 4749 } 4750 /* Ack interrupt and stop others from occurring. */ 4751 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4752 BGE_EVCNT_INCR(sc->bge_ev_intr); 4753 4754 /* clear status word */ 4755 sc->bge_rdata->bge_status_block.bge_status = 0; 4756 4757 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4758 offsetof(struct bge_ring_data, bge_status_block), 4759 sizeof (struct bge_status_block), 4760 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4761 4762 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4763 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4764 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4765 bge_link_upd(sc); 4766 4767 if (ifp->if_flags & IFF_RUNNING) { 4768 /* Check RX return ring producer/consumer */ 4769 bge_rxeof(sc); 4770 4771 /* Check TX ring producer/consumer */ 4772 bge_txeof(sc); 4773 } 4774 4775 if (sc->bge_pending_rxintr_change) { 4776 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4777 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4778 4779 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4780 DELAY(10); 4781 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4782 4783 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4784 DELAY(10); 4785 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4786 4787 sc->bge_pending_rxintr_change = 0; 4788 } 4789 bge_handle_events(sc); 4790 4791 /* Re-enable interrupts. */ 4792 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4793 4794 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4795 bge_start(ifp); 4796 4797 return 1; 4798 } 4799 4800 static void 4801 bge_asf_driver_up(struct bge_softc *sc) 4802 { 4803 if (sc->bge_asf_mode & ASF_STACKUP) { 4804 /* Send ASF heartbeat aprox. every 2s */ 4805 if (sc->bge_asf_count) 4806 sc->bge_asf_count --; 4807 else { 4808 sc->bge_asf_count = 2; 4809 4810 bge_wait_for_event_ack(sc); 4811 4812 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4813 BGE_FW_CMD_DRV_ALIVE3); 4814 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4815 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4816 BGE_FW_HB_TIMEOUT_SEC); 4817 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4818 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4819 BGE_RX_CPU_DRV_EVENT); 4820 } 4821 } 4822 } 4823 4824 static void 4825 bge_tick(void *xsc) 4826 { 4827 struct bge_softc *sc = xsc; 4828 struct mii_data *mii = &sc->bge_mii; 4829 int s; 4830 4831 s = splnet(); 4832 4833 if (BGE_IS_5705_PLUS(sc)) 4834 bge_stats_update_regs(sc); 4835 else 4836 bge_stats_update(sc); 4837 4838 if (sc->bge_flags & BGEF_FIBER_TBI) { 4839 /* 4840 * Since in TBI mode auto-polling can't be used we should poll 4841 * link status manually. Here we register pending link event 4842 * and trigger interrupt. 4843 */ 4844 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4845 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4846 } else { 4847 /* 4848 * Do not touch PHY if we have link up. This could break 4849 * IPMI/ASF mode or produce extra input errors. 4850 * (extra input errors was reported for bcm5701 & bcm5704). 4851 */ 4852 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4853 mii_tick(mii); 4854 } 4855 4856 bge_asf_driver_up(sc); 4857 4858 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4859 4860 splx(s); 4861 } 4862 4863 static void 4864 bge_stats_update_regs(struct bge_softc *sc) 4865 { 4866 struct ifnet *ifp = &sc->ethercom.ec_if; 4867 4868 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4869 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4870 4871 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4872 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4873 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4874 } 4875 4876 static void 4877 bge_stats_update(struct bge_softc *sc) 4878 { 4879 struct ifnet *ifp = &sc->ethercom.ec_if; 4880 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4881 4882 #define READ_STAT(sc, stats, stat) \ 4883 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4884 4885 ifp->if_collisions += 4886 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4887 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4888 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4889 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4890 ifp->if_collisions; 4891 4892 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4893 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4894 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4895 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4896 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4897 READ_STAT(sc, stats, 4898 xoffPauseFramesReceived.bge_addr_lo)); 4899 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4900 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4901 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4902 READ_STAT(sc, stats, 4903 macControlFramesReceived.bge_addr_lo)); 4904 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4905 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4906 4907 #undef READ_STAT 4908 4909 #ifdef notdef 4910 ifp->if_collisions += 4911 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4912 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4913 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4914 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4915 ifp->if_collisions; 4916 #endif 4917 } 4918 4919 /* 4920 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4921 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4922 * but when such padded frames employ the bge IP/TCP checksum offload, 4923 * the hardware checksum assist gives incorrect results (possibly 4924 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4925 * If we pad such runts with zeros, the onboard checksum comes out correct. 4926 */ 4927 static inline int 4928 bge_cksum_pad(struct mbuf *pkt) 4929 { 4930 struct mbuf *last = NULL; 4931 int padlen; 4932 4933 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4934 4935 /* if there's only the packet-header and we can pad there, use it. */ 4936 if (pkt->m_pkthdr.len == pkt->m_len && 4937 M_TRAILINGSPACE(pkt) >= padlen) { 4938 last = pkt; 4939 } else { 4940 /* 4941 * Walk packet chain to find last mbuf. We will either 4942 * pad there, or append a new mbuf and pad it 4943 * (thus perhaps avoiding the bcm5700 dma-min bug). 4944 */ 4945 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4946 continue; /* do nothing */ 4947 } 4948 4949 /* `last' now points to last in chain. */ 4950 if (M_TRAILINGSPACE(last) < padlen) { 4951 /* Allocate new empty mbuf, pad it. Compact later. */ 4952 struct mbuf *n; 4953 MGET(n, M_DONTWAIT, MT_DATA); 4954 if (n == NULL) 4955 return ENOBUFS; 4956 n->m_len = 0; 4957 last->m_next = n; 4958 last = n; 4959 } 4960 } 4961 4962 KDASSERT(!M_READONLY(last)); 4963 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4964 4965 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4966 memset(mtod(last, char *) + last->m_len, 0, padlen); 4967 last->m_len += padlen; 4968 pkt->m_pkthdr.len += padlen; 4969 return 0; 4970 } 4971 4972 /* 4973 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4974 */ 4975 static inline int 4976 bge_compact_dma_runt(struct mbuf *pkt) 4977 { 4978 struct mbuf *m, *prev; 4979 int totlen; 4980 4981 prev = NULL; 4982 totlen = 0; 4983 4984 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4985 int mlen = m->m_len; 4986 int shortfall = 8 - mlen ; 4987 4988 totlen += mlen; 4989 if (mlen == 0) 4990 continue; 4991 if (mlen >= 8) 4992 continue; 4993 4994 /* If we get here, mbuf data is too small for DMA engine. 4995 * Try to fix by shuffling data to prev or next in chain. 4996 * If that fails, do a compacting deep-copy of the whole chain. 4997 */ 4998 4999 /* Internal frag. If fits in prev, copy it there. */ 5000 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5001 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5002 prev->m_len += mlen; 5003 m->m_len = 0; 5004 /* XXX stitch chain */ 5005 prev->m_next = m_free(m); 5006 m = prev; 5007 continue; 5008 } 5009 else if (m->m_next != NULL && 5010 M_TRAILINGSPACE(m) >= shortfall && 5011 m->m_next->m_len >= (8 + shortfall)) { 5012 /* m is writable and have enough data in next, pull up. */ 5013 5014 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5015 shortfall); 5016 m->m_len += shortfall; 5017 m->m_next->m_len -= shortfall; 5018 m->m_next->m_data += shortfall; 5019 } 5020 else if (m->m_next == NULL || 1) { 5021 /* Got a runt at the very end of the packet. 5022 * borrow data from the tail of the preceding mbuf and 5023 * update its length in-place. (The original data is still 5024 * valid, so we can do this even if prev is not writable.) 5025 */ 5026 5027 /* if we'd make prev a runt, just move all of its data. */ 5028 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5029 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5030 5031 if ((prev->m_len - shortfall) < 8) 5032 shortfall = prev->m_len; 5033 5034 #ifdef notyet /* just do the safe slow thing for now */ 5035 if (!M_READONLY(m)) { 5036 if (M_LEADINGSPACE(m) < shorfall) { 5037 void *m_dat; 5038 m_dat = (m->m_flags & M_PKTHDR) ? 5039 m->m_pktdat : m->dat; 5040 memmove(m_dat, mtod(m, void*), m->m_len); 5041 m->m_data = m_dat; 5042 } 5043 } else 5044 #endif /* just do the safe slow thing */ 5045 { 5046 struct mbuf * n = NULL; 5047 int newprevlen = prev->m_len - shortfall; 5048 5049 MGET(n, M_NOWAIT, MT_DATA); 5050 if (n == NULL) 5051 return ENOBUFS; 5052 KASSERT(m->m_len + shortfall < MLEN 5053 /*, 5054 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5055 5056 /* first copy the data we're stealing from prev */ 5057 memcpy(n->m_data, prev->m_data + newprevlen, 5058 shortfall); 5059 5060 /* update prev->m_len accordingly */ 5061 prev->m_len -= shortfall; 5062 5063 /* copy data from runt m */ 5064 memcpy(n->m_data + shortfall, m->m_data, 5065 m->m_len); 5066 5067 /* n holds what we stole from prev, plus m */ 5068 n->m_len = shortfall + m->m_len; 5069 5070 /* stitch n into chain and free m */ 5071 n->m_next = m->m_next; 5072 prev->m_next = n; 5073 /* KASSERT(m->m_next == NULL); */ 5074 m->m_next = NULL; 5075 m_free(m); 5076 m = n; /* for continuing loop */ 5077 } 5078 } 5079 } 5080 return 0; 5081 } 5082 5083 /* 5084 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5085 * pointers to descriptors. 5086 */ 5087 static int 5088 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5089 { 5090 struct bge_tx_bd *f = NULL; 5091 uint32_t frag, cur; 5092 uint16_t csum_flags = 0; 5093 uint16_t txbd_tso_flags = 0; 5094 struct txdmamap_pool_entry *dma; 5095 bus_dmamap_t dmamap; 5096 int i = 0; 5097 struct m_tag *mtag; 5098 int use_tso, maxsegsize, error; 5099 5100 cur = frag = *txidx; 5101 5102 if (m_head->m_pkthdr.csum_flags) { 5103 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5104 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5105 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 5106 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5107 } 5108 5109 /* 5110 * If we were asked to do an outboard checksum, and the NIC 5111 * has the bug where it sometimes adds in the Ethernet padding, 5112 * explicitly pad with zeros so the cksum will be correct either way. 5113 * (For now, do this for all chip versions, until newer 5114 * are confirmed to not require the workaround.) 5115 */ 5116 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5117 #ifdef notyet 5118 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5119 #endif 5120 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5121 goto check_dma_bug; 5122 5123 if (bge_cksum_pad(m_head) != 0) 5124 return ENOBUFS; 5125 5126 check_dma_bug: 5127 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5128 goto doit; 5129 5130 /* 5131 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5132 * less than eight bytes. If we encounter a teeny mbuf 5133 * at the end of a chain, we can pad. Otherwise, copy. 5134 */ 5135 if (bge_compact_dma_runt(m_head) != 0) 5136 return ENOBUFS; 5137 5138 doit: 5139 dma = SLIST_FIRST(&sc->txdma_list); 5140 if (dma == NULL) 5141 return ENOBUFS; 5142 dmamap = dma->dmamap; 5143 5144 /* 5145 * Set up any necessary TSO state before we start packing... 5146 */ 5147 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5148 if (!use_tso) { 5149 maxsegsize = 0; 5150 } else { /* TSO setup */ 5151 unsigned mss; 5152 struct ether_header *eh; 5153 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5154 struct mbuf * m0 = m_head; 5155 struct ip *ip; 5156 struct tcphdr *th; 5157 int iphl, hlen; 5158 5159 /* 5160 * XXX It would be nice if the mbuf pkthdr had offset 5161 * fields for the protocol headers. 5162 */ 5163 5164 eh = mtod(m0, struct ether_header *); 5165 switch (htons(eh->ether_type)) { 5166 case ETHERTYPE_IP: 5167 offset = ETHER_HDR_LEN; 5168 break; 5169 5170 case ETHERTYPE_VLAN: 5171 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5172 break; 5173 5174 default: 5175 /* 5176 * Don't support this protocol or encapsulation. 5177 */ 5178 return ENOBUFS; 5179 } 5180 5181 /* 5182 * TCP/IP headers are in the first mbuf; we can do 5183 * this the easy way. 5184 */ 5185 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5186 hlen = iphl + offset; 5187 if (__predict_false(m0->m_len < 5188 (hlen + sizeof(struct tcphdr)))) { 5189 5190 aprint_debug_dev(sc->bge_dev, 5191 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5192 "not handled yet\n", 5193 m0->m_len, hlen+ sizeof(struct tcphdr)); 5194 #ifdef NOTYET 5195 /* 5196 * XXX jonathan (at) NetBSD.org: untested. 5197 * how to force this branch to be taken? 5198 */ 5199 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5200 5201 m_copydata(m0, offset, sizeof(ip), &ip); 5202 m_copydata(m0, hlen, sizeof(th), &th); 5203 5204 ip.ip_len = 0; 5205 5206 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5207 sizeof(ip.ip_len), &ip.ip_len); 5208 5209 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5210 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5211 5212 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5213 sizeof(th.th_sum), &th.th_sum); 5214 5215 hlen += th.th_off << 2; 5216 iptcp_opt_words = hlen; 5217 #else 5218 /* 5219 * if_wm "hard" case not yet supported, can we not 5220 * mandate it out of existence? 5221 */ 5222 (void) ip; (void)th; (void) ip_tcp_hlen; 5223 5224 return ENOBUFS; 5225 #endif 5226 } else { 5227 ip = (struct ip *) (mtod(m0, char *) + offset); 5228 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5229 ip_tcp_hlen = iphl + (th->th_off << 2); 5230 5231 /* Total IP/TCP options, in 32-bit words */ 5232 iptcp_opt_words = (ip_tcp_hlen 5233 - sizeof(struct tcphdr) 5234 - sizeof(struct ip)) >> 2; 5235 } 5236 if (BGE_IS_575X_PLUS(sc)) { 5237 th->th_sum = 0; 5238 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5239 } else { 5240 /* 5241 * XXX jonathan (at) NetBSD.org: 5705 untested. 5242 * Requires TSO firmware patch for 5701/5703/5704. 5243 */ 5244 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5245 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5246 } 5247 5248 mss = m_head->m_pkthdr.segsz; 5249 txbd_tso_flags |= 5250 BGE_TXBDFLAG_CPU_PRE_DMA | 5251 BGE_TXBDFLAG_CPU_POST_DMA; 5252 5253 /* 5254 * Our NIC TSO-assist assumes TSO has standard, optionless 5255 * IPv4 and TCP headers, which total 40 bytes. By default, 5256 * the NIC copies 40 bytes of IP/TCP header from the 5257 * supplied header into the IP/TCP header portion of 5258 * each post-TSO-segment. If the supplied packet has IP or 5259 * TCP options, we need to tell the NIC to copy those extra 5260 * bytes into each post-TSO header, in addition to the normal 5261 * 40-byte IP/TCP header (and to leave space accordingly). 5262 * Unfortunately, the driver encoding of option length 5263 * varies across different ASIC families. 5264 */ 5265 tcp_seg_flags = 0; 5266 if (iptcp_opt_words) { 5267 if (BGE_IS_5705_PLUS(sc)) { 5268 tcp_seg_flags = 5269 iptcp_opt_words << 11; 5270 } else { 5271 txbd_tso_flags |= 5272 iptcp_opt_words << 12; 5273 } 5274 } 5275 maxsegsize = mss | tcp_seg_flags; 5276 ip->ip_len = htons(mss + ip_tcp_hlen); 5277 5278 } /* TSO setup */ 5279 5280 /* 5281 * Start packing the mbufs in this chain into 5282 * the fragment pointers. Stop when we run out 5283 * of fragments or hit the end of the mbuf chain. 5284 */ 5285 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5286 BUS_DMA_NOWAIT); 5287 if (error) 5288 return ENOBUFS; 5289 /* 5290 * Sanity check: avoid coming within 16 descriptors 5291 * of the end of the ring. 5292 */ 5293 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5294 BGE_TSO_PRINTF(("%s: " 5295 " dmamap_load_mbuf too close to ring wrap\n", 5296 device_xname(sc->bge_dev))); 5297 goto fail_unload; 5298 } 5299 5300 mtag = sc->ethercom.ec_nvlans ? 5301 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5302 5303 5304 /* Iterate over dmap-map fragments. */ 5305 for (i = 0; i < dmamap->dm_nsegs; i++) { 5306 f = &sc->bge_rdata->bge_tx_ring[frag]; 5307 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5308 break; 5309 5310 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5311 f->bge_len = dmamap->dm_segs[i].ds_len; 5312 5313 /* 5314 * For 5751 and follow-ons, for TSO we must turn 5315 * off checksum-assist flag in the tx-descr, and 5316 * supply the ASIC-revision-specific encoding 5317 * of TSO flags and segsize. 5318 */ 5319 if (use_tso) { 5320 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5321 f->bge_rsvd = maxsegsize; 5322 f->bge_flags = csum_flags | txbd_tso_flags; 5323 } else { 5324 f->bge_rsvd = 0; 5325 f->bge_flags = 5326 (csum_flags | txbd_tso_flags) & 0x0fff; 5327 } 5328 } else { 5329 f->bge_rsvd = 0; 5330 f->bge_flags = csum_flags; 5331 } 5332 5333 if (mtag != NULL) { 5334 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5335 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5336 } else { 5337 f->bge_vlan_tag = 0; 5338 } 5339 cur = frag; 5340 BGE_INC(frag, BGE_TX_RING_CNT); 5341 } 5342 5343 if (i < dmamap->dm_nsegs) { 5344 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5345 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5346 goto fail_unload; 5347 } 5348 5349 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5350 BUS_DMASYNC_PREWRITE); 5351 5352 if (frag == sc->bge_tx_saved_considx) { 5353 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5354 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5355 5356 goto fail_unload; 5357 } 5358 5359 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5360 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5361 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5362 sc->txdma[cur] = dma; 5363 sc->bge_txcnt += dmamap->dm_nsegs; 5364 5365 *txidx = frag; 5366 5367 return 0; 5368 5369 fail_unload: 5370 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5371 5372 return ENOBUFS; 5373 } 5374 5375 /* 5376 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5377 * to the mbuf data regions directly in the transmit descriptors. 5378 */ 5379 static void 5380 bge_start(struct ifnet *ifp) 5381 { 5382 struct bge_softc *sc; 5383 struct mbuf *m_head = NULL; 5384 uint32_t prodidx; 5385 int pkts = 0; 5386 5387 sc = ifp->if_softc; 5388 5389 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5390 return; 5391 5392 prodidx = sc->bge_tx_prodidx; 5393 5394 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5395 IFQ_POLL(&ifp->if_snd, m_head); 5396 if (m_head == NULL) 5397 break; 5398 5399 #if 0 5400 /* 5401 * XXX 5402 * safety overkill. If this is a fragmented packet chain 5403 * with delayed TCP/UDP checksums, then only encapsulate 5404 * it if we have enough descriptors to handle the entire 5405 * chain at once. 5406 * (paranoia -- may not actually be needed) 5407 */ 5408 if (m_head->m_flags & M_FIRSTFRAG && 5409 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5410 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5411 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5412 ifp->if_flags |= IFF_OACTIVE; 5413 break; 5414 } 5415 } 5416 #endif 5417 5418 /* 5419 * Pack the data into the transmit ring. If we 5420 * don't have room, set the OACTIVE flag and wait 5421 * for the NIC to drain the ring. 5422 */ 5423 if (bge_encap(sc, m_head, &prodidx)) { 5424 ifp->if_flags |= IFF_OACTIVE; 5425 break; 5426 } 5427 5428 /* now we are committed to transmit the packet */ 5429 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5430 pkts++; 5431 5432 /* 5433 * If there's a BPF listener, bounce a copy of this frame 5434 * to him. 5435 */ 5436 bpf_mtap(ifp, m_head); 5437 } 5438 if (pkts == 0) 5439 return; 5440 5441 /* Transmit */ 5442 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5443 /* 5700 b2 errata */ 5444 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5445 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5446 5447 sc->bge_tx_prodidx = prodidx; 5448 5449 /* 5450 * Set a timeout in case the chip goes out to lunch. 5451 */ 5452 ifp->if_timer = 5; 5453 } 5454 5455 static int 5456 bge_init(struct ifnet *ifp) 5457 { 5458 struct bge_softc *sc = ifp->if_softc; 5459 const uint16_t *m; 5460 uint32_t mode, reg; 5461 int s, error = 0; 5462 5463 s = splnet(); 5464 5465 ifp = &sc->ethercom.ec_if; 5466 5467 /* Cancel pending I/O and flush buffers. */ 5468 bge_stop(ifp, 0); 5469 5470 bge_stop_fw(sc); 5471 bge_sig_pre_reset(sc, BGE_RESET_START); 5472 bge_reset(sc); 5473 bge_sig_legacy(sc, BGE_RESET_START); 5474 5475 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5476 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5477 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5478 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5479 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5480 5481 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5482 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5483 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5484 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5485 5486 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5487 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5488 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5489 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5490 5491 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5492 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5493 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5494 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5495 } 5496 5497 bge_sig_post_reset(sc, BGE_RESET_START); 5498 5499 bge_chipinit(sc); 5500 5501 /* 5502 * Init the various state machines, ring 5503 * control blocks and firmware. 5504 */ 5505 error = bge_blockinit(sc); 5506 if (error != 0) { 5507 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5508 error); 5509 splx(s); 5510 return error; 5511 } 5512 5513 ifp = &sc->ethercom.ec_if; 5514 5515 /* 5718 step 25, 57XX step 54 */ 5516 /* Specify MTU. */ 5517 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5518 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5519 5520 /* 5718 step 23 */ 5521 /* Load our MAC address. */ 5522 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5523 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5524 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5525 5526 /* Enable or disable promiscuous mode as needed. */ 5527 if (ifp->if_flags & IFF_PROMISC) 5528 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5529 else 5530 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5531 5532 /* Program multicast filter. */ 5533 bge_setmulti(sc); 5534 5535 /* Init RX ring. */ 5536 bge_init_rx_ring_std(sc); 5537 5538 /* 5539 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5540 * memory to insure that the chip has in fact read the first 5541 * entry of the ring. 5542 */ 5543 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5544 uint32_t v, i; 5545 for (i = 0; i < 10; i++) { 5546 DELAY(20); 5547 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5548 if (v == (MCLBYTES - ETHER_ALIGN)) 5549 break; 5550 } 5551 if (i == 10) 5552 aprint_error_dev(sc->bge_dev, 5553 "5705 A0 chip failed to load RX ring\n"); 5554 } 5555 5556 /* Init jumbo RX ring. */ 5557 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5558 bge_init_rx_ring_jumbo(sc); 5559 5560 /* Init our RX return ring index */ 5561 sc->bge_rx_saved_considx = 0; 5562 5563 /* Init TX ring. */ 5564 bge_init_tx_ring(sc); 5565 5566 /* 5718 step 63, 57XX step 94 */ 5567 /* Enable TX MAC state machine lockup fix. */ 5568 mode = CSR_READ_4(sc, BGE_TX_MODE); 5569 if (BGE_IS_5755_PLUS(sc) || 5570 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5571 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5572 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5573 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5574 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5575 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5576 } 5577 5578 /* Turn on transmitter */ 5579 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5580 /* 5718 step 64 */ 5581 DELAY(100); 5582 5583 /* 5718 step 65, 57XX step 95 */ 5584 /* Turn on receiver */ 5585 mode = CSR_READ_4(sc, BGE_RX_MODE); 5586 if (BGE_IS_5755_PLUS(sc)) 5587 mode |= BGE_RXMODE_IPV6_ENABLE; 5588 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5589 /* 5718 step 66 */ 5590 DELAY(10); 5591 5592 /* 5718 step 12, 57XX step 37 */ 5593 /* 5594 * XXX Doucments of 5718 series and 577xx say the recommended value 5595 * is 1, but tg3 set 1 only on 57765 series. 5596 */ 5597 if (BGE_IS_57765_PLUS(sc)) 5598 reg = 1; 5599 else 5600 reg = 2; 5601 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5602 5603 /* Tell firmware we're alive. */ 5604 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5605 5606 /* Enable host interrupts. */ 5607 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5608 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5609 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5610 5611 if ((error = bge_ifmedia_upd(ifp)) != 0) 5612 goto out; 5613 5614 ifp->if_flags |= IFF_RUNNING; 5615 ifp->if_flags &= ~IFF_OACTIVE; 5616 5617 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5618 5619 out: 5620 sc->bge_if_flags = ifp->if_flags; 5621 splx(s); 5622 5623 return error; 5624 } 5625 5626 /* 5627 * Set media options. 5628 */ 5629 static int 5630 bge_ifmedia_upd(struct ifnet *ifp) 5631 { 5632 struct bge_softc *sc = ifp->if_softc; 5633 struct mii_data *mii = &sc->bge_mii; 5634 struct ifmedia *ifm = &sc->bge_ifmedia; 5635 int rc; 5636 5637 /* If this is a 1000baseX NIC, enable the TBI port. */ 5638 if (sc->bge_flags & BGEF_FIBER_TBI) { 5639 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5640 return EINVAL; 5641 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5642 case IFM_AUTO: 5643 /* 5644 * The BCM5704 ASIC appears to have a special 5645 * mechanism for programming the autoneg 5646 * advertisement registers in TBI mode. 5647 */ 5648 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5649 uint32_t sgdig; 5650 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5651 if (sgdig & BGE_SGDIGSTS_DONE) { 5652 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5653 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5654 sgdig |= BGE_SGDIGCFG_AUTO | 5655 BGE_SGDIGCFG_PAUSE_CAP | 5656 BGE_SGDIGCFG_ASYM_PAUSE; 5657 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5658 sgdig | BGE_SGDIGCFG_SEND); 5659 DELAY(5); 5660 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5661 sgdig); 5662 } 5663 } 5664 break; 5665 case IFM_1000_SX: 5666 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5667 BGE_CLRBIT(sc, BGE_MAC_MODE, 5668 BGE_MACMODE_HALF_DUPLEX); 5669 } else { 5670 BGE_SETBIT(sc, BGE_MAC_MODE, 5671 BGE_MACMODE_HALF_DUPLEX); 5672 } 5673 DELAY(40); 5674 break; 5675 default: 5676 return EINVAL; 5677 } 5678 /* XXX 802.3x flow control for 1000BASE-SX */ 5679 return 0; 5680 } 5681 5682 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5683 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5684 uint32_t reg; 5685 5686 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5687 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5688 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5689 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5690 } 5691 } 5692 5693 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5694 if ((rc = mii_mediachg(mii)) == ENXIO) 5695 return 0; 5696 5697 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5698 uint32_t reg; 5699 5700 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5701 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5702 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5703 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5704 delay(40); 5705 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5706 } 5707 } 5708 5709 /* 5710 * Force an interrupt so that we will call bge_link_upd 5711 * if needed and clear any pending link state attention. 5712 * Without this we are not getting any further interrupts 5713 * for link state changes and thus will not UP the link and 5714 * not be able to send in bge_start. The only way to get 5715 * things working was to receive a packet and get a RX intr. 5716 */ 5717 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5718 sc->bge_flags & BGEF_IS_5788) 5719 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5720 else 5721 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5722 5723 return rc; 5724 } 5725 5726 /* 5727 * Report current media status. 5728 */ 5729 static void 5730 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5731 { 5732 struct bge_softc *sc = ifp->if_softc; 5733 struct mii_data *mii = &sc->bge_mii; 5734 5735 if (sc->bge_flags & BGEF_FIBER_TBI) { 5736 ifmr->ifm_status = IFM_AVALID; 5737 ifmr->ifm_active = IFM_ETHER; 5738 if (CSR_READ_4(sc, BGE_MAC_STS) & 5739 BGE_MACSTAT_TBI_PCS_SYNCHED) 5740 ifmr->ifm_status |= IFM_ACTIVE; 5741 ifmr->ifm_active |= IFM_1000_SX; 5742 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5743 ifmr->ifm_active |= IFM_HDX; 5744 else 5745 ifmr->ifm_active |= IFM_FDX; 5746 return; 5747 } 5748 5749 mii_pollstat(mii); 5750 ifmr->ifm_status = mii->mii_media_status; 5751 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5752 sc->bge_flowflags; 5753 } 5754 5755 static int 5756 bge_ifflags_cb(struct ethercom *ec) 5757 { 5758 struct ifnet *ifp = &ec->ec_if; 5759 struct bge_softc *sc = ifp->if_softc; 5760 int change = ifp->if_flags ^ sc->bge_if_flags; 5761 5762 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5763 return ENETRESET; 5764 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5765 return 0; 5766 5767 if ((ifp->if_flags & IFF_PROMISC) == 0) 5768 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5769 else 5770 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5771 5772 bge_setmulti(sc); 5773 5774 sc->bge_if_flags = ifp->if_flags; 5775 return 0; 5776 } 5777 5778 static int 5779 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5780 { 5781 struct bge_softc *sc = ifp->if_softc; 5782 struct ifreq *ifr = (struct ifreq *) data; 5783 int s, error = 0; 5784 struct mii_data *mii; 5785 5786 s = splnet(); 5787 5788 switch (command) { 5789 case SIOCSIFMEDIA: 5790 /* XXX Flow control is not supported for 1000BASE-SX */ 5791 if (sc->bge_flags & BGEF_FIBER_TBI) { 5792 ifr->ifr_media &= ~IFM_ETH_FMASK; 5793 sc->bge_flowflags = 0; 5794 } 5795 5796 /* Flow control requires full-duplex mode. */ 5797 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5798 (ifr->ifr_media & IFM_FDX) == 0) { 5799 ifr->ifr_media &= ~IFM_ETH_FMASK; 5800 } 5801 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5802 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5803 /* We can do both TXPAUSE and RXPAUSE. */ 5804 ifr->ifr_media |= 5805 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5806 } 5807 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5808 } 5809 /* FALLTHROUGH */ 5810 case SIOCGIFMEDIA: 5811 if (sc->bge_flags & BGEF_FIBER_TBI) { 5812 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5813 command); 5814 } else { 5815 mii = &sc->bge_mii; 5816 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5817 command); 5818 } 5819 break; 5820 default: 5821 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5822 break; 5823 5824 error = 0; 5825 5826 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5827 ; 5828 else if (ifp->if_flags & IFF_RUNNING) 5829 bge_setmulti(sc); 5830 break; 5831 } 5832 5833 splx(s); 5834 5835 return error; 5836 } 5837 5838 static void 5839 bge_watchdog(struct ifnet *ifp) 5840 { 5841 struct bge_softc *sc; 5842 5843 sc = ifp->if_softc; 5844 5845 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5846 5847 ifp->if_flags &= ~IFF_RUNNING; 5848 bge_init(ifp); 5849 5850 ifp->if_oerrors++; 5851 } 5852 5853 static void 5854 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5855 { 5856 int i; 5857 5858 BGE_CLRBIT_FLUSH(sc, reg, bit); 5859 5860 for (i = 0; i < 1000; i++) { 5861 delay(100); 5862 if ((CSR_READ_4(sc, reg) & bit) == 0) 5863 return; 5864 } 5865 5866 /* 5867 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5868 * on some environment (and once after boot?) 5869 */ 5870 if (reg != BGE_SRS_MODE) 5871 aprint_error_dev(sc->bge_dev, 5872 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5873 (u_long)reg, bit); 5874 } 5875 5876 /* 5877 * Stop the adapter and free any mbufs allocated to the 5878 * RX and TX lists. 5879 */ 5880 static void 5881 bge_stop(struct ifnet *ifp, int disable) 5882 { 5883 struct bge_softc *sc = ifp->if_softc; 5884 5885 if (disable) 5886 callout_halt(&sc->bge_timeout, NULL); 5887 else 5888 callout_stop(&sc->bge_timeout); 5889 5890 /* Disable host interrupts. */ 5891 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5892 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5893 5894 /* 5895 * Tell firmware we're shutting down. 5896 */ 5897 bge_stop_fw(sc); 5898 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5899 5900 /* 5901 * Disable all of the receiver blocks. 5902 */ 5903 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5904 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5905 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5906 if (BGE_IS_5700_FAMILY(sc)) 5907 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5908 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5909 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5910 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5911 5912 /* 5913 * Disable all of the transmit blocks. 5914 */ 5915 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5916 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5917 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5918 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5919 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5920 if (BGE_IS_5700_FAMILY(sc)) 5921 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5922 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5923 5924 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5925 delay(40); 5926 5927 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5928 5929 /* 5930 * Shut down all of the memory managers and related 5931 * state machines. 5932 */ 5933 /* 5718 step 5a,5b */ 5934 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5935 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5936 if (BGE_IS_5700_FAMILY(sc)) 5937 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5938 5939 /* 5718 step 5c,5d */ 5940 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5941 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5942 5943 if (BGE_IS_5700_FAMILY(sc)) { 5944 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5945 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5946 } 5947 5948 bge_reset(sc); 5949 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5950 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5951 5952 /* 5953 * Keep the ASF firmware running if up. 5954 */ 5955 if (sc->bge_asf_mode & ASF_STACKUP) 5956 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5957 else 5958 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5959 5960 /* Free the RX lists. */ 5961 bge_free_rx_ring_std(sc); 5962 5963 /* Free jumbo RX list. */ 5964 if (BGE_IS_JUMBO_CAPABLE(sc)) 5965 bge_free_rx_ring_jumbo(sc); 5966 5967 /* Free TX buffers. */ 5968 bge_free_tx_ring(sc); 5969 5970 /* 5971 * Isolate/power down the PHY. 5972 */ 5973 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 5974 mii_down(&sc->bge_mii); 5975 5976 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5977 5978 /* Clear MAC's link state (PHY may still have link UP). */ 5979 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5980 5981 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5982 } 5983 5984 static void 5985 bge_link_upd(struct bge_softc *sc) 5986 { 5987 struct ifnet *ifp = &sc->ethercom.ec_if; 5988 struct mii_data *mii = &sc->bge_mii; 5989 uint32_t status; 5990 int link; 5991 5992 /* Clear 'pending link event' flag */ 5993 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5994 5995 /* 5996 * Process link state changes. 5997 * Grrr. The link status word in the status block does 5998 * not work correctly on the BCM5700 rev AX and BX chips, 5999 * according to all available information. Hence, we have 6000 * to enable MII interrupts in order to properly obtain 6001 * async link changes. Unfortunately, this also means that 6002 * we have to read the MAC status register to detect link 6003 * changes, thereby adding an additional register access to 6004 * the interrupt handler. 6005 */ 6006 6007 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6008 status = CSR_READ_4(sc, BGE_MAC_STS); 6009 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6010 mii_pollstat(mii); 6011 6012 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6013 mii->mii_media_status & IFM_ACTIVE && 6014 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6015 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6016 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6017 (!(mii->mii_media_status & IFM_ACTIVE) || 6018 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6019 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6020 6021 /* Clear the interrupt */ 6022 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6023 BGE_EVTENB_MI_INTERRUPT); 6024 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6025 BRGPHY_MII_ISR); 6026 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6027 BRGPHY_MII_IMR, BRGPHY_INTRS); 6028 } 6029 return; 6030 } 6031 6032 if (sc->bge_flags & BGEF_FIBER_TBI) { 6033 status = CSR_READ_4(sc, BGE_MAC_STS); 6034 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6035 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6036 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6037 if (BGE_ASICREV(sc->bge_chipid) 6038 == BGE_ASICREV_BCM5704) { 6039 BGE_CLRBIT(sc, BGE_MAC_MODE, 6040 BGE_MACMODE_TBI_SEND_CFGS); 6041 DELAY(40); 6042 } 6043 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6044 if_link_state_change(ifp, LINK_STATE_UP); 6045 } 6046 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6047 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6048 if_link_state_change(ifp, LINK_STATE_DOWN); 6049 } 6050 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6051 /* 6052 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6053 * bit in status word always set. Workaround this bug by 6054 * reading PHY link status directly. 6055 */ 6056 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6057 BGE_STS_LINK : 0; 6058 6059 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6060 mii_pollstat(mii); 6061 6062 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6063 mii->mii_media_status & IFM_ACTIVE && 6064 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6065 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6066 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6067 (!(mii->mii_media_status & IFM_ACTIVE) || 6068 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6069 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6070 } 6071 } else { 6072 /* 6073 * For controllers that call mii_tick, we have to poll 6074 * link status. 6075 */ 6076 mii_pollstat(mii); 6077 } 6078 6079 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6080 uint32_t reg, scale; 6081 6082 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6083 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6084 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6085 scale = 65; 6086 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6087 scale = 6; 6088 else 6089 scale = 12; 6090 6091 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6092 ~BGE_MISCCFG_TIMER_PRESCALER; 6093 reg |= scale << 1; 6094 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6095 } 6096 /* Clear the attention */ 6097 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6098 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6099 BGE_MACSTAT_LINK_CHANGED); 6100 } 6101 6102 static int 6103 bge_sysctl_verify(SYSCTLFN_ARGS) 6104 { 6105 int error, t; 6106 struct sysctlnode node; 6107 6108 node = *rnode; 6109 t = *(int*)rnode->sysctl_data; 6110 node.sysctl_data = &t; 6111 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6112 if (error || newp == NULL) 6113 return error; 6114 6115 #if 0 6116 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6117 node.sysctl_num, rnode->sysctl_num)); 6118 #endif 6119 6120 if (node.sysctl_num == bge_rxthresh_nodenum) { 6121 if (t < 0 || t >= NBGE_RX_THRESH) 6122 return EINVAL; 6123 bge_update_all_threshes(t); 6124 } else 6125 return EINVAL; 6126 6127 *(int*)rnode->sysctl_data = t; 6128 6129 return 0; 6130 } 6131 6132 /* 6133 * Set up sysctl(3) MIB, hw.bge.*. 6134 */ 6135 static void 6136 bge_sysctl_init(struct bge_softc *sc) 6137 { 6138 int rc, bge_root_num; 6139 const struct sysctlnode *node; 6140 6141 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6142 0, CTLTYPE_NODE, "bge", 6143 SYSCTL_DESCR("BGE interface controls"), 6144 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6145 goto out; 6146 } 6147 6148 bge_root_num = node->sysctl_num; 6149 6150 /* BGE Rx interrupt mitigation level */ 6151 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6152 CTLFLAG_READWRITE, 6153 CTLTYPE_INT, "rx_lvl", 6154 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6155 bge_sysctl_verify, 0, 6156 &bge_rx_thresh_lvl, 6157 0, CTL_HW, bge_root_num, CTL_CREATE, 6158 CTL_EOL)) != 0) { 6159 goto out; 6160 } 6161 6162 bge_rxthresh_nodenum = node->sysctl_num; 6163 6164 return; 6165 6166 out: 6167 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6168 } 6169 6170 #ifdef BGE_DEBUG 6171 void 6172 bge_debug_info(struct bge_softc *sc) 6173 { 6174 6175 printf("Hardware Flags:\n"); 6176 if (BGE_IS_57765_PLUS(sc)) 6177 printf(" - 57765 Plus\n"); 6178 if (BGE_IS_5717_PLUS(sc)) 6179 printf(" - 5717 Plus\n"); 6180 if (BGE_IS_5755_PLUS(sc)) 6181 printf(" - 5755 Plus\n"); 6182 if (BGE_IS_575X_PLUS(sc)) 6183 printf(" - 575X Plus\n"); 6184 if (BGE_IS_5705_PLUS(sc)) 6185 printf(" - 5705 Plus\n"); 6186 if (BGE_IS_5714_FAMILY(sc)) 6187 printf(" - 5714 Family\n"); 6188 if (BGE_IS_5700_FAMILY(sc)) 6189 printf(" - 5700 Family\n"); 6190 if (sc->bge_flags & BGEF_IS_5788) 6191 printf(" - 5788\n"); 6192 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6193 printf(" - Supports Jumbo Frames\n"); 6194 if (sc->bge_flags & BGEF_NO_EEPROM) 6195 printf(" - No EEPROM\n"); 6196 if (sc->bge_flags & BGEF_PCIX) 6197 printf(" - PCI-X Bus\n"); 6198 if (sc->bge_flags & BGEF_PCIE) 6199 printf(" - PCI Express Bus\n"); 6200 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6201 printf(" - RX Alignment Bug\n"); 6202 if (sc->bge_flags & BGEF_APE) 6203 printf(" - APE\n"); 6204 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6205 printf(" - CPMU\n"); 6206 if (sc->bge_flags & BGEF_TSO) 6207 printf(" - TSO\n"); 6208 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6209 printf(" - TAGGED_STATUS\n"); 6210 6211 /* PHY related */ 6212 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6213 printf(" - No 3 LEDs\n"); 6214 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6215 printf(" - CRC bug\n"); 6216 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6217 printf(" - ADC bug\n"); 6218 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6219 printf(" - 5704 A0 bug\n"); 6220 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6221 printf(" - jitter bug\n"); 6222 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6223 printf(" - BER bug\n"); 6224 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6225 printf(" - adjust trim\n"); 6226 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6227 printf(" - no wirespeed\n"); 6228 6229 /* ASF related */ 6230 if (sc->bge_asf_mode & ASF_ENABLE) 6231 printf(" - ASF enable\n"); 6232 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6233 printf(" - ASF new handshake\n"); 6234 if (sc->bge_asf_mode & ASF_STACKUP) 6235 printf(" - ASF stackup\n"); 6236 } 6237 #endif /* BGE_DEBUG */ 6238 6239 static int 6240 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6241 { 6242 prop_dictionary_t dict; 6243 prop_data_t ea; 6244 6245 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6246 return 1; 6247 6248 dict = device_properties(sc->bge_dev); 6249 ea = prop_dictionary_get(dict, "mac-address"); 6250 if (ea != NULL) { 6251 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6252 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6253 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6254 return 0; 6255 } 6256 6257 return 1; 6258 } 6259 6260 static int 6261 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6262 { 6263 uint32_t mac_addr; 6264 6265 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6266 if ((mac_addr >> 16) == 0x484b) { 6267 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6268 ether_addr[1] = (uint8_t)mac_addr; 6269 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6270 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6271 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6272 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6273 ether_addr[5] = (uint8_t)mac_addr; 6274 return 0; 6275 } 6276 return 1; 6277 } 6278 6279 static int 6280 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6281 { 6282 int mac_offset = BGE_EE_MAC_OFFSET; 6283 6284 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6285 mac_offset = BGE_EE_MAC_OFFSET_5906; 6286 6287 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6288 ETHER_ADDR_LEN)); 6289 } 6290 6291 static int 6292 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6293 { 6294 6295 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6296 return 1; 6297 6298 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6299 ETHER_ADDR_LEN)); 6300 } 6301 6302 static int 6303 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6304 { 6305 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6306 /* NOTE: Order is critical */ 6307 bge_get_eaddr_fw, 6308 bge_get_eaddr_mem, 6309 bge_get_eaddr_nvram, 6310 bge_get_eaddr_eeprom, 6311 NULL 6312 }; 6313 const bge_eaddr_fcn_t *func; 6314 6315 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6316 if ((*func)(sc, eaddr) == 0) 6317 break; 6318 } 6319 return (*func == NULL ? ENXIO : 0); 6320 } 6321
Indexes created Tue Sep 23 21:09:50 GMT 2025