if_bge.c revision 1.292
1 /* $NetBSD: if_bge.c,v 1.292 2015/06/14 08:46:33 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.292 2015/06/14 08:46:33 martin Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 #ifdef __HAVE_PCI_MSI_MSIX 187 static int bge_can_use_msi(struct bge_softc *); 188 #endif 189 static int bge_probe(device_t, cfdata_t, void *); 190 static void bge_attach(device_t, device_t, void *); 191 static int bge_detach(device_t, int); 192 static void bge_release_resources(struct bge_softc *); 193 194 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 198 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 199 200 static void bge_txeof(struct bge_softc *); 201 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 202 static void bge_rxeof(struct bge_softc *); 203 204 static void bge_asf_driver_up (struct bge_softc *); 205 static void bge_tick(void *); 206 static void bge_stats_update(struct bge_softc *); 207 static void bge_stats_update_regs(struct bge_softc *); 208 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 209 210 static int bge_intr(void *); 211 static void bge_start(struct ifnet *); 212 static int bge_ifflags_cb(struct ethercom *); 213 static int bge_ioctl(struct ifnet *, u_long, void *); 214 static int bge_init(struct ifnet *); 215 static void bge_stop(struct ifnet *, int); 216 static void bge_watchdog(struct ifnet *); 217 static int bge_ifmedia_upd(struct ifnet *); 218 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 219 220 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 222 223 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 224 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 225 static void bge_setmulti(struct bge_softc *); 226 227 static void bge_handle_events(struct bge_softc *); 228 static int bge_alloc_jumbo_mem(struct bge_softc *); 229 #if 0 /* XXX */ 230 static void bge_free_jumbo_mem(struct bge_softc *); 231 #endif 232 static void *bge_jalloc(struct bge_softc *); 233 static void bge_jfree(struct mbuf *, void *, size_t, void *); 234 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 235 bus_dmamap_t); 236 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 237 static int bge_init_rx_ring_std(struct bge_softc *); 238 static void bge_free_rx_ring_std(struct bge_softc *); 239 static int bge_init_rx_ring_jumbo(struct bge_softc *); 240 static void bge_free_rx_ring_jumbo(struct bge_softc *); 241 static void bge_free_tx_ring(struct bge_softc *); 242 static int bge_init_tx_ring(struct bge_softc *); 243 244 static int bge_chipinit(struct bge_softc *); 245 static int bge_blockinit(struct bge_softc *); 246 static int bge_phy_addr(struct bge_softc *); 247 static uint32_t bge_readmem_ind(struct bge_softc *, int); 248 static void bge_writemem_ind(struct bge_softc *, int, int); 249 static void bge_writembx(struct bge_softc *, int, int); 250 static void bge_writembx_flush(struct bge_softc *, int, int); 251 static void bge_writemem_direct(struct bge_softc *, int, int); 252 static void bge_writereg_ind(struct bge_softc *, int, int); 253 static void bge_set_max_readrq(struct bge_softc *); 254 255 static int bge_miibus_readreg(device_t, int, int); 256 static void bge_miibus_writereg(device_t, int, int, int); 257 static void bge_miibus_statchg(struct ifnet *); 258 259 #define BGE_RESET_SHUTDOWN 0 260 #define BGE_RESET_START 1 261 #define BGE_RESET_SUSPEND 2 262 static void bge_sig_post_reset(struct bge_softc *, int); 263 static void bge_sig_legacy(struct bge_softc *, int); 264 static void bge_sig_pre_reset(struct bge_softc *, int); 265 static void bge_wait_for_event_ack(struct bge_softc *); 266 static void bge_stop_fw(struct bge_softc *); 267 static int bge_reset(struct bge_softc *); 268 static void bge_link_upd(struct bge_softc *); 269 static void bge_sysctl_init(struct bge_softc *); 270 static int bge_sysctl_verify(SYSCTLFN_PROTO); 271 272 static void bge_ape_lock_init(struct bge_softc *); 273 static void bge_ape_read_fw_ver(struct bge_softc *); 274 static int bge_ape_lock(struct bge_softc *, int); 275 static void bge_ape_unlock(struct bge_softc *, int); 276 static void bge_ape_send_event(struct bge_softc *, uint32_t); 277 static void bge_ape_driver_state_change(struct bge_softc *, int); 278 279 #ifdef BGE_DEBUG 280 #define DPRINTF(x) if (bgedebug) printf x 281 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 282 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 283 int bgedebug = 0; 284 int bge_tso_debug = 0; 285 void bge_debug_info(struct bge_softc *); 286 #else 287 #define DPRINTF(x) 288 #define DPRINTFN(n,x) 289 #define BGE_TSO_PRINTF(x) 290 #endif 291 292 #ifdef BGE_EVENT_COUNTERS 293 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 294 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 295 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 296 #else 297 #define BGE_EVCNT_INCR(ev) /* nothing */ 298 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 299 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 300 #endif 301 302 static const struct bge_product { 303 pci_vendor_id_t bp_vendor; 304 pci_product_id_t bp_product; 305 const char *bp_name; 306 } bge_products[] = { 307 /* 308 * The BCM5700 documentation seems to indicate that the hardware 309 * still has the Alteon vendor ID burned into it, though it 310 * should always be overridden by the value in the EEPROM. We'll 311 * check for it anyway. 312 */ 313 { PCI_VENDOR_ALTEON, 314 PCI_PRODUCT_ALTEON_BCM5700, 315 "Broadcom BCM5700 Gigabit Ethernet", 316 }, 317 { PCI_VENDOR_ALTEON, 318 PCI_PRODUCT_ALTEON_BCM5701, 319 "Broadcom BCM5701 Gigabit Ethernet", 320 }, 321 { PCI_VENDOR_ALTIMA, 322 PCI_PRODUCT_ALTIMA_AC1000, 323 "Altima AC1000 Gigabit Ethernet", 324 }, 325 { PCI_VENDOR_ALTIMA, 326 PCI_PRODUCT_ALTIMA_AC1001, 327 "Altima AC1001 Gigabit Ethernet", 328 }, 329 { PCI_VENDOR_ALTIMA, 330 PCI_PRODUCT_ALTIMA_AC1003, 331 "Altima AC1003 Gigabit Ethernet", 332 }, 333 { PCI_VENDOR_ALTIMA, 334 PCI_PRODUCT_ALTIMA_AC9100, 335 "Altima AC9100 Gigabit Ethernet", 336 }, 337 { PCI_VENDOR_APPLE, 338 PCI_PRODUCT_APPLE_BCM5701, 339 "APPLE BCM5701 Gigabit Ethernet", 340 }, 341 { PCI_VENDOR_BROADCOM, 342 PCI_PRODUCT_BROADCOM_BCM5700, 343 "Broadcom BCM5700 Gigabit Ethernet", 344 }, 345 { PCI_VENDOR_BROADCOM, 346 PCI_PRODUCT_BROADCOM_BCM5701, 347 "Broadcom BCM5701 Gigabit Ethernet", 348 }, 349 { PCI_VENDOR_BROADCOM, 350 PCI_PRODUCT_BROADCOM_BCM5702, 351 "Broadcom BCM5702 Gigabit Ethernet", 352 }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5702X, 355 "Broadcom BCM5702X Gigabit Ethernet" }, 356 { PCI_VENDOR_BROADCOM, 357 PCI_PRODUCT_BROADCOM_BCM5703, 358 "Broadcom BCM5703 Gigabit Ethernet", 359 }, 360 { PCI_VENDOR_BROADCOM, 361 PCI_PRODUCT_BROADCOM_BCM5703X, 362 "Broadcom BCM5703X Gigabit Ethernet", 363 }, 364 { PCI_VENDOR_BROADCOM, 365 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 366 "Broadcom BCM5703 Gigabit Ethernet", 367 }, 368 { PCI_VENDOR_BROADCOM, 369 PCI_PRODUCT_BROADCOM_BCM5704C, 370 "Broadcom BCM5704C Dual Gigabit Ethernet", 371 }, 372 { PCI_VENDOR_BROADCOM, 373 PCI_PRODUCT_BROADCOM_BCM5704S, 374 "Broadcom BCM5704S Dual Gigabit Ethernet", 375 }, 376 { PCI_VENDOR_BROADCOM, 377 PCI_PRODUCT_BROADCOM_BCM5705, 378 "Broadcom BCM5705 Gigabit Ethernet", 379 }, 380 { PCI_VENDOR_BROADCOM, 381 PCI_PRODUCT_BROADCOM_BCM5705F, 382 "Broadcom BCM5705F Gigabit Ethernet", 383 }, 384 { PCI_VENDOR_BROADCOM, 385 PCI_PRODUCT_BROADCOM_BCM5705K, 386 "Broadcom BCM5705K Gigabit Ethernet", 387 }, 388 { PCI_VENDOR_BROADCOM, 389 PCI_PRODUCT_BROADCOM_BCM5705M, 390 "Broadcom BCM5705M Gigabit Ethernet", 391 }, 392 { PCI_VENDOR_BROADCOM, 393 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 394 "Broadcom BCM5705M Gigabit Ethernet", 395 }, 396 { PCI_VENDOR_BROADCOM, 397 PCI_PRODUCT_BROADCOM_BCM5714, 398 "Broadcom BCM5714 Gigabit Ethernet", 399 }, 400 { PCI_VENDOR_BROADCOM, 401 PCI_PRODUCT_BROADCOM_BCM5714S, 402 "Broadcom BCM5714S Gigabit Ethernet", 403 }, 404 { PCI_VENDOR_BROADCOM, 405 PCI_PRODUCT_BROADCOM_BCM5715, 406 "Broadcom BCM5715 Gigabit Ethernet", 407 }, 408 { PCI_VENDOR_BROADCOM, 409 PCI_PRODUCT_BROADCOM_BCM5715S, 410 "Broadcom BCM5715S Gigabit Ethernet", 411 }, 412 { PCI_VENDOR_BROADCOM, 413 PCI_PRODUCT_BROADCOM_BCM5717, 414 "Broadcom BCM5717 Gigabit Ethernet", 415 }, 416 { PCI_VENDOR_BROADCOM, 417 PCI_PRODUCT_BROADCOM_BCM5718, 418 "Broadcom BCM5718 Gigabit Ethernet", 419 }, 420 { PCI_VENDOR_BROADCOM, 421 PCI_PRODUCT_BROADCOM_BCM5719, 422 "Broadcom BCM5719 Gigabit Ethernet", 423 }, 424 { PCI_VENDOR_BROADCOM, 425 PCI_PRODUCT_BROADCOM_BCM5720, 426 "Broadcom BCM5720 Gigabit Ethernet", 427 }, 428 { PCI_VENDOR_BROADCOM, 429 PCI_PRODUCT_BROADCOM_BCM5721, 430 "Broadcom BCM5721 Gigabit Ethernet", 431 }, 432 { PCI_VENDOR_BROADCOM, 433 PCI_PRODUCT_BROADCOM_BCM5722, 434 "Broadcom BCM5722 Gigabit Ethernet", 435 }, 436 { PCI_VENDOR_BROADCOM, 437 PCI_PRODUCT_BROADCOM_BCM5723, 438 "Broadcom BCM5723 Gigabit Ethernet", 439 }, 440 { PCI_VENDOR_BROADCOM, 441 PCI_PRODUCT_BROADCOM_BCM5750, 442 "Broadcom BCM5750 Gigabit Ethernet", 443 }, 444 { PCI_VENDOR_BROADCOM, 445 PCI_PRODUCT_BROADCOM_BCM5751, 446 "Broadcom BCM5751 Gigabit Ethernet", 447 }, 448 { PCI_VENDOR_BROADCOM, 449 PCI_PRODUCT_BROADCOM_BCM5751F, 450 "Broadcom BCM5751F Gigabit Ethernet", 451 }, 452 { PCI_VENDOR_BROADCOM, 453 PCI_PRODUCT_BROADCOM_BCM5751M, 454 "Broadcom BCM5751M Gigabit Ethernet", 455 }, 456 { PCI_VENDOR_BROADCOM, 457 PCI_PRODUCT_BROADCOM_BCM5752, 458 "Broadcom BCM5752 Gigabit Ethernet", 459 }, 460 { PCI_VENDOR_BROADCOM, 461 PCI_PRODUCT_BROADCOM_BCM5752M, 462 "Broadcom BCM5752M Gigabit Ethernet", 463 }, 464 { PCI_VENDOR_BROADCOM, 465 PCI_PRODUCT_BROADCOM_BCM5753, 466 "Broadcom BCM5753 Gigabit Ethernet", 467 }, 468 { PCI_VENDOR_BROADCOM, 469 PCI_PRODUCT_BROADCOM_BCM5753F, 470 "Broadcom BCM5753F Gigabit Ethernet", 471 }, 472 { PCI_VENDOR_BROADCOM, 473 PCI_PRODUCT_BROADCOM_BCM5753M, 474 "Broadcom BCM5753M Gigabit Ethernet", 475 }, 476 { PCI_VENDOR_BROADCOM, 477 PCI_PRODUCT_BROADCOM_BCM5754, 478 "Broadcom BCM5754 Gigabit Ethernet", 479 }, 480 { PCI_VENDOR_BROADCOM, 481 PCI_PRODUCT_BROADCOM_BCM5754M, 482 "Broadcom BCM5754M Gigabit Ethernet", 483 }, 484 { PCI_VENDOR_BROADCOM, 485 PCI_PRODUCT_BROADCOM_BCM5755, 486 "Broadcom BCM5755 Gigabit Ethernet", 487 }, 488 { PCI_VENDOR_BROADCOM, 489 PCI_PRODUCT_BROADCOM_BCM5755M, 490 "Broadcom BCM5755M Gigabit Ethernet", 491 }, 492 { PCI_VENDOR_BROADCOM, 493 PCI_PRODUCT_BROADCOM_BCM5756, 494 "Broadcom BCM5756 Gigabit Ethernet", 495 }, 496 { PCI_VENDOR_BROADCOM, 497 PCI_PRODUCT_BROADCOM_BCM5761, 498 "Broadcom BCM5761 Gigabit Ethernet", 499 }, 500 { PCI_VENDOR_BROADCOM, 501 PCI_PRODUCT_BROADCOM_BCM5761E, 502 "Broadcom BCM5761E Gigabit Ethernet", 503 }, 504 { PCI_VENDOR_BROADCOM, 505 PCI_PRODUCT_BROADCOM_BCM5761S, 506 "Broadcom BCM5761S Gigabit Ethernet", 507 }, 508 { PCI_VENDOR_BROADCOM, 509 PCI_PRODUCT_BROADCOM_BCM5761SE, 510 "Broadcom BCM5761SE Gigabit Ethernet", 511 }, 512 { PCI_VENDOR_BROADCOM, 513 PCI_PRODUCT_BROADCOM_BCM5764, 514 "Broadcom BCM5764 Gigabit Ethernet", 515 }, 516 { PCI_VENDOR_BROADCOM, 517 PCI_PRODUCT_BROADCOM_BCM5780, 518 "Broadcom BCM5780 Gigabit Ethernet", 519 }, 520 { PCI_VENDOR_BROADCOM, 521 PCI_PRODUCT_BROADCOM_BCM5780S, 522 "Broadcom BCM5780S Gigabit Ethernet", 523 }, 524 { PCI_VENDOR_BROADCOM, 525 PCI_PRODUCT_BROADCOM_BCM5781, 526 "Broadcom BCM5781 Gigabit Ethernet", 527 }, 528 { PCI_VENDOR_BROADCOM, 529 PCI_PRODUCT_BROADCOM_BCM5782, 530 "Broadcom BCM5782 Gigabit Ethernet", 531 }, 532 { PCI_VENDOR_BROADCOM, 533 PCI_PRODUCT_BROADCOM_BCM5784M, 534 "BCM5784M NetLink 1000baseT Ethernet", 535 }, 536 { PCI_VENDOR_BROADCOM, 537 PCI_PRODUCT_BROADCOM_BCM5785F, 538 "BCM5785F NetLink 10/100 Ethernet", 539 }, 540 { PCI_VENDOR_BROADCOM, 541 PCI_PRODUCT_BROADCOM_BCM5785G, 542 "BCM5785G NetLink 1000baseT Ethernet", 543 }, 544 { PCI_VENDOR_BROADCOM, 545 PCI_PRODUCT_BROADCOM_BCM5786, 546 "Broadcom BCM5786 Gigabit Ethernet", 547 }, 548 { PCI_VENDOR_BROADCOM, 549 PCI_PRODUCT_BROADCOM_BCM5787, 550 "Broadcom BCM5787 Gigabit Ethernet", 551 }, 552 { PCI_VENDOR_BROADCOM, 553 PCI_PRODUCT_BROADCOM_BCM5787F, 554 "Broadcom BCM5787F 10/100 Ethernet", 555 }, 556 { PCI_VENDOR_BROADCOM, 557 PCI_PRODUCT_BROADCOM_BCM5787M, 558 "Broadcom BCM5787M Gigabit Ethernet", 559 }, 560 { PCI_VENDOR_BROADCOM, 561 PCI_PRODUCT_BROADCOM_BCM5788, 562 "Broadcom BCM5788 Gigabit Ethernet", 563 }, 564 { PCI_VENDOR_BROADCOM, 565 PCI_PRODUCT_BROADCOM_BCM5789, 566 "Broadcom BCM5789 Gigabit Ethernet", 567 }, 568 { PCI_VENDOR_BROADCOM, 569 PCI_PRODUCT_BROADCOM_BCM5901, 570 "Broadcom BCM5901 Fast Ethernet", 571 }, 572 { PCI_VENDOR_BROADCOM, 573 PCI_PRODUCT_BROADCOM_BCM5901A2, 574 "Broadcom BCM5901A2 Fast Ethernet", 575 }, 576 { PCI_VENDOR_BROADCOM, 577 PCI_PRODUCT_BROADCOM_BCM5903M, 578 "Broadcom BCM5903M Fast Ethernet", 579 }, 580 { PCI_VENDOR_BROADCOM, 581 PCI_PRODUCT_BROADCOM_BCM5906, 582 "Broadcom BCM5906 Fast Ethernet", 583 }, 584 { PCI_VENDOR_BROADCOM, 585 PCI_PRODUCT_BROADCOM_BCM5906M, 586 "Broadcom BCM5906M Fast Ethernet", 587 }, 588 { PCI_VENDOR_BROADCOM, 589 PCI_PRODUCT_BROADCOM_BCM57760, 590 "Broadcom BCM57760 Fast Ethernet", 591 }, 592 { PCI_VENDOR_BROADCOM, 593 PCI_PRODUCT_BROADCOM_BCM57761, 594 "Broadcom BCM57761 Fast Ethernet", 595 }, 596 { PCI_VENDOR_BROADCOM, 597 PCI_PRODUCT_BROADCOM_BCM57762, 598 "Broadcom BCM57762 Gigabit Ethernet", 599 }, 600 { PCI_VENDOR_BROADCOM, 601 PCI_PRODUCT_BROADCOM_BCM57765, 602 "Broadcom BCM57765 Fast Ethernet", 603 }, 604 { PCI_VENDOR_BROADCOM, 605 PCI_PRODUCT_BROADCOM_BCM57766, 606 "Broadcom BCM57766 Fast Ethernet", 607 }, 608 { PCI_VENDOR_BROADCOM, 609 PCI_PRODUCT_BROADCOM_BCM57780, 610 "Broadcom BCM57780 Fast Ethernet", 611 }, 612 { PCI_VENDOR_BROADCOM, 613 PCI_PRODUCT_BROADCOM_BCM57781, 614 "Broadcom BCM57781 Fast Ethernet", 615 }, 616 { PCI_VENDOR_BROADCOM, 617 PCI_PRODUCT_BROADCOM_BCM57782, 618 "Broadcom BCM57782 Fast Ethernet", 619 }, 620 { PCI_VENDOR_BROADCOM, 621 PCI_PRODUCT_BROADCOM_BCM57785, 622 "Broadcom BCM57785 Fast Ethernet", 623 }, 624 { PCI_VENDOR_BROADCOM, 625 PCI_PRODUCT_BROADCOM_BCM57786, 626 "Broadcom BCM57786 Fast Ethernet", 627 }, 628 { PCI_VENDOR_BROADCOM, 629 PCI_PRODUCT_BROADCOM_BCM57788, 630 "Broadcom BCM57788 Fast Ethernet", 631 }, 632 { PCI_VENDOR_BROADCOM, 633 PCI_PRODUCT_BROADCOM_BCM57790, 634 "Broadcom BCM57790 Fast Ethernet", 635 }, 636 { PCI_VENDOR_BROADCOM, 637 PCI_PRODUCT_BROADCOM_BCM57791, 638 "Broadcom BCM57791 Fast Ethernet", 639 }, 640 { PCI_VENDOR_BROADCOM, 641 PCI_PRODUCT_BROADCOM_BCM57795, 642 "Broadcom BCM57795 Fast Ethernet", 643 }, 644 { PCI_VENDOR_SCHNEIDERKOCH, 645 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 646 "SysKonnect SK-9Dx1 Gigabit Ethernet", 647 }, 648 { PCI_VENDOR_3COM, 649 PCI_PRODUCT_3COM_3C996, 650 "3Com 3c996 Gigabit Ethernet", 651 }, 652 { PCI_VENDOR_FUJITSU4, 653 PCI_PRODUCT_FUJITSU4_PW008GE4, 654 "Fujitsu PW008GE4 Gigabit Ethernet", 655 }, 656 { PCI_VENDOR_FUJITSU4, 657 PCI_PRODUCT_FUJITSU4_PW008GE5, 658 "Fujitsu PW008GE5 Gigabit Ethernet", 659 }, 660 { PCI_VENDOR_FUJITSU4, 661 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 662 "Fujitsu Primepower 250/450 Gigabit Ethernet", 663 }, 664 { 0, 665 0, 666 NULL }, 667 }; 668 669 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 670 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 671 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 672 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 673 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 674 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 675 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 676 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 677 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 678 679 static const struct bge_revision { 680 uint32_t br_chipid; 681 const char *br_name; 682 } bge_revisions[] = { 683 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 684 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 685 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 686 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 687 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 688 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 689 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 690 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 691 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 692 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 693 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 694 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 695 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 696 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 697 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 698 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 699 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 700 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 701 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 702 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 703 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 704 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 705 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 706 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 707 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 708 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 709 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 710 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 711 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 712 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 713 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 714 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 715 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 716 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 717 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 718 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 719 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 720 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 721 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 722 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 723 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 724 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 725 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 726 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 727 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 728 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 729 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 730 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 731 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 732 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 733 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 734 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 735 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 736 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 737 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 738 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 739 /* 5754 and 5787 share the same ASIC ID */ 740 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 741 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 742 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 743 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 744 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 745 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 746 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 747 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 748 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 749 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 750 751 { 0, NULL } 752 }; 753 754 /* 755 * Some defaults for major revisions, so that newer steppings 756 * that we don't know about have a shot at working. 757 */ 758 static const struct bge_revision bge_majorrevs[] = { 759 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 760 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 761 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 762 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 763 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 764 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 765 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 766 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 767 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 768 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 769 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 770 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 771 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 772 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 773 /* 5754 and 5787 share the same ASIC ID */ 774 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 775 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 776 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 777 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 778 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 779 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 780 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 781 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 782 783 { 0, NULL } 784 }; 785 786 static int bge_allow_asf = 1; 787 788 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 789 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 790 791 static uint32_t 792 bge_readmem_ind(struct bge_softc *sc, int off) 793 { 794 pcireg_t val; 795 796 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 797 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 798 return 0; 799 800 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 801 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 802 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 803 return val; 804 } 805 806 static void 807 bge_writemem_ind(struct bge_softc *sc, int off, int val) 808 { 809 810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 811 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 812 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 813 } 814 815 /* 816 * PCI Express only 817 */ 818 static void 819 bge_set_max_readrq(struct bge_softc *sc) 820 { 821 pcireg_t val; 822 823 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 824 + PCIE_DCSR); 825 val &= ~PCIE_DCSR_MAX_READ_REQ; 826 switch (sc->bge_expmrq) { 827 case 2048: 828 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 829 break; 830 case 4096: 831 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 832 break; 833 default: 834 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 835 break; 836 } 837 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 838 + PCIE_DCSR, val); 839 } 840 841 #ifdef notdef 842 static uint32_t 843 bge_readreg_ind(struct bge_softc *sc, int off) 844 { 845 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 846 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 847 } 848 #endif 849 850 static void 851 bge_writereg_ind(struct bge_softc *sc, int off, int val) 852 { 853 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 854 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 855 } 856 857 static void 858 bge_writemem_direct(struct bge_softc *sc, int off, int val) 859 { 860 CSR_WRITE_4(sc, off, val); 861 } 862 863 static void 864 bge_writembx(struct bge_softc *sc, int off, int val) 865 { 866 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 867 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 868 869 CSR_WRITE_4(sc, off, val); 870 } 871 872 static void 873 bge_writembx_flush(struct bge_softc *sc, int off, int val) 874 { 875 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 876 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 877 878 CSR_WRITE_4_FLUSH(sc, off, val); 879 } 880 881 /* 882 * Clear all stale locks and select the lock for this driver instance. 883 */ 884 void 885 bge_ape_lock_init(struct bge_softc *sc) 886 { 887 struct pci_attach_args *pa = &(sc->bge_pa); 888 uint32_t bit, regbase; 889 int i; 890 891 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 892 regbase = BGE_APE_LOCK_GRANT; 893 else 894 regbase = BGE_APE_PER_LOCK_GRANT; 895 896 /* Clear any stale locks. */ 897 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 898 switch (i) { 899 case BGE_APE_LOCK_PHY0: 900 case BGE_APE_LOCK_PHY1: 901 case BGE_APE_LOCK_PHY2: 902 case BGE_APE_LOCK_PHY3: 903 bit = BGE_APE_LOCK_GRANT_DRIVER0; 904 break; 905 default: 906 if (pa->pa_function == 0) 907 bit = BGE_APE_LOCK_GRANT_DRIVER0; 908 else 909 bit = (1 << pa->pa_function); 910 } 911 APE_WRITE_4(sc, regbase + 4 * i, bit); 912 } 913 914 /* Select the PHY lock based on the device's function number. */ 915 switch (pa->pa_function) { 916 case 0: 917 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 918 break; 919 case 1: 920 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 921 break; 922 case 2: 923 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 924 break; 925 case 3: 926 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 927 break; 928 default: 929 printf("%s: PHY lock not supported on function\n", 930 device_xname(sc->bge_dev)); 931 break; 932 } 933 } 934 935 /* 936 * Check for APE firmware, set flags, and print version info. 937 */ 938 void 939 bge_ape_read_fw_ver(struct bge_softc *sc) 940 { 941 const char *fwtype; 942 uint32_t apedata, features; 943 944 /* Check for a valid APE signature in shared memory. */ 945 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 946 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 947 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 948 return; 949 } 950 951 /* Check if APE firmware is running. */ 952 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 953 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 954 printf("%s: APE signature found but FW status not ready! " 955 "0x%08x\n", device_xname(sc->bge_dev), apedata); 956 return; 957 } 958 959 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 960 961 /* Fetch the APE firwmare type and version. */ 962 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 963 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 964 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 965 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 966 fwtype = "NCSI"; 967 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 968 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 969 fwtype = "DASH"; 970 } else 971 fwtype = "UNKN"; 972 973 /* Print the APE firmware version. */ 974 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 975 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 976 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 977 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 978 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 979 } 980 981 int 982 bge_ape_lock(struct bge_softc *sc, int locknum) 983 { 984 struct pci_attach_args *pa = &(sc->bge_pa); 985 uint32_t bit, gnt, req, status; 986 int i, off; 987 988 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 989 return (0); 990 991 /* Lock request/grant registers have different bases. */ 992 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 993 req = BGE_APE_LOCK_REQ; 994 gnt = BGE_APE_LOCK_GRANT; 995 } else { 996 req = BGE_APE_PER_LOCK_REQ; 997 gnt = BGE_APE_PER_LOCK_GRANT; 998 } 999 1000 off = 4 * locknum; 1001 1002 switch (locknum) { 1003 case BGE_APE_LOCK_GPIO: 1004 /* Lock required when using GPIO. */ 1005 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1006 return (0); 1007 if (pa->pa_function == 0) 1008 bit = BGE_APE_LOCK_REQ_DRIVER0; 1009 else 1010 bit = (1 << pa->pa_function); 1011 break; 1012 case BGE_APE_LOCK_GRC: 1013 /* Lock required to reset the device. */ 1014 if (pa->pa_function == 0) 1015 bit = BGE_APE_LOCK_REQ_DRIVER0; 1016 else 1017 bit = (1 << pa->pa_function); 1018 break; 1019 case BGE_APE_LOCK_MEM: 1020 /* Lock required when accessing certain APE memory. */ 1021 if (pa->pa_function == 0) 1022 bit = BGE_APE_LOCK_REQ_DRIVER0; 1023 else 1024 bit = (1 << pa->pa_function); 1025 break; 1026 case BGE_APE_LOCK_PHY0: 1027 case BGE_APE_LOCK_PHY1: 1028 case BGE_APE_LOCK_PHY2: 1029 case BGE_APE_LOCK_PHY3: 1030 /* Lock required when accessing PHYs. */ 1031 bit = BGE_APE_LOCK_REQ_DRIVER0; 1032 break; 1033 default: 1034 return (EINVAL); 1035 } 1036 1037 /* Request a lock. */ 1038 APE_WRITE_4_FLUSH(sc, req + off, bit); 1039 1040 /* Wait up to 1 second to acquire lock. */ 1041 for (i = 0; i < 20000; i++) { 1042 status = APE_READ_4(sc, gnt + off); 1043 if (status == bit) 1044 break; 1045 DELAY(50); 1046 } 1047 1048 /* Handle any errors. */ 1049 if (status != bit) { 1050 printf("%s: APE lock %d request failed! " 1051 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1052 device_xname(sc->bge_dev), 1053 locknum, req + off, bit & 0xFFFF, gnt + off, 1054 status & 0xFFFF); 1055 /* Revoke the lock request. */ 1056 APE_WRITE_4(sc, gnt + off, bit); 1057 return (EBUSY); 1058 } 1059 1060 return (0); 1061 } 1062 1063 void 1064 bge_ape_unlock(struct bge_softc *sc, int locknum) 1065 { 1066 struct pci_attach_args *pa = &(sc->bge_pa); 1067 uint32_t bit, gnt; 1068 int off; 1069 1070 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1071 return; 1072 1073 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1074 gnt = BGE_APE_LOCK_GRANT; 1075 else 1076 gnt = BGE_APE_PER_LOCK_GRANT; 1077 1078 off = 4 * locknum; 1079 1080 switch (locknum) { 1081 case BGE_APE_LOCK_GPIO: 1082 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1083 return; 1084 if (pa->pa_function == 0) 1085 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1086 else 1087 bit = (1 << pa->pa_function); 1088 break; 1089 case BGE_APE_LOCK_GRC: 1090 if (pa->pa_function == 0) 1091 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1092 else 1093 bit = (1 << pa->pa_function); 1094 break; 1095 case BGE_APE_LOCK_MEM: 1096 if (pa->pa_function == 0) 1097 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1098 else 1099 bit = (1 << pa->pa_function); 1100 break; 1101 case BGE_APE_LOCK_PHY0: 1102 case BGE_APE_LOCK_PHY1: 1103 case BGE_APE_LOCK_PHY2: 1104 case BGE_APE_LOCK_PHY3: 1105 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1106 break; 1107 default: 1108 return; 1109 } 1110 1111 /* Write and flush for consecutive bge_ape_lock() */ 1112 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1113 } 1114 1115 /* 1116 * Send an event to the APE firmware. 1117 */ 1118 void 1119 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1120 { 1121 uint32_t apedata; 1122 int i; 1123 1124 /* NCSI does not support APE events. */ 1125 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1126 return; 1127 1128 /* Wait up to 1ms for APE to service previous event. */ 1129 for (i = 10; i > 0; i--) { 1130 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1131 break; 1132 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1133 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1134 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1135 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1136 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1137 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1138 break; 1139 } 1140 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1141 DELAY(100); 1142 } 1143 if (i == 0) { 1144 printf("%s: APE event 0x%08x send timed out\n", 1145 device_xname(sc->bge_dev), event); 1146 } 1147 } 1148 1149 void 1150 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1151 { 1152 uint32_t apedata, event; 1153 1154 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1155 return; 1156 1157 switch (kind) { 1158 case BGE_RESET_START: 1159 /* If this is the first load, clear the load counter. */ 1160 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1161 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1162 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1163 else { 1164 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1165 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1166 } 1167 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1168 BGE_APE_HOST_SEG_SIG_MAGIC); 1169 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1170 BGE_APE_HOST_SEG_LEN_MAGIC); 1171 1172 /* Add some version info if bge(4) supports it. */ 1173 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1174 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1175 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1176 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1177 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1178 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1179 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1180 BGE_APE_HOST_DRVR_STATE_START); 1181 event = BGE_APE_EVENT_STATUS_STATE_START; 1182 break; 1183 case BGE_RESET_SHUTDOWN: 1184 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1185 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1186 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1187 break; 1188 case BGE_RESET_SUSPEND: 1189 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1190 break; 1191 default: 1192 return; 1193 } 1194 1195 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1196 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1197 } 1198 1199 static uint8_t 1200 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1201 { 1202 uint32_t access, byte = 0; 1203 int i; 1204 1205 /* Lock. */ 1206 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1207 for (i = 0; i < 8000; i++) { 1208 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1209 break; 1210 DELAY(20); 1211 } 1212 if (i == 8000) 1213 return 1; 1214 1215 /* Enable access. */ 1216 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1217 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1218 1219 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1220 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1221 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1222 DELAY(10); 1223 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1224 DELAY(10); 1225 break; 1226 } 1227 } 1228 1229 if (i == BGE_TIMEOUT * 10) { 1230 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1231 return 1; 1232 } 1233 1234 /* Get result. */ 1235 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1236 1237 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1238 1239 /* Disable access. */ 1240 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1241 1242 /* Unlock. */ 1243 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1244 1245 return 0; 1246 } 1247 1248 /* 1249 * Read a sequence of bytes from NVRAM. 1250 */ 1251 static int 1252 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1253 { 1254 int error = 0, i; 1255 uint8_t byte = 0; 1256 1257 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1258 return 1; 1259 1260 for (i = 0; i < cnt; i++) { 1261 error = bge_nvram_getbyte(sc, off + i, &byte); 1262 if (error) 1263 break; 1264 *(dest + i) = byte; 1265 } 1266 1267 return (error ? 1 : 0); 1268 } 1269 1270 /* 1271 * Read a byte of data stored in the EEPROM at address 'addr.' The 1272 * BCM570x supports both the traditional bitbang interface and an 1273 * auto access interface for reading the EEPROM. We use the auto 1274 * access method. 1275 */ 1276 static uint8_t 1277 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1278 { 1279 int i; 1280 uint32_t byte = 0; 1281 1282 /* 1283 * Enable use of auto EEPROM access so we can avoid 1284 * having to use the bitbang method. 1285 */ 1286 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1287 1288 /* Reset the EEPROM, load the clock period. */ 1289 CSR_WRITE_4(sc, BGE_EE_ADDR, 1290 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1291 DELAY(20); 1292 1293 /* Issue the read EEPROM command. */ 1294 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1295 1296 /* Wait for completion */ 1297 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1298 DELAY(10); 1299 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1300 break; 1301 } 1302 1303 if (i == BGE_TIMEOUT * 10) { 1304 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1305 return 1; 1306 } 1307 1308 /* Get result. */ 1309 byte = CSR_READ_4(sc, BGE_EE_DATA); 1310 1311 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1312 1313 return 0; 1314 } 1315 1316 /* 1317 * Read a sequence of bytes from the EEPROM. 1318 */ 1319 static int 1320 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1321 { 1322 int error = 0, i; 1323 uint8_t byte = 0; 1324 char *dest = destv; 1325 1326 for (i = 0; i < cnt; i++) { 1327 error = bge_eeprom_getbyte(sc, off + i, &byte); 1328 if (error) 1329 break; 1330 *(dest + i) = byte; 1331 } 1332 1333 return (error ? 1 : 0); 1334 } 1335 1336 static int 1337 bge_miibus_readreg(device_t dev, int phy, int reg) 1338 { 1339 struct bge_softc *sc = device_private(dev); 1340 uint32_t val; 1341 uint32_t autopoll; 1342 int i; 1343 1344 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1345 return 0; 1346 1347 /* Reading with autopolling on may trigger PCI errors */ 1348 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1349 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1350 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1351 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1352 DELAY(80); 1353 } 1354 1355 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1356 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1357 1358 for (i = 0; i < BGE_TIMEOUT; i++) { 1359 delay(10); 1360 val = CSR_READ_4(sc, BGE_MI_COMM); 1361 if (!(val & BGE_MICOMM_BUSY)) { 1362 DELAY(5); 1363 val = CSR_READ_4(sc, BGE_MI_COMM); 1364 break; 1365 } 1366 } 1367 1368 if (i == BGE_TIMEOUT) { 1369 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1370 val = 0; 1371 goto done; 1372 } 1373 1374 done: 1375 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1376 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1377 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1378 DELAY(80); 1379 } 1380 1381 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1382 1383 if (val & BGE_MICOMM_READFAIL) 1384 return 0; 1385 1386 return (val & 0xFFFF); 1387 } 1388 1389 static void 1390 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1391 { 1392 struct bge_softc *sc = device_private(dev); 1393 uint32_t autopoll; 1394 int i; 1395 1396 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1397 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1398 return; 1399 1400 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1401 return; 1402 1403 /* Reading with autopolling on may trigger PCI errors */ 1404 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1405 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1406 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1407 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1408 DELAY(80); 1409 } 1410 1411 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1412 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1413 1414 for (i = 0; i < BGE_TIMEOUT; i++) { 1415 delay(10); 1416 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1417 delay(5); 1418 CSR_READ_4(sc, BGE_MI_COMM); 1419 break; 1420 } 1421 } 1422 1423 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1424 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1425 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1426 delay(80); 1427 } 1428 1429 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1430 1431 if (i == BGE_TIMEOUT) 1432 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1433 } 1434 1435 static void 1436 bge_miibus_statchg(struct ifnet *ifp) 1437 { 1438 struct bge_softc *sc = ifp->if_softc; 1439 struct mii_data *mii = &sc->bge_mii; 1440 uint32_t mac_mode, rx_mode, tx_mode; 1441 1442 /* 1443 * Get flow control negotiation result. 1444 */ 1445 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1446 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1447 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1448 1449 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1450 mii->mii_media_status & IFM_ACTIVE && 1451 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1452 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1453 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1454 (!(mii->mii_media_status & IFM_ACTIVE) || 1455 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1456 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1457 1458 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1459 return; 1460 1461 /* Set the port mode (MII/GMII) to match the link speed. */ 1462 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1463 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1464 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1465 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1466 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1467 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1468 mac_mode |= BGE_PORTMODE_GMII; 1469 else 1470 mac_mode |= BGE_PORTMODE_MII; 1471 1472 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1473 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1474 if ((mii->mii_media_active & IFM_FDX) != 0) { 1475 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1476 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1477 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1478 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1479 } else 1480 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1481 1482 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1483 DELAY(40); 1484 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1485 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1486 } 1487 1488 /* 1489 * Update rx threshold levels to values in a particular slot 1490 * of the interrupt-mitigation table bge_rx_threshes. 1491 */ 1492 static void 1493 bge_set_thresh(struct ifnet *ifp, int lvl) 1494 { 1495 struct bge_softc *sc = ifp->if_softc; 1496 int s; 1497 1498 /* For now, just save the new Rx-intr thresholds and record 1499 * that a threshold update is pending. Updating the hardware 1500 * registers here (even at splhigh()) is observed to 1501 * occasionaly cause glitches where Rx-interrupts are not 1502 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1503 */ 1504 s = splnet(); 1505 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1506 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1507 sc->bge_pending_rxintr_change = 1; 1508 splx(s); 1509 } 1510 1511 1512 /* 1513 * Update Rx thresholds of all bge devices 1514 */ 1515 static void 1516 bge_update_all_threshes(int lvl) 1517 { 1518 struct ifnet *ifp; 1519 const char * const namebuf = "bge"; 1520 int namelen; 1521 1522 if (lvl < 0) 1523 lvl = 0; 1524 else if (lvl >= NBGE_RX_THRESH) 1525 lvl = NBGE_RX_THRESH - 1; 1526 1527 namelen = strlen(namebuf); 1528 /* 1529 * Now search all the interfaces for this name/number 1530 */ 1531 IFNET_FOREACH(ifp) { 1532 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1533 continue; 1534 /* We got a match: update if doing auto-threshold-tuning */ 1535 if (bge_auto_thresh) 1536 bge_set_thresh(ifp, lvl); 1537 } 1538 } 1539 1540 /* 1541 * Handle events that have triggered interrupts. 1542 */ 1543 static void 1544 bge_handle_events(struct bge_softc *sc) 1545 { 1546 1547 return; 1548 } 1549 1550 /* 1551 * Memory management for jumbo frames. 1552 */ 1553 1554 static int 1555 bge_alloc_jumbo_mem(struct bge_softc *sc) 1556 { 1557 char *ptr, *kva; 1558 bus_dma_segment_t seg; 1559 int i, rseg, state, error; 1560 struct bge_jpool_entry *entry; 1561 1562 state = error = 0; 1563 1564 /* Grab a big chunk o' storage. */ 1565 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1566 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1567 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1568 return ENOBUFS; 1569 } 1570 1571 state = 1; 1572 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1573 BUS_DMA_NOWAIT)) { 1574 aprint_error_dev(sc->bge_dev, 1575 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1576 error = ENOBUFS; 1577 goto out; 1578 } 1579 1580 state = 2; 1581 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1582 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1583 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1584 error = ENOBUFS; 1585 goto out; 1586 } 1587 1588 state = 3; 1589 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1590 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1591 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1592 error = ENOBUFS; 1593 goto out; 1594 } 1595 1596 state = 4; 1597 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1598 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1599 1600 SLIST_INIT(&sc->bge_jfree_listhead); 1601 SLIST_INIT(&sc->bge_jinuse_listhead); 1602 1603 /* 1604 * Now divide it up into 9K pieces and save the addresses 1605 * in an array. 1606 */ 1607 ptr = sc->bge_cdata.bge_jumbo_buf; 1608 for (i = 0; i < BGE_JSLOTS; i++) { 1609 sc->bge_cdata.bge_jslots[i] = ptr; 1610 ptr += BGE_JLEN; 1611 entry = malloc(sizeof(struct bge_jpool_entry), 1612 M_DEVBUF, M_NOWAIT); 1613 if (entry == NULL) { 1614 aprint_error_dev(sc->bge_dev, 1615 "no memory for jumbo buffer queue!\n"); 1616 error = ENOBUFS; 1617 goto out; 1618 } 1619 entry->slot = i; 1620 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1621 entry, jpool_entries); 1622 } 1623 out: 1624 if (error != 0) { 1625 switch (state) { 1626 case 4: 1627 bus_dmamap_unload(sc->bge_dmatag, 1628 sc->bge_cdata.bge_rx_jumbo_map); 1629 case 3: 1630 bus_dmamap_destroy(sc->bge_dmatag, 1631 sc->bge_cdata.bge_rx_jumbo_map); 1632 case 2: 1633 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1634 case 1: 1635 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1636 break; 1637 default: 1638 break; 1639 } 1640 } 1641 1642 return error; 1643 } 1644 1645 /* 1646 * Allocate a jumbo buffer. 1647 */ 1648 static void * 1649 bge_jalloc(struct bge_softc *sc) 1650 { 1651 struct bge_jpool_entry *entry; 1652 1653 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1654 1655 if (entry == NULL) { 1656 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1657 return NULL; 1658 } 1659 1660 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1661 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1662 return (sc->bge_cdata.bge_jslots[entry->slot]); 1663 } 1664 1665 /* 1666 * Release a jumbo buffer. 1667 */ 1668 static void 1669 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1670 { 1671 struct bge_jpool_entry *entry; 1672 struct bge_softc *sc; 1673 int i, s; 1674 1675 /* Extract the softc struct pointer. */ 1676 sc = (struct bge_softc *)arg; 1677 1678 if (sc == NULL) 1679 panic("bge_jfree: can't find softc pointer!"); 1680 1681 /* calculate the slot this buffer belongs to */ 1682 1683 i = ((char *)buf 1684 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1685 1686 if ((i < 0) || (i >= BGE_JSLOTS)) 1687 panic("bge_jfree: asked to free buffer that we don't manage!"); 1688 1689 s = splvm(); 1690 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1691 if (entry == NULL) 1692 panic("bge_jfree: buffer not in use!"); 1693 entry->slot = i; 1694 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1695 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1696 1697 if (__predict_true(m != NULL)) 1698 pool_cache_put(mb_cache, m); 1699 splx(s); 1700 } 1701 1702 1703 /* 1704 * Initialize a standard receive ring descriptor. 1705 */ 1706 static int 1707 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1708 bus_dmamap_t dmamap) 1709 { 1710 struct mbuf *m_new = NULL; 1711 struct bge_rx_bd *r; 1712 int error; 1713 1714 if (dmamap == NULL) { 1715 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1716 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1717 if (error != 0) 1718 return error; 1719 } 1720 1721 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1722 1723 if (m == NULL) { 1724 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1725 if (m_new == NULL) 1726 return ENOBUFS; 1727 1728 MCLGET(m_new, M_DONTWAIT); 1729 if (!(m_new->m_flags & M_EXT)) { 1730 m_freem(m_new); 1731 return ENOBUFS; 1732 } 1733 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1734 1735 } else { 1736 m_new = m; 1737 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1738 m_new->m_data = m_new->m_ext.ext_buf; 1739 } 1740 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1741 m_adj(m_new, ETHER_ALIGN); 1742 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1743 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1744 m_freem(m_new); 1745 return ENOBUFS; 1746 } 1747 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1748 BUS_DMASYNC_PREREAD); 1749 1750 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1751 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1752 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1753 r->bge_flags = BGE_RXBDFLAG_END; 1754 r->bge_len = m_new->m_len; 1755 r->bge_idx = i; 1756 1757 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1758 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1759 i * sizeof (struct bge_rx_bd), 1760 sizeof (struct bge_rx_bd), 1761 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1762 1763 return 0; 1764 } 1765 1766 /* 1767 * Initialize a jumbo receive ring descriptor. This allocates 1768 * a jumbo buffer from the pool managed internally by the driver. 1769 */ 1770 static int 1771 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1772 { 1773 struct mbuf *m_new = NULL; 1774 struct bge_rx_bd *r; 1775 void *buf = NULL; 1776 1777 if (m == NULL) { 1778 1779 /* Allocate the mbuf. */ 1780 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1781 if (m_new == NULL) 1782 return ENOBUFS; 1783 1784 /* Allocate the jumbo buffer */ 1785 buf = bge_jalloc(sc); 1786 if (buf == NULL) { 1787 m_freem(m_new); 1788 aprint_error_dev(sc->bge_dev, 1789 "jumbo allocation failed -- packet dropped!\n"); 1790 return ENOBUFS; 1791 } 1792 1793 /* Attach the buffer to the mbuf. */ 1794 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1795 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1796 bge_jfree, sc); 1797 m_new->m_flags |= M_EXT_RW; 1798 } else { 1799 m_new = m; 1800 buf = m_new->m_data = m_new->m_ext.ext_buf; 1801 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1802 } 1803 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1804 m_adj(m_new, ETHER_ALIGN); 1805 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1806 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1807 BUS_DMASYNC_PREREAD); 1808 /* Set up the descriptor. */ 1809 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1810 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1811 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1812 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1813 r->bge_len = m_new->m_len; 1814 r->bge_idx = i; 1815 1816 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1817 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1818 i * sizeof (struct bge_rx_bd), 1819 sizeof (struct bge_rx_bd), 1820 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1821 1822 return 0; 1823 } 1824 1825 /* 1826 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1827 * that's 1MB or memory, which is a lot. For now, we fill only the first 1828 * 256 ring entries and hope that our CPU is fast enough to keep up with 1829 * the NIC. 1830 */ 1831 static int 1832 bge_init_rx_ring_std(struct bge_softc *sc) 1833 { 1834 int i; 1835 1836 if (sc->bge_flags & BGEF_RXRING_VALID) 1837 return 0; 1838 1839 for (i = 0; i < BGE_SSLOTS; i++) { 1840 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1841 return ENOBUFS; 1842 } 1843 1844 sc->bge_std = i - 1; 1845 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1846 1847 sc->bge_flags |= BGEF_RXRING_VALID; 1848 1849 return 0; 1850 } 1851 1852 static void 1853 bge_free_rx_ring_std(struct bge_softc *sc) 1854 { 1855 int i; 1856 1857 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1858 return; 1859 1860 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1861 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1862 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1863 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1864 bus_dmamap_destroy(sc->bge_dmatag, 1865 sc->bge_cdata.bge_rx_std_map[i]); 1866 } 1867 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1868 sizeof(struct bge_rx_bd)); 1869 } 1870 1871 sc->bge_flags &= ~BGEF_RXRING_VALID; 1872 } 1873 1874 static int 1875 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1876 { 1877 int i; 1878 volatile struct bge_rcb *rcb; 1879 1880 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1881 return 0; 1882 1883 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1884 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1885 return ENOBUFS; 1886 } 1887 1888 sc->bge_jumbo = i - 1; 1889 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1890 1891 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1892 rcb->bge_maxlen_flags = 0; 1893 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1894 1895 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1896 1897 return 0; 1898 } 1899 1900 static void 1901 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1902 { 1903 int i; 1904 1905 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1906 return; 1907 1908 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1909 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1910 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1911 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1912 } 1913 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1914 sizeof(struct bge_rx_bd)); 1915 } 1916 1917 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1918 } 1919 1920 static void 1921 bge_free_tx_ring(struct bge_softc *sc) 1922 { 1923 int i; 1924 struct txdmamap_pool_entry *dma; 1925 1926 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1927 return; 1928 1929 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1930 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1931 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1932 sc->bge_cdata.bge_tx_chain[i] = NULL; 1933 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1934 link); 1935 sc->txdma[i] = 0; 1936 } 1937 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1938 sizeof(struct bge_tx_bd)); 1939 } 1940 1941 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1942 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1943 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1944 free(dma, M_DEVBUF); 1945 } 1946 1947 sc->bge_flags &= ~BGEF_TXRING_VALID; 1948 } 1949 1950 static int 1951 bge_init_tx_ring(struct bge_softc *sc) 1952 { 1953 struct ifnet *ifp = &sc->ethercom.ec_if; 1954 int i; 1955 bus_dmamap_t dmamap; 1956 bus_size_t maxsegsz; 1957 struct txdmamap_pool_entry *dma; 1958 1959 if (sc->bge_flags & BGEF_TXRING_VALID) 1960 return 0; 1961 1962 sc->bge_txcnt = 0; 1963 sc->bge_tx_saved_considx = 0; 1964 1965 /* Initialize transmit producer index for host-memory send ring. */ 1966 sc->bge_tx_prodidx = 0; 1967 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1968 /* 5700 b2 errata */ 1969 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1970 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1971 1972 /* NIC-memory send ring not used; initialize to zero. */ 1973 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1974 /* 5700 b2 errata */ 1975 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1976 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1977 1978 /* Limit DMA segment size for some chips */ 1979 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1980 (ifp->if_mtu <= ETHERMTU)) 1981 maxsegsz = 2048; 1982 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1983 maxsegsz = 4096; 1984 else 1985 maxsegsz = ETHER_MAX_LEN_JUMBO; 1986 SLIST_INIT(&sc->txdma_list); 1987 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1988 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1989 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, 1990 &dmamap)) 1991 return ENOBUFS; 1992 if (dmamap == NULL) 1993 panic("dmamap NULL in bge_init_tx_ring"); 1994 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1995 if (dma == NULL) { 1996 aprint_error_dev(sc->bge_dev, 1997 "can't alloc txdmamap_pool_entry\n"); 1998 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1999 return ENOMEM; 2000 } 2001 dma->dmamap = dmamap; 2002 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2003 } 2004 2005 sc->bge_flags |= BGEF_TXRING_VALID; 2006 2007 return 0; 2008 } 2009 2010 static void 2011 bge_setmulti(struct bge_softc *sc) 2012 { 2013 struct ethercom *ac = &sc->ethercom; 2014 struct ifnet *ifp = &ac->ec_if; 2015 struct ether_multi *enm; 2016 struct ether_multistep step; 2017 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2018 uint32_t h; 2019 int i; 2020 2021 if (ifp->if_flags & IFF_PROMISC) 2022 goto allmulti; 2023 2024 /* Now program new ones. */ 2025 ETHER_FIRST_MULTI(step, ac, enm); 2026 while (enm != NULL) { 2027 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2028 /* 2029 * We must listen to a range of multicast addresses. 2030 * For now, just accept all multicasts, rather than 2031 * trying to set only those filter bits needed to match 2032 * the range. (At this time, the only use of address 2033 * ranges is for IP multicast routing, for which the 2034 * range is big enough to require all bits set.) 2035 */ 2036 goto allmulti; 2037 } 2038 2039 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2040 2041 /* Just want the 7 least-significant bits. */ 2042 h &= 0x7f; 2043 2044 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2045 ETHER_NEXT_MULTI(step, enm); 2046 } 2047 2048 ifp->if_flags &= ~IFF_ALLMULTI; 2049 goto setit; 2050 2051 allmulti: 2052 ifp->if_flags |= IFF_ALLMULTI; 2053 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2054 2055 setit: 2056 for (i = 0; i < 4; i++) 2057 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2058 } 2059 2060 static void 2061 bge_sig_pre_reset(struct bge_softc *sc, int type) 2062 { 2063 2064 /* 2065 * Some chips don't like this so only do this if ASF is enabled 2066 */ 2067 if (sc->bge_asf_mode) 2068 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2069 2070 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2071 switch (type) { 2072 case BGE_RESET_START: 2073 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2074 BGE_FW_DRV_STATE_START); 2075 break; 2076 case BGE_RESET_SHUTDOWN: 2077 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2078 BGE_FW_DRV_STATE_UNLOAD); 2079 break; 2080 case BGE_RESET_SUSPEND: 2081 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2082 BGE_FW_DRV_STATE_SUSPEND); 2083 break; 2084 } 2085 } 2086 2087 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2088 bge_ape_driver_state_change(sc, type); 2089 } 2090 2091 static void 2092 bge_sig_post_reset(struct bge_softc *sc, int type) 2093 { 2094 2095 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2096 switch (type) { 2097 case BGE_RESET_START: 2098 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2099 BGE_FW_DRV_STATE_START_DONE); 2100 /* START DONE */ 2101 break; 2102 case BGE_RESET_SHUTDOWN: 2103 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2104 BGE_FW_DRV_STATE_UNLOAD_DONE); 2105 break; 2106 } 2107 } 2108 2109 if (type == BGE_RESET_SHUTDOWN) 2110 bge_ape_driver_state_change(sc, type); 2111 } 2112 2113 static void 2114 bge_sig_legacy(struct bge_softc *sc, int type) 2115 { 2116 2117 if (sc->bge_asf_mode) { 2118 switch (type) { 2119 case BGE_RESET_START: 2120 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2121 BGE_FW_DRV_STATE_START); 2122 break; 2123 case BGE_RESET_SHUTDOWN: 2124 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2125 BGE_FW_DRV_STATE_UNLOAD); 2126 break; 2127 } 2128 } 2129 } 2130 2131 static void 2132 bge_wait_for_event_ack(struct bge_softc *sc) 2133 { 2134 int i; 2135 2136 /* wait up to 2500usec */ 2137 for (i = 0; i < 250; i++) { 2138 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2139 BGE_RX_CPU_DRV_EVENT)) 2140 break; 2141 DELAY(10); 2142 } 2143 } 2144 2145 static void 2146 bge_stop_fw(struct bge_softc *sc) 2147 { 2148 2149 if (sc->bge_asf_mode) { 2150 bge_wait_for_event_ack(sc); 2151 2152 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2153 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2154 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2155 2156 bge_wait_for_event_ack(sc); 2157 } 2158 } 2159 2160 static int 2161 bge_poll_fw(struct bge_softc *sc) 2162 { 2163 uint32_t val; 2164 int i; 2165 2166 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2167 for (i = 0; i < BGE_TIMEOUT; i++) { 2168 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2169 if (val & BGE_VCPU_STATUS_INIT_DONE) 2170 break; 2171 DELAY(100); 2172 } 2173 if (i >= BGE_TIMEOUT) { 2174 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2175 return -1; 2176 } 2177 } else { 2178 /* 2179 * Poll the value location we just wrote until 2180 * we see the 1's complement of the magic number. 2181 * This indicates that the firmware initialization 2182 * is complete. 2183 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2184 */ 2185 for (i = 0; i < BGE_TIMEOUT; i++) { 2186 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2187 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2188 break; 2189 DELAY(10); 2190 } 2191 2192 if ((i >= BGE_TIMEOUT) 2193 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2194 aprint_error_dev(sc->bge_dev, 2195 "firmware handshake timed out, val = %x\n", val); 2196 return -1; 2197 } 2198 } 2199 2200 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2201 /* tg3 says we have to wait extra time */ 2202 delay(10 * 1000); 2203 } 2204 2205 return 0; 2206 } 2207 2208 int 2209 bge_phy_addr(struct bge_softc *sc) 2210 { 2211 struct pci_attach_args *pa = &(sc->bge_pa); 2212 int phy_addr = 1; 2213 2214 /* 2215 * PHY address mapping for various devices. 2216 * 2217 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2218 * ---------+-------+-------+-------+-------+ 2219 * BCM57XX | 1 | X | X | X | 2220 * BCM5704 | 1 | X | 1 | X | 2221 * BCM5717 | 1 | 8 | 2 | 9 | 2222 * BCM5719 | 1 | 8 | 2 | 9 | 2223 * BCM5720 | 1 | 8 | 2 | 9 | 2224 * 2225 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2226 * ---------+-------+-------+-------+-------+ 2227 * BCM57XX | X | X | X | X | 2228 * BCM5704 | X | X | X | X | 2229 * BCM5717 | X | X | X | X | 2230 * BCM5719 | 3 | 10 | 4 | 11 | 2231 * BCM5720 | X | X | X | X | 2232 * 2233 * Other addresses may respond but they are not 2234 * IEEE compliant PHYs and should be ignored. 2235 */ 2236 switch (BGE_ASICREV(sc->bge_chipid)) { 2237 case BGE_ASICREV_BCM5717: 2238 case BGE_ASICREV_BCM5719: 2239 case BGE_ASICREV_BCM5720: 2240 phy_addr = pa->pa_function; 2241 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2242 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2243 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2244 } else { 2245 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2246 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2247 } 2248 } 2249 2250 return phy_addr; 2251 } 2252 2253 /* 2254 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2255 * self-test results. 2256 */ 2257 static int 2258 bge_chipinit(struct bge_softc *sc) 2259 { 2260 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2261 int i; 2262 2263 /* Set endianness before we access any non-PCI registers. */ 2264 misc_ctl = BGE_INIT; 2265 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2266 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2267 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2268 misc_ctl); 2269 2270 /* 2271 * Clear the MAC statistics block in the NIC's 2272 * internal memory. 2273 */ 2274 for (i = BGE_STATS_BLOCK; 2275 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2276 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2277 2278 for (i = BGE_STATUS_BLOCK; 2279 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2280 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2281 2282 /* 5717 workaround from tg3 */ 2283 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2284 /* Save */ 2285 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2286 2287 /* Temporary modify MODE_CTL to control TLP */ 2288 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2289 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2290 2291 /* Control TLP */ 2292 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2293 BGE_TLP_PHYCTL1); 2294 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2295 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2296 2297 /* Restore */ 2298 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2299 } 2300 2301 if (BGE_IS_57765_FAMILY(sc)) { 2302 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2303 /* Save */ 2304 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2305 2306 /* Temporary modify MODE_CTL to control TLP */ 2307 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2308 CSR_WRITE_4(sc, BGE_MODE_CTL, 2309 reg | BGE_MODECTL_PCIE_TLPADDR1); 2310 2311 /* Control TLP */ 2312 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2313 BGE_TLP_PHYCTL5); 2314 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2315 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2316 2317 /* Restore */ 2318 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2319 } 2320 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2321 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2322 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2323 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2324 2325 /* Save */ 2326 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2327 2328 /* Temporary modify MODE_CTL to control TLP */ 2329 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2330 CSR_WRITE_4(sc, BGE_MODE_CTL, 2331 reg | BGE_MODECTL_PCIE_TLPADDR0); 2332 2333 /* Control TLP */ 2334 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2335 BGE_TLP_FTSMAX); 2336 reg &= ~BGE_TLP_FTSMAX_MSK; 2337 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2338 reg | BGE_TLP_FTSMAX_VAL); 2339 2340 /* Restore */ 2341 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2342 } 2343 2344 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2345 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2346 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2347 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2348 } 2349 2350 /* Set up the PCI DMA control register. */ 2351 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2352 if (sc->bge_flags & BGEF_PCIE) { 2353 /* Read watermark not used, 128 bytes for write. */ 2354 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2355 device_xname(sc->bge_dev))); 2356 if (sc->bge_mps >= 256) 2357 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2358 else 2359 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2360 } else if (sc->bge_flags & BGEF_PCIX) { 2361 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2362 device_xname(sc->bge_dev))); 2363 /* PCI-X bus */ 2364 if (BGE_IS_5714_FAMILY(sc)) { 2365 /* 256 bytes for read and write. */ 2366 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2367 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2368 2369 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2370 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2371 else 2372 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2373 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2374 /* 2375 * In the BCM5703, the DMA read watermark should 2376 * be set to less than or equal to the maximum 2377 * memory read byte count of the PCI-X command 2378 * register. 2379 */ 2380 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2381 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2382 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2383 /* 1536 bytes for read, 384 bytes for write. */ 2384 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2385 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2386 } else { 2387 /* 384 bytes for read and write. */ 2388 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2389 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2390 (0x0F); 2391 } 2392 2393 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2394 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2395 uint32_t tmp; 2396 2397 /* Set ONEDMA_ATONCE for hardware workaround. */ 2398 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2399 if (tmp == 6 || tmp == 7) 2400 dma_rw_ctl |= 2401 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2402 2403 /* Set PCI-X DMA write workaround. */ 2404 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2405 } 2406 } else { 2407 /* Conventional PCI bus: 256 bytes for read and write. */ 2408 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2409 device_xname(sc->bge_dev))); 2410 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2411 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2412 2413 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2414 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2415 dma_rw_ctl |= 0x0F; 2416 } 2417 2418 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2419 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2420 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2421 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2422 2423 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2424 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2425 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2426 2427 if (BGE_IS_57765_PLUS(sc)) { 2428 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2429 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2430 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2431 2432 /* 2433 * Enable HW workaround for controllers that misinterpret 2434 * a status tag update and leave interrupts permanently 2435 * disabled. 2436 */ 2437 if (!BGE_IS_57765_FAMILY(sc) && 2438 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2439 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2440 } 2441 2442 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2443 dma_rw_ctl); 2444 2445 /* 2446 * Set up general mode register. 2447 */ 2448 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2449 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2450 /* Retain Host-2-BMC settings written by APE firmware. */ 2451 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2452 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2453 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2454 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2455 } 2456 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2457 BGE_MODECTL_TX_NO_PHDR_CSUM; 2458 2459 /* 2460 * BCM5701 B5 have a bug causing data corruption when using 2461 * 64-bit DMA reads, which can be terminated early and then 2462 * completed later as 32-bit accesses, in combination with 2463 * certain bridges. 2464 */ 2465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2466 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2467 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2468 2469 /* 2470 * Tell the firmware the driver is running 2471 */ 2472 if (sc->bge_asf_mode & ASF_STACKUP) 2473 mode_ctl |= BGE_MODECTL_STACKUP; 2474 2475 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2476 2477 /* 2478 * Disable memory write invalidate. Apparently it is not supported 2479 * properly by these devices. 2480 */ 2481 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2482 PCI_COMMAND_INVALIDATE_ENABLE); 2483 2484 #ifdef __brokenalpha__ 2485 /* 2486 * Must insure that we do not cross an 8K (bytes) boundary 2487 * for DMA reads. Our highest limit is 1K bytes. This is a 2488 * restriction on some ALPHA platforms with early revision 2489 * 21174 PCI chipsets, such as the AlphaPC 164lx 2490 */ 2491 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2492 #endif 2493 2494 /* Set the timer prescaler (always 66MHz) */ 2495 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2496 2497 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2498 DELAY(40); /* XXX */ 2499 2500 /* Put PHY into ready state */ 2501 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2502 DELAY(40); 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int 2509 bge_blockinit(struct bge_softc *sc) 2510 { 2511 volatile struct bge_rcb *rcb; 2512 bus_size_t rcb_addr; 2513 struct ifnet *ifp = &sc->ethercom.ec_if; 2514 bge_hostaddr taddr; 2515 uint32_t dmactl, mimode, val; 2516 int i, limit; 2517 2518 /* 2519 * Initialize the memory window pointer register so that 2520 * we can access the first 32K of internal NIC RAM. This will 2521 * allow us to set up the TX send ring RCBs and the RX return 2522 * ring RCBs, plus other things which live in NIC memory. 2523 */ 2524 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2525 2526 if (!BGE_IS_5705_PLUS(sc)) { 2527 /* 57XX step 33 */ 2528 /* Configure mbuf memory pool */ 2529 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2530 BGE_BUFFPOOL_1); 2531 2532 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2534 else 2535 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2536 2537 /* 57XX step 34 */ 2538 /* Configure DMA resource pool */ 2539 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2540 BGE_DMA_DESCRIPTORS); 2541 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2542 } 2543 2544 /* 5718 step 11, 57XX step 35 */ 2545 /* 2546 * Configure mbuf pool watermarks. New broadcom docs strongly 2547 * recommend these. 2548 */ 2549 if (BGE_IS_5717_PLUS(sc)) { 2550 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2551 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2552 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2553 } else if (BGE_IS_5705_PLUS(sc)) { 2554 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2555 2556 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2557 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2558 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2559 } else { 2560 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2561 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2562 } 2563 } else { 2564 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2565 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2566 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2567 } 2568 2569 /* 57XX step 36 */ 2570 /* Configure DMA resource watermarks */ 2571 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2572 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2573 2574 /* 5718 step 13, 57XX step 38 */ 2575 /* Enable buffer manager */ 2576 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2577 /* 2578 * Change the arbitration algorithm of TXMBUF read request to 2579 * round-robin instead of priority based for BCM5719. When 2580 * TXFIFO is almost empty, RDMA will hold its request until 2581 * TXFIFO is not almost empty. 2582 */ 2583 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2584 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2585 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2586 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2587 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2588 val |= BGE_BMANMODE_LOMBUF_ATTN; 2589 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2590 2591 /* 57XX step 39 */ 2592 /* Poll for buffer manager start indication */ 2593 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2594 DELAY(10); 2595 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2596 break; 2597 } 2598 2599 if (i == BGE_TIMEOUT * 2) { 2600 aprint_error_dev(sc->bge_dev, 2601 "buffer manager failed to start\n"); 2602 return ENXIO; 2603 } 2604 2605 /* 57XX step 40 */ 2606 /* Enable flow-through queues */ 2607 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2608 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2609 2610 /* Wait until queue initialization is complete */ 2611 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2612 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2613 break; 2614 DELAY(10); 2615 } 2616 2617 if (i == BGE_TIMEOUT * 2) { 2618 aprint_error_dev(sc->bge_dev, 2619 "flow-through queue init failed\n"); 2620 return ENXIO; 2621 } 2622 2623 /* 2624 * Summary of rings supported by the controller: 2625 * 2626 * Standard Receive Producer Ring 2627 * - This ring is used to feed receive buffers for "standard" 2628 * sized frames (typically 1536 bytes) to the controller. 2629 * 2630 * Jumbo Receive Producer Ring 2631 * - This ring is used to feed receive buffers for jumbo sized 2632 * frames (i.e. anything bigger than the "standard" frames) 2633 * to the controller. 2634 * 2635 * Mini Receive Producer Ring 2636 * - This ring is used to feed receive buffers for "mini" 2637 * sized frames to the controller. 2638 * - This feature required external memory for the controller 2639 * but was never used in a production system. Should always 2640 * be disabled. 2641 * 2642 * Receive Return Ring 2643 * - After the controller has placed an incoming frame into a 2644 * receive buffer that buffer is moved into a receive return 2645 * ring. The driver is then responsible to passing the 2646 * buffer up to the stack. Many versions of the controller 2647 * support multiple RR rings. 2648 * 2649 * Send Ring 2650 * - This ring is used for outgoing frames. Many versions of 2651 * the controller support multiple send rings. 2652 */ 2653 2654 /* 5718 step 15, 57XX step 41 */ 2655 /* Initialize the standard RX ring control block */ 2656 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2657 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2658 /* 5718 step 16 */ 2659 if (BGE_IS_57765_PLUS(sc)) { 2660 /* 2661 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2662 * Bits 15-2 : Maximum RX frame size 2663 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2664 * Bit 0 : Reserved 2665 */ 2666 rcb->bge_maxlen_flags = 2667 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2668 } else if (BGE_IS_5705_PLUS(sc)) { 2669 /* 2670 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2671 * Bits 15-2 : Reserved (should be 0) 2672 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2673 * Bit 0 : Reserved 2674 */ 2675 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2676 } else { 2677 /* 2678 * Ring size is always XXX entries 2679 * Bits 31-16: Maximum RX frame size 2680 * Bits 15-2 : Reserved (should be 0) 2681 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2682 * Bit 0 : Reserved 2683 */ 2684 rcb->bge_maxlen_flags = 2685 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2686 } 2687 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2688 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2689 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2690 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2691 else 2692 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2693 /* Write the standard receive producer ring control block. */ 2694 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2695 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2696 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2697 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2698 2699 /* Reset the standard receive producer ring producer index. */ 2700 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2701 2702 /* 57XX step 42 */ 2703 /* 2704 * Initialize the jumbo RX ring control block 2705 * We set the 'ring disabled' bit in the flags 2706 * field until we're actually ready to start 2707 * using this ring (i.e. once we set the MTU 2708 * high enough to require it). 2709 */ 2710 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2711 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2712 BGE_HOSTADDR(rcb->bge_hostaddr, 2713 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2714 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2715 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2716 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2717 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2718 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2719 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2720 else 2721 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2722 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2723 rcb->bge_hostaddr.bge_addr_hi); 2724 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2725 rcb->bge_hostaddr.bge_addr_lo); 2726 /* Program the jumbo receive producer ring RCB parameters. */ 2727 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2728 rcb->bge_maxlen_flags); 2729 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2730 /* Reset the jumbo receive producer ring producer index. */ 2731 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2732 } 2733 2734 /* 57XX step 43 */ 2735 /* Disable the mini receive producer ring RCB. */ 2736 if (BGE_IS_5700_FAMILY(sc)) { 2737 /* Set up dummy disabled mini ring RCB */ 2738 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2739 rcb->bge_maxlen_flags = 2740 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2741 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2742 rcb->bge_maxlen_flags); 2743 /* Reset the mini receive producer ring producer index. */ 2744 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2745 2746 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2747 offsetof(struct bge_ring_data, bge_info), 2748 sizeof (struct bge_gib), 2749 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2750 } 2751 2752 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2753 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2754 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2755 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2756 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2757 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2758 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2759 } 2760 /* 5718 step 14, 57XX step 44 */ 2761 /* 2762 * The BD ring replenish thresholds control how often the 2763 * hardware fetches new BD's from the producer rings in host 2764 * memory. Setting the value too low on a busy system can 2765 * starve the hardware and recue the throughpout. 2766 * 2767 * Set the BD ring replenish thresholds. The recommended 2768 * values are 1/8th the number of descriptors allocated to 2769 * each ring, but since we try to avoid filling the entire 2770 * ring we set these to the minimal value of 8. This needs to 2771 * be done on several of the supported chip revisions anyway, 2772 * to work around HW bugs. 2773 */ 2774 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2775 if (BGE_IS_JUMBO_CAPABLE(sc)) 2776 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2777 2778 /* 5718 step 18 */ 2779 if (BGE_IS_5717_PLUS(sc)) { 2780 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2781 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2782 } 2783 2784 /* 57XX step 45 */ 2785 /* 2786 * Disable all send rings by setting the 'ring disabled' bit 2787 * in the flags field of all the TX send ring control blocks, 2788 * located in NIC memory. 2789 */ 2790 if (BGE_IS_5700_FAMILY(sc)) { 2791 /* 5700 to 5704 had 16 send rings. */ 2792 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2793 } else if (BGE_IS_5717_PLUS(sc)) { 2794 limit = BGE_TX_RINGS_5717_MAX; 2795 } else if (BGE_IS_57765_FAMILY(sc)) { 2796 limit = BGE_TX_RINGS_57765_MAX; 2797 } else 2798 limit = 1; 2799 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2800 for (i = 0; i < limit; i++) { 2801 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2802 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2803 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2804 rcb_addr += sizeof(struct bge_rcb); 2805 } 2806 2807 /* 57XX step 46 and 47 */ 2808 /* Configure send ring RCB 0 (we use only the first ring) */ 2809 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2810 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2811 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2812 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2813 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2814 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2815 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2816 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2817 else 2818 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2819 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2820 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2821 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2822 2823 /* 57XX step 48 */ 2824 /* 2825 * Disable all receive return rings by setting the 2826 * 'ring diabled' bit in the flags field of all the receive 2827 * return ring control blocks, located in NIC memory. 2828 */ 2829 if (BGE_IS_5717_PLUS(sc)) { 2830 /* Should be 17, use 16 until we get an SRAM map. */ 2831 limit = 16; 2832 } else if (BGE_IS_5700_FAMILY(sc)) 2833 limit = BGE_RX_RINGS_MAX; 2834 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2835 BGE_IS_57765_FAMILY(sc)) 2836 limit = 4; 2837 else 2838 limit = 1; 2839 /* Disable all receive return rings */ 2840 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2841 for (i = 0; i < limit; i++) { 2842 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2843 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2844 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2845 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2846 BGE_RCB_FLAG_RING_DISABLED)); 2847 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2848 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2849 (i * (sizeof(uint64_t))), 0); 2850 rcb_addr += sizeof(struct bge_rcb); 2851 } 2852 2853 /* 57XX step 49 */ 2854 /* 2855 * Set up receive return ring 0. Note that the NIC address 2856 * for RX return rings is 0x0. The return rings live entirely 2857 * within the host, so the nicaddr field in the RCB isn't used. 2858 */ 2859 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2860 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2861 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2862 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2863 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2864 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2865 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2866 2867 /* 5718 step 24, 57XX step 53 */ 2868 /* Set random backoff seed for TX */ 2869 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2870 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2871 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2872 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2873 BGE_TX_BACKOFF_SEED_MASK); 2874 2875 /* 5718 step 26, 57XX step 55 */ 2876 /* Set inter-packet gap */ 2877 val = 0x2620; 2878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2879 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2880 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2881 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2882 2883 /* 5718 step 27, 57XX step 56 */ 2884 /* 2885 * Specify which ring to use for packets that don't match 2886 * any RX rules. 2887 */ 2888 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2889 2890 /* 5718 step 28, 57XX step 57 */ 2891 /* 2892 * Configure number of RX lists. One interrupt distribution 2893 * list, sixteen active lists, one bad frames class. 2894 */ 2895 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2896 2897 /* 5718 step 29, 57XX step 58 */ 2898 /* Inialize RX list placement stats mask. */ 2899 if (BGE_IS_575X_PLUS(sc)) { 2900 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2901 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2902 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2903 } else 2904 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2905 2906 /* 5718 step 30, 57XX step 59 */ 2907 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2908 2909 /* 5718 step 33, 57XX step 62 */ 2910 /* Disable host coalescing until we get it set up */ 2911 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2912 2913 /* 5718 step 34, 57XX step 63 */ 2914 /* Poll to make sure it's shut down. */ 2915 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2916 DELAY(10); 2917 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2918 break; 2919 } 2920 2921 if (i == BGE_TIMEOUT * 2) { 2922 aprint_error_dev(sc->bge_dev, 2923 "host coalescing engine failed to idle\n"); 2924 return ENXIO; 2925 } 2926 2927 /* 5718 step 35, 36, 37 */ 2928 /* Set up host coalescing defaults */ 2929 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2930 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2931 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2932 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2933 if (!(BGE_IS_5705_PLUS(sc))) { 2934 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2935 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2936 } 2937 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2938 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2939 2940 /* Set up address of statistics block */ 2941 if (BGE_IS_5700_FAMILY(sc)) { 2942 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2943 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2944 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2945 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2946 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2947 } 2948 2949 /* 5718 step 38 */ 2950 /* Set up address of status block */ 2951 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2952 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2953 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2954 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2955 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2956 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2957 2958 /* Set up status block size. */ 2959 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2960 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2961 val = BGE_STATBLKSZ_FULL; 2962 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2963 } else { 2964 val = BGE_STATBLKSZ_32BYTE; 2965 bzero(&sc->bge_rdata->bge_status_block, 32); 2966 } 2967 2968 /* 5718 step 39, 57XX step 73 */ 2969 /* Turn on host coalescing state machine */ 2970 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2971 2972 /* 5718 step 40, 57XX step 74 */ 2973 /* Turn on RX BD completion state machine and enable attentions */ 2974 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2975 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2976 2977 /* 5718 step 41, 57XX step 75 */ 2978 /* Turn on RX list placement state machine */ 2979 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2980 2981 /* 57XX step 76 */ 2982 /* Turn on RX list selector state machine. */ 2983 if (!(BGE_IS_5705_PLUS(sc))) 2984 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2985 2986 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2987 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2988 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2989 BGE_MACMODE_FRMHDR_DMA_ENB; 2990 2991 if (sc->bge_flags & BGEF_FIBER_TBI) 2992 val |= BGE_PORTMODE_TBI; 2993 else if (sc->bge_flags & BGEF_FIBER_MII) 2994 val |= BGE_PORTMODE_GMII; 2995 else 2996 val |= BGE_PORTMODE_MII; 2997 2998 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2999 /* Allow APE to send/receive frames. */ 3000 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3001 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3002 3003 /* Turn on DMA, clear stats */ 3004 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3005 /* 5718 step 44 */ 3006 DELAY(40); 3007 3008 /* 5718 step 45, 57XX step 79 */ 3009 /* Set misc. local control, enable interrupts on attentions */ 3010 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3011 if (BGE_IS_5717_PLUS(sc)) { 3012 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3013 /* 5718 step 46 */ 3014 DELAY(100); 3015 } 3016 3017 /* 57XX step 81 */ 3018 /* Turn on DMA completion state machine */ 3019 if (!(BGE_IS_5705_PLUS(sc))) 3020 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3021 3022 /* 5718 step 47, 57XX step 82 */ 3023 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3024 3025 /* 5718 step 48 */ 3026 /* Enable host coalescing bug fix. */ 3027 if (BGE_IS_5755_PLUS(sc)) 3028 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3029 3030 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3031 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3032 3033 /* Turn on write DMA state machine */ 3034 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3035 /* 5718 step 49 */ 3036 DELAY(40); 3037 3038 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3039 3040 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3041 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3042 3043 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3044 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3045 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3046 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3047 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3048 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3049 3050 if (sc->bge_flags & BGEF_PCIE) 3051 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3052 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3053 if (ifp->if_mtu <= ETHERMTU) 3054 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3055 } 3056 if (sc->bge_flags & BGEF_TSO) 3057 val |= BGE_RDMAMODE_TSO4_ENABLE; 3058 3059 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3060 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3061 BGE_RDMAMODE_H2BNC_VLAN_DET; 3062 /* 3063 * Allow multiple outstanding read requests from 3064 * non-LSO read DMA engine. 3065 */ 3066 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3067 } 3068 3069 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3070 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3071 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3072 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3073 BGE_IS_57765_PLUS(sc)) { 3074 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3075 /* 3076 * Adjust tx margin to prevent TX data corruption and 3077 * fix internal FIFO overflow. 3078 */ 3079 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3080 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3081 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3082 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3083 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3084 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3085 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3086 } 3087 /* 3088 * Enable fix for read DMA FIFO overruns. 3089 * The fix is to limit the number of RX BDs 3090 * the hardware would fetch at a fime. 3091 */ 3092 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3093 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3094 } 3095 3096 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3097 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3098 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3099 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3100 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3101 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3102 /* 3103 * Allow 4KB burst length reads for non-LSO frames. 3104 * Enable 512B burst length reads for buffer descriptors. 3105 */ 3106 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3107 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3108 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3109 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3110 } 3111 3112 /* Turn on read DMA state machine */ 3113 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3114 /* 5718 step 52 */ 3115 delay(40); 3116 3117 /* 5718 step 56, 57XX step 84 */ 3118 /* Turn on RX data completion state machine */ 3119 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3120 3121 /* Turn on RX data and RX BD initiator state machine */ 3122 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3123 3124 /* 57XX step 85 */ 3125 /* Turn on Mbuf cluster free state machine */ 3126 if (!BGE_IS_5705_PLUS(sc)) 3127 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3128 3129 /* 5718 step 57, 57XX step 86 */ 3130 /* Turn on send data completion state machine */ 3131 val = BGE_SDCMODE_ENABLE; 3132 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3133 val |= BGE_SDCMODE_CDELAY; 3134 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3135 3136 /* 5718 step 58 */ 3137 /* Turn on send BD completion state machine */ 3138 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3139 3140 /* 57XX step 88 */ 3141 /* Turn on RX BD initiator state machine */ 3142 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3143 3144 /* 5718 step 60, 57XX step 90 */ 3145 /* Turn on send data initiator state machine */ 3146 if (sc->bge_flags & BGEF_TSO) { 3147 /* XXX: magic value from Linux driver */ 3148 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3149 BGE_SDIMODE_HW_LSO_PRE_DMA); 3150 } else 3151 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3152 3153 /* 5718 step 61, 57XX step 91 */ 3154 /* Turn on send BD initiator state machine */ 3155 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3156 3157 /* 5718 step 62, 57XX step 92 */ 3158 /* Turn on send BD selector state machine */ 3159 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3160 3161 /* 5718 step 31, 57XX step 60 */ 3162 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3163 /* 5718 step 32, 57XX step 61 */ 3164 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3165 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3166 3167 /* ack/clear link change events */ 3168 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3169 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3170 BGE_MACSTAT_LINK_CHANGED); 3171 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3172 3173 /* 3174 * Enable attention when the link has changed state for 3175 * devices that use auto polling. 3176 */ 3177 if (sc->bge_flags & BGEF_FIBER_TBI) { 3178 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3179 } else { 3180 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3181 mimode = BGE_MIMODE_500KHZ_CONST; 3182 else 3183 mimode = BGE_MIMODE_BASE; 3184 /* 5718 step 68. 5718 step 69 (optionally). */ 3185 if (BGE_IS_5700_FAMILY(sc) || 3186 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3187 mimode |= BGE_MIMODE_AUTOPOLL; 3188 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3189 } 3190 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3191 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3192 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3193 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3194 BGE_EVTENB_MI_INTERRUPT); 3195 } 3196 3197 /* 3198 * Clear any pending link state attention. 3199 * Otherwise some link state change events may be lost until attention 3200 * is cleared by bge_intr() -> bge_link_upd() sequence. 3201 * It's not necessary on newer BCM chips - perhaps enabling link 3202 * state change attentions implies clearing pending attention. 3203 */ 3204 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3205 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3206 BGE_MACSTAT_LINK_CHANGED); 3207 3208 /* Enable link state change attentions. */ 3209 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3210 3211 return 0; 3212 } 3213 3214 static const struct bge_revision * 3215 bge_lookup_rev(uint32_t chipid) 3216 { 3217 const struct bge_revision *br; 3218 3219 for (br = bge_revisions; br->br_name != NULL; br++) { 3220 if (br->br_chipid == chipid) 3221 return br; 3222 } 3223 3224 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3225 if (br->br_chipid == BGE_ASICREV(chipid)) 3226 return br; 3227 } 3228 3229 return NULL; 3230 } 3231 3232 static const struct bge_product * 3233 bge_lookup(const struct pci_attach_args *pa) 3234 { 3235 const struct bge_product *bp; 3236 3237 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3238 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3239 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3240 return bp; 3241 } 3242 3243 return NULL; 3244 } 3245 3246 static uint32_t 3247 bge_chipid(const struct pci_attach_args *pa) 3248 { 3249 uint32_t id; 3250 3251 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3252 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3253 3254 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3255 switch (PCI_PRODUCT(pa->pa_id)) { 3256 case PCI_PRODUCT_BROADCOM_BCM5717: 3257 case PCI_PRODUCT_BROADCOM_BCM5718: 3258 case PCI_PRODUCT_BROADCOM_BCM5719: 3259 case PCI_PRODUCT_BROADCOM_BCM5720: 3260 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3261 BGE_PCI_GEN2_PRODID_ASICREV); 3262 break; 3263 case PCI_PRODUCT_BROADCOM_BCM57761: 3264 case PCI_PRODUCT_BROADCOM_BCM57762: 3265 case PCI_PRODUCT_BROADCOM_BCM57765: 3266 case PCI_PRODUCT_BROADCOM_BCM57766: 3267 case PCI_PRODUCT_BROADCOM_BCM57781: 3268 case PCI_PRODUCT_BROADCOM_BCM57785: 3269 case PCI_PRODUCT_BROADCOM_BCM57791: 3270 case PCI_PRODUCT_BROADCOM_BCM57795: 3271 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3272 BGE_PCI_GEN15_PRODID_ASICREV); 3273 break; 3274 default: 3275 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3276 BGE_PCI_PRODID_ASICREV); 3277 break; 3278 } 3279 } 3280 3281 return id; 3282 } 3283 3284 #ifdef __HAVE_PCI_MSI_MSIX 3285 /* 3286 * Return true if MSI can be used with this device. 3287 */ 3288 static int 3289 bge_can_use_msi(struct bge_softc *sc) 3290 { 3291 int can_use_msi = 0; 3292 3293 switch (BGE_ASICREV(sc->bge_chipid)) { 3294 case BGE_ASICREV_BCM5714_A0: 3295 case BGE_ASICREV_BCM5714: 3296 /* 3297 * Apparently, MSI doesn't work when these chips are 3298 * configured in single-port mode. 3299 */ 3300 break; 3301 case BGE_ASICREV_BCM5750: 3302 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3303 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3304 can_use_msi = 1; 3305 break; 3306 default: 3307 if (BGE_IS_575X_PLUS(sc)) 3308 can_use_msi = 1; 3309 } 3310 return (can_use_msi); 3311 } 3312 #endif 3313 3314 /* 3315 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3316 * against our list and return its name if we find a match. Note 3317 * that since the Broadcom controller contains VPD support, we 3318 * can get the device name string from the controller itself instead 3319 * of the compiled-in string. This is a little slow, but it guarantees 3320 * we'll always announce the right product name. 3321 */ 3322 static int 3323 bge_probe(device_t parent, cfdata_t match, void *aux) 3324 { 3325 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3326 3327 if (bge_lookup(pa) != NULL) 3328 return 1; 3329 3330 return 0; 3331 } 3332 3333 static void 3334 bge_attach(device_t parent, device_t self, void *aux) 3335 { 3336 struct bge_softc *sc = device_private(self); 3337 struct pci_attach_args *pa = aux; 3338 prop_dictionary_t dict; 3339 const struct bge_product *bp; 3340 const struct bge_revision *br; 3341 pci_chipset_tag_t pc; 3342 #ifndef __HAVE_PCI_MSI_MSIX 3343 pci_intr_handle_t ih; 3344 #endif 3345 const char *intrstr = NULL; 3346 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3347 uint32_t command; 3348 struct ifnet *ifp; 3349 uint32_t misccfg, mimode; 3350 void * kva; 3351 u_char eaddr[ETHER_ADDR_LEN]; 3352 pcireg_t memtype, subid, reg; 3353 bus_addr_t memaddr; 3354 uint32_t pm_ctl; 3355 bool no_seeprom; 3356 int capmask; 3357 int mii_flags; 3358 int map_flags; 3359 #ifdef __HAVE_PCI_MSI_MSIX 3360 int rv; 3361 #endif 3362 char intrbuf[PCI_INTRSTR_LEN]; 3363 3364 bp = bge_lookup(pa); 3365 KASSERT(bp != NULL); 3366 3367 sc->sc_pc = pa->pa_pc; 3368 sc->sc_pcitag = pa->pa_tag; 3369 sc->bge_dev = self; 3370 3371 sc->bge_pa = *pa; 3372 pc = sc->sc_pc; 3373 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3374 3375 aprint_naive(": Ethernet controller\n"); 3376 aprint_normal(": %s\n", bp->bp_name); 3377 3378 /* 3379 * Map control/status registers. 3380 */ 3381 DPRINTFN(5, ("Map control/status regs\n")); 3382 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3383 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3384 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3385 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3386 3387 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3388 aprint_error_dev(sc->bge_dev, 3389 "failed to enable memory mapping!\n"); 3390 return; 3391 } 3392 3393 DPRINTFN(5, ("pci_mem_find\n")); 3394 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3395 switch (memtype) { 3396 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3397 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3398 #if 0 3399 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3400 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3401 &memaddr, &sc->bge_bsize) == 0) 3402 break; 3403 #else 3404 /* 3405 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3406 * system get NMI on boot (PR#48451). This problem might not be 3407 * the driver's bug but our PCI common part's bug. Until we 3408 * find a real reason, we ignore the prefetchable bit. 3409 */ 3410 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3411 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3412 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3413 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3414 map_flags, &sc->bge_bhandle) == 0) { 3415 sc->bge_btag = pa->pa_memt; 3416 break; 3417 } 3418 } 3419 #endif 3420 default: 3421 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3422 return; 3423 } 3424 3425 /* Save various chip information. */ 3426 sc->bge_chipid = bge_chipid(pa); 3427 sc->bge_phy_addr = bge_phy_addr(sc); 3428 3429 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3430 &sc->bge_pciecap, NULL) != 0) 3431 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 3432 /* PCIe */ 3433 sc->bge_flags |= BGEF_PCIE; 3434 /* Extract supported maximum payload size. */ 3435 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3436 sc->bge_pciecap + PCIE_DCAP); 3437 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3438 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3439 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3440 sc->bge_expmrq = 2048; 3441 else 3442 sc->bge_expmrq = 4096; 3443 bge_set_max_readrq(sc); 3444 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3445 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3446 /* PCI-X */ 3447 sc->bge_flags |= BGEF_PCIX; 3448 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3449 &sc->bge_pcixcap, NULL) == 0) 3450 aprint_error_dev(sc->bge_dev, 3451 "unable to find PCIX capability\n"); 3452 } 3453 3454 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3455 /* 3456 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3457 * can clobber the chip's PCI config-space power control 3458 * registers, leaving the card in D3 powersave state. We do 3459 * not have memory-mapped registers in this state, so force 3460 * device into D0 state before starting initialization. 3461 */ 3462 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3463 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3464 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3465 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3466 DELAY(1000); /* 27 usec is allegedly sufficent */ 3467 } 3468 3469 /* Save chipset family. */ 3470 switch (BGE_ASICREV(sc->bge_chipid)) { 3471 case BGE_ASICREV_BCM5717: 3472 case BGE_ASICREV_BCM5719: 3473 case BGE_ASICREV_BCM5720: 3474 sc->bge_flags |= BGEF_5717_PLUS; 3475 /* FALLTHROUGH */ 3476 case BGE_ASICREV_BCM57765: 3477 case BGE_ASICREV_BCM57766: 3478 if (!BGE_IS_5717_PLUS(sc)) 3479 sc->bge_flags |= BGEF_57765_FAMILY; 3480 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3481 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3482 /* Jumbo frame on BCM5719 A0 does not work. */ 3483 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3484 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3485 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3486 break; 3487 case BGE_ASICREV_BCM5755: 3488 case BGE_ASICREV_BCM5761: 3489 case BGE_ASICREV_BCM5784: 3490 case BGE_ASICREV_BCM5785: 3491 case BGE_ASICREV_BCM5787: 3492 case BGE_ASICREV_BCM57780: 3493 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3494 break; 3495 case BGE_ASICREV_BCM5700: 3496 case BGE_ASICREV_BCM5701: 3497 case BGE_ASICREV_BCM5703: 3498 case BGE_ASICREV_BCM5704: 3499 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3500 break; 3501 case BGE_ASICREV_BCM5714_A0: 3502 case BGE_ASICREV_BCM5780: 3503 case BGE_ASICREV_BCM5714: 3504 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3505 /* FALLTHROUGH */ 3506 case BGE_ASICREV_BCM5750: 3507 case BGE_ASICREV_BCM5752: 3508 case BGE_ASICREV_BCM5906: 3509 sc->bge_flags |= BGEF_575X_PLUS; 3510 /* FALLTHROUGH */ 3511 case BGE_ASICREV_BCM5705: 3512 sc->bge_flags |= BGEF_5705_PLUS; 3513 break; 3514 } 3515 3516 /* Identify chips with APE processor. */ 3517 switch (BGE_ASICREV(sc->bge_chipid)) { 3518 case BGE_ASICREV_BCM5717: 3519 case BGE_ASICREV_BCM5719: 3520 case BGE_ASICREV_BCM5720: 3521 case BGE_ASICREV_BCM5761: 3522 sc->bge_flags |= BGEF_APE; 3523 break; 3524 } 3525 3526 /* 3527 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3528 * not actually a MAC controller bug but an issue with the embedded 3529 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3530 */ 3531 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3532 sc->bge_flags |= BGEF_40BIT_BUG; 3533 3534 /* Chips with APE need BAR2 access for APE registers/memory. */ 3535 if ((sc->bge_flags & BGEF_APE) != 0) { 3536 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3537 #if 0 3538 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3539 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3540 &sc->bge_apesize)) { 3541 aprint_error_dev(sc->bge_dev, 3542 "couldn't map BAR2 memory\n"); 3543 return; 3544 } 3545 #else 3546 /* 3547 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3548 * system get NMI on boot (PR#48451). This problem might not be 3549 * the driver's bug but our PCI common part's bug. Until we 3550 * find a real reason, we ignore the prefetchable bit. 3551 */ 3552 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3553 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3554 aprint_error_dev(sc->bge_dev, 3555 "couldn't map BAR2 memory\n"); 3556 return; 3557 } 3558 3559 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3560 if (bus_space_map(pa->pa_memt, memaddr, 3561 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3562 aprint_error_dev(sc->bge_dev, 3563 "couldn't map BAR2 memory\n"); 3564 return; 3565 } 3566 sc->bge_apetag = pa->pa_memt; 3567 #endif 3568 3569 /* Enable APE register/memory access by host driver. */ 3570 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3571 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3572 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3573 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3574 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3575 3576 bge_ape_lock_init(sc); 3577 bge_ape_read_fw_ver(sc); 3578 } 3579 3580 /* Identify the chips that use an CPMU. */ 3581 if (BGE_IS_5717_PLUS(sc) || 3582 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3583 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3584 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3585 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3586 sc->bge_flags |= BGEF_CPMU_PRESENT; 3587 3588 /* Set MI_MODE */ 3589 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3590 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3591 mimode |= BGE_MIMODE_500KHZ_CONST; 3592 else 3593 mimode |= BGE_MIMODE_BASE; 3594 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3595 3596 /* 3597 * When using the BCM5701 in PCI-X mode, data corruption has 3598 * been observed in the first few bytes of some received packets. 3599 * Aligning the packet buffer in memory eliminates the corruption. 3600 * Unfortunately, this misaligns the packet payloads. On platforms 3601 * which do not support unaligned accesses, we will realign the 3602 * payloads by copying the received packets. 3603 */ 3604 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3605 sc->bge_flags & BGEF_PCIX) 3606 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3607 3608 if (BGE_IS_5700_FAMILY(sc)) 3609 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3610 3611 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3612 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3613 3614 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3615 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3616 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3617 sc->bge_flags |= BGEF_IS_5788; 3618 3619 /* 3620 * Some controllers seem to require a special firmware to use 3621 * TSO. But the firmware is not available to FreeBSD and Linux 3622 * claims that the TSO performed by the firmware is slower than 3623 * hardware based TSO. Moreover the firmware based TSO has one 3624 * known bug which can't handle TSO if ethernet header + IP/TCP 3625 * header is greater than 80 bytes. The workaround for the TSO 3626 * bug exist but it seems it's too expensive than not using 3627 * TSO at all. Some hardwares also have the TSO bug so limit 3628 * the TSO to the controllers that are not affected TSO issues 3629 * (e.g. 5755 or higher). 3630 */ 3631 if (BGE_IS_5755_PLUS(sc)) { 3632 /* 3633 * BCM5754 and BCM5787 shares the same ASIC id so 3634 * explicit device id check is required. 3635 */ 3636 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3637 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3638 sc->bge_flags |= BGEF_TSO; 3639 } 3640 3641 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3642 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3643 (misccfg == 0x4000 || misccfg == 0x8000)) || 3644 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3645 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3646 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3647 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3648 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3649 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3650 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3651 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3652 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3653 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3654 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3655 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3656 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3657 /* These chips are 10/100 only. */ 3658 capmask &= ~BMSR_EXTSTAT; 3659 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3660 } 3661 3662 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3663 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3664 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3665 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3666 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3667 3668 /* Set various PHY bug flags. */ 3669 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3670 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3671 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3672 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3673 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3674 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3675 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3676 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3677 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3678 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3679 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3680 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3681 if (BGE_IS_5705_PLUS(sc) && 3682 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3683 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3684 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3685 !BGE_IS_57765_PLUS(sc)) { 3686 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3687 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3688 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3689 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3690 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3691 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3692 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3693 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3694 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3695 } else 3696 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3697 } 3698 3699 /* 3700 * SEEPROM check. 3701 * First check if firmware knows we do not have SEEPROM. 3702 */ 3703 if (prop_dictionary_get_bool(device_properties(self), 3704 "without-seeprom", &no_seeprom) && no_seeprom) 3705 sc->bge_flags |= BGEF_NO_EEPROM; 3706 3707 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3708 sc->bge_flags |= BGEF_NO_EEPROM; 3709 3710 /* Now check the 'ROM failed' bit on the RX CPU */ 3711 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3712 sc->bge_flags |= BGEF_NO_EEPROM; 3713 3714 sc->bge_asf_mode = 0; 3715 /* No ASF if APE present. */ 3716 if ((sc->bge_flags & BGEF_APE) == 0) { 3717 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3718 BGE_SRAM_DATA_SIG_MAGIC)) { 3719 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3720 BGE_HWCFG_ASF) { 3721 sc->bge_asf_mode |= ASF_ENABLE; 3722 sc->bge_asf_mode |= ASF_STACKUP; 3723 if (BGE_IS_575X_PLUS(sc)) 3724 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3725 } 3726 } 3727 } 3728 3729 #ifdef __HAVE_PCI_MSI_MSIX 3730 DPRINTFN(5, ("pci_get_capability\n")); 3731 /* Check MSI capability */ 3732 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, 3733 &sc->bge_msicap, NULL) != 0) { 3734 if (bge_can_use_msi(sc) != 0) 3735 sc->bge_flags |= BGEF_MSI; 3736 } 3737 rv = -1; 3738 if (((sc->bge_flags & BGEF_MSI) != 0) && (pci_msi_count(pa) > 0)) { 3739 DPRINTFN(5, ("pci_msi_alloc\n")); 3740 rv = pci_msi_alloc_exact(pa, &sc->bge_pihp, 1); 3741 if (rv != 0) 3742 sc->bge_flags &= ~BGEF_MSI; 3743 } 3744 if (rv != 0) { 3745 DPRINTFN(5, ("pci_intx_alloc\n")); 3746 if (pci_intx_alloc(pa, &sc->bge_pihp)) { 3747 aprint_error_dev(self, "can't map interrupt\n"); 3748 return; 3749 } 3750 sc->bge_flags &= ~BGEF_MSI; 3751 } 3752 #else /* !__HAVE_PCI_MSI_MSIX */ 3753 DPRINTFN(5, ("pci_intr_map\n")); 3754 if (pci_intr_map(pa, &ih)) { 3755 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 3756 return; 3757 } 3758 #endif 3759 3760 #ifdef __HAVE_PCI_MSI_MSIX 3761 DPRINTFN(5, ("pci_intr_string\n")); 3762 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3763 sizeof(intrbuf)); 3764 DPRINTFN(5, ("pci_intr_establish\n")); 3765 sc->bge_intrhand = pci_intr_establish(pc, sc->bge_pihp[0], IPL_NET, 3766 bge_intr, sc); 3767 #else /* !__HAVE_PCI_MSI_MSIX */ 3768 DPRINTFN(5, ("pci_intr_string\n")); 3769 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 3770 3771 DPRINTFN(5, ("pci_intr_establish\n")); 3772 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 3773 #endif 3774 3775 if (sc->bge_intrhand == NULL) { 3776 aprint_error_dev(sc->bge_dev, 3777 "couldn't establish interrupt%s%s\n", 3778 intrstr ? " at " : "", intrstr ? intrstr : ""); 3779 return; 3780 } 3781 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3782 3783 /* 3784 * All controllers except BCM5700 supports tagged status but 3785 * we use tagged status only for MSI case on BCM5717. Otherwise 3786 * MSI on BCM5717 does not work. 3787 */ 3788 if (BGE_IS_5717_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3789 sc->bge_flags |= BGEF_TAGGED_STATUS; 3790 3791 /* 3792 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3793 * lock in bge_reset(). 3794 */ 3795 CSR_WRITE_4(sc, BGE_EE_ADDR, 3796 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3797 delay(1000); 3798 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3799 3800 bge_stop_fw(sc); 3801 bge_sig_pre_reset(sc, BGE_RESET_START); 3802 if (bge_reset(sc)) 3803 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3804 3805 /* 3806 * Read the hardware config word in the first 32k of NIC internal 3807 * memory, or fall back to the config word in the EEPROM. 3808 * Note: on some BCM5700 cards, this value appears to be unset. 3809 */ 3810 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3811 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3812 BGE_SRAM_DATA_SIG_MAGIC) { 3813 uint32_t tmp; 3814 3815 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3816 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3817 BGE_SRAM_DATA_VER_SHIFT; 3818 if ((0 < tmp) && (tmp < 0x100)) 3819 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3820 if (sc->bge_flags & BGEF_PCIE) 3821 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3823 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3824 if (BGE_IS_5717_PLUS(sc)) 3825 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3826 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3827 bge_read_eeprom(sc, (void *)&hwcfg, 3828 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3829 hwcfg = be32toh(hwcfg); 3830 } 3831 aprint_normal_dev(sc->bge_dev, 3832 "HW config %08x, %08x, %08x, %08x %08x\n", 3833 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3834 3835 bge_sig_legacy(sc, BGE_RESET_START); 3836 bge_sig_post_reset(sc, BGE_RESET_START); 3837 3838 if (bge_chipinit(sc)) { 3839 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3840 bge_release_resources(sc); 3841 return; 3842 } 3843 3844 /* 3845 * Get station address from the EEPROM. 3846 */ 3847 if (bge_get_eaddr(sc, eaddr)) { 3848 aprint_error_dev(sc->bge_dev, 3849 "failed to read station address\n"); 3850 bge_release_resources(sc); 3851 return; 3852 } 3853 3854 br = bge_lookup_rev(sc->bge_chipid); 3855 3856 if (br == NULL) { 3857 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3858 sc->bge_chipid); 3859 } else { 3860 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3861 br->br_name, sc->bge_chipid); 3862 } 3863 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3864 3865 /* Allocate the general information block and ring buffers. */ 3866 if (pci_dma64_available(pa)) 3867 sc->bge_dmatag = pa->pa_dmat64; 3868 else 3869 sc->bge_dmatag = pa->pa_dmat; 3870 3871 /* 40bit DMA workaround */ 3872 if (sizeof(bus_addr_t) > 4) { 3873 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3874 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3875 3876 if (bus_dmatag_subregion(olddmatag, 0, 3877 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3878 BUS_DMA_NOWAIT) != 0) { 3879 aprint_error_dev(self, 3880 "WARNING: failed to restrict dma range," 3881 " falling back to parent bus dma range\n"); 3882 sc->bge_dmatag = olddmatag; 3883 } 3884 } 3885 } 3886 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3887 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3888 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3889 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3890 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3891 return; 3892 } 3893 DPRINTFN(5, ("bus_dmamem_map\n")); 3894 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3895 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3896 BUS_DMA_NOWAIT)) { 3897 aprint_error_dev(sc->bge_dev, 3898 "can't map DMA buffers (%zu bytes)\n", 3899 sizeof(struct bge_ring_data)); 3900 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3901 sc->bge_ring_rseg); 3902 return; 3903 } 3904 DPRINTFN(5, ("bus_dmamem_create\n")); 3905 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3906 sizeof(struct bge_ring_data), 0, 3907 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3908 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3909 bus_dmamem_unmap(sc->bge_dmatag, kva, 3910 sizeof(struct bge_ring_data)); 3911 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3912 sc->bge_ring_rseg); 3913 return; 3914 } 3915 DPRINTFN(5, ("bus_dmamem_load\n")); 3916 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3917 sizeof(struct bge_ring_data), NULL, 3918 BUS_DMA_NOWAIT)) { 3919 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3920 bus_dmamem_unmap(sc->bge_dmatag, kva, 3921 sizeof(struct bge_ring_data)); 3922 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3923 sc->bge_ring_rseg); 3924 return; 3925 } 3926 3927 DPRINTFN(5, ("bzero\n")); 3928 sc->bge_rdata = (struct bge_ring_data *)kva; 3929 3930 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3931 3932 /* Try to allocate memory for jumbo buffers. */ 3933 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3934 if (bge_alloc_jumbo_mem(sc)) { 3935 aprint_error_dev(sc->bge_dev, 3936 "jumbo buffer allocation failed\n"); 3937 } else 3938 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3939 } 3940 3941 /* Set default tuneable values. */ 3942 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3943 sc->bge_rx_coal_ticks = 150; 3944 sc->bge_rx_max_coal_bds = 64; 3945 sc->bge_tx_coal_ticks = 300; 3946 sc->bge_tx_max_coal_bds = 400; 3947 if (BGE_IS_5705_PLUS(sc)) { 3948 sc->bge_tx_coal_ticks = (12 * 5); 3949 sc->bge_tx_max_coal_bds = (12 * 5); 3950 aprint_verbose_dev(sc->bge_dev, 3951 "setting short Tx thresholds\n"); 3952 } 3953 3954 if (BGE_IS_5717_PLUS(sc)) 3955 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3956 else if (BGE_IS_5705_PLUS(sc)) 3957 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3958 else 3959 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3960 3961 /* Set up ifnet structure */ 3962 ifp = &sc->ethercom.ec_if; 3963 ifp->if_softc = sc; 3964 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3965 ifp->if_ioctl = bge_ioctl; 3966 ifp->if_stop = bge_stop; 3967 ifp->if_start = bge_start; 3968 ifp->if_init = bge_init; 3969 ifp->if_watchdog = bge_watchdog; 3970 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3971 IFQ_SET_READY(&ifp->if_snd); 3972 DPRINTFN(5, ("strcpy if_xname\n")); 3973 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3974 3975 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3976 sc->ethercom.ec_if.if_capabilities |= 3977 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3978 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3979 sc->ethercom.ec_if.if_capabilities |= 3980 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3981 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3982 #endif 3983 sc->ethercom.ec_capabilities |= 3984 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3985 3986 if (sc->bge_flags & BGEF_TSO) 3987 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3988 3989 /* 3990 * Do MII setup. 3991 */ 3992 DPRINTFN(5, ("mii setup\n")); 3993 sc->bge_mii.mii_ifp = ifp; 3994 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3995 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3996 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3997 3998 /* 3999 * Figure out what sort of media we have by checking the hardware 4000 * config word. Note: on some BCM5700 cards, this value appears to be 4001 * unset. If that's the case, we have to rely on identifying the NIC 4002 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 4003 * The SysKonnect SK-9D41 is a 1000baseSX card. 4004 */ 4005 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 4006 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 4007 if (BGE_IS_5705_PLUS(sc)) { 4008 sc->bge_flags |= BGEF_FIBER_MII; 4009 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 4010 } else 4011 sc->bge_flags |= BGEF_FIBER_TBI; 4012 } 4013 4014 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 4015 if (BGE_IS_JUMBO_CAPABLE(sc)) 4016 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 4017 4018 /* set phyflags and chipid before mii_attach() */ 4019 dict = device_properties(self); 4020 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 4021 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 4022 4023 if (sc->bge_flags & BGEF_FIBER_TBI) { 4024 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 4025 bge_ifmedia_sts); 4026 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 4027 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 4028 0, NULL); 4029 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 4030 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 4031 /* Pretend the user requested this setting */ 4032 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 4033 } else { 4034 /* 4035 * Do transceiver setup and tell the firmware the 4036 * driver is down so we can try to get access the 4037 * probe if ASF is running. Retry a couple of times 4038 * if we get a conflict with the ASF firmware accessing 4039 * the PHY. 4040 */ 4041 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4042 bge_asf_driver_up(sc); 4043 4044 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 4045 bge_ifmedia_sts); 4046 mii_flags = MIIF_DOPAUSE; 4047 if (sc->bge_flags & BGEF_FIBER_MII) 4048 mii_flags |= MIIF_HAVEFIBER; 4049 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 4050 MII_OFFSET_ANY, mii_flags); 4051 4052 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 4053 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4054 ifmedia_add(&sc->bge_mii.mii_media, 4055 IFM_ETHER|IFM_MANUAL, 0, NULL); 4056 ifmedia_set(&sc->bge_mii.mii_media, 4057 IFM_ETHER|IFM_MANUAL); 4058 } else 4059 ifmedia_set(&sc->bge_mii.mii_media, 4060 IFM_ETHER|IFM_AUTO); 4061 4062 /* 4063 * Now tell the firmware we are going up after probing the PHY 4064 */ 4065 if (sc->bge_asf_mode & ASF_STACKUP) 4066 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4067 } 4068 4069 /* 4070 * Call MI attach routine. 4071 */ 4072 DPRINTFN(5, ("if_attach\n")); 4073 if_attach(ifp); 4074 DPRINTFN(5, ("ether_ifattach\n")); 4075 ether_ifattach(ifp, eaddr); 4076 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4077 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4078 RND_TYPE_NET, RND_FLAG_DEFAULT); 4079 #ifdef BGE_EVENT_COUNTERS 4080 /* 4081 * Attach event counters. 4082 */ 4083 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4084 NULL, device_xname(sc->bge_dev), "intr"); 4085 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4086 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4087 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4088 NULL, device_xname(sc->bge_dev), "tx_xon"); 4089 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4090 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4091 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4092 NULL, device_xname(sc->bge_dev), "rx_xon"); 4093 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4094 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4095 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4096 NULL, device_xname(sc->bge_dev), "xoffentered"); 4097 #endif /* BGE_EVENT_COUNTERS */ 4098 DPRINTFN(5, ("callout_init\n")); 4099 callout_init(&sc->bge_timeout, 0); 4100 4101 if (pmf_device_register(self, NULL, NULL)) 4102 pmf_class_network_register(self, ifp); 4103 else 4104 aprint_error_dev(self, "couldn't establish power handler\n"); 4105 4106 bge_sysctl_init(sc); 4107 4108 #ifdef BGE_DEBUG 4109 bge_debug_info(sc); 4110 #endif 4111 } 4112 4113 /* 4114 * Stop all chip I/O so that the kernel's probe routines don't 4115 * get confused by errant DMAs when rebooting. 4116 */ 4117 static int 4118 bge_detach(device_t self, int flags __unused) 4119 { 4120 struct bge_softc *sc = device_private(self); 4121 struct ifnet *ifp = &sc->ethercom.ec_if; 4122 int s; 4123 4124 s = splnet(); 4125 /* Stop the interface. Callouts are stopped in it. */ 4126 bge_stop(ifp, 1); 4127 splx(s); 4128 4129 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4130 4131 /* Delete all remaining media. */ 4132 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4133 4134 ether_ifdetach(ifp); 4135 if_detach(ifp); 4136 4137 bge_release_resources(sc); 4138 4139 return 0; 4140 } 4141 4142 static void 4143 bge_release_resources(struct bge_softc *sc) 4144 { 4145 4146 /* Disestablish the interrupt handler */ 4147 if (sc->bge_intrhand != NULL) { 4148 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4149 #ifdef __HAVE_PCI_MSI_MSIX 4150 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4151 #endif 4152 sc->bge_intrhand = NULL; 4153 } 4154 4155 if (sc->bge_dmatag != NULL) { 4156 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4157 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4158 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4159 sizeof(struct bge_ring_data)); 4160 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_rseg); 4161 } 4162 4163 /* Unmap the device registers */ 4164 if (sc->bge_bsize != 0) { 4165 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4166 sc->bge_bsize = 0; 4167 } 4168 4169 /* Unmap the APE registers */ 4170 if (sc->bge_apesize != 0) { 4171 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4172 sc->bge_apesize); 4173 sc->bge_apesize = 0; 4174 } 4175 } 4176 4177 static int 4178 bge_reset(struct bge_softc *sc) 4179 { 4180 uint32_t cachesize, command; 4181 uint32_t reset, mac_mode, mac_mode_mask; 4182 pcireg_t devctl, reg; 4183 int i, val; 4184 void (*write_op)(struct bge_softc *, int, int); 4185 4186 /* Make mask for BGE_MAC_MODE register. */ 4187 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4188 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4189 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4190 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4191 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4192 4193 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4194 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4195 if (sc->bge_flags & BGEF_PCIE) 4196 write_op = bge_writemem_direct; 4197 else 4198 write_op = bge_writemem_ind; 4199 } else 4200 write_op = bge_writereg_ind; 4201 4202 /* 57XX step 4 */ 4203 /* Acquire the NVM lock */ 4204 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4205 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4206 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4207 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4208 for (i = 0; i < 8000; i++) { 4209 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4210 BGE_NVRAMSWARB_GNT1) 4211 break; 4212 DELAY(20); 4213 } 4214 if (i == 8000) { 4215 printf("%s: NVRAM lock timedout!\n", 4216 device_xname(sc->bge_dev)); 4217 } 4218 } 4219 4220 /* Take APE lock when performing reset. */ 4221 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4222 4223 /* 57XX step 3 */ 4224 /* Save some important PCI state. */ 4225 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4226 /* 5718 reset step 3 */ 4227 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4228 4229 /* 5718 reset step 5, 57XX step 5b-5d */ 4230 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4231 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4232 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4233 4234 /* XXX ???: Disable fastboot on controllers that support it. */ 4235 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4236 BGE_IS_5755_PLUS(sc)) 4237 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4238 4239 /* 5718 reset step 2, 57XX step 6 */ 4240 /* 4241 * Write the magic number to SRAM at offset 0xB50. 4242 * When firmware finishes its initialization it will 4243 * write ~BGE_MAGIC_NUMBER to the same location. 4244 */ 4245 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4246 4247 /* 5718 reset step 6, 57XX step 7 */ 4248 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4249 /* 4250 * XXX: from FreeBSD/Linux; no documentation 4251 */ 4252 if (sc->bge_flags & BGEF_PCIE) { 4253 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4254 !BGE_IS_57765_PLUS(sc) && 4255 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4256 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4257 /* PCI Express 1.0 system */ 4258 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4259 BGE_PHY_PCIE_SCRAM_MODE); 4260 } 4261 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4262 /* 4263 * Prevent PCI Express link training 4264 * during global reset. 4265 */ 4266 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4267 reset |= (1 << 29); 4268 } 4269 } 4270 4271 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4272 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4273 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4274 i | BGE_VCPU_STATUS_DRV_RESET); 4275 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4276 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4277 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4278 } 4279 4280 /* 4281 * Set GPHY Power Down Override to leave GPHY 4282 * powered up in D0 uninitialized. 4283 */ 4284 if (BGE_IS_5705_PLUS(sc) && 4285 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4286 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4287 4288 /* Issue global reset */ 4289 write_op(sc, BGE_MISC_CFG, reset); 4290 4291 /* 5718 reset step 7, 57XX step 8 */ 4292 if (sc->bge_flags & BGEF_PCIE) 4293 delay(100*1000); /* too big */ 4294 else 4295 delay(1000); 4296 4297 if (sc->bge_flags & BGEF_PCIE) { 4298 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4299 DELAY(500000); 4300 /* XXX: Magic Numbers */ 4301 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4302 BGE_PCI_UNKNOWN0); 4303 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4304 BGE_PCI_UNKNOWN0, 4305 reg | (1 << 15)); 4306 } 4307 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4308 sc->bge_pciecap + PCIE_DCSR); 4309 /* Clear enable no snoop and disable relaxed ordering. */ 4310 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4311 PCIE_DCSR_ENA_NO_SNOOP); 4312 4313 /* Set PCIE max payload size to 128 for older PCIe devices */ 4314 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4315 devctl &= ~(0x00e0); 4316 /* Clear device status register. Write 1b to clear */ 4317 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4318 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4319 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4320 sc->bge_pciecap + PCIE_DCSR, devctl); 4321 bge_set_max_readrq(sc); 4322 } 4323 4324 /* From Linux: dummy read to flush PCI posted writes */ 4325 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4326 4327 /* 4328 * Reset some of the PCI state that got zapped by reset 4329 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4330 * set, too. 4331 */ 4332 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4333 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4334 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4335 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4336 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4337 (sc->bge_flags & BGEF_PCIX) != 0) 4338 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4339 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4340 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4341 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4342 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4343 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4344 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4345 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4346 4347 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4348 if (sc->bge_flags & BGEF_PCIX) { 4349 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4350 + PCIX_CMD); 4351 /* Set max memory read byte count to 2K */ 4352 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4353 reg &= ~PCIX_CMD_BYTECNT_MASK; 4354 reg |= PCIX_CMD_BCNT_2048; 4355 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4356 /* 4357 * For 5704, set max outstanding split transaction 4358 * field to 0 (0 means it supports 1 request) 4359 */ 4360 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4361 | PCIX_CMD_BYTECNT_MASK); 4362 reg |= PCIX_CMD_BCNT_2048; 4363 } 4364 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4365 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4366 } 4367 4368 /* 5718 reset step 10, 57XX step 12 */ 4369 /* Enable memory arbiter. */ 4370 if (BGE_IS_5714_FAMILY(sc)) { 4371 val = CSR_READ_4(sc, BGE_MARB_MODE); 4372 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4373 } else 4374 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4375 4376 /* XXX 5721, 5751 and 5752 */ 4377 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4378 /* Step 19: */ 4379 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4380 /* Step 20: */ 4381 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4382 } 4383 4384 /* 5718 reset step 12, 57XX step 15 and 16 */ 4385 /* Fix up byte swapping */ 4386 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4387 4388 /* 5718 reset step 13, 57XX step 17 */ 4389 /* Poll until the firmware initialization is complete */ 4390 bge_poll_fw(sc); 4391 4392 /* 57XX step 21 */ 4393 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4394 pcireg_t msidata; 4395 4396 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4397 BGE_PCI_MSI_DATA); 4398 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4399 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4400 msidata); 4401 } 4402 4403 /* 57XX step 18 */ 4404 /* Write mac mode. */ 4405 val = CSR_READ_4(sc, BGE_MAC_MODE); 4406 /* Restore mac_mode_mask's bits using mac_mode */ 4407 val = (val & ~mac_mode_mask) | mac_mode; 4408 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4409 DELAY(40); 4410 4411 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4412 4413 /* 4414 * The 5704 in TBI mode apparently needs some special 4415 * adjustment to insure the SERDES drive level is set 4416 * to 1.2V. 4417 */ 4418 if (sc->bge_flags & BGEF_FIBER_TBI && 4419 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4420 uint32_t serdescfg; 4421 4422 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4423 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4424 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4425 } 4426 4427 if (sc->bge_flags & BGEF_PCIE && 4428 !BGE_IS_57765_PLUS(sc) && 4429 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4430 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4431 uint32_t v; 4432 4433 /* Enable PCI Express bug fix */ 4434 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4435 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4436 v | BGE_TLP_DATA_FIFO_PROTECT); 4437 } 4438 4439 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4440 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4441 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4442 4443 return 0; 4444 } 4445 4446 /* 4447 * Frame reception handling. This is called if there's a frame 4448 * on the receive return list. 4449 * 4450 * Note: we have to be able to handle two possibilities here: 4451 * 1) the frame is from the jumbo receive ring 4452 * 2) the frame is from the standard receive ring 4453 */ 4454 4455 static void 4456 bge_rxeof(struct bge_softc *sc) 4457 { 4458 struct ifnet *ifp; 4459 uint16_t rx_prod, rx_cons; 4460 int stdcnt = 0, jumbocnt = 0; 4461 bus_dmamap_t dmamap; 4462 bus_addr_t offset, toff; 4463 bus_size_t tlen; 4464 int tosync; 4465 4466 rx_cons = sc->bge_rx_saved_considx; 4467 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4468 4469 /* Nothing to do */ 4470 if (rx_cons == rx_prod) 4471 return; 4472 4473 ifp = &sc->ethercom.ec_if; 4474 4475 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4476 offsetof(struct bge_ring_data, bge_status_block), 4477 sizeof (struct bge_status_block), 4478 BUS_DMASYNC_POSTREAD); 4479 4480 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4481 tosync = rx_prod - rx_cons; 4482 4483 if (tosync != 0) 4484 rnd_add_uint32(&sc->rnd_source, tosync); 4485 4486 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4487 4488 if (tosync < 0) { 4489 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4490 sizeof (struct bge_rx_bd); 4491 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4492 toff, tlen, BUS_DMASYNC_POSTREAD); 4493 tosync = -tosync; 4494 } 4495 4496 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4497 offset, tosync * sizeof (struct bge_rx_bd), 4498 BUS_DMASYNC_POSTREAD); 4499 4500 while (rx_cons != rx_prod) { 4501 struct bge_rx_bd *cur_rx; 4502 uint32_t rxidx; 4503 struct mbuf *m = NULL; 4504 4505 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4506 4507 rxidx = cur_rx->bge_idx; 4508 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4509 4510 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4511 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4512 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4513 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4514 jumbocnt++; 4515 bus_dmamap_sync(sc->bge_dmatag, 4516 sc->bge_cdata.bge_rx_jumbo_map, 4517 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4518 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4519 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4520 ifp->if_ierrors++; 4521 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4522 continue; 4523 } 4524 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4525 NULL)== ENOBUFS) { 4526 ifp->if_ierrors++; 4527 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4528 continue; 4529 } 4530 } else { 4531 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4532 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4533 4534 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4535 stdcnt++; 4536 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4537 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4538 if (dmamap == NULL) { 4539 ifp->if_ierrors++; 4540 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4541 continue; 4542 } 4543 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4544 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4545 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4546 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4547 ifp->if_ierrors++; 4548 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4549 continue; 4550 } 4551 if (bge_newbuf_std(sc, sc->bge_std, 4552 NULL, dmamap) == ENOBUFS) { 4553 ifp->if_ierrors++; 4554 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4555 continue; 4556 } 4557 } 4558 4559 ifp->if_ipackets++; 4560 #ifndef __NO_STRICT_ALIGNMENT 4561 /* 4562 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4563 * the Rx buffer has the layer-2 header unaligned. 4564 * If our CPU requires alignment, re-align by copying. 4565 */ 4566 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4567 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4568 cur_rx->bge_len); 4569 m->m_data += ETHER_ALIGN; 4570 } 4571 #endif 4572 4573 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4574 m->m_pkthdr.rcvif = ifp; 4575 4576 /* 4577 * Handle BPF listeners. Let the BPF user see the packet. 4578 */ 4579 bpf_mtap(ifp, m); 4580 4581 bge_rxcsum(sc, cur_rx, m); 4582 4583 /* 4584 * If we received a packet with a vlan tag, pass it 4585 * to vlan_input() instead of ether_input(). 4586 */ 4587 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4588 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 4589 } 4590 4591 (*ifp->if_input)(ifp, m); 4592 } 4593 4594 sc->bge_rx_saved_considx = rx_cons; 4595 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4596 if (stdcnt) 4597 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4598 if (jumbocnt) 4599 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4600 } 4601 4602 static void 4603 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4604 { 4605 4606 if (BGE_IS_57765_PLUS(sc)) { 4607 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4608 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4609 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4610 if ((cur_rx->bge_error_flag & 4611 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4612 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4613 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4614 m->m_pkthdr.csum_data = 4615 cur_rx->bge_tcp_udp_csum; 4616 m->m_pkthdr.csum_flags |= 4617 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4618 M_CSUM_DATA); 4619 } 4620 } 4621 } else { 4622 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4623 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4624 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4625 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4626 /* 4627 * Rx transport checksum-offload may also 4628 * have bugs with packets which, when transmitted, 4629 * were `runts' requiring padding. 4630 */ 4631 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4632 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4633 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4634 m->m_pkthdr.csum_data = 4635 cur_rx->bge_tcp_udp_csum; 4636 m->m_pkthdr.csum_flags |= 4637 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4638 M_CSUM_DATA); 4639 } 4640 } 4641 } 4642 4643 static void 4644 bge_txeof(struct bge_softc *sc) 4645 { 4646 struct bge_tx_bd *cur_tx = NULL; 4647 struct ifnet *ifp; 4648 struct txdmamap_pool_entry *dma; 4649 bus_addr_t offset, toff; 4650 bus_size_t tlen; 4651 int tosync; 4652 struct mbuf *m; 4653 4654 ifp = &sc->ethercom.ec_if; 4655 4656 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4657 offsetof(struct bge_ring_data, bge_status_block), 4658 sizeof (struct bge_status_block), 4659 BUS_DMASYNC_POSTREAD); 4660 4661 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4662 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4663 sc->bge_tx_saved_considx; 4664 4665 if (tosync != 0) 4666 rnd_add_uint32(&sc->rnd_source, tosync); 4667 4668 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4669 4670 if (tosync < 0) { 4671 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4672 sizeof (struct bge_tx_bd); 4673 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4674 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4675 tosync = -tosync; 4676 } 4677 4678 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4679 offset, tosync * sizeof (struct bge_tx_bd), 4680 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4681 4682 /* 4683 * Go through our tx ring and free mbufs for those 4684 * frames that have been sent. 4685 */ 4686 while (sc->bge_tx_saved_considx != 4687 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4688 uint32_t idx = 0; 4689 4690 idx = sc->bge_tx_saved_considx; 4691 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4692 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4693 ifp->if_opackets++; 4694 m = sc->bge_cdata.bge_tx_chain[idx]; 4695 if (m != NULL) { 4696 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4697 dma = sc->txdma[idx]; 4698 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4699 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4700 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4701 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4702 sc->txdma[idx] = NULL; 4703 4704 m_freem(m); 4705 } 4706 sc->bge_txcnt--; 4707 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4708 ifp->if_timer = 0; 4709 } 4710 4711 if (cur_tx != NULL) 4712 ifp->if_flags &= ~IFF_OACTIVE; 4713 } 4714 4715 static int 4716 bge_intr(void *xsc) 4717 { 4718 struct bge_softc *sc; 4719 struct ifnet *ifp; 4720 uint32_t pcistate, statusword, statustag; 4721 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4722 4723 sc = xsc; 4724 ifp = &sc->ethercom.ec_if; 4725 4726 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4727 if (BGE_IS_5717_PLUS(sc)) 4728 intrmask = 0; 4729 4730 /* It is possible for the interrupt to arrive before 4731 * the status block is updated prior to the interrupt. 4732 * Reading the PCI State register will confirm whether the 4733 * interrupt is ours and will flush the status block. 4734 */ 4735 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4736 4737 /* read status word from status block */ 4738 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4739 offsetof(struct bge_ring_data, bge_status_block), 4740 sizeof (struct bge_status_block), 4741 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4742 statusword = sc->bge_rdata->bge_status_block.bge_status; 4743 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4744 4745 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4746 if (sc->bge_lasttag == statustag && 4747 (~pcistate & intrmask)) { 4748 return (0); 4749 } 4750 sc->bge_lasttag = statustag; 4751 } else { 4752 if (!(statusword & BGE_STATFLAG_UPDATED) && 4753 !(~pcistate & intrmask)) { 4754 return (0); 4755 } 4756 statustag = 0; 4757 } 4758 /* Ack interrupt and stop others from occurring. */ 4759 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4760 BGE_EVCNT_INCR(sc->bge_ev_intr); 4761 4762 /* clear status word */ 4763 sc->bge_rdata->bge_status_block.bge_status = 0; 4764 4765 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4766 offsetof(struct bge_ring_data, bge_status_block), 4767 sizeof (struct bge_status_block), 4768 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4769 4770 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4771 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4772 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4773 bge_link_upd(sc); 4774 4775 if (ifp->if_flags & IFF_RUNNING) { 4776 /* Check RX return ring producer/consumer */ 4777 bge_rxeof(sc); 4778 4779 /* Check TX ring producer/consumer */ 4780 bge_txeof(sc); 4781 } 4782 4783 if (sc->bge_pending_rxintr_change) { 4784 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4785 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4786 4787 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4788 DELAY(10); 4789 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4790 4791 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4792 DELAY(10); 4793 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4794 4795 sc->bge_pending_rxintr_change = 0; 4796 } 4797 bge_handle_events(sc); 4798 4799 /* Re-enable interrupts. */ 4800 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4801 4802 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 4803 bge_start(ifp); 4804 4805 return 1; 4806 } 4807 4808 static void 4809 bge_asf_driver_up(struct bge_softc *sc) 4810 { 4811 if (sc->bge_asf_mode & ASF_STACKUP) { 4812 /* Send ASF heartbeat aprox. every 2s */ 4813 if (sc->bge_asf_count) 4814 sc->bge_asf_count --; 4815 else { 4816 sc->bge_asf_count = 2; 4817 4818 bge_wait_for_event_ack(sc); 4819 4820 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4821 BGE_FW_CMD_DRV_ALIVE3); 4822 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4823 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4824 BGE_FW_HB_TIMEOUT_SEC); 4825 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4826 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4827 BGE_RX_CPU_DRV_EVENT); 4828 } 4829 } 4830 } 4831 4832 static void 4833 bge_tick(void *xsc) 4834 { 4835 struct bge_softc *sc = xsc; 4836 struct mii_data *mii = &sc->bge_mii; 4837 int s; 4838 4839 s = splnet(); 4840 4841 if (BGE_IS_5705_PLUS(sc)) 4842 bge_stats_update_regs(sc); 4843 else 4844 bge_stats_update(sc); 4845 4846 if (sc->bge_flags & BGEF_FIBER_TBI) { 4847 /* 4848 * Since in TBI mode auto-polling can't be used we should poll 4849 * link status manually. Here we register pending link event 4850 * and trigger interrupt. 4851 */ 4852 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4853 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4854 } else { 4855 /* 4856 * Do not touch PHY if we have link up. This could break 4857 * IPMI/ASF mode or produce extra input errors. 4858 * (extra input errors was reported for bcm5701 & bcm5704). 4859 */ 4860 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4861 mii_tick(mii); 4862 } 4863 4864 bge_asf_driver_up(sc); 4865 4866 if (!sc->bge_detaching) 4867 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4868 4869 splx(s); 4870 } 4871 4872 static void 4873 bge_stats_update_regs(struct bge_softc *sc) 4874 { 4875 struct ifnet *ifp = &sc->ethercom.ec_if; 4876 4877 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4878 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4879 4880 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4881 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4882 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4883 } 4884 4885 static void 4886 bge_stats_update(struct bge_softc *sc) 4887 { 4888 struct ifnet *ifp = &sc->ethercom.ec_if; 4889 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4890 4891 #define READ_STAT(sc, stats, stat) \ 4892 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4893 4894 ifp->if_collisions += 4895 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4896 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4897 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4898 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4899 ifp->if_collisions; 4900 4901 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4902 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4903 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4904 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4905 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4906 READ_STAT(sc, stats, 4907 xoffPauseFramesReceived.bge_addr_lo)); 4908 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4909 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4910 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4911 READ_STAT(sc, stats, 4912 macControlFramesReceived.bge_addr_lo)); 4913 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4914 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4915 4916 #undef READ_STAT 4917 4918 #ifdef notdef 4919 ifp->if_collisions += 4920 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4921 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4922 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4923 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4924 ifp->if_collisions; 4925 #endif 4926 } 4927 4928 /* 4929 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4930 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4931 * but when such padded frames employ the bge IP/TCP checksum offload, 4932 * the hardware checksum assist gives incorrect results (possibly 4933 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4934 * If we pad such runts with zeros, the onboard checksum comes out correct. 4935 */ 4936 static inline int 4937 bge_cksum_pad(struct mbuf *pkt) 4938 { 4939 struct mbuf *last = NULL; 4940 int padlen; 4941 4942 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4943 4944 /* if there's only the packet-header and we can pad there, use it. */ 4945 if (pkt->m_pkthdr.len == pkt->m_len && 4946 M_TRAILINGSPACE(pkt) >= padlen) { 4947 last = pkt; 4948 } else { 4949 /* 4950 * Walk packet chain to find last mbuf. We will either 4951 * pad there, or append a new mbuf and pad it 4952 * (thus perhaps avoiding the bcm5700 dma-min bug). 4953 */ 4954 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4955 continue; /* do nothing */ 4956 } 4957 4958 /* `last' now points to last in chain. */ 4959 if (M_TRAILINGSPACE(last) < padlen) { 4960 /* Allocate new empty mbuf, pad it. Compact later. */ 4961 struct mbuf *n; 4962 MGET(n, M_DONTWAIT, MT_DATA); 4963 if (n == NULL) 4964 return ENOBUFS; 4965 n->m_len = 0; 4966 last->m_next = n; 4967 last = n; 4968 } 4969 } 4970 4971 KDASSERT(!M_READONLY(last)); 4972 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4973 4974 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4975 memset(mtod(last, char *) + last->m_len, 0, padlen); 4976 last->m_len += padlen; 4977 pkt->m_pkthdr.len += padlen; 4978 return 0; 4979 } 4980 4981 /* 4982 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4983 */ 4984 static inline int 4985 bge_compact_dma_runt(struct mbuf *pkt) 4986 { 4987 struct mbuf *m, *prev; 4988 int totlen; 4989 4990 prev = NULL; 4991 totlen = 0; 4992 4993 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4994 int mlen = m->m_len; 4995 int shortfall = 8 - mlen ; 4996 4997 totlen += mlen; 4998 if (mlen == 0) 4999 continue; 5000 if (mlen >= 8) 5001 continue; 5002 5003 /* If we get here, mbuf data is too small for DMA engine. 5004 * Try to fix by shuffling data to prev or next in chain. 5005 * If that fails, do a compacting deep-copy of the whole chain. 5006 */ 5007 5008 /* Internal frag. If fits in prev, copy it there. */ 5009 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5010 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5011 prev->m_len += mlen; 5012 m->m_len = 0; 5013 /* XXX stitch chain */ 5014 prev->m_next = m_free(m); 5015 m = prev; 5016 continue; 5017 } 5018 else if (m->m_next != NULL && 5019 M_TRAILINGSPACE(m) >= shortfall && 5020 m->m_next->m_len >= (8 + shortfall)) { 5021 /* m is writable and have enough data in next, pull up. */ 5022 5023 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5024 shortfall); 5025 m->m_len += shortfall; 5026 m->m_next->m_len -= shortfall; 5027 m->m_next->m_data += shortfall; 5028 } 5029 else if (m->m_next == NULL || 1) { 5030 /* Got a runt at the very end of the packet. 5031 * borrow data from the tail of the preceding mbuf and 5032 * update its length in-place. (The original data is still 5033 * valid, so we can do this even if prev is not writable.) 5034 */ 5035 5036 /* if we'd make prev a runt, just move all of its data. */ 5037 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5038 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5039 5040 if ((prev->m_len - shortfall) < 8) 5041 shortfall = prev->m_len; 5042 5043 #ifdef notyet /* just do the safe slow thing for now */ 5044 if (!M_READONLY(m)) { 5045 if (M_LEADINGSPACE(m) < shorfall) { 5046 void *m_dat; 5047 m_dat = (m->m_flags & M_PKTHDR) ? 5048 m->m_pktdat : m->dat; 5049 memmove(m_dat, mtod(m, void*), m->m_len); 5050 m->m_data = m_dat; 5051 } 5052 } else 5053 #endif /* just do the safe slow thing */ 5054 { 5055 struct mbuf * n = NULL; 5056 int newprevlen = prev->m_len - shortfall; 5057 5058 MGET(n, M_NOWAIT, MT_DATA); 5059 if (n == NULL) 5060 return ENOBUFS; 5061 KASSERT(m->m_len + shortfall < MLEN 5062 /*, 5063 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5064 5065 /* first copy the data we're stealing from prev */ 5066 memcpy(n->m_data, prev->m_data + newprevlen, 5067 shortfall); 5068 5069 /* update prev->m_len accordingly */ 5070 prev->m_len -= shortfall; 5071 5072 /* copy data from runt m */ 5073 memcpy(n->m_data + shortfall, m->m_data, 5074 m->m_len); 5075 5076 /* n holds what we stole from prev, plus m */ 5077 n->m_len = shortfall + m->m_len; 5078 5079 /* stitch n into chain and free m */ 5080 n->m_next = m->m_next; 5081 prev->m_next = n; 5082 /* KASSERT(m->m_next == NULL); */ 5083 m->m_next = NULL; 5084 m_free(m); 5085 m = n; /* for continuing loop */ 5086 } 5087 } 5088 } 5089 return 0; 5090 } 5091 5092 /* 5093 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5094 * pointers to descriptors. 5095 */ 5096 static int 5097 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5098 { 5099 struct bge_tx_bd *f = NULL; 5100 uint32_t frag, cur; 5101 uint16_t csum_flags = 0; 5102 uint16_t txbd_tso_flags = 0; 5103 struct txdmamap_pool_entry *dma; 5104 bus_dmamap_t dmamap; 5105 int i = 0; 5106 struct m_tag *mtag; 5107 int use_tso, maxsegsize, error; 5108 5109 cur = frag = *txidx; 5110 5111 if (m_head->m_pkthdr.csum_flags) { 5112 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5113 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5114 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 5115 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5116 } 5117 5118 /* 5119 * If we were asked to do an outboard checksum, and the NIC 5120 * has the bug where it sometimes adds in the Ethernet padding, 5121 * explicitly pad with zeros so the cksum will be correct either way. 5122 * (For now, do this for all chip versions, until newer 5123 * are confirmed to not require the workaround.) 5124 */ 5125 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5126 #ifdef notyet 5127 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5128 #endif 5129 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5130 goto check_dma_bug; 5131 5132 if (bge_cksum_pad(m_head) != 0) 5133 return ENOBUFS; 5134 5135 check_dma_bug: 5136 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5137 goto doit; 5138 5139 /* 5140 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5141 * less than eight bytes. If we encounter a teeny mbuf 5142 * at the end of a chain, we can pad. Otherwise, copy. 5143 */ 5144 if (bge_compact_dma_runt(m_head) != 0) 5145 return ENOBUFS; 5146 5147 doit: 5148 dma = SLIST_FIRST(&sc->txdma_list); 5149 if (dma == NULL) 5150 return ENOBUFS; 5151 dmamap = dma->dmamap; 5152 5153 /* 5154 * Set up any necessary TSO state before we start packing... 5155 */ 5156 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5157 if (!use_tso) { 5158 maxsegsize = 0; 5159 } else { /* TSO setup */ 5160 unsigned mss; 5161 struct ether_header *eh; 5162 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5163 struct mbuf * m0 = m_head; 5164 struct ip *ip; 5165 struct tcphdr *th; 5166 int iphl, hlen; 5167 5168 /* 5169 * XXX It would be nice if the mbuf pkthdr had offset 5170 * fields for the protocol headers. 5171 */ 5172 5173 eh = mtod(m0, struct ether_header *); 5174 switch (htons(eh->ether_type)) { 5175 case ETHERTYPE_IP: 5176 offset = ETHER_HDR_LEN; 5177 break; 5178 5179 case ETHERTYPE_VLAN: 5180 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5181 break; 5182 5183 default: 5184 /* 5185 * Don't support this protocol or encapsulation. 5186 */ 5187 return ENOBUFS; 5188 } 5189 5190 /* 5191 * TCP/IP headers are in the first mbuf; we can do 5192 * this the easy way. 5193 */ 5194 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5195 hlen = iphl + offset; 5196 if (__predict_false(m0->m_len < 5197 (hlen + sizeof(struct tcphdr)))) { 5198 5199 aprint_debug_dev(sc->bge_dev, 5200 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5201 "not handled yet\n", 5202 m0->m_len, hlen+ sizeof(struct tcphdr)); 5203 #ifdef NOTYET 5204 /* 5205 * XXX jonathan (at) NetBSD.org: untested. 5206 * how to force this branch to be taken? 5207 */ 5208 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5209 5210 m_copydata(m0, offset, sizeof(ip), &ip); 5211 m_copydata(m0, hlen, sizeof(th), &th); 5212 5213 ip.ip_len = 0; 5214 5215 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5216 sizeof(ip.ip_len), &ip.ip_len); 5217 5218 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5219 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5220 5221 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5222 sizeof(th.th_sum), &th.th_sum); 5223 5224 hlen += th.th_off << 2; 5225 iptcp_opt_words = hlen; 5226 #else 5227 /* 5228 * if_wm "hard" case not yet supported, can we not 5229 * mandate it out of existence? 5230 */ 5231 (void) ip; (void)th; (void) ip_tcp_hlen; 5232 5233 return ENOBUFS; 5234 #endif 5235 } else { 5236 ip = (struct ip *) (mtod(m0, char *) + offset); 5237 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5238 ip_tcp_hlen = iphl + (th->th_off << 2); 5239 5240 /* Total IP/TCP options, in 32-bit words */ 5241 iptcp_opt_words = (ip_tcp_hlen 5242 - sizeof(struct tcphdr) 5243 - sizeof(struct ip)) >> 2; 5244 } 5245 if (BGE_IS_575X_PLUS(sc)) { 5246 th->th_sum = 0; 5247 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5248 } else { 5249 /* 5250 * XXX jonathan (at) NetBSD.org: 5705 untested. 5251 * Requires TSO firmware patch for 5701/5703/5704. 5252 */ 5253 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5254 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5255 } 5256 5257 mss = m_head->m_pkthdr.segsz; 5258 txbd_tso_flags |= 5259 BGE_TXBDFLAG_CPU_PRE_DMA | 5260 BGE_TXBDFLAG_CPU_POST_DMA; 5261 5262 /* 5263 * Our NIC TSO-assist assumes TSO has standard, optionless 5264 * IPv4 and TCP headers, which total 40 bytes. By default, 5265 * the NIC copies 40 bytes of IP/TCP header from the 5266 * supplied header into the IP/TCP header portion of 5267 * each post-TSO-segment. If the supplied packet has IP or 5268 * TCP options, we need to tell the NIC to copy those extra 5269 * bytes into each post-TSO header, in addition to the normal 5270 * 40-byte IP/TCP header (and to leave space accordingly). 5271 * Unfortunately, the driver encoding of option length 5272 * varies across different ASIC families. 5273 */ 5274 tcp_seg_flags = 0; 5275 if (iptcp_opt_words) { 5276 if (BGE_IS_5705_PLUS(sc)) { 5277 tcp_seg_flags = 5278 iptcp_opt_words << 11; 5279 } else { 5280 txbd_tso_flags |= 5281 iptcp_opt_words << 12; 5282 } 5283 } 5284 maxsegsize = mss | tcp_seg_flags; 5285 ip->ip_len = htons(mss + ip_tcp_hlen); 5286 5287 } /* TSO setup */ 5288 5289 /* 5290 * Start packing the mbufs in this chain into 5291 * the fragment pointers. Stop when we run out 5292 * of fragments or hit the end of the mbuf chain. 5293 */ 5294 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5295 BUS_DMA_NOWAIT); 5296 if (error) 5297 return ENOBUFS; 5298 /* 5299 * Sanity check: avoid coming within 16 descriptors 5300 * of the end of the ring. 5301 */ 5302 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5303 BGE_TSO_PRINTF(("%s: " 5304 " dmamap_load_mbuf too close to ring wrap\n", 5305 device_xname(sc->bge_dev))); 5306 goto fail_unload; 5307 } 5308 5309 mtag = sc->ethercom.ec_nvlans ? 5310 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 5311 5312 5313 /* Iterate over dmap-map fragments. */ 5314 for (i = 0; i < dmamap->dm_nsegs; i++) { 5315 f = &sc->bge_rdata->bge_tx_ring[frag]; 5316 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5317 break; 5318 5319 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5320 f->bge_len = dmamap->dm_segs[i].ds_len; 5321 5322 /* 5323 * For 5751 and follow-ons, for TSO we must turn 5324 * off checksum-assist flag in the tx-descr, and 5325 * supply the ASIC-revision-specific encoding 5326 * of TSO flags and segsize. 5327 */ 5328 if (use_tso) { 5329 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5330 f->bge_rsvd = maxsegsize; 5331 f->bge_flags = csum_flags | txbd_tso_flags; 5332 } else { 5333 f->bge_rsvd = 0; 5334 f->bge_flags = 5335 (csum_flags | txbd_tso_flags) & 0x0fff; 5336 } 5337 } else { 5338 f->bge_rsvd = 0; 5339 f->bge_flags = csum_flags; 5340 } 5341 5342 if (mtag != NULL) { 5343 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5344 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 5345 } else { 5346 f->bge_vlan_tag = 0; 5347 } 5348 cur = frag; 5349 BGE_INC(frag, BGE_TX_RING_CNT); 5350 } 5351 5352 if (i < dmamap->dm_nsegs) { 5353 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5354 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5355 goto fail_unload; 5356 } 5357 5358 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5359 BUS_DMASYNC_PREWRITE); 5360 5361 if (frag == sc->bge_tx_saved_considx) { 5362 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5363 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5364 5365 goto fail_unload; 5366 } 5367 5368 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5369 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5370 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5371 sc->txdma[cur] = dma; 5372 sc->bge_txcnt += dmamap->dm_nsegs; 5373 5374 *txidx = frag; 5375 5376 return 0; 5377 5378 fail_unload: 5379 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5380 5381 return ENOBUFS; 5382 } 5383 5384 /* 5385 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5386 * to the mbuf data regions directly in the transmit descriptors. 5387 */ 5388 static void 5389 bge_start(struct ifnet *ifp) 5390 { 5391 struct bge_softc *sc; 5392 struct mbuf *m_head = NULL; 5393 uint32_t prodidx; 5394 int pkts = 0; 5395 5396 sc = ifp->if_softc; 5397 5398 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5399 return; 5400 5401 prodidx = sc->bge_tx_prodidx; 5402 5403 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5404 IFQ_POLL(&ifp->if_snd, m_head); 5405 if (m_head == NULL) 5406 break; 5407 5408 #if 0 5409 /* 5410 * XXX 5411 * safety overkill. If this is a fragmented packet chain 5412 * with delayed TCP/UDP checksums, then only encapsulate 5413 * it if we have enough descriptors to handle the entire 5414 * chain at once. 5415 * (paranoia -- may not actually be needed) 5416 */ 5417 if (m_head->m_flags & M_FIRSTFRAG && 5418 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5419 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5420 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5421 ifp->if_flags |= IFF_OACTIVE; 5422 break; 5423 } 5424 } 5425 #endif 5426 5427 /* 5428 * Pack the data into the transmit ring. If we 5429 * don't have room, set the OACTIVE flag and wait 5430 * for the NIC to drain the ring. 5431 */ 5432 if (bge_encap(sc, m_head, &prodidx)) { 5433 ifp->if_flags |= IFF_OACTIVE; 5434 break; 5435 } 5436 5437 /* now we are committed to transmit the packet */ 5438 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5439 pkts++; 5440 5441 /* 5442 * If there's a BPF listener, bounce a copy of this frame 5443 * to him. 5444 */ 5445 bpf_mtap(ifp, m_head); 5446 } 5447 if (pkts == 0) 5448 return; 5449 5450 /* Transmit */ 5451 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5452 /* 5700 b2 errata */ 5453 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5454 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5455 5456 sc->bge_tx_prodidx = prodidx; 5457 5458 /* 5459 * Set a timeout in case the chip goes out to lunch. 5460 */ 5461 ifp->if_timer = 5; 5462 } 5463 5464 static int 5465 bge_init(struct ifnet *ifp) 5466 { 5467 struct bge_softc *sc = ifp->if_softc; 5468 const uint16_t *m; 5469 uint32_t mode, reg; 5470 int s, error = 0; 5471 5472 s = splnet(); 5473 5474 ifp = &sc->ethercom.ec_if; 5475 5476 /* Cancel pending I/O and flush buffers. */ 5477 bge_stop(ifp, 0); 5478 5479 bge_stop_fw(sc); 5480 bge_sig_pre_reset(sc, BGE_RESET_START); 5481 bge_reset(sc); 5482 bge_sig_legacy(sc, BGE_RESET_START); 5483 5484 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5485 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5486 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5487 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5488 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5489 5490 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5491 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5492 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5493 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5494 5495 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5496 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5497 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5498 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5499 5500 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5501 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5502 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5503 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5504 } 5505 5506 bge_sig_post_reset(sc, BGE_RESET_START); 5507 5508 bge_chipinit(sc); 5509 5510 /* 5511 * Init the various state machines, ring 5512 * control blocks and firmware. 5513 */ 5514 error = bge_blockinit(sc); 5515 if (error != 0) { 5516 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5517 error); 5518 splx(s); 5519 return error; 5520 } 5521 5522 ifp = &sc->ethercom.ec_if; 5523 5524 /* 5718 step 25, 57XX step 54 */ 5525 /* Specify MTU. */ 5526 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5527 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5528 5529 /* 5718 step 23 */ 5530 /* Load our MAC address. */ 5531 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5532 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5533 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5534 5535 /* Enable or disable promiscuous mode as needed. */ 5536 if (ifp->if_flags & IFF_PROMISC) 5537 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5538 else 5539 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5540 5541 /* Program multicast filter. */ 5542 bge_setmulti(sc); 5543 5544 /* Init RX ring. */ 5545 bge_init_rx_ring_std(sc); 5546 5547 /* 5548 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5549 * memory to insure that the chip has in fact read the first 5550 * entry of the ring. 5551 */ 5552 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5553 uint32_t v, i; 5554 for (i = 0; i < 10; i++) { 5555 DELAY(20); 5556 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5557 if (v == (MCLBYTES - ETHER_ALIGN)) 5558 break; 5559 } 5560 if (i == 10) 5561 aprint_error_dev(sc->bge_dev, 5562 "5705 A0 chip failed to load RX ring\n"); 5563 } 5564 5565 /* Init jumbo RX ring. */ 5566 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5567 bge_init_rx_ring_jumbo(sc); 5568 5569 /* Init our RX return ring index */ 5570 sc->bge_rx_saved_considx = 0; 5571 5572 /* Init TX ring. */ 5573 bge_init_tx_ring(sc); 5574 5575 /* 5718 step 63, 57XX step 94 */ 5576 /* Enable TX MAC state machine lockup fix. */ 5577 mode = CSR_READ_4(sc, BGE_TX_MODE); 5578 if (BGE_IS_5755_PLUS(sc) || 5579 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5580 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5581 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5582 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5583 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5584 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5585 } 5586 5587 /* Turn on transmitter */ 5588 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5589 /* 5718 step 64 */ 5590 DELAY(100); 5591 5592 /* 5718 step 65, 57XX step 95 */ 5593 /* Turn on receiver */ 5594 mode = CSR_READ_4(sc, BGE_RX_MODE); 5595 if (BGE_IS_5755_PLUS(sc)) 5596 mode |= BGE_RXMODE_IPV6_ENABLE; 5597 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5598 /* 5718 step 66 */ 5599 DELAY(10); 5600 5601 /* 5718 step 12, 57XX step 37 */ 5602 /* 5603 * XXX Doucments of 5718 series and 577xx say the recommended value 5604 * is 1, but tg3 set 1 only on 57765 series. 5605 */ 5606 if (BGE_IS_57765_PLUS(sc)) 5607 reg = 1; 5608 else 5609 reg = 2; 5610 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5611 5612 /* Tell firmware we're alive. */ 5613 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5614 5615 /* Enable host interrupts. */ 5616 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5617 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5618 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5619 5620 if ((error = bge_ifmedia_upd(ifp)) != 0) 5621 goto out; 5622 5623 ifp->if_flags |= IFF_RUNNING; 5624 ifp->if_flags &= ~IFF_OACTIVE; 5625 5626 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5627 5628 out: 5629 sc->bge_if_flags = ifp->if_flags; 5630 splx(s); 5631 5632 return error; 5633 } 5634 5635 /* 5636 * Set media options. 5637 */ 5638 static int 5639 bge_ifmedia_upd(struct ifnet *ifp) 5640 { 5641 struct bge_softc *sc = ifp->if_softc; 5642 struct mii_data *mii = &sc->bge_mii; 5643 struct ifmedia *ifm = &sc->bge_ifmedia; 5644 int rc; 5645 5646 /* If this is a 1000baseX NIC, enable the TBI port. */ 5647 if (sc->bge_flags & BGEF_FIBER_TBI) { 5648 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5649 return EINVAL; 5650 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5651 case IFM_AUTO: 5652 /* 5653 * The BCM5704 ASIC appears to have a special 5654 * mechanism for programming the autoneg 5655 * advertisement registers in TBI mode. 5656 */ 5657 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5658 uint32_t sgdig; 5659 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5660 if (sgdig & BGE_SGDIGSTS_DONE) { 5661 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5662 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5663 sgdig |= BGE_SGDIGCFG_AUTO | 5664 BGE_SGDIGCFG_PAUSE_CAP | 5665 BGE_SGDIGCFG_ASYM_PAUSE; 5666 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5667 sgdig | BGE_SGDIGCFG_SEND); 5668 DELAY(5); 5669 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5670 sgdig); 5671 } 5672 } 5673 break; 5674 case IFM_1000_SX: 5675 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5676 BGE_CLRBIT(sc, BGE_MAC_MODE, 5677 BGE_MACMODE_HALF_DUPLEX); 5678 } else { 5679 BGE_SETBIT(sc, BGE_MAC_MODE, 5680 BGE_MACMODE_HALF_DUPLEX); 5681 } 5682 DELAY(40); 5683 break; 5684 default: 5685 return EINVAL; 5686 } 5687 /* XXX 802.3x flow control for 1000BASE-SX */ 5688 return 0; 5689 } 5690 5691 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5692 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5693 uint32_t reg; 5694 5695 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5696 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5697 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5698 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5699 } 5700 } 5701 5702 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5703 if ((rc = mii_mediachg(mii)) == ENXIO) 5704 return 0; 5705 5706 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5707 uint32_t reg; 5708 5709 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5710 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5711 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5712 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5713 delay(40); 5714 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5715 } 5716 } 5717 5718 /* 5719 * Force an interrupt so that we will call bge_link_upd 5720 * if needed and clear any pending link state attention. 5721 * Without this we are not getting any further interrupts 5722 * for link state changes and thus will not UP the link and 5723 * not be able to send in bge_start. The only way to get 5724 * things working was to receive a packet and get a RX intr. 5725 */ 5726 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5727 sc->bge_flags & BGEF_IS_5788) 5728 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5729 else 5730 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5731 5732 return rc; 5733 } 5734 5735 /* 5736 * Report current media status. 5737 */ 5738 static void 5739 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5740 { 5741 struct bge_softc *sc = ifp->if_softc; 5742 struct mii_data *mii = &sc->bge_mii; 5743 5744 if (sc->bge_flags & BGEF_FIBER_TBI) { 5745 ifmr->ifm_status = IFM_AVALID; 5746 ifmr->ifm_active = IFM_ETHER; 5747 if (CSR_READ_4(sc, BGE_MAC_STS) & 5748 BGE_MACSTAT_TBI_PCS_SYNCHED) 5749 ifmr->ifm_status |= IFM_ACTIVE; 5750 ifmr->ifm_active |= IFM_1000_SX; 5751 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5752 ifmr->ifm_active |= IFM_HDX; 5753 else 5754 ifmr->ifm_active |= IFM_FDX; 5755 return; 5756 } 5757 5758 mii_pollstat(mii); 5759 ifmr->ifm_status = mii->mii_media_status; 5760 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5761 sc->bge_flowflags; 5762 } 5763 5764 static int 5765 bge_ifflags_cb(struct ethercom *ec) 5766 { 5767 struct ifnet *ifp = &ec->ec_if; 5768 struct bge_softc *sc = ifp->if_softc; 5769 int change = ifp->if_flags ^ sc->bge_if_flags; 5770 5771 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5772 return ENETRESET; 5773 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5774 return 0; 5775 5776 if ((ifp->if_flags & IFF_PROMISC) == 0) 5777 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5778 else 5779 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5780 5781 bge_setmulti(sc); 5782 5783 sc->bge_if_flags = ifp->if_flags; 5784 return 0; 5785 } 5786 5787 static int 5788 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5789 { 5790 struct bge_softc *sc = ifp->if_softc; 5791 struct ifreq *ifr = (struct ifreq *) data; 5792 int s, error = 0; 5793 struct mii_data *mii; 5794 5795 s = splnet(); 5796 5797 switch (command) { 5798 case SIOCSIFMEDIA: 5799 /* XXX Flow control is not supported for 1000BASE-SX */ 5800 if (sc->bge_flags & BGEF_FIBER_TBI) { 5801 ifr->ifr_media &= ~IFM_ETH_FMASK; 5802 sc->bge_flowflags = 0; 5803 } 5804 5805 /* Flow control requires full-duplex mode. */ 5806 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5807 (ifr->ifr_media & IFM_FDX) == 0) { 5808 ifr->ifr_media &= ~IFM_ETH_FMASK; 5809 } 5810 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5811 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5812 /* We can do both TXPAUSE and RXPAUSE. */ 5813 ifr->ifr_media |= 5814 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5815 } 5816 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5817 } 5818 /* FALLTHROUGH */ 5819 case SIOCGIFMEDIA: 5820 if (sc->bge_flags & BGEF_FIBER_TBI) { 5821 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5822 command); 5823 } else { 5824 mii = &sc->bge_mii; 5825 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5826 command); 5827 } 5828 break; 5829 default: 5830 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5831 break; 5832 5833 error = 0; 5834 5835 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5836 ; 5837 else if (ifp->if_flags & IFF_RUNNING) 5838 bge_setmulti(sc); 5839 break; 5840 } 5841 5842 splx(s); 5843 5844 return error; 5845 } 5846 5847 static void 5848 bge_watchdog(struct ifnet *ifp) 5849 { 5850 struct bge_softc *sc; 5851 5852 sc = ifp->if_softc; 5853 5854 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5855 5856 ifp->if_flags &= ~IFF_RUNNING; 5857 bge_init(ifp); 5858 5859 ifp->if_oerrors++; 5860 } 5861 5862 static void 5863 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5864 { 5865 int i; 5866 5867 BGE_CLRBIT_FLUSH(sc, reg, bit); 5868 5869 for (i = 0; i < 1000; i++) { 5870 delay(100); 5871 if ((CSR_READ_4(sc, reg) & bit) == 0) 5872 return; 5873 } 5874 5875 /* 5876 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5877 * on some environment (and once after boot?) 5878 */ 5879 if (reg != BGE_SRS_MODE) 5880 aprint_error_dev(sc->bge_dev, 5881 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5882 (u_long)reg, bit); 5883 } 5884 5885 /* 5886 * Stop the adapter and free any mbufs allocated to the 5887 * RX and TX lists. 5888 */ 5889 static void 5890 bge_stop(struct ifnet *ifp, int disable) 5891 { 5892 struct bge_softc *sc = ifp->if_softc; 5893 5894 if (disable) { 5895 sc->bge_detaching = 1; 5896 callout_halt(&sc->bge_timeout, NULL); 5897 } else 5898 callout_stop(&sc->bge_timeout); 5899 5900 /* Disable host interrupts. */ 5901 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5902 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5903 5904 /* 5905 * Tell firmware we're shutting down. 5906 */ 5907 bge_stop_fw(sc); 5908 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5909 5910 /* 5911 * Disable all of the receiver blocks. 5912 */ 5913 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5914 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5915 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5916 if (BGE_IS_5700_FAMILY(sc)) 5917 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5918 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5919 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5920 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5921 5922 /* 5923 * Disable all of the transmit blocks. 5924 */ 5925 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5926 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5927 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5928 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5929 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5930 if (BGE_IS_5700_FAMILY(sc)) 5931 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5932 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5933 5934 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5935 delay(40); 5936 5937 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5938 5939 /* 5940 * Shut down all of the memory managers and related 5941 * state machines. 5942 */ 5943 /* 5718 step 5a,5b */ 5944 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5945 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5946 if (BGE_IS_5700_FAMILY(sc)) 5947 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5948 5949 /* 5718 step 5c,5d */ 5950 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5951 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5952 5953 if (BGE_IS_5700_FAMILY(sc)) { 5954 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5955 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5956 } 5957 5958 bge_reset(sc); 5959 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5960 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5961 5962 /* 5963 * Keep the ASF firmware running if up. 5964 */ 5965 if (sc->bge_asf_mode & ASF_STACKUP) 5966 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5967 else 5968 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5969 5970 /* Free the RX lists. */ 5971 bge_free_rx_ring_std(sc); 5972 5973 /* Free jumbo RX list. */ 5974 if (BGE_IS_JUMBO_CAPABLE(sc)) 5975 bge_free_rx_ring_jumbo(sc); 5976 5977 /* Free TX buffers. */ 5978 bge_free_tx_ring(sc); 5979 5980 /* 5981 * Isolate/power down the PHY. 5982 */ 5983 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 5984 mii_down(&sc->bge_mii); 5985 5986 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5987 5988 /* Clear MAC's link state (PHY may still have link UP). */ 5989 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5990 5991 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5992 } 5993 5994 static void 5995 bge_link_upd(struct bge_softc *sc) 5996 { 5997 struct ifnet *ifp = &sc->ethercom.ec_if; 5998 struct mii_data *mii = &sc->bge_mii; 5999 uint32_t status; 6000 int link; 6001 6002 /* Clear 'pending link event' flag */ 6003 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6004 6005 /* 6006 * Process link state changes. 6007 * Grrr. The link status word in the status block does 6008 * not work correctly on the BCM5700 rev AX and BX chips, 6009 * according to all available information. Hence, we have 6010 * to enable MII interrupts in order to properly obtain 6011 * async link changes. Unfortunately, this also means that 6012 * we have to read the MAC status register to detect link 6013 * changes, thereby adding an additional register access to 6014 * the interrupt handler. 6015 */ 6016 6017 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6018 status = CSR_READ_4(sc, BGE_MAC_STS); 6019 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6020 mii_pollstat(mii); 6021 6022 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6023 mii->mii_media_status & IFM_ACTIVE && 6024 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6025 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6026 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6027 (!(mii->mii_media_status & IFM_ACTIVE) || 6028 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6029 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6030 6031 /* Clear the interrupt */ 6032 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6033 BGE_EVTENB_MI_INTERRUPT); 6034 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6035 BRGPHY_MII_ISR); 6036 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6037 BRGPHY_MII_IMR, BRGPHY_INTRS); 6038 } 6039 return; 6040 } 6041 6042 if (sc->bge_flags & BGEF_FIBER_TBI) { 6043 status = CSR_READ_4(sc, BGE_MAC_STS); 6044 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6045 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6046 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6047 if (BGE_ASICREV(sc->bge_chipid) 6048 == BGE_ASICREV_BCM5704) { 6049 BGE_CLRBIT(sc, BGE_MAC_MODE, 6050 BGE_MACMODE_TBI_SEND_CFGS); 6051 DELAY(40); 6052 } 6053 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6054 if_link_state_change(ifp, LINK_STATE_UP); 6055 } 6056 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6057 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6058 if_link_state_change(ifp, LINK_STATE_DOWN); 6059 } 6060 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6061 /* 6062 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6063 * bit in status word always set. Workaround this bug by 6064 * reading PHY link status directly. 6065 */ 6066 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6067 BGE_STS_LINK : 0; 6068 6069 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6070 mii_pollstat(mii); 6071 6072 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6073 mii->mii_media_status & IFM_ACTIVE && 6074 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6075 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6076 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6077 (!(mii->mii_media_status & IFM_ACTIVE) || 6078 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6079 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6080 } 6081 } else { 6082 /* 6083 * For controllers that call mii_tick, we have to poll 6084 * link status. 6085 */ 6086 mii_pollstat(mii); 6087 } 6088 6089 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6090 uint32_t reg, scale; 6091 6092 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6093 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6094 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6095 scale = 65; 6096 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6097 scale = 6; 6098 else 6099 scale = 12; 6100 6101 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6102 ~BGE_MISCCFG_TIMER_PRESCALER; 6103 reg |= scale << 1; 6104 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6105 } 6106 /* Clear the attention */ 6107 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6108 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6109 BGE_MACSTAT_LINK_CHANGED); 6110 } 6111 6112 static int 6113 bge_sysctl_verify(SYSCTLFN_ARGS) 6114 { 6115 int error, t; 6116 struct sysctlnode node; 6117 6118 node = *rnode; 6119 t = *(int*)rnode->sysctl_data; 6120 node.sysctl_data = &t; 6121 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6122 if (error || newp == NULL) 6123 return error; 6124 6125 #if 0 6126 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6127 node.sysctl_num, rnode->sysctl_num)); 6128 #endif 6129 6130 if (node.sysctl_num == bge_rxthresh_nodenum) { 6131 if (t < 0 || t >= NBGE_RX_THRESH) 6132 return EINVAL; 6133 bge_update_all_threshes(t); 6134 } else 6135 return EINVAL; 6136 6137 *(int*)rnode->sysctl_data = t; 6138 6139 return 0; 6140 } 6141 6142 /* 6143 * Set up sysctl(3) MIB, hw.bge.*. 6144 */ 6145 static void 6146 bge_sysctl_init(struct bge_softc *sc) 6147 { 6148 int rc, bge_root_num; 6149 const struct sysctlnode *node; 6150 6151 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6152 0, CTLTYPE_NODE, "bge", 6153 SYSCTL_DESCR("BGE interface controls"), 6154 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6155 goto out; 6156 } 6157 6158 bge_root_num = node->sysctl_num; 6159 6160 /* BGE Rx interrupt mitigation level */ 6161 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6162 CTLFLAG_READWRITE, 6163 CTLTYPE_INT, "rx_lvl", 6164 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6165 bge_sysctl_verify, 0, 6166 &bge_rx_thresh_lvl, 6167 0, CTL_HW, bge_root_num, CTL_CREATE, 6168 CTL_EOL)) != 0) { 6169 goto out; 6170 } 6171 6172 bge_rxthresh_nodenum = node->sysctl_num; 6173 6174 return; 6175 6176 out: 6177 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6178 } 6179 6180 #ifdef BGE_DEBUG 6181 void 6182 bge_debug_info(struct bge_softc *sc) 6183 { 6184 6185 printf("Hardware Flags:\n"); 6186 if (BGE_IS_57765_PLUS(sc)) 6187 printf(" - 57765 Plus\n"); 6188 if (BGE_IS_5717_PLUS(sc)) 6189 printf(" - 5717 Plus\n"); 6190 if (BGE_IS_5755_PLUS(sc)) 6191 printf(" - 5755 Plus\n"); 6192 if (BGE_IS_575X_PLUS(sc)) 6193 printf(" - 575X Plus\n"); 6194 if (BGE_IS_5705_PLUS(sc)) 6195 printf(" - 5705 Plus\n"); 6196 if (BGE_IS_5714_FAMILY(sc)) 6197 printf(" - 5714 Family\n"); 6198 if (BGE_IS_5700_FAMILY(sc)) 6199 printf(" - 5700 Family\n"); 6200 if (sc->bge_flags & BGEF_IS_5788) 6201 printf(" - 5788\n"); 6202 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6203 printf(" - Supports Jumbo Frames\n"); 6204 if (sc->bge_flags & BGEF_NO_EEPROM) 6205 printf(" - No EEPROM\n"); 6206 if (sc->bge_flags & BGEF_PCIX) 6207 printf(" - PCI-X Bus\n"); 6208 if (sc->bge_flags & BGEF_PCIE) 6209 printf(" - PCI Express Bus\n"); 6210 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6211 printf(" - RX Alignment Bug\n"); 6212 if (sc->bge_flags & BGEF_APE) 6213 printf(" - APE\n"); 6214 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6215 printf(" - CPMU\n"); 6216 if (sc->bge_flags & BGEF_TSO) 6217 printf(" - TSO\n"); 6218 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6219 printf(" - TAGGED_STATUS\n"); 6220 6221 /* PHY related */ 6222 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6223 printf(" - No 3 LEDs\n"); 6224 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6225 printf(" - CRC bug\n"); 6226 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6227 printf(" - ADC bug\n"); 6228 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6229 printf(" - 5704 A0 bug\n"); 6230 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6231 printf(" - jitter bug\n"); 6232 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6233 printf(" - BER bug\n"); 6234 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6235 printf(" - adjust trim\n"); 6236 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6237 printf(" - no wirespeed\n"); 6238 6239 /* ASF related */ 6240 if (sc->bge_asf_mode & ASF_ENABLE) 6241 printf(" - ASF enable\n"); 6242 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6243 printf(" - ASF new handshake\n"); 6244 if (sc->bge_asf_mode & ASF_STACKUP) 6245 printf(" - ASF stackup\n"); 6246 } 6247 #endif /* BGE_DEBUG */ 6248 6249 static int 6250 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6251 { 6252 prop_dictionary_t dict; 6253 prop_data_t ea; 6254 6255 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6256 return 1; 6257 6258 dict = device_properties(sc->bge_dev); 6259 ea = prop_dictionary_get(dict, "mac-address"); 6260 if (ea != NULL) { 6261 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6262 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6263 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6264 return 0; 6265 } 6266 6267 return 1; 6268 } 6269 6270 static int 6271 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6272 { 6273 uint32_t mac_addr; 6274 6275 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6276 if ((mac_addr >> 16) == 0x484b) { 6277 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6278 ether_addr[1] = (uint8_t)mac_addr; 6279 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6280 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6281 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6282 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6283 ether_addr[5] = (uint8_t)mac_addr; 6284 return 0; 6285 } 6286 return 1; 6287 } 6288 6289 static int 6290 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6291 { 6292 int mac_offset = BGE_EE_MAC_OFFSET; 6293 6294 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6295 mac_offset = BGE_EE_MAC_OFFSET_5906; 6296 6297 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6298 ETHER_ADDR_LEN)); 6299 } 6300 6301 static int 6302 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6303 { 6304 6305 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6306 return 1; 6307 6308 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6309 ETHER_ADDR_LEN)); 6310 } 6311 6312 static int 6313 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6314 { 6315 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6316 /* NOTE: Order is critical */ 6317 bge_get_eaddr_fw, 6318 bge_get_eaddr_mem, 6319 bge_get_eaddr_nvram, 6320 bge_get_eaddr_eeprom, 6321 NULL 6322 }; 6323 const bge_eaddr_fcn_t *func; 6324 6325 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6326 if ((*func)(sc, eaddr) == 0) 6327 break; 6328 } 6329 return (*func == NULL ? ENXIO : 0); 6330 } 6331
Indexes created Fri Sep 26 08:10:20 GMT 2025