if_bge.c revision 1.313
1 /* $NetBSD: if_bge.c,v 1.313 2017/11/22 02:35:54 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.313 2017/11/22 02:35:54 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_can_use_msi(struct bge_softc *); 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static int bge_detach(device_t, int); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int); 254 static void bge_miibus_writereg(device_t, int, int, int); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5750, 440 "Broadcom BCM5750 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5751, 444 "Broadcom BCM5751 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5751F, 448 "Broadcom BCM5751F Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751M, 452 "Broadcom BCM5751M Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5752, 456 "Broadcom BCM5752 Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5752M, 460 "Broadcom BCM5752M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5753, 464 "Broadcom BCM5753 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5753F, 468 "Broadcom BCM5753F Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753M, 472 "Broadcom BCM5753M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5754, 476 "Broadcom BCM5754 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5754M, 480 "Broadcom BCM5754M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5755, 484 "Broadcom BCM5755 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5755M, 488 "Broadcom BCM5755M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5756, 492 "Broadcom BCM5756 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5761, 496 "Broadcom BCM5761 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5761E, 500 "Broadcom BCM5761E Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761S, 504 "Broadcom BCM5761S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761SE, 508 "Broadcom BCM5761SE Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5764, 512 "Broadcom BCM5764 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5780, 516 "Broadcom BCM5780 Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5780S, 520 "Broadcom BCM5780S Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5781, 524 "Broadcom BCM5781 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5782, 528 "Broadcom BCM5782 Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5784M, 532 "BCM5784M NetLink 1000baseT Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5785F, 536 "BCM5785F NetLink 10/100 Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5785G, 540 "BCM5785G NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5786, 544 "Broadcom BCM5786 Gigabit Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5787, 548 "Broadcom BCM5787 Gigabit Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5787F, 552 "Broadcom BCM5787F 10/100 Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787M, 556 "Broadcom BCM5787M Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5788, 560 "Broadcom BCM5788 Gigabit Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5789, 564 "Broadcom BCM5789 Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5901, 568 "Broadcom BCM5901 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5901A2, 572 "Broadcom BCM5901A2 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5903M, 576 "Broadcom BCM5903M Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5906, 580 "Broadcom BCM5906 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5906M, 584 "Broadcom BCM5906M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57760, 588 "Broadcom BCM57760 Gigabit Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57761, 592 "Broadcom BCM57761 Gigabit Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57762, 596 "Broadcom BCM57762 Gigabit Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57765, 600 "Broadcom BCM57765 Gigabit Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57766, 604 "Broadcom BCM57766 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57780, 608 "Broadcom BCM57780 Gigabit Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57781, 612 "Broadcom BCM57781 Gigabit Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57782, 616 "Broadcom BCM57782 Gigabit Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57785, 620 "Broadcom BCM57785 Gigabit Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57786, 624 "Broadcom BCM57786 Gigabit Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57788, 628 "Broadcom BCM57788 Gigabit Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57790, 632 "Broadcom BCM57790 Gigabit Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57791, 636 "Broadcom BCM57791 Gigabit Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57795, 640 "Broadcom BCM57795 Gigabit Ethernet", 641 }, 642 { PCI_VENDOR_SCHNEIDERKOCH, 643 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 644 "SysKonnect SK-9Dx1 Gigabit Ethernet", 645 }, 646 { PCI_VENDOR_3COM, 647 PCI_PRODUCT_3COM_3C996, 648 "3Com 3c996 Gigabit Ethernet", 649 }, 650 { PCI_VENDOR_FUJITSU4, 651 PCI_PRODUCT_FUJITSU4_PW008GE4, 652 "Fujitsu PW008GE4 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_FUJITSU4, 655 PCI_PRODUCT_FUJITSU4_PW008GE5, 656 "Fujitsu PW008GE5 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 660 "Fujitsu Primepower 250/450 Gigabit Ethernet", 661 }, 662 { 0, 663 0, 664 NULL }, 665 }; 666 667 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 668 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 669 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 670 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 671 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 672 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 673 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 674 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 675 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 676 677 static const struct bge_revision { 678 uint32_t br_chipid; 679 const char *br_name; 680 } bge_revisions[] = { 681 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 682 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 683 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 684 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 685 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 686 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 687 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 688 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 689 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 690 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 691 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 692 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 693 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 694 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 695 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 696 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 697 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 698 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 699 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 700 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 701 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 702 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 703 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 704 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 705 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 706 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 707 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 708 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 709 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 710 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 711 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 712 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 713 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 714 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 715 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 716 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 717 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 718 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 719 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 720 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 721 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 722 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 723 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 724 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 725 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 726 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 727 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 728 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 729 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 730 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 731 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 732 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 733 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 734 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 735 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 736 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 737 /* 5754 and 5787 share the same ASIC ID */ 738 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 739 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 740 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 741 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 742 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 743 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 744 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 745 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 746 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 747 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 748 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 749 750 { 0, NULL } 751 }; 752 753 /* 754 * Some defaults for major revisions, so that newer steppings 755 * that we don't know about have a shot at working. 756 */ 757 static const struct bge_revision bge_majorrevs[] = { 758 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 759 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 760 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 761 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 762 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 763 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 764 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 765 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 766 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 767 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 768 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 769 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 770 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 771 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 772 /* 5754 and 5787 share the same ASIC ID */ 773 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 774 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 775 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 776 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 777 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 778 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 779 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 780 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 781 782 { 0, NULL } 783 }; 784 785 static int bge_allow_asf = 1; 786 787 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 788 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 789 790 static uint32_t 791 bge_readmem_ind(struct bge_softc *sc, int off) 792 { 793 pcireg_t val; 794 795 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 796 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 797 return 0; 798 799 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 800 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 801 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 802 return val; 803 } 804 805 static void 806 bge_writemem_ind(struct bge_softc *sc, int off, int val) 807 { 808 809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 811 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 812 } 813 814 /* 815 * PCI Express only 816 */ 817 static void 818 bge_set_max_readrq(struct bge_softc *sc) 819 { 820 pcireg_t val; 821 822 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 823 + PCIE_DCSR); 824 val &= ~PCIE_DCSR_MAX_READ_REQ; 825 switch (sc->bge_expmrq) { 826 case 2048: 827 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 828 break; 829 case 4096: 830 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 831 break; 832 default: 833 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 834 break; 835 } 836 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 837 + PCIE_DCSR, val); 838 } 839 840 #ifdef notdef 841 static uint32_t 842 bge_readreg_ind(struct bge_softc *sc, int off) 843 { 844 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 845 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 846 } 847 #endif 848 849 static void 850 bge_writereg_ind(struct bge_softc *sc, int off, int val) 851 { 852 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 853 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 854 } 855 856 static void 857 bge_writemem_direct(struct bge_softc *sc, int off, int val) 858 { 859 CSR_WRITE_4(sc, off, val); 860 } 861 862 static void 863 bge_writembx(struct bge_softc *sc, int off, int val) 864 { 865 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 866 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 867 868 CSR_WRITE_4(sc, off, val); 869 } 870 871 static void 872 bge_writembx_flush(struct bge_softc *sc, int off, int val) 873 { 874 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 875 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 876 877 CSR_WRITE_4_FLUSH(sc, off, val); 878 } 879 880 /* 881 * Clear all stale locks and select the lock for this driver instance. 882 */ 883 void 884 bge_ape_lock_init(struct bge_softc *sc) 885 { 886 struct pci_attach_args *pa = &(sc->bge_pa); 887 uint32_t bit, regbase; 888 int i; 889 890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 891 regbase = BGE_APE_LOCK_GRANT; 892 else 893 regbase = BGE_APE_PER_LOCK_GRANT; 894 895 /* Clear any stale locks. */ 896 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 897 switch (i) { 898 case BGE_APE_LOCK_PHY0: 899 case BGE_APE_LOCK_PHY1: 900 case BGE_APE_LOCK_PHY2: 901 case BGE_APE_LOCK_PHY3: 902 bit = BGE_APE_LOCK_GRANT_DRIVER0; 903 break; 904 default: 905 if (pa->pa_function == 0) 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 else 908 bit = (1 << pa->pa_function); 909 } 910 APE_WRITE_4(sc, regbase + 4 * i, bit); 911 } 912 913 /* Select the PHY lock based on the device's function number. */ 914 switch (pa->pa_function) { 915 case 0: 916 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 917 break; 918 case 1: 919 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 920 break; 921 case 2: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 923 break; 924 case 3: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 926 break; 927 default: 928 printf("%s: PHY lock not supported on function\n", 929 device_xname(sc->bge_dev)); 930 break; 931 } 932 } 933 934 /* 935 * Check for APE firmware, set flags, and print version info. 936 */ 937 void 938 bge_ape_read_fw_ver(struct bge_softc *sc) 939 { 940 const char *fwtype; 941 uint32_t apedata, features; 942 943 /* Check for a valid APE signature in shared memory. */ 944 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 945 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 946 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 947 return; 948 } 949 950 /* Check if APE firmware is running. */ 951 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 952 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 953 printf("%s: APE signature found but FW status not ready! " 954 "0x%08x\n", device_xname(sc->bge_dev), apedata); 955 return; 956 } 957 958 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 959 960 /* Fetch the APE firwmare type and version. */ 961 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 962 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 963 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 964 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 965 fwtype = "NCSI"; 966 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 967 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 968 fwtype = "DASH"; 969 } else 970 fwtype = "UNKN"; 971 972 /* Print the APE firmware version. */ 973 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 974 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 975 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 976 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 977 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 978 } 979 980 int 981 bge_ape_lock(struct bge_softc *sc, int locknum) 982 { 983 struct pci_attach_args *pa = &(sc->bge_pa); 984 uint32_t bit, gnt, req, status; 985 int i, off; 986 987 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 988 return (0); 989 990 /* Lock request/grant registers have different bases. */ 991 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 992 req = BGE_APE_LOCK_REQ; 993 gnt = BGE_APE_LOCK_GRANT; 994 } else { 995 req = BGE_APE_PER_LOCK_REQ; 996 gnt = BGE_APE_PER_LOCK_GRANT; 997 } 998 999 off = 4 * locknum; 1000 1001 switch (locknum) { 1002 case BGE_APE_LOCK_GPIO: 1003 /* Lock required when using GPIO. */ 1004 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1005 return (0); 1006 if (pa->pa_function == 0) 1007 bit = BGE_APE_LOCK_REQ_DRIVER0; 1008 else 1009 bit = (1 << pa->pa_function); 1010 break; 1011 case BGE_APE_LOCK_GRC: 1012 /* Lock required to reset the device. */ 1013 if (pa->pa_function == 0) 1014 bit = BGE_APE_LOCK_REQ_DRIVER0; 1015 else 1016 bit = (1 << pa->pa_function); 1017 break; 1018 case BGE_APE_LOCK_MEM: 1019 /* Lock required when accessing certain APE memory. */ 1020 if (pa->pa_function == 0) 1021 bit = BGE_APE_LOCK_REQ_DRIVER0; 1022 else 1023 bit = (1 << pa->pa_function); 1024 break; 1025 case BGE_APE_LOCK_PHY0: 1026 case BGE_APE_LOCK_PHY1: 1027 case BGE_APE_LOCK_PHY2: 1028 case BGE_APE_LOCK_PHY3: 1029 /* Lock required when accessing PHYs. */ 1030 bit = BGE_APE_LOCK_REQ_DRIVER0; 1031 break; 1032 default: 1033 return (EINVAL); 1034 } 1035 1036 /* Request a lock. */ 1037 APE_WRITE_4_FLUSH(sc, req + off, bit); 1038 1039 /* Wait up to 1 second to acquire lock. */ 1040 for (i = 0; i < 20000; i++) { 1041 status = APE_READ_4(sc, gnt + off); 1042 if (status == bit) 1043 break; 1044 DELAY(50); 1045 } 1046 1047 /* Handle any errors. */ 1048 if (status != bit) { 1049 printf("%s: APE lock %d request failed! " 1050 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1051 device_xname(sc->bge_dev), 1052 locknum, req + off, bit & 0xFFFF, gnt + off, 1053 status & 0xFFFF); 1054 /* Revoke the lock request. */ 1055 APE_WRITE_4(sc, gnt + off, bit); 1056 return (EBUSY); 1057 } 1058 1059 return (0); 1060 } 1061 1062 void 1063 bge_ape_unlock(struct bge_softc *sc, int locknum) 1064 { 1065 struct pci_attach_args *pa = &(sc->bge_pa); 1066 uint32_t bit, gnt; 1067 int off; 1068 1069 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1070 return; 1071 1072 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1073 gnt = BGE_APE_LOCK_GRANT; 1074 else 1075 gnt = BGE_APE_PER_LOCK_GRANT; 1076 1077 off = 4 * locknum; 1078 1079 switch (locknum) { 1080 case BGE_APE_LOCK_GPIO: 1081 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1082 return; 1083 if (pa->pa_function == 0) 1084 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1085 else 1086 bit = (1 << pa->pa_function); 1087 break; 1088 case BGE_APE_LOCK_GRC: 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_MEM: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_PHY0: 1101 case BGE_APE_LOCK_PHY1: 1102 case BGE_APE_LOCK_PHY2: 1103 case BGE_APE_LOCK_PHY3: 1104 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1105 break; 1106 default: 1107 return; 1108 } 1109 1110 /* Write and flush for consecutive bge_ape_lock() */ 1111 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1112 } 1113 1114 /* 1115 * Send an event to the APE firmware. 1116 */ 1117 void 1118 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1119 { 1120 uint32_t apedata; 1121 int i; 1122 1123 /* NCSI does not support APE events. */ 1124 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1125 return; 1126 1127 /* Wait up to 1ms for APE to service previous event. */ 1128 for (i = 10; i > 0; i--) { 1129 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1130 break; 1131 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1132 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1133 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1134 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1135 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1136 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1137 break; 1138 } 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 DELAY(100); 1141 } 1142 if (i == 0) { 1143 printf("%s: APE event 0x%08x send timed out\n", 1144 device_xname(sc->bge_dev), event); 1145 } 1146 } 1147 1148 void 1149 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1150 { 1151 uint32_t apedata, event; 1152 1153 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1154 return; 1155 1156 switch (kind) { 1157 case BGE_RESET_START: 1158 /* If this is the first load, clear the load counter. */ 1159 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1160 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1161 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1162 else { 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1164 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1165 } 1166 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1167 BGE_APE_HOST_SEG_SIG_MAGIC); 1168 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1169 BGE_APE_HOST_SEG_LEN_MAGIC); 1170 1171 /* Add some version info if bge(4) supports it. */ 1172 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1173 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1174 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1175 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1176 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1177 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1178 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1179 BGE_APE_HOST_DRVR_STATE_START); 1180 event = BGE_APE_EVENT_STATUS_STATE_START; 1181 break; 1182 case BGE_RESET_SHUTDOWN: 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1185 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1186 break; 1187 case BGE_RESET_SUSPEND: 1188 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1189 break; 1190 default: 1191 return; 1192 } 1193 1194 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1195 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1196 } 1197 1198 static uint8_t 1199 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1200 { 1201 uint32_t access, byte = 0; 1202 int i; 1203 1204 /* Lock. */ 1205 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1206 for (i = 0; i < 8000; i++) { 1207 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1208 break; 1209 DELAY(20); 1210 } 1211 if (i == 8000) 1212 return 1; 1213 1214 /* Enable access. */ 1215 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1216 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1217 1218 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1219 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1220 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1221 DELAY(10); 1222 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1223 DELAY(10); 1224 break; 1225 } 1226 } 1227 1228 if (i == BGE_TIMEOUT * 10) { 1229 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1230 return 1; 1231 } 1232 1233 /* Get result. */ 1234 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1235 1236 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1237 1238 /* Disable access. */ 1239 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1240 1241 /* Unlock. */ 1242 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1243 1244 return 0; 1245 } 1246 1247 /* 1248 * Read a sequence of bytes from NVRAM. 1249 */ 1250 static int 1251 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1252 { 1253 int error = 0, i; 1254 uint8_t byte = 0; 1255 1256 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1257 return 1; 1258 1259 for (i = 0; i < cnt; i++) { 1260 error = bge_nvram_getbyte(sc, off + i, &byte); 1261 if (error) 1262 break; 1263 *(dest + i) = byte; 1264 } 1265 1266 return (error ? 1 : 0); 1267 } 1268 1269 /* 1270 * Read a byte of data stored in the EEPROM at address 'addr.' The 1271 * BCM570x supports both the traditional bitbang interface and an 1272 * auto access interface for reading the EEPROM. We use the auto 1273 * access method. 1274 */ 1275 static uint8_t 1276 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1277 { 1278 int i; 1279 uint32_t byte = 0; 1280 1281 /* 1282 * Enable use of auto EEPROM access so we can avoid 1283 * having to use the bitbang method. 1284 */ 1285 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1286 1287 /* Reset the EEPROM, load the clock period. */ 1288 CSR_WRITE_4(sc, BGE_EE_ADDR, 1289 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1290 DELAY(20); 1291 1292 /* Issue the read EEPROM command. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1294 1295 /* Wait for completion */ 1296 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1297 DELAY(10); 1298 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1299 break; 1300 } 1301 1302 if (i == BGE_TIMEOUT * 10) { 1303 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1304 return 1; 1305 } 1306 1307 /* Get result. */ 1308 byte = CSR_READ_4(sc, BGE_EE_DATA); 1309 1310 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1311 1312 return 0; 1313 } 1314 1315 /* 1316 * Read a sequence of bytes from the EEPROM. 1317 */ 1318 static int 1319 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1320 { 1321 int error = 0, i; 1322 uint8_t byte = 0; 1323 char *dest = destv; 1324 1325 for (i = 0; i < cnt; i++) { 1326 error = bge_eeprom_getbyte(sc, off + i, &byte); 1327 if (error) 1328 break; 1329 *(dest + i) = byte; 1330 } 1331 1332 return (error ? 1 : 0); 1333 } 1334 1335 static int 1336 bge_miibus_readreg(device_t dev, int phy, int reg) 1337 { 1338 struct bge_softc *sc = device_private(dev); 1339 uint32_t val; 1340 uint32_t autopoll; 1341 int i; 1342 1343 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1344 return 0; 1345 1346 /* Reading with autopolling on may trigger PCI errors */ 1347 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1348 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1349 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1350 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1351 DELAY(80); 1352 } 1353 1354 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1355 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1356 1357 for (i = 0; i < BGE_TIMEOUT; i++) { 1358 delay(10); 1359 val = CSR_READ_4(sc, BGE_MI_COMM); 1360 if (!(val & BGE_MICOMM_BUSY)) { 1361 DELAY(5); 1362 val = CSR_READ_4(sc, BGE_MI_COMM); 1363 break; 1364 } 1365 } 1366 1367 if (i == BGE_TIMEOUT) { 1368 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1369 val = 0; 1370 goto done; 1371 } 1372 1373 done: 1374 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1375 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1376 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1377 DELAY(80); 1378 } 1379 1380 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1381 1382 if (val & BGE_MICOMM_READFAIL) 1383 return 0; 1384 1385 return (val & 0xFFFF); 1386 } 1387 1388 static void 1389 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1390 { 1391 struct bge_softc *sc = device_private(dev); 1392 uint32_t autopoll; 1393 int i; 1394 1395 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1396 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1397 return; 1398 1399 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1400 return; 1401 1402 /* Reading with autopolling on may trigger PCI errors */ 1403 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1404 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1405 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1406 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1407 DELAY(80); 1408 } 1409 1410 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1411 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1412 1413 for (i = 0; i < BGE_TIMEOUT; i++) { 1414 delay(10); 1415 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1416 delay(5); 1417 CSR_READ_4(sc, BGE_MI_COMM); 1418 break; 1419 } 1420 } 1421 1422 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1423 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1424 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1425 delay(80); 1426 } 1427 1428 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1429 1430 if (i == BGE_TIMEOUT) 1431 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1432 } 1433 1434 static void 1435 bge_miibus_statchg(struct ifnet *ifp) 1436 { 1437 struct bge_softc *sc = ifp->if_softc; 1438 struct mii_data *mii = &sc->bge_mii; 1439 uint32_t mac_mode, rx_mode, tx_mode; 1440 1441 /* 1442 * Get flow control negotiation result. 1443 */ 1444 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1445 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1446 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1447 1448 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1449 mii->mii_media_status & IFM_ACTIVE && 1450 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1451 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1452 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1453 (!(mii->mii_media_status & IFM_ACTIVE) || 1454 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1455 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1456 1457 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1458 return; 1459 1460 /* Set the port mode (MII/GMII) to match the link speed. */ 1461 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1462 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1463 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1464 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1465 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1466 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1467 mac_mode |= BGE_PORTMODE_GMII; 1468 else 1469 mac_mode |= BGE_PORTMODE_MII; 1470 1471 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1472 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1473 if ((mii->mii_media_active & IFM_FDX) != 0) { 1474 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1475 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1476 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1477 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1478 } else 1479 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1480 1481 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1482 DELAY(40); 1483 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1484 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1485 } 1486 1487 /* 1488 * Update rx threshold levels to values in a particular slot 1489 * of the interrupt-mitigation table bge_rx_threshes. 1490 */ 1491 static void 1492 bge_set_thresh(struct ifnet *ifp, int lvl) 1493 { 1494 struct bge_softc *sc = ifp->if_softc; 1495 int s; 1496 1497 /* For now, just save the new Rx-intr thresholds and record 1498 * that a threshold update is pending. Updating the hardware 1499 * registers here (even at splhigh()) is observed to 1500 * occasionaly cause glitches where Rx-interrupts are not 1501 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1502 */ 1503 s = splnet(); 1504 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1505 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1506 sc->bge_pending_rxintr_change = 1; 1507 splx(s); 1508 } 1509 1510 1511 /* 1512 * Update Rx thresholds of all bge devices 1513 */ 1514 static void 1515 bge_update_all_threshes(int lvl) 1516 { 1517 struct ifnet *ifp; 1518 const char * const namebuf = "bge"; 1519 int namelen; 1520 int s; 1521 1522 if (lvl < 0) 1523 lvl = 0; 1524 else if (lvl >= NBGE_RX_THRESH) 1525 lvl = NBGE_RX_THRESH - 1; 1526 1527 namelen = strlen(namebuf); 1528 /* 1529 * Now search all the interfaces for this name/number 1530 */ 1531 s = pserialize_read_enter(); 1532 IFNET_READER_FOREACH(ifp) { 1533 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1534 continue; 1535 /* We got a match: update if doing auto-threshold-tuning */ 1536 if (bge_auto_thresh) 1537 bge_set_thresh(ifp, lvl); 1538 } 1539 pserialize_read_exit(s); 1540 } 1541 1542 /* 1543 * Handle events that have triggered interrupts. 1544 */ 1545 static void 1546 bge_handle_events(struct bge_softc *sc) 1547 { 1548 1549 return; 1550 } 1551 1552 /* 1553 * Memory management for jumbo frames. 1554 */ 1555 1556 static int 1557 bge_alloc_jumbo_mem(struct bge_softc *sc) 1558 { 1559 char *ptr, *kva; 1560 bus_dma_segment_t seg; 1561 int i, rseg, state, error; 1562 struct bge_jpool_entry *entry; 1563 1564 state = error = 0; 1565 1566 /* Grab a big chunk o' storage. */ 1567 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1568 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1569 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1570 return ENOBUFS; 1571 } 1572 1573 state = 1; 1574 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1575 BUS_DMA_NOWAIT)) { 1576 aprint_error_dev(sc->bge_dev, 1577 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1578 error = ENOBUFS; 1579 goto out; 1580 } 1581 1582 state = 2; 1583 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1584 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1585 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1586 error = ENOBUFS; 1587 goto out; 1588 } 1589 1590 state = 3; 1591 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1592 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1593 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1594 error = ENOBUFS; 1595 goto out; 1596 } 1597 1598 state = 4; 1599 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1600 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1601 1602 SLIST_INIT(&sc->bge_jfree_listhead); 1603 SLIST_INIT(&sc->bge_jinuse_listhead); 1604 1605 /* 1606 * Now divide it up into 9K pieces and save the addresses 1607 * in an array. 1608 */ 1609 ptr = sc->bge_cdata.bge_jumbo_buf; 1610 for (i = 0; i < BGE_JSLOTS; i++) { 1611 sc->bge_cdata.bge_jslots[i] = ptr; 1612 ptr += BGE_JLEN; 1613 entry = malloc(sizeof(struct bge_jpool_entry), 1614 M_DEVBUF, M_NOWAIT); 1615 if (entry == NULL) { 1616 aprint_error_dev(sc->bge_dev, 1617 "no memory for jumbo buffer queue!\n"); 1618 error = ENOBUFS; 1619 goto out; 1620 } 1621 entry->slot = i; 1622 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1623 entry, jpool_entries); 1624 } 1625 out: 1626 if (error != 0) { 1627 switch (state) { 1628 case 4: 1629 bus_dmamap_unload(sc->bge_dmatag, 1630 sc->bge_cdata.bge_rx_jumbo_map); 1631 case 3: 1632 bus_dmamap_destroy(sc->bge_dmatag, 1633 sc->bge_cdata.bge_rx_jumbo_map); 1634 case 2: 1635 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1636 case 1: 1637 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1638 break; 1639 default: 1640 break; 1641 } 1642 } 1643 1644 return error; 1645 } 1646 1647 /* 1648 * Allocate a jumbo buffer. 1649 */ 1650 static void * 1651 bge_jalloc(struct bge_softc *sc) 1652 { 1653 struct bge_jpool_entry *entry; 1654 1655 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1656 1657 if (entry == NULL) { 1658 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1659 return NULL; 1660 } 1661 1662 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1663 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1664 return (sc->bge_cdata.bge_jslots[entry->slot]); 1665 } 1666 1667 /* 1668 * Release a jumbo buffer. 1669 */ 1670 static void 1671 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1672 { 1673 struct bge_jpool_entry *entry; 1674 struct bge_softc *sc; 1675 int i, s; 1676 1677 /* Extract the softc struct pointer. */ 1678 sc = (struct bge_softc *)arg; 1679 1680 if (sc == NULL) 1681 panic("bge_jfree: can't find softc pointer!"); 1682 1683 /* calculate the slot this buffer belongs to */ 1684 1685 i = ((char *)buf 1686 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1687 1688 if ((i < 0) || (i >= BGE_JSLOTS)) 1689 panic("bge_jfree: asked to free buffer that we don't manage!"); 1690 1691 s = splvm(); 1692 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1693 if (entry == NULL) 1694 panic("bge_jfree: buffer not in use!"); 1695 entry->slot = i; 1696 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1697 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1698 1699 if (__predict_true(m != NULL)) 1700 pool_cache_put(mb_cache, m); 1701 splx(s); 1702 } 1703 1704 1705 /* 1706 * Initialize a standard receive ring descriptor. 1707 */ 1708 static int 1709 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1710 bus_dmamap_t dmamap) 1711 { 1712 struct mbuf *m_new = NULL; 1713 struct bge_rx_bd *r; 1714 int error; 1715 1716 if (dmamap == NULL) { 1717 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1718 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1719 if (error != 0) 1720 return error; 1721 } 1722 1723 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1724 1725 if (m == NULL) { 1726 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1727 if (m_new == NULL) 1728 return ENOBUFS; 1729 1730 MCLGET(m_new, M_DONTWAIT); 1731 if (!(m_new->m_flags & M_EXT)) { 1732 m_freem(m_new); 1733 return ENOBUFS; 1734 } 1735 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1736 1737 } else { 1738 m_new = m; 1739 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1740 m_new->m_data = m_new->m_ext.ext_buf; 1741 } 1742 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1743 m_adj(m_new, ETHER_ALIGN); 1744 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1745 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1746 m_freem(m_new); 1747 return ENOBUFS; 1748 } 1749 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1750 BUS_DMASYNC_PREREAD); 1751 1752 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1753 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1754 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1755 r->bge_flags = BGE_RXBDFLAG_END; 1756 r->bge_len = m_new->m_len; 1757 r->bge_idx = i; 1758 1759 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1760 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1761 i * sizeof (struct bge_rx_bd), 1762 sizeof (struct bge_rx_bd), 1763 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1764 1765 return 0; 1766 } 1767 1768 /* 1769 * Initialize a jumbo receive ring descriptor. This allocates 1770 * a jumbo buffer from the pool managed internally by the driver. 1771 */ 1772 static int 1773 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1774 { 1775 struct mbuf *m_new = NULL; 1776 struct bge_rx_bd *r; 1777 void *buf = NULL; 1778 1779 if (m == NULL) { 1780 1781 /* Allocate the mbuf. */ 1782 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1783 if (m_new == NULL) 1784 return ENOBUFS; 1785 1786 /* Allocate the jumbo buffer */ 1787 buf = bge_jalloc(sc); 1788 if (buf == NULL) { 1789 m_freem(m_new); 1790 aprint_error_dev(sc->bge_dev, 1791 "jumbo allocation failed -- packet dropped!\n"); 1792 return ENOBUFS; 1793 } 1794 1795 /* Attach the buffer to the mbuf. */ 1796 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1797 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1798 bge_jfree, sc); 1799 m_new->m_flags |= M_EXT_RW; 1800 } else { 1801 m_new = m; 1802 buf = m_new->m_data = m_new->m_ext.ext_buf; 1803 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1804 } 1805 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1806 m_adj(m_new, ETHER_ALIGN); 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1808 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1809 BUS_DMASYNC_PREREAD); 1810 /* Set up the descriptor. */ 1811 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1812 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1813 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1814 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1815 r->bge_len = m_new->m_len; 1816 r->bge_idx = i; 1817 1818 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1819 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1820 i * sizeof (struct bge_rx_bd), 1821 sizeof (struct bge_rx_bd), 1822 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1823 1824 return 0; 1825 } 1826 1827 /* 1828 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1829 * that's 1MB or memory, which is a lot. For now, we fill only the first 1830 * 256 ring entries and hope that our CPU is fast enough to keep up with 1831 * the NIC. 1832 */ 1833 static int 1834 bge_init_rx_ring_std(struct bge_softc *sc) 1835 { 1836 int i; 1837 1838 if (sc->bge_flags & BGEF_RXRING_VALID) 1839 return 0; 1840 1841 for (i = 0; i < BGE_SSLOTS; i++) { 1842 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1843 return ENOBUFS; 1844 } 1845 1846 sc->bge_std = i - 1; 1847 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1848 1849 sc->bge_flags |= BGEF_RXRING_VALID; 1850 1851 return 0; 1852 } 1853 1854 static void 1855 bge_free_rx_ring_std(struct bge_softc *sc) 1856 { 1857 int i; 1858 1859 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1860 return; 1861 1862 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1863 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1864 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1865 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1866 bus_dmamap_destroy(sc->bge_dmatag, 1867 sc->bge_cdata.bge_rx_std_map[i]); 1868 } 1869 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1870 sizeof(struct bge_rx_bd)); 1871 } 1872 1873 sc->bge_flags &= ~BGEF_RXRING_VALID; 1874 } 1875 1876 static int 1877 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1878 { 1879 int i; 1880 volatile struct bge_rcb *rcb; 1881 1882 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1883 return 0; 1884 1885 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1886 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1887 return ENOBUFS; 1888 } 1889 1890 sc->bge_jumbo = i - 1; 1891 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1892 1893 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1894 rcb->bge_maxlen_flags = 0; 1895 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1896 1897 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1898 1899 return 0; 1900 } 1901 1902 static void 1903 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1904 { 1905 int i; 1906 1907 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1908 return; 1909 1910 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1911 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1912 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1913 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1914 } 1915 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1916 sizeof(struct bge_rx_bd)); 1917 } 1918 1919 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1920 } 1921 1922 static void 1923 bge_free_tx_ring(struct bge_softc *sc) 1924 { 1925 int i; 1926 struct txdmamap_pool_entry *dma; 1927 1928 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1929 return; 1930 1931 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1932 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1933 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1934 sc->bge_cdata.bge_tx_chain[i] = NULL; 1935 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1936 link); 1937 sc->txdma[i] = 0; 1938 } 1939 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1940 sizeof(struct bge_tx_bd)); 1941 } 1942 1943 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1944 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1945 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1946 free(dma, M_DEVBUF); 1947 } 1948 1949 sc->bge_flags &= ~BGEF_TXRING_VALID; 1950 } 1951 1952 static int 1953 bge_init_tx_ring(struct bge_softc *sc) 1954 { 1955 struct ifnet *ifp = &sc->ethercom.ec_if; 1956 int i; 1957 bus_dmamap_t dmamap; 1958 bus_size_t maxsegsz; 1959 struct txdmamap_pool_entry *dma; 1960 1961 if (sc->bge_flags & BGEF_TXRING_VALID) 1962 return 0; 1963 1964 sc->bge_txcnt = 0; 1965 sc->bge_tx_saved_considx = 0; 1966 1967 /* Initialize transmit producer index for host-memory send ring. */ 1968 sc->bge_tx_prodidx = 0; 1969 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1970 /* 5700 b2 errata */ 1971 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1972 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1973 1974 /* NIC-memory send ring not used; initialize to zero. */ 1975 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1976 /* 5700 b2 errata */ 1977 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1978 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1979 1980 /* Limit DMA segment size for some chips */ 1981 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1982 (ifp->if_mtu <= ETHERMTU)) 1983 maxsegsz = 2048; 1984 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1985 maxsegsz = 4096; 1986 else 1987 maxsegsz = ETHER_MAX_LEN_JUMBO; 1988 SLIST_INIT(&sc->txdma_list); 1989 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1990 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1991 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, 1992 &dmamap)) 1993 return ENOBUFS; 1994 if (dmamap == NULL) 1995 panic("dmamap NULL in bge_init_tx_ring"); 1996 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1997 if (dma == NULL) { 1998 aprint_error_dev(sc->bge_dev, 1999 "can't alloc txdmamap_pool_entry\n"); 2000 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2001 return ENOMEM; 2002 } 2003 dma->dmamap = dmamap; 2004 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2005 } 2006 2007 sc->bge_flags |= BGEF_TXRING_VALID; 2008 2009 return 0; 2010 } 2011 2012 static void 2013 bge_setmulti(struct bge_softc *sc) 2014 { 2015 struct ethercom *ac = &sc->ethercom; 2016 struct ifnet *ifp = &ac->ec_if; 2017 struct ether_multi *enm; 2018 struct ether_multistep step; 2019 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2020 uint32_t h; 2021 int i; 2022 2023 if (ifp->if_flags & IFF_PROMISC) 2024 goto allmulti; 2025 2026 /* Now program new ones. */ 2027 ETHER_FIRST_MULTI(step, ac, enm); 2028 while (enm != NULL) { 2029 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2030 /* 2031 * We must listen to a range of multicast addresses. 2032 * For now, just accept all multicasts, rather than 2033 * trying to set only those filter bits needed to match 2034 * the range. (At this time, the only use of address 2035 * ranges is for IP multicast routing, for which the 2036 * range is big enough to require all bits set.) 2037 */ 2038 goto allmulti; 2039 } 2040 2041 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2042 2043 /* Just want the 7 least-significant bits. */ 2044 h &= 0x7f; 2045 2046 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2047 ETHER_NEXT_MULTI(step, enm); 2048 } 2049 2050 ifp->if_flags &= ~IFF_ALLMULTI; 2051 goto setit; 2052 2053 allmulti: 2054 ifp->if_flags |= IFF_ALLMULTI; 2055 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2056 2057 setit: 2058 for (i = 0; i < 4; i++) 2059 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2060 } 2061 2062 static void 2063 bge_sig_pre_reset(struct bge_softc *sc, int type) 2064 { 2065 2066 /* 2067 * Some chips don't like this so only do this if ASF is enabled 2068 */ 2069 if (sc->bge_asf_mode) 2070 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2071 2072 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2073 switch (type) { 2074 case BGE_RESET_START: 2075 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2076 BGE_FW_DRV_STATE_START); 2077 break; 2078 case BGE_RESET_SHUTDOWN: 2079 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2080 BGE_FW_DRV_STATE_UNLOAD); 2081 break; 2082 case BGE_RESET_SUSPEND: 2083 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2084 BGE_FW_DRV_STATE_SUSPEND); 2085 break; 2086 } 2087 } 2088 2089 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2090 bge_ape_driver_state_change(sc, type); 2091 } 2092 2093 static void 2094 bge_sig_post_reset(struct bge_softc *sc, int type) 2095 { 2096 2097 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2098 switch (type) { 2099 case BGE_RESET_START: 2100 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2101 BGE_FW_DRV_STATE_START_DONE); 2102 /* START DONE */ 2103 break; 2104 case BGE_RESET_SHUTDOWN: 2105 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2106 BGE_FW_DRV_STATE_UNLOAD_DONE); 2107 break; 2108 } 2109 } 2110 2111 if (type == BGE_RESET_SHUTDOWN) 2112 bge_ape_driver_state_change(sc, type); 2113 } 2114 2115 static void 2116 bge_sig_legacy(struct bge_softc *sc, int type) 2117 { 2118 2119 if (sc->bge_asf_mode) { 2120 switch (type) { 2121 case BGE_RESET_START: 2122 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2123 BGE_FW_DRV_STATE_START); 2124 break; 2125 case BGE_RESET_SHUTDOWN: 2126 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2127 BGE_FW_DRV_STATE_UNLOAD); 2128 break; 2129 } 2130 } 2131 } 2132 2133 static void 2134 bge_wait_for_event_ack(struct bge_softc *sc) 2135 { 2136 int i; 2137 2138 /* wait up to 2500usec */ 2139 for (i = 0; i < 250; i++) { 2140 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2141 BGE_RX_CPU_DRV_EVENT)) 2142 break; 2143 DELAY(10); 2144 } 2145 } 2146 2147 static void 2148 bge_stop_fw(struct bge_softc *sc) 2149 { 2150 2151 if (sc->bge_asf_mode) { 2152 bge_wait_for_event_ack(sc); 2153 2154 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2155 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2156 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2157 2158 bge_wait_for_event_ack(sc); 2159 } 2160 } 2161 2162 static int 2163 bge_poll_fw(struct bge_softc *sc) 2164 { 2165 uint32_t val; 2166 int i; 2167 2168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2169 for (i = 0; i < BGE_TIMEOUT; i++) { 2170 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2171 if (val & BGE_VCPU_STATUS_INIT_DONE) 2172 break; 2173 DELAY(100); 2174 } 2175 if (i >= BGE_TIMEOUT) { 2176 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2177 return -1; 2178 } 2179 } else { 2180 /* 2181 * Poll the value location we just wrote until 2182 * we see the 1's complement of the magic number. 2183 * This indicates that the firmware initialization 2184 * is complete. 2185 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2186 */ 2187 for (i = 0; i < BGE_TIMEOUT; i++) { 2188 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2189 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2190 break; 2191 DELAY(10); 2192 } 2193 2194 if ((i >= BGE_TIMEOUT) 2195 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2196 aprint_error_dev(sc->bge_dev, 2197 "firmware handshake timed out, val = %x\n", val); 2198 return -1; 2199 } 2200 } 2201 2202 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2203 /* tg3 says we have to wait extra time */ 2204 delay(10 * 1000); 2205 } 2206 2207 return 0; 2208 } 2209 2210 int 2211 bge_phy_addr(struct bge_softc *sc) 2212 { 2213 struct pci_attach_args *pa = &(sc->bge_pa); 2214 int phy_addr = 1; 2215 2216 /* 2217 * PHY address mapping for various devices. 2218 * 2219 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2220 * ---------+-------+-------+-------+-------+ 2221 * BCM57XX | 1 | X | X | X | 2222 * BCM5704 | 1 | X | 1 | X | 2223 * BCM5717 | 1 | 8 | 2 | 9 | 2224 * BCM5719 | 1 | 8 | 2 | 9 | 2225 * BCM5720 | 1 | 8 | 2 | 9 | 2226 * 2227 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2228 * ---------+-------+-------+-------+-------+ 2229 * BCM57XX | X | X | X | X | 2230 * BCM5704 | X | X | X | X | 2231 * BCM5717 | X | X | X | X | 2232 * BCM5719 | 3 | 10 | 4 | 11 | 2233 * BCM5720 | X | X | X | X | 2234 * 2235 * Other addresses may respond but they are not 2236 * IEEE compliant PHYs and should be ignored. 2237 */ 2238 switch (BGE_ASICREV(sc->bge_chipid)) { 2239 case BGE_ASICREV_BCM5717: 2240 case BGE_ASICREV_BCM5719: 2241 case BGE_ASICREV_BCM5720: 2242 phy_addr = pa->pa_function; 2243 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2244 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2245 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2246 } else { 2247 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2248 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2249 } 2250 } 2251 2252 return phy_addr; 2253 } 2254 2255 /* 2256 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2257 * self-test results. 2258 */ 2259 static int 2260 bge_chipinit(struct bge_softc *sc) 2261 { 2262 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2263 int i; 2264 2265 /* Set endianness before we access any non-PCI registers. */ 2266 misc_ctl = BGE_INIT; 2267 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2268 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2269 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2270 misc_ctl); 2271 2272 /* 2273 * Clear the MAC statistics block in the NIC's 2274 * internal memory. 2275 */ 2276 for (i = BGE_STATS_BLOCK; 2277 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2278 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2279 2280 for (i = BGE_STATUS_BLOCK; 2281 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2282 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2283 2284 /* 5717 workaround from tg3 */ 2285 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2286 /* Save */ 2287 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2288 2289 /* Temporary modify MODE_CTL to control TLP */ 2290 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2291 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2292 2293 /* Control TLP */ 2294 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2295 BGE_TLP_PHYCTL1); 2296 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2297 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2298 2299 /* Restore */ 2300 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2301 } 2302 2303 if (BGE_IS_57765_FAMILY(sc)) { 2304 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2305 /* Save */ 2306 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2307 2308 /* Temporary modify MODE_CTL to control TLP */ 2309 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2310 CSR_WRITE_4(sc, BGE_MODE_CTL, 2311 reg | BGE_MODECTL_PCIE_TLPADDR1); 2312 2313 /* Control TLP */ 2314 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2315 BGE_TLP_PHYCTL5); 2316 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2317 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2318 2319 /* Restore */ 2320 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2321 } 2322 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2323 /* 2324 * For the 57766 and non Ax versions of 57765, bootcode 2325 * needs to setup the PCIE Fast Training Sequence (FTS) 2326 * value to prevent transmit hangs. 2327 */ 2328 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2329 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2330 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2331 2332 /* Save */ 2333 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2334 2335 /* Temporary modify MODE_CTL to control TLP */ 2336 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2337 CSR_WRITE_4(sc, BGE_MODE_CTL, 2338 reg | BGE_MODECTL_PCIE_TLPADDR0); 2339 2340 /* Control TLP */ 2341 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2342 BGE_TLP_FTSMAX); 2343 reg &= ~BGE_TLP_FTSMAX_MSK; 2344 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2345 reg | BGE_TLP_FTSMAX_VAL); 2346 2347 /* Restore */ 2348 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2349 } 2350 2351 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2352 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2353 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2354 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2355 } 2356 2357 /* Set up the PCI DMA control register. */ 2358 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2359 if (sc->bge_flags & BGEF_PCIE) { 2360 /* Read watermark not used, 128 bytes for write. */ 2361 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2362 device_xname(sc->bge_dev))); 2363 if (sc->bge_mps >= 256) 2364 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2365 else 2366 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2367 } else if (sc->bge_flags & BGEF_PCIX) { 2368 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2369 device_xname(sc->bge_dev))); 2370 /* PCI-X bus */ 2371 if (BGE_IS_5714_FAMILY(sc)) { 2372 /* 256 bytes for read and write. */ 2373 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2374 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2375 2376 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2377 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2378 else 2379 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2380 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2381 /* 2382 * In the BCM5703, the DMA read watermark should 2383 * be set to less than or equal to the maximum 2384 * memory read byte count of the PCI-X command 2385 * register. 2386 */ 2387 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2388 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2389 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2390 /* 1536 bytes for read, 384 bytes for write. */ 2391 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2392 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2393 } else { 2394 /* 384 bytes for read and write. */ 2395 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2396 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2397 (0x0F); 2398 } 2399 2400 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2401 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2402 uint32_t tmp; 2403 2404 /* Set ONEDMA_ATONCE for hardware workaround. */ 2405 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2406 if (tmp == 6 || tmp == 7) 2407 dma_rw_ctl |= 2408 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2409 2410 /* Set PCI-X DMA write workaround. */ 2411 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2412 } 2413 } else { 2414 /* Conventional PCI bus: 256 bytes for read and write. */ 2415 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2416 device_xname(sc->bge_dev))); 2417 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2418 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2419 2420 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2421 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2422 dma_rw_ctl |= 0x0F; 2423 } 2424 2425 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2426 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2427 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2428 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2429 2430 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2431 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2432 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2433 2434 if (BGE_IS_57765_PLUS(sc)) { 2435 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2436 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2437 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2438 2439 /* 2440 * Enable HW workaround for controllers that misinterpret 2441 * a status tag update and leave interrupts permanently 2442 * disabled. 2443 */ 2444 if (!BGE_IS_57765_FAMILY(sc) && 2445 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2446 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2447 } 2448 2449 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2450 dma_rw_ctl); 2451 2452 /* 2453 * Set up general mode register. 2454 */ 2455 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2456 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2457 /* Retain Host-2-BMC settings written by APE firmware. */ 2458 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2459 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2460 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2461 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2462 } 2463 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2464 BGE_MODECTL_TX_NO_PHDR_CSUM; 2465 2466 /* 2467 * BCM5701 B5 have a bug causing data corruption when using 2468 * 64-bit DMA reads, which can be terminated early and then 2469 * completed later as 32-bit accesses, in combination with 2470 * certain bridges. 2471 */ 2472 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2473 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2474 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2475 2476 /* 2477 * Tell the firmware the driver is running 2478 */ 2479 if (sc->bge_asf_mode & ASF_STACKUP) 2480 mode_ctl |= BGE_MODECTL_STACKUP; 2481 2482 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2483 2484 /* 2485 * Disable memory write invalidate. Apparently it is not supported 2486 * properly by these devices. 2487 */ 2488 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2489 PCI_COMMAND_INVALIDATE_ENABLE); 2490 2491 #ifdef __brokenalpha__ 2492 /* 2493 * Must insure that we do not cross an 8K (bytes) boundary 2494 * for DMA reads. Our highest limit is 1K bytes. This is a 2495 * restriction on some ALPHA platforms with early revision 2496 * 21174 PCI chipsets, such as the AlphaPC 164lx 2497 */ 2498 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2499 #endif 2500 2501 /* Set the timer prescaler (always 66MHz) */ 2502 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2503 2504 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2505 DELAY(40); /* XXX */ 2506 2507 /* Put PHY into ready state */ 2508 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2509 DELAY(40); 2510 } 2511 2512 return 0; 2513 } 2514 2515 static int 2516 bge_blockinit(struct bge_softc *sc) 2517 { 2518 volatile struct bge_rcb *rcb; 2519 bus_size_t rcb_addr; 2520 struct ifnet *ifp = &sc->ethercom.ec_if; 2521 bge_hostaddr taddr; 2522 uint32_t dmactl, mimode, val; 2523 int i, limit; 2524 2525 /* 2526 * Initialize the memory window pointer register so that 2527 * we can access the first 32K of internal NIC RAM. This will 2528 * allow us to set up the TX send ring RCBs and the RX return 2529 * ring RCBs, plus other things which live in NIC memory. 2530 */ 2531 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2532 2533 if (!BGE_IS_5705_PLUS(sc)) { 2534 /* 57XX step 33 */ 2535 /* Configure mbuf memory pool */ 2536 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2537 BGE_BUFFPOOL_1); 2538 2539 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2540 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2541 else 2542 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2543 2544 /* 57XX step 34 */ 2545 /* Configure DMA resource pool */ 2546 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2547 BGE_DMA_DESCRIPTORS); 2548 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2549 } 2550 2551 /* 5718 step 11, 57XX step 35 */ 2552 /* 2553 * Configure mbuf pool watermarks. New broadcom docs strongly 2554 * recommend these. 2555 */ 2556 if (BGE_IS_5717_PLUS(sc)) { 2557 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2558 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2559 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2560 } else if (BGE_IS_5705_PLUS(sc)) { 2561 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2562 2563 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2564 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2565 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2566 } else { 2567 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2568 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2569 } 2570 } else { 2571 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2572 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2573 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2574 } 2575 2576 /* 57XX step 36 */ 2577 /* Configure DMA resource watermarks */ 2578 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2579 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2580 2581 /* 5718 step 13, 57XX step 38 */ 2582 /* Enable buffer manager */ 2583 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2584 /* 2585 * Change the arbitration algorithm of TXMBUF read request to 2586 * round-robin instead of priority based for BCM5719. When 2587 * TXFIFO is almost empty, RDMA will hold its request until 2588 * TXFIFO is not almost empty. 2589 */ 2590 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2591 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2592 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2593 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2594 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2595 val |= BGE_BMANMODE_LOMBUF_ATTN; 2596 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2597 2598 /* 57XX step 39 */ 2599 /* Poll for buffer manager start indication */ 2600 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2601 DELAY(10); 2602 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2603 break; 2604 } 2605 2606 if (i == BGE_TIMEOUT * 2) { 2607 aprint_error_dev(sc->bge_dev, 2608 "buffer manager failed to start\n"); 2609 return ENXIO; 2610 } 2611 2612 /* 57XX step 40 */ 2613 /* Enable flow-through queues */ 2614 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2615 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2616 2617 /* Wait until queue initialization is complete */ 2618 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2619 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2620 break; 2621 DELAY(10); 2622 } 2623 2624 if (i == BGE_TIMEOUT * 2) { 2625 aprint_error_dev(sc->bge_dev, 2626 "flow-through queue init failed\n"); 2627 return ENXIO; 2628 } 2629 2630 /* 2631 * Summary of rings supported by the controller: 2632 * 2633 * Standard Receive Producer Ring 2634 * - This ring is used to feed receive buffers for "standard" 2635 * sized frames (typically 1536 bytes) to the controller. 2636 * 2637 * Jumbo Receive Producer Ring 2638 * - This ring is used to feed receive buffers for jumbo sized 2639 * frames (i.e. anything bigger than the "standard" frames) 2640 * to the controller. 2641 * 2642 * Mini Receive Producer Ring 2643 * - This ring is used to feed receive buffers for "mini" 2644 * sized frames to the controller. 2645 * - This feature required external memory for the controller 2646 * but was never used in a production system. Should always 2647 * be disabled. 2648 * 2649 * Receive Return Ring 2650 * - After the controller has placed an incoming frame into a 2651 * receive buffer that buffer is moved into a receive return 2652 * ring. The driver is then responsible to passing the 2653 * buffer up to the stack. Many versions of the controller 2654 * support multiple RR rings. 2655 * 2656 * Send Ring 2657 * - This ring is used for outgoing frames. Many versions of 2658 * the controller support multiple send rings. 2659 */ 2660 2661 /* 5718 step 15, 57XX step 41 */ 2662 /* Initialize the standard RX ring control block */ 2663 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2664 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2665 /* 5718 step 16 */ 2666 if (BGE_IS_57765_PLUS(sc)) { 2667 /* 2668 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2669 * Bits 15-2 : Maximum RX frame size 2670 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2671 * Bit 0 : Reserved 2672 */ 2673 rcb->bge_maxlen_flags = 2674 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2675 } else if (BGE_IS_5705_PLUS(sc)) { 2676 /* 2677 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2678 * Bits 15-2 : Reserved (should be 0) 2679 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2680 * Bit 0 : Reserved 2681 */ 2682 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2683 } else { 2684 /* 2685 * Ring size is always XXX entries 2686 * Bits 31-16: Maximum RX frame size 2687 * Bits 15-2 : Reserved (should be 0) 2688 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2689 * Bit 0 : Reserved 2690 */ 2691 rcb->bge_maxlen_flags = 2692 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2693 } 2694 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2695 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2696 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2697 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2698 else 2699 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2700 /* Write the standard receive producer ring control block. */ 2701 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2702 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2703 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2704 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2705 2706 /* Reset the standard receive producer ring producer index. */ 2707 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2708 2709 /* 57XX step 42 */ 2710 /* 2711 * Initialize the jumbo RX ring control block 2712 * We set the 'ring disabled' bit in the flags 2713 * field until we're actually ready to start 2714 * using this ring (i.e. once we set the MTU 2715 * high enough to require it). 2716 */ 2717 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2718 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2719 BGE_HOSTADDR(rcb->bge_hostaddr, 2720 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2721 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2722 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2723 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2724 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2725 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2726 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2727 else 2728 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2729 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2730 rcb->bge_hostaddr.bge_addr_hi); 2731 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2732 rcb->bge_hostaddr.bge_addr_lo); 2733 /* Program the jumbo receive producer ring RCB parameters. */ 2734 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2735 rcb->bge_maxlen_flags); 2736 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2737 /* Reset the jumbo receive producer ring producer index. */ 2738 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2739 } 2740 2741 /* 57XX step 43 */ 2742 /* Disable the mini receive producer ring RCB. */ 2743 if (BGE_IS_5700_FAMILY(sc)) { 2744 /* Set up dummy disabled mini ring RCB */ 2745 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2746 rcb->bge_maxlen_flags = 2747 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2748 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2749 rcb->bge_maxlen_flags); 2750 /* Reset the mini receive producer ring producer index. */ 2751 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2752 2753 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2754 offsetof(struct bge_ring_data, bge_info), 2755 sizeof (struct bge_gib), 2756 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2757 } 2758 2759 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2760 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2761 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2762 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2763 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2764 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2765 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2766 } 2767 /* 5718 step 14, 57XX step 44 */ 2768 /* 2769 * The BD ring replenish thresholds control how often the 2770 * hardware fetches new BD's from the producer rings in host 2771 * memory. Setting the value too low on a busy system can 2772 * starve the hardware and recue the throughpout. 2773 * 2774 * Set the BD ring replenish thresholds. The recommended 2775 * values are 1/8th the number of descriptors allocated to 2776 * each ring, but since we try to avoid filling the entire 2777 * ring we set these to the minimal value of 8. This needs to 2778 * be done on several of the supported chip revisions anyway, 2779 * to work around HW bugs. 2780 */ 2781 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2782 if (BGE_IS_JUMBO_CAPABLE(sc)) 2783 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2784 2785 /* 5718 step 18 */ 2786 if (BGE_IS_5717_PLUS(sc)) { 2787 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2788 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2789 } 2790 2791 /* 57XX step 45 */ 2792 /* 2793 * Disable all send rings by setting the 'ring disabled' bit 2794 * in the flags field of all the TX send ring control blocks, 2795 * located in NIC memory. 2796 */ 2797 if (BGE_IS_5700_FAMILY(sc)) { 2798 /* 5700 to 5704 had 16 send rings. */ 2799 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2800 } else if (BGE_IS_5717_PLUS(sc)) { 2801 limit = BGE_TX_RINGS_5717_MAX; 2802 } else if (BGE_IS_57765_FAMILY(sc)) { 2803 limit = BGE_TX_RINGS_57765_MAX; 2804 } else 2805 limit = 1; 2806 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2807 for (i = 0; i < limit; i++) { 2808 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2809 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2810 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2811 rcb_addr += sizeof(struct bge_rcb); 2812 } 2813 2814 /* 57XX step 46 and 47 */ 2815 /* Configure send ring RCB 0 (we use only the first ring) */ 2816 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2817 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2818 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2819 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2820 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2821 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2822 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2823 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2824 else 2825 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2826 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2827 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2828 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2829 2830 /* 57XX step 48 */ 2831 /* 2832 * Disable all receive return rings by setting the 2833 * 'ring diabled' bit in the flags field of all the receive 2834 * return ring control blocks, located in NIC memory. 2835 */ 2836 if (BGE_IS_5717_PLUS(sc)) { 2837 /* Should be 17, use 16 until we get an SRAM map. */ 2838 limit = 16; 2839 } else if (BGE_IS_5700_FAMILY(sc)) 2840 limit = BGE_RX_RINGS_MAX; 2841 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2842 BGE_IS_57765_FAMILY(sc)) 2843 limit = 4; 2844 else 2845 limit = 1; 2846 /* Disable all receive return rings */ 2847 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2848 for (i = 0; i < limit; i++) { 2849 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2850 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2851 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2852 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2853 BGE_RCB_FLAG_RING_DISABLED)); 2854 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2855 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2856 (i * (sizeof(uint64_t))), 0); 2857 rcb_addr += sizeof(struct bge_rcb); 2858 } 2859 2860 /* 57XX step 49 */ 2861 /* 2862 * Set up receive return ring 0. Note that the NIC address 2863 * for RX return rings is 0x0. The return rings live entirely 2864 * within the host, so the nicaddr field in the RCB isn't used. 2865 */ 2866 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2867 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2868 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2869 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2870 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2871 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2872 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2873 2874 /* 5718 step 24, 57XX step 53 */ 2875 /* Set random backoff seed for TX */ 2876 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2877 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2878 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2879 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2880 BGE_TX_BACKOFF_SEED_MASK); 2881 2882 /* 5718 step 26, 57XX step 55 */ 2883 /* Set inter-packet gap */ 2884 val = 0x2620; 2885 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2886 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2887 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2888 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2889 2890 /* 5718 step 27, 57XX step 56 */ 2891 /* 2892 * Specify which ring to use for packets that don't match 2893 * any RX rules. 2894 */ 2895 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2896 2897 /* 5718 step 28, 57XX step 57 */ 2898 /* 2899 * Configure number of RX lists. One interrupt distribution 2900 * list, sixteen active lists, one bad frames class. 2901 */ 2902 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2903 2904 /* 5718 step 29, 57XX step 58 */ 2905 /* Inialize RX list placement stats mask. */ 2906 if (BGE_IS_575X_PLUS(sc)) { 2907 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2908 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2909 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2910 } else 2911 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2912 2913 /* 5718 step 30, 57XX step 59 */ 2914 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2915 2916 /* 5718 step 33, 57XX step 62 */ 2917 /* Disable host coalescing until we get it set up */ 2918 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2919 2920 /* 5718 step 34, 57XX step 63 */ 2921 /* Poll to make sure it's shut down. */ 2922 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2923 DELAY(10); 2924 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2925 break; 2926 } 2927 2928 if (i == BGE_TIMEOUT * 2) { 2929 aprint_error_dev(sc->bge_dev, 2930 "host coalescing engine failed to idle\n"); 2931 return ENXIO; 2932 } 2933 2934 /* 5718 step 35, 36, 37 */ 2935 /* Set up host coalescing defaults */ 2936 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2937 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2938 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2939 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2940 if (!(BGE_IS_5705_PLUS(sc))) { 2941 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2942 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2943 } 2944 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2945 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2946 2947 /* Set up address of statistics block */ 2948 if (BGE_IS_5700_FAMILY(sc)) { 2949 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2950 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2951 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2952 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2953 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2954 } 2955 2956 /* 5718 step 38 */ 2957 /* Set up address of status block */ 2958 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2959 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2960 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2961 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2962 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2963 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2964 2965 /* Set up status block size. */ 2966 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2967 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2968 val = BGE_STATBLKSZ_FULL; 2969 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2970 } else { 2971 val = BGE_STATBLKSZ_32BYTE; 2972 bzero(&sc->bge_rdata->bge_status_block, 32); 2973 } 2974 2975 /* 5718 step 39, 57XX step 73 */ 2976 /* Turn on host coalescing state machine */ 2977 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2978 2979 /* 5718 step 40, 57XX step 74 */ 2980 /* Turn on RX BD completion state machine and enable attentions */ 2981 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2982 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2983 2984 /* 5718 step 41, 57XX step 75 */ 2985 /* Turn on RX list placement state machine */ 2986 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2987 2988 /* 57XX step 76 */ 2989 /* Turn on RX list selector state machine. */ 2990 if (!(BGE_IS_5705_PLUS(sc))) 2991 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2992 2993 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2994 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2995 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2996 BGE_MACMODE_FRMHDR_DMA_ENB; 2997 2998 if (sc->bge_flags & BGEF_FIBER_TBI) 2999 val |= BGE_PORTMODE_TBI; 3000 else if (sc->bge_flags & BGEF_FIBER_MII) 3001 val |= BGE_PORTMODE_GMII; 3002 else 3003 val |= BGE_PORTMODE_MII; 3004 3005 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 3006 /* Allow APE to send/receive frames. */ 3007 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3008 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3009 3010 /* Turn on DMA, clear stats */ 3011 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3012 /* 5718 step 44 */ 3013 DELAY(40); 3014 3015 /* 5718 step 45, 57XX step 79 */ 3016 /* Set misc. local control, enable interrupts on attentions */ 3017 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3018 if (BGE_IS_5717_PLUS(sc)) { 3019 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3020 /* 5718 step 46 */ 3021 DELAY(100); 3022 } 3023 3024 /* 57XX step 81 */ 3025 /* Turn on DMA completion state machine */ 3026 if (!(BGE_IS_5705_PLUS(sc))) 3027 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3028 3029 /* 5718 step 47, 57XX step 82 */ 3030 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3031 3032 /* 5718 step 48 */ 3033 /* Enable host coalescing bug fix. */ 3034 if (BGE_IS_5755_PLUS(sc)) 3035 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3036 3037 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3038 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3039 3040 /* Turn on write DMA state machine */ 3041 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3042 /* 5718 step 49 */ 3043 DELAY(40); 3044 3045 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3046 3047 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3048 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3049 3050 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3051 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3052 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3053 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3054 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3055 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3056 3057 if (sc->bge_flags & BGEF_PCIE) 3058 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3059 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3060 if (ifp->if_mtu <= ETHERMTU) 3061 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3062 } 3063 if (sc->bge_flags & BGEF_TSO) 3064 val |= BGE_RDMAMODE_TSO4_ENABLE; 3065 3066 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3067 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3068 BGE_RDMAMODE_H2BNC_VLAN_DET; 3069 /* 3070 * Allow multiple outstanding read requests from 3071 * non-LSO read DMA engine. 3072 */ 3073 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3074 } 3075 3076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3077 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3078 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3079 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3080 BGE_IS_57765_PLUS(sc)) { 3081 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3082 /* 3083 * Adjust tx margin to prevent TX data corruption and 3084 * fix internal FIFO overflow. 3085 */ 3086 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3087 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3088 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3089 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3090 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3091 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3092 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3093 } 3094 /* 3095 * Enable fix for read DMA FIFO overruns. 3096 * The fix is to limit the number of RX BDs 3097 * the hardware would fetch at a fime. 3098 */ 3099 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3100 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3101 } 3102 3103 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3104 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3105 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3106 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3107 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3108 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3109 /* 3110 * Allow 4KB burst length reads for non-LSO frames. 3111 * Enable 512B burst length reads for buffer descriptors. 3112 */ 3113 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3114 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3115 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3116 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3117 } 3118 3119 /* Turn on read DMA state machine */ 3120 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3121 /* 5718 step 52 */ 3122 delay(40); 3123 3124 /* 5718 step 56, 57XX step 84 */ 3125 /* Turn on RX data completion state machine */ 3126 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3127 3128 /* Turn on RX data and RX BD initiator state machine */ 3129 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3130 3131 /* 57XX step 85 */ 3132 /* Turn on Mbuf cluster free state machine */ 3133 if (!BGE_IS_5705_PLUS(sc)) 3134 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3135 3136 /* 5718 step 57, 57XX step 86 */ 3137 /* Turn on send data completion state machine */ 3138 val = BGE_SDCMODE_ENABLE; 3139 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3140 val |= BGE_SDCMODE_CDELAY; 3141 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3142 3143 /* 5718 step 58 */ 3144 /* Turn on send BD completion state machine */ 3145 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3146 3147 /* 57XX step 88 */ 3148 /* Turn on RX BD initiator state machine */ 3149 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3150 3151 /* 5718 step 60, 57XX step 90 */ 3152 /* Turn on send data initiator state machine */ 3153 if (sc->bge_flags & BGEF_TSO) { 3154 /* XXX: magic value from Linux driver */ 3155 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3156 BGE_SDIMODE_HW_LSO_PRE_DMA); 3157 } else 3158 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3159 3160 /* 5718 step 61, 57XX step 91 */ 3161 /* Turn on send BD initiator state machine */ 3162 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3163 3164 /* 5718 step 62, 57XX step 92 */ 3165 /* Turn on send BD selector state machine */ 3166 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3167 3168 /* 5718 step 31, 57XX step 60 */ 3169 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3170 /* 5718 step 32, 57XX step 61 */ 3171 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3172 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3173 3174 /* ack/clear link change events */ 3175 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3176 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3177 BGE_MACSTAT_LINK_CHANGED); 3178 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3179 3180 /* 3181 * Enable attention when the link has changed state for 3182 * devices that use auto polling. 3183 */ 3184 if (sc->bge_flags & BGEF_FIBER_TBI) { 3185 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3186 } else { 3187 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3188 mimode = BGE_MIMODE_500KHZ_CONST; 3189 else 3190 mimode = BGE_MIMODE_BASE; 3191 /* 5718 step 68. 5718 step 69 (optionally). */ 3192 if (BGE_IS_5700_FAMILY(sc) || 3193 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3194 mimode |= BGE_MIMODE_AUTOPOLL; 3195 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3196 } 3197 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3198 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3199 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3200 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3201 BGE_EVTENB_MI_INTERRUPT); 3202 } 3203 3204 /* 3205 * Clear any pending link state attention. 3206 * Otherwise some link state change events may be lost until attention 3207 * is cleared by bge_intr() -> bge_link_upd() sequence. 3208 * It's not necessary on newer BCM chips - perhaps enabling link 3209 * state change attentions implies clearing pending attention. 3210 */ 3211 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3212 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3213 BGE_MACSTAT_LINK_CHANGED); 3214 3215 /* Enable link state change attentions. */ 3216 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3217 3218 return 0; 3219 } 3220 3221 static const struct bge_revision * 3222 bge_lookup_rev(uint32_t chipid) 3223 { 3224 const struct bge_revision *br; 3225 3226 for (br = bge_revisions; br->br_name != NULL; br++) { 3227 if (br->br_chipid == chipid) 3228 return br; 3229 } 3230 3231 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3232 if (br->br_chipid == BGE_ASICREV(chipid)) 3233 return br; 3234 } 3235 3236 return NULL; 3237 } 3238 3239 static const struct bge_product * 3240 bge_lookup(const struct pci_attach_args *pa) 3241 { 3242 const struct bge_product *bp; 3243 3244 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3245 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3246 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3247 return bp; 3248 } 3249 3250 return NULL; 3251 } 3252 3253 static uint32_t 3254 bge_chipid(const struct pci_attach_args *pa) 3255 { 3256 uint32_t id; 3257 3258 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3259 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3260 3261 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3262 switch (PCI_PRODUCT(pa->pa_id)) { 3263 case PCI_PRODUCT_BROADCOM_BCM5717: 3264 case PCI_PRODUCT_BROADCOM_BCM5718: 3265 case PCI_PRODUCT_BROADCOM_BCM5719: 3266 case PCI_PRODUCT_BROADCOM_BCM5720: 3267 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3268 BGE_PCI_GEN2_PRODID_ASICREV); 3269 break; 3270 case PCI_PRODUCT_BROADCOM_BCM57761: 3271 case PCI_PRODUCT_BROADCOM_BCM57762: 3272 case PCI_PRODUCT_BROADCOM_BCM57765: 3273 case PCI_PRODUCT_BROADCOM_BCM57766: 3274 case PCI_PRODUCT_BROADCOM_BCM57781: 3275 case PCI_PRODUCT_BROADCOM_BCM57782: 3276 case PCI_PRODUCT_BROADCOM_BCM57785: 3277 case PCI_PRODUCT_BROADCOM_BCM57786: 3278 case PCI_PRODUCT_BROADCOM_BCM57791: 3279 case PCI_PRODUCT_BROADCOM_BCM57795: 3280 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3281 BGE_PCI_GEN15_PRODID_ASICREV); 3282 break; 3283 default: 3284 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3285 BGE_PCI_PRODID_ASICREV); 3286 break; 3287 } 3288 } 3289 3290 return id; 3291 } 3292 3293 /* 3294 * Return true if MSI can be used with this device. 3295 */ 3296 static int 3297 bge_can_use_msi(struct bge_softc *sc) 3298 { 3299 int can_use_msi = 0; 3300 3301 switch (BGE_ASICREV(sc->bge_chipid)) { 3302 case BGE_ASICREV_BCM5714_A0: 3303 case BGE_ASICREV_BCM5714: 3304 /* 3305 * Apparently, MSI doesn't work when these chips are 3306 * configured in single-port mode. 3307 */ 3308 break; 3309 case BGE_ASICREV_BCM5750: 3310 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3311 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3312 can_use_msi = 1; 3313 break; 3314 default: 3315 if (BGE_IS_575X_PLUS(sc)) 3316 can_use_msi = 1; 3317 } 3318 return (can_use_msi); 3319 } 3320 3321 /* 3322 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3323 * against our list and return its name if we find a match. Note 3324 * that since the Broadcom controller contains VPD support, we 3325 * can get the device name string from the controller itself instead 3326 * of the compiled-in string. This is a little slow, but it guarantees 3327 * we'll always announce the right product name. 3328 */ 3329 static int 3330 bge_probe(device_t parent, cfdata_t match, void *aux) 3331 { 3332 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3333 3334 if (bge_lookup(pa) != NULL) 3335 return 1; 3336 3337 return 0; 3338 } 3339 3340 static void 3341 bge_attach(device_t parent, device_t self, void *aux) 3342 { 3343 struct bge_softc *sc = device_private(self); 3344 struct pci_attach_args *pa = aux; 3345 prop_dictionary_t dict; 3346 const struct bge_product *bp; 3347 const struct bge_revision *br; 3348 pci_chipset_tag_t pc; 3349 int counts[PCI_INTR_TYPE_SIZE]; 3350 pci_intr_type_t intr_type, max_type; 3351 const char *intrstr = NULL; 3352 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3353 uint32_t command; 3354 struct ifnet *ifp; 3355 uint32_t misccfg, mimode; 3356 void * kva; 3357 u_char eaddr[ETHER_ADDR_LEN]; 3358 pcireg_t memtype, subid, reg; 3359 bus_addr_t memaddr; 3360 uint32_t pm_ctl; 3361 bool no_seeprom; 3362 int capmask; 3363 int mii_flags; 3364 int map_flags; 3365 char intrbuf[PCI_INTRSTR_LEN]; 3366 3367 bp = bge_lookup(pa); 3368 KASSERT(bp != NULL); 3369 3370 sc->sc_pc = pa->pa_pc; 3371 sc->sc_pcitag = pa->pa_tag; 3372 sc->bge_dev = self; 3373 3374 sc->bge_pa = *pa; 3375 pc = sc->sc_pc; 3376 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3377 3378 aprint_naive(": Ethernet controller\n"); 3379 aprint_normal(": %s\n", bp->bp_name); 3380 3381 /* 3382 * Map control/status registers. 3383 */ 3384 DPRINTFN(5, ("Map control/status regs\n")); 3385 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3386 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3387 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3388 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3389 3390 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3391 aprint_error_dev(sc->bge_dev, 3392 "failed to enable memory mapping!\n"); 3393 return; 3394 } 3395 3396 DPRINTFN(5, ("pci_mem_find\n")); 3397 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3398 switch (memtype) { 3399 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3400 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3401 #if 0 3402 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3403 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3404 &memaddr, &sc->bge_bsize) == 0) 3405 break; 3406 #else 3407 /* 3408 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3409 * system get NMI on boot (PR#48451). This problem might not be 3410 * the driver's bug but our PCI common part's bug. Until we 3411 * find a real reason, we ignore the prefetchable bit. 3412 */ 3413 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3414 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3415 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3416 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3417 map_flags, &sc->bge_bhandle) == 0) { 3418 sc->bge_btag = pa->pa_memt; 3419 break; 3420 } 3421 } 3422 #endif 3423 default: 3424 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3425 return; 3426 } 3427 3428 /* Save various chip information. */ 3429 sc->bge_chipid = bge_chipid(pa); 3430 sc->bge_phy_addr = bge_phy_addr(sc); 3431 3432 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3433 &sc->bge_pciecap, NULL) != 0) { 3434 /* PCIe */ 3435 sc->bge_flags |= BGEF_PCIE; 3436 /* Extract supported maximum payload size. */ 3437 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3438 sc->bge_pciecap + PCIE_DCAP); 3439 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3440 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3441 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3442 sc->bge_expmrq = 2048; 3443 else 3444 sc->bge_expmrq = 4096; 3445 bge_set_max_readrq(sc); 3446 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3447 /* PCIe without PCIe cap */ 3448 sc->bge_flags |= BGEF_PCIE; 3449 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3450 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3451 /* PCI-X */ 3452 sc->bge_flags |= BGEF_PCIX; 3453 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3454 &sc->bge_pcixcap, NULL) == 0) 3455 aprint_error_dev(sc->bge_dev, 3456 "unable to find PCIX capability\n"); 3457 } 3458 3459 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3460 /* 3461 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3462 * can clobber the chip's PCI config-space power control 3463 * registers, leaving the card in D3 powersave state. We do 3464 * not have memory-mapped registers in this state, so force 3465 * device into D0 state before starting initialization. 3466 */ 3467 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3468 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3469 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3470 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3471 DELAY(1000); /* 27 usec is allegedly sufficent */ 3472 } 3473 3474 /* Save chipset family. */ 3475 switch (BGE_ASICREV(sc->bge_chipid)) { 3476 case BGE_ASICREV_BCM5717: 3477 case BGE_ASICREV_BCM5719: 3478 case BGE_ASICREV_BCM5720: 3479 sc->bge_flags |= BGEF_5717_PLUS; 3480 /* FALLTHROUGH */ 3481 case BGE_ASICREV_BCM57765: 3482 case BGE_ASICREV_BCM57766: 3483 if (!BGE_IS_5717_PLUS(sc)) 3484 sc->bge_flags |= BGEF_57765_FAMILY; 3485 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3486 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3487 /* Jumbo frame on BCM5719 A0 does not work. */ 3488 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3489 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3490 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3491 break; 3492 case BGE_ASICREV_BCM5755: 3493 case BGE_ASICREV_BCM5761: 3494 case BGE_ASICREV_BCM5784: 3495 case BGE_ASICREV_BCM5785: 3496 case BGE_ASICREV_BCM5787: 3497 case BGE_ASICREV_BCM57780: 3498 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3499 break; 3500 case BGE_ASICREV_BCM5700: 3501 case BGE_ASICREV_BCM5701: 3502 case BGE_ASICREV_BCM5703: 3503 case BGE_ASICREV_BCM5704: 3504 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3505 break; 3506 case BGE_ASICREV_BCM5714_A0: 3507 case BGE_ASICREV_BCM5780: 3508 case BGE_ASICREV_BCM5714: 3509 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3510 /* FALLTHROUGH */ 3511 case BGE_ASICREV_BCM5750: 3512 case BGE_ASICREV_BCM5752: 3513 case BGE_ASICREV_BCM5906: 3514 sc->bge_flags |= BGEF_575X_PLUS; 3515 /* FALLTHROUGH */ 3516 case BGE_ASICREV_BCM5705: 3517 sc->bge_flags |= BGEF_5705_PLUS; 3518 break; 3519 } 3520 3521 /* Identify chips with APE processor. */ 3522 switch (BGE_ASICREV(sc->bge_chipid)) { 3523 case BGE_ASICREV_BCM5717: 3524 case BGE_ASICREV_BCM5719: 3525 case BGE_ASICREV_BCM5720: 3526 case BGE_ASICREV_BCM5761: 3527 sc->bge_flags |= BGEF_APE; 3528 break; 3529 } 3530 3531 /* 3532 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3533 * not actually a MAC controller bug but an issue with the embedded 3534 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3535 */ 3536 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3537 sc->bge_flags |= BGEF_40BIT_BUG; 3538 3539 /* Chips with APE need BAR2 access for APE registers/memory. */ 3540 if ((sc->bge_flags & BGEF_APE) != 0) { 3541 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3542 #if 0 3543 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3544 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3545 &sc->bge_apesize)) { 3546 aprint_error_dev(sc->bge_dev, 3547 "couldn't map BAR2 memory\n"); 3548 return; 3549 } 3550 #else 3551 /* 3552 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3553 * system get NMI on boot (PR#48451). This problem might not be 3554 * the driver's bug but our PCI common part's bug. Until we 3555 * find a real reason, we ignore the prefetchable bit. 3556 */ 3557 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3558 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3559 aprint_error_dev(sc->bge_dev, 3560 "couldn't map BAR2 memory\n"); 3561 return; 3562 } 3563 3564 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3565 if (bus_space_map(pa->pa_memt, memaddr, 3566 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3567 aprint_error_dev(sc->bge_dev, 3568 "couldn't map BAR2 memory\n"); 3569 return; 3570 } 3571 sc->bge_apetag = pa->pa_memt; 3572 #endif 3573 3574 /* Enable APE register/memory access by host driver. */ 3575 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3576 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3577 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3578 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3579 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3580 3581 bge_ape_lock_init(sc); 3582 bge_ape_read_fw_ver(sc); 3583 } 3584 3585 /* Identify the chips that use an CPMU. */ 3586 if (BGE_IS_5717_PLUS(sc) || 3587 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3588 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3589 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3590 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3591 sc->bge_flags |= BGEF_CPMU_PRESENT; 3592 3593 /* Set MI_MODE */ 3594 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3595 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3596 mimode |= BGE_MIMODE_500KHZ_CONST; 3597 else 3598 mimode |= BGE_MIMODE_BASE; 3599 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3600 3601 /* 3602 * When using the BCM5701 in PCI-X mode, data corruption has 3603 * been observed in the first few bytes of some received packets. 3604 * Aligning the packet buffer in memory eliminates the corruption. 3605 * Unfortunately, this misaligns the packet payloads. On platforms 3606 * which do not support unaligned accesses, we will realign the 3607 * payloads by copying the received packets. 3608 */ 3609 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3610 sc->bge_flags & BGEF_PCIX) 3611 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3612 3613 if (BGE_IS_5700_FAMILY(sc)) 3614 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3615 3616 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3617 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3618 3619 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3620 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3621 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3622 sc->bge_flags |= BGEF_IS_5788; 3623 3624 /* 3625 * Some controllers seem to require a special firmware to use 3626 * TSO. But the firmware is not available to FreeBSD and Linux 3627 * claims that the TSO performed by the firmware is slower than 3628 * hardware based TSO. Moreover the firmware based TSO has one 3629 * known bug which can't handle TSO if ethernet header + IP/TCP 3630 * header is greater than 80 bytes. The workaround for the TSO 3631 * bug exist but it seems it's too expensive than not using 3632 * TSO at all. Some hardwares also have the TSO bug so limit 3633 * the TSO to the controllers that are not affected TSO issues 3634 * (e.g. 5755 or higher). 3635 */ 3636 if (BGE_IS_5755_PLUS(sc)) { 3637 /* 3638 * BCM5754 and BCM5787 shares the same ASIC id so 3639 * explicit device id check is required. 3640 */ 3641 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3642 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3643 sc->bge_flags |= BGEF_TSO; 3644 } 3645 3646 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3647 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3648 (misccfg == 0x4000 || misccfg == 0x8000)) || 3649 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3650 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3651 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3652 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3653 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3654 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3655 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3656 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3657 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3658 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3659 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3660 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3661 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3662 /* These chips are 10/100 only. */ 3663 capmask &= ~BMSR_EXTSTAT; 3664 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3665 } 3666 3667 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3668 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3669 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3670 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3671 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3672 3673 /* Set various PHY bug flags. */ 3674 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3675 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3676 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3677 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3678 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3679 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3680 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3681 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3682 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3683 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3684 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3685 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3686 if (BGE_IS_5705_PLUS(sc) && 3687 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3688 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3689 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3690 !BGE_IS_57765_PLUS(sc)) { 3691 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3692 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3693 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3694 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3695 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3696 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3697 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3698 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3699 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3700 } else 3701 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3702 } 3703 3704 /* 3705 * SEEPROM check. 3706 * First check if firmware knows we do not have SEEPROM. 3707 */ 3708 if (prop_dictionary_get_bool(device_properties(self), 3709 "without-seeprom", &no_seeprom) && no_seeprom) 3710 sc->bge_flags |= BGEF_NO_EEPROM; 3711 3712 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3713 sc->bge_flags |= BGEF_NO_EEPROM; 3714 3715 /* Now check the 'ROM failed' bit on the RX CPU */ 3716 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3717 sc->bge_flags |= BGEF_NO_EEPROM; 3718 3719 sc->bge_asf_mode = 0; 3720 /* No ASF if APE present. */ 3721 if ((sc->bge_flags & BGEF_APE) == 0) { 3722 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3723 BGE_SRAM_DATA_SIG_MAGIC)) { 3724 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3725 BGE_HWCFG_ASF) { 3726 sc->bge_asf_mode |= ASF_ENABLE; 3727 sc->bge_asf_mode |= ASF_STACKUP; 3728 if (BGE_IS_575X_PLUS(sc)) 3729 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3730 } 3731 } 3732 } 3733 3734 /* MSI-X will be used in future */ 3735 counts[PCI_INTR_TYPE_MSI] = 1; 3736 counts[PCI_INTR_TYPE_INTX] = 1; 3737 /* Check MSI capability */ 3738 if (bge_can_use_msi(sc) != 0) { 3739 max_type = PCI_INTR_TYPE_MSI; 3740 sc->bge_flags |= BGEF_MSI; 3741 } else 3742 max_type = PCI_INTR_TYPE_INTX; 3743 3744 alloc_retry: 3745 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3746 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3747 return; 3748 } 3749 3750 DPRINTFN(5, ("pci_intr_string\n")); 3751 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3752 sizeof(intrbuf)); 3753 DPRINTFN(5, ("pci_intr_establish\n")); 3754 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3755 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3756 if (sc->bge_intrhand == NULL) { 3757 intr_type = pci_intr_type(pc, sc->bge_pihp[0]); 3758 aprint_error_dev(sc->bge_dev,"unable to establish %s\n", 3759 (intr_type == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 3760 pci_intr_release(pc, sc->bge_pihp, 1); 3761 switch (intr_type) { 3762 case PCI_INTR_TYPE_MSI: 3763 /* The next try is for INTx: Disable MSI */ 3764 max_type = PCI_INTR_TYPE_INTX; 3765 counts[PCI_INTR_TYPE_INTX] = 1; 3766 sc->bge_flags &= ~BGEF_MSI; 3767 goto alloc_retry; 3768 case PCI_INTR_TYPE_INTX: 3769 default: 3770 /* See below */ 3771 break; 3772 } 3773 } 3774 3775 if (sc->bge_intrhand == NULL) { 3776 aprint_error_dev(sc->bge_dev, 3777 "couldn't establish interrupt%s%s\n", 3778 intrstr ? " at " : "", intrstr ? intrstr : ""); 3779 return; 3780 } 3781 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3782 3783 /* 3784 * All controllers except BCM5700 supports tagged status but 3785 * we use tagged status only for MSI case on BCM5717. Otherwise 3786 * MSI on BCM5717 does not work. 3787 */ 3788 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3789 sc->bge_flags |= BGEF_TAGGED_STATUS; 3790 3791 /* 3792 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3793 * lock in bge_reset(). 3794 */ 3795 CSR_WRITE_4(sc, BGE_EE_ADDR, 3796 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3797 delay(1000); 3798 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3799 3800 bge_stop_fw(sc); 3801 bge_sig_pre_reset(sc, BGE_RESET_START); 3802 if (bge_reset(sc)) 3803 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3804 3805 /* 3806 * Read the hardware config word in the first 32k of NIC internal 3807 * memory, or fall back to the config word in the EEPROM. 3808 * Note: on some BCM5700 cards, this value appears to be unset. 3809 */ 3810 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3811 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3812 BGE_SRAM_DATA_SIG_MAGIC) { 3813 uint32_t tmp; 3814 3815 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3816 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3817 BGE_SRAM_DATA_VER_SHIFT; 3818 if ((0 < tmp) && (tmp < 0x100)) 3819 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3820 if (sc->bge_flags & BGEF_PCIE) 3821 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3823 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3824 if (BGE_IS_5717_PLUS(sc)) 3825 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3826 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3827 bge_read_eeprom(sc, (void *)&hwcfg, 3828 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3829 hwcfg = be32toh(hwcfg); 3830 } 3831 aprint_normal_dev(sc->bge_dev, 3832 "HW config %08x, %08x, %08x, %08x %08x\n", 3833 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3834 3835 bge_sig_legacy(sc, BGE_RESET_START); 3836 bge_sig_post_reset(sc, BGE_RESET_START); 3837 3838 if (bge_chipinit(sc)) { 3839 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3840 bge_release_resources(sc); 3841 return; 3842 } 3843 3844 /* 3845 * Get station address from the EEPROM. 3846 */ 3847 if (bge_get_eaddr(sc, eaddr)) { 3848 aprint_error_dev(sc->bge_dev, 3849 "failed to read station address\n"); 3850 bge_release_resources(sc); 3851 return; 3852 } 3853 3854 br = bge_lookup_rev(sc->bge_chipid); 3855 3856 if (br == NULL) { 3857 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3858 sc->bge_chipid); 3859 } else { 3860 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3861 br->br_name, sc->bge_chipid); 3862 } 3863 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3864 3865 /* Allocate the general information block and ring buffers. */ 3866 if (pci_dma64_available(pa)) 3867 sc->bge_dmatag = pa->pa_dmat64; 3868 else 3869 sc->bge_dmatag = pa->pa_dmat; 3870 3871 /* 40bit DMA workaround */ 3872 if (sizeof(bus_addr_t) > 4) { 3873 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3874 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3875 3876 if (bus_dmatag_subregion(olddmatag, 0, 3877 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3878 BUS_DMA_NOWAIT) != 0) { 3879 aprint_error_dev(self, 3880 "WARNING: failed to restrict dma range," 3881 " falling back to parent bus dma range\n"); 3882 sc->bge_dmatag = olddmatag; 3883 } 3884 } 3885 } 3886 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3887 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3888 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3889 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3890 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3891 return; 3892 } 3893 DPRINTFN(5, ("bus_dmamem_map\n")); 3894 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3895 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3896 BUS_DMA_NOWAIT)) { 3897 aprint_error_dev(sc->bge_dev, 3898 "can't map DMA buffers (%zu bytes)\n", 3899 sizeof(struct bge_ring_data)); 3900 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3901 sc->bge_ring_rseg); 3902 return; 3903 } 3904 DPRINTFN(5, ("bus_dmamem_create\n")); 3905 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3906 sizeof(struct bge_ring_data), 0, 3907 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3908 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3909 bus_dmamem_unmap(sc->bge_dmatag, kva, 3910 sizeof(struct bge_ring_data)); 3911 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3912 sc->bge_ring_rseg); 3913 return; 3914 } 3915 DPRINTFN(5, ("bus_dmamem_load\n")); 3916 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3917 sizeof(struct bge_ring_data), NULL, 3918 BUS_DMA_NOWAIT)) { 3919 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3920 bus_dmamem_unmap(sc->bge_dmatag, kva, 3921 sizeof(struct bge_ring_data)); 3922 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3923 sc->bge_ring_rseg); 3924 return; 3925 } 3926 3927 DPRINTFN(5, ("bzero\n")); 3928 sc->bge_rdata = (struct bge_ring_data *)kva; 3929 3930 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3931 3932 /* Try to allocate memory for jumbo buffers. */ 3933 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3934 if (bge_alloc_jumbo_mem(sc)) { 3935 aprint_error_dev(sc->bge_dev, 3936 "jumbo buffer allocation failed\n"); 3937 } else 3938 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3939 } 3940 3941 /* Set default tuneable values. */ 3942 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3943 sc->bge_rx_coal_ticks = 150; 3944 sc->bge_rx_max_coal_bds = 64; 3945 sc->bge_tx_coal_ticks = 300; 3946 sc->bge_tx_max_coal_bds = 400; 3947 if (BGE_IS_5705_PLUS(sc)) { 3948 sc->bge_tx_coal_ticks = (12 * 5); 3949 sc->bge_tx_max_coal_bds = (12 * 5); 3950 aprint_verbose_dev(sc->bge_dev, 3951 "setting short Tx thresholds\n"); 3952 } 3953 3954 if (BGE_IS_5717_PLUS(sc)) 3955 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3956 else if (BGE_IS_5705_PLUS(sc)) 3957 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3958 else 3959 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3960 3961 /* Set up ifnet structure */ 3962 ifp = &sc->ethercom.ec_if; 3963 ifp->if_softc = sc; 3964 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3965 ifp->if_ioctl = bge_ioctl; 3966 ifp->if_stop = bge_stop; 3967 ifp->if_start = bge_start; 3968 ifp->if_init = bge_init; 3969 ifp->if_watchdog = bge_watchdog; 3970 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3971 IFQ_SET_READY(&ifp->if_snd); 3972 DPRINTFN(5, ("strcpy if_xname\n")); 3973 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3974 3975 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3976 sc->ethercom.ec_if.if_capabilities |= 3977 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3978 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3979 sc->ethercom.ec_if.if_capabilities |= 3980 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3981 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3982 #endif 3983 sc->ethercom.ec_capabilities |= 3984 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3985 3986 if (sc->bge_flags & BGEF_TSO) 3987 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3988 3989 /* 3990 * Do MII setup. 3991 */ 3992 DPRINTFN(5, ("mii setup\n")); 3993 sc->bge_mii.mii_ifp = ifp; 3994 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3995 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3996 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3997 3998 /* 3999 * Figure out what sort of media we have by checking the hardware 4000 * config word. Note: on some BCM5700 cards, this value appears to be 4001 * unset. If that's the case, we have to rely on identifying the NIC 4002 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 4003 * The SysKonnect SK-9D41 is a 1000baseSX card. 4004 */ 4005 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 4006 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 4007 if (BGE_IS_5705_PLUS(sc)) { 4008 sc->bge_flags |= BGEF_FIBER_MII; 4009 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 4010 } else 4011 sc->bge_flags |= BGEF_FIBER_TBI; 4012 } 4013 4014 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 4015 if (BGE_IS_JUMBO_CAPABLE(sc)) 4016 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 4017 4018 /* set phyflags and chipid before mii_attach() */ 4019 dict = device_properties(self); 4020 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 4021 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 4022 4023 if (sc->bge_flags & BGEF_FIBER_TBI) { 4024 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 4025 bge_ifmedia_sts); 4026 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 4027 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 4028 0, NULL); 4029 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 4030 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 4031 /* Pretend the user requested this setting */ 4032 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 4033 } else { 4034 /* 4035 * Do transceiver setup and tell the firmware the 4036 * driver is down so we can try to get access the 4037 * probe if ASF is running. Retry a couple of times 4038 * if we get a conflict with the ASF firmware accessing 4039 * the PHY. 4040 */ 4041 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4042 bge_asf_driver_up(sc); 4043 4044 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 4045 bge_ifmedia_sts); 4046 mii_flags = MIIF_DOPAUSE; 4047 if (sc->bge_flags & BGEF_FIBER_MII) 4048 mii_flags |= MIIF_HAVEFIBER; 4049 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 4050 MII_OFFSET_ANY, mii_flags); 4051 4052 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 4053 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4054 ifmedia_add(&sc->bge_mii.mii_media, 4055 IFM_ETHER|IFM_MANUAL, 0, NULL); 4056 ifmedia_set(&sc->bge_mii.mii_media, 4057 IFM_ETHER|IFM_MANUAL); 4058 } else 4059 ifmedia_set(&sc->bge_mii.mii_media, 4060 IFM_ETHER|IFM_AUTO); 4061 4062 /* 4063 * Now tell the firmware we are going up after probing the PHY 4064 */ 4065 if (sc->bge_asf_mode & ASF_STACKUP) 4066 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4067 } 4068 4069 /* 4070 * Call MI attach routine. 4071 */ 4072 DPRINTFN(5, ("if_attach\n")); 4073 if_attach(ifp); 4074 if_deferred_start_init(ifp, NULL); 4075 DPRINTFN(5, ("ether_ifattach\n")); 4076 ether_ifattach(ifp, eaddr); 4077 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4078 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4079 RND_TYPE_NET, RND_FLAG_DEFAULT); 4080 #ifdef BGE_EVENT_COUNTERS 4081 /* 4082 * Attach event counters. 4083 */ 4084 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4085 NULL, device_xname(sc->bge_dev), "intr"); 4086 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4087 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4088 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4089 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4090 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4091 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4092 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4093 NULL, device_xname(sc->bge_dev), "tx_xon"); 4094 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4095 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4096 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4097 NULL, device_xname(sc->bge_dev), "rx_xon"); 4098 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4099 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4100 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4101 NULL, device_xname(sc->bge_dev), "xoffentered"); 4102 #endif /* BGE_EVENT_COUNTERS */ 4103 DPRINTFN(5, ("callout_init\n")); 4104 callout_init(&sc->bge_timeout, 0); 4105 4106 if (pmf_device_register(self, NULL, NULL)) 4107 pmf_class_network_register(self, ifp); 4108 else 4109 aprint_error_dev(self, "couldn't establish power handler\n"); 4110 4111 bge_sysctl_init(sc); 4112 4113 #ifdef BGE_DEBUG 4114 bge_debug_info(sc); 4115 #endif 4116 } 4117 4118 /* 4119 * Stop all chip I/O so that the kernel's probe routines don't 4120 * get confused by errant DMAs when rebooting. 4121 */ 4122 static int 4123 bge_detach(device_t self, int flags __unused) 4124 { 4125 struct bge_softc *sc = device_private(self); 4126 struct ifnet *ifp = &sc->ethercom.ec_if; 4127 int s; 4128 4129 s = splnet(); 4130 /* Stop the interface. Callouts are stopped in it. */ 4131 bge_stop(ifp, 1); 4132 splx(s); 4133 4134 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4135 4136 /* Delete all remaining media. */ 4137 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4138 4139 ether_ifdetach(ifp); 4140 if_detach(ifp); 4141 4142 bge_release_resources(sc); 4143 4144 return 0; 4145 } 4146 4147 static void 4148 bge_release_resources(struct bge_softc *sc) 4149 { 4150 4151 /* Detach sysctl */ 4152 if (sc->bge_log != NULL) 4153 sysctl_teardown(&sc->bge_log); 4154 4155 #ifdef BGE_EVENT_COUNTERS 4156 /* Detach event counters. */ 4157 evcnt_detach(&sc->bge_ev_intr); 4158 evcnt_detach(&sc->bge_ev_intr_spurious); 4159 evcnt_detach(&sc->bge_ev_intr_spurious2); 4160 evcnt_detach(&sc->bge_ev_tx_xoff); 4161 evcnt_detach(&sc->bge_ev_tx_xon); 4162 evcnt_detach(&sc->bge_ev_rx_xoff); 4163 evcnt_detach(&sc->bge_ev_rx_xon); 4164 evcnt_detach(&sc->bge_ev_rx_macctl); 4165 evcnt_detach(&sc->bge_ev_xoffentered); 4166 #endif /* BGE_EVENT_COUNTERS */ 4167 4168 /* Disestablish the interrupt handler */ 4169 if (sc->bge_intrhand != NULL) { 4170 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4171 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4172 sc->bge_intrhand = NULL; 4173 } 4174 4175 if (sc->bge_dmatag != NULL) { 4176 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4177 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4178 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4179 sizeof(struct bge_ring_data)); 4180 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4181 sc->bge_ring_rseg); 4182 } 4183 4184 /* Unmap the device registers */ 4185 if (sc->bge_bsize != 0) { 4186 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4187 sc->bge_bsize = 0; 4188 } 4189 4190 /* Unmap the APE registers */ 4191 if (sc->bge_apesize != 0) { 4192 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4193 sc->bge_apesize); 4194 sc->bge_apesize = 0; 4195 } 4196 } 4197 4198 static int 4199 bge_reset(struct bge_softc *sc) 4200 { 4201 uint32_t cachesize, command; 4202 uint32_t reset, mac_mode, mac_mode_mask; 4203 pcireg_t devctl, reg; 4204 int i, val; 4205 void (*write_op)(struct bge_softc *, int, int); 4206 4207 /* Make mask for BGE_MAC_MODE register. */ 4208 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4209 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4210 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4211 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4212 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4213 4214 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4215 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4216 if (sc->bge_flags & BGEF_PCIE) 4217 write_op = bge_writemem_direct; 4218 else 4219 write_op = bge_writemem_ind; 4220 } else 4221 write_op = bge_writereg_ind; 4222 4223 /* 57XX step 4 */ 4224 /* Acquire the NVM lock */ 4225 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4226 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4227 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4228 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4229 for (i = 0; i < 8000; i++) { 4230 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4231 BGE_NVRAMSWARB_GNT1) 4232 break; 4233 DELAY(20); 4234 } 4235 if (i == 8000) { 4236 printf("%s: NVRAM lock timedout!\n", 4237 device_xname(sc->bge_dev)); 4238 } 4239 } 4240 4241 /* Take APE lock when performing reset. */ 4242 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4243 4244 /* 57XX step 3 */ 4245 /* Save some important PCI state. */ 4246 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4247 /* 5718 reset step 3 */ 4248 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4249 4250 /* 5718 reset step 5, 57XX step 5b-5d */ 4251 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4252 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4253 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4254 4255 /* XXX ???: Disable fastboot on controllers that support it. */ 4256 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4257 BGE_IS_5755_PLUS(sc)) 4258 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4259 4260 /* 5718 reset step 2, 57XX step 6 */ 4261 /* 4262 * Write the magic number to SRAM at offset 0xB50. 4263 * When firmware finishes its initialization it will 4264 * write ~BGE_MAGIC_NUMBER to the same location. 4265 */ 4266 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4267 4268 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4269 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4270 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4271 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4272 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4273 } 4274 4275 /* 5718 reset step 6, 57XX step 7 */ 4276 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4277 /* 4278 * XXX: from FreeBSD/Linux; no documentation 4279 */ 4280 if (sc->bge_flags & BGEF_PCIE) { 4281 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4282 !BGE_IS_57765_PLUS(sc) && 4283 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4284 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4285 /* PCI Express 1.0 system */ 4286 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4287 BGE_PHY_PCIE_SCRAM_MODE); 4288 } 4289 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4290 /* 4291 * Prevent PCI Express link training 4292 * during global reset. 4293 */ 4294 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4295 reset |= (1 << 29); 4296 } 4297 } 4298 4299 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4300 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4301 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4302 i | BGE_VCPU_STATUS_DRV_RESET); 4303 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4304 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4305 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4306 } 4307 4308 /* 4309 * Set GPHY Power Down Override to leave GPHY 4310 * powered up in D0 uninitialized. 4311 */ 4312 if (BGE_IS_5705_PLUS(sc) && 4313 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4314 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4315 4316 /* Issue global reset */ 4317 write_op(sc, BGE_MISC_CFG, reset); 4318 4319 /* 5718 reset step 7, 57XX step 8 */ 4320 if (sc->bge_flags & BGEF_PCIE) 4321 delay(100*1000); /* too big */ 4322 else 4323 delay(1000); 4324 4325 if (sc->bge_flags & BGEF_PCIE) { 4326 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4327 DELAY(500000); 4328 /* XXX: Magic Numbers */ 4329 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4330 BGE_PCI_UNKNOWN0); 4331 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4332 BGE_PCI_UNKNOWN0, 4333 reg | (1 << 15)); 4334 } 4335 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4336 sc->bge_pciecap + PCIE_DCSR); 4337 /* Clear enable no snoop and disable relaxed ordering. */ 4338 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4339 PCIE_DCSR_ENA_NO_SNOOP); 4340 4341 /* Set PCIE max payload size to 128 for older PCIe devices */ 4342 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4343 devctl &= ~(0x00e0); 4344 /* Clear device status register. Write 1b to clear */ 4345 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4346 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4347 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4348 sc->bge_pciecap + PCIE_DCSR, devctl); 4349 bge_set_max_readrq(sc); 4350 } 4351 4352 /* From Linux: dummy read to flush PCI posted writes */ 4353 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4354 4355 /* 4356 * Reset some of the PCI state that got zapped by reset 4357 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4358 * set, too. 4359 */ 4360 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4361 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4362 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4363 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4364 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4365 (sc->bge_flags & BGEF_PCIX) != 0) 4366 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4367 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4368 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4369 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4370 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4371 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4372 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4373 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4374 4375 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4376 if (sc->bge_flags & BGEF_PCIX) { 4377 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4378 + PCIX_CMD); 4379 /* Set max memory read byte count to 2K */ 4380 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4381 reg &= ~PCIX_CMD_BYTECNT_MASK; 4382 reg |= PCIX_CMD_BCNT_2048; 4383 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4384 /* 4385 * For 5704, set max outstanding split transaction 4386 * field to 0 (0 means it supports 1 request) 4387 */ 4388 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4389 | PCIX_CMD_BYTECNT_MASK); 4390 reg |= PCIX_CMD_BCNT_2048; 4391 } 4392 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4393 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4394 } 4395 4396 /* 5718 reset step 10, 57XX step 12 */ 4397 /* Enable memory arbiter. */ 4398 if (BGE_IS_5714_FAMILY(sc)) { 4399 val = CSR_READ_4(sc, BGE_MARB_MODE); 4400 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4401 } else 4402 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4403 4404 /* XXX 5721, 5751 and 5752 */ 4405 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4406 /* Step 19: */ 4407 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4408 /* Step 20: */ 4409 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4410 } 4411 4412 /* 5718 reset step 12, 57XX step 15 and 16 */ 4413 /* Fix up byte swapping */ 4414 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4415 4416 /* 5718 reset step 13, 57XX step 17 */ 4417 /* Poll until the firmware initialization is complete */ 4418 bge_poll_fw(sc); 4419 4420 /* 57XX step 21 */ 4421 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4422 pcireg_t msidata; 4423 4424 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4425 BGE_PCI_MSI_DATA); 4426 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4427 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4428 msidata); 4429 } 4430 4431 /* 57XX step 18 */ 4432 /* Write mac mode. */ 4433 val = CSR_READ_4(sc, BGE_MAC_MODE); 4434 /* Restore mac_mode_mask's bits using mac_mode */ 4435 val = (val & ~mac_mode_mask) | mac_mode; 4436 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4437 DELAY(40); 4438 4439 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4440 4441 /* 4442 * The 5704 in TBI mode apparently needs some special 4443 * adjustment to insure the SERDES drive level is set 4444 * to 1.2V. 4445 */ 4446 if (sc->bge_flags & BGEF_FIBER_TBI && 4447 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4448 uint32_t serdescfg; 4449 4450 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4451 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4452 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4453 } 4454 4455 if (sc->bge_flags & BGEF_PCIE && 4456 !BGE_IS_57765_PLUS(sc) && 4457 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4458 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4459 uint32_t v; 4460 4461 /* Enable PCI Express bug fix */ 4462 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4463 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4464 v | BGE_TLP_DATA_FIFO_PROTECT); 4465 } 4466 4467 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4468 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4469 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4470 4471 return 0; 4472 } 4473 4474 /* 4475 * Frame reception handling. This is called if there's a frame 4476 * on the receive return list. 4477 * 4478 * Note: we have to be able to handle two possibilities here: 4479 * 1) the frame is from the jumbo receive ring 4480 * 2) the frame is from the standard receive ring 4481 */ 4482 4483 static void 4484 bge_rxeof(struct bge_softc *sc) 4485 { 4486 struct ifnet *ifp; 4487 uint16_t rx_prod, rx_cons; 4488 int stdcnt = 0, jumbocnt = 0; 4489 bus_dmamap_t dmamap; 4490 bus_addr_t offset, toff; 4491 bus_size_t tlen; 4492 int tosync; 4493 4494 rx_cons = sc->bge_rx_saved_considx; 4495 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4496 4497 /* Nothing to do */ 4498 if (rx_cons == rx_prod) 4499 return; 4500 4501 ifp = &sc->ethercom.ec_if; 4502 4503 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4504 offsetof(struct bge_ring_data, bge_status_block), 4505 sizeof (struct bge_status_block), 4506 BUS_DMASYNC_POSTREAD); 4507 4508 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4509 tosync = rx_prod - rx_cons; 4510 4511 if (tosync != 0) 4512 rnd_add_uint32(&sc->rnd_source, tosync); 4513 4514 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4515 4516 if (tosync < 0) { 4517 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4518 sizeof (struct bge_rx_bd); 4519 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4520 toff, tlen, BUS_DMASYNC_POSTREAD); 4521 tosync = -tosync; 4522 } 4523 4524 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4525 offset, tosync * sizeof (struct bge_rx_bd), 4526 BUS_DMASYNC_POSTREAD); 4527 4528 while (rx_cons != rx_prod) { 4529 struct bge_rx_bd *cur_rx; 4530 uint32_t rxidx; 4531 struct mbuf *m = NULL; 4532 4533 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4534 4535 rxidx = cur_rx->bge_idx; 4536 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4537 4538 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4539 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4540 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4541 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4542 jumbocnt++; 4543 bus_dmamap_sync(sc->bge_dmatag, 4544 sc->bge_cdata.bge_rx_jumbo_map, 4545 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4546 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4547 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4548 ifp->if_ierrors++; 4549 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4550 continue; 4551 } 4552 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4553 NULL)== ENOBUFS) { 4554 ifp->if_ierrors++; 4555 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4556 continue; 4557 } 4558 } else { 4559 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4560 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4561 4562 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4563 stdcnt++; 4564 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4565 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4566 if (dmamap == NULL) { 4567 ifp->if_ierrors++; 4568 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4569 continue; 4570 } 4571 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4572 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4573 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4574 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4575 ifp->if_ierrors++; 4576 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4577 continue; 4578 } 4579 if (bge_newbuf_std(sc, sc->bge_std, 4580 NULL, dmamap) == ENOBUFS) { 4581 ifp->if_ierrors++; 4582 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4583 continue; 4584 } 4585 } 4586 4587 #ifndef __NO_STRICT_ALIGNMENT 4588 /* 4589 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4590 * the Rx buffer has the layer-2 header unaligned. 4591 * If our CPU requires alignment, re-align by copying. 4592 */ 4593 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4594 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4595 cur_rx->bge_len); 4596 m->m_data += ETHER_ALIGN; 4597 } 4598 #endif 4599 4600 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4601 m_set_rcvif(m, ifp); 4602 4603 bge_rxcsum(sc, cur_rx, m); 4604 4605 /* 4606 * If we received a packet with a vlan tag, pass it 4607 * to vlan_input() instead of ether_input(). 4608 */ 4609 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4610 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4611 } 4612 4613 if_percpuq_enqueue(ifp->if_percpuq, m); 4614 } 4615 4616 sc->bge_rx_saved_considx = rx_cons; 4617 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4618 if (stdcnt) 4619 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4620 if (jumbocnt) 4621 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4622 } 4623 4624 static void 4625 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4626 { 4627 4628 if (BGE_IS_57765_PLUS(sc)) { 4629 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4630 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4631 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4632 if ((cur_rx->bge_error_flag & 4633 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4634 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4635 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4636 m->m_pkthdr.csum_data = 4637 cur_rx->bge_tcp_udp_csum; 4638 m->m_pkthdr.csum_flags |= 4639 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4640 M_CSUM_DATA); 4641 } 4642 } 4643 } else { 4644 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4645 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4646 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4647 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4648 /* 4649 * Rx transport checksum-offload may also 4650 * have bugs with packets which, when transmitted, 4651 * were `runts' requiring padding. 4652 */ 4653 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4654 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4655 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4656 m->m_pkthdr.csum_data = 4657 cur_rx->bge_tcp_udp_csum; 4658 m->m_pkthdr.csum_flags |= 4659 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4660 M_CSUM_DATA); 4661 } 4662 } 4663 } 4664 4665 static void 4666 bge_txeof(struct bge_softc *sc) 4667 { 4668 struct bge_tx_bd *cur_tx = NULL; 4669 struct ifnet *ifp; 4670 struct txdmamap_pool_entry *dma; 4671 bus_addr_t offset, toff; 4672 bus_size_t tlen; 4673 int tosync; 4674 struct mbuf *m; 4675 4676 ifp = &sc->ethercom.ec_if; 4677 4678 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4679 offsetof(struct bge_ring_data, bge_status_block), 4680 sizeof (struct bge_status_block), 4681 BUS_DMASYNC_POSTREAD); 4682 4683 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4684 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4685 sc->bge_tx_saved_considx; 4686 4687 if (tosync != 0) 4688 rnd_add_uint32(&sc->rnd_source, tosync); 4689 4690 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4691 4692 if (tosync < 0) { 4693 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4694 sizeof (struct bge_tx_bd); 4695 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4696 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4697 tosync = -tosync; 4698 } 4699 4700 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4701 offset, tosync * sizeof (struct bge_tx_bd), 4702 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4703 4704 /* 4705 * Go through our tx ring and free mbufs for those 4706 * frames that have been sent. 4707 */ 4708 while (sc->bge_tx_saved_considx != 4709 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4710 uint32_t idx = 0; 4711 4712 idx = sc->bge_tx_saved_considx; 4713 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4714 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4715 ifp->if_opackets++; 4716 m = sc->bge_cdata.bge_tx_chain[idx]; 4717 if (m != NULL) { 4718 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4719 dma = sc->txdma[idx]; 4720 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 4721 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4722 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4723 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4724 sc->txdma[idx] = NULL; 4725 4726 m_freem(m); 4727 } 4728 sc->bge_txcnt--; 4729 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4730 ifp->if_timer = 0; 4731 } 4732 4733 if (cur_tx != NULL) 4734 ifp->if_flags &= ~IFF_OACTIVE; 4735 } 4736 4737 static int 4738 bge_intr(void *xsc) 4739 { 4740 struct bge_softc *sc; 4741 struct ifnet *ifp; 4742 uint32_t pcistate, statusword, statustag; 4743 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4744 4745 sc = xsc; 4746 ifp = &sc->ethercom.ec_if; 4747 4748 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4749 if (BGE_IS_5717_PLUS(sc)) 4750 intrmask = 0; 4751 4752 /* It is possible for the interrupt to arrive before 4753 * the status block is updated prior to the interrupt. 4754 * Reading the PCI State register will confirm whether the 4755 * interrupt is ours and will flush the status block. 4756 */ 4757 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4758 4759 /* read status word from status block */ 4760 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4761 offsetof(struct bge_ring_data, bge_status_block), 4762 sizeof (struct bge_status_block), 4763 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4764 statusword = sc->bge_rdata->bge_status_block.bge_status; 4765 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4766 4767 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4768 if (sc->bge_lasttag == statustag && 4769 (~pcistate & intrmask)) { 4770 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4771 return (0); 4772 } 4773 sc->bge_lasttag = statustag; 4774 } else { 4775 if (!(statusword & BGE_STATFLAG_UPDATED) && 4776 !(~pcistate & intrmask)) { 4777 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4778 return (0); 4779 } 4780 statustag = 0; 4781 } 4782 /* Ack interrupt and stop others from occurring. */ 4783 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4784 BGE_EVCNT_INCR(sc->bge_ev_intr); 4785 4786 /* clear status word */ 4787 sc->bge_rdata->bge_status_block.bge_status = 0; 4788 4789 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4790 offsetof(struct bge_ring_data, bge_status_block), 4791 sizeof (struct bge_status_block), 4792 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4793 4794 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4795 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4796 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4797 bge_link_upd(sc); 4798 4799 if (ifp->if_flags & IFF_RUNNING) { 4800 /* Check RX return ring producer/consumer */ 4801 bge_rxeof(sc); 4802 4803 /* Check TX ring producer/consumer */ 4804 bge_txeof(sc); 4805 } 4806 4807 if (sc->bge_pending_rxintr_change) { 4808 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4809 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4810 4811 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4812 DELAY(10); 4813 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4814 4815 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4816 DELAY(10); 4817 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4818 4819 sc->bge_pending_rxintr_change = 0; 4820 } 4821 bge_handle_events(sc); 4822 4823 /* Re-enable interrupts. */ 4824 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4825 4826 if (ifp->if_flags & IFF_RUNNING) 4827 if_schedule_deferred_start(ifp); 4828 4829 return 1; 4830 } 4831 4832 static void 4833 bge_asf_driver_up(struct bge_softc *sc) 4834 { 4835 if (sc->bge_asf_mode & ASF_STACKUP) { 4836 /* Send ASF heartbeat aprox. every 2s */ 4837 if (sc->bge_asf_count) 4838 sc->bge_asf_count --; 4839 else { 4840 sc->bge_asf_count = 2; 4841 4842 bge_wait_for_event_ack(sc); 4843 4844 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4845 BGE_FW_CMD_DRV_ALIVE3); 4846 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4847 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4848 BGE_FW_HB_TIMEOUT_SEC); 4849 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4850 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4851 BGE_RX_CPU_DRV_EVENT); 4852 } 4853 } 4854 } 4855 4856 static void 4857 bge_tick(void *xsc) 4858 { 4859 struct bge_softc *sc = xsc; 4860 struct mii_data *mii = &sc->bge_mii; 4861 int s; 4862 4863 s = splnet(); 4864 4865 if (BGE_IS_5705_PLUS(sc)) 4866 bge_stats_update_regs(sc); 4867 else 4868 bge_stats_update(sc); 4869 4870 if (sc->bge_flags & BGEF_FIBER_TBI) { 4871 /* 4872 * Since in TBI mode auto-polling can't be used we should poll 4873 * link status manually. Here we register pending link event 4874 * and trigger interrupt. 4875 */ 4876 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4877 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4878 } else { 4879 /* 4880 * Do not touch PHY if we have link up. This could break 4881 * IPMI/ASF mode or produce extra input errors. 4882 * (extra input errors was reported for bcm5701 & bcm5704). 4883 */ 4884 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4885 mii_tick(mii); 4886 } 4887 4888 bge_asf_driver_up(sc); 4889 4890 if (!sc->bge_detaching) 4891 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4892 4893 splx(s); 4894 } 4895 4896 static void 4897 bge_stats_update_regs(struct bge_softc *sc) 4898 { 4899 struct ifnet *ifp = &sc->ethercom.ec_if; 4900 4901 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4902 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4903 4904 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4905 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4906 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4907 } 4908 4909 static void 4910 bge_stats_update(struct bge_softc *sc) 4911 { 4912 struct ifnet *ifp = &sc->ethercom.ec_if; 4913 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4914 4915 #define READ_STAT(sc, stats, stat) \ 4916 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4917 4918 ifp->if_collisions += 4919 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4920 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4921 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4922 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4923 ifp->if_collisions; 4924 4925 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4926 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4927 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4928 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4929 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4930 READ_STAT(sc, stats, 4931 xoffPauseFramesReceived.bge_addr_lo)); 4932 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4933 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4934 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4935 READ_STAT(sc, stats, 4936 macControlFramesReceived.bge_addr_lo)); 4937 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4938 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4939 4940 #undef READ_STAT 4941 4942 #ifdef notdef 4943 ifp->if_collisions += 4944 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4945 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4946 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4947 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4948 ifp->if_collisions; 4949 #endif 4950 } 4951 4952 /* 4953 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4954 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4955 * but when such padded frames employ the bge IP/TCP checksum offload, 4956 * the hardware checksum assist gives incorrect results (possibly 4957 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4958 * If we pad such runts with zeros, the onboard checksum comes out correct. 4959 */ 4960 static inline int 4961 bge_cksum_pad(struct mbuf *pkt) 4962 { 4963 struct mbuf *last = NULL; 4964 int padlen; 4965 4966 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4967 4968 /* if there's only the packet-header and we can pad there, use it. */ 4969 if (pkt->m_pkthdr.len == pkt->m_len && 4970 M_TRAILINGSPACE(pkt) >= padlen) { 4971 last = pkt; 4972 } else { 4973 /* 4974 * Walk packet chain to find last mbuf. We will either 4975 * pad there, or append a new mbuf and pad it 4976 * (thus perhaps avoiding the bcm5700 dma-min bug). 4977 */ 4978 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4979 continue; /* do nothing */ 4980 } 4981 4982 /* `last' now points to last in chain. */ 4983 if (M_TRAILINGSPACE(last) < padlen) { 4984 /* Allocate new empty mbuf, pad it. Compact later. */ 4985 struct mbuf *n; 4986 MGET(n, M_DONTWAIT, MT_DATA); 4987 if (n == NULL) 4988 return ENOBUFS; 4989 n->m_len = 0; 4990 last->m_next = n; 4991 last = n; 4992 } 4993 } 4994 4995 KDASSERT(!M_READONLY(last)); 4996 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4997 4998 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4999 memset(mtod(last, char *) + last->m_len, 0, padlen); 5000 last->m_len += padlen; 5001 pkt->m_pkthdr.len += padlen; 5002 return 0; 5003 } 5004 5005 /* 5006 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5007 */ 5008 static inline int 5009 bge_compact_dma_runt(struct mbuf *pkt) 5010 { 5011 struct mbuf *m, *prev; 5012 int totlen; 5013 5014 prev = NULL; 5015 totlen = 0; 5016 5017 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 5018 int mlen = m->m_len; 5019 int shortfall = 8 - mlen ; 5020 5021 totlen += mlen; 5022 if (mlen == 0) 5023 continue; 5024 if (mlen >= 8) 5025 continue; 5026 5027 /* If we get here, mbuf data is too small for DMA engine. 5028 * Try to fix by shuffling data to prev or next in chain. 5029 * If that fails, do a compacting deep-copy of the whole chain. 5030 */ 5031 5032 /* Internal frag. If fits in prev, copy it there. */ 5033 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5034 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5035 prev->m_len += mlen; 5036 m->m_len = 0; 5037 /* XXX stitch chain */ 5038 prev->m_next = m_free(m); 5039 m = prev; 5040 continue; 5041 } 5042 else if (m->m_next != NULL && 5043 M_TRAILINGSPACE(m) >= shortfall && 5044 m->m_next->m_len >= (8 + shortfall)) { 5045 /* m is writable and have enough data in next, pull up. */ 5046 5047 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5048 shortfall); 5049 m->m_len += shortfall; 5050 m->m_next->m_len -= shortfall; 5051 m->m_next->m_data += shortfall; 5052 } 5053 else if (m->m_next == NULL || 1) { 5054 /* Got a runt at the very end of the packet. 5055 * borrow data from the tail of the preceding mbuf and 5056 * update its length in-place. (The original data is still 5057 * valid, so we can do this even if prev is not writable.) 5058 */ 5059 5060 /* if we'd make prev a runt, just move all of its data. */ 5061 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5062 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5063 5064 if ((prev->m_len - shortfall) < 8) 5065 shortfall = prev->m_len; 5066 5067 #ifdef notyet /* just do the safe slow thing for now */ 5068 if (!M_READONLY(m)) { 5069 if (M_LEADINGSPACE(m) < shorfall) { 5070 void *m_dat; 5071 m_dat = (m->m_flags & M_PKTHDR) ? 5072 m->m_pktdat : m->dat; 5073 memmove(m_dat, mtod(m, void*), m->m_len); 5074 m->m_data = m_dat; 5075 } 5076 } else 5077 #endif /* just do the safe slow thing */ 5078 { 5079 struct mbuf * n = NULL; 5080 int newprevlen = prev->m_len - shortfall; 5081 5082 MGET(n, M_NOWAIT, MT_DATA); 5083 if (n == NULL) 5084 return ENOBUFS; 5085 KASSERT(m->m_len + shortfall < MLEN 5086 /*, 5087 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5088 5089 /* first copy the data we're stealing from prev */ 5090 memcpy(n->m_data, prev->m_data + newprevlen, 5091 shortfall); 5092 5093 /* update prev->m_len accordingly */ 5094 prev->m_len -= shortfall; 5095 5096 /* copy data from runt m */ 5097 memcpy(n->m_data + shortfall, m->m_data, 5098 m->m_len); 5099 5100 /* n holds what we stole from prev, plus m */ 5101 n->m_len = shortfall + m->m_len; 5102 5103 /* stitch n into chain and free m */ 5104 n->m_next = m->m_next; 5105 prev->m_next = n; 5106 /* KASSERT(m->m_next == NULL); */ 5107 m->m_next = NULL; 5108 m_free(m); 5109 m = n; /* for continuing loop */ 5110 } 5111 } 5112 } 5113 return 0; 5114 } 5115 5116 /* 5117 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5118 * pointers to descriptors. 5119 */ 5120 static int 5121 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5122 { 5123 struct bge_tx_bd *f = NULL; 5124 uint32_t frag, cur; 5125 uint16_t csum_flags = 0; 5126 uint16_t txbd_tso_flags = 0; 5127 struct txdmamap_pool_entry *dma; 5128 bus_dmamap_t dmamap; 5129 int i = 0; 5130 int use_tso, maxsegsize, error; 5131 bool have_vtag; 5132 uint16_t vtag; 5133 5134 cur = frag = *txidx; 5135 5136 if (m_head->m_pkthdr.csum_flags) { 5137 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5138 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5139 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 5140 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5141 } 5142 5143 /* 5144 * If we were asked to do an outboard checksum, and the NIC 5145 * has the bug where it sometimes adds in the Ethernet padding, 5146 * explicitly pad with zeros so the cksum will be correct either way. 5147 * (For now, do this for all chip versions, until newer 5148 * are confirmed to not require the workaround.) 5149 */ 5150 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5151 #ifdef notyet 5152 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5153 #endif 5154 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5155 goto check_dma_bug; 5156 5157 if (bge_cksum_pad(m_head) != 0) 5158 return ENOBUFS; 5159 5160 check_dma_bug: 5161 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5162 goto doit; 5163 5164 /* 5165 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5166 * less than eight bytes. If we encounter a teeny mbuf 5167 * at the end of a chain, we can pad. Otherwise, copy. 5168 */ 5169 if (bge_compact_dma_runt(m_head) != 0) 5170 return ENOBUFS; 5171 5172 doit: 5173 dma = SLIST_FIRST(&sc->txdma_list); 5174 if (dma == NULL) 5175 return ENOBUFS; 5176 dmamap = dma->dmamap; 5177 5178 /* 5179 * Set up any necessary TSO state before we start packing... 5180 */ 5181 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5182 if (!use_tso) { 5183 maxsegsize = 0; 5184 } else { /* TSO setup */ 5185 unsigned mss; 5186 struct ether_header *eh; 5187 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5188 struct mbuf * m0 = m_head; 5189 struct ip *ip; 5190 struct tcphdr *th; 5191 int iphl, hlen; 5192 5193 /* 5194 * XXX It would be nice if the mbuf pkthdr had offset 5195 * fields for the protocol headers. 5196 */ 5197 5198 eh = mtod(m0, struct ether_header *); 5199 switch (htons(eh->ether_type)) { 5200 case ETHERTYPE_IP: 5201 offset = ETHER_HDR_LEN; 5202 break; 5203 5204 case ETHERTYPE_VLAN: 5205 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5206 break; 5207 5208 default: 5209 /* 5210 * Don't support this protocol or encapsulation. 5211 */ 5212 return ENOBUFS; 5213 } 5214 5215 /* 5216 * TCP/IP headers are in the first mbuf; we can do 5217 * this the easy way. 5218 */ 5219 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5220 hlen = iphl + offset; 5221 if (__predict_false(m0->m_len < 5222 (hlen + sizeof(struct tcphdr)))) { 5223 5224 aprint_debug_dev(sc->bge_dev, 5225 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5226 "not handled yet\n", 5227 m0->m_len, hlen+ sizeof(struct tcphdr)); 5228 #ifdef NOTYET 5229 /* 5230 * XXX jonathan (at) NetBSD.org: untested. 5231 * how to force this branch to be taken? 5232 */ 5233 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5234 5235 m_copydata(m0, offset, sizeof(ip), &ip); 5236 m_copydata(m0, hlen, sizeof(th), &th); 5237 5238 ip.ip_len = 0; 5239 5240 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5241 sizeof(ip.ip_len), &ip.ip_len); 5242 5243 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5244 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5245 5246 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5247 sizeof(th.th_sum), &th.th_sum); 5248 5249 hlen += th.th_off << 2; 5250 iptcp_opt_words = hlen; 5251 #else 5252 /* 5253 * if_wm "hard" case not yet supported, can we not 5254 * mandate it out of existence? 5255 */ 5256 (void) ip; (void)th; (void) ip_tcp_hlen; 5257 5258 return ENOBUFS; 5259 #endif 5260 } else { 5261 ip = (struct ip *) (mtod(m0, char *) + offset); 5262 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5263 ip_tcp_hlen = iphl + (th->th_off << 2); 5264 5265 /* Total IP/TCP options, in 32-bit words */ 5266 iptcp_opt_words = (ip_tcp_hlen 5267 - sizeof(struct tcphdr) 5268 - sizeof(struct ip)) >> 2; 5269 } 5270 if (BGE_IS_575X_PLUS(sc)) { 5271 th->th_sum = 0; 5272 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 5273 } else { 5274 /* 5275 * XXX jonathan (at) NetBSD.org: 5705 untested. 5276 * Requires TSO firmware patch for 5701/5703/5704. 5277 */ 5278 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5279 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5280 } 5281 5282 mss = m_head->m_pkthdr.segsz; 5283 txbd_tso_flags |= 5284 BGE_TXBDFLAG_CPU_PRE_DMA | 5285 BGE_TXBDFLAG_CPU_POST_DMA; 5286 5287 /* 5288 * Our NIC TSO-assist assumes TSO has standard, optionless 5289 * IPv4 and TCP headers, which total 40 bytes. By default, 5290 * the NIC copies 40 bytes of IP/TCP header from the 5291 * supplied header into the IP/TCP header portion of 5292 * each post-TSO-segment. If the supplied packet has IP or 5293 * TCP options, we need to tell the NIC to copy those extra 5294 * bytes into each post-TSO header, in addition to the normal 5295 * 40-byte IP/TCP header (and to leave space accordingly). 5296 * Unfortunately, the driver encoding of option length 5297 * varies across different ASIC families. 5298 */ 5299 tcp_seg_flags = 0; 5300 if (iptcp_opt_words) { 5301 if (BGE_IS_5705_PLUS(sc)) { 5302 tcp_seg_flags = 5303 iptcp_opt_words << 11; 5304 } else { 5305 txbd_tso_flags |= 5306 iptcp_opt_words << 12; 5307 } 5308 } 5309 maxsegsize = mss | tcp_seg_flags; 5310 ip->ip_len = htons(mss + ip_tcp_hlen); 5311 5312 } /* TSO setup */ 5313 5314 /* 5315 * Start packing the mbufs in this chain into 5316 * the fragment pointers. Stop when we run out 5317 * of fragments or hit the end of the mbuf chain. 5318 */ 5319 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 5320 BUS_DMA_NOWAIT); 5321 if (error) 5322 return ENOBUFS; 5323 /* 5324 * Sanity check: avoid coming within 16 descriptors 5325 * of the end of the ring. 5326 */ 5327 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5328 BGE_TSO_PRINTF(("%s: " 5329 " dmamap_load_mbuf too close to ring wrap\n", 5330 device_xname(sc->bge_dev))); 5331 goto fail_unload; 5332 } 5333 5334 have_vtag = vlan_has_tag(m_head); 5335 if (have_vtag) 5336 vtag = vlan_get_tag(m_head); 5337 5338 /* Iterate over dmap-map fragments. */ 5339 for (i = 0; i < dmamap->dm_nsegs; i++) { 5340 f = &sc->bge_rdata->bge_tx_ring[frag]; 5341 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5342 break; 5343 5344 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5345 f->bge_len = dmamap->dm_segs[i].ds_len; 5346 5347 /* 5348 * For 5751 and follow-ons, for TSO we must turn 5349 * off checksum-assist flag in the tx-descr, and 5350 * supply the ASIC-revision-specific encoding 5351 * of TSO flags and segsize. 5352 */ 5353 if (use_tso) { 5354 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5355 f->bge_rsvd = maxsegsize; 5356 f->bge_flags = csum_flags | txbd_tso_flags; 5357 } else { 5358 f->bge_rsvd = 0; 5359 f->bge_flags = 5360 (csum_flags | txbd_tso_flags) & 0x0fff; 5361 } 5362 } else { 5363 f->bge_rsvd = 0; 5364 f->bge_flags = csum_flags; 5365 } 5366 5367 if (have_vtag) { 5368 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5369 f->bge_vlan_tag = vtag; 5370 } else { 5371 f->bge_vlan_tag = 0; 5372 } 5373 cur = frag; 5374 BGE_INC(frag, BGE_TX_RING_CNT); 5375 } 5376 5377 if (i < dmamap->dm_nsegs) { 5378 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5379 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5380 goto fail_unload; 5381 } 5382 5383 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 5384 BUS_DMASYNC_PREWRITE); 5385 5386 if (frag == sc->bge_tx_saved_considx) { 5387 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5388 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5389 5390 goto fail_unload; 5391 } 5392 5393 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5394 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5395 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5396 sc->txdma[cur] = dma; 5397 sc->bge_txcnt += dmamap->dm_nsegs; 5398 5399 *txidx = frag; 5400 5401 return 0; 5402 5403 fail_unload: 5404 bus_dmamap_unload(sc->bge_dmatag, dmamap); 5405 5406 return ENOBUFS; 5407 } 5408 5409 /* 5410 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5411 * to the mbuf data regions directly in the transmit descriptors. 5412 */ 5413 static void 5414 bge_start(struct ifnet *ifp) 5415 { 5416 struct bge_softc *sc; 5417 struct mbuf *m_head = NULL; 5418 uint32_t prodidx; 5419 int pkts = 0; 5420 5421 sc = ifp->if_softc; 5422 5423 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5424 return; 5425 5426 prodidx = sc->bge_tx_prodidx; 5427 5428 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5429 IFQ_POLL(&ifp->if_snd, m_head); 5430 if (m_head == NULL) 5431 break; 5432 5433 #if 0 5434 /* 5435 * XXX 5436 * safety overkill. If this is a fragmented packet chain 5437 * with delayed TCP/UDP checksums, then only encapsulate 5438 * it if we have enough descriptors to handle the entire 5439 * chain at once. 5440 * (paranoia -- may not actually be needed) 5441 */ 5442 if (m_head->m_flags & M_FIRSTFRAG && 5443 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5444 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5445 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5446 ifp->if_flags |= IFF_OACTIVE; 5447 break; 5448 } 5449 } 5450 #endif 5451 5452 /* 5453 * Pack the data into the transmit ring. If we 5454 * don't have room, set the OACTIVE flag and wait 5455 * for the NIC to drain the ring. 5456 */ 5457 if (bge_encap(sc, m_head, &prodidx)) { 5458 ifp->if_flags |= IFF_OACTIVE; 5459 break; 5460 } 5461 5462 /* now we are committed to transmit the packet */ 5463 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5464 pkts++; 5465 5466 /* 5467 * If there's a BPF listener, bounce a copy of this frame 5468 * to him. 5469 */ 5470 bpf_mtap(ifp, m_head); 5471 } 5472 if (pkts == 0) 5473 return; 5474 5475 /* Transmit */ 5476 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5477 /* 5700 b2 errata */ 5478 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5479 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5480 5481 sc->bge_tx_prodidx = prodidx; 5482 5483 /* 5484 * Set a timeout in case the chip goes out to lunch. 5485 */ 5486 ifp->if_timer = 5; 5487 } 5488 5489 static int 5490 bge_init(struct ifnet *ifp) 5491 { 5492 struct bge_softc *sc = ifp->if_softc; 5493 const uint16_t *m; 5494 uint32_t mode, reg; 5495 int s, error = 0; 5496 5497 s = splnet(); 5498 5499 ifp = &sc->ethercom.ec_if; 5500 5501 /* Cancel pending I/O and flush buffers. */ 5502 bge_stop(ifp, 0); 5503 5504 bge_stop_fw(sc); 5505 bge_sig_pre_reset(sc, BGE_RESET_START); 5506 bge_reset(sc); 5507 bge_sig_legacy(sc, BGE_RESET_START); 5508 5509 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5510 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5511 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5512 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5513 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5514 5515 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5516 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5517 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5518 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5519 5520 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5521 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5522 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5523 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5524 5525 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5526 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5527 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5528 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5529 } 5530 5531 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5532 pcireg_t aercap; 5533 5534 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5535 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5536 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5537 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5538 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5539 5540 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5541 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5542 | BGE_PCIE_EIDLE_DELAY_13CLK; 5543 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5544 5545 /* Clear correctable error */ 5546 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5547 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5548 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5549 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5550 5551 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5552 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5553 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5554 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5555 } 5556 5557 bge_sig_post_reset(sc, BGE_RESET_START); 5558 5559 bge_chipinit(sc); 5560 5561 /* 5562 * Init the various state machines, ring 5563 * control blocks and firmware. 5564 */ 5565 error = bge_blockinit(sc); 5566 if (error != 0) { 5567 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5568 error); 5569 splx(s); 5570 return error; 5571 } 5572 5573 ifp = &sc->ethercom.ec_if; 5574 5575 /* 5718 step 25, 57XX step 54 */ 5576 /* Specify MTU. */ 5577 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5578 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5579 5580 /* 5718 step 23 */ 5581 /* Load our MAC address. */ 5582 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5583 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5584 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5585 5586 /* Enable or disable promiscuous mode as needed. */ 5587 if (ifp->if_flags & IFF_PROMISC) 5588 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5589 else 5590 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5591 5592 /* Program multicast filter. */ 5593 bge_setmulti(sc); 5594 5595 /* Init RX ring. */ 5596 bge_init_rx_ring_std(sc); 5597 5598 /* 5599 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5600 * memory to insure that the chip has in fact read the first 5601 * entry of the ring. 5602 */ 5603 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5604 uint32_t v, i; 5605 for (i = 0; i < 10; i++) { 5606 DELAY(20); 5607 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5608 if (v == (MCLBYTES - ETHER_ALIGN)) 5609 break; 5610 } 5611 if (i == 10) 5612 aprint_error_dev(sc->bge_dev, 5613 "5705 A0 chip failed to load RX ring\n"); 5614 } 5615 5616 /* Init jumbo RX ring. */ 5617 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5618 bge_init_rx_ring_jumbo(sc); 5619 5620 /* Init our RX return ring index */ 5621 sc->bge_rx_saved_considx = 0; 5622 5623 /* Init TX ring. */ 5624 bge_init_tx_ring(sc); 5625 5626 /* 5718 step 63, 57XX step 94 */ 5627 /* Enable TX MAC state machine lockup fix. */ 5628 mode = CSR_READ_4(sc, BGE_TX_MODE); 5629 if (BGE_IS_5755_PLUS(sc) || 5630 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5631 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5632 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5633 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5634 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5635 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5636 } 5637 5638 /* Turn on transmitter */ 5639 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5640 /* 5718 step 64 */ 5641 DELAY(100); 5642 5643 /* 5718 step 65, 57XX step 95 */ 5644 /* Turn on receiver */ 5645 mode = CSR_READ_4(sc, BGE_RX_MODE); 5646 if (BGE_IS_5755_PLUS(sc)) 5647 mode |= BGE_RXMODE_IPV6_ENABLE; 5648 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5649 /* 5718 step 66 */ 5650 DELAY(10); 5651 5652 /* 5718 step 12, 57XX step 37 */ 5653 /* 5654 * XXX Doucments of 5718 series and 577xx say the recommended value 5655 * is 1, but tg3 set 1 only on 57765 series. 5656 */ 5657 if (BGE_IS_57765_PLUS(sc)) 5658 reg = 1; 5659 else 5660 reg = 2; 5661 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5662 5663 /* Tell firmware we're alive. */ 5664 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5665 5666 /* Enable host interrupts. */ 5667 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5668 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5669 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5670 5671 if ((error = bge_ifmedia_upd(ifp)) != 0) 5672 goto out; 5673 5674 ifp->if_flags |= IFF_RUNNING; 5675 ifp->if_flags &= ~IFF_OACTIVE; 5676 5677 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5678 5679 out: 5680 sc->bge_if_flags = ifp->if_flags; 5681 splx(s); 5682 5683 return error; 5684 } 5685 5686 /* 5687 * Set media options. 5688 */ 5689 static int 5690 bge_ifmedia_upd(struct ifnet *ifp) 5691 { 5692 struct bge_softc *sc = ifp->if_softc; 5693 struct mii_data *mii = &sc->bge_mii; 5694 struct ifmedia *ifm = &sc->bge_ifmedia; 5695 int rc; 5696 5697 /* If this is a 1000baseX NIC, enable the TBI port. */ 5698 if (sc->bge_flags & BGEF_FIBER_TBI) { 5699 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5700 return EINVAL; 5701 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5702 case IFM_AUTO: 5703 /* 5704 * The BCM5704 ASIC appears to have a special 5705 * mechanism for programming the autoneg 5706 * advertisement registers in TBI mode. 5707 */ 5708 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5709 uint32_t sgdig; 5710 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5711 if (sgdig & BGE_SGDIGSTS_DONE) { 5712 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5713 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5714 sgdig |= BGE_SGDIGCFG_AUTO | 5715 BGE_SGDIGCFG_PAUSE_CAP | 5716 BGE_SGDIGCFG_ASYM_PAUSE; 5717 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5718 sgdig | BGE_SGDIGCFG_SEND); 5719 DELAY(5); 5720 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5721 sgdig); 5722 } 5723 } 5724 break; 5725 case IFM_1000_SX: 5726 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5727 BGE_CLRBIT(sc, BGE_MAC_MODE, 5728 BGE_MACMODE_HALF_DUPLEX); 5729 } else { 5730 BGE_SETBIT(sc, BGE_MAC_MODE, 5731 BGE_MACMODE_HALF_DUPLEX); 5732 } 5733 DELAY(40); 5734 break; 5735 default: 5736 return EINVAL; 5737 } 5738 /* XXX 802.3x flow control for 1000BASE-SX */ 5739 return 0; 5740 } 5741 5742 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5743 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5744 uint32_t reg; 5745 5746 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5747 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5748 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5749 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5750 } 5751 } 5752 5753 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5754 if ((rc = mii_mediachg(mii)) == ENXIO) 5755 return 0; 5756 5757 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5758 uint32_t reg; 5759 5760 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5761 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5762 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5763 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5764 delay(40); 5765 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5766 } 5767 } 5768 5769 /* 5770 * Force an interrupt so that we will call bge_link_upd 5771 * if needed and clear any pending link state attention. 5772 * Without this we are not getting any further interrupts 5773 * for link state changes and thus will not UP the link and 5774 * not be able to send in bge_start. The only way to get 5775 * things working was to receive a packet and get a RX intr. 5776 */ 5777 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5778 sc->bge_flags & BGEF_IS_5788) 5779 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5780 else 5781 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5782 5783 return rc; 5784 } 5785 5786 /* 5787 * Report current media status. 5788 */ 5789 static void 5790 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5791 { 5792 struct bge_softc *sc = ifp->if_softc; 5793 struct mii_data *mii = &sc->bge_mii; 5794 5795 if (sc->bge_flags & BGEF_FIBER_TBI) { 5796 ifmr->ifm_status = IFM_AVALID; 5797 ifmr->ifm_active = IFM_ETHER; 5798 if (CSR_READ_4(sc, BGE_MAC_STS) & 5799 BGE_MACSTAT_TBI_PCS_SYNCHED) 5800 ifmr->ifm_status |= IFM_ACTIVE; 5801 ifmr->ifm_active |= IFM_1000_SX; 5802 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5803 ifmr->ifm_active |= IFM_HDX; 5804 else 5805 ifmr->ifm_active |= IFM_FDX; 5806 return; 5807 } 5808 5809 mii_pollstat(mii); 5810 ifmr->ifm_status = mii->mii_media_status; 5811 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5812 sc->bge_flowflags; 5813 } 5814 5815 static int 5816 bge_ifflags_cb(struct ethercom *ec) 5817 { 5818 struct ifnet *ifp = &ec->ec_if; 5819 struct bge_softc *sc = ifp->if_softc; 5820 int change = ifp->if_flags ^ sc->bge_if_flags; 5821 5822 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5823 return ENETRESET; 5824 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5825 return 0; 5826 5827 if ((ifp->if_flags & IFF_PROMISC) == 0) 5828 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5829 else 5830 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5831 5832 bge_setmulti(sc); 5833 5834 sc->bge_if_flags = ifp->if_flags; 5835 return 0; 5836 } 5837 5838 static int 5839 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5840 { 5841 struct bge_softc *sc = ifp->if_softc; 5842 struct ifreq *ifr = (struct ifreq *) data; 5843 int s, error = 0; 5844 struct mii_data *mii; 5845 5846 s = splnet(); 5847 5848 switch (command) { 5849 case SIOCSIFMEDIA: 5850 /* XXX Flow control is not supported for 1000BASE-SX */ 5851 if (sc->bge_flags & BGEF_FIBER_TBI) { 5852 ifr->ifr_media &= ~IFM_ETH_FMASK; 5853 sc->bge_flowflags = 0; 5854 } 5855 5856 /* Flow control requires full-duplex mode. */ 5857 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5858 (ifr->ifr_media & IFM_FDX) == 0) { 5859 ifr->ifr_media &= ~IFM_ETH_FMASK; 5860 } 5861 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5862 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5863 /* We can do both TXPAUSE and RXPAUSE. */ 5864 ifr->ifr_media |= 5865 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5866 } 5867 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5868 } 5869 /* FALLTHROUGH */ 5870 case SIOCGIFMEDIA: 5871 if (sc->bge_flags & BGEF_FIBER_TBI) { 5872 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5873 command); 5874 } else { 5875 mii = &sc->bge_mii; 5876 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5877 command); 5878 } 5879 break; 5880 default: 5881 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5882 break; 5883 5884 error = 0; 5885 5886 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5887 ; 5888 else if (ifp->if_flags & IFF_RUNNING) 5889 bge_setmulti(sc); 5890 break; 5891 } 5892 5893 splx(s); 5894 5895 return error; 5896 } 5897 5898 static void 5899 bge_watchdog(struct ifnet *ifp) 5900 { 5901 struct bge_softc *sc; 5902 5903 sc = ifp->if_softc; 5904 5905 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5906 5907 ifp->if_flags &= ~IFF_RUNNING; 5908 bge_init(ifp); 5909 5910 ifp->if_oerrors++; 5911 } 5912 5913 static void 5914 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5915 { 5916 int i; 5917 5918 BGE_CLRBIT_FLUSH(sc, reg, bit); 5919 5920 for (i = 0; i < 1000; i++) { 5921 delay(100); 5922 if ((CSR_READ_4(sc, reg) & bit) == 0) 5923 return; 5924 } 5925 5926 /* 5927 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5928 * on some environment (and once after boot?) 5929 */ 5930 if (reg != BGE_SRS_MODE) 5931 aprint_error_dev(sc->bge_dev, 5932 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5933 (u_long)reg, bit); 5934 } 5935 5936 /* 5937 * Stop the adapter and free any mbufs allocated to the 5938 * RX and TX lists. 5939 */ 5940 static void 5941 bge_stop(struct ifnet *ifp, int disable) 5942 { 5943 struct bge_softc *sc = ifp->if_softc; 5944 5945 if (disable) { 5946 sc->bge_detaching = 1; 5947 callout_halt(&sc->bge_timeout, NULL); 5948 } else 5949 callout_stop(&sc->bge_timeout); 5950 5951 /* Disable host interrupts. */ 5952 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5953 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5954 5955 /* 5956 * Tell firmware we're shutting down. 5957 */ 5958 bge_stop_fw(sc); 5959 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5960 5961 /* 5962 * Disable all of the receiver blocks. 5963 */ 5964 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5965 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5966 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5967 if (BGE_IS_5700_FAMILY(sc)) 5968 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5969 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5970 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5971 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5972 5973 /* 5974 * Disable all of the transmit blocks. 5975 */ 5976 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5977 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5978 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5979 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5980 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5981 if (BGE_IS_5700_FAMILY(sc)) 5982 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5983 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5984 5985 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5986 delay(40); 5987 5988 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5989 5990 /* 5991 * Shut down all of the memory managers and related 5992 * state machines. 5993 */ 5994 /* 5718 step 5a,5b */ 5995 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5996 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5997 if (BGE_IS_5700_FAMILY(sc)) 5998 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5999 6000 /* 5718 step 5c,5d */ 6001 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6002 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6003 6004 if (BGE_IS_5700_FAMILY(sc)) { 6005 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6006 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6007 } 6008 6009 bge_reset(sc); 6010 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6011 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6012 6013 /* 6014 * Keep the ASF firmware running if up. 6015 */ 6016 if (sc->bge_asf_mode & ASF_STACKUP) 6017 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6018 else 6019 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6020 6021 /* Free the RX lists. */ 6022 bge_free_rx_ring_std(sc); 6023 6024 /* Free jumbo RX list. */ 6025 if (BGE_IS_JUMBO_CAPABLE(sc)) 6026 bge_free_rx_ring_jumbo(sc); 6027 6028 /* Free TX buffers. */ 6029 bge_free_tx_ring(sc); 6030 6031 /* 6032 * Isolate/power down the PHY. 6033 */ 6034 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6035 mii_down(&sc->bge_mii); 6036 6037 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6038 6039 /* Clear MAC's link state (PHY may still have link UP). */ 6040 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6041 6042 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6043 } 6044 6045 static void 6046 bge_link_upd(struct bge_softc *sc) 6047 { 6048 struct ifnet *ifp = &sc->ethercom.ec_if; 6049 struct mii_data *mii = &sc->bge_mii; 6050 uint32_t status; 6051 int link; 6052 6053 /* Clear 'pending link event' flag */ 6054 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6055 6056 /* 6057 * Process link state changes. 6058 * Grrr. The link status word in the status block does 6059 * not work correctly on the BCM5700 rev AX and BX chips, 6060 * according to all available information. Hence, we have 6061 * to enable MII interrupts in order to properly obtain 6062 * async link changes. Unfortunately, this also means that 6063 * we have to read the MAC status register to detect link 6064 * changes, thereby adding an additional register access to 6065 * the interrupt handler. 6066 */ 6067 6068 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6069 status = CSR_READ_4(sc, BGE_MAC_STS); 6070 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6071 mii_pollstat(mii); 6072 6073 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6074 mii->mii_media_status & IFM_ACTIVE && 6075 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6076 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6077 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6078 (!(mii->mii_media_status & IFM_ACTIVE) || 6079 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6080 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6081 6082 /* Clear the interrupt */ 6083 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6084 BGE_EVTENB_MI_INTERRUPT); 6085 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6086 BRGPHY_MII_ISR); 6087 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6088 BRGPHY_MII_IMR, BRGPHY_INTRS); 6089 } 6090 return; 6091 } 6092 6093 if (sc->bge_flags & BGEF_FIBER_TBI) { 6094 status = CSR_READ_4(sc, BGE_MAC_STS); 6095 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6096 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6097 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6098 if (BGE_ASICREV(sc->bge_chipid) 6099 == BGE_ASICREV_BCM5704) { 6100 BGE_CLRBIT(sc, BGE_MAC_MODE, 6101 BGE_MACMODE_TBI_SEND_CFGS); 6102 DELAY(40); 6103 } 6104 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6105 if_link_state_change(ifp, LINK_STATE_UP); 6106 } 6107 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6108 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6109 if_link_state_change(ifp, LINK_STATE_DOWN); 6110 } 6111 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6112 /* 6113 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6114 * bit in status word always set. Workaround this bug by 6115 * reading PHY link status directly. 6116 */ 6117 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6118 BGE_STS_LINK : 0; 6119 6120 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6121 mii_pollstat(mii); 6122 6123 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6124 mii->mii_media_status & IFM_ACTIVE && 6125 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6126 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6127 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6128 (!(mii->mii_media_status & IFM_ACTIVE) || 6129 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6130 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6131 } 6132 } else { 6133 /* 6134 * For controllers that call mii_tick, we have to poll 6135 * link status. 6136 */ 6137 mii_pollstat(mii); 6138 } 6139 6140 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6141 uint32_t reg, scale; 6142 6143 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6144 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6145 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6146 scale = 65; 6147 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6148 scale = 6; 6149 else 6150 scale = 12; 6151 6152 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6153 ~BGE_MISCCFG_TIMER_PRESCALER; 6154 reg |= scale << 1; 6155 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6156 } 6157 /* Clear the attention */ 6158 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6159 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6160 BGE_MACSTAT_LINK_CHANGED); 6161 } 6162 6163 static int 6164 bge_sysctl_verify(SYSCTLFN_ARGS) 6165 { 6166 int error, t; 6167 struct sysctlnode node; 6168 6169 node = *rnode; 6170 t = *(int*)rnode->sysctl_data; 6171 node.sysctl_data = &t; 6172 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6173 if (error || newp == NULL) 6174 return error; 6175 6176 #if 0 6177 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6178 node.sysctl_num, rnode->sysctl_num)); 6179 #endif 6180 6181 if (node.sysctl_num == bge_rxthresh_nodenum) { 6182 if (t < 0 || t >= NBGE_RX_THRESH) 6183 return EINVAL; 6184 bge_update_all_threshes(t); 6185 } else 6186 return EINVAL; 6187 6188 *(int*)rnode->sysctl_data = t; 6189 6190 return 0; 6191 } 6192 6193 /* 6194 * Set up sysctl(3) MIB, hw.bge.*. 6195 */ 6196 static void 6197 bge_sysctl_init(struct bge_softc *sc) 6198 { 6199 int rc, bge_root_num; 6200 const struct sysctlnode *node; 6201 6202 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6203 0, CTLTYPE_NODE, "bge", 6204 SYSCTL_DESCR("BGE interface controls"), 6205 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6206 goto out; 6207 } 6208 6209 bge_root_num = node->sysctl_num; 6210 6211 /* BGE Rx interrupt mitigation level */ 6212 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6213 CTLFLAG_READWRITE, 6214 CTLTYPE_INT, "rx_lvl", 6215 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6216 bge_sysctl_verify, 0, 6217 &bge_rx_thresh_lvl, 6218 0, CTL_HW, bge_root_num, CTL_CREATE, 6219 CTL_EOL)) != 0) { 6220 goto out; 6221 } 6222 6223 bge_rxthresh_nodenum = node->sysctl_num; 6224 6225 return; 6226 6227 out: 6228 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6229 } 6230 6231 #ifdef BGE_DEBUG 6232 void 6233 bge_debug_info(struct bge_softc *sc) 6234 { 6235 6236 printf("Hardware Flags:\n"); 6237 if (BGE_IS_57765_PLUS(sc)) 6238 printf(" - 57765 Plus\n"); 6239 if (BGE_IS_5717_PLUS(sc)) 6240 printf(" - 5717 Plus\n"); 6241 if (BGE_IS_5755_PLUS(sc)) 6242 printf(" - 5755 Plus\n"); 6243 if (BGE_IS_575X_PLUS(sc)) 6244 printf(" - 575X Plus\n"); 6245 if (BGE_IS_5705_PLUS(sc)) 6246 printf(" - 5705 Plus\n"); 6247 if (BGE_IS_5714_FAMILY(sc)) 6248 printf(" - 5714 Family\n"); 6249 if (BGE_IS_5700_FAMILY(sc)) 6250 printf(" - 5700 Family\n"); 6251 if (sc->bge_flags & BGEF_IS_5788) 6252 printf(" - 5788\n"); 6253 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6254 printf(" - Supports Jumbo Frames\n"); 6255 if (sc->bge_flags & BGEF_NO_EEPROM) 6256 printf(" - No EEPROM\n"); 6257 if (sc->bge_flags & BGEF_PCIX) 6258 printf(" - PCI-X Bus\n"); 6259 if (sc->bge_flags & BGEF_PCIE) 6260 printf(" - PCI Express Bus\n"); 6261 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6262 printf(" - RX Alignment Bug\n"); 6263 if (sc->bge_flags & BGEF_APE) 6264 printf(" - APE\n"); 6265 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6266 printf(" - CPMU\n"); 6267 if (sc->bge_flags & BGEF_TSO) 6268 printf(" - TSO\n"); 6269 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6270 printf(" - TAGGED_STATUS\n"); 6271 6272 /* PHY related */ 6273 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6274 printf(" - No 3 LEDs\n"); 6275 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6276 printf(" - CRC bug\n"); 6277 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6278 printf(" - ADC bug\n"); 6279 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6280 printf(" - 5704 A0 bug\n"); 6281 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6282 printf(" - jitter bug\n"); 6283 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6284 printf(" - BER bug\n"); 6285 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6286 printf(" - adjust trim\n"); 6287 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6288 printf(" - no wirespeed\n"); 6289 6290 /* ASF related */ 6291 if (sc->bge_asf_mode & ASF_ENABLE) 6292 printf(" - ASF enable\n"); 6293 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6294 printf(" - ASF new handshake\n"); 6295 if (sc->bge_asf_mode & ASF_STACKUP) 6296 printf(" - ASF stackup\n"); 6297 } 6298 #endif /* BGE_DEBUG */ 6299 6300 static int 6301 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6302 { 6303 prop_dictionary_t dict; 6304 prop_data_t ea; 6305 6306 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6307 return 1; 6308 6309 dict = device_properties(sc->bge_dev); 6310 ea = prop_dictionary_get(dict, "mac-address"); 6311 if (ea != NULL) { 6312 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6313 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6314 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6315 return 0; 6316 } 6317 6318 return 1; 6319 } 6320 6321 static int 6322 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6323 { 6324 uint32_t mac_addr; 6325 6326 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6327 if ((mac_addr >> 16) == 0x484b) { 6328 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6329 ether_addr[1] = (uint8_t)mac_addr; 6330 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6331 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6332 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6333 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6334 ether_addr[5] = (uint8_t)mac_addr; 6335 return 0; 6336 } 6337 return 1; 6338 } 6339 6340 static int 6341 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6342 { 6343 int mac_offset = BGE_EE_MAC_OFFSET; 6344 6345 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6346 mac_offset = BGE_EE_MAC_OFFSET_5906; 6347 6348 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6349 ETHER_ADDR_LEN)); 6350 } 6351 6352 static int 6353 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6354 { 6355 6356 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6357 return 1; 6358 6359 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6360 ETHER_ADDR_LEN)); 6361 } 6362 6363 static int 6364 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6365 { 6366 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6367 /* NOTE: Order is critical */ 6368 bge_get_eaddr_fw, 6369 bge_get_eaddr_mem, 6370 bge_get_eaddr_nvram, 6371 bge_get_eaddr_eeprom, 6372 NULL 6373 }; 6374 const bge_eaddr_fcn_t *func; 6375 6376 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6377 if ((*func)(sc, eaddr) == 0) 6378 break; 6379 } 6380 return (*func == NULL ? ENXIO : 0); 6381 } 6382
Indexes created Tue Sep 23 02:09:52 GMT 2025