if_bge.c revision 1.319
1 /* $NetBSD: if_bge.c,v 1.319 2018/11/30 17:53:08 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.319 2018/11/30 17:53:08 jdolecek Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_can_use_msi(struct bge_softc *); 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static int bge_detach(device_t, int); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int); 254 static void bge_miibus_writereg(device_t, int, int, int); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5750, 440 "Broadcom BCM5750 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5751, 444 "Broadcom BCM5751 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5751F, 448 "Broadcom BCM5751F Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751M, 452 "Broadcom BCM5751M Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5752, 456 "Broadcom BCM5752 Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5752M, 460 "Broadcom BCM5752M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5753, 464 "Broadcom BCM5753 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5753F, 468 "Broadcom BCM5753F Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753M, 472 "Broadcom BCM5753M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5754, 476 "Broadcom BCM5754 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5754M, 480 "Broadcom BCM5754M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5755, 484 "Broadcom BCM5755 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5755M, 488 "Broadcom BCM5755M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5756, 492 "Broadcom BCM5756 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5761, 496 "Broadcom BCM5761 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5761E, 500 "Broadcom BCM5761E Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761S, 504 "Broadcom BCM5761S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761SE, 508 "Broadcom BCM5761SE Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5764, 512 "Broadcom BCM5764 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5780, 516 "Broadcom BCM5780 Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5780S, 520 "Broadcom BCM5780S Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5781, 524 "Broadcom BCM5781 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5782, 528 "Broadcom BCM5782 Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5784M, 532 "BCM5784M NetLink 1000baseT Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5785F, 536 "BCM5785F NetLink 10/100 Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5785G, 540 "BCM5785G NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5786, 544 "Broadcom BCM5786 Gigabit Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5787, 548 "Broadcom BCM5787 Gigabit Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5787F, 552 "Broadcom BCM5787F 10/100 Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787M, 556 "Broadcom BCM5787M Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5788, 560 "Broadcom BCM5788 Gigabit Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5789, 564 "Broadcom BCM5789 Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5901, 568 "Broadcom BCM5901 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5901A2, 572 "Broadcom BCM5901A2 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5903M, 576 "Broadcom BCM5903M Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5906, 580 "Broadcom BCM5906 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5906M, 584 "Broadcom BCM5906M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57760, 588 "Broadcom BCM57760 Gigabit Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57761, 592 "Broadcom BCM57761 Gigabit Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57762, 596 "Broadcom BCM57762 Gigabit Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57765, 600 "Broadcom BCM57765 Gigabit Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57766, 604 "Broadcom BCM57766 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57780, 608 "Broadcom BCM57780 Gigabit Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57781, 612 "Broadcom BCM57781 Gigabit Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57782, 616 "Broadcom BCM57782 Gigabit Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57785, 620 "Broadcom BCM57785 Gigabit Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57786, 624 "Broadcom BCM57786 Gigabit Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57788, 628 "Broadcom BCM57788 Gigabit Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57790, 632 "Broadcom BCM57790 Gigabit Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57791, 636 "Broadcom BCM57791 Gigabit Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57795, 640 "Broadcom BCM57795 Gigabit Ethernet", 641 }, 642 { PCI_VENDOR_SCHNEIDERKOCH, 643 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 644 "SysKonnect SK-9Dx1 Gigabit Ethernet", 645 }, 646 { PCI_VENDOR_3COM, 647 PCI_PRODUCT_3COM_3C996, 648 "3Com 3c996 Gigabit Ethernet", 649 }, 650 { PCI_VENDOR_FUJITSU4, 651 PCI_PRODUCT_FUJITSU4_PW008GE4, 652 "Fujitsu PW008GE4 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_FUJITSU4, 655 PCI_PRODUCT_FUJITSU4_PW008GE5, 656 "Fujitsu PW008GE5 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 660 "Fujitsu Primepower 250/450 Gigabit Ethernet", 661 }, 662 { 0, 663 0, 664 NULL }, 665 }; 666 667 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 668 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 669 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 670 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 671 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 672 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 673 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 674 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 675 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 676 677 static const struct bge_revision { 678 uint32_t br_chipid; 679 const char *br_name; 680 } bge_revisions[] = { 681 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 682 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 683 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 684 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 685 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 686 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 687 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 688 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 689 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 690 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 691 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 692 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 693 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 694 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 695 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 696 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 697 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 698 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 699 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 700 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 701 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 702 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 703 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 704 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 705 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 706 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 707 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 708 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 709 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 710 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 711 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 712 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 713 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 714 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 715 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 716 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 717 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 718 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 719 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 720 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 721 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 722 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 723 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 724 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 725 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 726 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 727 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 728 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 729 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 730 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 731 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 732 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 733 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 734 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 735 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 736 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 737 /* 5754 and 5787 share the same ASIC ID */ 738 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 739 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 740 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 741 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 742 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 743 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 744 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 745 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 746 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 747 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 748 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 749 750 { 0, NULL } 751 }; 752 753 /* 754 * Some defaults for major revisions, so that newer steppings 755 * that we don't know about have a shot at working. 756 */ 757 static const struct bge_revision bge_majorrevs[] = { 758 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 759 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 760 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 761 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 762 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 763 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 764 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 765 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 766 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 767 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 768 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 769 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 770 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 771 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 772 /* 5754 and 5787 share the same ASIC ID */ 773 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 774 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 775 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 776 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 777 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 778 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 779 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 780 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 781 782 { 0, NULL } 783 }; 784 785 static int bge_allow_asf = 1; 786 787 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 788 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 789 790 static uint32_t 791 bge_readmem_ind(struct bge_softc *sc, int off) 792 { 793 pcireg_t val; 794 795 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 796 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 797 return 0; 798 799 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 800 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 801 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 802 return val; 803 } 804 805 static void 806 bge_writemem_ind(struct bge_softc *sc, int off, int val) 807 { 808 809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 811 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 812 } 813 814 /* 815 * PCI Express only 816 */ 817 static void 818 bge_set_max_readrq(struct bge_softc *sc) 819 { 820 pcireg_t val; 821 822 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 823 + PCIE_DCSR); 824 val &= ~PCIE_DCSR_MAX_READ_REQ; 825 switch (sc->bge_expmrq) { 826 case 2048: 827 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 828 break; 829 case 4096: 830 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 831 break; 832 default: 833 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 834 break; 835 } 836 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 837 + PCIE_DCSR, val); 838 } 839 840 #ifdef notdef 841 static uint32_t 842 bge_readreg_ind(struct bge_softc *sc, int off) 843 { 844 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 845 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 846 } 847 #endif 848 849 static void 850 bge_writereg_ind(struct bge_softc *sc, int off, int val) 851 { 852 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 853 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 854 } 855 856 static void 857 bge_writemem_direct(struct bge_softc *sc, int off, int val) 858 { 859 CSR_WRITE_4(sc, off, val); 860 } 861 862 static void 863 bge_writembx(struct bge_softc *sc, int off, int val) 864 { 865 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 866 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 867 868 CSR_WRITE_4(sc, off, val); 869 } 870 871 static void 872 bge_writembx_flush(struct bge_softc *sc, int off, int val) 873 { 874 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 875 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 876 877 CSR_WRITE_4_FLUSH(sc, off, val); 878 } 879 880 /* 881 * Clear all stale locks and select the lock for this driver instance. 882 */ 883 void 884 bge_ape_lock_init(struct bge_softc *sc) 885 { 886 struct pci_attach_args *pa = &(sc->bge_pa); 887 uint32_t bit, regbase; 888 int i; 889 890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 891 regbase = BGE_APE_LOCK_GRANT; 892 else 893 regbase = BGE_APE_PER_LOCK_GRANT; 894 895 /* Clear any stale locks. */ 896 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 897 switch (i) { 898 case BGE_APE_LOCK_PHY0: 899 case BGE_APE_LOCK_PHY1: 900 case BGE_APE_LOCK_PHY2: 901 case BGE_APE_LOCK_PHY3: 902 bit = BGE_APE_LOCK_GRANT_DRIVER0; 903 break; 904 default: 905 if (pa->pa_function == 0) 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 else 908 bit = (1 << pa->pa_function); 909 } 910 APE_WRITE_4(sc, regbase + 4 * i, bit); 911 } 912 913 /* Select the PHY lock based on the device's function number. */ 914 switch (pa->pa_function) { 915 case 0: 916 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 917 break; 918 case 1: 919 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 920 break; 921 case 2: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 923 break; 924 case 3: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 926 break; 927 default: 928 printf("%s: PHY lock not supported on function\n", 929 device_xname(sc->bge_dev)); 930 break; 931 } 932 } 933 934 /* 935 * Check for APE firmware, set flags, and print version info. 936 */ 937 void 938 bge_ape_read_fw_ver(struct bge_softc *sc) 939 { 940 const char *fwtype; 941 uint32_t apedata, features; 942 943 /* Check for a valid APE signature in shared memory. */ 944 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 945 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 946 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 947 return; 948 } 949 950 /* Check if APE firmware is running. */ 951 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 952 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 953 printf("%s: APE signature found but FW status not ready! " 954 "0x%08x\n", device_xname(sc->bge_dev), apedata); 955 return; 956 } 957 958 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 959 960 /* Fetch the APE firwmare type and version. */ 961 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 962 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 963 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 964 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 965 fwtype = "NCSI"; 966 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 967 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 968 fwtype = "DASH"; 969 } else 970 fwtype = "UNKN"; 971 972 /* Print the APE firmware version. */ 973 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 974 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 975 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 976 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 977 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 978 } 979 980 int 981 bge_ape_lock(struct bge_softc *sc, int locknum) 982 { 983 struct pci_attach_args *pa = &(sc->bge_pa); 984 uint32_t bit, gnt, req, status; 985 int i, off; 986 987 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 988 return (0); 989 990 /* Lock request/grant registers have different bases. */ 991 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 992 req = BGE_APE_LOCK_REQ; 993 gnt = BGE_APE_LOCK_GRANT; 994 } else { 995 req = BGE_APE_PER_LOCK_REQ; 996 gnt = BGE_APE_PER_LOCK_GRANT; 997 } 998 999 off = 4 * locknum; 1000 1001 switch (locknum) { 1002 case BGE_APE_LOCK_GPIO: 1003 /* Lock required when using GPIO. */ 1004 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1005 return (0); 1006 if (pa->pa_function == 0) 1007 bit = BGE_APE_LOCK_REQ_DRIVER0; 1008 else 1009 bit = (1 << pa->pa_function); 1010 break; 1011 case BGE_APE_LOCK_GRC: 1012 /* Lock required to reset the device. */ 1013 if (pa->pa_function == 0) 1014 bit = BGE_APE_LOCK_REQ_DRIVER0; 1015 else 1016 bit = (1 << pa->pa_function); 1017 break; 1018 case BGE_APE_LOCK_MEM: 1019 /* Lock required when accessing certain APE memory. */ 1020 if (pa->pa_function == 0) 1021 bit = BGE_APE_LOCK_REQ_DRIVER0; 1022 else 1023 bit = (1 << pa->pa_function); 1024 break; 1025 case BGE_APE_LOCK_PHY0: 1026 case BGE_APE_LOCK_PHY1: 1027 case BGE_APE_LOCK_PHY2: 1028 case BGE_APE_LOCK_PHY3: 1029 /* Lock required when accessing PHYs. */ 1030 bit = BGE_APE_LOCK_REQ_DRIVER0; 1031 break; 1032 default: 1033 return (EINVAL); 1034 } 1035 1036 /* Request a lock. */ 1037 APE_WRITE_4_FLUSH(sc, req + off, bit); 1038 1039 /* Wait up to 1 second to acquire lock. */ 1040 for (i = 0; i < 20000; i++) { 1041 status = APE_READ_4(sc, gnt + off); 1042 if (status == bit) 1043 break; 1044 DELAY(50); 1045 } 1046 1047 /* Handle any errors. */ 1048 if (status != bit) { 1049 printf("%s: APE lock %d request failed! " 1050 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1051 device_xname(sc->bge_dev), 1052 locknum, req + off, bit & 0xFFFF, gnt + off, 1053 status & 0xFFFF); 1054 /* Revoke the lock request. */ 1055 APE_WRITE_4(sc, gnt + off, bit); 1056 return (EBUSY); 1057 } 1058 1059 return (0); 1060 } 1061 1062 void 1063 bge_ape_unlock(struct bge_softc *sc, int locknum) 1064 { 1065 struct pci_attach_args *pa = &(sc->bge_pa); 1066 uint32_t bit, gnt; 1067 int off; 1068 1069 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1070 return; 1071 1072 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1073 gnt = BGE_APE_LOCK_GRANT; 1074 else 1075 gnt = BGE_APE_PER_LOCK_GRANT; 1076 1077 off = 4 * locknum; 1078 1079 switch (locknum) { 1080 case BGE_APE_LOCK_GPIO: 1081 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1082 return; 1083 if (pa->pa_function == 0) 1084 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1085 else 1086 bit = (1 << pa->pa_function); 1087 break; 1088 case BGE_APE_LOCK_GRC: 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_MEM: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_PHY0: 1101 case BGE_APE_LOCK_PHY1: 1102 case BGE_APE_LOCK_PHY2: 1103 case BGE_APE_LOCK_PHY3: 1104 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1105 break; 1106 default: 1107 return; 1108 } 1109 1110 /* Write and flush for consecutive bge_ape_lock() */ 1111 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1112 } 1113 1114 /* 1115 * Send an event to the APE firmware. 1116 */ 1117 void 1118 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1119 { 1120 uint32_t apedata; 1121 int i; 1122 1123 /* NCSI does not support APE events. */ 1124 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1125 return; 1126 1127 /* Wait up to 1ms for APE to service previous event. */ 1128 for (i = 10; i > 0; i--) { 1129 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1130 break; 1131 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1132 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1133 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1134 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1135 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1136 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1137 break; 1138 } 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 DELAY(100); 1141 } 1142 if (i == 0) { 1143 printf("%s: APE event 0x%08x send timed out\n", 1144 device_xname(sc->bge_dev), event); 1145 } 1146 } 1147 1148 void 1149 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1150 { 1151 uint32_t apedata, event; 1152 1153 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1154 return; 1155 1156 switch (kind) { 1157 case BGE_RESET_START: 1158 /* If this is the first load, clear the load counter. */ 1159 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1160 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1161 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1162 else { 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1164 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1165 } 1166 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1167 BGE_APE_HOST_SEG_SIG_MAGIC); 1168 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1169 BGE_APE_HOST_SEG_LEN_MAGIC); 1170 1171 /* Add some version info if bge(4) supports it. */ 1172 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1173 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1174 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1175 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1176 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1177 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1178 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1179 BGE_APE_HOST_DRVR_STATE_START); 1180 event = BGE_APE_EVENT_STATUS_STATE_START; 1181 break; 1182 case BGE_RESET_SHUTDOWN: 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1185 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1186 break; 1187 case BGE_RESET_SUSPEND: 1188 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1189 break; 1190 default: 1191 return; 1192 } 1193 1194 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1195 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1196 } 1197 1198 static uint8_t 1199 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1200 { 1201 uint32_t access, byte = 0; 1202 int i; 1203 1204 /* Lock. */ 1205 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1206 for (i = 0; i < 8000; i++) { 1207 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1208 break; 1209 DELAY(20); 1210 } 1211 if (i == 8000) 1212 return 1; 1213 1214 /* Enable access. */ 1215 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1216 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1217 1218 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1219 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1220 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1221 DELAY(10); 1222 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1223 DELAY(10); 1224 break; 1225 } 1226 } 1227 1228 if (i == BGE_TIMEOUT * 10) { 1229 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1230 return 1; 1231 } 1232 1233 /* Get result. */ 1234 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1235 1236 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1237 1238 /* Disable access. */ 1239 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1240 1241 /* Unlock. */ 1242 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1243 1244 return 0; 1245 } 1246 1247 /* 1248 * Read a sequence of bytes from NVRAM. 1249 */ 1250 static int 1251 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1252 { 1253 int error = 0, i; 1254 uint8_t byte = 0; 1255 1256 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1257 return 1; 1258 1259 for (i = 0; i < cnt; i++) { 1260 error = bge_nvram_getbyte(sc, off + i, &byte); 1261 if (error) 1262 break; 1263 *(dest + i) = byte; 1264 } 1265 1266 return (error ? 1 : 0); 1267 } 1268 1269 /* 1270 * Read a byte of data stored in the EEPROM at address 'addr.' The 1271 * BCM570x supports both the traditional bitbang interface and an 1272 * auto access interface for reading the EEPROM. We use the auto 1273 * access method. 1274 */ 1275 static uint8_t 1276 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1277 { 1278 int i; 1279 uint32_t byte = 0; 1280 1281 /* 1282 * Enable use of auto EEPROM access so we can avoid 1283 * having to use the bitbang method. 1284 */ 1285 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1286 1287 /* Reset the EEPROM, load the clock period. */ 1288 CSR_WRITE_4(sc, BGE_EE_ADDR, 1289 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1290 DELAY(20); 1291 1292 /* Issue the read EEPROM command. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1294 1295 /* Wait for completion */ 1296 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1297 DELAY(10); 1298 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1299 break; 1300 } 1301 1302 if (i == BGE_TIMEOUT * 10) { 1303 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1304 return 1; 1305 } 1306 1307 /* Get result. */ 1308 byte = CSR_READ_4(sc, BGE_EE_DATA); 1309 1310 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1311 1312 return 0; 1313 } 1314 1315 /* 1316 * Read a sequence of bytes from the EEPROM. 1317 */ 1318 static int 1319 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1320 { 1321 int error = 0, i; 1322 uint8_t byte = 0; 1323 char *dest = destv; 1324 1325 for (i = 0; i < cnt; i++) { 1326 error = bge_eeprom_getbyte(sc, off + i, &byte); 1327 if (error) 1328 break; 1329 *(dest + i) = byte; 1330 } 1331 1332 return (error ? 1 : 0); 1333 } 1334 1335 static int 1336 bge_miibus_readreg(device_t dev, int phy, int reg) 1337 { 1338 struct bge_softc *sc = device_private(dev); 1339 uint32_t val; 1340 uint32_t autopoll; 1341 int i; 1342 1343 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1344 return 0; 1345 1346 /* Reading with autopolling on may trigger PCI errors */ 1347 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1348 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1349 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1350 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1351 DELAY(80); 1352 } 1353 1354 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1355 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1356 1357 for (i = 0; i < BGE_TIMEOUT; i++) { 1358 delay(10); 1359 val = CSR_READ_4(sc, BGE_MI_COMM); 1360 if (!(val & BGE_MICOMM_BUSY)) { 1361 DELAY(5); 1362 val = CSR_READ_4(sc, BGE_MI_COMM); 1363 break; 1364 } 1365 } 1366 1367 if (i == BGE_TIMEOUT) { 1368 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1369 val = 0; 1370 goto done; 1371 } 1372 1373 done: 1374 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1375 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1376 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1377 DELAY(80); 1378 } 1379 1380 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1381 1382 if (val & BGE_MICOMM_READFAIL) 1383 return 0; 1384 1385 return (val & 0xFFFF); 1386 } 1387 1388 static void 1389 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1390 { 1391 struct bge_softc *sc = device_private(dev); 1392 uint32_t autopoll; 1393 int i; 1394 1395 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1396 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1397 return; 1398 1399 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1400 return; 1401 1402 /* Reading with autopolling on may trigger PCI errors */ 1403 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1404 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1405 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1406 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1407 DELAY(80); 1408 } 1409 1410 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1411 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1412 1413 for (i = 0; i < BGE_TIMEOUT; i++) { 1414 delay(10); 1415 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1416 delay(5); 1417 CSR_READ_4(sc, BGE_MI_COMM); 1418 break; 1419 } 1420 } 1421 1422 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1423 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1424 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1425 delay(80); 1426 } 1427 1428 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1429 1430 if (i == BGE_TIMEOUT) 1431 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1432 } 1433 1434 static void 1435 bge_miibus_statchg(struct ifnet *ifp) 1436 { 1437 struct bge_softc *sc = ifp->if_softc; 1438 struct mii_data *mii = &sc->bge_mii; 1439 uint32_t mac_mode, rx_mode, tx_mode; 1440 1441 /* 1442 * Get flow control negotiation result. 1443 */ 1444 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1445 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1446 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1447 1448 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1449 mii->mii_media_status & IFM_ACTIVE && 1450 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1451 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1452 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1453 (!(mii->mii_media_status & IFM_ACTIVE) || 1454 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1455 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1456 1457 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1458 return; 1459 1460 /* Set the port mode (MII/GMII) to match the link speed. */ 1461 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1462 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1463 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1464 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1465 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1466 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1467 mac_mode |= BGE_PORTMODE_GMII; 1468 else 1469 mac_mode |= BGE_PORTMODE_MII; 1470 1471 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1472 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1473 if ((mii->mii_media_active & IFM_FDX) != 0) { 1474 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1475 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1476 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1477 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1478 } else 1479 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1480 1481 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1482 DELAY(40); 1483 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1484 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1485 } 1486 1487 /* 1488 * Update rx threshold levels to values in a particular slot 1489 * of the interrupt-mitigation table bge_rx_threshes. 1490 */ 1491 static void 1492 bge_set_thresh(struct ifnet *ifp, int lvl) 1493 { 1494 struct bge_softc *sc = ifp->if_softc; 1495 int s; 1496 1497 /* For now, just save the new Rx-intr thresholds and record 1498 * that a threshold update is pending. Updating the hardware 1499 * registers here (even at splhigh()) is observed to 1500 * occasionaly cause glitches where Rx-interrupts are not 1501 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1502 */ 1503 s = splnet(); 1504 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1505 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1506 sc->bge_pending_rxintr_change = 1; 1507 splx(s); 1508 } 1509 1510 1511 /* 1512 * Update Rx thresholds of all bge devices 1513 */ 1514 static void 1515 bge_update_all_threshes(int lvl) 1516 { 1517 struct ifnet *ifp; 1518 const char * const namebuf = "bge"; 1519 int namelen; 1520 int s; 1521 1522 if (lvl < 0) 1523 lvl = 0; 1524 else if (lvl >= NBGE_RX_THRESH) 1525 lvl = NBGE_RX_THRESH - 1; 1526 1527 namelen = strlen(namebuf); 1528 /* 1529 * Now search all the interfaces for this name/number 1530 */ 1531 s = pserialize_read_enter(); 1532 IFNET_READER_FOREACH(ifp) { 1533 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1534 continue; 1535 /* We got a match: update if doing auto-threshold-tuning */ 1536 if (bge_auto_thresh) 1537 bge_set_thresh(ifp, lvl); 1538 } 1539 pserialize_read_exit(s); 1540 } 1541 1542 /* 1543 * Handle events that have triggered interrupts. 1544 */ 1545 static void 1546 bge_handle_events(struct bge_softc *sc) 1547 { 1548 1549 return; 1550 } 1551 1552 /* 1553 * Memory management for jumbo frames. 1554 */ 1555 1556 static int 1557 bge_alloc_jumbo_mem(struct bge_softc *sc) 1558 { 1559 char *ptr, *kva; 1560 bus_dma_segment_t seg; 1561 int i, rseg, state, error; 1562 struct bge_jpool_entry *entry; 1563 1564 state = error = 0; 1565 1566 /* Grab a big chunk o' storage. */ 1567 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1568 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1569 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1570 return ENOBUFS; 1571 } 1572 1573 state = 1; 1574 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1575 BUS_DMA_NOWAIT)) { 1576 aprint_error_dev(sc->bge_dev, 1577 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1578 error = ENOBUFS; 1579 goto out; 1580 } 1581 1582 state = 2; 1583 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1584 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1585 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1586 error = ENOBUFS; 1587 goto out; 1588 } 1589 1590 state = 3; 1591 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1592 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1593 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1594 error = ENOBUFS; 1595 goto out; 1596 } 1597 1598 state = 4; 1599 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1600 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1601 1602 SLIST_INIT(&sc->bge_jfree_listhead); 1603 SLIST_INIT(&sc->bge_jinuse_listhead); 1604 1605 /* 1606 * Now divide it up into 9K pieces and save the addresses 1607 * in an array. 1608 */ 1609 ptr = sc->bge_cdata.bge_jumbo_buf; 1610 for (i = 0; i < BGE_JSLOTS; i++) { 1611 sc->bge_cdata.bge_jslots[i] = ptr; 1612 ptr += BGE_JLEN; 1613 entry = malloc(sizeof(struct bge_jpool_entry), 1614 M_DEVBUF, M_NOWAIT); 1615 if (entry == NULL) { 1616 aprint_error_dev(sc->bge_dev, 1617 "no memory for jumbo buffer queue!\n"); 1618 error = ENOBUFS; 1619 goto out; 1620 } 1621 entry->slot = i; 1622 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1623 entry, jpool_entries); 1624 } 1625 out: 1626 if (error != 0) { 1627 switch (state) { 1628 case 4: 1629 bus_dmamap_unload(sc->bge_dmatag, 1630 sc->bge_cdata.bge_rx_jumbo_map); 1631 case 3: 1632 bus_dmamap_destroy(sc->bge_dmatag, 1633 sc->bge_cdata.bge_rx_jumbo_map); 1634 case 2: 1635 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1636 case 1: 1637 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1638 break; 1639 default: 1640 break; 1641 } 1642 } 1643 1644 return error; 1645 } 1646 1647 /* 1648 * Allocate a jumbo buffer. 1649 */ 1650 static void * 1651 bge_jalloc(struct bge_softc *sc) 1652 { 1653 struct bge_jpool_entry *entry; 1654 1655 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1656 1657 if (entry == NULL) { 1658 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1659 return NULL; 1660 } 1661 1662 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1663 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1664 return (sc->bge_cdata.bge_jslots[entry->slot]); 1665 } 1666 1667 /* 1668 * Release a jumbo buffer. 1669 */ 1670 static void 1671 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1672 { 1673 struct bge_jpool_entry *entry; 1674 struct bge_softc *sc; 1675 int i, s; 1676 1677 /* Extract the softc struct pointer. */ 1678 sc = (struct bge_softc *)arg; 1679 1680 if (sc == NULL) 1681 panic("bge_jfree: can't find softc pointer!"); 1682 1683 /* calculate the slot this buffer belongs to */ 1684 1685 i = ((char *)buf 1686 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1687 1688 if ((i < 0) || (i >= BGE_JSLOTS)) 1689 panic("bge_jfree: asked to free buffer that we don't manage!"); 1690 1691 s = splvm(); 1692 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1693 if (entry == NULL) 1694 panic("bge_jfree: buffer not in use!"); 1695 entry->slot = i; 1696 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1697 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1698 1699 if (__predict_true(m != NULL)) 1700 pool_cache_put(mb_cache, m); 1701 splx(s); 1702 } 1703 1704 1705 /* 1706 * Initialize a standard receive ring descriptor. 1707 */ 1708 static int 1709 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1710 bus_dmamap_t dmamap) 1711 { 1712 struct mbuf *m_new = NULL; 1713 struct bge_rx_bd *r; 1714 int error; 1715 1716 if (dmamap == NULL) { 1717 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1718 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1719 if (error != 0) 1720 return error; 1721 } 1722 1723 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1724 1725 if (m == NULL) { 1726 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1727 if (m_new == NULL) 1728 return ENOBUFS; 1729 1730 MCLGET(m_new, M_DONTWAIT); 1731 if (!(m_new->m_flags & M_EXT)) { 1732 m_freem(m_new); 1733 return ENOBUFS; 1734 } 1735 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1736 1737 } else { 1738 m_new = m; 1739 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1740 m_new->m_data = m_new->m_ext.ext_buf; 1741 } 1742 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1743 m_adj(m_new, ETHER_ALIGN); 1744 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1745 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1746 m_freem(m_new); 1747 return ENOBUFS; 1748 } 1749 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1750 BUS_DMASYNC_PREREAD); 1751 1752 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1753 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1754 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1755 r->bge_flags = BGE_RXBDFLAG_END; 1756 r->bge_len = m_new->m_len; 1757 r->bge_idx = i; 1758 1759 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1760 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1761 i * sizeof (struct bge_rx_bd), 1762 sizeof (struct bge_rx_bd), 1763 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1764 1765 return 0; 1766 } 1767 1768 /* 1769 * Initialize a jumbo receive ring descriptor. This allocates 1770 * a jumbo buffer from the pool managed internally by the driver. 1771 */ 1772 static int 1773 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1774 { 1775 struct mbuf *m_new = NULL; 1776 struct bge_rx_bd *r; 1777 void *buf = NULL; 1778 1779 if (m == NULL) { 1780 1781 /* Allocate the mbuf. */ 1782 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1783 if (m_new == NULL) 1784 return ENOBUFS; 1785 1786 /* Allocate the jumbo buffer */ 1787 buf = bge_jalloc(sc); 1788 if (buf == NULL) { 1789 m_freem(m_new); 1790 aprint_error_dev(sc->bge_dev, 1791 "jumbo allocation failed -- packet dropped!\n"); 1792 return ENOBUFS; 1793 } 1794 1795 /* Attach the buffer to the mbuf. */ 1796 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1797 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1798 bge_jfree, sc); 1799 m_new->m_flags |= M_EXT_RW; 1800 } else { 1801 m_new = m; 1802 buf = m_new->m_data = m_new->m_ext.ext_buf; 1803 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1804 } 1805 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1806 m_adj(m_new, ETHER_ALIGN); 1807 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1808 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1809 BUS_DMASYNC_PREREAD); 1810 /* Set up the descriptor. */ 1811 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1812 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1813 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1814 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1815 r->bge_len = m_new->m_len; 1816 r->bge_idx = i; 1817 1818 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1819 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1820 i * sizeof (struct bge_rx_bd), 1821 sizeof (struct bge_rx_bd), 1822 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1823 1824 return 0; 1825 } 1826 1827 /* 1828 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1829 * that's 1MB or memory, which is a lot. For now, we fill only the first 1830 * 256 ring entries and hope that our CPU is fast enough to keep up with 1831 * the NIC. 1832 */ 1833 static int 1834 bge_init_rx_ring_std(struct bge_softc *sc) 1835 { 1836 int i; 1837 1838 if (sc->bge_flags & BGEF_RXRING_VALID) 1839 return 0; 1840 1841 for (i = 0; i < BGE_SSLOTS; i++) { 1842 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1843 return ENOBUFS; 1844 } 1845 1846 sc->bge_std = i - 1; 1847 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1848 1849 sc->bge_flags |= BGEF_RXRING_VALID; 1850 1851 return 0; 1852 } 1853 1854 static void 1855 bge_free_rx_ring_std(struct bge_softc *sc) 1856 { 1857 int i; 1858 1859 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1860 return; 1861 1862 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1863 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1864 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1865 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1866 bus_dmamap_destroy(sc->bge_dmatag, 1867 sc->bge_cdata.bge_rx_std_map[i]); 1868 } 1869 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1870 sizeof(struct bge_rx_bd)); 1871 } 1872 1873 sc->bge_flags &= ~BGEF_RXRING_VALID; 1874 } 1875 1876 static int 1877 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1878 { 1879 int i; 1880 volatile struct bge_rcb *rcb; 1881 1882 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1883 return 0; 1884 1885 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1886 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1887 return ENOBUFS; 1888 } 1889 1890 sc->bge_jumbo = i - 1; 1891 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1892 1893 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1894 rcb->bge_maxlen_flags = 0; 1895 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1896 1897 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1898 1899 return 0; 1900 } 1901 1902 static void 1903 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1904 { 1905 int i; 1906 1907 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1908 return; 1909 1910 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1911 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1912 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1913 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1914 } 1915 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1916 sizeof(struct bge_rx_bd)); 1917 } 1918 1919 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1920 } 1921 1922 static void 1923 bge_free_tx_ring(struct bge_softc *sc) 1924 { 1925 int i; 1926 struct txdmamap_pool_entry *dma; 1927 1928 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1929 return; 1930 1931 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1932 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1933 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1934 sc->bge_cdata.bge_tx_chain[i] = NULL; 1935 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1936 link); 1937 sc->txdma[i] = 0; 1938 } 1939 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1940 sizeof(struct bge_tx_bd)); 1941 } 1942 1943 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1944 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1945 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1946 if (sc->bge_dma64) 1947 bus_dmamap_destroy(sc->bge_dmatag32, dma->dmamap32); 1948 free(dma, M_DEVBUF); 1949 } 1950 1951 sc->bge_flags &= ~BGEF_TXRING_VALID; 1952 } 1953 1954 static int 1955 bge_init_tx_ring(struct bge_softc *sc) 1956 { 1957 struct ifnet *ifp = &sc->ethercom.ec_if; 1958 int i; 1959 bus_dmamap_t dmamap, dmamap32; 1960 bus_size_t maxsegsz; 1961 struct txdmamap_pool_entry *dma; 1962 1963 if (sc->bge_flags & BGEF_TXRING_VALID) 1964 return 0; 1965 1966 sc->bge_txcnt = 0; 1967 sc->bge_tx_saved_considx = 0; 1968 1969 /* Initialize transmit producer index for host-memory send ring. */ 1970 sc->bge_tx_prodidx = 0; 1971 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1972 /* 5700 b2 errata */ 1973 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1974 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1975 1976 /* NIC-memory send ring not used; initialize to zero. */ 1977 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1978 /* 5700 b2 errata */ 1979 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1980 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1981 1982 /* Limit DMA segment size for some chips */ 1983 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1984 (ifp->if_mtu <= ETHERMTU)) 1985 maxsegsz = 2048; 1986 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1987 maxsegsz = 4096; 1988 else 1989 maxsegsz = ETHER_MAX_LEN_JUMBO; 1990 1991 SLIST_INIT(&sc->txdma_list); 1992 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1993 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1994 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1995 &dmamap)) 1996 return ENOBUFS; 1997 if (dmamap == NULL) 1998 panic("dmamap NULL in bge_init_tx_ring"); 1999 if (sc->bge_dma64) { 2000 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 2001 BGE_NTXSEG, maxsegsz, 0, 2002 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2003 &dmamap32)) { 2004 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2005 return ENOBUFS; 2006 } 2007 if (dmamap32 == NULL) 2008 panic("dmamap32 NULL in bge_init_tx_ring"); 2009 } else 2010 dmamap32 = dmamap; 2011 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 2012 if (dma == NULL) { 2013 aprint_error_dev(sc->bge_dev, 2014 "can't alloc txdmamap_pool_entry\n"); 2015 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2016 if (sc->bge_dma64) 2017 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 2018 return ENOMEM; 2019 } 2020 dma->dmamap = dmamap; 2021 dma->dmamap32 = dmamap32; 2022 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2023 } 2024 2025 sc->bge_flags |= BGEF_TXRING_VALID; 2026 2027 return 0; 2028 } 2029 2030 static void 2031 bge_setmulti(struct bge_softc *sc) 2032 { 2033 struct ethercom *ac = &sc->ethercom; 2034 struct ifnet *ifp = &ac->ec_if; 2035 struct ether_multi *enm; 2036 struct ether_multistep step; 2037 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2038 uint32_t h; 2039 int i; 2040 2041 if (ifp->if_flags & IFF_PROMISC) 2042 goto allmulti; 2043 2044 /* Now program new ones. */ 2045 ETHER_FIRST_MULTI(step, ac, enm); 2046 while (enm != NULL) { 2047 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2048 /* 2049 * We must listen to a range of multicast addresses. 2050 * For now, just accept all multicasts, rather than 2051 * trying to set only those filter bits needed to match 2052 * the range. (At this time, the only use of address 2053 * ranges is for IP multicast routing, for which the 2054 * range is big enough to require all bits set.) 2055 */ 2056 goto allmulti; 2057 } 2058 2059 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2060 2061 /* Just want the 7 least-significant bits. */ 2062 h &= 0x7f; 2063 2064 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2065 ETHER_NEXT_MULTI(step, enm); 2066 } 2067 2068 ifp->if_flags &= ~IFF_ALLMULTI; 2069 goto setit; 2070 2071 allmulti: 2072 ifp->if_flags |= IFF_ALLMULTI; 2073 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2074 2075 setit: 2076 for (i = 0; i < 4; i++) 2077 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2078 } 2079 2080 static void 2081 bge_sig_pre_reset(struct bge_softc *sc, int type) 2082 { 2083 2084 /* 2085 * Some chips don't like this so only do this if ASF is enabled 2086 */ 2087 if (sc->bge_asf_mode) 2088 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2089 2090 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2091 switch (type) { 2092 case BGE_RESET_START: 2093 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2094 BGE_FW_DRV_STATE_START); 2095 break; 2096 case BGE_RESET_SHUTDOWN: 2097 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2098 BGE_FW_DRV_STATE_UNLOAD); 2099 break; 2100 case BGE_RESET_SUSPEND: 2101 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2102 BGE_FW_DRV_STATE_SUSPEND); 2103 break; 2104 } 2105 } 2106 2107 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2108 bge_ape_driver_state_change(sc, type); 2109 } 2110 2111 static void 2112 bge_sig_post_reset(struct bge_softc *sc, int type) 2113 { 2114 2115 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2116 switch (type) { 2117 case BGE_RESET_START: 2118 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2119 BGE_FW_DRV_STATE_START_DONE); 2120 /* START DONE */ 2121 break; 2122 case BGE_RESET_SHUTDOWN: 2123 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2124 BGE_FW_DRV_STATE_UNLOAD_DONE); 2125 break; 2126 } 2127 } 2128 2129 if (type == BGE_RESET_SHUTDOWN) 2130 bge_ape_driver_state_change(sc, type); 2131 } 2132 2133 static void 2134 bge_sig_legacy(struct bge_softc *sc, int type) 2135 { 2136 2137 if (sc->bge_asf_mode) { 2138 switch (type) { 2139 case BGE_RESET_START: 2140 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2141 BGE_FW_DRV_STATE_START); 2142 break; 2143 case BGE_RESET_SHUTDOWN: 2144 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2145 BGE_FW_DRV_STATE_UNLOAD); 2146 break; 2147 } 2148 } 2149 } 2150 2151 static void 2152 bge_wait_for_event_ack(struct bge_softc *sc) 2153 { 2154 int i; 2155 2156 /* wait up to 2500usec */ 2157 for (i = 0; i < 250; i++) { 2158 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2159 BGE_RX_CPU_DRV_EVENT)) 2160 break; 2161 DELAY(10); 2162 } 2163 } 2164 2165 static void 2166 bge_stop_fw(struct bge_softc *sc) 2167 { 2168 2169 if (sc->bge_asf_mode) { 2170 bge_wait_for_event_ack(sc); 2171 2172 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2173 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2174 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2175 2176 bge_wait_for_event_ack(sc); 2177 } 2178 } 2179 2180 static int 2181 bge_poll_fw(struct bge_softc *sc) 2182 { 2183 uint32_t val; 2184 int i; 2185 2186 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2187 for (i = 0; i < BGE_TIMEOUT; i++) { 2188 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2189 if (val & BGE_VCPU_STATUS_INIT_DONE) 2190 break; 2191 DELAY(100); 2192 } 2193 if (i >= BGE_TIMEOUT) { 2194 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2195 return -1; 2196 } 2197 } else { 2198 /* 2199 * Poll the value location we just wrote until 2200 * we see the 1's complement of the magic number. 2201 * This indicates that the firmware initialization 2202 * is complete. 2203 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2204 */ 2205 for (i = 0; i < BGE_TIMEOUT; i++) { 2206 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2207 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2208 break; 2209 DELAY(10); 2210 } 2211 2212 if ((i >= BGE_TIMEOUT) 2213 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2214 aprint_error_dev(sc->bge_dev, 2215 "firmware handshake timed out, val = %x\n", val); 2216 return -1; 2217 } 2218 } 2219 2220 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2221 /* tg3 says we have to wait extra time */ 2222 delay(10 * 1000); 2223 } 2224 2225 return 0; 2226 } 2227 2228 int 2229 bge_phy_addr(struct bge_softc *sc) 2230 { 2231 struct pci_attach_args *pa = &(sc->bge_pa); 2232 int phy_addr = 1; 2233 2234 /* 2235 * PHY address mapping for various devices. 2236 * 2237 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2238 * ---------+-------+-------+-------+-------+ 2239 * BCM57XX | 1 | X | X | X | 2240 * BCM5704 | 1 | X | 1 | X | 2241 * BCM5717 | 1 | 8 | 2 | 9 | 2242 * BCM5719 | 1 | 8 | 2 | 9 | 2243 * BCM5720 | 1 | 8 | 2 | 9 | 2244 * 2245 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2246 * ---------+-------+-------+-------+-------+ 2247 * BCM57XX | X | X | X | X | 2248 * BCM5704 | X | X | X | X | 2249 * BCM5717 | X | X | X | X | 2250 * BCM5719 | 3 | 10 | 4 | 11 | 2251 * BCM5720 | X | X | X | X | 2252 * 2253 * Other addresses may respond but they are not 2254 * IEEE compliant PHYs and should be ignored. 2255 */ 2256 switch (BGE_ASICREV(sc->bge_chipid)) { 2257 case BGE_ASICREV_BCM5717: 2258 case BGE_ASICREV_BCM5719: 2259 case BGE_ASICREV_BCM5720: 2260 phy_addr = pa->pa_function; 2261 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2262 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2263 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2264 } else { 2265 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2266 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2267 } 2268 } 2269 2270 return phy_addr; 2271 } 2272 2273 /* 2274 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2275 * self-test results. 2276 */ 2277 static int 2278 bge_chipinit(struct bge_softc *sc) 2279 { 2280 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2281 int i; 2282 2283 /* Set endianness before we access any non-PCI registers. */ 2284 misc_ctl = BGE_INIT; 2285 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2286 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2287 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2288 misc_ctl); 2289 2290 /* 2291 * Clear the MAC statistics block in the NIC's 2292 * internal memory. 2293 */ 2294 for (i = BGE_STATS_BLOCK; 2295 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2296 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2297 2298 for (i = BGE_STATUS_BLOCK; 2299 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2300 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2301 2302 /* 5717 workaround from tg3 */ 2303 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2304 /* Save */ 2305 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2306 2307 /* Temporary modify MODE_CTL to control TLP */ 2308 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2309 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2310 2311 /* Control TLP */ 2312 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2313 BGE_TLP_PHYCTL1); 2314 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2315 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2316 2317 /* Restore */ 2318 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2319 } 2320 2321 if (BGE_IS_57765_FAMILY(sc)) { 2322 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2323 /* Save */ 2324 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2325 2326 /* Temporary modify MODE_CTL to control TLP */ 2327 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2328 CSR_WRITE_4(sc, BGE_MODE_CTL, 2329 reg | BGE_MODECTL_PCIE_TLPADDR1); 2330 2331 /* Control TLP */ 2332 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2333 BGE_TLP_PHYCTL5); 2334 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2335 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2336 2337 /* Restore */ 2338 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2339 } 2340 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2341 /* 2342 * For the 57766 and non Ax versions of 57765, bootcode 2343 * needs to setup the PCIE Fast Training Sequence (FTS) 2344 * value to prevent transmit hangs. 2345 */ 2346 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2347 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2348 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2349 2350 /* Save */ 2351 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2352 2353 /* Temporary modify MODE_CTL to control TLP */ 2354 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2355 CSR_WRITE_4(sc, BGE_MODE_CTL, 2356 reg | BGE_MODECTL_PCIE_TLPADDR0); 2357 2358 /* Control TLP */ 2359 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2360 BGE_TLP_FTSMAX); 2361 reg &= ~BGE_TLP_FTSMAX_MSK; 2362 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2363 reg | BGE_TLP_FTSMAX_VAL); 2364 2365 /* Restore */ 2366 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2367 } 2368 2369 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2370 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2371 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2372 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2373 } 2374 2375 /* Set up the PCI DMA control register. */ 2376 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2377 if (sc->bge_flags & BGEF_PCIE) { 2378 /* Read watermark not used, 128 bytes for write. */ 2379 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2380 device_xname(sc->bge_dev))); 2381 if (sc->bge_mps >= 256) 2382 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2383 else 2384 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2385 } else if (sc->bge_flags & BGEF_PCIX) { 2386 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2387 device_xname(sc->bge_dev))); 2388 /* PCI-X bus */ 2389 if (BGE_IS_5714_FAMILY(sc)) { 2390 /* 256 bytes for read and write. */ 2391 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2392 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2393 2394 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2395 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2396 else 2397 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2398 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2399 /* 2400 * In the BCM5703, the DMA read watermark should 2401 * be set to less than or equal to the maximum 2402 * memory read byte count of the PCI-X command 2403 * register. 2404 */ 2405 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2406 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2407 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2408 /* 1536 bytes for read, 384 bytes for write. */ 2409 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2410 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2411 } else { 2412 /* 384 bytes for read and write. */ 2413 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2414 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2415 (0x0F); 2416 } 2417 2418 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2419 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2420 uint32_t tmp; 2421 2422 /* Set ONEDMA_ATONCE for hardware workaround. */ 2423 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2424 if (tmp == 6 || tmp == 7) 2425 dma_rw_ctl |= 2426 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2427 2428 /* Set PCI-X DMA write workaround. */ 2429 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2430 } 2431 } else { 2432 /* Conventional PCI bus: 256 bytes for read and write. */ 2433 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2434 device_xname(sc->bge_dev))); 2435 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2436 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2437 2438 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2439 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2440 dma_rw_ctl |= 0x0F; 2441 } 2442 2443 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2444 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2445 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2446 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2447 2448 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2449 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2450 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2451 2452 if (BGE_IS_57765_PLUS(sc)) { 2453 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2454 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2455 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2456 2457 /* 2458 * Enable HW workaround for controllers that misinterpret 2459 * a status tag update and leave interrupts permanently 2460 * disabled. 2461 */ 2462 if (!BGE_IS_57765_FAMILY(sc) && 2463 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2464 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2465 } 2466 2467 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2468 dma_rw_ctl); 2469 2470 /* 2471 * Set up general mode register. 2472 */ 2473 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2474 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2475 /* Retain Host-2-BMC settings written by APE firmware. */ 2476 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2477 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2478 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2479 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2480 } 2481 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2482 BGE_MODECTL_TX_NO_PHDR_CSUM; 2483 2484 /* 2485 * BCM5701 B5 have a bug causing data corruption when using 2486 * 64-bit DMA reads, which can be terminated early and then 2487 * completed later as 32-bit accesses, in combination with 2488 * certain bridges. 2489 */ 2490 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2491 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2492 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2493 2494 /* 2495 * Tell the firmware the driver is running 2496 */ 2497 if (sc->bge_asf_mode & ASF_STACKUP) 2498 mode_ctl |= BGE_MODECTL_STACKUP; 2499 2500 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2501 2502 /* 2503 * Disable memory write invalidate. Apparently it is not supported 2504 * properly by these devices. 2505 */ 2506 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2507 PCI_COMMAND_INVALIDATE_ENABLE); 2508 2509 #ifdef __brokenalpha__ 2510 /* 2511 * Must insure that we do not cross an 8K (bytes) boundary 2512 * for DMA reads. Our highest limit is 1K bytes. This is a 2513 * restriction on some ALPHA platforms with early revision 2514 * 21174 PCI chipsets, such as the AlphaPC 164lx 2515 */ 2516 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2517 #endif 2518 2519 /* Set the timer prescaler (always 66MHz) */ 2520 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2521 2522 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2523 DELAY(40); /* XXX */ 2524 2525 /* Put PHY into ready state */ 2526 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2527 DELAY(40); 2528 } 2529 2530 return 0; 2531 } 2532 2533 static int 2534 bge_blockinit(struct bge_softc *sc) 2535 { 2536 volatile struct bge_rcb *rcb; 2537 bus_size_t rcb_addr; 2538 struct ifnet *ifp = &sc->ethercom.ec_if; 2539 bge_hostaddr taddr; 2540 uint32_t dmactl, mimode, val; 2541 int i, limit; 2542 2543 /* 2544 * Initialize the memory window pointer register so that 2545 * we can access the first 32K of internal NIC RAM. This will 2546 * allow us to set up the TX send ring RCBs and the RX return 2547 * ring RCBs, plus other things which live in NIC memory. 2548 */ 2549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2550 2551 if (!BGE_IS_5705_PLUS(sc)) { 2552 /* 57XX step 33 */ 2553 /* Configure mbuf memory pool */ 2554 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2555 BGE_BUFFPOOL_1); 2556 2557 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2558 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2559 else 2560 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2561 2562 /* 57XX step 34 */ 2563 /* Configure DMA resource pool */ 2564 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2565 BGE_DMA_DESCRIPTORS); 2566 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2567 } 2568 2569 /* 5718 step 11, 57XX step 35 */ 2570 /* 2571 * Configure mbuf pool watermarks. New broadcom docs strongly 2572 * recommend these. 2573 */ 2574 if (BGE_IS_5717_PLUS(sc)) { 2575 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2576 if (ifp->if_mtu > ETHERMTU) { 2577 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2578 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2579 } else { 2580 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2581 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2582 } 2583 } else if (BGE_IS_5705_PLUS(sc)) { 2584 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2585 2586 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2587 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2588 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2589 } else { 2590 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2591 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2592 } 2593 } else { 2594 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2595 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2596 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2597 } 2598 2599 /* 57XX step 36 */ 2600 /* Configure DMA resource watermarks */ 2601 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2602 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2603 2604 /* 5718 step 13, 57XX step 38 */ 2605 /* Enable buffer manager */ 2606 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2607 /* 2608 * Change the arbitration algorithm of TXMBUF read request to 2609 * round-robin instead of priority based for BCM5719. When 2610 * TXFIFO is almost empty, RDMA will hold its request until 2611 * TXFIFO is not almost empty. 2612 */ 2613 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2614 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2615 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2616 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2617 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2618 val |= BGE_BMANMODE_LOMBUF_ATTN; 2619 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2620 2621 /* 57XX step 39 */ 2622 /* Poll for buffer manager start indication */ 2623 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2624 DELAY(10); 2625 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2626 break; 2627 } 2628 2629 if (i == BGE_TIMEOUT * 2) { 2630 aprint_error_dev(sc->bge_dev, 2631 "buffer manager failed to start\n"); 2632 return ENXIO; 2633 } 2634 2635 /* 57XX step 40 */ 2636 /* Enable flow-through queues */ 2637 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2638 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2639 2640 /* Wait until queue initialization is complete */ 2641 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2642 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2643 break; 2644 DELAY(10); 2645 } 2646 2647 if (i == BGE_TIMEOUT * 2) { 2648 aprint_error_dev(sc->bge_dev, 2649 "flow-through queue init failed\n"); 2650 return ENXIO; 2651 } 2652 2653 /* 2654 * Summary of rings supported by the controller: 2655 * 2656 * Standard Receive Producer Ring 2657 * - This ring is used to feed receive buffers for "standard" 2658 * sized frames (typically 1536 bytes) to the controller. 2659 * 2660 * Jumbo Receive Producer Ring 2661 * - This ring is used to feed receive buffers for jumbo sized 2662 * frames (i.e. anything bigger than the "standard" frames) 2663 * to the controller. 2664 * 2665 * Mini Receive Producer Ring 2666 * - This ring is used to feed receive buffers for "mini" 2667 * sized frames to the controller. 2668 * - This feature required external memory for the controller 2669 * but was never used in a production system. Should always 2670 * be disabled. 2671 * 2672 * Receive Return Ring 2673 * - After the controller has placed an incoming frame into a 2674 * receive buffer that buffer is moved into a receive return 2675 * ring. The driver is then responsible to passing the 2676 * buffer up to the stack. Many versions of the controller 2677 * support multiple RR rings. 2678 * 2679 * Send Ring 2680 * - This ring is used for outgoing frames. Many versions of 2681 * the controller support multiple send rings. 2682 */ 2683 2684 /* 5718 step 15, 57XX step 41 */ 2685 /* Initialize the standard RX ring control block */ 2686 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2687 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2688 /* 5718 step 16 */ 2689 if (BGE_IS_57765_PLUS(sc)) { 2690 /* 2691 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2692 * Bits 15-2 : Maximum RX frame size 2693 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2694 * Bit 0 : Reserved 2695 */ 2696 rcb->bge_maxlen_flags = 2697 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2698 } else if (BGE_IS_5705_PLUS(sc)) { 2699 /* 2700 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2701 * Bits 15-2 : Reserved (should be 0) 2702 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2703 * Bit 0 : Reserved 2704 */ 2705 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2706 } else { 2707 /* 2708 * Ring size is always XXX entries 2709 * Bits 31-16: Maximum RX frame size 2710 * Bits 15-2 : Reserved (should be 0) 2711 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2712 * Bit 0 : Reserved 2713 */ 2714 rcb->bge_maxlen_flags = 2715 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2716 } 2717 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2718 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2719 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2720 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2721 else 2722 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2723 /* Write the standard receive producer ring control block. */ 2724 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2725 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2726 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2727 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2728 2729 /* Reset the standard receive producer ring producer index. */ 2730 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2731 2732 /* 57XX step 42 */ 2733 /* 2734 * Initialize the jumbo RX ring control block 2735 * We set the 'ring disabled' bit in the flags 2736 * field until we're actually ready to start 2737 * using this ring (i.e. once we set the MTU 2738 * high enough to require it). 2739 */ 2740 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2741 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2742 BGE_HOSTADDR(rcb->bge_hostaddr, 2743 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2744 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2745 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2746 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2747 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2748 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2749 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2750 else 2751 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2752 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2753 rcb->bge_hostaddr.bge_addr_hi); 2754 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2755 rcb->bge_hostaddr.bge_addr_lo); 2756 /* Program the jumbo receive producer ring RCB parameters. */ 2757 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2758 rcb->bge_maxlen_flags); 2759 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2760 /* Reset the jumbo receive producer ring producer index. */ 2761 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2762 } 2763 2764 /* 57XX step 43 */ 2765 /* Disable the mini receive producer ring RCB. */ 2766 if (BGE_IS_5700_FAMILY(sc)) { 2767 /* Set up dummy disabled mini ring RCB */ 2768 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2769 rcb->bge_maxlen_flags = 2770 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2771 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2772 rcb->bge_maxlen_flags); 2773 /* Reset the mini receive producer ring producer index. */ 2774 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2775 2776 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2777 offsetof(struct bge_ring_data, bge_info), 2778 sizeof (struct bge_gib), 2779 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2780 } 2781 2782 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2783 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2784 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2785 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2786 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2787 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2788 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2789 } 2790 /* 5718 step 14, 57XX step 44 */ 2791 /* 2792 * The BD ring replenish thresholds control how often the 2793 * hardware fetches new BD's from the producer rings in host 2794 * memory. Setting the value too low on a busy system can 2795 * starve the hardware and recue the throughpout. 2796 * 2797 * Set the BD ring replenish thresholds. The recommended 2798 * values are 1/8th the number of descriptors allocated to 2799 * each ring, but since we try to avoid filling the entire 2800 * ring we set these to the minimal value of 8. This needs to 2801 * be done on several of the supported chip revisions anyway, 2802 * to work around HW bugs. 2803 */ 2804 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2805 if (BGE_IS_JUMBO_CAPABLE(sc)) 2806 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2807 2808 /* 5718 step 18 */ 2809 if (BGE_IS_5717_PLUS(sc)) { 2810 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2811 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2812 } 2813 2814 /* 57XX step 45 */ 2815 /* 2816 * Disable all send rings by setting the 'ring disabled' bit 2817 * in the flags field of all the TX send ring control blocks, 2818 * located in NIC memory. 2819 */ 2820 if (BGE_IS_5700_FAMILY(sc)) { 2821 /* 5700 to 5704 had 16 send rings. */ 2822 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2823 } else if (BGE_IS_5717_PLUS(sc)) { 2824 limit = BGE_TX_RINGS_5717_MAX; 2825 } else if (BGE_IS_57765_FAMILY(sc)) { 2826 limit = BGE_TX_RINGS_57765_MAX; 2827 } else 2828 limit = 1; 2829 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2830 for (i = 0; i < limit; i++) { 2831 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2832 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2833 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2834 rcb_addr += sizeof(struct bge_rcb); 2835 } 2836 2837 /* 57XX step 46 and 47 */ 2838 /* Configure send ring RCB 0 (we use only the first ring) */ 2839 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2840 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2841 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2842 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2843 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2844 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2845 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2846 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2847 else 2848 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2849 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2850 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2851 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2852 2853 /* 57XX step 48 */ 2854 /* 2855 * Disable all receive return rings by setting the 2856 * 'ring diabled' bit in the flags field of all the receive 2857 * return ring control blocks, located in NIC memory. 2858 */ 2859 if (BGE_IS_5717_PLUS(sc)) { 2860 /* Should be 17, use 16 until we get an SRAM map. */ 2861 limit = 16; 2862 } else if (BGE_IS_5700_FAMILY(sc)) 2863 limit = BGE_RX_RINGS_MAX; 2864 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2865 BGE_IS_57765_FAMILY(sc)) 2866 limit = 4; 2867 else 2868 limit = 1; 2869 /* Disable all receive return rings */ 2870 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2871 for (i = 0; i < limit; i++) { 2872 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2873 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2874 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2875 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2876 BGE_RCB_FLAG_RING_DISABLED)); 2877 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2878 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2879 (i * (sizeof(uint64_t))), 0); 2880 rcb_addr += sizeof(struct bge_rcb); 2881 } 2882 2883 /* 57XX step 49 */ 2884 /* 2885 * Set up receive return ring 0. Note that the NIC address 2886 * for RX return rings is 0x0. The return rings live entirely 2887 * within the host, so the nicaddr field in the RCB isn't used. 2888 */ 2889 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2890 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2891 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2892 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2893 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2894 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2895 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2896 2897 /* 5718 step 24, 57XX step 53 */ 2898 /* Set random backoff seed for TX */ 2899 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2900 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2901 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2902 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2903 BGE_TX_BACKOFF_SEED_MASK); 2904 2905 /* 5718 step 26, 57XX step 55 */ 2906 /* Set inter-packet gap */ 2907 val = 0x2620; 2908 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2909 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2910 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2911 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2912 2913 /* 5718 step 27, 57XX step 56 */ 2914 /* 2915 * Specify which ring to use for packets that don't match 2916 * any RX rules. 2917 */ 2918 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2919 2920 /* 5718 step 28, 57XX step 57 */ 2921 /* 2922 * Configure number of RX lists. One interrupt distribution 2923 * list, sixteen active lists, one bad frames class. 2924 */ 2925 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2926 2927 /* 5718 step 29, 57XX step 58 */ 2928 /* Inialize RX list placement stats mask. */ 2929 if (BGE_IS_575X_PLUS(sc)) { 2930 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2931 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2932 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2933 } else 2934 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2935 2936 /* 5718 step 30, 57XX step 59 */ 2937 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2938 2939 /* 5718 step 33, 57XX step 62 */ 2940 /* Disable host coalescing until we get it set up */ 2941 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2942 2943 /* 5718 step 34, 57XX step 63 */ 2944 /* Poll to make sure it's shut down. */ 2945 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2946 DELAY(10); 2947 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2948 break; 2949 } 2950 2951 if (i == BGE_TIMEOUT * 2) { 2952 aprint_error_dev(sc->bge_dev, 2953 "host coalescing engine failed to idle\n"); 2954 return ENXIO; 2955 } 2956 2957 /* 5718 step 35, 36, 37 */ 2958 /* Set up host coalescing defaults */ 2959 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2960 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2961 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2962 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2963 if (!(BGE_IS_5705_PLUS(sc))) { 2964 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2965 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2966 } 2967 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2968 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2969 2970 /* Set up address of statistics block */ 2971 if (BGE_IS_5700_FAMILY(sc)) { 2972 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2973 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2974 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2975 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2976 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2977 } 2978 2979 /* 5718 step 38 */ 2980 /* Set up address of status block */ 2981 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2982 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2983 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2984 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2985 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2986 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2987 2988 /* Set up status block size. */ 2989 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2990 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2991 val = BGE_STATBLKSZ_FULL; 2992 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2993 } else { 2994 val = BGE_STATBLKSZ_32BYTE; 2995 bzero(&sc->bge_rdata->bge_status_block, 32); 2996 } 2997 2998 /* 5718 step 39, 57XX step 73 */ 2999 /* Turn on host coalescing state machine */ 3000 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 3001 3002 /* 5718 step 40, 57XX step 74 */ 3003 /* Turn on RX BD completion state machine and enable attentions */ 3004 CSR_WRITE_4(sc, BGE_RBDC_MODE, 3005 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 3006 3007 /* 5718 step 41, 57XX step 75 */ 3008 /* Turn on RX list placement state machine */ 3009 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3010 3011 /* 57XX step 76 */ 3012 /* Turn on RX list selector state machine. */ 3013 if (!(BGE_IS_5705_PLUS(sc))) 3014 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3015 3016 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 3017 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 3018 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 3019 BGE_MACMODE_FRMHDR_DMA_ENB; 3020 3021 if (sc->bge_flags & BGEF_FIBER_TBI) 3022 val |= BGE_PORTMODE_TBI; 3023 else if (sc->bge_flags & BGEF_FIBER_MII) 3024 val |= BGE_PORTMODE_GMII; 3025 else 3026 val |= BGE_PORTMODE_MII; 3027 3028 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 3029 /* Allow APE to send/receive frames. */ 3030 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3031 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3032 3033 /* Turn on DMA, clear stats */ 3034 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3035 /* 5718 step 44 */ 3036 DELAY(40); 3037 3038 /* 5718 step 45, 57XX step 79 */ 3039 /* Set misc. local control, enable interrupts on attentions */ 3040 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3041 if (BGE_IS_5717_PLUS(sc)) { 3042 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3043 /* 5718 step 46 */ 3044 DELAY(100); 3045 } 3046 3047 /* 57XX step 81 */ 3048 /* Turn on DMA completion state machine */ 3049 if (!(BGE_IS_5705_PLUS(sc))) 3050 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3051 3052 /* 5718 step 47, 57XX step 82 */ 3053 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3054 3055 /* 5718 step 48 */ 3056 /* Enable host coalescing bug fix. */ 3057 if (BGE_IS_5755_PLUS(sc)) 3058 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3059 3060 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3061 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3062 3063 /* Turn on write DMA state machine */ 3064 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3065 /* 5718 step 49 */ 3066 DELAY(40); 3067 3068 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3069 3070 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3071 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3072 3073 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3074 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3075 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3076 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3077 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3078 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3079 3080 if (sc->bge_flags & BGEF_PCIE) 3081 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3082 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3083 if (ifp->if_mtu <= ETHERMTU) 3084 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3085 } 3086 if (sc->bge_flags & BGEF_TSO) { 3087 val |= BGE_RDMAMODE_TSO4_ENABLE; 3088 if (BGE_IS_5717_PLUS(sc)) 3089 val |= BGE_RDMAMODE_TSO6_ENABLE; 3090 } 3091 3092 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3093 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3094 BGE_RDMAMODE_H2BNC_VLAN_DET; 3095 /* 3096 * Allow multiple outstanding read requests from 3097 * non-LSO read DMA engine. 3098 */ 3099 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3100 } 3101 3102 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3103 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3104 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3105 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3106 BGE_IS_57765_PLUS(sc)) { 3107 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3108 /* 3109 * Adjust tx margin to prevent TX data corruption and 3110 * fix internal FIFO overflow. 3111 */ 3112 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3113 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3114 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3115 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3116 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3117 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3118 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3119 } 3120 /* 3121 * Enable fix for read DMA FIFO overruns. 3122 * The fix is to limit the number of RX BDs 3123 * the hardware would fetch at a fime. 3124 */ 3125 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3126 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3127 } 3128 3129 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3130 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3131 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3132 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3133 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3134 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3135 /* 3136 * Allow 4KB burst length reads for non-LSO frames. 3137 * Enable 512B burst length reads for buffer descriptors. 3138 */ 3139 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3140 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3141 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3142 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3143 } 3144 3145 /* Turn on read DMA state machine */ 3146 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3147 /* 5718 step 52 */ 3148 delay(40); 3149 3150 /* 5718 step 56, 57XX step 84 */ 3151 /* Turn on RX data completion state machine */ 3152 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3153 3154 /* Turn on RX data and RX BD initiator state machine */ 3155 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3156 3157 /* 57XX step 85 */ 3158 /* Turn on Mbuf cluster free state machine */ 3159 if (!BGE_IS_5705_PLUS(sc)) 3160 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3161 3162 /* 5718 step 57, 57XX step 86 */ 3163 /* Turn on send data completion state machine */ 3164 val = BGE_SDCMODE_ENABLE; 3165 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3166 val |= BGE_SDCMODE_CDELAY; 3167 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3168 3169 /* 5718 step 58 */ 3170 /* Turn on send BD completion state machine */ 3171 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3172 3173 /* 57XX step 88 */ 3174 /* Turn on RX BD initiator state machine */ 3175 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3176 3177 /* 5718 step 60, 57XX step 90 */ 3178 /* Turn on send data initiator state machine */ 3179 if (sc->bge_flags & BGEF_TSO) { 3180 /* XXX: magic value from Linux driver */ 3181 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3182 BGE_SDIMODE_HW_LSO_PRE_DMA); 3183 } else 3184 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3185 3186 /* 5718 step 61, 57XX step 91 */ 3187 /* Turn on send BD initiator state machine */ 3188 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3189 3190 /* 5718 step 62, 57XX step 92 */ 3191 /* Turn on send BD selector state machine */ 3192 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3193 3194 /* 5718 step 31, 57XX step 60 */ 3195 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3196 /* 5718 step 32, 57XX step 61 */ 3197 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3198 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3199 3200 /* ack/clear link change events */ 3201 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3202 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3203 BGE_MACSTAT_LINK_CHANGED); 3204 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3205 3206 /* 3207 * Enable attention when the link has changed state for 3208 * devices that use auto polling. 3209 */ 3210 if (sc->bge_flags & BGEF_FIBER_TBI) { 3211 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3212 } else { 3213 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3214 mimode = BGE_MIMODE_500KHZ_CONST; 3215 else 3216 mimode = BGE_MIMODE_BASE; 3217 /* 5718 step 68. 5718 step 69 (optionally). */ 3218 if (BGE_IS_5700_FAMILY(sc) || 3219 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3220 mimode |= BGE_MIMODE_AUTOPOLL; 3221 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3222 } 3223 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3224 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3225 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3226 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3227 BGE_EVTENB_MI_INTERRUPT); 3228 } 3229 3230 /* 3231 * Clear any pending link state attention. 3232 * Otherwise some link state change events may be lost until attention 3233 * is cleared by bge_intr() -> bge_link_upd() sequence. 3234 * It's not necessary on newer BCM chips - perhaps enabling link 3235 * state change attentions implies clearing pending attention. 3236 */ 3237 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3238 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3239 BGE_MACSTAT_LINK_CHANGED); 3240 3241 /* Enable link state change attentions. */ 3242 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3243 3244 return 0; 3245 } 3246 3247 static const struct bge_revision * 3248 bge_lookup_rev(uint32_t chipid) 3249 { 3250 const struct bge_revision *br; 3251 3252 for (br = bge_revisions; br->br_name != NULL; br++) { 3253 if (br->br_chipid == chipid) 3254 return br; 3255 } 3256 3257 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3258 if (br->br_chipid == BGE_ASICREV(chipid)) 3259 return br; 3260 } 3261 3262 return NULL; 3263 } 3264 3265 static const struct bge_product * 3266 bge_lookup(const struct pci_attach_args *pa) 3267 { 3268 const struct bge_product *bp; 3269 3270 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3271 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3272 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3273 return bp; 3274 } 3275 3276 return NULL; 3277 } 3278 3279 static uint32_t 3280 bge_chipid(const struct pci_attach_args *pa) 3281 { 3282 uint32_t id; 3283 3284 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3285 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3286 3287 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3288 switch (PCI_PRODUCT(pa->pa_id)) { 3289 case PCI_PRODUCT_BROADCOM_BCM5717: 3290 case PCI_PRODUCT_BROADCOM_BCM5718: 3291 case PCI_PRODUCT_BROADCOM_BCM5719: 3292 case PCI_PRODUCT_BROADCOM_BCM5720: 3293 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3294 BGE_PCI_GEN2_PRODID_ASICREV); 3295 break; 3296 case PCI_PRODUCT_BROADCOM_BCM57761: 3297 case PCI_PRODUCT_BROADCOM_BCM57762: 3298 case PCI_PRODUCT_BROADCOM_BCM57765: 3299 case PCI_PRODUCT_BROADCOM_BCM57766: 3300 case PCI_PRODUCT_BROADCOM_BCM57781: 3301 case PCI_PRODUCT_BROADCOM_BCM57782: 3302 case PCI_PRODUCT_BROADCOM_BCM57785: 3303 case PCI_PRODUCT_BROADCOM_BCM57786: 3304 case PCI_PRODUCT_BROADCOM_BCM57791: 3305 case PCI_PRODUCT_BROADCOM_BCM57795: 3306 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3307 BGE_PCI_GEN15_PRODID_ASICREV); 3308 break; 3309 default: 3310 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3311 BGE_PCI_PRODID_ASICREV); 3312 break; 3313 } 3314 } 3315 3316 return id; 3317 } 3318 3319 /* 3320 * Return true if MSI can be used with this device. 3321 */ 3322 static int 3323 bge_can_use_msi(struct bge_softc *sc) 3324 { 3325 int can_use_msi = 0; 3326 3327 switch (BGE_ASICREV(sc->bge_chipid)) { 3328 case BGE_ASICREV_BCM5714_A0: 3329 case BGE_ASICREV_BCM5714: 3330 /* 3331 * Apparently, MSI doesn't work when these chips are 3332 * configured in single-port mode. 3333 */ 3334 break; 3335 case BGE_ASICREV_BCM5750: 3336 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3337 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3338 can_use_msi = 1; 3339 break; 3340 default: 3341 if (BGE_IS_575X_PLUS(sc)) 3342 can_use_msi = 1; 3343 } 3344 return (can_use_msi); 3345 } 3346 3347 /* 3348 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3349 * against our list and return its name if we find a match. Note 3350 * that since the Broadcom controller contains VPD support, we 3351 * can get the device name string from the controller itself instead 3352 * of the compiled-in string. This is a little slow, but it guarantees 3353 * we'll always announce the right product name. 3354 */ 3355 static int 3356 bge_probe(device_t parent, cfdata_t match, void *aux) 3357 { 3358 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3359 3360 if (bge_lookup(pa) != NULL) 3361 return 1; 3362 3363 return 0; 3364 } 3365 3366 static void 3367 bge_attach(device_t parent, device_t self, void *aux) 3368 { 3369 struct bge_softc *sc = device_private(self); 3370 struct pci_attach_args *pa = aux; 3371 prop_dictionary_t dict; 3372 const struct bge_product *bp; 3373 const struct bge_revision *br; 3374 pci_chipset_tag_t pc; 3375 const char *intrstr = NULL; 3376 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3377 uint32_t command; 3378 struct ifnet *ifp; 3379 uint32_t misccfg, mimode; 3380 void * kva; 3381 u_char eaddr[ETHER_ADDR_LEN]; 3382 pcireg_t memtype, subid, reg; 3383 bus_addr_t memaddr; 3384 uint32_t pm_ctl; 3385 bool no_seeprom; 3386 int capmask; 3387 int mii_flags; 3388 int map_flags; 3389 char intrbuf[PCI_INTRSTR_LEN]; 3390 3391 bp = bge_lookup(pa); 3392 KASSERT(bp != NULL); 3393 3394 sc->sc_pc = pa->pa_pc; 3395 sc->sc_pcitag = pa->pa_tag; 3396 sc->bge_dev = self; 3397 3398 sc->bge_pa = *pa; 3399 pc = sc->sc_pc; 3400 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3401 3402 aprint_naive(": Ethernet controller\n"); 3403 aprint_normal(": %s\n", bp->bp_name); 3404 3405 /* 3406 * Map control/status registers. 3407 */ 3408 DPRINTFN(5, ("Map control/status regs\n")); 3409 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3410 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3411 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3412 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3413 3414 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3415 aprint_error_dev(sc->bge_dev, 3416 "failed to enable memory mapping!\n"); 3417 return; 3418 } 3419 3420 DPRINTFN(5, ("pci_mem_find\n")); 3421 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3422 switch (memtype) { 3423 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3424 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3425 #if 0 3426 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3427 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3428 &memaddr, &sc->bge_bsize) == 0) 3429 break; 3430 #else 3431 /* 3432 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3433 * system get NMI on boot (PR#48451). This problem might not be 3434 * the driver's bug but our PCI common part's bug. Until we 3435 * find a real reason, we ignore the prefetchable bit. 3436 */ 3437 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3438 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3439 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3440 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3441 map_flags, &sc->bge_bhandle) == 0) { 3442 sc->bge_btag = pa->pa_memt; 3443 break; 3444 } 3445 } 3446 #endif 3447 default: 3448 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3449 return; 3450 } 3451 3452 /* Save various chip information. */ 3453 sc->bge_chipid = bge_chipid(pa); 3454 sc->bge_phy_addr = bge_phy_addr(sc); 3455 3456 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3457 &sc->bge_pciecap, NULL) != 0) { 3458 /* PCIe */ 3459 sc->bge_flags |= BGEF_PCIE; 3460 /* Extract supported maximum payload size. */ 3461 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3462 sc->bge_pciecap + PCIE_DCAP); 3463 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3464 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3465 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3466 sc->bge_expmrq = 2048; 3467 else 3468 sc->bge_expmrq = 4096; 3469 bge_set_max_readrq(sc); 3470 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3471 /* PCIe without PCIe cap */ 3472 sc->bge_flags |= BGEF_PCIE; 3473 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3474 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3475 /* PCI-X */ 3476 sc->bge_flags |= BGEF_PCIX; 3477 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3478 &sc->bge_pcixcap, NULL) == 0) 3479 aprint_error_dev(sc->bge_dev, 3480 "unable to find PCIX capability\n"); 3481 } 3482 3483 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3484 /* 3485 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3486 * can clobber the chip's PCI config-space power control 3487 * registers, leaving the card in D3 powersave state. We do 3488 * not have memory-mapped registers in this state, so force 3489 * device into D0 state before starting initialization. 3490 */ 3491 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3492 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3493 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3494 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3495 DELAY(1000); /* 27 usec is allegedly sufficent */ 3496 } 3497 3498 /* Save chipset family. */ 3499 switch (BGE_ASICREV(sc->bge_chipid)) { 3500 case BGE_ASICREV_BCM5717: 3501 case BGE_ASICREV_BCM5719: 3502 case BGE_ASICREV_BCM5720: 3503 sc->bge_flags |= BGEF_5717_PLUS; 3504 /* FALLTHROUGH */ 3505 case BGE_ASICREV_BCM57765: 3506 case BGE_ASICREV_BCM57766: 3507 if (!BGE_IS_5717_PLUS(sc)) 3508 sc->bge_flags |= BGEF_57765_FAMILY; 3509 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3510 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3511 /* Jumbo frame on BCM5719 A0 does not work. */ 3512 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3513 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3514 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3515 break; 3516 case BGE_ASICREV_BCM5755: 3517 case BGE_ASICREV_BCM5761: 3518 case BGE_ASICREV_BCM5784: 3519 case BGE_ASICREV_BCM5785: 3520 case BGE_ASICREV_BCM5787: 3521 case BGE_ASICREV_BCM57780: 3522 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3523 break; 3524 case BGE_ASICREV_BCM5700: 3525 case BGE_ASICREV_BCM5701: 3526 case BGE_ASICREV_BCM5703: 3527 case BGE_ASICREV_BCM5704: 3528 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3529 break; 3530 case BGE_ASICREV_BCM5714_A0: 3531 case BGE_ASICREV_BCM5780: 3532 case BGE_ASICREV_BCM5714: 3533 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3534 /* FALLTHROUGH */ 3535 case BGE_ASICREV_BCM5750: 3536 case BGE_ASICREV_BCM5752: 3537 case BGE_ASICREV_BCM5906: 3538 sc->bge_flags |= BGEF_575X_PLUS; 3539 /* FALLTHROUGH */ 3540 case BGE_ASICREV_BCM5705: 3541 sc->bge_flags |= BGEF_5705_PLUS; 3542 break; 3543 } 3544 3545 /* Identify chips with APE processor. */ 3546 switch (BGE_ASICREV(sc->bge_chipid)) { 3547 case BGE_ASICREV_BCM5717: 3548 case BGE_ASICREV_BCM5719: 3549 case BGE_ASICREV_BCM5720: 3550 case BGE_ASICREV_BCM5761: 3551 sc->bge_flags |= BGEF_APE; 3552 break; 3553 } 3554 3555 /* 3556 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3557 * not actually a MAC controller bug but an issue with the embedded 3558 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3559 */ 3560 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3561 sc->bge_flags |= BGEF_40BIT_BUG; 3562 3563 /* Chips with APE need BAR2 access for APE registers/memory. */ 3564 if ((sc->bge_flags & BGEF_APE) != 0) { 3565 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3566 #if 0 3567 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3568 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3569 &sc->bge_apesize)) { 3570 aprint_error_dev(sc->bge_dev, 3571 "couldn't map BAR2 memory\n"); 3572 return; 3573 } 3574 #else 3575 /* 3576 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3577 * system get NMI on boot (PR#48451). This problem might not be 3578 * the driver's bug but our PCI common part's bug. Until we 3579 * find a real reason, we ignore the prefetchable bit. 3580 */ 3581 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3582 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3583 aprint_error_dev(sc->bge_dev, 3584 "couldn't map BAR2 memory\n"); 3585 return; 3586 } 3587 3588 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3589 if (bus_space_map(pa->pa_memt, memaddr, 3590 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3591 aprint_error_dev(sc->bge_dev, 3592 "couldn't map BAR2 memory\n"); 3593 return; 3594 } 3595 sc->bge_apetag = pa->pa_memt; 3596 #endif 3597 3598 /* Enable APE register/memory access by host driver. */ 3599 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3600 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3601 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3602 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3603 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3604 3605 bge_ape_lock_init(sc); 3606 bge_ape_read_fw_ver(sc); 3607 } 3608 3609 /* Identify the chips that use an CPMU. */ 3610 if (BGE_IS_5717_PLUS(sc) || 3611 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3612 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3613 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3614 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3615 sc->bge_flags |= BGEF_CPMU_PRESENT; 3616 3617 /* Set MI_MODE */ 3618 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3619 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3620 mimode |= BGE_MIMODE_500KHZ_CONST; 3621 else 3622 mimode |= BGE_MIMODE_BASE; 3623 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3624 3625 /* 3626 * When using the BCM5701 in PCI-X mode, data corruption has 3627 * been observed in the first few bytes of some received packets. 3628 * Aligning the packet buffer in memory eliminates the corruption. 3629 * Unfortunately, this misaligns the packet payloads. On platforms 3630 * which do not support unaligned accesses, we will realign the 3631 * payloads by copying the received packets. 3632 */ 3633 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3634 sc->bge_flags & BGEF_PCIX) 3635 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3636 3637 if (BGE_IS_5700_FAMILY(sc)) 3638 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3639 3640 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3641 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3642 3643 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3644 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3645 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3646 sc->bge_flags |= BGEF_IS_5788; 3647 3648 /* 3649 * Some controllers seem to require a special firmware to use 3650 * TSO. But the firmware is not available to FreeBSD and Linux 3651 * claims that the TSO performed by the firmware is slower than 3652 * hardware based TSO. Moreover the firmware based TSO has one 3653 * known bug which can't handle TSO if ethernet header + IP/TCP 3654 * header is greater than 80 bytes. The workaround for the TSO 3655 * bug exist but it seems it's too expensive than not using 3656 * TSO at all. Some hardwares also have the TSO bug so limit 3657 * the TSO to the controllers that are not affected TSO issues 3658 * (e.g. 5755 or higher). 3659 */ 3660 if (BGE_IS_5755_PLUS(sc)) { 3661 /* 3662 * BCM5754 and BCM5787 shares the same ASIC id so 3663 * explicit device id check is required. 3664 */ 3665 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3666 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3667 sc->bge_flags |= BGEF_TSO; 3668 /* TSO on BCM5719 A0 does not work. */ 3669 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3670 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3671 sc->bge_flags &= ~BGEF_TSO; 3672 } 3673 3674 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3675 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3676 (misccfg == 0x4000 || misccfg == 0x8000)) || 3677 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3678 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3679 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3680 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3681 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3682 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3683 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3684 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3685 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3686 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3687 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3688 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3689 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3690 /* These chips are 10/100 only. */ 3691 capmask &= ~BMSR_EXTSTAT; 3692 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3693 } 3694 3695 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3696 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3697 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3698 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3699 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3700 3701 /* Set various PHY bug flags. */ 3702 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3703 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3704 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3705 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3706 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3707 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3708 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3709 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3710 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3711 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3712 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3713 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3714 if (BGE_IS_5705_PLUS(sc) && 3715 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3716 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3717 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3718 !BGE_IS_57765_PLUS(sc)) { 3719 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3720 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3721 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3722 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3723 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3724 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3725 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3726 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3727 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3728 } else 3729 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3730 } 3731 3732 /* 3733 * SEEPROM check. 3734 * First check if firmware knows we do not have SEEPROM. 3735 */ 3736 if (prop_dictionary_get_bool(device_properties(self), 3737 "without-seeprom", &no_seeprom) && no_seeprom) 3738 sc->bge_flags |= BGEF_NO_EEPROM; 3739 3740 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3741 sc->bge_flags |= BGEF_NO_EEPROM; 3742 3743 /* Now check the 'ROM failed' bit on the RX CPU */ 3744 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3745 sc->bge_flags |= BGEF_NO_EEPROM; 3746 3747 sc->bge_asf_mode = 0; 3748 /* No ASF if APE present. */ 3749 if ((sc->bge_flags & BGEF_APE) == 0) { 3750 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3751 BGE_SRAM_DATA_SIG_MAGIC)) { 3752 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3753 BGE_HWCFG_ASF) { 3754 sc->bge_asf_mode |= ASF_ENABLE; 3755 sc->bge_asf_mode |= ASF_STACKUP; 3756 if (BGE_IS_575X_PLUS(sc)) 3757 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3758 } 3759 } 3760 } 3761 3762 int counts[PCI_INTR_TYPE_SIZE] = { 3763 [PCI_INTR_TYPE_INTX] = 1, 3764 [PCI_INTR_TYPE_MSI] = 1, 3765 [PCI_INTR_TYPE_MSIX] = 1, 3766 }; 3767 int max_type = PCI_INTR_TYPE_MSIX; 3768 3769 if (!bge_can_use_msi(sc)) { 3770 /* MSI broken, allow only INTx */ 3771 max_type = PCI_INTR_TYPE_INTX; 3772 } 3773 3774 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3775 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3776 return; 3777 } 3778 3779 DPRINTFN(5, ("pci_intr_string\n")); 3780 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3781 sizeof(intrbuf)); 3782 DPRINTFN(5, ("pci_intr_establish\n")); 3783 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3784 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3785 if (sc->bge_intrhand == NULL) { 3786 pci_intr_release(pc, sc->bge_pihp, 1); 3787 sc->bge_pihp = NULL; 3788 3789 aprint_error_dev(self, "couldn't establish interrupt"); 3790 if (intrstr != NULL) 3791 aprint_error(" at %s", intrstr); 3792 aprint_error("\n"); 3793 return; 3794 } 3795 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3796 3797 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3798 case PCI_INTR_TYPE_MSIX: 3799 case PCI_INTR_TYPE_MSI: 3800 KASSERT(bge_can_use_msi(sc)); 3801 sc->bge_flags |= BGEF_MSI; 3802 break; 3803 default: 3804 /* nothing to do */ 3805 break; 3806 } 3807 3808 /* 3809 * All controllers except BCM5700 supports tagged status but 3810 * we use tagged status only for MSI case on BCM5717. Otherwise 3811 * MSI on BCM5717 does not work. 3812 */ 3813 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3814 sc->bge_flags |= BGEF_TAGGED_STATUS; 3815 3816 /* 3817 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3818 * lock in bge_reset(). 3819 */ 3820 CSR_WRITE_4(sc, BGE_EE_ADDR, 3821 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3822 delay(1000); 3823 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3824 3825 bge_stop_fw(sc); 3826 bge_sig_pre_reset(sc, BGE_RESET_START); 3827 if (bge_reset(sc)) 3828 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3829 3830 /* 3831 * Read the hardware config word in the first 32k of NIC internal 3832 * memory, or fall back to the config word in the EEPROM. 3833 * Note: on some BCM5700 cards, this value appears to be unset. 3834 */ 3835 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3836 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3837 BGE_SRAM_DATA_SIG_MAGIC) { 3838 uint32_t tmp; 3839 3840 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3841 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3842 BGE_SRAM_DATA_VER_SHIFT; 3843 if ((0 < tmp) && (tmp < 0x100)) 3844 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3845 if (sc->bge_flags & BGEF_PCIE) 3846 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3847 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3848 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3849 if (BGE_IS_5717_PLUS(sc)) 3850 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3851 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3852 bge_read_eeprom(sc, (void *)&hwcfg, 3853 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3854 hwcfg = be32toh(hwcfg); 3855 } 3856 aprint_normal_dev(sc->bge_dev, 3857 "HW config %08x, %08x, %08x, %08x %08x\n", 3858 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3859 3860 bge_sig_legacy(sc, BGE_RESET_START); 3861 bge_sig_post_reset(sc, BGE_RESET_START); 3862 3863 if (bge_chipinit(sc)) { 3864 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3865 bge_release_resources(sc); 3866 return; 3867 } 3868 3869 /* 3870 * Get station address from the EEPROM. 3871 */ 3872 if (bge_get_eaddr(sc, eaddr)) { 3873 aprint_error_dev(sc->bge_dev, 3874 "failed to read station address\n"); 3875 bge_release_resources(sc); 3876 return; 3877 } 3878 3879 br = bge_lookup_rev(sc->bge_chipid); 3880 3881 if (br == NULL) { 3882 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3883 sc->bge_chipid); 3884 } else { 3885 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3886 br->br_name, sc->bge_chipid); 3887 } 3888 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3889 3890 /* Allocate the general information block and ring buffers. */ 3891 if (pci_dma64_available(pa)) { 3892 sc->bge_dmatag = pa->pa_dmat64; 3893 sc->bge_dmatag32 = pa->pa_dmat; 3894 sc->bge_dma64 = true; 3895 } else { 3896 sc->bge_dmatag = pa->pa_dmat; 3897 sc->bge_dmatag32 = pa->pa_dmat; 3898 sc->bge_dma64 = false; 3899 } 3900 3901 /* 40bit DMA workaround */ 3902 if (sizeof(bus_addr_t) > 4) { 3903 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3904 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3905 3906 if (bus_dmatag_subregion(olddmatag, 0, 3907 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3908 BUS_DMA_NOWAIT) != 0) { 3909 aprint_error_dev(self, 3910 "WARNING: failed to restrict dma range," 3911 " falling back to parent bus dma range\n"); 3912 sc->bge_dmatag = olddmatag; 3913 } 3914 } 3915 } 3916 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3917 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3918 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3919 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3920 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3921 return; 3922 } 3923 DPRINTFN(5, ("bus_dmamem_map\n")); 3924 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3925 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3926 BUS_DMA_NOWAIT)) { 3927 aprint_error_dev(sc->bge_dev, 3928 "can't map DMA buffers (%zu bytes)\n", 3929 sizeof(struct bge_ring_data)); 3930 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3931 sc->bge_ring_rseg); 3932 return; 3933 } 3934 DPRINTFN(5, ("bus_dmamem_create\n")); 3935 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3936 sizeof(struct bge_ring_data), 0, 3937 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3938 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3939 bus_dmamem_unmap(sc->bge_dmatag, kva, 3940 sizeof(struct bge_ring_data)); 3941 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3942 sc->bge_ring_rseg); 3943 return; 3944 } 3945 DPRINTFN(5, ("bus_dmamem_load\n")); 3946 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3947 sizeof(struct bge_ring_data), NULL, 3948 BUS_DMA_NOWAIT)) { 3949 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3950 bus_dmamem_unmap(sc->bge_dmatag, kva, 3951 sizeof(struct bge_ring_data)); 3952 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3953 sc->bge_ring_rseg); 3954 return; 3955 } 3956 3957 DPRINTFN(5, ("bzero\n")); 3958 sc->bge_rdata = (struct bge_ring_data *)kva; 3959 3960 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3961 3962 /* Try to allocate memory for jumbo buffers. */ 3963 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3964 if (bge_alloc_jumbo_mem(sc)) { 3965 aprint_error_dev(sc->bge_dev, 3966 "jumbo buffer allocation failed\n"); 3967 } else 3968 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3969 } 3970 3971 /* Set default tuneable values. */ 3972 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3973 sc->bge_rx_coal_ticks = 150; 3974 sc->bge_rx_max_coal_bds = 64; 3975 sc->bge_tx_coal_ticks = 300; 3976 sc->bge_tx_max_coal_bds = 400; 3977 if (BGE_IS_5705_PLUS(sc)) { 3978 sc->bge_tx_coal_ticks = (12 * 5); 3979 sc->bge_tx_max_coal_bds = (12 * 5); 3980 aprint_verbose_dev(sc->bge_dev, 3981 "setting short Tx thresholds\n"); 3982 } 3983 3984 if (BGE_IS_5717_PLUS(sc)) 3985 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3986 else if (BGE_IS_5705_PLUS(sc)) 3987 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3988 else 3989 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3990 3991 /* Set up ifnet structure */ 3992 ifp = &sc->ethercom.ec_if; 3993 ifp->if_softc = sc; 3994 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3995 ifp->if_ioctl = bge_ioctl; 3996 ifp->if_stop = bge_stop; 3997 ifp->if_start = bge_start; 3998 ifp->if_init = bge_init; 3999 ifp->if_watchdog = bge_watchdog; 4000 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 4001 IFQ_SET_READY(&ifp->if_snd); 4002 DPRINTFN(5, ("strcpy if_xname\n")); 4003 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 4004 4005 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 4006 sc->ethercom.ec_if.if_capabilities |= 4007 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 4008 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 4009 sc->ethercom.ec_if.if_capabilities |= 4010 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 4011 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 4012 #endif 4013 sc->ethercom.ec_capabilities |= 4014 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 4015 4016 if (sc->bge_flags & BGEF_TSO) 4017 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 4018 4019 /* 4020 * Do MII setup. 4021 */ 4022 DPRINTFN(5, ("mii setup\n")); 4023 sc->bge_mii.mii_ifp = ifp; 4024 sc->bge_mii.mii_readreg = bge_miibus_readreg; 4025 sc->bge_mii.mii_writereg = bge_miibus_writereg; 4026 sc->bge_mii.mii_statchg = bge_miibus_statchg; 4027 4028 /* 4029 * Figure out what sort of media we have by checking the hardware 4030 * config word. Note: on some BCM5700 cards, this value appears to be 4031 * unset. If that's the case, we have to rely on identifying the NIC 4032 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 4033 * The SysKonnect SK-9D41 is a 1000baseSX card. 4034 */ 4035 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 4036 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 4037 if (BGE_IS_5705_PLUS(sc)) { 4038 sc->bge_flags |= BGEF_FIBER_MII; 4039 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 4040 } else 4041 sc->bge_flags |= BGEF_FIBER_TBI; 4042 } 4043 4044 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 4045 if (BGE_IS_JUMBO_CAPABLE(sc)) 4046 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 4047 4048 /* set phyflags and chipid before mii_attach() */ 4049 dict = device_properties(self); 4050 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 4051 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 4052 4053 if (sc->bge_flags & BGEF_FIBER_TBI) { 4054 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 4055 bge_ifmedia_sts); 4056 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 4057 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 4058 0, NULL); 4059 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 4060 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 4061 /* Pretend the user requested this setting */ 4062 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 4063 } else { 4064 /* 4065 * Do transceiver setup and tell the firmware the 4066 * driver is down so we can try to get access the 4067 * probe if ASF is running. Retry a couple of times 4068 * if we get a conflict with the ASF firmware accessing 4069 * the PHY. 4070 */ 4071 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4072 bge_asf_driver_up(sc); 4073 4074 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 4075 bge_ifmedia_sts); 4076 mii_flags = MIIF_DOPAUSE; 4077 if (sc->bge_flags & BGEF_FIBER_MII) 4078 mii_flags |= MIIF_HAVEFIBER; 4079 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 4080 MII_OFFSET_ANY, mii_flags); 4081 4082 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 4083 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4084 ifmedia_add(&sc->bge_mii.mii_media, 4085 IFM_ETHER|IFM_MANUAL, 0, NULL); 4086 ifmedia_set(&sc->bge_mii.mii_media, 4087 IFM_ETHER|IFM_MANUAL); 4088 } else 4089 ifmedia_set(&sc->bge_mii.mii_media, 4090 IFM_ETHER|IFM_AUTO); 4091 4092 /* 4093 * Now tell the firmware we are going up after probing the PHY 4094 */ 4095 if (sc->bge_asf_mode & ASF_STACKUP) 4096 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4097 } 4098 4099 /* 4100 * Call MI attach routine. 4101 */ 4102 DPRINTFN(5, ("if_attach\n")); 4103 if_attach(ifp); 4104 if_deferred_start_init(ifp, NULL); 4105 DPRINTFN(5, ("ether_ifattach\n")); 4106 ether_ifattach(ifp, eaddr); 4107 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4108 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4109 RND_TYPE_NET, RND_FLAG_DEFAULT); 4110 #ifdef BGE_EVENT_COUNTERS 4111 /* 4112 * Attach event counters. 4113 */ 4114 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4115 NULL, device_xname(sc->bge_dev), "intr"); 4116 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4117 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4118 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4119 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4120 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4121 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4122 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4123 NULL, device_xname(sc->bge_dev), "tx_xon"); 4124 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4125 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4126 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4127 NULL, device_xname(sc->bge_dev), "rx_xon"); 4128 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4129 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4130 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4131 NULL, device_xname(sc->bge_dev), "xoffentered"); 4132 #endif /* BGE_EVENT_COUNTERS */ 4133 DPRINTFN(5, ("callout_init\n")); 4134 callout_init(&sc->bge_timeout, 0); 4135 4136 if (pmf_device_register(self, NULL, NULL)) 4137 pmf_class_network_register(self, ifp); 4138 else 4139 aprint_error_dev(self, "couldn't establish power handler\n"); 4140 4141 bge_sysctl_init(sc); 4142 4143 #ifdef BGE_DEBUG 4144 bge_debug_info(sc); 4145 #endif 4146 } 4147 4148 /* 4149 * Stop all chip I/O so that the kernel's probe routines don't 4150 * get confused by errant DMAs when rebooting. 4151 */ 4152 static int 4153 bge_detach(device_t self, int flags __unused) 4154 { 4155 struct bge_softc *sc = device_private(self); 4156 struct ifnet *ifp = &sc->ethercom.ec_if; 4157 int s; 4158 4159 s = splnet(); 4160 /* Stop the interface. Callouts are stopped in it. */ 4161 bge_stop(ifp, 1); 4162 splx(s); 4163 4164 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4165 4166 /* Delete all remaining media. */ 4167 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4168 4169 ether_ifdetach(ifp); 4170 if_detach(ifp); 4171 4172 bge_release_resources(sc); 4173 4174 return 0; 4175 } 4176 4177 static void 4178 bge_release_resources(struct bge_softc *sc) 4179 { 4180 4181 /* Detach sysctl */ 4182 if (sc->bge_log != NULL) 4183 sysctl_teardown(&sc->bge_log); 4184 4185 #ifdef BGE_EVENT_COUNTERS 4186 /* Detach event counters. */ 4187 evcnt_detach(&sc->bge_ev_intr); 4188 evcnt_detach(&sc->bge_ev_intr_spurious); 4189 evcnt_detach(&sc->bge_ev_intr_spurious2); 4190 evcnt_detach(&sc->bge_ev_tx_xoff); 4191 evcnt_detach(&sc->bge_ev_tx_xon); 4192 evcnt_detach(&sc->bge_ev_rx_xoff); 4193 evcnt_detach(&sc->bge_ev_rx_xon); 4194 evcnt_detach(&sc->bge_ev_rx_macctl); 4195 evcnt_detach(&sc->bge_ev_xoffentered); 4196 #endif /* BGE_EVENT_COUNTERS */ 4197 4198 /* Disestablish the interrupt handler */ 4199 if (sc->bge_intrhand != NULL) { 4200 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4201 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4202 sc->bge_intrhand = NULL; 4203 } 4204 4205 if (sc->bge_dmatag != NULL) { 4206 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4207 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4208 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4209 sizeof(struct bge_ring_data)); 4210 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4211 sc->bge_ring_rseg); 4212 } 4213 4214 /* Unmap the device registers */ 4215 if (sc->bge_bsize != 0) { 4216 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4217 sc->bge_bsize = 0; 4218 } 4219 4220 /* Unmap the APE registers */ 4221 if (sc->bge_apesize != 0) { 4222 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4223 sc->bge_apesize); 4224 sc->bge_apesize = 0; 4225 } 4226 } 4227 4228 static int 4229 bge_reset(struct bge_softc *sc) 4230 { 4231 uint32_t cachesize, command; 4232 uint32_t reset, mac_mode, mac_mode_mask; 4233 pcireg_t devctl, reg; 4234 int i, val; 4235 void (*write_op)(struct bge_softc *, int, int); 4236 4237 /* Make mask for BGE_MAC_MODE register. */ 4238 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4239 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4240 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4241 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4242 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4243 4244 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4245 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4246 if (sc->bge_flags & BGEF_PCIE) 4247 write_op = bge_writemem_direct; 4248 else 4249 write_op = bge_writemem_ind; 4250 } else 4251 write_op = bge_writereg_ind; 4252 4253 /* 57XX step 4 */ 4254 /* Acquire the NVM lock */ 4255 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4256 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4257 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4258 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4259 for (i = 0; i < 8000; i++) { 4260 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4261 BGE_NVRAMSWARB_GNT1) 4262 break; 4263 DELAY(20); 4264 } 4265 if (i == 8000) { 4266 printf("%s: NVRAM lock timedout!\n", 4267 device_xname(sc->bge_dev)); 4268 } 4269 } 4270 4271 /* Take APE lock when performing reset. */ 4272 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4273 4274 /* 57XX step 3 */ 4275 /* Save some important PCI state. */ 4276 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4277 /* 5718 reset step 3 */ 4278 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4279 4280 /* 5718 reset step 5, 57XX step 5b-5d */ 4281 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4282 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4283 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4284 4285 /* XXX ???: Disable fastboot on controllers that support it. */ 4286 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4287 BGE_IS_5755_PLUS(sc)) 4288 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4289 4290 /* 5718 reset step 2, 57XX step 6 */ 4291 /* 4292 * Write the magic number to SRAM at offset 0xB50. 4293 * When firmware finishes its initialization it will 4294 * write ~BGE_MAGIC_NUMBER to the same location. 4295 */ 4296 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4297 4298 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4299 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4300 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4301 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4302 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4303 } 4304 4305 /* 5718 reset step 6, 57XX step 7 */ 4306 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4307 /* 4308 * XXX: from FreeBSD/Linux; no documentation 4309 */ 4310 if (sc->bge_flags & BGEF_PCIE) { 4311 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4312 !BGE_IS_57765_PLUS(sc) && 4313 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4314 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4315 /* PCI Express 1.0 system */ 4316 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4317 BGE_PHY_PCIE_SCRAM_MODE); 4318 } 4319 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4320 /* 4321 * Prevent PCI Express link training 4322 * during global reset. 4323 */ 4324 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4325 reset |= (1 << 29); 4326 } 4327 } 4328 4329 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4330 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4331 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4332 i | BGE_VCPU_STATUS_DRV_RESET); 4333 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4334 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4335 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4336 } 4337 4338 /* 4339 * Set GPHY Power Down Override to leave GPHY 4340 * powered up in D0 uninitialized. 4341 */ 4342 if (BGE_IS_5705_PLUS(sc) && 4343 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4344 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4345 4346 /* Issue global reset */ 4347 write_op(sc, BGE_MISC_CFG, reset); 4348 4349 /* 5718 reset step 7, 57XX step 8 */ 4350 if (sc->bge_flags & BGEF_PCIE) 4351 delay(100*1000); /* too big */ 4352 else 4353 delay(1000); 4354 4355 if (sc->bge_flags & BGEF_PCIE) { 4356 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4357 DELAY(500000); 4358 /* XXX: Magic Numbers */ 4359 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4360 BGE_PCI_UNKNOWN0); 4361 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4362 BGE_PCI_UNKNOWN0, 4363 reg | (1 << 15)); 4364 } 4365 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4366 sc->bge_pciecap + PCIE_DCSR); 4367 /* Clear enable no snoop and disable relaxed ordering. */ 4368 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4369 PCIE_DCSR_ENA_NO_SNOOP); 4370 4371 /* Set PCIE max payload size to 128 for older PCIe devices */ 4372 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4373 devctl &= ~(0x00e0); 4374 /* Clear device status register. Write 1b to clear */ 4375 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4376 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4377 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4378 sc->bge_pciecap + PCIE_DCSR, devctl); 4379 bge_set_max_readrq(sc); 4380 } 4381 4382 /* From Linux: dummy read to flush PCI posted writes */ 4383 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4384 4385 /* 4386 * Reset some of the PCI state that got zapped by reset 4387 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4388 * set, too. 4389 */ 4390 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4391 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4392 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4393 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4394 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4395 (sc->bge_flags & BGEF_PCIX) != 0) 4396 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4397 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4398 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4399 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4400 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4401 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4402 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4403 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4404 4405 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4406 if (sc->bge_flags & BGEF_PCIX) { 4407 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4408 + PCIX_CMD); 4409 /* Set max memory read byte count to 2K */ 4410 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4411 reg &= ~PCIX_CMD_BYTECNT_MASK; 4412 reg |= PCIX_CMD_BCNT_2048; 4413 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4414 /* 4415 * For 5704, set max outstanding split transaction 4416 * field to 0 (0 means it supports 1 request) 4417 */ 4418 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4419 | PCIX_CMD_BYTECNT_MASK); 4420 reg |= PCIX_CMD_BCNT_2048; 4421 } 4422 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4423 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4424 } 4425 4426 /* 5718 reset step 10, 57XX step 12 */ 4427 /* Enable memory arbiter. */ 4428 if (BGE_IS_5714_FAMILY(sc)) { 4429 val = CSR_READ_4(sc, BGE_MARB_MODE); 4430 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4431 } else 4432 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4433 4434 /* XXX 5721, 5751 and 5752 */ 4435 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4436 /* Step 19: */ 4437 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4438 /* Step 20: */ 4439 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4440 } 4441 4442 /* 5718 reset step 12, 57XX step 15 and 16 */ 4443 /* Fix up byte swapping */ 4444 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4445 4446 /* 5718 reset step 13, 57XX step 17 */ 4447 /* Poll until the firmware initialization is complete */ 4448 bge_poll_fw(sc); 4449 4450 /* 57XX step 21 */ 4451 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4452 pcireg_t msidata; 4453 4454 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4455 BGE_PCI_MSI_DATA); 4456 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4457 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4458 msidata); 4459 } 4460 4461 /* 57XX step 18 */ 4462 /* Write mac mode. */ 4463 val = CSR_READ_4(sc, BGE_MAC_MODE); 4464 /* Restore mac_mode_mask's bits using mac_mode */ 4465 val = (val & ~mac_mode_mask) | mac_mode; 4466 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4467 DELAY(40); 4468 4469 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4470 4471 /* 4472 * The 5704 in TBI mode apparently needs some special 4473 * adjustment to insure the SERDES drive level is set 4474 * to 1.2V. 4475 */ 4476 if (sc->bge_flags & BGEF_FIBER_TBI && 4477 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4478 uint32_t serdescfg; 4479 4480 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4481 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4482 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4483 } 4484 4485 if (sc->bge_flags & BGEF_PCIE && 4486 !BGE_IS_57765_PLUS(sc) && 4487 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4488 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4489 uint32_t v; 4490 4491 /* Enable PCI Express bug fix */ 4492 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4493 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4494 v | BGE_TLP_DATA_FIFO_PROTECT); 4495 } 4496 4497 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4498 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4499 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4500 4501 return 0; 4502 } 4503 4504 /* 4505 * Frame reception handling. This is called if there's a frame 4506 * on the receive return list. 4507 * 4508 * Note: we have to be able to handle two possibilities here: 4509 * 1) the frame is from the jumbo receive ring 4510 * 2) the frame is from the standard receive ring 4511 */ 4512 4513 static void 4514 bge_rxeof(struct bge_softc *sc) 4515 { 4516 struct ifnet *ifp; 4517 uint16_t rx_prod, rx_cons; 4518 int stdcnt = 0, jumbocnt = 0; 4519 bus_dmamap_t dmamap; 4520 bus_addr_t offset, toff; 4521 bus_size_t tlen; 4522 int tosync; 4523 4524 rx_cons = sc->bge_rx_saved_considx; 4525 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4526 4527 /* Nothing to do */ 4528 if (rx_cons == rx_prod) 4529 return; 4530 4531 ifp = &sc->ethercom.ec_if; 4532 4533 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4534 offsetof(struct bge_ring_data, bge_status_block), 4535 sizeof (struct bge_status_block), 4536 BUS_DMASYNC_POSTREAD); 4537 4538 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4539 tosync = rx_prod - rx_cons; 4540 4541 if (tosync != 0) 4542 rnd_add_uint32(&sc->rnd_source, tosync); 4543 4544 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4545 4546 if (tosync < 0) { 4547 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4548 sizeof (struct bge_rx_bd); 4549 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4550 toff, tlen, BUS_DMASYNC_POSTREAD); 4551 tosync = -tosync; 4552 } 4553 4554 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4555 offset, tosync * sizeof (struct bge_rx_bd), 4556 BUS_DMASYNC_POSTREAD); 4557 4558 while (rx_cons != rx_prod) { 4559 struct bge_rx_bd *cur_rx; 4560 uint32_t rxidx; 4561 struct mbuf *m = NULL; 4562 4563 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4564 4565 rxidx = cur_rx->bge_idx; 4566 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4567 4568 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4569 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4570 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4571 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4572 jumbocnt++; 4573 bus_dmamap_sync(sc->bge_dmatag, 4574 sc->bge_cdata.bge_rx_jumbo_map, 4575 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4576 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4577 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4578 ifp->if_ierrors++; 4579 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4580 continue; 4581 } 4582 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4583 NULL)== ENOBUFS) { 4584 ifp->if_ierrors++; 4585 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4586 continue; 4587 } 4588 } else { 4589 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4590 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4591 4592 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4593 stdcnt++; 4594 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4595 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 4596 if (dmamap == NULL) { 4597 ifp->if_ierrors++; 4598 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4599 continue; 4600 } 4601 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4602 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4603 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4604 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4605 ifp->if_ierrors++; 4606 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4607 continue; 4608 } 4609 if (bge_newbuf_std(sc, sc->bge_std, 4610 NULL, dmamap) == ENOBUFS) { 4611 ifp->if_ierrors++; 4612 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4613 continue; 4614 } 4615 } 4616 4617 #ifndef __NO_STRICT_ALIGNMENT 4618 /* 4619 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4620 * the Rx buffer has the layer-2 header unaligned. 4621 * If our CPU requires alignment, re-align by copying. 4622 */ 4623 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4624 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4625 cur_rx->bge_len); 4626 m->m_data += ETHER_ALIGN; 4627 } 4628 #endif 4629 4630 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4631 m_set_rcvif(m, ifp); 4632 4633 bge_rxcsum(sc, cur_rx, m); 4634 4635 /* 4636 * If we received a packet with a vlan tag, pass it 4637 * to vlan_input() instead of ether_input(). 4638 */ 4639 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4640 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4641 } 4642 4643 if_percpuq_enqueue(ifp->if_percpuq, m); 4644 } 4645 4646 sc->bge_rx_saved_considx = rx_cons; 4647 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4648 if (stdcnt) 4649 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4650 if (jumbocnt) 4651 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4652 } 4653 4654 static void 4655 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4656 { 4657 4658 if (BGE_IS_57765_PLUS(sc)) { 4659 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4660 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4661 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4662 if ((cur_rx->bge_error_flag & 4663 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4664 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4665 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4666 m->m_pkthdr.csum_data = 4667 cur_rx->bge_tcp_udp_csum; 4668 m->m_pkthdr.csum_flags |= 4669 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4670 M_CSUM_DATA); 4671 } 4672 } 4673 } else { 4674 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4675 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4676 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4677 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4678 /* 4679 * Rx transport checksum-offload may also 4680 * have bugs with packets which, when transmitted, 4681 * were `runts' requiring padding. 4682 */ 4683 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4684 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4685 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4686 m->m_pkthdr.csum_data = 4687 cur_rx->bge_tcp_udp_csum; 4688 m->m_pkthdr.csum_flags |= 4689 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4690 M_CSUM_DATA); 4691 } 4692 } 4693 } 4694 4695 static void 4696 bge_txeof(struct bge_softc *sc) 4697 { 4698 struct bge_tx_bd *cur_tx = NULL; 4699 struct ifnet *ifp; 4700 struct txdmamap_pool_entry *dma; 4701 bus_addr_t offset, toff; 4702 bus_size_t tlen; 4703 int tosync; 4704 struct mbuf *m; 4705 4706 ifp = &sc->ethercom.ec_if; 4707 4708 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4709 offsetof(struct bge_ring_data, bge_status_block), 4710 sizeof (struct bge_status_block), 4711 BUS_DMASYNC_POSTREAD); 4712 4713 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4714 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4715 sc->bge_tx_saved_considx; 4716 4717 if (tosync != 0) 4718 rnd_add_uint32(&sc->rnd_source, tosync); 4719 4720 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4721 4722 if (tosync < 0) { 4723 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4724 sizeof (struct bge_tx_bd); 4725 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4726 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4727 tosync = -tosync; 4728 } 4729 4730 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4731 offset, tosync * sizeof (struct bge_tx_bd), 4732 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4733 4734 /* 4735 * Go through our tx ring and free mbufs for those 4736 * frames that have been sent. 4737 */ 4738 while (sc->bge_tx_saved_considx != 4739 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4740 uint32_t idx = 0; 4741 4742 idx = sc->bge_tx_saved_considx; 4743 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4744 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4745 ifp->if_opackets++; 4746 m = sc->bge_cdata.bge_tx_chain[idx]; 4747 if (m != NULL) { 4748 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4749 dma = sc->txdma[idx]; 4750 if (dma->is_dma32) { 4751 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4752 0, dma->dmamap32->dm_mapsize, 4753 BUS_DMASYNC_POSTWRITE); 4754 bus_dmamap_unload( 4755 sc->bge_dmatag32, dma->dmamap32); 4756 } else { 4757 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4758 0, dma->dmamap->dm_mapsize, 4759 BUS_DMASYNC_POSTWRITE); 4760 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4761 } 4762 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4763 sc->txdma[idx] = NULL; 4764 4765 m_freem(m); 4766 } 4767 sc->bge_txcnt--; 4768 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4769 ifp->if_timer = 0; 4770 } 4771 4772 if (cur_tx != NULL) 4773 ifp->if_flags &= ~IFF_OACTIVE; 4774 } 4775 4776 static int 4777 bge_intr(void *xsc) 4778 { 4779 struct bge_softc *sc; 4780 struct ifnet *ifp; 4781 uint32_t pcistate, statusword, statustag; 4782 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4783 4784 sc = xsc; 4785 ifp = &sc->ethercom.ec_if; 4786 4787 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4788 if (BGE_IS_5717_PLUS(sc)) 4789 intrmask = 0; 4790 4791 /* It is possible for the interrupt to arrive before 4792 * the status block is updated prior to the interrupt. 4793 * Reading the PCI State register will confirm whether the 4794 * interrupt is ours and will flush the status block. 4795 */ 4796 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4797 4798 /* read status word from status block */ 4799 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4800 offsetof(struct bge_ring_data, bge_status_block), 4801 sizeof (struct bge_status_block), 4802 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4803 statusword = sc->bge_rdata->bge_status_block.bge_status; 4804 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4805 4806 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4807 if (sc->bge_lasttag == statustag && 4808 (~pcistate & intrmask)) { 4809 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4810 return (0); 4811 } 4812 sc->bge_lasttag = statustag; 4813 } else { 4814 if (!(statusword & BGE_STATFLAG_UPDATED) && 4815 !(~pcistate & intrmask)) { 4816 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4817 return (0); 4818 } 4819 statustag = 0; 4820 } 4821 /* Ack interrupt and stop others from occurring. */ 4822 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4823 BGE_EVCNT_INCR(sc->bge_ev_intr); 4824 4825 /* clear status word */ 4826 sc->bge_rdata->bge_status_block.bge_status = 0; 4827 4828 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4829 offsetof(struct bge_ring_data, bge_status_block), 4830 sizeof (struct bge_status_block), 4831 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4832 4833 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4834 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4835 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4836 bge_link_upd(sc); 4837 4838 if (ifp->if_flags & IFF_RUNNING) { 4839 /* Check RX return ring producer/consumer */ 4840 bge_rxeof(sc); 4841 4842 /* Check TX ring producer/consumer */ 4843 bge_txeof(sc); 4844 } 4845 4846 if (sc->bge_pending_rxintr_change) { 4847 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4848 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4849 4850 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4851 DELAY(10); 4852 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4853 4854 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4855 DELAY(10); 4856 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4857 4858 sc->bge_pending_rxintr_change = 0; 4859 } 4860 bge_handle_events(sc); 4861 4862 /* Re-enable interrupts. */ 4863 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4864 4865 if (ifp->if_flags & IFF_RUNNING) 4866 if_schedule_deferred_start(ifp); 4867 4868 return 1; 4869 } 4870 4871 static void 4872 bge_asf_driver_up(struct bge_softc *sc) 4873 { 4874 if (sc->bge_asf_mode & ASF_STACKUP) { 4875 /* Send ASF heartbeat aprox. every 2s */ 4876 if (sc->bge_asf_count) 4877 sc->bge_asf_count --; 4878 else { 4879 sc->bge_asf_count = 2; 4880 4881 bge_wait_for_event_ack(sc); 4882 4883 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4884 BGE_FW_CMD_DRV_ALIVE3); 4885 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4886 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4887 BGE_FW_HB_TIMEOUT_SEC); 4888 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4889 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4890 BGE_RX_CPU_DRV_EVENT); 4891 } 4892 } 4893 } 4894 4895 static void 4896 bge_tick(void *xsc) 4897 { 4898 struct bge_softc *sc = xsc; 4899 struct mii_data *mii = &sc->bge_mii; 4900 int s; 4901 4902 s = splnet(); 4903 4904 if (BGE_IS_5705_PLUS(sc)) 4905 bge_stats_update_regs(sc); 4906 else 4907 bge_stats_update(sc); 4908 4909 if (sc->bge_flags & BGEF_FIBER_TBI) { 4910 /* 4911 * Since in TBI mode auto-polling can't be used we should poll 4912 * link status manually. Here we register pending link event 4913 * and trigger interrupt. 4914 */ 4915 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4916 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4917 } else { 4918 /* 4919 * Do not touch PHY if we have link up. This could break 4920 * IPMI/ASF mode or produce extra input errors. 4921 * (extra input errors was reported for bcm5701 & bcm5704). 4922 */ 4923 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4924 mii_tick(mii); 4925 } 4926 4927 bge_asf_driver_up(sc); 4928 4929 if (!sc->bge_detaching) 4930 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4931 4932 splx(s); 4933 } 4934 4935 static void 4936 bge_stats_update_regs(struct bge_softc *sc) 4937 { 4938 struct ifnet *ifp = &sc->ethercom.ec_if; 4939 4940 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4941 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4942 4943 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4944 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4945 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4946 } 4947 4948 static void 4949 bge_stats_update(struct bge_softc *sc) 4950 { 4951 struct ifnet *ifp = &sc->ethercom.ec_if; 4952 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4953 4954 #define READ_STAT(sc, stats, stat) \ 4955 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4956 4957 ifp->if_collisions += 4958 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4959 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4960 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4961 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4962 ifp->if_collisions; 4963 4964 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4965 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4966 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4967 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4968 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4969 READ_STAT(sc, stats, 4970 xoffPauseFramesReceived.bge_addr_lo)); 4971 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4972 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4973 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4974 READ_STAT(sc, stats, 4975 macControlFramesReceived.bge_addr_lo)); 4976 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4977 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4978 4979 #undef READ_STAT 4980 4981 #ifdef notdef 4982 ifp->if_collisions += 4983 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4984 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4985 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4986 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4987 ifp->if_collisions; 4988 #endif 4989 } 4990 4991 /* 4992 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4993 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4994 * but when such padded frames employ the bge IP/TCP checksum offload, 4995 * the hardware checksum assist gives incorrect results (possibly 4996 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4997 * If we pad such runts with zeros, the onboard checksum comes out correct. 4998 */ 4999 static inline int 5000 bge_cksum_pad(struct mbuf *pkt) 5001 { 5002 struct mbuf *last = NULL; 5003 int padlen; 5004 5005 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 5006 5007 /* if there's only the packet-header and we can pad there, use it. */ 5008 if (pkt->m_pkthdr.len == pkt->m_len && 5009 M_TRAILINGSPACE(pkt) >= padlen) { 5010 last = pkt; 5011 } else { 5012 /* 5013 * Walk packet chain to find last mbuf. We will either 5014 * pad there, or append a new mbuf and pad it 5015 * (thus perhaps avoiding the bcm5700 dma-min bug). 5016 */ 5017 for (last = pkt; last->m_next != NULL; last = last->m_next) { 5018 continue; /* do nothing */ 5019 } 5020 5021 /* `last' now points to last in chain. */ 5022 if (M_TRAILINGSPACE(last) < padlen) { 5023 /* Allocate new empty mbuf, pad it. Compact later. */ 5024 struct mbuf *n; 5025 MGET(n, M_DONTWAIT, MT_DATA); 5026 if (n == NULL) 5027 return ENOBUFS; 5028 n->m_len = 0; 5029 last->m_next = n; 5030 last = n; 5031 } 5032 } 5033 5034 KDASSERT(!M_READONLY(last)); 5035 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 5036 5037 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 5038 memset(mtod(last, char *) + last->m_len, 0, padlen); 5039 last->m_len += padlen; 5040 pkt->m_pkthdr.len += padlen; 5041 return 0; 5042 } 5043 5044 /* 5045 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5046 */ 5047 static inline int 5048 bge_compact_dma_runt(struct mbuf *pkt) 5049 { 5050 struct mbuf *m, *prev; 5051 int totlen; 5052 5053 prev = NULL; 5054 totlen = 0; 5055 5056 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 5057 int mlen = m->m_len; 5058 int shortfall = 8 - mlen ; 5059 5060 totlen += mlen; 5061 if (mlen == 0) 5062 continue; 5063 if (mlen >= 8) 5064 continue; 5065 5066 /* If we get here, mbuf data is too small for DMA engine. 5067 * Try to fix by shuffling data to prev or next in chain. 5068 * If that fails, do a compacting deep-copy of the whole chain. 5069 */ 5070 5071 /* Internal frag. If fits in prev, copy it there. */ 5072 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5073 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5074 prev->m_len += mlen; 5075 m->m_len = 0; 5076 /* XXX stitch chain */ 5077 prev->m_next = m_free(m); 5078 m = prev; 5079 continue; 5080 } 5081 else if (m->m_next != NULL && 5082 M_TRAILINGSPACE(m) >= shortfall && 5083 m->m_next->m_len >= (8 + shortfall)) { 5084 /* m is writable and have enough data in next, pull up. */ 5085 5086 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5087 shortfall); 5088 m->m_len += shortfall; 5089 m->m_next->m_len -= shortfall; 5090 m->m_next->m_data += shortfall; 5091 } 5092 else if (m->m_next == NULL || 1) { 5093 /* Got a runt at the very end of the packet. 5094 * borrow data from the tail of the preceding mbuf and 5095 * update its length in-place. (The original data is still 5096 * valid, so we can do this even if prev is not writable.) 5097 */ 5098 5099 /* if we'd make prev a runt, just move all of its data. */ 5100 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5101 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5102 5103 if ((prev->m_len - shortfall) < 8) 5104 shortfall = prev->m_len; 5105 5106 #ifdef notyet /* just do the safe slow thing for now */ 5107 if (!M_READONLY(m)) { 5108 if (M_LEADINGSPACE(m) < shorfall) { 5109 void *m_dat; 5110 m_dat = (m->m_flags & M_PKTHDR) ? 5111 m->m_pktdat : m->dat; 5112 memmove(m_dat, mtod(m, void*), m->m_len); 5113 m->m_data = m_dat; 5114 } 5115 } else 5116 #endif /* just do the safe slow thing */ 5117 { 5118 struct mbuf * n = NULL; 5119 int newprevlen = prev->m_len - shortfall; 5120 5121 MGET(n, M_NOWAIT, MT_DATA); 5122 if (n == NULL) 5123 return ENOBUFS; 5124 KASSERT(m->m_len + shortfall < MLEN 5125 /*, 5126 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5127 5128 /* first copy the data we're stealing from prev */ 5129 memcpy(n->m_data, prev->m_data + newprevlen, 5130 shortfall); 5131 5132 /* update prev->m_len accordingly */ 5133 prev->m_len -= shortfall; 5134 5135 /* copy data from runt m */ 5136 memcpy(n->m_data + shortfall, m->m_data, 5137 m->m_len); 5138 5139 /* n holds what we stole from prev, plus m */ 5140 n->m_len = shortfall + m->m_len; 5141 5142 /* stitch n into chain and free m */ 5143 n->m_next = m->m_next; 5144 prev->m_next = n; 5145 /* KASSERT(m->m_next == NULL); */ 5146 m->m_next = NULL; 5147 m_free(m); 5148 m = n; /* for continuing loop */ 5149 } 5150 } 5151 } 5152 return 0; 5153 } 5154 5155 /* 5156 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5157 * pointers to descriptors. 5158 */ 5159 static int 5160 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5161 { 5162 struct bge_tx_bd *f, *prev_f; 5163 uint32_t frag, cur; 5164 uint16_t csum_flags = 0; 5165 uint16_t txbd_tso_flags = 0; 5166 struct txdmamap_pool_entry *dma; 5167 bus_dmamap_t dmamap; 5168 bus_dma_tag_t dmatag; 5169 int i = 0; 5170 int use_tso, maxsegsize, error; 5171 bool have_vtag; 5172 uint16_t vtag; 5173 5174 if (m_head->m_pkthdr.csum_flags) { 5175 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5176 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5177 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 5178 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5179 } 5180 5181 /* 5182 * If we were asked to do an outboard checksum, and the NIC 5183 * has the bug where it sometimes adds in the Ethernet padding, 5184 * explicitly pad with zeros so the cksum will be correct either way. 5185 * (For now, do this for all chip versions, until newer 5186 * are confirmed to not require the workaround.) 5187 */ 5188 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5189 #ifdef notyet 5190 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5191 #endif 5192 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5193 goto check_dma_bug; 5194 5195 if (bge_cksum_pad(m_head) != 0) 5196 return ENOBUFS; 5197 5198 check_dma_bug: 5199 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5200 goto doit; 5201 5202 /* 5203 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5204 * less than eight bytes. If we encounter a teeny mbuf 5205 * at the end of a chain, we can pad. Otherwise, copy. 5206 */ 5207 if (bge_compact_dma_runt(m_head) != 0) 5208 return ENOBUFS; 5209 5210 doit: 5211 dma = SLIST_FIRST(&sc->txdma_list); 5212 if (dma == NULL) 5213 return ENOBUFS; 5214 dmamap = dma->dmamap; 5215 dmatag = sc->bge_dmatag; 5216 dma->is_dma32 = false; 5217 5218 /* 5219 * Set up any necessary TSO state before we start packing... 5220 */ 5221 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5222 if (!use_tso) { 5223 maxsegsize = 0; 5224 } else { /* TSO setup */ 5225 unsigned mss; 5226 struct ether_header *eh; 5227 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5228 unsigned bge_hlen; 5229 struct mbuf * m0 = m_head; 5230 struct ip *ip; 5231 struct tcphdr *th; 5232 int iphl, hlen; 5233 5234 /* 5235 * XXX It would be nice if the mbuf pkthdr had offset 5236 * fields for the protocol headers. 5237 */ 5238 5239 eh = mtod(m0, struct ether_header *); 5240 switch (htons(eh->ether_type)) { 5241 case ETHERTYPE_IP: 5242 offset = ETHER_HDR_LEN; 5243 break; 5244 5245 case ETHERTYPE_VLAN: 5246 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5247 break; 5248 5249 default: 5250 /* 5251 * Don't support this protocol or encapsulation. 5252 */ 5253 return ENOBUFS; 5254 } 5255 5256 /* 5257 * TCP/IP headers are in the first mbuf; we can do 5258 * this the easy way. 5259 */ 5260 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5261 hlen = iphl + offset; 5262 if (__predict_false(m0->m_len < 5263 (hlen + sizeof(struct tcphdr)))) { 5264 5265 aprint_error_dev(sc->bge_dev, 5266 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5267 "not handled yet\n", 5268 m0->m_len, hlen+ sizeof(struct tcphdr)); 5269 #ifdef NOTYET 5270 /* 5271 * XXX jonathan (at) NetBSD.org: untested. 5272 * how to force this branch to be taken? 5273 */ 5274 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5275 5276 m_copydata(m0, offset, sizeof(ip), &ip); 5277 m_copydata(m0, hlen, sizeof(th), &th); 5278 5279 ip.ip_len = 0; 5280 5281 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5282 sizeof(ip.ip_len), &ip.ip_len); 5283 5284 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5285 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5286 5287 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5288 sizeof(th.th_sum), &th.th_sum); 5289 5290 hlen += th.th_off << 2; 5291 iptcp_opt_words = hlen; 5292 #else 5293 /* 5294 * if_wm "hard" case not yet supported, can we not 5295 * mandate it out of existence? 5296 */ 5297 (void) ip; (void)th; (void) ip_tcp_hlen; 5298 5299 return ENOBUFS; 5300 #endif 5301 } else { 5302 ip = (struct ip *) (mtod(m0, char *) + offset); 5303 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5304 ip_tcp_hlen = iphl + (th->th_off << 2); 5305 5306 /* Total IP/TCP options, in 32-bit words */ 5307 iptcp_opt_words = (ip_tcp_hlen 5308 - sizeof(struct tcphdr) 5309 - sizeof(struct ip)) >> 2; 5310 } 5311 if (BGE_IS_575X_PLUS(sc)) { 5312 th->th_sum = 0; 5313 csum_flags = 0; 5314 } else { 5315 /* 5316 * XXX jonathan (at) NetBSD.org: 5705 untested. 5317 * Requires TSO firmware patch for 5701/5703/5704. 5318 */ 5319 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5320 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5321 } 5322 5323 mss = m_head->m_pkthdr.segsz; 5324 txbd_tso_flags |= 5325 BGE_TXBDFLAG_CPU_PRE_DMA | 5326 BGE_TXBDFLAG_CPU_POST_DMA; 5327 5328 /* 5329 * Our NIC TSO-assist assumes TSO has standard, optionless 5330 * IPv4 and TCP headers, which total 40 bytes. By default, 5331 * the NIC copies 40 bytes of IP/TCP header from the 5332 * supplied header into the IP/TCP header portion of 5333 * each post-TSO-segment. If the supplied packet has IP or 5334 * TCP options, we need to tell the NIC to copy those extra 5335 * bytes into each post-TSO header, in addition to the normal 5336 * 40-byte IP/TCP header (and to leave space accordingly). 5337 * Unfortunately, the driver encoding of option length 5338 * varies across different ASIC families. 5339 */ 5340 tcp_seg_flags = 0; 5341 bge_hlen = ip_tcp_hlen >> 2; 5342 if (BGE_IS_5717_PLUS(sc)) { 5343 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5344 txbd_tso_flags |= 5345 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5346 } else if (BGE_IS_5705_PLUS(sc)) { 5347 tcp_seg_flags = 5348 bge_hlen << 11; 5349 } else { 5350 /* XXX iptcp_opt_words or bge_hlen ? */ 5351 txbd_tso_flags |= 5352 iptcp_opt_words << 12; 5353 } 5354 maxsegsize = mss | tcp_seg_flags; 5355 ip->ip_len = htons(mss + ip_tcp_hlen); 5356 ip->ip_sum = 0; 5357 5358 } /* TSO setup */ 5359 5360 have_vtag = vlan_has_tag(m_head); 5361 if (have_vtag) 5362 vtag = vlan_get_tag(m_head); 5363 5364 /* 5365 * Start packing the mbufs in this chain into 5366 * the fragment pointers. Stop when we run out 5367 * of fragments or hit the end of the mbuf chain. 5368 */ 5369 load_again: 5370 error = bus_dmamap_load_mbuf(dmatag, dmamap, 5371 m_head, BUS_DMA_NOWAIT); 5372 if (error) 5373 return ENOBUFS; 5374 /* 5375 * Sanity check: avoid coming within 16 descriptors 5376 * of the end of the ring. 5377 */ 5378 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5379 BGE_TSO_PRINTF(("%s: " 5380 " dmamap_load_mbuf too close to ring wrap\n", 5381 device_xname(sc->bge_dev))); 5382 goto fail_unload; 5383 } 5384 5385 /* Iterate over dmap-map fragments. */ 5386 f = prev_f = NULL; 5387 cur = frag = *txidx; 5388 5389 for (i = 0; i < dmamap->dm_nsegs; i++) { 5390 f = &sc->bge_rdata->bge_tx_ring[frag]; 5391 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5392 break; 5393 5394 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5395 f->bge_len = dmamap->dm_segs[i].ds_len; 5396 if (dma->is_dma32 == false && prev_f != NULL && 5397 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi) { 5398 /* 5399 * watchdog timeout issue was observed with TSO, 5400 * limiting DMA address space to 32bits seems to 5401 * address the issue. 5402 */ 5403 bus_dmamap_unload(dmatag, dmamap); 5404 dmatag = sc->bge_dmatag32; 5405 dmamap = dma->dmamap32; 5406 dma->is_dma32 = true; 5407 goto load_again; 5408 } 5409 5410 /* 5411 * For 5751 and follow-ons, for TSO we must turn 5412 * off checksum-assist flag in the tx-descr, and 5413 * supply the ASIC-revision-specific encoding 5414 * of TSO flags and segsize. 5415 */ 5416 if (use_tso) { 5417 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5418 f->bge_rsvd = maxsegsize; 5419 f->bge_flags = csum_flags | txbd_tso_flags; 5420 } else { 5421 f->bge_rsvd = 0; 5422 f->bge_flags = 5423 (csum_flags | txbd_tso_flags) & 0x0fff; 5424 } 5425 } else { 5426 f->bge_rsvd = 0; 5427 f->bge_flags = csum_flags; 5428 } 5429 5430 if (have_vtag) { 5431 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5432 f->bge_vlan_tag = vtag; 5433 } else { 5434 f->bge_vlan_tag = 0; 5435 } 5436 prev_f = f; 5437 cur = frag; 5438 BGE_INC(frag, BGE_TX_RING_CNT); 5439 } 5440 5441 if (i < dmamap->dm_nsegs) { 5442 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5443 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5444 goto fail_unload; 5445 } 5446 5447 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5448 BUS_DMASYNC_PREWRITE); 5449 5450 if (frag == sc->bge_tx_saved_considx) { 5451 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5452 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5453 5454 goto fail_unload; 5455 } 5456 5457 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5458 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5459 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5460 sc->txdma[cur] = dma; 5461 sc->bge_txcnt += dmamap->dm_nsegs; 5462 5463 *txidx = frag; 5464 5465 return 0; 5466 5467 fail_unload: 5468 bus_dmamap_unload(dmatag, dmamap); 5469 5470 return ENOBUFS; 5471 } 5472 5473 /* 5474 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5475 * to the mbuf data regions directly in the transmit descriptors. 5476 */ 5477 static void 5478 bge_start(struct ifnet *ifp) 5479 { 5480 struct bge_softc *sc; 5481 struct mbuf *m_head = NULL; 5482 uint32_t prodidx; 5483 int pkts = 0; 5484 5485 sc = ifp->if_softc; 5486 5487 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5488 return; 5489 5490 prodidx = sc->bge_tx_prodidx; 5491 5492 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5493 IFQ_POLL(&ifp->if_snd, m_head); 5494 if (m_head == NULL) 5495 break; 5496 5497 #if 0 5498 /* 5499 * XXX 5500 * safety overkill. If this is a fragmented packet chain 5501 * with delayed TCP/UDP checksums, then only encapsulate 5502 * it if we have enough descriptors to handle the entire 5503 * chain at once. 5504 * (paranoia -- may not actually be needed) 5505 */ 5506 if (m_head->m_flags & M_FIRSTFRAG && 5507 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5508 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5509 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5510 ifp->if_flags |= IFF_OACTIVE; 5511 break; 5512 } 5513 } 5514 #endif 5515 5516 /* 5517 * Pack the data into the transmit ring. If we 5518 * don't have room, set the OACTIVE flag and wait 5519 * for the NIC to drain the ring. 5520 */ 5521 if (bge_encap(sc, m_head, &prodidx)) { 5522 ifp->if_flags |= IFF_OACTIVE; 5523 break; 5524 } 5525 5526 /* now we are committed to transmit the packet */ 5527 IFQ_DEQUEUE(&ifp->if_snd, m_head); 5528 pkts++; 5529 5530 /* 5531 * If there's a BPF listener, bounce a copy of this frame 5532 * to him. 5533 */ 5534 bpf_mtap(ifp, m_head, BPF_D_OUT); 5535 } 5536 if (pkts == 0) 5537 return; 5538 5539 /* Transmit */ 5540 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5541 /* 5700 b2 errata */ 5542 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5543 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5544 5545 sc->bge_tx_prodidx = prodidx; 5546 5547 /* 5548 * Set a timeout in case the chip goes out to lunch. 5549 */ 5550 ifp->if_timer = 5; 5551 } 5552 5553 static int 5554 bge_init(struct ifnet *ifp) 5555 { 5556 struct bge_softc *sc = ifp->if_softc; 5557 const uint16_t *m; 5558 uint32_t mode, reg; 5559 int s, error = 0; 5560 5561 s = splnet(); 5562 5563 ifp = &sc->ethercom.ec_if; 5564 5565 /* Cancel pending I/O and flush buffers. */ 5566 bge_stop(ifp, 0); 5567 5568 bge_stop_fw(sc); 5569 bge_sig_pre_reset(sc, BGE_RESET_START); 5570 bge_reset(sc); 5571 bge_sig_legacy(sc, BGE_RESET_START); 5572 5573 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5574 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5575 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5576 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5577 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5578 5579 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5580 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5581 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5582 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5583 5584 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5585 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5586 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5587 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5588 5589 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5590 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5591 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5592 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5593 } 5594 5595 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5596 pcireg_t aercap; 5597 5598 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5599 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5600 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5601 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5602 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5603 5604 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5605 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5606 | BGE_PCIE_EIDLE_DELAY_13CLK; 5607 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5608 5609 /* Clear correctable error */ 5610 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5611 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5612 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5613 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5614 5615 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5616 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5617 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5618 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5619 } 5620 5621 bge_sig_post_reset(sc, BGE_RESET_START); 5622 5623 bge_chipinit(sc); 5624 5625 /* 5626 * Init the various state machines, ring 5627 * control blocks and firmware. 5628 */ 5629 error = bge_blockinit(sc); 5630 if (error != 0) { 5631 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5632 error); 5633 splx(s); 5634 return error; 5635 } 5636 5637 ifp = &sc->ethercom.ec_if; 5638 5639 /* 5718 step 25, 57XX step 54 */ 5640 /* Specify MTU. */ 5641 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5642 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5643 5644 /* 5718 step 23 */ 5645 /* Load our MAC address. */ 5646 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5647 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5648 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5649 5650 /* Enable or disable promiscuous mode as needed. */ 5651 if (ifp->if_flags & IFF_PROMISC) 5652 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5653 else 5654 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5655 5656 /* Program multicast filter. */ 5657 bge_setmulti(sc); 5658 5659 /* Init RX ring. */ 5660 bge_init_rx_ring_std(sc); 5661 5662 /* 5663 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5664 * memory to insure that the chip has in fact read the first 5665 * entry of the ring. 5666 */ 5667 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5668 uint32_t v, i; 5669 for (i = 0; i < 10; i++) { 5670 DELAY(20); 5671 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5672 if (v == (MCLBYTES - ETHER_ALIGN)) 5673 break; 5674 } 5675 if (i == 10) 5676 aprint_error_dev(sc->bge_dev, 5677 "5705 A0 chip failed to load RX ring\n"); 5678 } 5679 5680 /* Init jumbo RX ring. */ 5681 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5682 bge_init_rx_ring_jumbo(sc); 5683 5684 /* Init our RX return ring index */ 5685 sc->bge_rx_saved_considx = 0; 5686 5687 /* Init TX ring. */ 5688 bge_init_tx_ring(sc); 5689 5690 /* 5718 step 63, 57XX step 94 */ 5691 /* Enable TX MAC state machine lockup fix. */ 5692 mode = CSR_READ_4(sc, BGE_TX_MODE); 5693 if (BGE_IS_5755_PLUS(sc) || 5694 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5695 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5696 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5697 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5698 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5699 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5700 } 5701 5702 /* Turn on transmitter */ 5703 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5704 /* 5718 step 64 */ 5705 DELAY(100); 5706 5707 /* 5718 step 65, 57XX step 95 */ 5708 /* Turn on receiver */ 5709 mode = CSR_READ_4(sc, BGE_RX_MODE); 5710 if (BGE_IS_5755_PLUS(sc)) 5711 mode |= BGE_RXMODE_IPV6_ENABLE; 5712 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5713 /* 5718 step 66 */ 5714 DELAY(10); 5715 5716 /* 5718 step 12, 57XX step 37 */ 5717 /* 5718 * XXX Doucments of 5718 series and 577xx say the recommended value 5719 * is 1, but tg3 set 1 only on 57765 series. 5720 */ 5721 if (BGE_IS_57765_PLUS(sc)) 5722 reg = 1; 5723 else 5724 reg = 2; 5725 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5726 5727 /* Tell firmware we're alive. */ 5728 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5729 5730 /* Enable host interrupts. */ 5731 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5732 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5733 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5734 5735 if ((error = bge_ifmedia_upd(ifp)) != 0) 5736 goto out; 5737 5738 ifp->if_flags |= IFF_RUNNING; 5739 ifp->if_flags &= ~IFF_OACTIVE; 5740 5741 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5742 5743 out: 5744 sc->bge_if_flags = ifp->if_flags; 5745 splx(s); 5746 5747 return error; 5748 } 5749 5750 /* 5751 * Set media options. 5752 */ 5753 static int 5754 bge_ifmedia_upd(struct ifnet *ifp) 5755 { 5756 struct bge_softc *sc = ifp->if_softc; 5757 struct mii_data *mii = &sc->bge_mii; 5758 struct ifmedia *ifm = &sc->bge_ifmedia; 5759 int rc; 5760 5761 /* If this is a 1000baseX NIC, enable the TBI port. */ 5762 if (sc->bge_flags & BGEF_FIBER_TBI) { 5763 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5764 return EINVAL; 5765 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5766 case IFM_AUTO: 5767 /* 5768 * The BCM5704 ASIC appears to have a special 5769 * mechanism for programming the autoneg 5770 * advertisement registers in TBI mode. 5771 */ 5772 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5773 uint32_t sgdig; 5774 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5775 if (sgdig & BGE_SGDIGSTS_DONE) { 5776 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5777 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5778 sgdig |= BGE_SGDIGCFG_AUTO | 5779 BGE_SGDIGCFG_PAUSE_CAP | 5780 BGE_SGDIGCFG_ASYM_PAUSE; 5781 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5782 sgdig | BGE_SGDIGCFG_SEND); 5783 DELAY(5); 5784 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5785 sgdig); 5786 } 5787 } 5788 break; 5789 case IFM_1000_SX: 5790 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5791 BGE_CLRBIT(sc, BGE_MAC_MODE, 5792 BGE_MACMODE_HALF_DUPLEX); 5793 } else { 5794 BGE_SETBIT(sc, BGE_MAC_MODE, 5795 BGE_MACMODE_HALF_DUPLEX); 5796 } 5797 DELAY(40); 5798 break; 5799 default: 5800 return EINVAL; 5801 } 5802 /* XXX 802.3x flow control for 1000BASE-SX */ 5803 return 0; 5804 } 5805 5806 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5807 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5808 uint32_t reg; 5809 5810 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5811 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5812 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5813 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5814 } 5815 } 5816 5817 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5818 if ((rc = mii_mediachg(mii)) == ENXIO) 5819 return 0; 5820 5821 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5822 uint32_t reg; 5823 5824 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5825 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5826 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5827 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5828 delay(40); 5829 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5830 } 5831 } 5832 5833 /* 5834 * Force an interrupt so that we will call bge_link_upd 5835 * if needed and clear any pending link state attention. 5836 * Without this we are not getting any further interrupts 5837 * for link state changes and thus will not UP the link and 5838 * not be able to send in bge_start. The only way to get 5839 * things working was to receive a packet and get a RX intr. 5840 */ 5841 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5842 sc->bge_flags & BGEF_IS_5788) 5843 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5844 else 5845 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5846 5847 return rc; 5848 } 5849 5850 /* 5851 * Report current media status. 5852 */ 5853 static void 5854 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5855 { 5856 struct bge_softc *sc = ifp->if_softc; 5857 struct mii_data *mii = &sc->bge_mii; 5858 5859 if (sc->bge_flags & BGEF_FIBER_TBI) { 5860 ifmr->ifm_status = IFM_AVALID; 5861 ifmr->ifm_active = IFM_ETHER; 5862 if (CSR_READ_4(sc, BGE_MAC_STS) & 5863 BGE_MACSTAT_TBI_PCS_SYNCHED) 5864 ifmr->ifm_status |= IFM_ACTIVE; 5865 ifmr->ifm_active |= IFM_1000_SX; 5866 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5867 ifmr->ifm_active |= IFM_HDX; 5868 else 5869 ifmr->ifm_active |= IFM_FDX; 5870 return; 5871 } 5872 5873 mii_pollstat(mii); 5874 ifmr->ifm_status = mii->mii_media_status; 5875 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5876 sc->bge_flowflags; 5877 } 5878 5879 static int 5880 bge_ifflags_cb(struct ethercom *ec) 5881 { 5882 struct ifnet *ifp = &ec->ec_if; 5883 struct bge_softc *sc = ifp->if_softc; 5884 int change = ifp->if_flags ^ sc->bge_if_flags; 5885 5886 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5887 return ENETRESET; 5888 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5889 return 0; 5890 5891 if ((ifp->if_flags & IFF_PROMISC) == 0) 5892 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5893 else 5894 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5895 5896 bge_setmulti(sc); 5897 5898 sc->bge_if_flags = ifp->if_flags; 5899 return 0; 5900 } 5901 5902 static int 5903 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5904 { 5905 struct bge_softc *sc = ifp->if_softc; 5906 struct ifreq *ifr = (struct ifreq *) data; 5907 int s, error = 0; 5908 struct mii_data *mii; 5909 5910 s = splnet(); 5911 5912 switch (command) { 5913 case SIOCSIFMEDIA: 5914 /* XXX Flow control is not supported for 1000BASE-SX */ 5915 if (sc->bge_flags & BGEF_FIBER_TBI) { 5916 ifr->ifr_media &= ~IFM_ETH_FMASK; 5917 sc->bge_flowflags = 0; 5918 } 5919 5920 /* Flow control requires full-duplex mode. */ 5921 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5922 (ifr->ifr_media & IFM_FDX) == 0) { 5923 ifr->ifr_media &= ~IFM_ETH_FMASK; 5924 } 5925 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5926 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5927 /* We can do both TXPAUSE and RXPAUSE. */ 5928 ifr->ifr_media |= 5929 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5930 } 5931 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5932 } 5933 /* FALLTHROUGH */ 5934 case SIOCGIFMEDIA: 5935 if (sc->bge_flags & BGEF_FIBER_TBI) { 5936 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5937 command); 5938 } else { 5939 mii = &sc->bge_mii; 5940 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5941 command); 5942 } 5943 break; 5944 default: 5945 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5946 break; 5947 5948 error = 0; 5949 5950 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5951 ; 5952 else if (ifp->if_flags & IFF_RUNNING) 5953 bge_setmulti(sc); 5954 break; 5955 } 5956 5957 splx(s); 5958 5959 return error; 5960 } 5961 5962 static void 5963 bge_watchdog(struct ifnet *ifp) 5964 { 5965 struct bge_softc *sc; 5966 5967 sc = ifp->if_softc; 5968 5969 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5970 5971 ifp->if_flags &= ~IFF_RUNNING; 5972 bge_init(ifp); 5973 5974 ifp->if_oerrors++; 5975 } 5976 5977 static void 5978 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5979 { 5980 int i; 5981 5982 BGE_CLRBIT_FLUSH(sc, reg, bit); 5983 5984 for (i = 0; i < 1000; i++) { 5985 delay(100); 5986 if ((CSR_READ_4(sc, reg) & bit) == 0) 5987 return; 5988 } 5989 5990 /* 5991 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5992 * on some environment (and once after boot?) 5993 */ 5994 if (reg != BGE_SRS_MODE) 5995 aprint_error_dev(sc->bge_dev, 5996 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5997 (u_long)reg, bit); 5998 } 5999 6000 /* 6001 * Stop the adapter and free any mbufs allocated to the 6002 * RX and TX lists. 6003 */ 6004 static void 6005 bge_stop(struct ifnet *ifp, int disable) 6006 { 6007 struct bge_softc *sc = ifp->if_softc; 6008 6009 if (disable) { 6010 sc->bge_detaching = 1; 6011 callout_halt(&sc->bge_timeout, NULL); 6012 } else 6013 callout_stop(&sc->bge_timeout); 6014 6015 /* Disable host interrupts. */ 6016 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6017 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6018 6019 /* 6020 * Tell firmware we're shutting down. 6021 */ 6022 bge_stop_fw(sc); 6023 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6024 6025 /* 6026 * Disable all of the receiver blocks. 6027 */ 6028 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6029 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6030 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6031 if (BGE_IS_5700_FAMILY(sc)) 6032 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6033 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6034 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6035 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6036 6037 /* 6038 * Disable all of the transmit blocks. 6039 */ 6040 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6041 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6042 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6043 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6044 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6045 if (BGE_IS_5700_FAMILY(sc)) 6046 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6047 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6048 6049 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6050 delay(40); 6051 6052 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6053 6054 /* 6055 * Shut down all of the memory managers and related 6056 * state machines. 6057 */ 6058 /* 5718 step 5a,5b */ 6059 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6060 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6061 if (BGE_IS_5700_FAMILY(sc)) 6062 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6063 6064 /* 5718 step 5c,5d */ 6065 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6066 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6067 6068 if (BGE_IS_5700_FAMILY(sc)) { 6069 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6070 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6071 } 6072 6073 bge_reset(sc); 6074 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6075 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6076 6077 /* 6078 * Keep the ASF firmware running if up. 6079 */ 6080 if (sc->bge_asf_mode & ASF_STACKUP) 6081 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6082 else 6083 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6084 6085 /* Free the RX lists. */ 6086 bge_free_rx_ring_std(sc); 6087 6088 /* Free jumbo RX list. */ 6089 if (BGE_IS_JUMBO_CAPABLE(sc)) 6090 bge_free_rx_ring_jumbo(sc); 6091 6092 /* Free TX buffers. */ 6093 bge_free_tx_ring(sc); 6094 6095 /* 6096 * Isolate/power down the PHY. 6097 */ 6098 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6099 mii_down(&sc->bge_mii); 6100 6101 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6102 6103 /* Clear MAC's link state (PHY may still have link UP). */ 6104 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6105 6106 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6107 } 6108 6109 static void 6110 bge_link_upd(struct bge_softc *sc) 6111 { 6112 struct ifnet *ifp = &sc->ethercom.ec_if; 6113 struct mii_data *mii = &sc->bge_mii; 6114 uint32_t status; 6115 int link; 6116 6117 /* Clear 'pending link event' flag */ 6118 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6119 6120 /* 6121 * Process link state changes. 6122 * Grrr. The link status word in the status block does 6123 * not work correctly on the BCM5700 rev AX and BX chips, 6124 * according to all available information. Hence, we have 6125 * to enable MII interrupts in order to properly obtain 6126 * async link changes. Unfortunately, this also means that 6127 * we have to read the MAC status register to detect link 6128 * changes, thereby adding an additional register access to 6129 * the interrupt handler. 6130 */ 6131 6132 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6133 status = CSR_READ_4(sc, BGE_MAC_STS); 6134 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6135 mii_pollstat(mii); 6136 6137 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6138 mii->mii_media_status & IFM_ACTIVE && 6139 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6140 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6141 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6142 (!(mii->mii_media_status & IFM_ACTIVE) || 6143 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6144 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6145 6146 /* Clear the interrupt */ 6147 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6148 BGE_EVTENB_MI_INTERRUPT); 6149 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6150 BRGPHY_MII_ISR); 6151 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6152 BRGPHY_MII_IMR, BRGPHY_INTRS); 6153 } 6154 return; 6155 } 6156 6157 if (sc->bge_flags & BGEF_FIBER_TBI) { 6158 status = CSR_READ_4(sc, BGE_MAC_STS); 6159 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6160 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6161 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6162 if (BGE_ASICREV(sc->bge_chipid) 6163 == BGE_ASICREV_BCM5704) { 6164 BGE_CLRBIT(sc, BGE_MAC_MODE, 6165 BGE_MACMODE_TBI_SEND_CFGS); 6166 DELAY(40); 6167 } 6168 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6169 if_link_state_change(ifp, LINK_STATE_UP); 6170 } 6171 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6172 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6173 if_link_state_change(ifp, LINK_STATE_DOWN); 6174 } 6175 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6176 /* 6177 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6178 * bit in status word always set. Workaround this bug by 6179 * reading PHY link status directly. 6180 */ 6181 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6182 BGE_STS_LINK : 0; 6183 6184 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6185 mii_pollstat(mii); 6186 6187 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6188 mii->mii_media_status & IFM_ACTIVE && 6189 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6190 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6191 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6192 (!(mii->mii_media_status & IFM_ACTIVE) || 6193 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6194 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6195 } 6196 } else { 6197 /* 6198 * For controllers that call mii_tick, we have to poll 6199 * link status. 6200 */ 6201 mii_pollstat(mii); 6202 } 6203 6204 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6205 uint32_t reg, scale; 6206 6207 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6208 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6209 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6210 scale = 65; 6211 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6212 scale = 6; 6213 else 6214 scale = 12; 6215 6216 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6217 ~BGE_MISCCFG_TIMER_PRESCALER; 6218 reg |= scale << 1; 6219 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6220 } 6221 /* Clear the attention */ 6222 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6223 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6224 BGE_MACSTAT_LINK_CHANGED); 6225 } 6226 6227 static int 6228 bge_sysctl_verify(SYSCTLFN_ARGS) 6229 { 6230 int error, t; 6231 struct sysctlnode node; 6232 6233 node = *rnode; 6234 t = *(int*)rnode->sysctl_data; 6235 node.sysctl_data = &t; 6236 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6237 if (error || newp == NULL) 6238 return error; 6239 6240 #if 0 6241 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6242 node.sysctl_num, rnode->sysctl_num)); 6243 #endif 6244 6245 if (node.sysctl_num == bge_rxthresh_nodenum) { 6246 if (t < 0 || t >= NBGE_RX_THRESH) 6247 return EINVAL; 6248 bge_update_all_threshes(t); 6249 } else 6250 return EINVAL; 6251 6252 *(int*)rnode->sysctl_data = t; 6253 6254 return 0; 6255 } 6256 6257 /* 6258 * Set up sysctl(3) MIB, hw.bge.*. 6259 */ 6260 static void 6261 bge_sysctl_init(struct bge_softc *sc) 6262 { 6263 int rc, bge_root_num; 6264 const struct sysctlnode *node; 6265 6266 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6267 0, CTLTYPE_NODE, "bge", 6268 SYSCTL_DESCR("BGE interface controls"), 6269 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6270 goto out; 6271 } 6272 6273 bge_root_num = node->sysctl_num; 6274 6275 /* BGE Rx interrupt mitigation level */ 6276 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6277 CTLFLAG_READWRITE, 6278 CTLTYPE_INT, "rx_lvl", 6279 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6280 bge_sysctl_verify, 0, 6281 &bge_rx_thresh_lvl, 6282 0, CTL_HW, bge_root_num, CTL_CREATE, 6283 CTL_EOL)) != 0) { 6284 goto out; 6285 } 6286 6287 bge_rxthresh_nodenum = node->sysctl_num; 6288 6289 return; 6290 6291 out: 6292 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6293 } 6294 6295 #ifdef BGE_DEBUG 6296 void 6297 bge_debug_info(struct bge_softc *sc) 6298 { 6299 6300 printf("Hardware Flags:\n"); 6301 if (BGE_IS_57765_PLUS(sc)) 6302 printf(" - 57765 Plus\n"); 6303 if (BGE_IS_5717_PLUS(sc)) 6304 printf(" - 5717 Plus\n"); 6305 if (BGE_IS_5755_PLUS(sc)) 6306 printf(" - 5755 Plus\n"); 6307 if (BGE_IS_575X_PLUS(sc)) 6308 printf(" - 575X Plus\n"); 6309 if (BGE_IS_5705_PLUS(sc)) 6310 printf(" - 5705 Plus\n"); 6311 if (BGE_IS_5714_FAMILY(sc)) 6312 printf(" - 5714 Family\n"); 6313 if (BGE_IS_5700_FAMILY(sc)) 6314 printf(" - 5700 Family\n"); 6315 if (sc->bge_flags & BGEF_IS_5788) 6316 printf(" - 5788\n"); 6317 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6318 printf(" - Supports Jumbo Frames\n"); 6319 if (sc->bge_flags & BGEF_NO_EEPROM) 6320 printf(" - No EEPROM\n"); 6321 if (sc->bge_flags & BGEF_PCIX) 6322 printf(" - PCI-X Bus\n"); 6323 if (sc->bge_flags & BGEF_PCIE) 6324 printf(" - PCI Express Bus\n"); 6325 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6326 printf(" - RX Alignment Bug\n"); 6327 if (sc->bge_flags & BGEF_APE) 6328 printf(" - APE\n"); 6329 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6330 printf(" - CPMU\n"); 6331 if (sc->bge_flags & BGEF_TSO) 6332 printf(" - TSO\n"); 6333 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6334 printf(" - TAGGED_STATUS\n"); 6335 6336 /* PHY related */ 6337 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6338 printf(" - No 3 LEDs\n"); 6339 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6340 printf(" - CRC bug\n"); 6341 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6342 printf(" - ADC bug\n"); 6343 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6344 printf(" - 5704 A0 bug\n"); 6345 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6346 printf(" - jitter bug\n"); 6347 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6348 printf(" - BER bug\n"); 6349 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6350 printf(" - adjust trim\n"); 6351 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6352 printf(" - no wirespeed\n"); 6353 6354 /* ASF related */ 6355 if (sc->bge_asf_mode & ASF_ENABLE) 6356 printf(" - ASF enable\n"); 6357 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6358 printf(" - ASF new handshake\n"); 6359 if (sc->bge_asf_mode & ASF_STACKUP) 6360 printf(" - ASF stackup\n"); 6361 } 6362 #endif /* BGE_DEBUG */ 6363 6364 static int 6365 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6366 { 6367 prop_dictionary_t dict; 6368 prop_data_t ea; 6369 6370 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6371 return 1; 6372 6373 dict = device_properties(sc->bge_dev); 6374 ea = prop_dictionary_get(dict, "mac-address"); 6375 if (ea != NULL) { 6376 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6377 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6378 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6379 return 0; 6380 } 6381 6382 return 1; 6383 } 6384 6385 static int 6386 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6387 { 6388 uint32_t mac_addr; 6389 6390 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6391 if ((mac_addr >> 16) == 0x484b) { 6392 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6393 ether_addr[1] = (uint8_t)mac_addr; 6394 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6395 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6396 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6397 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6398 ether_addr[5] = (uint8_t)mac_addr; 6399 return 0; 6400 } 6401 return 1; 6402 } 6403 6404 static int 6405 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6406 { 6407 int mac_offset = BGE_EE_MAC_OFFSET; 6408 6409 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6410 mac_offset = BGE_EE_MAC_OFFSET_5906; 6411 6412 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6413 ETHER_ADDR_LEN)); 6414 } 6415 6416 static int 6417 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6418 { 6419 6420 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6421 return 1; 6422 6423 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6424 ETHER_ADDR_LEN)); 6425 } 6426 6427 static int 6428 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6429 { 6430 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6431 /* NOTE: Order is critical */ 6432 bge_get_eaddr_fw, 6433 bge_get_eaddr_mem, 6434 bge_get_eaddr_nvram, 6435 bge_get_eaddr_eeprom, 6436 NULL 6437 }; 6438 const bge_eaddr_fcn_t *func; 6439 6440 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6441 if ((*func)(sc, eaddr) == 0) 6442 break; 6443 } 6444 return (*func == NULL ? ENXIO : 0); 6445 } 6446
Indexes created Mon Sep 22 13:09:51 GMT 2025