if_bge.c revision 1.322
1 /* $NetBSD: if_bge.c,v 1.322 2019/01/22 03:42:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.322 2019/01/22 03:42:27 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_can_use_msi(struct bge_softc *); 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static int bge_detach(device_t, int); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *m, bool); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 254 static int bge_miibus_writereg(device_t, int, int, uint16_t); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5750, 440 "Broadcom BCM5750 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5751, 444 "Broadcom BCM5751 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5751F, 448 "Broadcom BCM5751F Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751M, 452 "Broadcom BCM5751M Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5752, 456 "Broadcom BCM5752 Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5752M, 460 "Broadcom BCM5752M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5753, 464 "Broadcom BCM5753 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5753F, 468 "Broadcom BCM5753F Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753M, 472 "Broadcom BCM5753M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5754, 476 "Broadcom BCM5754 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5754M, 480 "Broadcom BCM5754M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5755, 484 "Broadcom BCM5755 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5755M, 488 "Broadcom BCM5755M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5756, 492 "Broadcom BCM5756 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5761, 496 "Broadcom BCM5761 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5761E, 500 "Broadcom BCM5761E Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761S, 504 "Broadcom BCM5761S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761SE, 508 "Broadcom BCM5761SE Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5764, 512 "Broadcom BCM5764 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5780, 516 "Broadcom BCM5780 Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5780S, 520 "Broadcom BCM5780S Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5781, 524 "Broadcom BCM5781 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5782, 528 "Broadcom BCM5782 Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5784M, 532 "BCM5784M NetLink 1000baseT Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5785F, 536 "BCM5785F NetLink 10/100 Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5785G, 540 "BCM5785G NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5786, 544 "Broadcom BCM5786 Gigabit Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5787, 548 "Broadcom BCM5787 Gigabit Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5787F, 552 "Broadcom BCM5787F 10/100 Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787M, 556 "Broadcom BCM5787M Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5788, 560 "Broadcom BCM5788 Gigabit Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5789, 564 "Broadcom BCM5789 Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5901, 568 "Broadcom BCM5901 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5901A2, 572 "Broadcom BCM5901A2 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5903M, 576 "Broadcom BCM5903M Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5906, 580 "Broadcom BCM5906 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5906M, 584 "Broadcom BCM5906M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57760, 588 "Broadcom BCM57760 Gigabit Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57761, 592 "Broadcom BCM57761 Gigabit Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57762, 596 "Broadcom BCM57762 Gigabit Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57765, 600 "Broadcom BCM57765 Gigabit Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57766, 604 "Broadcom BCM57766 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57780, 608 "Broadcom BCM57780 Gigabit Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57781, 612 "Broadcom BCM57781 Gigabit Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57782, 616 "Broadcom BCM57782 Gigabit Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57785, 620 "Broadcom BCM57785 Gigabit Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57786, 624 "Broadcom BCM57786 Gigabit Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57788, 628 "Broadcom BCM57788 Gigabit Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57790, 632 "Broadcom BCM57790 Gigabit Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57791, 636 "Broadcom BCM57791 Gigabit Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57795, 640 "Broadcom BCM57795 Gigabit Ethernet", 641 }, 642 { PCI_VENDOR_SCHNEIDERKOCH, 643 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 644 "SysKonnect SK-9Dx1 Gigabit Ethernet", 645 }, 646 { PCI_VENDOR_3COM, 647 PCI_PRODUCT_3COM_3C996, 648 "3Com 3c996 Gigabit Ethernet", 649 }, 650 { PCI_VENDOR_FUJITSU4, 651 PCI_PRODUCT_FUJITSU4_PW008GE4, 652 "Fujitsu PW008GE4 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_FUJITSU4, 655 PCI_PRODUCT_FUJITSU4_PW008GE5, 656 "Fujitsu PW008GE5 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 660 "Fujitsu Primepower 250/450 Gigabit Ethernet", 661 }, 662 { 0, 663 0, 664 NULL }, 665 }; 666 667 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 668 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 669 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 670 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 671 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 672 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 673 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 674 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 675 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 676 677 static const struct bge_revision { 678 uint32_t br_chipid; 679 const char *br_name; 680 } bge_revisions[] = { 681 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 682 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 683 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 684 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 685 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 686 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 687 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 688 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 689 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 690 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 691 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 692 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 693 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 694 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 695 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 696 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 697 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 698 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 699 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 700 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 701 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 702 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 703 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 704 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 705 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 706 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 707 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 708 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 709 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 710 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 711 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 712 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 713 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 714 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 715 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 716 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 717 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 718 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 719 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 720 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 721 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 722 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 723 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 724 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 725 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 726 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 727 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 728 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 729 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 730 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 731 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 732 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 733 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 734 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 735 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 736 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 737 /* 5754 and 5787 share the same ASIC ID */ 738 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 739 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 740 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 741 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 742 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 743 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 744 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 745 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 746 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 747 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 748 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 749 750 { 0, NULL } 751 }; 752 753 /* 754 * Some defaults for major revisions, so that newer steppings 755 * that we don't know about have a shot at working. 756 */ 757 static const struct bge_revision bge_majorrevs[] = { 758 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 759 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 760 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 761 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 762 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 763 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 764 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 765 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 766 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 767 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 768 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 769 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 770 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 771 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 772 /* 5754 and 5787 share the same ASIC ID */ 773 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 774 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 775 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 776 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 777 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 778 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 779 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 780 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 781 782 { 0, NULL } 783 }; 784 785 static int bge_allow_asf = 1; 786 787 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 788 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 789 790 static uint32_t 791 bge_readmem_ind(struct bge_softc *sc, int off) 792 { 793 pcireg_t val; 794 795 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 796 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 797 return 0; 798 799 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 800 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 801 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 802 return val; 803 } 804 805 static void 806 bge_writemem_ind(struct bge_softc *sc, int off, int val) 807 { 808 809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 811 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 812 } 813 814 /* 815 * PCI Express only 816 */ 817 static void 818 bge_set_max_readrq(struct bge_softc *sc) 819 { 820 pcireg_t val; 821 822 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 823 + PCIE_DCSR); 824 val &= ~PCIE_DCSR_MAX_READ_REQ; 825 switch (sc->bge_expmrq) { 826 case 2048: 827 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 828 break; 829 case 4096: 830 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 831 break; 832 default: 833 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 834 break; 835 } 836 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 837 + PCIE_DCSR, val); 838 } 839 840 #ifdef notdef 841 static uint32_t 842 bge_readreg_ind(struct bge_softc *sc, int off) 843 { 844 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 845 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 846 } 847 #endif 848 849 static void 850 bge_writereg_ind(struct bge_softc *sc, int off, int val) 851 { 852 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 853 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 854 } 855 856 static void 857 bge_writemem_direct(struct bge_softc *sc, int off, int val) 858 { 859 CSR_WRITE_4(sc, off, val); 860 } 861 862 static void 863 bge_writembx(struct bge_softc *sc, int off, int val) 864 { 865 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 866 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 867 868 CSR_WRITE_4(sc, off, val); 869 } 870 871 static void 872 bge_writembx_flush(struct bge_softc *sc, int off, int val) 873 { 874 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 875 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 876 877 CSR_WRITE_4_FLUSH(sc, off, val); 878 } 879 880 /* 881 * Clear all stale locks and select the lock for this driver instance. 882 */ 883 void 884 bge_ape_lock_init(struct bge_softc *sc) 885 { 886 struct pci_attach_args *pa = &(sc->bge_pa); 887 uint32_t bit, regbase; 888 int i; 889 890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 891 regbase = BGE_APE_LOCK_GRANT; 892 else 893 regbase = BGE_APE_PER_LOCK_GRANT; 894 895 /* Clear any stale locks. */ 896 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 897 switch (i) { 898 case BGE_APE_LOCK_PHY0: 899 case BGE_APE_LOCK_PHY1: 900 case BGE_APE_LOCK_PHY2: 901 case BGE_APE_LOCK_PHY3: 902 bit = BGE_APE_LOCK_GRANT_DRIVER0; 903 break; 904 default: 905 if (pa->pa_function == 0) 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 else 908 bit = (1 << pa->pa_function); 909 } 910 APE_WRITE_4(sc, regbase + 4 * i, bit); 911 } 912 913 /* Select the PHY lock based on the device's function number. */ 914 switch (pa->pa_function) { 915 case 0: 916 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 917 break; 918 case 1: 919 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 920 break; 921 case 2: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 923 break; 924 case 3: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 926 break; 927 default: 928 printf("%s: PHY lock not supported on function\n", 929 device_xname(sc->bge_dev)); 930 break; 931 } 932 } 933 934 /* 935 * Check for APE firmware, set flags, and print version info. 936 */ 937 void 938 bge_ape_read_fw_ver(struct bge_softc *sc) 939 { 940 const char *fwtype; 941 uint32_t apedata, features; 942 943 /* Check for a valid APE signature in shared memory. */ 944 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 945 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 946 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 947 return; 948 } 949 950 /* Check if APE firmware is running. */ 951 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 952 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 953 printf("%s: APE signature found but FW status not ready! " 954 "0x%08x\n", device_xname(sc->bge_dev), apedata); 955 return; 956 } 957 958 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 959 960 /* Fetch the APE firwmare type and version. */ 961 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 962 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 963 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 964 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 965 fwtype = "NCSI"; 966 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 967 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 968 fwtype = "DASH"; 969 } else 970 fwtype = "UNKN"; 971 972 /* Print the APE firmware version. */ 973 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 974 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 975 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 976 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 977 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 978 } 979 980 int 981 bge_ape_lock(struct bge_softc *sc, int locknum) 982 { 983 struct pci_attach_args *pa = &(sc->bge_pa); 984 uint32_t bit, gnt, req, status; 985 int i, off; 986 987 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 988 return (0); 989 990 /* Lock request/grant registers have different bases. */ 991 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 992 req = BGE_APE_LOCK_REQ; 993 gnt = BGE_APE_LOCK_GRANT; 994 } else { 995 req = BGE_APE_PER_LOCK_REQ; 996 gnt = BGE_APE_PER_LOCK_GRANT; 997 } 998 999 off = 4 * locknum; 1000 1001 switch (locknum) { 1002 case BGE_APE_LOCK_GPIO: 1003 /* Lock required when using GPIO. */ 1004 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1005 return (0); 1006 if (pa->pa_function == 0) 1007 bit = BGE_APE_LOCK_REQ_DRIVER0; 1008 else 1009 bit = (1 << pa->pa_function); 1010 break; 1011 case BGE_APE_LOCK_GRC: 1012 /* Lock required to reset the device. */ 1013 if (pa->pa_function == 0) 1014 bit = BGE_APE_LOCK_REQ_DRIVER0; 1015 else 1016 bit = (1 << pa->pa_function); 1017 break; 1018 case BGE_APE_LOCK_MEM: 1019 /* Lock required when accessing certain APE memory. */ 1020 if (pa->pa_function == 0) 1021 bit = BGE_APE_LOCK_REQ_DRIVER0; 1022 else 1023 bit = (1 << pa->pa_function); 1024 break; 1025 case BGE_APE_LOCK_PHY0: 1026 case BGE_APE_LOCK_PHY1: 1027 case BGE_APE_LOCK_PHY2: 1028 case BGE_APE_LOCK_PHY3: 1029 /* Lock required when accessing PHYs. */ 1030 bit = BGE_APE_LOCK_REQ_DRIVER0; 1031 break; 1032 default: 1033 return (EINVAL); 1034 } 1035 1036 /* Request a lock. */ 1037 APE_WRITE_4_FLUSH(sc, req + off, bit); 1038 1039 /* Wait up to 1 second to acquire lock. */ 1040 for (i = 0; i < 20000; i++) { 1041 status = APE_READ_4(sc, gnt + off); 1042 if (status == bit) 1043 break; 1044 DELAY(50); 1045 } 1046 1047 /* Handle any errors. */ 1048 if (status != bit) { 1049 printf("%s: APE lock %d request failed! " 1050 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1051 device_xname(sc->bge_dev), 1052 locknum, req + off, bit & 0xFFFF, gnt + off, 1053 status & 0xFFFF); 1054 /* Revoke the lock request. */ 1055 APE_WRITE_4(sc, gnt + off, bit); 1056 return (EBUSY); 1057 } 1058 1059 return (0); 1060 } 1061 1062 void 1063 bge_ape_unlock(struct bge_softc *sc, int locknum) 1064 { 1065 struct pci_attach_args *pa = &(sc->bge_pa); 1066 uint32_t bit, gnt; 1067 int off; 1068 1069 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1070 return; 1071 1072 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1073 gnt = BGE_APE_LOCK_GRANT; 1074 else 1075 gnt = BGE_APE_PER_LOCK_GRANT; 1076 1077 off = 4 * locknum; 1078 1079 switch (locknum) { 1080 case BGE_APE_LOCK_GPIO: 1081 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1082 return; 1083 if (pa->pa_function == 0) 1084 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1085 else 1086 bit = (1 << pa->pa_function); 1087 break; 1088 case BGE_APE_LOCK_GRC: 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_MEM: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_PHY0: 1101 case BGE_APE_LOCK_PHY1: 1102 case BGE_APE_LOCK_PHY2: 1103 case BGE_APE_LOCK_PHY3: 1104 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1105 break; 1106 default: 1107 return; 1108 } 1109 1110 /* Write and flush for consecutive bge_ape_lock() */ 1111 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1112 } 1113 1114 /* 1115 * Send an event to the APE firmware. 1116 */ 1117 void 1118 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1119 { 1120 uint32_t apedata; 1121 int i; 1122 1123 /* NCSI does not support APE events. */ 1124 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1125 return; 1126 1127 /* Wait up to 1ms for APE to service previous event. */ 1128 for (i = 10; i > 0; i--) { 1129 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1130 break; 1131 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1132 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1133 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1134 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1135 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1136 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1137 break; 1138 } 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 DELAY(100); 1141 } 1142 if (i == 0) { 1143 printf("%s: APE event 0x%08x send timed out\n", 1144 device_xname(sc->bge_dev), event); 1145 } 1146 } 1147 1148 void 1149 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1150 { 1151 uint32_t apedata, event; 1152 1153 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1154 return; 1155 1156 switch (kind) { 1157 case BGE_RESET_START: 1158 /* If this is the first load, clear the load counter. */ 1159 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1160 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1161 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1162 else { 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1164 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1165 } 1166 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1167 BGE_APE_HOST_SEG_SIG_MAGIC); 1168 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1169 BGE_APE_HOST_SEG_LEN_MAGIC); 1170 1171 /* Add some version info if bge(4) supports it. */ 1172 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1173 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1174 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1175 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1176 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1177 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1178 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1179 BGE_APE_HOST_DRVR_STATE_START); 1180 event = BGE_APE_EVENT_STATUS_STATE_START; 1181 break; 1182 case BGE_RESET_SHUTDOWN: 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1185 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1186 break; 1187 case BGE_RESET_SUSPEND: 1188 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1189 break; 1190 default: 1191 return; 1192 } 1193 1194 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1195 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1196 } 1197 1198 static uint8_t 1199 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1200 { 1201 uint32_t access, byte = 0; 1202 int i; 1203 1204 /* Lock. */ 1205 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1206 for (i = 0; i < 8000; i++) { 1207 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1208 break; 1209 DELAY(20); 1210 } 1211 if (i == 8000) 1212 return 1; 1213 1214 /* Enable access. */ 1215 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1216 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1217 1218 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1219 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1220 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1221 DELAY(10); 1222 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1223 DELAY(10); 1224 break; 1225 } 1226 } 1227 1228 if (i == BGE_TIMEOUT * 10) { 1229 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1230 return 1; 1231 } 1232 1233 /* Get result. */ 1234 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1235 1236 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1237 1238 /* Disable access. */ 1239 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1240 1241 /* Unlock. */ 1242 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1243 1244 return 0; 1245 } 1246 1247 /* 1248 * Read a sequence of bytes from NVRAM. 1249 */ 1250 static int 1251 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1252 { 1253 int error = 0, i; 1254 uint8_t byte = 0; 1255 1256 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1257 return 1; 1258 1259 for (i = 0; i < cnt; i++) { 1260 error = bge_nvram_getbyte(sc, off + i, &byte); 1261 if (error) 1262 break; 1263 *(dest + i) = byte; 1264 } 1265 1266 return (error ? 1 : 0); 1267 } 1268 1269 /* 1270 * Read a byte of data stored in the EEPROM at address 'addr.' The 1271 * BCM570x supports both the traditional bitbang interface and an 1272 * auto access interface for reading the EEPROM. We use the auto 1273 * access method. 1274 */ 1275 static uint8_t 1276 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1277 { 1278 int i; 1279 uint32_t byte = 0; 1280 1281 /* 1282 * Enable use of auto EEPROM access so we can avoid 1283 * having to use the bitbang method. 1284 */ 1285 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1286 1287 /* Reset the EEPROM, load the clock period. */ 1288 CSR_WRITE_4(sc, BGE_EE_ADDR, 1289 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1290 DELAY(20); 1291 1292 /* Issue the read EEPROM command. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1294 1295 /* Wait for completion */ 1296 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1297 DELAY(10); 1298 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1299 break; 1300 } 1301 1302 if (i == BGE_TIMEOUT * 10) { 1303 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1304 return 1; 1305 } 1306 1307 /* Get result. */ 1308 byte = CSR_READ_4(sc, BGE_EE_DATA); 1309 1310 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1311 1312 return 0; 1313 } 1314 1315 /* 1316 * Read a sequence of bytes from the EEPROM. 1317 */ 1318 static int 1319 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1320 { 1321 int error = 0, i; 1322 uint8_t byte = 0; 1323 char *dest = destv; 1324 1325 for (i = 0; i < cnt; i++) { 1326 error = bge_eeprom_getbyte(sc, off + i, &byte); 1327 if (error) 1328 break; 1329 *(dest + i) = byte; 1330 } 1331 1332 return (error ? 1 : 0); 1333 } 1334 1335 static int 1336 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1337 { 1338 struct bge_softc *sc = device_private(dev); 1339 uint32_t data; 1340 uint32_t autopoll; 1341 int rv = 0; 1342 int i; 1343 1344 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1345 return -1; 1346 1347 /* Reading with autopolling on may trigger PCI errors */ 1348 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1349 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1350 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1351 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1352 DELAY(80); 1353 } 1354 1355 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1356 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1357 1358 for (i = 0; i < BGE_TIMEOUT; i++) { 1359 delay(10); 1360 data = CSR_READ_4(sc, BGE_MI_COMM); 1361 if (!(data & BGE_MICOMM_BUSY)) { 1362 DELAY(5); 1363 data = CSR_READ_4(sc, BGE_MI_COMM); 1364 break; 1365 } 1366 } 1367 1368 if (i == BGE_TIMEOUT) { 1369 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1370 rv = ETIMEDOUT; 1371 } else if ((data & BGE_MICOMM_READFAIL) != 0) 1372 rv = -1; 1373 else 1374 *val = data & BGE_MICOMM_DATA; 1375 1376 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1377 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1378 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1379 DELAY(80); 1380 } 1381 1382 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1383 1384 return rv; 1385 } 1386 1387 static int 1388 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1389 { 1390 struct bge_softc *sc = device_private(dev); 1391 uint32_t autopoll; 1392 int i; 1393 1394 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1395 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1396 return 0; 1397 1398 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1399 return -1; 1400 1401 /* Reading with autopolling on may trigger PCI errors */ 1402 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1403 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1404 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1405 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1406 DELAY(80); 1407 } 1408 1409 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1410 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1411 1412 for (i = 0; i < BGE_TIMEOUT; i++) { 1413 delay(10); 1414 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1415 delay(5); 1416 CSR_READ_4(sc, BGE_MI_COMM); 1417 break; 1418 } 1419 } 1420 1421 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1422 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1423 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1424 delay(80); 1425 } 1426 1427 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1428 1429 if (i == BGE_TIMEOUT) { 1430 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1431 return ETIMEDOUT; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static void 1438 bge_miibus_statchg(struct ifnet *ifp) 1439 { 1440 struct bge_softc *sc = ifp->if_softc; 1441 struct mii_data *mii = &sc->bge_mii; 1442 uint32_t mac_mode, rx_mode, tx_mode; 1443 1444 /* 1445 * Get flow control negotiation result. 1446 */ 1447 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1448 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1449 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1450 1451 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1452 mii->mii_media_status & IFM_ACTIVE && 1453 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1454 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1455 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1456 (!(mii->mii_media_status & IFM_ACTIVE) || 1457 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1458 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1459 1460 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1461 return; 1462 1463 /* Set the port mode (MII/GMII) to match the link speed. */ 1464 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1465 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1466 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1467 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1468 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1469 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1470 mac_mode |= BGE_PORTMODE_GMII; 1471 else 1472 mac_mode |= BGE_PORTMODE_MII; 1473 1474 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1475 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1476 if ((mii->mii_media_active & IFM_FDX) != 0) { 1477 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1478 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1479 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1480 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1481 } else 1482 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1483 1484 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1485 DELAY(40); 1486 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1487 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1488 } 1489 1490 /* 1491 * Update rx threshold levels to values in a particular slot 1492 * of the interrupt-mitigation table bge_rx_threshes. 1493 */ 1494 static void 1495 bge_set_thresh(struct ifnet *ifp, int lvl) 1496 { 1497 struct bge_softc *sc = ifp->if_softc; 1498 int s; 1499 1500 /* For now, just save the new Rx-intr thresholds and record 1501 * that a threshold update is pending. Updating the hardware 1502 * registers here (even at splhigh()) is observed to 1503 * occasionaly cause glitches where Rx-interrupts are not 1504 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1505 */ 1506 s = splnet(); 1507 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1508 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1509 sc->bge_pending_rxintr_change = 1; 1510 splx(s); 1511 } 1512 1513 1514 /* 1515 * Update Rx thresholds of all bge devices 1516 */ 1517 static void 1518 bge_update_all_threshes(int lvl) 1519 { 1520 struct ifnet *ifp; 1521 const char * const namebuf = "bge"; 1522 int namelen; 1523 int s; 1524 1525 if (lvl < 0) 1526 lvl = 0; 1527 else if (lvl >= NBGE_RX_THRESH) 1528 lvl = NBGE_RX_THRESH - 1; 1529 1530 namelen = strlen(namebuf); 1531 /* 1532 * Now search all the interfaces for this name/number 1533 */ 1534 s = pserialize_read_enter(); 1535 IFNET_READER_FOREACH(ifp) { 1536 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1537 continue; 1538 /* We got a match: update if doing auto-threshold-tuning */ 1539 if (bge_auto_thresh) 1540 bge_set_thresh(ifp, lvl); 1541 } 1542 pserialize_read_exit(s); 1543 } 1544 1545 /* 1546 * Handle events that have triggered interrupts. 1547 */ 1548 static void 1549 bge_handle_events(struct bge_softc *sc) 1550 { 1551 1552 return; 1553 } 1554 1555 /* 1556 * Memory management for jumbo frames. 1557 */ 1558 1559 static int 1560 bge_alloc_jumbo_mem(struct bge_softc *sc) 1561 { 1562 char *ptr, *kva; 1563 bus_dma_segment_t seg; 1564 int i, rseg, state, error; 1565 struct bge_jpool_entry *entry; 1566 1567 state = error = 0; 1568 1569 /* Grab a big chunk o' storage. */ 1570 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1571 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1572 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1573 return ENOBUFS; 1574 } 1575 1576 state = 1; 1577 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1578 BUS_DMA_NOWAIT)) { 1579 aprint_error_dev(sc->bge_dev, 1580 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1581 error = ENOBUFS; 1582 goto out; 1583 } 1584 1585 state = 2; 1586 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1587 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1588 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1589 error = ENOBUFS; 1590 goto out; 1591 } 1592 1593 state = 3; 1594 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1595 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1596 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1597 error = ENOBUFS; 1598 goto out; 1599 } 1600 1601 state = 4; 1602 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1603 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1604 1605 SLIST_INIT(&sc->bge_jfree_listhead); 1606 SLIST_INIT(&sc->bge_jinuse_listhead); 1607 1608 /* 1609 * Now divide it up into 9K pieces and save the addresses 1610 * in an array. 1611 */ 1612 ptr = sc->bge_cdata.bge_jumbo_buf; 1613 for (i = 0; i < BGE_JSLOTS; i++) { 1614 sc->bge_cdata.bge_jslots[i] = ptr; 1615 ptr += BGE_JLEN; 1616 entry = malloc(sizeof(struct bge_jpool_entry), 1617 M_DEVBUF, M_NOWAIT); 1618 if (entry == NULL) { 1619 aprint_error_dev(sc->bge_dev, 1620 "no memory for jumbo buffer queue!\n"); 1621 error = ENOBUFS; 1622 goto out; 1623 } 1624 entry->slot = i; 1625 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1626 entry, jpool_entries); 1627 } 1628 out: 1629 if (error != 0) { 1630 switch (state) { 1631 case 4: 1632 bus_dmamap_unload(sc->bge_dmatag, 1633 sc->bge_cdata.bge_rx_jumbo_map); 1634 case 3: 1635 bus_dmamap_destroy(sc->bge_dmatag, 1636 sc->bge_cdata.bge_rx_jumbo_map); 1637 case 2: 1638 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1639 case 1: 1640 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1641 break; 1642 default: 1643 break; 1644 } 1645 } 1646 1647 return error; 1648 } 1649 1650 /* 1651 * Allocate a jumbo buffer. 1652 */ 1653 static void * 1654 bge_jalloc(struct bge_softc *sc) 1655 { 1656 struct bge_jpool_entry *entry; 1657 1658 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1659 1660 if (entry == NULL) { 1661 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1662 return NULL; 1663 } 1664 1665 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1666 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1667 return (sc->bge_cdata.bge_jslots[entry->slot]); 1668 } 1669 1670 /* 1671 * Release a jumbo buffer. 1672 */ 1673 static void 1674 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1675 { 1676 struct bge_jpool_entry *entry; 1677 struct bge_softc *sc; 1678 int i, s; 1679 1680 /* Extract the softc struct pointer. */ 1681 sc = (struct bge_softc *)arg; 1682 1683 if (sc == NULL) 1684 panic("bge_jfree: can't find softc pointer!"); 1685 1686 /* calculate the slot this buffer belongs to */ 1687 1688 i = ((char *)buf 1689 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1690 1691 if ((i < 0) || (i >= BGE_JSLOTS)) 1692 panic("bge_jfree: asked to free buffer that we don't manage!"); 1693 1694 s = splvm(); 1695 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1696 if (entry == NULL) 1697 panic("bge_jfree: buffer not in use!"); 1698 entry->slot = i; 1699 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1700 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1701 1702 if (__predict_true(m != NULL)) 1703 pool_cache_put(mb_cache, m); 1704 splx(s); 1705 } 1706 1707 1708 /* 1709 * Initialize a standard receive ring descriptor. 1710 */ 1711 static int 1712 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1713 bus_dmamap_t dmamap) 1714 { 1715 struct mbuf *m_new = NULL; 1716 struct bge_rx_bd *r; 1717 int error; 1718 1719 if (dmamap == NULL) 1720 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1721 1722 if (dmamap == NULL) { 1723 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1724 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1725 if (error != 0) 1726 return error; 1727 } 1728 1729 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1730 1731 if (m == NULL) { 1732 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1733 if (m_new == NULL) 1734 return ENOBUFS; 1735 1736 MCLGET(m_new, M_DONTWAIT); 1737 if (!(m_new->m_flags & M_EXT)) { 1738 m_freem(m_new); 1739 return ENOBUFS; 1740 } 1741 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1742 1743 } else { 1744 m_new = m; 1745 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1746 m_new->m_data = m_new->m_ext.ext_buf; 1747 } 1748 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1749 m_adj(m_new, ETHER_ALIGN); 1750 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1751 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1752 m_freem(m_new); 1753 return ENOBUFS; 1754 } 1755 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1756 BUS_DMASYNC_PREREAD); 1757 1758 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1759 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1760 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1761 r->bge_flags = BGE_RXBDFLAG_END; 1762 r->bge_len = m_new->m_len; 1763 r->bge_idx = i; 1764 1765 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1766 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1767 i * sizeof (struct bge_rx_bd), 1768 sizeof (struct bge_rx_bd), 1769 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1770 1771 return 0; 1772 } 1773 1774 /* 1775 * Initialize a jumbo receive ring descriptor. This allocates 1776 * a jumbo buffer from the pool managed internally by the driver. 1777 */ 1778 static int 1779 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1780 { 1781 struct mbuf *m_new = NULL; 1782 struct bge_rx_bd *r; 1783 void *buf = NULL; 1784 1785 if (m == NULL) { 1786 1787 /* Allocate the mbuf. */ 1788 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1789 if (m_new == NULL) 1790 return ENOBUFS; 1791 1792 /* Allocate the jumbo buffer */ 1793 buf = bge_jalloc(sc); 1794 if (buf == NULL) { 1795 m_freem(m_new); 1796 aprint_error_dev(sc->bge_dev, 1797 "jumbo allocation failed -- packet dropped!\n"); 1798 return ENOBUFS; 1799 } 1800 1801 /* Attach the buffer to the mbuf. */ 1802 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1803 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1804 bge_jfree, sc); 1805 m_new->m_flags |= M_EXT_RW; 1806 } else { 1807 m_new = m; 1808 buf = m_new->m_data = m_new->m_ext.ext_buf; 1809 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1810 } 1811 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1812 m_adj(m_new, ETHER_ALIGN); 1813 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1814 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1815 BUS_DMASYNC_PREREAD); 1816 /* Set up the descriptor. */ 1817 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1818 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1819 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1820 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1821 r->bge_len = m_new->m_len; 1822 r->bge_idx = i; 1823 1824 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1825 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1826 i * sizeof (struct bge_rx_bd), 1827 sizeof (struct bge_rx_bd), 1828 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1829 1830 return 0; 1831 } 1832 1833 /* 1834 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1835 * that's 1MB or memory, which is a lot. For now, we fill only the first 1836 * 256 ring entries and hope that our CPU is fast enough to keep up with 1837 * the NIC. 1838 */ 1839 static int 1840 bge_init_rx_ring_std(struct bge_softc *sc) 1841 { 1842 int i; 1843 1844 if (sc->bge_flags & BGEF_RXRING_VALID) 1845 return 0; 1846 1847 for (i = 0; i < BGE_SSLOTS; i++) { 1848 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1849 return ENOBUFS; 1850 } 1851 1852 sc->bge_std = i - 1; 1853 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1854 1855 sc->bge_flags |= BGEF_RXRING_VALID; 1856 1857 return 0; 1858 } 1859 1860 static void 1861 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1862 { 1863 int i; 1864 1865 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1866 return; 1867 1868 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1869 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1870 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1871 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1872 if (disable) { 1873 bus_dmamap_destroy(sc->bge_dmatag, 1874 sc->bge_cdata.bge_rx_std_map[i]); 1875 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1876 } 1877 } 1878 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1879 sizeof(struct bge_rx_bd)); 1880 } 1881 1882 sc->bge_flags &= ~BGEF_RXRING_VALID; 1883 } 1884 1885 static int 1886 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1887 { 1888 int i; 1889 volatile struct bge_rcb *rcb; 1890 1891 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1892 return 0; 1893 1894 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1895 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1896 return ENOBUFS; 1897 } 1898 1899 sc->bge_jumbo = i - 1; 1900 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1901 1902 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1903 rcb->bge_maxlen_flags = 0; 1904 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1905 1906 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1907 1908 return 0; 1909 } 1910 1911 static void 1912 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1913 { 1914 int i; 1915 1916 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1917 return; 1918 1919 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1920 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1921 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1922 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1923 } 1924 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1925 sizeof(struct bge_rx_bd)); 1926 } 1927 1928 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1929 } 1930 1931 static void 1932 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1933 { 1934 int i; 1935 struct txdmamap_pool_entry *dma; 1936 1937 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1938 return; 1939 1940 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1941 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1942 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1943 sc->bge_cdata.bge_tx_chain[i] = NULL; 1944 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1945 link); 1946 sc->txdma[i] = 0; 1947 } 1948 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1949 sizeof(struct bge_tx_bd)); 1950 } 1951 1952 if (disable) { 1953 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1954 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1955 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1956 if (sc->bge_dma64) { 1957 bus_dmamap_destroy(sc->bge_dmatag32, 1958 dma->dmamap32); 1959 } 1960 free(dma, M_DEVBUF); 1961 } 1962 SLIST_INIT(&sc->txdma_list); 1963 } 1964 1965 sc->bge_flags &= ~BGEF_TXRING_VALID; 1966 } 1967 1968 static int 1969 bge_init_tx_ring(struct bge_softc *sc) 1970 { 1971 struct ifnet *ifp = &sc->ethercom.ec_if; 1972 int i; 1973 bus_dmamap_t dmamap, dmamap32; 1974 bus_size_t maxsegsz; 1975 struct txdmamap_pool_entry *dma; 1976 1977 if (sc->bge_flags & BGEF_TXRING_VALID) 1978 return 0; 1979 1980 sc->bge_txcnt = 0; 1981 sc->bge_tx_saved_considx = 0; 1982 1983 /* Initialize transmit producer index for host-memory send ring. */ 1984 sc->bge_tx_prodidx = 0; 1985 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1986 /* 5700 b2 errata */ 1987 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1988 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1989 1990 /* NIC-memory send ring not used; initialize to zero. */ 1991 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1992 /* 5700 b2 errata */ 1993 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1994 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1995 1996 /* Limit DMA segment size for some chips */ 1997 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1998 (ifp->if_mtu <= ETHERMTU)) 1999 maxsegsz = 2048; 2000 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2001 maxsegsz = 4096; 2002 else 2003 maxsegsz = ETHER_MAX_LEN_JUMBO; 2004 2005 if (SLIST_FIRST(&sc->txdma_list) != NULL) 2006 goto alloc_done; 2007 2008 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2009 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 2010 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2011 &dmamap)) 2012 return ENOBUFS; 2013 if (dmamap == NULL) 2014 panic("dmamap NULL in bge_init_tx_ring"); 2015 if (sc->bge_dma64) { 2016 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 2017 BGE_NTXSEG, maxsegsz, 0, 2018 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2019 &dmamap32)) { 2020 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2021 return ENOBUFS; 2022 } 2023 if (dmamap32 == NULL) 2024 panic("dmamap32 NULL in bge_init_tx_ring"); 2025 } else 2026 dmamap32 = dmamap; 2027 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 2028 if (dma == NULL) { 2029 aprint_error_dev(sc->bge_dev, 2030 "can't alloc txdmamap_pool_entry\n"); 2031 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2032 if (sc->bge_dma64) 2033 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 2034 return ENOMEM; 2035 } 2036 dma->dmamap = dmamap; 2037 dma->dmamap32 = dmamap32; 2038 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2039 } 2040 alloc_done: 2041 sc->bge_flags |= BGEF_TXRING_VALID; 2042 2043 return 0; 2044 } 2045 2046 static void 2047 bge_setmulti(struct bge_softc *sc) 2048 { 2049 struct ethercom *ac = &sc->ethercom; 2050 struct ifnet *ifp = &ac->ec_if; 2051 struct ether_multi *enm; 2052 struct ether_multistep step; 2053 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2054 uint32_t h; 2055 int i; 2056 2057 if (ifp->if_flags & IFF_PROMISC) 2058 goto allmulti; 2059 2060 /* Now program new ones. */ 2061 ETHER_FIRST_MULTI(step, ac, enm); 2062 while (enm != NULL) { 2063 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2064 /* 2065 * We must listen to a range of multicast addresses. 2066 * For now, just accept all multicasts, rather than 2067 * trying to set only those filter bits needed to match 2068 * the range. (At this time, the only use of address 2069 * ranges is for IP multicast routing, for which the 2070 * range is big enough to require all bits set.) 2071 */ 2072 goto allmulti; 2073 } 2074 2075 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2076 2077 /* Just want the 7 least-significant bits. */ 2078 h &= 0x7f; 2079 2080 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2081 ETHER_NEXT_MULTI(step, enm); 2082 } 2083 2084 ifp->if_flags &= ~IFF_ALLMULTI; 2085 goto setit; 2086 2087 allmulti: 2088 ifp->if_flags |= IFF_ALLMULTI; 2089 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2090 2091 setit: 2092 for (i = 0; i < 4; i++) 2093 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2094 } 2095 2096 static void 2097 bge_sig_pre_reset(struct bge_softc *sc, int type) 2098 { 2099 2100 /* 2101 * Some chips don't like this so only do this if ASF is enabled 2102 */ 2103 if (sc->bge_asf_mode) 2104 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2105 2106 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2107 switch (type) { 2108 case BGE_RESET_START: 2109 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2110 BGE_FW_DRV_STATE_START); 2111 break; 2112 case BGE_RESET_SHUTDOWN: 2113 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2114 BGE_FW_DRV_STATE_UNLOAD); 2115 break; 2116 case BGE_RESET_SUSPEND: 2117 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2118 BGE_FW_DRV_STATE_SUSPEND); 2119 break; 2120 } 2121 } 2122 2123 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2124 bge_ape_driver_state_change(sc, type); 2125 } 2126 2127 static void 2128 bge_sig_post_reset(struct bge_softc *sc, int type) 2129 { 2130 2131 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2132 switch (type) { 2133 case BGE_RESET_START: 2134 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2135 BGE_FW_DRV_STATE_START_DONE); 2136 /* START DONE */ 2137 break; 2138 case BGE_RESET_SHUTDOWN: 2139 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2140 BGE_FW_DRV_STATE_UNLOAD_DONE); 2141 break; 2142 } 2143 } 2144 2145 if (type == BGE_RESET_SHUTDOWN) 2146 bge_ape_driver_state_change(sc, type); 2147 } 2148 2149 static void 2150 bge_sig_legacy(struct bge_softc *sc, int type) 2151 { 2152 2153 if (sc->bge_asf_mode) { 2154 switch (type) { 2155 case BGE_RESET_START: 2156 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2157 BGE_FW_DRV_STATE_START); 2158 break; 2159 case BGE_RESET_SHUTDOWN: 2160 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2161 BGE_FW_DRV_STATE_UNLOAD); 2162 break; 2163 } 2164 } 2165 } 2166 2167 static void 2168 bge_wait_for_event_ack(struct bge_softc *sc) 2169 { 2170 int i; 2171 2172 /* wait up to 2500usec */ 2173 for (i = 0; i < 250; i++) { 2174 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2175 BGE_RX_CPU_DRV_EVENT)) 2176 break; 2177 DELAY(10); 2178 } 2179 } 2180 2181 static void 2182 bge_stop_fw(struct bge_softc *sc) 2183 { 2184 2185 if (sc->bge_asf_mode) { 2186 bge_wait_for_event_ack(sc); 2187 2188 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2189 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2190 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2191 2192 bge_wait_for_event_ack(sc); 2193 } 2194 } 2195 2196 static int 2197 bge_poll_fw(struct bge_softc *sc) 2198 { 2199 uint32_t val; 2200 int i; 2201 2202 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2203 for (i = 0; i < BGE_TIMEOUT; i++) { 2204 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2205 if (val & BGE_VCPU_STATUS_INIT_DONE) 2206 break; 2207 DELAY(100); 2208 } 2209 if (i >= BGE_TIMEOUT) { 2210 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2211 return -1; 2212 } 2213 } else { 2214 /* 2215 * Poll the value location we just wrote until 2216 * we see the 1's complement of the magic number. 2217 * This indicates that the firmware initialization 2218 * is complete. 2219 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2220 */ 2221 for (i = 0; i < BGE_TIMEOUT; i++) { 2222 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2223 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2224 break; 2225 DELAY(10); 2226 } 2227 2228 if ((i >= BGE_TIMEOUT) 2229 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2230 aprint_error_dev(sc->bge_dev, 2231 "firmware handshake timed out, val = %x\n", val); 2232 return -1; 2233 } 2234 } 2235 2236 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2237 /* tg3 says we have to wait extra time */ 2238 delay(10 * 1000); 2239 } 2240 2241 return 0; 2242 } 2243 2244 int 2245 bge_phy_addr(struct bge_softc *sc) 2246 { 2247 struct pci_attach_args *pa = &(sc->bge_pa); 2248 int phy_addr = 1; 2249 2250 /* 2251 * PHY address mapping for various devices. 2252 * 2253 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2254 * ---------+-------+-------+-------+-------+ 2255 * BCM57XX | 1 | X | X | X | 2256 * BCM5704 | 1 | X | 1 | X | 2257 * BCM5717 | 1 | 8 | 2 | 9 | 2258 * BCM5719 | 1 | 8 | 2 | 9 | 2259 * BCM5720 | 1 | 8 | 2 | 9 | 2260 * 2261 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2262 * ---------+-------+-------+-------+-------+ 2263 * BCM57XX | X | X | X | X | 2264 * BCM5704 | X | X | X | X | 2265 * BCM5717 | X | X | X | X | 2266 * BCM5719 | 3 | 10 | 4 | 11 | 2267 * BCM5720 | X | X | X | X | 2268 * 2269 * Other addresses may respond but they are not 2270 * IEEE compliant PHYs and should be ignored. 2271 */ 2272 switch (BGE_ASICREV(sc->bge_chipid)) { 2273 case BGE_ASICREV_BCM5717: 2274 case BGE_ASICREV_BCM5719: 2275 case BGE_ASICREV_BCM5720: 2276 phy_addr = pa->pa_function; 2277 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2278 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2279 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2280 } else { 2281 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2282 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2283 } 2284 } 2285 2286 return phy_addr; 2287 } 2288 2289 /* 2290 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2291 * self-test results. 2292 */ 2293 static int 2294 bge_chipinit(struct bge_softc *sc) 2295 { 2296 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2297 int i; 2298 2299 /* Set endianness before we access any non-PCI registers. */ 2300 misc_ctl = BGE_INIT; 2301 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2302 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2303 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2304 misc_ctl); 2305 2306 /* 2307 * Clear the MAC statistics block in the NIC's 2308 * internal memory. 2309 */ 2310 for (i = BGE_STATS_BLOCK; 2311 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2312 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2313 2314 for (i = BGE_STATUS_BLOCK; 2315 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2316 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2317 2318 /* 5717 workaround from tg3 */ 2319 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2320 /* Save */ 2321 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2322 2323 /* Temporary modify MODE_CTL to control TLP */ 2324 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2325 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2326 2327 /* Control TLP */ 2328 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2329 BGE_TLP_PHYCTL1); 2330 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2331 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2332 2333 /* Restore */ 2334 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2335 } 2336 2337 if (BGE_IS_57765_FAMILY(sc)) { 2338 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2339 /* Save */ 2340 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2341 2342 /* Temporary modify MODE_CTL to control TLP */ 2343 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2344 CSR_WRITE_4(sc, BGE_MODE_CTL, 2345 reg | BGE_MODECTL_PCIE_TLPADDR1); 2346 2347 /* Control TLP */ 2348 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2349 BGE_TLP_PHYCTL5); 2350 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2351 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2352 2353 /* Restore */ 2354 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2355 } 2356 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2357 /* 2358 * For the 57766 and non Ax versions of 57765, bootcode 2359 * needs to setup the PCIE Fast Training Sequence (FTS) 2360 * value to prevent transmit hangs. 2361 */ 2362 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2363 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2364 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2365 2366 /* Save */ 2367 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2368 2369 /* Temporary modify MODE_CTL to control TLP */ 2370 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2371 CSR_WRITE_4(sc, BGE_MODE_CTL, 2372 reg | BGE_MODECTL_PCIE_TLPADDR0); 2373 2374 /* Control TLP */ 2375 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2376 BGE_TLP_FTSMAX); 2377 reg &= ~BGE_TLP_FTSMAX_MSK; 2378 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2379 reg | BGE_TLP_FTSMAX_VAL); 2380 2381 /* Restore */ 2382 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2383 } 2384 2385 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2386 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2387 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2388 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2389 } 2390 2391 /* Set up the PCI DMA control register. */ 2392 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2393 if (sc->bge_flags & BGEF_PCIE) { 2394 /* Read watermark not used, 128 bytes for write. */ 2395 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2396 device_xname(sc->bge_dev))); 2397 if (sc->bge_mps >= 256) 2398 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2399 else 2400 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2401 } else if (sc->bge_flags & BGEF_PCIX) { 2402 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2403 device_xname(sc->bge_dev))); 2404 /* PCI-X bus */ 2405 if (BGE_IS_5714_FAMILY(sc)) { 2406 /* 256 bytes for read and write. */ 2407 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2408 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2409 2410 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2411 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2412 else 2413 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2414 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2415 /* 2416 * In the BCM5703, the DMA read watermark should 2417 * be set to less than or equal to the maximum 2418 * memory read byte count of the PCI-X command 2419 * register. 2420 */ 2421 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2422 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2423 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2424 /* 1536 bytes for read, 384 bytes for write. */ 2425 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2426 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2427 } else { 2428 /* 384 bytes for read and write. */ 2429 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2430 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2431 (0x0F); 2432 } 2433 2434 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2435 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2436 uint32_t tmp; 2437 2438 /* Set ONEDMA_ATONCE for hardware workaround. */ 2439 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2440 if (tmp == 6 || tmp == 7) 2441 dma_rw_ctl |= 2442 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2443 2444 /* Set PCI-X DMA write workaround. */ 2445 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2446 } 2447 } else { 2448 /* Conventional PCI bus: 256 bytes for read and write. */ 2449 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2450 device_xname(sc->bge_dev))); 2451 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2452 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2453 2454 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2455 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2456 dma_rw_ctl |= 0x0F; 2457 } 2458 2459 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2460 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2461 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2462 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2463 2464 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2465 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2466 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2467 2468 if (BGE_IS_57765_PLUS(sc)) { 2469 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2470 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2471 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2472 2473 /* 2474 * Enable HW workaround for controllers that misinterpret 2475 * a status tag update and leave interrupts permanently 2476 * disabled. 2477 */ 2478 if (!BGE_IS_57765_FAMILY(sc) && 2479 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2480 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2481 } 2482 2483 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2484 dma_rw_ctl); 2485 2486 /* 2487 * Set up general mode register. 2488 */ 2489 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2490 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2491 /* Retain Host-2-BMC settings written by APE firmware. */ 2492 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2493 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2494 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2495 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2496 } 2497 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2498 BGE_MODECTL_TX_NO_PHDR_CSUM; 2499 2500 /* 2501 * BCM5701 B5 have a bug causing data corruption when using 2502 * 64-bit DMA reads, which can be terminated early and then 2503 * completed later as 32-bit accesses, in combination with 2504 * certain bridges. 2505 */ 2506 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2507 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2508 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2509 2510 /* 2511 * Tell the firmware the driver is running 2512 */ 2513 if (sc->bge_asf_mode & ASF_STACKUP) 2514 mode_ctl |= BGE_MODECTL_STACKUP; 2515 2516 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2517 2518 /* 2519 * Disable memory write invalidate. Apparently it is not supported 2520 * properly by these devices. 2521 */ 2522 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2523 PCI_COMMAND_INVALIDATE_ENABLE); 2524 2525 #ifdef __brokenalpha__ 2526 /* 2527 * Must insure that we do not cross an 8K (bytes) boundary 2528 * for DMA reads. Our highest limit is 1K bytes. This is a 2529 * restriction on some ALPHA platforms with early revision 2530 * 21174 PCI chipsets, such as the AlphaPC 164lx 2531 */ 2532 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2533 #endif 2534 2535 /* Set the timer prescaler (always 66MHz) */ 2536 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2537 2538 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2539 DELAY(40); /* XXX */ 2540 2541 /* Put PHY into ready state */ 2542 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2543 DELAY(40); 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int 2550 bge_blockinit(struct bge_softc *sc) 2551 { 2552 volatile struct bge_rcb *rcb; 2553 bus_size_t rcb_addr; 2554 struct ifnet *ifp = &sc->ethercom.ec_if; 2555 bge_hostaddr taddr; 2556 uint32_t dmactl, mimode, val; 2557 int i, limit; 2558 2559 /* 2560 * Initialize the memory window pointer register so that 2561 * we can access the first 32K of internal NIC RAM. This will 2562 * allow us to set up the TX send ring RCBs and the RX return 2563 * ring RCBs, plus other things which live in NIC memory. 2564 */ 2565 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2566 2567 if (!BGE_IS_5705_PLUS(sc)) { 2568 /* 57XX step 33 */ 2569 /* Configure mbuf memory pool */ 2570 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2571 BGE_BUFFPOOL_1); 2572 2573 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2574 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2575 else 2576 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2577 2578 /* 57XX step 34 */ 2579 /* Configure DMA resource pool */ 2580 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2581 BGE_DMA_DESCRIPTORS); 2582 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2583 } 2584 2585 /* 5718 step 11, 57XX step 35 */ 2586 /* 2587 * Configure mbuf pool watermarks. New broadcom docs strongly 2588 * recommend these. 2589 */ 2590 if (BGE_IS_5717_PLUS(sc)) { 2591 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2592 if (ifp->if_mtu > ETHERMTU) { 2593 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2594 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2595 } else { 2596 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2597 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2598 } 2599 } else if (BGE_IS_5705_PLUS(sc)) { 2600 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2601 2602 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2603 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2604 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2605 } else { 2606 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2607 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2608 } 2609 } else { 2610 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2611 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2612 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2613 } 2614 2615 /* 57XX step 36 */ 2616 /* Configure DMA resource watermarks */ 2617 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2618 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2619 2620 /* 5718 step 13, 57XX step 38 */ 2621 /* Enable buffer manager */ 2622 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2623 /* 2624 * Change the arbitration algorithm of TXMBUF read request to 2625 * round-robin instead of priority based for BCM5719. When 2626 * TXFIFO is almost empty, RDMA will hold its request until 2627 * TXFIFO is not almost empty. 2628 */ 2629 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2630 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2631 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2632 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2633 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2634 val |= BGE_BMANMODE_LOMBUF_ATTN; 2635 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2636 2637 /* 57XX step 39 */ 2638 /* Poll for buffer manager start indication */ 2639 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2640 DELAY(10); 2641 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2642 break; 2643 } 2644 2645 if (i == BGE_TIMEOUT * 2) { 2646 aprint_error_dev(sc->bge_dev, 2647 "buffer manager failed to start\n"); 2648 return ENXIO; 2649 } 2650 2651 /* 57XX step 40 */ 2652 /* Enable flow-through queues */ 2653 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2654 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2655 2656 /* Wait until queue initialization is complete */ 2657 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2658 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2659 break; 2660 DELAY(10); 2661 } 2662 2663 if (i == BGE_TIMEOUT * 2) { 2664 aprint_error_dev(sc->bge_dev, 2665 "flow-through queue init failed\n"); 2666 return ENXIO; 2667 } 2668 2669 /* 2670 * Summary of rings supported by the controller: 2671 * 2672 * Standard Receive Producer Ring 2673 * - This ring is used to feed receive buffers for "standard" 2674 * sized frames (typically 1536 bytes) to the controller. 2675 * 2676 * Jumbo Receive Producer Ring 2677 * - This ring is used to feed receive buffers for jumbo sized 2678 * frames (i.e. anything bigger than the "standard" frames) 2679 * to the controller. 2680 * 2681 * Mini Receive Producer Ring 2682 * - This ring is used to feed receive buffers for "mini" 2683 * sized frames to the controller. 2684 * - This feature required external memory for the controller 2685 * but was never used in a production system. Should always 2686 * be disabled. 2687 * 2688 * Receive Return Ring 2689 * - After the controller has placed an incoming frame into a 2690 * receive buffer that buffer is moved into a receive return 2691 * ring. The driver is then responsible to passing the 2692 * buffer up to the stack. Many versions of the controller 2693 * support multiple RR rings. 2694 * 2695 * Send Ring 2696 * - This ring is used for outgoing frames. Many versions of 2697 * the controller support multiple send rings. 2698 */ 2699 2700 /* 5718 step 15, 57XX step 41 */ 2701 /* Initialize the standard RX ring control block */ 2702 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2703 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2704 /* 5718 step 16 */ 2705 if (BGE_IS_57765_PLUS(sc)) { 2706 /* 2707 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2708 * Bits 15-2 : Maximum RX frame size 2709 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2710 * Bit 0 : Reserved 2711 */ 2712 rcb->bge_maxlen_flags = 2713 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2714 } else if (BGE_IS_5705_PLUS(sc)) { 2715 /* 2716 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2717 * Bits 15-2 : Reserved (should be 0) 2718 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2719 * Bit 0 : Reserved 2720 */ 2721 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2722 } else { 2723 /* 2724 * Ring size is always XXX entries 2725 * Bits 31-16: Maximum RX frame size 2726 * Bits 15-2 : Reserved (should be 0) 2727 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2728 * Bit 0 : Reserved 2729 */ 2730 rcb->bge_maxlen_flags = 2731 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2732 } 2733 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2734 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2735 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2736 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2737 else 2738 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2739 /* Write the standard receive producer ring control block. */ 2740 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2741 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2742 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2743 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2744 2745 /* Reset the standard receive producer ring producer index. */ 2746 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2747 2748 /* 57XX step 42 */ 2749 /* 2750 * Initialize the jumbo RX ring control block 2751 * We set the 'ring disabled' bit in the flags 2752 * field until we're actually ready to start 2753 * using this ring (i.e. once we set the MTU 2754 * high enough to require it). 2755 */ 2756 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2757 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2758 BGE_HOSTADDR(rcb->bge_hostaddr, 2759 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2760 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2761 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2762 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2763 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2764 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2765 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2766 else 2767 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2768 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2769 rcb->bge_hostaddr.bge_addr_hi); 2770 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2771 rcb->bge_hostaddr.bge_addr_lo); 2772 /* Program the jumbo receive producer ring RCB parameters. */ 2773 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2774 rcb->bge_maxlen_flags); 2775 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2776 /* Reset the jumbo receive producer ring producer index. */ 2777 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2778 } 2779 2780 /* 57XX step 43 */ 2781 /* Disable the mini receive producer ring RCB. */ 2782 if (BGE_IS_5700_FAMILY(sc)) { 2783 /* Set up dummy disabled mini ring RCB */ 2784 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2785 rcb->bge_maxlen_flags = 2786 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2787 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2788 rcb->bge_maxlen_flags); 2789 /* Reset the mini receive producer ring producer index. */ 2790 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2791 2792 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2793 offsetof(struct bge_ring_data, bge_info), 2794 sizeof (struct bge_gib), 2795 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2796 } 2797 2798 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2799 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2800 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2801 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2802 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2803 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2804 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2805 } 2806 /* 5718 step 14, 57XX step 44 */ 2807 /* 2808 * The BD ring replenish thresholds control how often the 2809 * hardware fetches new BD's from the producer rings in host 2810 * memory. Setting the value too low on a busy system can 2811 * starve the hardware and recue the throughpout. 2812 * 2813 * Set the BD ring replenish thresholds. The recommended 2814 * values are 1/8th the number of descriptors allocated to 2815 * each ring, but since we try to avoid filling the entire 2816 * ring we set these to the minimal value of 8. This needs to 2817 * be done on several of the supported chip revisions anyway, 2818 * to work around HW bugs. 2819 */ 2820 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2821 if (BGE_IS_JUMBO_CAPABLE(sc)) 2822 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2823 2824 /* 5718 step 18 */ 2825 if (BGE_IS_5717_PLUS(sc)) { 2826 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2827 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2828 } 2829 2830 /* 57XX step 45 */ 2831 /* 2832 * Disable all send rings by setting the 'ring disabled' bit 2833 * in the flags field of all the TX send ring control blocks, 2834 * located in NIC memory. 2835 */ 2836 if (BGE_IS_5700_FAMILY(sc)) { 2837 /* 5700 to 5704 had 16 send rings. */ 2838 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2839 } else if (BGE_IS_5717_PLUS(sc)) { 2840 limit = BGE_TX_RINGS_5717_MAX; 2841 } else if (BGE_IS_57765_FAMILY(sc)) { 2842 limit = BGE_TX_RINGS_57765_MAX; 2843 } else 2844 limit = 1; 2845 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2846 for (i = 0; i < limit; i++) { 2847 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2848 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2849 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2850 rcb_addr += sizeof(struct bge_rcb); 2851 } 2852 2853 /* 57XX step 46 and 47 */ 2854 /* Configure send ring RCB 0 (we use only the first ring) */ 2855 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2856 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2857 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2858 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2859 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2860 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2861 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2862 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2863 else 2864 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2865 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2866 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2867 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2868 2869 /* 57XX step 48 */ 2870 /* 2871 * Disable all receive return rings by setting the 2872 * 'ring diabled' bit in the flags field of all the receive 2873 * return ring control blocks, located in NIC memory. 2874 */ 2875 if (BGE_IS_5717_PLUS(sc)) { 2876 /* Should be 17, use 16 until we get an SRAM map. */ 2877 limit = 16; 2878 } else if (BGE_IS_5700_FAMILY(sc)) 2879 limit = BGE_RX_RINGS_MAX; 2880 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2881 BGE_IS_57765_FAMILY(sc)) 2882 limit = 4; 2883 else 2884 limit = 1; 2885 /* Disable all receive return rings */ 2886 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2887 for (i = 0; i < limit; i++) { 2888 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2889 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2890 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2891 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2892 BGE_RCB_FLAG_RING_DISABLED)); 2893 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2894 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2895 (i * (sizeof(uint64_t))), 0); 2896 rcb_addr += sizeof(struct bge_rcb); 2897 } 2898 2899 /* 57XX step 49 */ 2900 /* 2901 * Set up receive return ring 0. Note that the NIC address 2902 * for RX return rings is 0x0. The return rings live entirely 2903 * within the host, so the nicaddr field in the RCB isn't used. 2904 */ 2905 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2906 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2907 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2908 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2909 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2910 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2911 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2912 2913 /* 5718 step 24, 57XX step 53 */ 2914 /* Set random backoff seed for TX */ 2915 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2916 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2917 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2918 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2919 BGE_TX_BACKOFF_SEED_MASK); 2920 2921 /* 5718 step 26, 57XX step 55 */ 2922 /* Set inter-packet gap */ 2923 val = 0x2620; 2924 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2925 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2926 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2927 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2928 2929 /* 5718 step 27, 57XX step 56 */ 2930 /* 2931 * Specify which ring to use for packets that don't match 2932 * any RX rules. 2933 */ 2934 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2935 2936 /* 5718 step 28, 57XX step 57 */ 2937 /* 2938 * Configure number of RX lists. One interrupt distribution 2939 * list, sixteen active lists, one bad frames class. 2940 */ 2941 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2942 2943 /* 5718 step 29, 57XX step 58 */ 2944 /* Inialize RX list placement stats mask. */ 2945 if (BGE_IS_575X_PLUS(sc)) { 2946 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2947 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2948 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2949 } else 2950 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2951 2952 /* 5718 step 30, 57XX step 59 */ 2953 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2954 2955 /* 5718 step 33, 57XX step 62 */ 2956 /* Disable host coalescing until we get it set up */ 2957 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2958 2959 /* 5718 step 34, 57XX step 63 */ 2960 /* Poll to make sure it's shut down. */ 2961 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2962 DELAY(10); 2963 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2964 break; 2965 } 2966 2967 if (i == BGE_TIMEOUT * 2) { 2968 aprint_error_dev(sc->bge_dev, 2969 "host coalescing engine failed to idle\n"); 2970 return ENXIO; 2971 } 2972 2973 /* 5718 step 35, 36, 37 */ 2974 /* Set up host coalescing defaults */ 2975 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2976 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2977 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2978 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2979 if (!(BGE_IS_5705_PLUS(sc))) { 2980 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2981 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2982 } 2983 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2984 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2985 2986 /* Set up address of statistics block */ 2987 if (BGE_IS_5700_FAMILY(sc)) { 2988 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2989 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2990 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2991 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2992 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2993 } 2994 2995 /* 5718 step 38 */ 2996 /* Set up address of status block */ 2997 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2998 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2999 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 3000 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 3001 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 3002 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 3003 3004 /* Set up status block size. */ 3005 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 3006 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 3007 val = BGE_STATBLKSZ_FULL; 3008 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 3009 } else { 3010 val = BGE_STATBLKSZ_32BYTE; 3011 bzero(&sc->bge_rdata->bge_status_block, 32); 3012 } 3013 3014 /* 5718 step 39, 57XX step 73 */ 3015 /* Turn on host coalescing state machine */ 3016 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 3017 3018 /* 5718 step 40, 57XX step 74 */ 3019 /* Turn on RX BD completion state machine and enable attentions */ 3020 CSR_WRITE_4(sc, BGE_RBDC_MODE, 3021 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 3022 3023 /* 5718 step 41, 57XX step 75 */ 3024 /* Turn on RX list placement state machine */ 3025 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3026 3027 /* 57XX step 76 */ 3028 /* Turn on RX list selector state machine. */ 3029 if (!(BGE_IS_5705_PLUS(sc))) 3030 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3031 3032 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 3033 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 3034 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 3035 BGE_MACMODE_FRMHDR_DMA_ENB; 3036 3037 if (sc->bge_flags & BGEF_FIBER_TBI) 3038 val |= BGE_PORTMODE_TBI; 3039 else if (sc->bge_flags & BGEF_FIBER_MII) 3040 val |= BGE_PORTMODE_GMII; 3041 else 3042 val |= BGE_PORTMODE_MII; 3043 3044 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 3045 /* Allow APE to send/receive frames. */ 3046 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3047 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3048 3049 /* Turn on DMA, clear stats */ 3050 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3051 /* 5718 step 44 */ 3052 DELAY(40); 3053 3054 /* 5718 step 45, 57XX step 79 */ 3055 /* Set misc. local control, enable interrupts on attentions */ 3056 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3057 if (BGE_IS_5717_PLUS(sc)) { 3058 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3059 /* 5718 step 46 */ 3060 DELAY(100); 3061 } 3062 3063 /* 57XX step 81 */ 3064 /* Turn on DMA completion state machine */ 3065 if (!(BGE_IS_5705_PLUS(sc))) 3066 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3067 3068 /* 5718 step 47, 57XX step 82 */ 3069 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3070 3071 /* 5718 step 48 */ 3072 /* Enable host coalescing bug fix. */ 3073 if (BGE_IS_5755_PLUS(sc)) 3074 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3075 3076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3077 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3078 3079 /* Turn on write DMA state machine */ 3080 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3081 /* 5718 step 49 */ 3082 DELAY(40); 3083 3084 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3085 3086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3087 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3088 3089 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3090 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3091 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3092 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3093 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3094 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3095 3096 if (sc->bge_flags & BGEF_PCIE) 3097 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3098 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3099 if (ifp->if_mtu <= ETHERMTU) 3100 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3101 } 3102 if (sc->bge_flags & BGEF_TSO) { 3103 val |= BGE_RDMAMODE_TSO4_ENABLE; 3104 if (BGE_IS_5717_PLUS(sc)) 3105 val |= BGE_RDMAMODE_TSO6_ENABLE; 3106 } 3107 3108 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3109 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3110 BGE_RDMAMODE_H2BNC_VLAN_DET; 3111 /* 3112 * Allow multiple outstanding read requests from 3113 * non-LSO read DMA engine. 3114 */ 3115 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3116 } 3117 3118 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3119 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3120 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3121 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3122 BGE_IS_57765_PLUS(sc)) { 3123 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3124 /* 3125 * Adjust tx margin to prevent TX data corruption and 3126 * fix internal FIFO overflow. 3127 */ 3128 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3129 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3130 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3131 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3132 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3133 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3134 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3135 } 3136 /* 3137 * Enable fix for read DMA FIFO overruns. 3138 * The fix is to limit the number of RX BDs 3139 * the hardware would fetch at a fime. 3140 */ 3141 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3142 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3143 } 3144 3145 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3146 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3147 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3148 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3149 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3150 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3151 /* 3152 * Allow 4KB burst length reads for non-LSO frames. 3153 * Enable 512B burst length reads for buffer descriptors. 3154 */ 3155 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3156 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3157 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3158 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3159 } 3160 /* Turn on read DMA state machine */ 3161 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3162 /* 5718 step 52 */ 3163 delay(40); 3164 3165 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3166 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3167 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 3168 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 3169 if ((val & 0xFFFF) > BGE_FRAMELEN) 3170 break; 3171 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 3172 break; 3173 } 3174 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 3175 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 3176 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 3177 val |= BGE_RDMA_TX_LENGTH_WA_5719; 3178 else 3179 val |= BGE_RDMA_TX_LENGTH_WA_5720; 3180 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 3181 } 3182 } 3183 3184 /* 5718 step 56, 57XX step 84 */ 3185 /* Turn on RX data completion state machine */ 3186 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3187 3188 /* Turn on RX data and RX BD initiator state machine */ 3189 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3190 3191 /* 57XX step 85 */ 3192 /* Turn on Mbuf cluster free state machine */ 3193 if (!BGE_IS_5705_PLUS(sc)) 3194 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3195 3196 /* 5718 step 57, 57XX step 86 */ 3197 /* Turn on send data completion state machine */ 3198 val = BGE_SDCMODE_ENABLE; 3199 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3200 val |= BGE_SDCMODE_CDELAY; 3201 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3202 3203 /* 5718 step 58 */ 3204 /* Turn on send BD completion state machine */ 3205 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3206 3207 /* 57XX step 88 */ 3208 /* Turn on RX BD initiator state machine */ 3209 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3210 3211 /* 5718 step 60, 57XX step 90 */ 3212 /* Turn on send data initiator state machine */ 3213 if (sc->bge_flags & BGEF_TSO) { 3214 /* XXX: magic value from Linux driver */ 3215 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3216 BGE_SDIMODE_HW_LSO_PRE_DMA); 3217 } else 3218 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3219 3220 /* 5718 step 61, 57XX step 91 */ 3221 /* Turn on send BD initiator state machine */ 3222 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3223 3224 /* 5718 step 62, 57XX step 92 */ 3225 /* Turn on send BD selector state machine */ 3226 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3227 3228 /* 5718 step 31, 57XX step 60 */ 3229 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3230 /* 5718 step 32, 57XX step 61 */ 3231 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3232 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3233 3234 /* ack/clear link change events */ 3235 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3236 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3237 BGE_MACSTAT_LINK_CHANGED); 3238 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3239 3240 /* 3241 * Enable attention when the link has changed state for 3242 * devices that use auto polling. 3243 */ 3244 if (sc->bge_flags & BGEF_FIBER_TBI) { 3245 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3246 } else { 3247 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3248 mimode = BGE_MIMODE_500KHZ_CONST; 3249 else 3250 mimode = BGE_MIMODE_BASE; 3251 /* 5718 step 68. 5718 step 69 (optionally). */ 3252 if (BGE_IS_5700_FAMILY(sc) || 3253 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3254 mimode |= BGE_MIMODE_AUTOPOLL; 3255 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3256 } 3257 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3258 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3259 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3260 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3261 BGE_EVTENB_MI_INTERRUPT); 3262 } 3263 3264 /* 3265 * Clear any pending link state attention. 3266 * Otherwise some link state change events may be lost until attention 3267 * is cleared by bge_intr() -> bge_link_upd() sequence. 3268 * It's not necessary on newer BCM chips - perhaps enabling link 3269 * state change attentions implies clearing pending attention. 3270 */ 3271 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3272 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3273 BGE_MACSTAT_LINK_CHANGED); 3274 3275 /* Enable link state change attentions. */ 3276 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3277 3278 return 0; 3279 } 3280 3281 static const struct bge_revision * 3282 bge_lookup_rev(uint32_t chipid) 3283 { 3284 const struct bge_revision *br; 3285 3286 for (br = bge_revisions; br->br_name != NULL; br++) { 3287 if (br->br_chipid == chipid) 3288 return br; 3289 } 3290 3291 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3292 if (br->br_chipid == BGE_ASICREV(chipid)) 3293 return br; 3294 } 3295 3296 return NULL; 3297 } 3298 3299 static const struct bge_product * 3300 bge_lookup(const struct pci_attach_args *pa) 3301 { 3302 const struct bge_product *bp; 3303 3304 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3305 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3306 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3307 return bp; 3308 } 3309 3310 return NULL; 3311 } 3312 3313 static uint32_t 3314 bge_chipid(const struct pci_attach_args *pa) 3315 { 3316 uint32_t id; 3317 3318 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3319 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3320 3321 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3322 switch (PCI_PRODUCT(pa->pa_id)) { 3323 case PCI_PRODUCT_BROADCOM_BCM5717: 3324 case PCI_PRODUCT_BROADCOM_BCM5718: 3325 case PCI_PRODUCT_BROADCOM_BCM5719: 3326 case PCI_PRODUCT_BROADCOM_BCM5720: 3327 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3328 BGE_PCI_GEN2_PRODID_ASICREV); 3329 break; 3330 case PCI_PRODUCT_BROADCOM_BCM57761: 3331 case PCI_PRODUCT_BROADCOM_BCM57762: 3332 case PCI_PRODUCT_BROADCOM_BCM57765: 3333 case PCI_PRODUCT_BROADCOM_BCM57766: 3334 case PCI_PRODUCT_BROADCOM_BCM57781: 3335 case PCI_PRODUCT_BROADCOM_BCM57782: 3336 case PCI_PRODUCT_BROADCOM_BCM57785: 3337 case PCI_PRODUCT_BROADCOM_BCM57786: 3338 case PCI_PRODUCT_BROADCOM_BCM57791: 3339 case PCI_PRODUCT_BROADCOM_BCM57795: 3340 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3341 BGE_PCI_GEN15_PRODID_ASICREV); 3342 break; 3343 default: 3344 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3345 BGE_PCI_PRODID_ASICREV); 3346 break; 3347 } 3348 } 3349 3350 return id; 3351 } 3352 3353 /* 3354 * Return true if MSI can be used with this device. 3355 */ 3356 static int 3357 bge_can_use_msi(struct bge_softc *sc) 3358 { 3359 int can_use_msi = 0; 3360 3361 switch (BGE_ASICREV(sc->bge_chipid)) { 3362 case BGE_ASICREV_BCM5714_A0: 3363 case BGE_ASICREV_BCM5714: 3364 /* 3365 * Apparently, MSI doesn't work when these chips are 3366 * configured in single-port mode. 3367 */ 3368 break; 3369 case BGE_ASICREV_BCM5750: 3370 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3371 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3372 can_use_msi = 1; 3373 break; 3374 default: 3375 if (BGE_IS_575X_PLUS(sc)) 3376 can_use_msi = 1; 3377 } 3378 return (can_use_msi); 3379 } 3380 3381 /* 3382 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3383 * against our list and return its name if we find a match. Note 3384 * that since the Broadcom controller contains VPD support, we 3385 * can get the device name string from the controller itself instead 3386 * of the compiled-in string. This is a little slow, but it guarantees 3387 * we'll always announce the right product name. 3388 */ 3389 static int 3390 bge_probe(device_t parent, cfdata_t match, void *aux) 3391 { 3392 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3393 3394 if (bge_lookup(pa) != NULL) 3395 return 1; 3396 3397 return 0; 3398 } 3399 3400 static void 3401 bge_attach(device_t parent, device_t self, void *aux) 3402 { 3403 struct bge_softc *sc = device_private(self); 3404 struct pci_attach_args *pa = aux; 3405 prop_dictionary_t dict; 3406 const struct bge_product *bp; 3407 const struct bge_revision *br; 3408 pci_chipset_tag_t pc; 3409 const char *intrstr = NULL; 3410 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3411 uint32_t command; 3412 struct ifnet *ifp; 3413 uint32_t misccfg, mimode; 3414 void * kva; 3415 u_char eaddr[ETHER_ADDR_LEN]; 3416 pcireg_t memtype, subid, reg; 3417 bus_addr_t memaddr; 3418 uint32_t pm_ctl; 3419 bool no_seeprom; 3420 int capmask; 3421 int mii_flags; 3422 int map_flags; 3423 char intrbuf[PCI_INTRSTR_LEN]; 3424 3425 bp = bge_lookup(pa); 3426 KASSERT(bp != NULL); 3427 3428 sc->sc_pc = pa->pa_pc; 3429 sc->sc_pcitag = pa->pa_tag; 3430 sc->bge_dev = self; 3431 3432 sc->bge_pa = *pa; 3433 pc = sc->sc_pc; 3434 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3435 3436 aprint_naive(": Ethernet controller\n"); 3437 aprint_normal(": %s\n", bp->bp_name); 3438 3439 /* 3440 * Map control/status registers. 3441 */ 3442 DPRINTFN(5, ("Map control/status regs\n")); 3443 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3444 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3445 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3446 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3447 3448 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3449 aprint_error_dev(sc->bge_dev, 3450 "failed to enable memory mapping!\n"); 3451 return; 3452 } 3453 3454 DPRINTFN(5, ("pci_mem_find\n")); 3455 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3456 switch (memtype) { 3457 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3458 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3459 #if 0 3460 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3461 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3462 &memaddr, &sc->bge_bsize) == 0) 3463 break; 3464 #else 3465 /* 3466 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3467 * system get NMI on boot (PR#48451). This problem might not be 3468 * the driver's bug but our PCI common part's bug. Until we 3469 * find a real reason, we ignore the prefetchable bit. 3470 */ 3471 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3472 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3473 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3474 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3475 map_flags, &sc->bge_bhandle) == 0) { 3476 sc->bge_btag = pa->pa_memt; 3477 break; 3478 } 3479 } 3480 #endif 3481 default: 3482 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3483 return; 3484 } 3485 3486 /* Save various chip information. */ 3487 sc->bge_chipid = bge_chipid(pa); 3488 sc->bge_phy_addr = bge_phy_addr(sc); 3489 3490 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3491 &sc->bge_pciecap, NULL) != 0) { 3492 /* PCIe */ 3493 sc->bge_flags |= BGEF_PCIE; 3494 /* Extract supported maximum payload size. */ 3495 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3496 sc->bge_pciecap + PCIE_DCAP); 3497 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3498 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3499 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3500 sc->bge_expmrq = 2048; 3501 else 3502 sc->bge_expmrq = 4096; 3503 bge_set_max_readrq(sc); 3504 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3505 /* PCIe without PCIe cap */ 3506 sc->bge_flags |= BGEF_PCIE; 3507 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3508 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3509 /* PCI-X */ 3510 sc->bge_flags |= BGEF_PCIX; 3511 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3512 &sc->bge_pcixcap, NULL) == 0) 3513 aprint_error_dev(sc->bge_dev, 3514 "unable to find PCIX capability\n"); 3515 } 3516 3517 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3518 /* 3519 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3520 * can clobber the chip's PCI config-space power control 3521 * registers, leaving the card in D3 powersave state. We do 3522 * not have memory-mapped registers in this state, so force 3523 * device into D0 state before starting initialization. 3524 */ 3525 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3526 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3527 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3528 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3529 DELAY(1000); /* 27 usec is allegedly sufficent */ 3530 } 3531 3532 /* Save chipset family. */ 3533 switch (BGE_ASICREV(sc->bge_chipid)) { 3534 case BGE_ASICREV_BCM5717: 3535 case BGE_ASICREV_BCM5719: 3536 case BGE_ASICREV_BCM5720: 3537 sc->bge_flags |= BGEF_5717_PLUS; 3538 /* FALLTHROUGH */ 3539 case BGE_ASICREV_BCM57765: 3540 case BGE_ASICREV_BCM57766: 3541 if (!BGE_IS_5717_PLUS(sc)) 3542 sc->bge_flags |= BGEF_57765_FAMILY; 3543 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3544 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3545 /* Jumbo frame on BCM5719 A0 does not work. */ 3546 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3547 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3548 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3549 break; 3550 case BGE_ASICREV_BCM5755: 3551 case BGE_ASICREV_BCM5761: 3552 case BGE_ASICREV_BCM5784: 3553 case BGE_ASICREV_BCM5785: 3554 case BGE_ASICREV_BCM5787: 3555 case BGE_ASICREV_BCM57780: 3556 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3557 break; 3558 case BGE_ASICREV_BCM5700: 3559 case BGE_ASICREV_BCM5701: 3560 case BGE_ASICREV_BCM5703: 3561 case BGE_ASICREV_BCM5704: 3562 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3563 break; 3564 case BGE_ASICREV_BCM5714_A0: 3565 case BGE_ASICREV_BCM5780: 3566 case BGE_ASICREV_BCM5714: 3567 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3568 /* FALLTHROUGH */ 3569 case BGE_ASICREV_BCM5750: 3570 case BGE_ASICREV_BCM5752: 3571 case BGE_ASICREV_BCM5906: 3572 sc->bge_flags |= BGEF_575X_PLUS; 3573 /* FALLTHROUGH */ 3574 case BGE_ASICREV_BCM5705: 3575 sc->bge_flags |= BGEF_5705_PLUS; 3576 break; 3577 } 3578 3579 /* Identify chips with APE processor. */ 3580 switch (BGE_ASICREV(sc->bge_chipid)) { 3581 case BGE_ASICREV_BCM5717: 3582 case BGE_ASICREV_BCM5719: 3583 case BGE_ASICREV_BCM5720: 3584 case BGE_ASICREV_BCM5761: 3585 sc->bge_flags |= BGEF_APE; 3586 break; 3587 } 3588 3589 /* 3590 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3591 * not actually a MAC controller bug but an issue with the embedded 3592 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3593 */ 3594 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3595 sc->bge_flags |= BGEF_40BIT_BUG; 3596 3597 /* Chips with APE need BAR2 access for APE registers/memory. */ 3598 if ((sc->bge_flags & BGEF_APE) != 0) { 3599 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3600 #if 0 3601 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3602 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3603 &sc->bge_apesize)) { 3604 aprint_error_dev(sc->bge_dev, 3605 "couldn't map BAR2 memory\n"); 3606 return; 3607 } 3608 #else 3609 /* 3610 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3611 * system get NMI on boot (PR#48451). This problem might not be 3612 * the driver's bug but our PCI common part's bug. Until we 3613 * find a real reason, we ignore the prefetchable bit. 3614 */ 3615 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3616 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3617 aprint_error_dev(sc->bge_dev, 3618 "couldn't map BAR2 memory\n"); 3619 return; 3620 } 3621 3622 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3623 if (bus_space_map(pa->pa_memt, memaddr, 3624 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3625 aprint_error_dev(sc->bge_dev, 3626 "couldn't map BAR2 memory\n"); 3627 return; 3628 } 3629 sc->bge_apetag = pa->pa_memt; 3630 #endif 3631 3632 /* Enable APE register/memory access by host driver. */ 3633 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3634 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3635 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3636 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3637 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3638 3639 bge_ape_lock_init(sc); 3640 bge_ape_read_fw_ver(sc); 3641 } 3642 3643 /* Identify the chips that use an CPMU. */ 3644 if (BGE_IS_5717_PLUS(sc) || 3645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3646 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3647 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3648 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3649 sc->bge_flags |= BGEF_CPMU_PRESENT; 3650 3651 /* Set MI_MODE */ 3652 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3653 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3654 mimode |= BGE_MIMODE_500KHZ_CONST; 3655 else 3656 mimode |= BGE_MIMODE_BASE; 3657 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3658 3659 /* 3660 * When using the BCM5701 in PCI-X mode, data corruption has 3661 * been observed in the first few bytes of some received packets. 3662 * Aligning the packet buffer in memory eliminates the corruption. 3663 * Unfortunately, this misaligns the packet payloads. On platforms 3664 * which do not support unaligned accesses, we will realign the 3665 * payloads by copying the received packets. 3666 */ 3667 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3668 sc->bge_flags & BGEF_PCIX) 3669 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3670 3671 if (BGE_IS_5700_FAMILY(sc)) 3672 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3673 3674 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3675 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3676 3677 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3678 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3679 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3680 sc->bge_flags |= BGEF_IS_5788; 3681 3682 /* 3683 * Some controllers seem to require a special firmware to use 3684 * TSO. But the firmware is not available to FreeBSD and Linux 3685 * claims that the TSO performed by the firmware is slower than 3686 * hardware based TSO. Moreover the firmware based TSO has one 3687 * known bug which can't handle TSO if ethernet header + IP/TCP 3688 * header is greater than 80 bytes. The workaround for the TSO 3689 * bug exist but it seems it's too expensive than not using 3690 * TSO at all. Some hardwares also have the TSO bug so limit 3691 * the TSO to the controllers that are not affected TSO issues 3692 * (e.g. 5755 or higher). 3693 */ 3694 if (BGE_IS_5755_PLUS(sc)) { 3695 /* 3696 * BCM5754 and BCM5787 shares the same ASIC id so 3697 * explicit device id check is required. 3698 */ 3699 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3700 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3701 sc->bge_flags |= BGEF_TSO; 3702 /* TSO on BCM5719 A0 does not work. */ 3703 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3704 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3705 sc->bge_flags &= ~BGEF_TSO; 3706 } 3707 3708 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3709 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3710 (misccfg == 0x4000 || misccfg == 0x8000)) || 3711 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3712 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3713 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3714 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3715 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3716 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3717 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3718 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3719 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3720 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3721 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3722 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3723 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3724 /* These chips are 10/100 only. */ 3725 capmask &= ~BMSR_EXTSTAT; 3726 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3727 } 3728 3729 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3730 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3731 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3732 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3733 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3734 3735 /* Set various PHY bug flags. */ 3736 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3737 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3738 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3739 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3740 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3741 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3742 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3743 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3744 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3745 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3746 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3747 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3748 if (BGE_IS_5705_PLUS(sc) && 3749 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3750 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3751 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3752 !BGE_IS_57765_PLUS(sc)) { 3753 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3754 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3755 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3756 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3757 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3758 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3759 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3760 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3761 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3762 } else 3763 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3764 } 3765 3766 /* 3767 * SEEPROM check. 3768 * First check if firmware knows we do not have SEEPROM. 3769 */ 3770 if (prop_dictionary_get_bool(device_properties(self), 3771 "without-seeprom", &no_seeprom) && no_seeprom) 3772 sc->bge_flags |= BGEF_NO_EEPROM; 3773 3774 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3775 sc->bge_flags |= BGEF_NO_EEPROM; 3776 3777 /* Now check the 'ROM failed' bit on the RX CPU */ 3778 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3779 sc->bge_flags |= BGEF_NO_EEPROM; 3780 3781 sc->bge_asf_mode = 0; 3782 /* No ASF if APE present. */ 3783 if ((sc->bge_flags & BGEF_APE) == 0) { 3784 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3785 BGE_SRAM_DATA_SIG_MAGIC)) { 3786 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3787 BGE_HWCFG_ASF) { 3788 sc->bge_asf_mode |= ASF_ENABLE; 3789 sc->bge_asf_mode |= ASF_STACKUP; 3790 if (BGE_IS_575X_PLUS(sc)) 3791 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3792 } 3793 } 3794 } 3795 3796 int counts[PCI_INTR_TYPE_SIZE] = { 3797 [PCI_INTR_TYPE_INTX] = 1, 3798 [PCI_INTR_TYPE_MSI] = 1, 3799 [PCI_INTR_TYPE_MSIX] = 1, 3800 }; 3801 int max_type = PCI_INTR_TYPE_MSIX; 3802 3803 if (!bge_can_use_msi(sc)) { 3804 /* MSI broken, allow only INTx */ 3805 max_type = PCI_INTR_TYPE_INTX; 3806 } 3807 3808 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3809 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3810 return; 3811 } 3812 3813 DPRINTFN(5, ("pci_intr_string\n")); 3814 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3815 sizeof(intrbuf)); 3816 DPRINTFN(5, ("pci_intr_establish\n")); 3817 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3818 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3819 if (sc->bge_intrhand == NULL) { 3820 pci_intr_release(pc, sc->bge_pihp, 1); 3821 sc->bge_pihp = NULL; 3822 3823 aprint_error_dev(self, "couldn't establish interrupt"); 3824 if (intrstr != NULL) 3825 aprint_error(" at %s", intrstr); 3826 aprint_error("\n"); 3827 return; 3828 } 3829 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3830 3831 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3832 case PCI_INTR_TYPE_MSIX: 3833 case PCI_INTR_TYPE_MSI: 3834 KASSERT(bge_can_use_msi(sc)); 3835 sc->bge_flags |= BGEF_MSI; 3836 break; 3837 default: 3838 /* nothing to do */ 3839 break; 3840 } 3841 3842 /* 3843 * All controllers except BCM5700 supports tagged status but 3844 * we use tagged status only for MSI case on BCM5717. Otherwise 3845 * MSI on BCM5717 does not work. 3846 */ 3847 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3848 sc->bge_flags |= BGEF_TAGGED_STATUS; 3849 3850 /* 3851 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3852 * lock in bge_reset(). 3853 */ 3854 CSR_WRITE_4(sc, BGE_EE_ADDR, 3855 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3856 delay(1000); 3857 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3858 3859 bge_stop_fw(sc); 3860 bge_sig_pre_reset(sc, BGE_RESET_START); 3861 if (bge_reset(sc)) 3862 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3863 3864 /* 3865 * Read the hardware config word in the first 32k of NIC internal 3866 * memory, or fall back to the config word in the EEPROM. 3867 * Note: on some BCM5700 cards, this value appears to be unset. 3868 */ 3869 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3870 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3871 BGE_SRAM_DATA_SIG_MAGIC) { 3872 uint32_t tmp; 3873 3874 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3875 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3876 BGE_SRAM_DATA_VER_SHIFT; 3877 if ((0 < tmp) && (tmp < 0x100)) 3878 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3879 if (sc->bge_flags & BGEF_PCIE) 3880 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3881 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3882 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3883 if (BGE_IS_5717_PLUS(sc)) 3884 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3885 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3886 bge_read_eeprom(sc, (void *)&hwcfg, 3887 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3888 hwcfg = be32toh(hwcfg); 3889 } 3890 aprint_normal_dev(sc->bge_dev, 3891 "HW config %08x, %08x, %08x, %08x %08x\n", 3892 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3893 3894 bge_sig_legacy(sc, BGE_RESET_START); 3895 bge_sig_post_reset(sc, BGE_RESET_START); 3896 3897 if (bge_chipinit(sc)) { 3898 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3899 bge_release_resources(sc); 3900 return; 3901 } 3902 3903 /* 3904 * Get station address from the EEPROM. 3905 */ 3906 if (bge_get_eaddr(sc, eaddr)) { 3907 aprint_error_dev(sc->bge_dev, 3908 "failed to read station address\n"); 3909 bge_release_resources(sc); 3910 return; 3911 } 3912 3913 br = bge_lookup_rev(sc->bge_chipid); 3914 3915 if (br == NULL) { 3916 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3917 sc->bge_chipid); 3918 } else { 3919 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3920 br->br_name, sc->bge_chipid); 3921 } 3922 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3923 3924 /* Allocate the general information block and ring buffers. */ 3925 if (pci_dma64_available(pa)) { 3926 sc->bge_dmatag = pa->pa_dmat64; 3927 sc->bge_dmatag32 = pa->pa_dmat; 3928 sc->bge_dma64 = true; 3929 } else { 3930 sc->bge_dmatag = pa->pa_dmat; 3931 sc->bge_dmatag32 = pa->pa_dmat; 3932 sc->bge_dma64 = false; 3933 } 3934 3935 /* 40bit DMA workaround */ 3936 if (sizeof(bus_addr_t) > 4) { 3937 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3938 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3939 3940 if (bus_dmatag_subregion(olddmatag, 0, 3941 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3942 BUS_DMA_NOWAIT) != 0) { 3943 aprint_error_dev(self, 3944 "WARNING: failed to restrict dma range," 3945 " falling back to parent bus dma range\n"); 3946 sc->bge_dmatag = olddmatag; 3947 } 3948 } 3949 } 3950 SLIST_INIT(&sc->txdma_list); 3951 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3952 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3953 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3954 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3955 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3956 return; 3957 } 3958 DPRINTFN(5, ("bus_dmamem_map\n")); 3959 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3960 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3961 BUS_DMA_NOWAIT)) { 3962 aprint_error_dev(sc->bge_dev, 3963 "can't map DMA buffers (%zu bytes)\n", 3964 sizeof(struct bge_ring_data)); 3965 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3966 sc->bge_ring_rseg); 3967 return; 3968 } 3969 DPRINTFN(5, ("bus_dmamem_create\n")); 3970 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3971 sizeof(struct bge_ring_data), 0, 3972 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3973 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3974 bus_dmamem_unmap(sc->bge_dmatag, kva, 3975 sizeof(struct bge_ring_data)); 3976 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3977 sc->bge_ring_rseg); 3978 return; 3979 } 3980 DPRINTFN(5, ("bus_dmamem_load\n")); 3981 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3982 sizeof(struct bge_ring_data), NULL, 3983 BUS_DMA_NOWAIT)) { 3984 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3985 bus_dmamem_unmap(sc->bge_dmatag, kva, 3986 sizeof(struct bge_ring_data)); 3987 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3988 sc->bge_ring_rseg); 3989 return; 3990 } 3991 3992 DPRINTFN(5, ("bzero\n")); 3993 sc->bge_rdata = (struct bge_ring_data *)kva; 3994 3995 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3996 3997 /* Try to allocate memory for jumbo buffers. */ 3998 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3999 if (bge_alloc_jumbo_mem(sc)) { 4000 aprint_error_dev(sc->bge_dev, 4001 "jumbo buffer allocation failed\n"); 4002 } else 4003 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 4004 } 4005 4006 /* Set default tuneable values. */ 4007 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 4008 sc->bge_rx_coal_ticks = 150; 4009 sc->bge_rx_max_coal_bds = 64; 4010 sc->bge_tx_coal_ticks = 300; 4011 sc->bge_tx_max_coal_bds = 400; 4012 if (BGE_IS_5705_PLUS(sc)) { 4013 sc->bge_tx_coal_ticks = (12 * 5); 4014 sc->bge_tx_max_coal_bds = (12 * 5); 4015 aprint_verbose_dev(sc->bge_dev, 4016 "setting short Tx thresholds\n"); 4017 } 4018 4019 if (BGE_IS_5717_PLUS(sc)) 4020 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 4021 else if (BGE_IS_5705_PLUS(sc)) 4022 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 4023 else 4024 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 4025 4026 /* Set up ifnet structure */ 4027 ifp = &sc->ethercom.ec_if; 4028 ifp->if_softc = sc; 4029 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 4030 ifp->if_ioctl = bge_ioctl; 4031 ifp->if_stop = bge_stop; 4032 ifp->if_start = bge_start; 4033 ifp->if_init = bge_init; 4034 ifp->if_watchdog = bge_watchdog; 4035 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 4036 IFQ_SET_READY(&ifp->if_snd); 4037 DPRINTFN(5, ("strcpy if_xname\n")); 4038 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 4039 4040 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 4041 sc->ethercom.ec_if.if_capabilities |= 4042 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 4043 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 4044 sc->ethercom.ec_if.if_capabilities |= 4045 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 4046 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 4047 #endif 4048 sc->ethercom.ec_capabilities |= 4049 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 4050 4051 if (sc->bge_flags & BGEF_TSO) 4052 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 4053 4054 /* 4055 * Do MII setup. 4056 */ 4057 DPRINTFN(5, ("mii setup\n")); 4058 sc->bge_mii.mii_ifp = ifp; 4059 sc->bge_mii.mii_readreg = bge_miibus_readreg; 4060 sc->bge_mii.mii_writereg = bge_miibus_writereg; 4061 sc->bge_mii.mii_statchg = bge_miibus_statchg; 4062 4063 /* 4064 * Figure out what sort of media we have by checking the hardware 4065 * config word. Note: on some BCM5700 cards, this value appears to be 4066 * unset. If that's the case, we have to rely on identifying the NIC 4067 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 4068 * The SysKonnect SK-9D41 is a 1000baseSX card. 4069 */ 4070 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 4071 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 4072 if (BGE_IS_5705_PLUS(sc)) { 4073 sc->bge_flags |= BGEF_FIBER_MII; 4074 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 4075 } else 4076 sc->bge_flags |= BGEF_FIBER_TBI; 4077 } 4078 4079 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 4080 if (BGE_IS_JUMBO_CAPABLE(sc)) 4081 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 4082 4083 /* set phyflags and chipid before mii_attach() */ 4084 dict = device_properties(self); 4085 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 4086 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 4087 4088 if (sc->bge_flags & BGEF_FIBER_TBI) { 4089 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 4090 bge_ifmedia_sts); 4091 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 4092 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 4093 0, NULL); 4094 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 4095 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 4096 /* Pretend the user requested this setting */ 4097 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 4098 } else { 4099 /* 4100 * Do transceiver setup and tell the firmware the 4101 * driver is down so we can try to get access the 4102 * probe if ASF is running. Retry a couple of times 4103 * if we get a conflict with the ASF firmware accessing 4104 * the PHY. 4105 */ 4106 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4107 bge_asf_driver_up(sc); 4108 4109 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 4110 bge_ifmedia_sts); 4111 mii_flags = MIIF_DOPAUSE; 4112 if (sc->bge_flags & BGEF_FIBER_MII) 4113 mii_flags |= MIIF_HAVEFIBER; 4114 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 4115 MII_OFFSET_ANY, mii_flags); 4116 4117 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 4118 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4119 ifmedia_add(&sc->bge_mii.mii_media, 4120 IFM_ETHER|IFM_MANUAL, 0, NULL); 4121 ifmedia_set(&sc->bge_mii.mii_media, 4122 IFM_ETHER|IFM_MANUAL); 4123 } else 4124 ifmedia_set(&sc->bge_mii.mii_media, 4125 IFM_ETHER|IFM_AUTO); 4126 4127 /* 4128 * Now tell the firmware we are going up after probing the PHY 4129 */ 4130 if (sc->bge_asf_mode & ASF_STACKUP) 4131 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4132 } 4133 4134 /* 4135 * Call MI attach routine. 4136 */ 4137 DPRINTFN(5, ("if_attach\n")); 4138 if_attach(ifp); 4139 if_deferred_start_init(ifp, NULL); 4140 DPRINTFN(5, ("ether_ifattach\n")); 4141 ether_ifattach(ifp, eaddr); 4142 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4143 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4144 RND_TYPE_NET, RND_FLAG_DEFAULT); 4145 #ifdef BGE_EVENT_COUNTERS 4146 /* 4147 * Attach event counters. 4148 */ 4149 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4150 NULL, device_xname(sc->bge_dev), "intr"); 4151 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4152 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4153 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4154 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4155 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4156 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4157 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4158 NULL, device_xname(sc->bge_dev), "tx_xon"); 4159 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4160 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4161 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4162 NULL, device_xname(sc->bge_dev), "rx_xon"); 4163 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4164 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4165 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4166 NULL, device_xname(sc->bge_dev), "xoffentered"); 4167 #endif /* BGE_EVENT_COUNTERS */ 4168 DPRINTFN(5, ("callout_init\n")); 4169 callout_init(&sc->bge_timeout, 0); 4170 4171 if (pmf_device_register(self, NULL, NULL)) 4172 pmf_class_network_register(self, ifp); 4173 else 4174 aprint_error_dev(self, "couldn't establish power handler\n"); 4175 4176 bge_sysctl_init(sc); 4177 4178 #ifdef BGE_DEBUG 4179 bge_debug_info(sc); 4180 #endif 4181 } 4182 4183 /* 4184 * Stop all chip I/O so that the kernel's probe routines don't 4185 * get confused by errant DMAs when rebooting. 4186 */ 4187 static int 4188 bge_detach(device_t self, int flags __unused) 4189 { 4190 struct bge_softc *sc = device_private(self); 4191 struct ifnet *ifp = &sc->ethercom.ec_if; 4192 int s; 4193 4194 s = splnet(); 4195 /* Stop the interface. Callouts are stopped in it. */ 4196 bge_stop(ifp, 1); 4197 splx(s); 4198 4199 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4200 4201 /* Delete all remaining media. */ 4202 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4203 4204 ether_ifdetach(ifp); 4205 if_detach(ifp); 4206 4207 bge_release_resources(sc); 4208 4209 return 0; 4210 } 4211 4212 static void 4213 bge_release_resources(struct bge_softc *sc) 4214 { 4215 4216 /* Detach sysctl */ 4217 if (sc->bge_log != NULL) 4218 sysctl_teardown(&sc->bge_log); 4219 4220 #ifdef BGE_EVENT_COUNTERS 4221 /* Detach event counters. */ 4222 evcnt_detach(&sc->bge_ev_intr); 4223 evcnt_detach(&sc->bge_ev_intr_spurious); 4224 evcnt_detach(&sc->bge_ev_intr_spurious2); 4225 evcnt_detach(&sc->bge_ev_tx_xoff); 4226 evcnt_detach(&sc->bge_ev_tx_xon); 4227 evcnt_detach(&sc->bge_ev_rx_xoff); 4228 evcnt_detach(&sc->bge_ev_rx_xon); 4229 evcnt_detach(&sc->bge_ev_rx_macctl); 4230 evcnt_detach(&sc->bge_ev_xoffentered); 4231 #endif /* BGE_EVENT_COUNTERS */ 4232 4233 /* Disestablish the interrupt handler */ 4234 if (sc->bge_intrhand != NULL) { 4235 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4236 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4237 sc->bge_intrhand = NULL; 4238 } 4239 4240 if (sc->bge_dmatag != NULL) { 4241 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4242 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4243 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4244 sizeof(struct bge_ring_data)); 4245 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4246 sc->bge_ring_rseg); 4247 } 4248 4249 /* Unmap the device registers */ 4250 if (sc->bge_bsize != 0) { 4251 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4252 sc->bge_bsize = 0; 4253 } 4254 4255 /* Unmap the APE registers */ 4256 if (sc->bge_apesize != 0) { 4257 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4258 sc->bge_apesize); 4259 sc->bge_apesize = 0; 4260 } 4261 } 4262 4263 static int 4264 bge_reset(struct bge_softc *sc) 4265 { 4266 uint32_t cachesize, command; 4267 uint32_t reset, mac_mode, mac_mode_mask; 4268 pcireg_t devctl, reg; 4269 int i, val; 4270 void (*write_op)(struct bge_softc *, int, int); 4271 4272 /* Make mask for BGE_MAC_MODE register. */ 4273 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4274 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4275 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4276 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4277 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4278 4279 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4280 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4281 if (sc->bge_flags & BGEF_PCIE) 4282 write_op = bge_writemem_direct; 4283 else 4284 write_op = bge_writemem_ind; 4285 } else 4286 write_op = bge_writereg_ind; 4287 4288 /* 57XX step 4 */ 4289 /* Acquire the NVM lock */ 4290 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4291 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4292 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4293 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4294 for (i = 0; i < 8000; i++) { 4295 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4296 BGE_NVRAMSWARB_GNT1) 4297 break; 4298 DELAY(20); 4299 } 4300 if (i == 8000) { 4301 printf("%s: NVRAM lock timedout!\n", 4302 device_xname(sc->bge_dev)); 4303 } 4304 } 4305 4306 /* Take APE lock when performing reset. */ 4307 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4308 4309 /* 57XX step 3 */ 4310 /* Save some important PCI state. */ 4311 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4312 /* 5718 reset step 3 */ 4313 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4314 4315 /* 5718 reset step 5, 57XX step 5b-5d */ 4316 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4317 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4318 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4319 4320 /* XXX ???: Disable fastboot on controllers that support it. */ 4321 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4322 BGE_IS_5755_PLUS(sc)) 4323 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4324 4325 /* 5718 reset step 2, 57XX step 6 */ 4326 /* 4327 * Write the magic number to SRAM at offset 0xB50. 4328 * When firmware finishes its initialization it will 4329 * write ~BGE_MAGIC_NUMBER to the same location. 4330 */ 4331 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4332 4333 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4334 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4335 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4336 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4337 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4338 } 4339 4340 /* 5718 reset step 6, 57XX step 7 */ 4341 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4342 /* 4343 * XXX: from FreeBSD/Linux; no documentation 4344 */ 4345 if (sc->bge_flags & BGEF_PCIE) { 4346 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4347 !BGE_IS_57765_PLUS(sc) && 4348 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4349 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4350 /* PCI Express 1.0 system */ 4351 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4352 BGE_PHY_PCIE_SCRAM_MODE); 4353 } 4354 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4355 /* 4356 * Prevent PCI Express link training 4357 * during global reset. 4358 */ 4359 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4360 reset |= (1 << 29); 4361 } 4362 } 4363 4364 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4365 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4366 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4367 i | BGE_VCPU_STATUS_DRV_RESET); 4368 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4369 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4370 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4371 } 4372 4373 /* 4374 * Set GPHY Power Down Override to leave GPHY 4375 * powered up in D0 uninitialized. 4376 */ 4377 if (BGE_IS_5705_PLUS(sc) && 4378 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4379 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4380 4381 /* Issue global reset */ 4382 write_op(sc, BGE_MISC_CFG, reset); 4383 4384 /* 5718 reset step 7, 57XX step 8 */ 4385 if (sc->bge_flags & BGEF_PCIE) 4386 delay(100*1000); /* too big */ 4387 else 4388 delay(1000); 4389 4390 if (sc->bge_flags & BGEF_PCIE) { 4391 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4392 DELAY(500000); 4393 /* XXX: Magic Numbers */ 4394 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4395 BGE_PCI_UNKNOWN0); 4396 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4397 BGE_PCI_UNKNOWN0, 4398 reg | (1 << 15)); 4399 } 4400 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4401 sc->bge_pciecap + PCIE_DCSR); 4402 /* Clear enable no snoop and disable relaxed ordering. */ 4403 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4404 PCIE_DCSR_ENA_NO_SNOOP); 4405 4406 /* Set PCIE max payload size to 128 for older PCIe devices */ 4407 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4408 devctl &= ~(0x00e0); 4409 /* Clear device status register. Write 1b to clear */ 4410 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4411 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4412 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4413 sc->bge_pciecap + PCIE_DCSR, devctl); 4414 bge_set_max_readrq(sc); 4415 } 4416 4417 /* From Linux: dummy read to flush PCI posted writes */ 4418 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4419 4420 /* 4421 * Reset some of the PCI state that got zapped by reset 4422 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4423 * set, too. 4424 */ 4425 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4426 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4427 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4428 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4429 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4430 (sc->bge_flags & BGEF_PCIX) != 0) 4431 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4432 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4433 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4434 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4435 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4436 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4437 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4438 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4439 4440 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4441 if (sc->bge_flags & BGEF_PCIX) { 4442 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4443 + PCIX_CMD); 4444 /* Set max memory read byte count to 2K */ 4445 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4446 reg &= ~PCIX_CMD_BYTECNT_MASK; 4447 reg |= PCIX_CMD_BCNT_2048; 4448 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4449 /* 4450 * For 5704, set max outstanding split transaction 4451 * field to 0 (0 means it supports 1 request) 4452 */ 4453 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4454 | PCIX_CMD_BYTECNT_MASK); 4455 reg |= PCIX_CMD_BCNT_2048; 4456 } 4457 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4458 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4459 } 4460 4461 /* 5718 reset step 10, 57XX step 12 */ 4462 /* Enable memory arbiter. */ 4463 if (BGE_IS_5714_FAMILY(sc)) { 4464 val = CSR_READ_4(sc, BGE_MARB_MODE); 4465 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4466 } else 4467 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4468 4469 /* XXX 5721, 5751 and 5752 */ 4470 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4471 /* Step 19: */ 4472 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4473 /* Step 20: */ 4474 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4475 } 4476 4477 /* 5718 reset step 12, 57XX step 15 and 16 */ 4478 /* Fix up byte swapping */ 4479 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4480 4481 /* 5718 reset step 13, 57XX step 17 */ 4482 /* Poll until the firmware initialization is complete */ 4483 bge_poll_fw(sc); 4484 4485 /* 57XX step 21 */ 4486 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4487 pcireg_t msidata; 4488 4489 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4490 BGE_PCI_MSI_DATA); 4491 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4492 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4493 msidata); 4494 } 4495 4496 /* 57XX step 18 */ 4497 /* Write mac mode. */ 4498 val = CSR_READ_4(sc, BGE_MAC_MODE); 4499 /* Restore mac_mode_mask's bits using mac_mode */ 4500 val = (val & ~mac_mode_mask) | mac_mode; 4501 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4502 DELAY(40); 4503 4504 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4505 4506 /* 4507 * The 5704 in TBI mode apparently needs some special 4508 * adjustment to insure the SERDES drive level is set 4509 * to 1.2V. 4510 */ 4511 if (sc->bge_flags & BGEF_FIBER_TBI && 4512 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4513 uint32_t serdescfg; 4514 4515 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4516 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4517 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4518 } 4519 4520 if (sc->bge_flags & BGEF_PCIE && 4521 !BGE_IS_57765_PLUS(sc) && 4522 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4523 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4524 uint32_t v; 4525 4526 /* Enable PCI Express bug fix */ 4527 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4528 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4529 v | BGE_TLP_DATA_FIFO_PROTECT); 4530 } 4531 4532 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4533 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4534 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4535 4536 return 0; 4537 } 4538 4539 /* 4540 * Frame reception handling. This is called if there's a frame 4541 * on the receive return list. 4542 * 4543 * Note: we have to be able to handle two possibilities here: 4544 * 1) the frame is from the jumbo receive ring 4545 * 2) the frame is from the standard receive ring 4546 */ 4547 4548 static void 4549 bge_rxeof(struct bge_softc *sc) 4550 { 4551 struct ifnet *ifp; 4552 uint16_t rx_prod, rx_cons; 4553 int stdcnt = 0, jumbocnt = 0; 4554 bus_dmamap_t dmamap; 4555 bus_addr_t offset, toff; 4556 bus_size_t tlen; 4557 int tosync; 4558 4559 rx_cons = sc->bge_rx_saved_considx; 4560 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4561 4562 /* Nothing to do */ 4563 if (rx_cons == rx_prod) 4564 return; 4565 4566 ifp = &sc->ethercom.ec_if; 4567 4568 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4569 offsetof(struct bge_ring_data, bge_status_block), 4570 sizeof (struct bge_status_block), 4571 BUS_DMASYNC_POSTREAD); 4572 4573 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4574 tosync = rx_prod - rx_cons; 4575 4576 if (tosync != 0) 4577 rnd_add_uint32(&sc->rnd_source, tosync); 4578 4579 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4580 4581 if (tosync < 0) { 4582 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4583 sizeof (struct bge_rx_bd); 4584 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4585 toff, tlen, BUS_DMASYNC_POSTREAD); 4586 tosync = -tosync; 4587 } 4588 4589 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4590 offset, tosync * sizeof (struct bge_rx_bd), 4591 BUS_DMASYNC_POSTREAD); 4592 4593 while (rx_cons != rx_prod) { 4594 struct bge_rx_bd *cur_rx; 4595 uint32_t rxidx; 4596 struct mbuf *m = NULL; 4597 4598 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4599 4600 rxidx = cur_rx->bge_idx; 4601 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4602 4603 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4604 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4605 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4606 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4607 jumbocnt++; 4608 bus_dmamap_sync(sc->bge_dmatag, 4609 sc->bge_cdata.bge_rx_jumbo_map, 4610 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4611 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4612 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4613 ifp->if_ierrors++; 4614 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4615 continue; 4616 } 4617 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4618 NULL)== ENOBUFS) { 4619 ifp->if_ierrors++; 4620 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4621 continue; 4622 } 4623 } else { 4624 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4625 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4626 4627 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4628 stdcnt++; 4629 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4630 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4631 if (dmamap == NULL) { 4632 ifp->if_ierrors++; 4633 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4634 continue; 4635 } 4636 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4637 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4638 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4639 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4640 ifp->if_ierrors++; 4641 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4642 continue; 4643 } 4644 if (bge_newbuf_std(sc, sc->bge_std, 4645 NULL, dmamap) == ENOBUFS) { 4646 ifp->if_ierrors++; 4647 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4648 continue; 4649 } 4650 } 4651 4652 #ifndef __NO_STRICT_ALIGNMENT 4653 /* 4654 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4655 * the Rx buffer has the layer-2 header unaligned. 4656 * If our CPU requires alignment, re-align by copying. 4657 */ 4658 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4659 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4660 cur_rx->bge_len); 4661 m->m_data += ETHER_ALIGN; 4662 } 4663 #endif 4664 4665 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4666 m_set_rcvif(m, ifp); 4667 4668 bge_rxcsum(sc, cur_rx, m); 4669 4670 /* 4671 * If we received a packet with a vlan tag, pass it 4672 * to vlan_input() instead of ether_input(). 4673 */ 4674 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4675 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4676 } 4677 4678 if_percpuq_enqueue(ifp->if_percpuq, m); 4679 } 4680 4681 sc->bge_rx_saved_considx = rx_cons; 4682 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4683 if (stdcnt) 4684 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4685 if (jumbocnt) 4686 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4687 } 4688 4689 static void 4690 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4691 { 4692 4693 if (BGE_IS_57765_PLUS(sc)) { 4694 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4695 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4696 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4697 if ((cur_rx->bge_error_flag & 4698 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4699 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4700 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4701 m->m_pkthdr.csum_data = 4702 cur_rx->bge_tcp_udp_csum; 4703 m->m_pkthdr.csum_flags |= 4704 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4705 M_CSUM_DATA); 4706 } 4707 } 4708 } else { 4709 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4710 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4711 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4712 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4713 /* 4714 * Rx transport checksum-offload may also 4715 * have bugs with packets which, when transmitted, 4716 * were `runts' requiring padding. 4717 */ 4718 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4719 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4720 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4721 m->m_pkthdr.csum_data = 4722 cur_rx->bge_tcp_udp_csum; 4723 m->m_pkthdr.csum_flags |= 4724 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4725 M_CSUM_DATA); 4726 } 4727 } 4728 } 4729 4730 static void 4731 bge_txeof(struct bge_softc *sc) 4732 { 4733 struct bge_tx_bd *cur_tx = NULL; 4734 struct ifnet *ifp; 4735 struct txdmamap_pool_entry *dma; 4736 bus_addr_t offset, toff; 4737 bus_size_t tlen; 4738 int tosync; 4739 struct mbuf *m; 4740 4741 ifp = &sc->ethercom.ec_if; 4742 4743 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4744 offsetof(struct bge_ring_data, bge_status_block), 4745 sizeof (struct bge_status_block), 4746 BUS_DMASYNC_POSTREAD); 4747 4748 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4749 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4750 sc->bge_tx_saved_considx; 4751 4752 if (tosync != 0) 4753 rnd_add_uint32(&sc->rnd_source, tosync); 4754 4755 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4756 4757 if (tosync < 0) { 4758 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4759 sizeof (struct bge_tx_bd); 4760 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4761 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4762 tosync = -tosync; 4763 } 4764 4765 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4766 offset, tosync * sizeof (struct bge_tx_bd), 4767 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4768 4769 /* 4770 * Go through our tx ring and free mbufs for those 4771 * frames that have been sent. 4772 */ 4773 while (sc->bge_tx_saved_considx != 4774 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4775 uint32_t idx = 0; 4776 4777 idx = sc->bge_tx_saved_considx; 4778 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4779 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4780 ifp->if_opackets++; 4781 m = sc->bge_cdata.bge_tx_chain[idx]; 4782 if (m != NULL) { 4783 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4784 dma = sc->txdma[idx]; 4785 if (dma->is_dma32) { 4786 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4787 0, dma->dmamap32->dm_mapsize, 4788 BUS_DMASYNC_POSTWRITE); 4789 bus_dmamap_unload( 4790 sc->bge_dmatag32, dma->dmamap32); 4791 } else { 4792 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4793 0, dma->dmamap->dm_mapsize, 4794 BUS_DMASYNC_POSTWRITE); 4795 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4796 } 4797 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4798 sc->txdma[idx] = NULL; 4799 4800 m_freem(m); 4801 } 4802 sc->bge_txcnt--; 4803 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4804 ifp->if_timer = 0; 4805 } 4806 4807 if (cur_tx != NULL) 4808 ifp->if_flags &= ~IFF_OACTIVE; 4809 } 4810 4811 static int 4812 bge_intr(void *xsc) 4813 { 4814 struct bge_softc *sc; 4815 struct ifnet *ifp; 4816 uint32_t pcistate, statusword, statustag; 4817 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4818 4819 sc = xsc; 4820 ifp = &sc->ethercom.ec_if; 4821 4822 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4823 if (BGE_IS_5717_PLUS(sc)) 4824 intrmask = 0; 4825 4826 /* It is possible for the interrupt to arrive before 4827 * the status block is updated prior to the interrupt. 4828 * Reading the PCI State register will confirm whether the 4829 * interrupt is ours and will flush the status block. 4830 */ 4831 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4832 4833 /* read status word from status block */ 4834 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4835 offsetof(struct bge_ring_data, bge_status_block), 4836 sizeof (struct bge_status_block), 4837 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4838 statusword = sc->bge_rdata->bge_status_block.bge_status; 4839 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4840 4841 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4842 if (sc->bge_lasttag == statustag && 4843 (~pcistate & intrmask)) { 4844 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4845 return (0); 4846 } 4847 sc->bge_lasttag = statustag; 4848 } else { 4849 if (!(statusword & BGE_STATFLAG_UPDATED) && 4850 !(~pcistate & intrmask)) { 4851 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4852 return (0); 4853 } 4854 statustag = 0; 4855 } 4856 /* Ack interrupt and stop others from occurring. */ 4857 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4858 BGE_EVCNT_INCR(sc->bge_ev_intr); 4859 4860 /* clear status word */ 4861 sc->bge_rdata->bge_status_block.bge_status = 0; 4862 4863 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4864 offsetof(struct bge_ring_data, bge_status_block), 4865 sizeof (struct bge_status_block), 4866 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4867 4868 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4869 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4870 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4871 bge_link_upd(sc); 4872 4873 if (ifp->if_flags & IFF_RUNNING) { 4874 /* Check RX return ring producer/consumer */ 4875 bge_rxeof(sc); 4876 4877 /* Check TX ring producer/consumer */ 4878 bge_txeof(sc); 4879 } 4880 4881 if (sc->bge_pending_rxintr_change) { 4882 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4883 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4884 4885 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4886 DELAY(10); 4887 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4888 4889 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4890 DELAY(10); 4891 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4892 4893 sc->bge_pending_rxintr_change = 0; 4894 } 4895 bge_handle_events(sc); 4896 4897 /* Re-enable interrupts. */ 4898 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4899 4900 if (ifp->if_flags & IFF_RUNNING) 4901 if_schedule_deferred_start(ifp); 4902 4903 return 1; 4904 } 4905 4906 static void 4907 bge_asf_driver_up(struct bge_softc *sc) 4908 { 4909 if (sc->bge_asf_mode & ASF_STACKUP) { 4910 /* Send ASF heartbeat aprox. every 2s */ 4911 if (sc->bge_asf_count) 4912 sc->bge_asf_count --; 4913 else { 4914 sc->bge_asf_count = 2; 4915 4916 bge_wait_for_event_ack(sc); 4917 4918 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4919 BGE_FW_CMD_DRV_ALIVE3); 4920 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4921 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4922 BGE_FW_HB_TIMEOUT_SEC); 4923 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4924 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4925 BGE_RX_CPU_DRV_EVENT); 4926 } 4927 } 4928 } 4929 4930 static void 4931 bge_tick(void *xsc) 4932 { 4933 struct bge_softc *sc = xsc; 4934 struct mii_data *mii = &sc->bge_mii; 4935 int s; 4936 4937 s = splnet(); 4938 4939 if (BGE_IS_5705_PLUS(sc)) 4940 bge_stats_update_regs(sc); 4941 else 4942 bge_stats_update(sc); 4943 4944 if (sc->bge_flags & BGEF_FIBER_TBI) { 4945 /* 4946 * Since in TBI mode auto-polling can't be used we should poll 4947 * link status manually. Here we register pending link event 4948 * and trigger interrupt. 4949 */ 4950 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4951 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4952 } else { 4953 /* 4954 * Do not touch PHY if we have link up. This could break 4955 * IPMI/ASF mode or produce extra input errors. 4956 * (extra input errors was reported for bcm5701 & bcm5704). 4957 */ 4958 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4959 mii_tick(mii); 4960 } 4961 4962 bge_asf_driver_up(sc); 4963 4964 if (!sc->bge_detaching) 4965 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4966 4967 splx(s); 4968 } 4969 4970 static void 4971 bge_stats_update_regs(struct bge_softc *sc) 4972 { 4973 struct ifnet *ifp = &sc->ethercom.ec_if; 4974 4975 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4976 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4977 4978 /* 4979 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4980 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4981 * (silicon bug). There's no reliable workaround so just 4982 * ignore the counter 4983 */ 4984 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4985 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5719_A0 && 4986 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5720_A0) { 4987 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4988 } 4989 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4990 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4991 } 4992 4993 static void 4994 bge_stats_update(struct bge_softc *sc) 4995 { 4996 struct ifnet *ifp = &sc->ethercom.ec_if; 4997 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4998 4999 #define READ_STAT(sc, stats, stat) \ 5000 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 5001 5002 ifp->if_collisions += 5003 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 5004 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 5005 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 5006 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 5007 ifp->if_collisions; 5008 5009 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 5010 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 5011 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 5012 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 5013 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 5014 READ_STAT(sc, stats, 5015 xoffPauseFramesReceived.bge_addr_lo)); 5016 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 5017 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 5018 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 5019 READ_STAT(sc, stats, 5020 macControlFramesReceived.bge_addr_lo)); 5021 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 5022 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 5023 5024 #undef READ_STAT 5025 5026 #ifdef notdef 5027 ifp->if_collisions += 5028 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 5029 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 5030 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 5031 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 5032 ifp->if_collisions; 5033 #endif 5034 } 5035 5036 /* 5037 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5038 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5039 * but when such padded frames employ the bge IP/TCP checksum offload, 5040 * the hardware checksum assist gives incorrect results (possibly 5041 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5042 * If we pad such runts with zeros, the onboard checksum comes out correct. 5043 */ 5044 static inline int 5045 bge_cksum_pad(struct mbuf *pkt) 5046 { 5047 struct mbuf *last = NULL; 5048 int padlen; 5049 5050 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 5051 5052 /* if there's only the packet-header and we can pad there, use it. */ 5053 if (pkt->m_pkthdr.len == pkt->m_len && 5054 M_TRAILINGSPACE(pkt) >= padlen) { 5055 last = pkt; 5056 } else { 5057 /* 5058 * Walk packet chain to find last mbuf. We will either 5059 * pad there, or append a new mbuf and pad it 5060 * (thus perhaps avoiding the bcm5700 dma-min bug). 5061 */ 5062 for (last = pkt; last->m_next != NULL; last = last->m_next) { 5063 continue; /* do nothing */ 5064 } 5065 5066 /* `last' now points to last in chain. */ 5067 if (M_TRAILINGSPACE(last) < padlen) { 5068 /* Allocate new empty mbuf, pad it. Compact later. */ 5069 struct mbuf *n; 5070 MGET(n, M_DONTWAIT, MT_DATA); 5071 if (n == NULL) 5072 return ENOBUFS; 5073 n->m_len = 0; 5074 last->m_next = n; 5075 last = n; 5076 } 5077 } 5078 5079 KDASSERT(!M_READONLY(last)); 5080 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 5081 5082 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 5083 memset(mtod(last, char *) + last->m_len, 0, padlen); 5084 last->m_len += padlen; 5085 pkt->m_pkthdr.len += padlen; 5086 return 0; 5087 } 5088 5089 /* 5090 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5091 */ 5092 static inline int 5093 bge_compact_dma_runt(struct mbuf *pkt) 5094 { 5095 struct mbuf *m, *prev; 5096 int totlen; 5097 5098 prev = NULL; 5099 totlen = 0; 5100 5101 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 5102 int mlen = m->m_len; 5103 int shortfall = 8 - mlen ; 5104 5105 totlen += mlen; 5106 if (mlen == 0) 5107 continue; 5108 if (mlen >= 8) 5109 continue; 5110 5111 /* If we get here, mbuf data is too small for DMA engine. 5112 * Try to fix by shuffling data to prev or next in chain. 5113 * If that fails, do a compacting deep-copy of the whole chain. 5114 */ 5115 5116 /* Internal frag. If fits in prev, copy it there. */ 5117 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5118 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5119 prev->m_len += mlen; 5120 m->m_len = 0; 5121 /* XXX stitch chain */ 5122 prev->m_next = m_free(m); 5123 m = prev; 5124 continue; 5125 } 5126 else if (m->m_next != NULL && 5127 M_TRAILINGSPACE(m) >= shortfall && 5128 m->m_next->m_len >= (8 + shortfall)) { 5129 /* m is writable and have enough data in next, pull up. */ 5130 5131 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5132 shortfall); 5133 m->m_len += shortfall; 5134 m->m_next->m_len -= shortfall; 5135 m->m_next->m_data += shortfall; 5136 } 5137 else if (m->m_next == NULL || 1) { 5138 /* Got a runt at the very end of the packet. 5139 * borrow data from the tail of the preceding mbuf and 5140 * update its length in-place. (The original data is still 5141 * valid, so we can do this even if prev is not writable.) 5142 */ 5143 5144 /* if we'd make prev a runt, just move all of its data. */ 5145 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5146 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5147 5148 if ((prev->m_len - shortfall) < 8) 5149 shortfall = prev->m_len; 5150 5151 #ifdef notyet /* just do the safe slow thing for now */ 5152 if (!M_READONLY(m)) { 5153 if (M_LEADINGSPACE(m) < shorfall) { 5154 void *m_dat; 5155 m_dat = (m->m_flags & M_PKTHDR) ? 5156 m->m_pktdat : m->dat; 5157 memmove(m_dat, mtod(m, void*), m->m_len); 5158 m->m_data = m_dat; 5159 } 5160 } else 5161 #endif /* just do the safe slow thing */ 5162 { 5163 struct mbuf * n = NULL; 5164 int newprevlen = prev->m_len - shortfall; 5165 5166 MGET(n, M_NOWAIT, MT_DATA); 5167 if (n == NULL) 5168 return ENOBUFS; 5169 KASSERT(m->m_len + shortfall < MLEN 5170 /*, 5171 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5172 5173 /* first copy the data we're stealing from prev */ 5174 memcpy(n->m_data, prev->m_data + newprevlen, 5175 shortfall); 5176 5177 /* update prev->m_len accordingly */ 5178 prev->m_len -= shortfall; 5179 5180 /* copy data from runt m */ 5181 memcpy(n->m_data + shortfall, m->m_data, 5182 m->m_len); 5183 5184 /* n holds what we stole from prev, plus m */ 5185 n->m_len = shortfall + m->m_len; 5186 5187 /* stitch n into chain and free m */ 5188 n->m_next = m->m_next; 5189 prev->m_next = n; 5190 /* KASSERT(m->m_next == NULL); */ 5191 m->m_next = NULL; 5192 m_free(m); 5193 m = n; /* for continuing loop */ 5194 } 5195 } 5196 } 5197 return 0; 5198 } 5199 5200 /* 5201 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5202 * pointers to descriptors. 5203 */ 5204 static int 5205 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5206 { 5207 struct ifnet *ifp = &sc->ethercom.ec_if; 5208 struct bge_tx_bd *f, *prev_f; 5209 uint32_t frag, cur; 5210 uint16_t csum_flags = 0; 5211 uint16_t txbd_tso_flags = 0; 5212 struct txdmamap_pool_entry *dma; 5213 bus_dmamap_t dmamap; 5214 bus_dma_tag_t dmatag; 5215 int i = 0; 5216 int use_tso, maxsegsize, error; 5217 bool have_vtag; 5218 uint16_t vtag; 5219 bool remap; 5220 5221 if (m_head->m_pkthdr.csum_flags) { 5222 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5223 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5224 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 5225 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5226 } 5227 5228 /* 5229 * If we were asked to do an outboard checksum, and the NIC 5230 * has the bug where it sometimes adds in the Ethernet padding, 5231 * explicitly pad with zeros so the cksum will be correct either way. 5232 * (For now, do this for all chip versions, until newer 5233 * are confirmed to not require the workaround.) 5234 */ 5235 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5236 #ifdef notyet 5237 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5238 #endif 5239 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5240 goto check_dma_bug; 5241 5242 if (bge_cksum_pad(m_head) != 0) 5243 return ENOBUFS; 5244 5245 check_dma_bug: 5246 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5247 goto doit; 5248 5249 /* 5250 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5251 * less than eight bytes. If we encounter a teeny mbuf 5252 * at the end of a chain, we can pad. Otherwise, copy. 5253 */ 5254 if (bge_compact_dma_runt(m_head) != 0) 5255 return ENOBUFS; 5256 5257 doit: 5258 dma = SLIST_FIRST(&sc->txdma_list); 5259 if (dma == NULL) { 5260 ifp->if_flags |= IFF_OACTIVE; 5261 return ENOBUFS; 5262 } 5263 dmamap = dma->dmamap; 5264 dmatag = sc->bge_dmatag; 5265 dma->is_dma32 = false; 5266 5267 /* 5268 * Set up any necessary TSO state before we start packing... 5269 */ 5270 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5271 if (!use_tso) { 5272 maxsegsize = 0; 5273 } else { /* TSO setup */ 5274 unsigned mss; 5275 struct ether_header *eh; 5276 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5277 unsigned bge_hlen; 5278 struct mbuf * m0 = m_head; 5279 struct ip *ip; 5280 struct tcphdr *th; 5281 int iphl, hlen; 5282 5283 /* 5284 * XXX It would be nice if the mbuf pkthdr had offset 5285 * fields for the protocol headers. 5286 */ 5287 5288 eh = mtod(m0, struct ether_header *); 5289 switch (htons(eh->ether_type)) { 5290 case ETHERTYPE_IP: 5291 offset = ETHER_HDR_LEN; 5292 break; 5293 5294 case ETHERTYPE_VLAN: 5295 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5296 break; 5297 5298 default: 5299 /* 5300 * Don't support this protocol or encapsulation. 5301 */ 5302 return ENOBUFS; 5303 } 5304 5305 /* 5306 * TCP/IP headers are in the first mbuf; we can do 5307 * this the easy way. 5308 */ 5309 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5310 hlen = iphl + offset; 5311 if (__predict_false(m0->m_len < 5312 (hlen + sizeof(struct tcphdr)))) { 5313 5314 aprint_error_dev(sc->bge_dev, 5315 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5316 "not handled yet\n", 5317 m0->m_len, hlen+ sizeof(struct tcphdr)); 5318 #ifdef NOTYET 5319 /* 5320 * XXX jonathan (at) NetBSD.org: untested. 5321 * how to force this branch to be taken? 5322 */ 5323 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5324 5325 m_copydata(m0, offset, sizeof(ip), &ip); 5326 m_copydata(m0, hlen, sizeof(th), &th); 5327 5328 ip.ip_len = 0; 5329 5330 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5331 sizeof(ip.ip_len), &ip.ip_len); 5332 5333 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5334 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5335 5336 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5337 sizeof(th.th_sum), &th.th_sum); 5338 5339 hlen += th.th_off << 2; 5340 iptcp_opt_words = hlen; 5341 #else 5342 /* 5343 * if_wm "hard" case not yet supported, can we not 5344 * mandate it out of existence? 5345 */ 5346 (void) ip; (void)th; (void) ip_tcp_hlen; 5347 5348 return ENOBUFS; 5349 #endif 5350 } else { 5351 ip = (struct ip *) (mtod(m0, char *) + offset); 5352 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5353 ip_tcp_hlen = iphl + (th->th_off << 2); 5354 5355 /* Total IP/TCP options, in 32-bit words */ 5356 iptcp_opt_words = (ip_tcp_hlen 5357 - sizeof(struct tcphdr) 5358 - sizeof(struct ip)) >> 2; 5359 } 5360 if (BGE_IS_575X_PLUS(sc)) { 5361 th->th_sum = 0; 5362 csum_flags = 0; 5363 } else { 5364 /* 5365 * XXX jonathan (at) NetBSD.org: 5705 untested. 5366 * Requires TSO firmware patch for 5701/5703/5704. 5367 */ 5368 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5369 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5370 } 5371 5372 mss = m_head->m_pkthdr.segsz; 5373 txbd_tso_flags |= 5374 BGE_TXBDFLAG_CPU_PRE_DMA | 5375 BGE_TXBDFLAG_CPU_POST_DMA; 5376 5377 /* 5378 * Our NIC TSO-assist assumes TSO has standard, optionless 5379 * IPv4 and TCP headers, which total 40 bytes. By default, 5380 * the NIC copies 40 bytes of IP/TCP header from the 5381 * supplied header into the IP/TCP header portion of 5382 * each post-TSO-segment. If the supplied packet has IP or 5383 * TCP options, we need to tell the NIC to copy those extra 5384 * bytes into each post-TSO header, in addition to the normal 5385 * 40-byte IP/TCP header (and to leave space accordingly). 5386 * Unfortunately, the driver encoding of option length 5387 * varies across different ASIC families. 5388 */ 5389 tcp_seg_flags = 0; 5390 bge_hlen = ip_tcp_hlen >> 2; 5391 if (BGE_IS_5717_PLUS(sc)) { 5392 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5393 txbd_tso_flags |= 5394 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5395 } else if (BGE_IS_5705_PLUS(sc)) { 5396 tcp_seg_flags = 5397 bge_hlen << 11; 5398 } else { 5399 /* XXX iptcp_opt_words or bge_hlen ? */ 5400 txbd_tso_flags |= 5401 iptcp_opt_words << 12; 5402 } 5403 maxsegsize = mss | tcp_seg_flags; 5404 ip->ip_len = htons(mss + ip_tcp_hlen); 5405 ip->ip_sum = 0; 5406 5407 } /* TSO setup */ 5408 5409 have_vtag = vlan_has_tag(m_head); 5410 if (have_vtag) 5411 vtag = vlan_get_tag(m_head); 5412 5413 /* 5414 * Start packing the mbufs in this chain into 5415 * the fragment pointers. Stop when we run out 5416 * of fragments or hit the end of the mbuf chain. 5417 */ 5418 remap = true; 5419 load_again: 5420 error = bus_dmamap_load_mbuf(dmatag, dmamap, 5421 m_head, BUS_DMA_NOWAIT); 5422 if (__predict_false(error)) { 5423 if (error == EFBIG && remap) { 5424 struct mbuf *m; 5425 remap = false; 5426 m = m_defrag(m_head, M_NOWAIT); 5427 if (m != NULL) { 5428 KASSERT(m == m_head); 5429 goto load_again; 5430 } 5431 } 5432 return error; 5433 } 5434 /* 5435 * Sanity check: avoid coming within 16 descriptors 5436 * of the end of the ring. 5437 */ 5438 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5439 BGE_TSO_PRINTF(("%s: " 5440 " dmamap_load_mbuf too close to ring wrap\n", 5441 device_xname(sc->bge_dev))); 5442 goto fail_unload; 5443 } 5444 5445 /* Iterate over dmap-map fragments. */ 5446 f = prev_f = NULL; 5447 cur = frag = *txidx; 5448 5449 for (i = 0; i < dmamap->dm_nsegs; i++) { 5450 f = &sc->bge_rdata->bge_tx_ring[frag]; 5451 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5452 break; 5453 5454 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5455 f->bge_len = dmamap->dm_segs[i].ds_len; 5456 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5457 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5458 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5459 (prev_f != NULL && 5460 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5461 ) { 5462 /* 5463 * watchdog timeout issue was observed with TSO, 5464 * limiting DMA address space to 32bits seems to 5465 * address the issue. 5466 */ 5467 bus_dmamap_unload(dmatag, dmamap); 5468 dmatag = sc->bge_dmatag32; 5469 dmamap = dma->dmamap32; 5470 dma->is_dma32 = true; 5471 remap = true; 5472 goto load_again; 5473 } 5474 5475 /* 5476 * For 5751 and follow-ons, for TSO we must turn 5477 * off checksum-assist flag in the tx-descr, and 5478 * supply the ASIC-revision-specific encoding 5479 * of TSO flags and segsize. 5480 */ 5481 if (use_tso) { 5482 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5483 f->bge_rsvd = maxsegsize; 5484 f->bge_flags = csum_flags | txbd_tso_flags; 5485 } else { 5486 f->bge_rsvd = 0; 5487 f->bge_flags = 5488 (csum_flags | txbd_tso_flags) & 0x0fff; 5489 } 5490 } else { 5491 f->bge_rsvd = 0; 5492 f->bge_flags = csum_flags; 5493 } 5494 5495 if (have_vtag) { 5496 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5497 f->bge_vlan_tag = vtag; 5498 } else { 5499 f->bge_vlan_tag = 0; 5500 } 5501 prev_f = f; 5502 cur = frag; 5503 BGE_INC(frag, BGE_TX_RING_CNT); 5504 } 5505 5506 if (i < dmamap->dm_nsegs) { 5507 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5508 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5509 goto fail_unload; 5510 } 5511 5512 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5513 BUS_DMASYNC_PREWRITE); 5514 5515 if (frag == sc->bge_tx_saved_considx) { 5516 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5517 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5518 5519 goto fail_unload; 5520 } 5521 5522 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5523 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5524 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5525 sc->txdma[cur] = dma; 5526 sc->bge_txcnt += dmamap->dm_nsegs; 5527 5528 *txidx = frag; 5529 5530 return 0; 5531 5532 fail_unload: 5533 bus_dmamap_unload(dmatag, dmamap); 5534 ifp->if_flags |= IFF_OACTIVE; 5535 5536 return ENOBUFS; 5537 } 5538 5539 /* 5540 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5541 * to the mbuf data regions directly in the transmit descriptors. 5542 */ 5543 static void 5544 bge_start(struct ifnet *ifp) 5545 { 5546 struct bge_softc *sc; 5547 struct mbuf *m_head = NULL; 5548 struct mbuf *m; 5549 uint32_t prodidx; 5550 int pkts = 0; 5551 int error; 5552 5553 sc = ifp->if_softc; 5554 5555 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5556 return; 5557 5558 prodidx = sc->bge_tx_prodidx; 5559 5560 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5561 IFQ_POLL(&ifp->if_snd, m_head); 5562 if (m_head == NULL) 5563 break; 5564 5565 #if 0 5566 /* 5567 * XXX 5568 * safety overkill. If this is a fragmented packet chain 5569 * with delayed TCP/UDP checksums, then only encapsulate 5570 * it if we have enough descriptors to handle the entire 5571 * chain at once. 5572 * (paranoia -- may not actually be needed) 5573 */ 5574 if (m_head->m_flags & M_FIRSTFRAG && 5575 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5576 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5577 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5578 ifp->if_flags |= IFF_OACTIVE; 5579 break; 5580 } 5581 } 5582 #endif 5583 5584 /* 5585 * Pack the data into the transmit ring. If we 5586 * don't have room, set the OACTIVE flag and wait 5587 * for the NIC to drain the ring. 5588 */ 5589 error = bge_encap(sc, m_head, &prodidx); 5590 if (__predict_false(error)) { 5591 if (ifp->if_flags & IFF_OACTIVE) { 5592 /* just wait for the transmit ring to drain */ 5593 break; 5594 } 5595 IFQ_DEQUEUE(&ifp->if_snd, m); 5596 KASSERT(m == m_head); 5597 m_freem(m_head); 5598 continue; 5599 } 5600 5601 /* now we are committed to transmit the packet */ 5602 IFQ_DEQUEUE(&ifp->if_snd, m); 5603 KASSERT(m == m_head); 5604 pkts++; 5605 5606 /* 5607 * If there's a BPF listener, bounce a copy of this frame 5608 * to him. 5609 */ 5610 bpf_mtap(ifp, m_head, BPF_D_OUT); 5611 } 5612 if (pkts == 0) 5613 return; 5614 5615 /* Transmit */ 5616 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5617 /* 5700 b2 errata */ 5618 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5619 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5620 5621 sc->bge_tx_prodidx = prodidx; 5622 5623 /* 5624 * Set a timeout in case the chip goes out to lunch. 5625 */ 5626 ifp->if_timer = 5; 5627 } 5628 5629 static int 5630 bge_init(struct ifnet *ifp) 5631 { 5632 struct bge_softc *sc = ifp->if_softc; 5633 const uint16_t *m; 5634 uint32_t mode, reg; 5635 int s, error = 0; 5636 5637 s = splnet(); 5638 5639 ifp = &sc->ethercom.ec_if; 5640 5641 /* Cancel pending I/O and flush buffers. */ 5642 bge_stop(ifp, 0); 5643 5644 bge_stop_fw(sc); 5645 bge_sig_pre_reset(sc, BGE_RESET_START); 5646 bge_reset(sc); 5647 bge_sig_legacy(sc, BGE_RESET_START); 5648 5649 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5650 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5651 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5652 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5653 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5654 5655 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5656 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5657 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5658 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5659 5660 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5661 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5662 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5663 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5664 5665 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5666 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5667 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5668 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5669 } 5670 5671 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5672 pcireg_t aercap; 5673 5674 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5675 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5676 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5677 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5678 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5679 5680 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5681 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5682 | BGE_PCIE_EIDLE_DELAY_13CLK; 5683 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5684 5685 /* Clear correctable error */ 5686 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5687 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5688 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5689 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5690 5691 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5692 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5693 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5694 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5695 } 5696 5697 bge_sig_post_reset(sc, BGE_RESET_START); 5698 5699 bge_chipinit(sc); 5700 5701 /* 5702 * Init the various state machines, ring 5703 * control blocks and firmware. 5704 */ 5705 error = bge_blockinit(sc); 5706 if (error != 0) { 5707 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5708 error); 5709 splx(s); 5710 return error; 5711 } 5712 5713 ifp = &sc->ethercom.ec_if; 5714 5715 /* 5718 step 25, 57XX step 54 */ 5716 /* Specify MTU. */ 5717 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5718 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5719 5720 /* 5718 step 23 */ 5721 /* Load our MAC address. */ 5722 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5723 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5724 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5725 5726 /* Enable or disable promiscuous mode as needed. */ 5727 if (ifp->if_flags & IFF_PROMISC) 5728 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5729 else 5730 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5731 5732 /* Program multicast filter. */ 5733 bge_setmulti(sc); 5734 5735 /* Init RX ring. */ 5736 bge_init_rx_ring_std(sc); 5737 5738 /* 5739 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5740 * memory to insure that the chip has in fact read the first 5741 * entry of the ring. 5742 */ 5743 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5744 uint32_t v, i; 5745 for (i = 0; i < 10; i++) { 5746 DELAY(20); 5747 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5748 if (v == (MCLBYTES - ETHER_ALIGN)) 5749 break; 5750 } 5751 if (i == 10) 5752 aprint_error_dev(sc->bge_dev, 5753 "5705 A0 chip failed to load RX ring\n"); 5754 } 5755 5756 /* Init jumbo RX ring. */ 5757 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5758 bge_init_rx_ring_jumbo(sc); 5759 5760 /* Init our RX return ring index */ 5761 sc->bge_rx_saved_considx = 0; 5762 5763 /* Init TX ring. */ 5764 bge_init_tx_ring(sc); 5765 5766 /* 5718 step 63, 57XX step 94 */ 5767 /* Enable TX MAC state machine lockup fix. */ 5768 mode = CSR_READ_4(sc, BGE_TX_MODE); 5769 if (BGE_IS_5755_PLUS(sc) || 5770 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5771 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5772 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5773 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5774 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5775 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5776 } 5777 5778 /* Turn on transmitter */ 5779 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5780 /* 5718 step 64 */ 5781 DELAY(100); 5782 5783 /* 5718 step 65, 57XX step 95 */ 5784 /* Turn on receiver */ 5785 mode = CSR_READ_4(sc, BGE_RX_MODE); 5786 if (BGE_IS_5755_PLUS(sc)) 5787 mode |= BGE_RXMODE_IPV6_ENABLE; 5788 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5789 /* 5718 step 66 */ 5790 DELAY(10); 5791 5792 /* 5718 step 12, 57XX step 37 */ 5793 /* 5794 * XXX Doucments of 5718 series and 577xx say the recommended value 5795 * is 1, but tg3 set 1 only on 57765 series. 5796 */ 5797 if (BGE_IS_57765_PLUS(sc)) 5798 reg = 1; 5799 else 5800 reg = 2; 5801 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5802 5803 /* Tell firmware we're alive. */ 5804 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5805 5806 /* Enable host interrupts. */ 5807 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5808 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5809 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5810 5811 if ((error = bge_ifmedia_upd(ifp)) != 0) 5812 goto out; 5813 5814 ifp->if_flags |= IFF_RUNNING; 5815 ifp->if_flags &= ~IFF_OACTIVE; 5816 5817 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5818 5819 out: 5820 sc->bge_if_flags = ifp->if_flags; 5821 splx(s); 5822 5823 return error; 5824 } 5825 5826 /* 5827 * Set media options. 5828 */ 5829 static int 5830 bge_ifmedia_upd(struct ifnet *ifp) 5831 { 5832 struct bge_softc *sc = ifp->if_softc; 5833 struct mii_data *mii = &sc->bge_mii; 5834 struct ifmedia *ifm = &sc->bge_ifmedia; 5835 int rc; 5836 5837 /* If this is a 1000baseX NIC, enable the TBI port. */ 5838 if (sc->bge_flags & BGEF_FIBER_TBI) { 5839 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5840 return EINVAL; 5841 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5842 case IFM_AUTO: 5843 /* 5844 * The BCM5704 ASIC appears to have a special 5845 * mechanism for programming the autoneg 5846 * advertisement registers in TBI mode. 5847 */ 5848 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5849 uint32_t sgdig; 5850 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5851 if (sgdig & BGE_SGDIGSTS_DONE) { 5852 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5853 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5854 sgdig |= BGE_SGDIGCFG_AUTO | 5855 BGE_SGDIGCFG_PAUSE_CAP | 5856 BGE_SGDIGCFG_ASYM_PAUSE; 5857 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5858 sgdig | BGE_SGDIGCFG_SEND); 5859 DELAY(5); 5860 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5861 sgdig); 5862 } 5863 } 5864 break; 5865 case IFM_1000_SX: 5866 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5867 BGE_CLRBIT(sc, BGE_MAC_MODE, 5868 BGE_MACMODE_HALF_DUPLEX); 5869 } else { 5870 BGE_SETBIT(sc, BGE_MAC_MODE, 5871 BGE_MACMODE_HALF_DUPLEX); 5872 } 5873 DELAY(40); 5874 break; 5875 default: 5876 return EINVAL; 5877 } 5878 /* XXX 802.3x flow control for 1000BASE-SX */ 5879 return 0; 5880 } 5881 5882 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5883 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5884 uint32_t reg; 5885 5886 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5887 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5888 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5889 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5890 } 5891 } 5892 5893 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5894 if ((rc = mii_mediachg(mii)) == ENXIO) 5895 return 0; 5896 5897 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5898 uint32_t reg; 5899 5900 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5901 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5902 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5903 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5904 delay(40); 5905 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5906 } 5907 } 5908 5909 /* 5910 * Force an interrupt so that we will call bge_link_upd 5911 * if needed and clear any pending link state attention. 5912 * Without this we are not getting any further interrupts 5913 * for link state changes and thus will not UP the link and 5914 * not be able to send in bge_start. The only way to get 5915 * things working was to receive a packet and get a RX intr. 5916 */ 5917 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5918 sc->bge_flags & BGEF_IS_5788) 5919 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5920 else 5921 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5922 5923 return rc; 5924 } 5925 5926 /* 5927 * Report current media status. 5928 */ 5929 static void 5930 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5931 { 5932 struct bge_softc *sc = ifp->if_softc; 5933 struct mii_data *mii = &sc->bge_mii; 5934 5935 if (sc->bge_flags & BGEF_FIBER_TBI) { 5936 ifmr->ifm_status = IFM_AVALID; 5937 ifmr->ifm_active = IFM_ETHER; 5938 if (CSR_READ_4(sc, BGE_MAC_STS) & 5939 BGE_MACSTAT_TBI_PCS_SYNCHED) 5940 ifmr->ifm_status |= IFM_ACTIVE; 5941 ifmr->ifm_active |= IFM_1000_SX; 5942 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5943 ifmr->ifm_active |= IFM_HDX; 5944 else 5945 ifmr->ifm_active |= IFM_FDX; 5946 return; 5947 } 5948 5949 mii_pollstat(mii); 5950 ifmr->ifm_status = mii->mii_media_status; 5951 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5952 sc->bge_flowflags; 5953 } 5954 5955 static int 5956 bge_ifflags_cb(struct ethercom *ec) 5957 { 5958 struct ifnet *ifp = &ec->ec_if; 5959 struct bge_softc *sc = ifp->if_softc; 5960 int change = ifp->if_flags ^ sc->bge_if_flags; 5961 5962 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5963 return ENETRESET; 5964 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5965 return 0; 5966 5967 if ((ifp->if_flags & IFF_PROMISC) == 0) 5968 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5969 else 5970 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5971 5972 bge_setmulti(sc); 5973 5974 sc->bge_if_flags = ifp->if_flags; 5975 return 0; 5976 } 5977 5978 static int 5979 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5980 { 5981 struct bge_softc *sc = ifp->if_softc; 5982 struct ifreq *ifr = (struct ifreq *) data; 5983 int s, error = 0; 5984 struct mii_data *mii; 5985 5986 s = splnet(); 5987 5988 switch (command) { 5989 case SIOCSIFMEDIA: 5990 /* XXX Flow control is not supported for 1000BASE-SX */ 5991 if (sc->bge_flags & BGEF_FIBER_TBI) { 5992 ifr->ifr_media &= ~IFM_ETH_FMASK; 5993 sc->bge_flowflags = 0; 5994 } 5995 5996 /* Flow control requires full-duplex mode. */ 5997 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5998 (ifr->ifr_media & IFM_FDX) == 0) { 5999 ifr->ifr_media &= ~IFM_ETH_FMASK; 6000 } 6001 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 6002 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 6003 /* We can do both TXPAUSE and RXPAUSE. */ 6004 ifr->ifr_media |= 6005 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 6006 } 6007 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 6008 } 6009 /* FALLTHROUGH */ 6010 case SIOCGIFMEDIA: 6011 if (sc->bge_flags & BGEF_FIBER_TBI) { 6012 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 6013 command); 6014 } else { 6015 mii = &sc->bge_mii; 6016 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 6017 command); 6018 } 6019 break; 6020 default: 6021 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 6022 break; 6023 6024 error = 0; 6025 6026 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 6027 ; 6028 else if (ifp->if_flags & IFF_RUNNING) 6029 bge_setmulti(sc); 6030 break; 6031 } 6032 6033 splx(s); 6034 6035 return error; 6036 } 6037 6038 static void 6039 bge_watchdog(struct ifnet *ifp) 6040 { 6041 struct bge_softc *sc; 6042 uint32_t status; 6043 6044 sc = ifp->if_softc; 6045 6046 /* If pause frames are active then don't reset the hardware. */ 6047 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 6048 status = CSR_READ_4(sc, BGE_RX_STS); 6049 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 6050 /* 6051 * If link partner has us in XOFF state then wait for 6052 * the condition to clear. 6053 */ 6054 CSR_WRITE_4(sc, BGE_RX_STS, status); 6055 ifp->if_timer = 5; 6056 return; 6057 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 6058 (status & BGE_RXSTAT_RCVD_XON) != 0) { 6059 /* 6060 * If link partner has us in XOFF state then wait for 6061 * the condition to clear. 6062 */ 6063 CSR_WRITE_4(sc, BGE_RX_STS, status); 6064 ifp->if_timer = 5; 6065 return; 6066 } 6067 /* 6068 * Any other condition is unexpected and the controller 6069 * should be reset. 6070 */ 6071 } 6072 6073 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 6074 6075 ifp->if_flags &= ~IFF_RUNNING; 6076 bge_init(ifp); 6077 6078 ifp->if_oerrors++; 6079 } 6080 6081 static void 6082 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 6083 { 6084 int i; 6085 6086 BGE_CLRBIT_FLUSH(sc, reg, bit); 6087 6088 for (i = 0; i < 1000; i++) { 6089 delay(100); 6090 if ((CSR_READ_4(sc, reg) & bit) == 0) 6091 return; 6092 } 6093 6094 /* 6095 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 6096 * on some environment (and once after boot?) 6097 */ 6098 if (reg != BGE_SRS_MODE) 6099 aprint_error_dev(sc->bge_dev, 6100 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 6101 (u_long)reg, bit); 6102 } 6103 6104 /* 6105 * Stop the adapter and free any mbufs allocated to the 6106 * RX and TX lists. 6107 */ 6108 static void 6109 bge_stop(struct ifnet *ifp, int disable) 6110 { 6111 struct bge_softc *sc = ifp->if_softc; 6112 6113 if (disable) { 6114 sc->bge_detaching = 1; 6115 callout_halt(&sc->bge_timeout, NULL); 6116 } else 6117 callout_stop(&sc->bge_timeout); 6118 6119 /* Disable host interrupts. */ 6120 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6121 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6122 6123 /* 6124 * Tell firmware we're shutting down. 6125 */ 6126 bge_stop_fw(sc); 6127 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6128 6129 /* 6130 * Disable all of the receiver blocks. 6131 */ 6132 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6133 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6134 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6135 if (BGE_IS_5700_FAMILY(sc)) 6136 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6137 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6138 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6139 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6140 6141 /* 6142 * Disable all of the transmit blocks. 6143 */ 6144 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6145 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6146 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6147 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6148 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6149 if (BGE_IS_5700_FAMILY(sc)) 6150 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6151 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6152 6153 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6154 delay(40); 6155 6156 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6157 6158 /* 6159 * Shut down all of the memory managers and related 6160 * state machines. 6161 */ 6162 /* 5718 step 5a,5b */ 6163 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6164 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6165 if (BGE_IS_5700_FAMILY(sc)) 6166 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6167 6168 /* 5718 step 5c,5d */ 6169 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6170 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6171 6172 if (BGE_IS_5700_FAMILY(sc)) { 6173 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6174 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6175 } 6176 6177 bge_reset(sc); 6178 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6179 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6180 6181 /* 6182 * Keep the ASF firmware running if up. 6183 */ 6184 if (sc->bge_asf_mode & ASF_STACKUP) 6185 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6186 else 6187 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6188 6189 /* Free the RX lists. */ 6190 bge_free_rx_ring_std(sc, disable); 6191 6192 /* Free jumbo RX list. */ 6193 if (BGE_IS_JUMBO_CAPABLE(sc)) 6194 bge_free_rx_ring_jumbo(sc); 6195 6196 /* Free TX buffers. */ 6197 bge_free_tx_ring(sc, disable); 6198 6199 /* 6200 * Isolate/power down the PHY. 6201 */ 6202 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6203 mii_down(&sc->bge_mii); 6204 6205 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6206 6207 /* Clear MAC's link state (PHY may still have link UP). */ 6208 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6209 6210 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6211 } 6212 6213 static void 6214 bge_link_upd(struct bge_softc *sc) 6215 { 6216 struct ifnet *ifp = &sc->ethercom.ec_if; 6217 struct mii_data *mii = &sc->bge_mii; 6218 uint32_t status; 6219 uint16_t phyval; 6220 int link; 6221 6222 /* Clear 'pending link event' flag */ 6223 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6224 6225 /* 6226 * Process link state changes. 6227 * Grrr. The link status word in the status block does 6228 * not work correctly on the BCM5700 rev AX and BX chips, 6229 * according to all available information. Hence, we have 6230 * to enable MII interrupts in order to properly obtain 6231 * async link changes. Unfortunately, this also means that 6232 * we have to read the MAC status register to detect link 6233 * changes, thereby adding an additional register access to 6234 * the interrupt handler. 6235 */ 6236 6237 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6238 status = CSR_READ_4(sc, BGE_MAC_STS); 6239 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6240 mii_pollstat(mii); 6241 6242 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6243 mii->mii_media_status & IFM_ACTIVE && 6244 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6245 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6246 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6247 (!(mii->mii_media_status & IFM_ACTIVE) || 6248 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6249 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6250 6251 /* Clear the interrupt */ 6252 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6253 BGE_EVTENB_MI_INTERRUPT); 6254 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6255 BRGPHY_MII_ISR, &phyval); 6256 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6257 BRGPHY_MII_IMR, BRGPHY_INTRS); 6258 } 6259 return; 6260 } 6261 6262 if (sc->bge_flags & BGEF_FIBER_TBI) { 6263 status = CSR_READ_4(sc, BGE_MAC_STS); 6264 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6265 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6266 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6267 if (BGE_ASICREV(sc->bge_chipid) 6268 == BGE_ASICREV_BCM5704) { 6269 BGE_CLRBIT(sc, BGE_MAC_MODE, 6270 BGE_MACMODE_TBI_SEND_CFGS); 6271 DELAY(40); 6272 } 6273 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6274 if_link_state_change(ifp, LINK_STATE_UP); 6275 } 6276 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6277 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6278 if_link_state_change(ifp, LINK_STATE_DOWN); 6279 } 6280 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6281 /* 6282 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6283 * bit in status word always set. Workaround this bug by 6284 * reading PHY link status directly. 6285 */ 6286 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6287 BGE_STS_LINK : 0; 6288 6289 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6290 mii_pollstat(mii); 6291 6292 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6293 mii->mii_media_status & IFM_ACTIVE && 6294 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6295 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6296 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6297 (!(mii->mii_media_status & IFM_ACTIVE) || 6298 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6299 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6300 } 6301 } else { 6302 /* 6303 * For controllers that call mii_tick, we have to poll 6304 * link status. 6305 */ 6306 mii_pollstat(mii); 6307 } 6308 6309 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6310 uint32_t reg, scale; 6311 6312 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6313 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6314 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6315 scale = 65; 6316 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6317 scale = 6; 6318 else 6319 scale = 12; 6320 6321 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6322 ~BGE_MISCCFG_TIMER_PRESCALER; 6323 reg |= scale << 1; 6324 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6325 } 6326 /* Clear the attention */ 6327 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6328 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6329 BGE_MACSTAT_LINK_CHANGED); 6330 } 6331 6332 static int 6333 bge_sysctl_verify(SYSCTLFN_ARGS) 6334 { 6335 int error, t; 6336 struct sysctlnode node; 6337 6338 node = *rnode; 6339 t = *(int*)rnode->sysctl_data; 6340 node.sysctl_data = &t; 6341 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6342 if (error || newp == NULL) 6343 return error; 6344 6345 #if 0 6346 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6347 node.sysctl_num, rnode->sysctl_num)); 6348 #endif 6349 6350 if (node.sysctl_num == bge_rxthresh_nodenum) { 6351 if (t < 0 || t >= NBGE_RX_THRESH) 6352 return EINVAL; 6353 bge_update_all_threshes(t); 6354 } else 6355 return EINVAL; 6356 6357 *(int*)rnode->sysctl_data = t; 6358 6359 return 0; 6360 } 6361 6362 /* 6363 * Set up sysctl(3) MIB, hw.bge.*. 6364 */ 6365 static void 6366 bge_sysctl_init(struct bge_softc *sc) 6367 { 6368 int rc, bge_root_num; 6369 const struct sysctlnode *node; 6370 6371 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6372 0, CTLTYPE_NODE, "bge", 6373 SYSCTL_DESCR("BGE interface controls"), 6374 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6375 goto out; 6376 } 6377 6378 bge_root_num = node->sysctl_num; 6379 6380 /* BGE Rx interrupt mitigation level */ 6381 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6382 CTLFLAG_READWRITE, 6383 CTLTYPE_INT, "rx_lvl", 6384 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6385 bge_sysctl_verify, 0, 6386 &bge_rx_thresh_lvl, 6387 0, CTL_HW, bge_root_num, CTL_CREATE, 6388 CTL_EOL)) != 0) { 6389 goto out; 6390 } 6391 6392 bge_rxthresh_nodenum = node->sysctl_num; 6393 6394 return; 6395 6396 out: 6397 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6398 } 6399 6400 #ifdef BGE_DEBUG 6401 void 6402 bge_debug_info(struct bge_softc *sc) 6403 { 6404 6405 printf("Hardware Flags:\n"); 6406 if (BGE_IS_57765_PLUS(sc)) 6407 printf(" - 57765 Plus\n"); 6408 if (BGE_IS_5717_PLUS(sc)) 6409 printf(" - 5717 Plus\n"); 6410 if (BGE_IS_5755_PLUS(sc)) 6411 printf(" - 5755 Plus\n"); 6412 if (BGE_IS_575X_PLUS(sc)) 6413 printf(" - 575X Plus\n"); 6414 if (BGE_IS_5705_PLUS(sc)) 6415 printf(" - 5705 Plus\n"); 6416 if (BGE_IS_5714_FAMILY(sc)) 6417 printf(" - 5714 Family\n"); 6418 if (BGE_IS_5700_FAMILY(sc)) 6419 printf(" - 5700 Family\n"); 6420 if (sc->bge_flags & BGEF_IS_5788) 6421 printf(" - 5788\n"); 6422 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6423 printf(" - Supports Jumbo Frames\n"); 6424 if (sc->bge_flags & BGEF_NO_EEPROM) 6425 printf(" - No EEPROM\n"); 6426 if (sc->bge_flags & BGEF_PCIX) 6427 printf(" - PCI-X Bus\n"); 6428 if (sc->bge_flags & BGEF_PCIE) 6429 printf(" - PCI Express Bus\n"); 6430 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6431 printf(" - RX Alignment Bug\n"); 6432 if (sc->bge_flags & BGEF_APE) 6433 printf(" - APE\n"); 6434 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6435 printf(" - CPMU\n"); 6436 if (sc->bge_flags & BGEF_TSO) 6437 printf(" - TSO\n"); 6438 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6439 printf(" - TAGGED_STATUS\n"); 6440 6441 /* PHY related */ 6442 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6443 printf(" - No 3 LEDs\n"); 6444 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6445 printf(" - CRC bug\n"); 6446 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6447 printf(" - ADC bug\n"); 6448 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6449 printf(" - 5704 A0 bug\n"); 6450 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6451 printf(" - jitter bug\n"); 6452 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6453 printf(" - BER bug\n"); 6454 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6455 printf(" - adjust trim\n"); 6456 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6457 printf(" - no wirespeed\n"); 6458 6459 /* ASF related */ 6460 if (sc->bge_asf_mode & ASF_ENABLE) 6461 printf(" - ASF enable\n"); 6462 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6463 printf(" - ASF new handshake\n"); 6464 if (sc->bge_asf_mode & ASF_STACKUP) 6465 printf(" - ASF stackup\n"); 6466 } 6467 #endif /* BGE_DEBUG */ 6468 6469 static int 6470 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6471 { 6472 prop_dictionary_t dict; 6473 prop_data_t ea; 6474 6475 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6476 return 1; 6477 6478 dict = device_properties(sc->bge_dev); 6479 ea = prop_dictionary_get(dict, "mac-address"); 6480 if (ea != NULL) { 6481 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6482 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6483 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6484 return 0; 6485 } 6486 6487 return 1; 6488 } 6489 6490 static int 6491 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6492 { 6493 uint32_t mac_addr; 6494 6495 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6496 if ((mac_addr >> 16) == 0x484b) { 6497 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6498 ether_addr[1] = (uint8_t)mac_addr; 6499 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6500 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6501 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6502 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6503 ether_addr[5] = (uint8_t)mac_addr; 6504 return 0; 6505 } 6506 return 1; 6507 } 6508 6509 static int 6510 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6511 { 6512 int mac_offset = BGE_EE_MAC_OFFSET; 6513 6514 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6515 mac_offset = BGE_EE_MAC_OFFSET_5906; 6516 6517 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6518 ETHER_ADDR_LEN)); 6519 } 6520 6521 static int 6522 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6523 { 6524 6525 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6526 return 1; 6527 6528 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6529 ETHER_ADDR_LEN)); 6530 } 6531 6532 static int 6533 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6534 { 6535 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6536 /* NOTE: Order is critical */ 6537 bge_get_eaddr_fw, 6538 bge_get_eaddr_mem, 6539 bge_get_eaddr_nvram, 6540 bge_get_eaddr_eeprom, 6541 NULL 6542 }; 6543 const bge_eaddr_fcn_t *func; 6544 6545 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6546 if ((*func)(sc, eaddr) == 0) 6547 break; 6548 } 6549 return (*func == NULL ? ENXIO : 0); 6550 } 6551
Indexes created Tue Sep 23 07:09:52 GMT 2025