if_bge.c revision 1.323
1 /* $NetBSD: if_bge.c,v 1.323 2019/02/03 03:19:27 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.323 2019/02/03 03:19:27 mrg Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_can_use_msi(struct bge_softc *); 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static int bge_detach(device_t, int); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *m, bool); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 254 static int bge_miibus_writereg(device_t, int, int, uint16_t); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 /* 306 * The BCM5700 documentation seems to indicate that the hardware 307 * still has the Alteon vendor ID burned into it, though it 308 * should always be overridden by the value in the EEPROM. We'll 309 * check for it anyway. 310 */ 311 { PCI_VENDOR_ALTEON, 312 PCI_PRODUCT_ALTEON_BCM5700, 313 "Broadcom BCM5700 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTEON, 316 PCI_PRODUCT_ALTEON_BCM5701, 317 "Broadcom BCM5701 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_ALTIMA, 320 PCI_PRODUCT_ALTIMA_AC1000, 321 "Altima AC1000 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_ALTIMA, 324 PCI_PRODUCT_ALTIMA_AC1001, 325 "Altima AC1001 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_ALTIMA, 328 PCI_PRODUCT_ALTIMA_AC1003, 329 "Altima AC1003 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_ALTIMA, 332 PCI_PRODUCT_ALTIMA_AC9100, 333 "Altima AC9100 Gigabit Ethernet", 334 }, 335 { PCI_VENDOR_APPLE, 336 PCI_PRODUCT_APPLE_BCM5701, 337 "APPLE BCM5701 Gigabit Ethernet", 338 }, 339 { PCI_VENDOR_BROADCOM, 340 PCI_PRODUCT_BROADCOM_BCM5700, 341 "Broadcom BCM5700 Gigabit Ethernet", 342 }, 343 { PCI_VENDOR_BROADCOM, 344 PCI_PRODUCT_BROADCOM_BCM5701, 345 "Broadcom BCM5701 Gigabit Ethernet", 346 }, 347 { PCI_VENDOR_BROADCOM, 348 PCI_PRODUCT_BROADCOM_BCM5702, 349 "Broadcom BCM5702 Gigabit Ethernet", 350 }, 351 { PCI_VENDOR_BROADCOM, 352 PCI_PRODUCT_BROADCOM_BCM5702X, 353 "Broadcom BCM5702X Gigabit Ethernet" }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5703, 356 "Broadcom BCM5703 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5703X, 360 "Broadcom BCM5703X Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 364 "Broadcom BCM5703 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5704C, 368 "Broadcom BCM5704C Dual Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5704S, 372 "Broadcom BCM5704S Dual Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5705, 376 "Broadcom BCM5705 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5705F, 380 "Broadcom BCM5705F Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5705K, 384 "Broadcom BCM5705K Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5705M, 388 "Broadcom BCM5705M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 392 "Broadcom BCM5705M Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5714, 396 "Broadcom BCM5714 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5714S, 400 "Broadcom BCM5714S Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5715, 404 "Broadcom BCM5715 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5715S, 408 "Broadcom BCM5715S Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5717, 412 "Broadcom BCM5717 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5718, 416 "Broadcom BCM5718 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5719, 420 "Broadcom BCM5719 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5720, 424 "Broadcom BCM5720 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5721, 428 "Broadcom BCM5721 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5722, 432 "Broadcom BCM5722 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5723, 436 "Broadcom BCM5723 Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5750, 440 "Broadcom BCM5750 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5751, 444 "Broadcom BCM5751 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5751F, 448 "Broadcom BCM5751F Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5751M, 452 "Broadcom BCM5751M Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5752, 456 "Broadcom BCM5752 Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5752M, 460 "Broadcom BCM5752M Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5753, 464 "Broadcom BCM5753 Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5753F, 468 "Broadcom BCM5753F Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5753M, 472 "Broadcom BCM5753M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5754, 476 "Broadcom BCM5754 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5754M, 480 "Broadcom BCM5754M Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5755, 484 "Broadcom BCM5755 Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5755M, 488 "Broadcom BCM5755M Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5756, 492 "Broadcom BCM5756 Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5761, 496 "Broadcom BCM5761 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5761E, 500 "Broadcom BCM5761E Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5761S, 504 "Broadcom BCM5761S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5761SE, 508 "Broadcom BCM5761SE Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5764, 512 "Broadcom BCM5764 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5780, 516 "Broadcom BCM5780 Gigabit Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5780S, 520 "Broadcom BCM5780S Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5781, 524 "Broadcom BCM5781 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5782, 528 "Broadcom BCM5782 Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5784M, 532 "BCM5784M NetLink 1000baseT Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5785F, 536 "BCM5785F NetLink 10/100 Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5785G, 540 "BCM5785G NetLink 1000baseT Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5786, 544 "Broadcom BCM5786 Gigabit Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5787, 548 "Broadcom BCM5787 Gigabit Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5787F, 552 "Broadcom BCM5787F 10/100 Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5787M, 556 "Broadcom BCM5787M Gigabit Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM5788, 560 "Broadcom BCM5788 Gigabit Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM5789, 564 "Broadcom BCM5789 Gigabit Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM5901, 568 "Broadcom BCM5901 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM5901A2, 572 "Broadcom BCM5901A2 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM5903M, 576 "Broadcom BCM5903M Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM5906, 580 "Broadcom BCM5906 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM5906M, 584 "Broadcom BCM5906M Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57760, 588 "Broadcom BCM57760 Gigabit Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57761, 592 "Broadcom BCM57761 Gigabit Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57762, 596 "Broadcom BCM57762 Gigabit Ethernet", 597 }, 598 { PCI_VENDOR_BROADCOM, 599 PCI_PRODUCT_BROADCOM_BCM57765, 600 "Broadcom BCM57765 Gigabit Ethernet", 601 }, 602 { PCI_VENDOR_BROADCOM, 603 PCI_PRODUCT_BROADCOM_BCM57766, 604 "Broadcom BCM57766 Gigabit Ethernet", 605 }, 606 { PCI_VENDOR_BROADCOM, 607 PCI_PRODUCT_BROADCOM_BCM57780, 608 "Broadcom BCM57780 Gigabit Ethernet", 609 }, 610 { PCI_VENDOR_BROADCOM, 611 PCI_PRODUCT_BROADCOM_BCM57781, 612 "Broadcom BCM57781 Gigabit Ethernet", 613 }, 614 { PCI_VENDOR_BROADCOM, 615 PCI_PRODUCT_BROADCOM_BCM57782, 616 "Broadcom BCM57782 Gigabit Ethernet", 617 }, 618 { PCI_VENDOR_BROADCOM, 619 PCI_PRODUCT_BROADCOM_BCM57785, 620 "Broadcom BCM57785 Gigabit Ethernet", 621 }, 622 { PCI_VENDOR_BROADCOM, 623 PCI_PRODUCT_BROADCOM_BCM57786, 624 "Broadcom BCM57786 Gigabit Ethernet", 625 }, 626 { PCI_VENDOR_BROADCOM, 627 PCI_PRODUCT_BROADCOM_BCM57788, 628 "Broadcom BCM57788 Gigabit Ethernet", 629 }, 630 { PCI_VENDOR_BROADCOM, 631 PCI_PRODUCT_BROADCOM_BCM57790, 632 "Broadcom BCM57790 Gigabit Ethernet", 633 }, 634 { PCI_VENDOR_BROADCOM, 635 PCI_PRODUCT_BROADCOM_BCM57791, 636 "Broadcom BCM57791 Gigabit Ethernet", 637 }, 638 { PCI_VENDOR_BROADCOM, 639 PCI_PRODUCT_BROADCOM_BCM57795, 640 "Broadcom BCM57795 Gigabit Ethernet", 641 }, 642 { PCI_VENDOR_SCHNEIDERKOCH, 643 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 644 "SysKonnect SK-9Dx1 Gigabit Ethernet", 645 }, 646 { PCI_VENDOR_3COM, 647 PCI_PRODUCT_3COM_3C996, 648 "3Com 3c996 Gigabit Ethernet", 649 }, 650 { PCI_VENDOR_FUJITSU4, 651 PCI_PRODUCT_FUJITSU4_PW008GE4, 652 "Fujitsu PW008GE4 Gigabit Ethernet", 653 }, 654 { PCI_VENDOR_FUJITSU4, 655 PCI_PRODUCT_FUJITSU4_PW008GE5, 656 "Fujitsu PW008GE5 Gigabit Ethernet", 657 }, 658 { PCI_VENDOR_FUJITSU4, 659 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 660 "Fujitsu Primepower 250/450 Gigabit Ethernet", 661 }, 662 { 0, 663 0, 664 NULL }, 665 }; 666 667 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 668 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 669 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 670 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 671 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 672 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 673 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 674 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 675 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 676 677 static const struct bge_revision { 678 uint32_t br_chipid; 679 const char *br_name; 680 } bge_revisions[] = { 681 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 682 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 683 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 684 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 685 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 686 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 687 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 688 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 689 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 690 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 691 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 692 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 693 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 694 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 695 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 696 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 697 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 698 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 699 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 700 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 701 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 702 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 703 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 704 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 705 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 706 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 707 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 708 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 709 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 710 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 711 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 712 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 713 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 714 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 715 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 716 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 717 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 718 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 719 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 720 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 721 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 722 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 723 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 724 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 725 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 726 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 727 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 728 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 729 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 730 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 731 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 732 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 733 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 734 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 735 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 736 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 737 /* 5754 and 5787 share the same ASIC ID */ 738 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 739 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 740 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 741 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 742 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 743 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 744 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 745 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 746 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 747 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 748 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 749 750 { 0, NULL } 751 }; 752 753 /* 754 * Some defaults for major revisions, so that newer steppings 755 * that we don't know about have a shot at working. 756 */ 757 static const struct bge_revision bge_majorrevs[] = { 758 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 759 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 760 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 761 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 762 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 763 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 764 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 765 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 766 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 767 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 768 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 769 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 770 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 771 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 772 /* 5754 and 5787 share the same ASIC ID */ 773 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 774 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 775 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 776 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 777 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 778 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 779 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 780 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 781 782 { 0, NULL } 783 }; 784 785 static int bge_allow_asf = 1; 786 787 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 788 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 789 790 static uint32_t 791 bge_readmem_ind(struct bge_softc *sc, int off) 792 { 793 pcireg_t val; 794 795 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 796 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 797 return 0; 798 799 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 800 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 801 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 802 return val; 803 } 804 805 static void 806 bge_writemem_ind(struct bge_softc *sc, int off, int val) 807 { 808 809 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 810 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 811 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 812 } 813 814 /* 815 * PCI Express only 816 */ 817 static void 818 bge_set_max_readrq(struct bge_softc *sc) 819 { 820 pcireg_t val; 821 822 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 823 + PCIE_DCSR); 824 val &= ~PCIE_DCSR_MAX_READ_REQ; 825 switch (sc->bge_expmrq) { 826 case 2048: 827 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 828 break; 829 case 4096: 830 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 831 break; 832 default: 833 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 834 break; 835 } 836 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 837 + PCIE_DCSR, val); 838 } 839 840 #ifdef notdef 841 static uint32_t 842 bge_readreg_ind(struct bge_softc *sc, int off) 843 { 844 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 845 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 846 } 847 #endif 848 849 static void 850 bge_writereg_ind(struct bge_softc *sc, int off, int val) 851 { 852 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 853 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 854 } 855 856 static void 857 bge_writemem_direct(struct bge_softc *sc, int off, int val) 858 { 859 CSR_WRITE_4(sc, off, val); 860 } 861 862 static void 863 bge_writembx(struct bge_softc *sc, int off, int val) 864 { 865 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 866 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 867 868 CSR_WRITE_4(sc, off, val); 869 } 870 871 static void 872 bge_writembx_flush(struct bge_softc *sc, int off, int val) 873 { 874 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 875 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 876 877 CSR_WRITE_4_FLUSH(sc, off, val); 878 } 879 880 /* 881 * Clear all stale locks and select the lock for this driver instance. 882 */ 883 void 884 bge_ape_lock_init(struct bge_softc *sc) 885 { 886 struct pci_attach_args *pa = &(sc->bge_pa); 887 uint32_t bit, regbase; 888 int i; 889 890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 891 regbase = BGE_APE_LOCK_GRANT; 892 else 893 regbase = BGE_APE_PER_LOCK_GRANT; 894 895 /* Clear any stale locks. */ 896 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 897 switch (i) { 898 case BGE_APE_LOCK_PHY0: 899 case BGE_APE_LOCK_PHY1: 900 case BGE_APE_LOCK_PHY2: 901 case BGE_APE_LOCK_PHY3: 902 bit = BGE_APE_LOCK_GRANT_DRIVER0; 903 break; 904 default: 905 if (pa->pa_function == 0) 906 bit = BGE_APE_LOCK_GRANT_DRIVER0; 907 else 908 bit = (1 << pa->pa_function); 909 } 910 APE_WRITE_4(sc, regbase + 4 * i, bit); 911 } 912 913 /* Select the PHY lock based on the device's function number. */ 914 switch (pa->pa_function) { 915 case 0: 916 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 917 break; 918 case 1: 919 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 920 break; 921 case 2: 922 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 923 break; 924 case 3: 925 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 926 break; 927 default: 928 printf("%s: PHY lock not supported on function\n", 929 device_xname(sc->bge_dev)); 930 break; 931 } 932 } 933 934 /* 935 * Check for APE firmware, set flags, and print version info. 936 */ 937 void 938 bge_ape_read_fw_ver(struct bge_softc *sc) 939 { 940 const char *fwtype; 941 uint32_t apedata, features; 942 943 /* Check for a valid APE signature in shared memory. */ 944 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 945 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 946 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 947 return; 948 } 949 950 /* Check if APE firmware is running. */ 951 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 952 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 953 printf("%s: APE signature found but FW status not ready! " 954 "0x%08x\n", device_xname(sc->bge_dev), apedata); 955 return; 956 } 957 958 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 959 960 /* Fetch the APE firwmare type and version. */ 961 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 962 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 963 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 964 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 965 fwtype = "NCSI"; 966 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 967 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 968 fwtype = "DASH"; 969 } else 970 fwtype = "UNKN"; 971 972 /* Print the APE firmware version. */ 973 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 974 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 975 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 976 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 977 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 978 } 979 980 int 981 bge_ape_lock(struct bge_softc *sc, int locknum) 982 { 983 struct pci_attach_args *pa = &(sc->bge_pa); 984 uint32_t bit, gnt, req, status; 985 int i, off; 986 987 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 988 return (0); 989 990 /* Lock request/grant registers have different bases. */ 991 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 992 req = BGE_APE_LOCK_REQ; 993 gnt = BGE_APE_LOCK_GRANT; 994 } else { 995 req = BGE_APE_PER_LOCK_REQ; 996 gnt = BGE_APE_PER_LOCK_GRANT; 997 } 998 999 off = 4 * locknum; 1000 1001 switch (locknum) { 1002 case BGE_APE_LOCK_GPIO: 1003 /* Lock required when using GPIO. */ 1004 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1005 return (0); 1006 if (pa->pa_function == 0) 1007 bit = BGE_APE_LOCK_REQ_DRIVER0; 1008 else 1009 bit = (1 << pa->pa_function); 1010 break; 1011 case BGE_APE_LOCK_GRC: 1012 /* Lock required to reset the device. */ 1013 if (pa->pa_function == 0) 1014 bit = BGE_APE_LOCK_REQ_DRIVER0; 1015 else 1016 bit = (1 << pa->pa_function); 1017 break; 1018 case BGE_APE_LOCK_MEM: 1019 /* Lock required when accessing certain APE memory. */ 1020 if (pa->pa_function == 0) 1021 bit = BGE_APE_LOCK_REQ_DRIVER0; 1022 else 1023 bit = (1 << pa->pa_function); 1024 break; 1025 case BGE_APE_LOCK_PHY0: 1026 case BGE_APE_LOCK_PHY1: 1027 case BGE_APE_LOCK_PHY2: 1028 case BGE_APE_LOCK_PHY3: 1029 /* Lock required when accessing PHYs. */ 1030 bit = BGE_APE_LOCK_REQ_DRIVER0; 1031 break; 1032 default: 1033 return (EINVAL); 1034 } 1035 1036 /* Request a lock. */ 1037 APE_WRITE_4_FLUSH(sc, req + off, bit); 1038 1039 /* Wait up to 1 second to acquire lock. */ 1040 for (i = 0; i < 20000; i++) { 1041 status = APE_READ_4(sc, gnt + off); 1042 if (status == bit) 1043 break; 1044 DELAY(50); 1045 } 1046 1047 /* Handle any errors. */ 1048 if (status != bit) { 1049 printf("%s: APE lock %d request failed! " 1050 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 1051 device_xname(sc->bge_dev), 1052 locknum, req + off, bit & 0xFFFF, gnt + off, 1053 status & 0xFFFF); 1054 /* Revoke the lock request. */ 1055 APE_WRITE_4(sc, gnt + off, bit); 1056 return (EBUSY); 1057 } 1058 1059 return (0); 1060 } 1061 1062 void 1063 bge_ape_unlock(struct bge_softc *sc, int locknum) 1064 { 1065 struct pci_attach_args *pa = &(sc->bge_pa); 1066 uint32_t bit, gnt; 1067 int off; 1068 1069 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1070 return; 1071 1072 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1073 gnt = BGE_APE_LOCK_GRANT; 1074 else 1075 gnt = BGE_APE_PER_LOCK_GRANT; 1076 1077 off = 4 * locknum; 1078 1079 switch (locknum) { 1080 case BGE_APE_LOCK_GPIO: 1081 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1082 return; 1083 if (pa->pa_function == 0) 1084 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1085 else 1086 bit = (1 << pa->pa_function); 1087 break; 1088 case BGE_APE_LOCK_GRC: 1089 if (pa->pa_function == 0) 1090 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1091 else 1092 bit = (1 << pa->pa_function); 1093 break; 1094 case BGE_APE_LOCK_MEM: 1095 if (pa->pa_function == 0) 1096 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1097 else 1098 bit = (1 << pa->pa_function); 1099 break; 1100 case BGE_APE_LOCK_PHY0: 1101 case BGE_APE_LOCK_PHY1: 1102 case BGE_APE_LOCK_PHY2: 1103 case BGE_APE_LOCK_PHY3: 1104 bit = BGE_APE_LOCK_GRANT_DRIVER0; 1105 break; 1106 default: 1107 return; 1108 } 1109 1110 /* Write and flush for consecutive bge_ape_lock() */ 1111 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 1112 } 1113 1114 /* 1115 * Send an event to the APE firmware. 1116 */ 1117 void 1118 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 1119 { 1120 uint32_t apedata; 1121 int i; 1122 1123 /* NCSI does not support APE events. */ 1124 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1125 return; 1126 1127 /* Wait up to 1ms for APE to service previous event. */ 1128 for (i = 10; i > 0; i--) { 1129 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 1130 break; 1131 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 1132 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 1133 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 1134 BGE_APE_EVENT_STATUS_EVENT_PENDING); 1135 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1136 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 1137 break; 1138 } 1139 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 1140 DELAY(100); 1141 } 1142 if (i == 0) { 1143 printf("%s: APE event 0x%08x send timed out\n", 1144 device_xname(sc->bge_dev), event); 1145 } 1146 } 1147 1148 void 1149 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 1150 { 1151 uint32_t apedata, event; 1152 1153 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 1154 return; 1155 1156 switch (kind) { 1157 case BGE_RESET_START: 1158 /* If this is the first load, clear the load counter. */ 1159 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 1160 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 1161 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 1162 else { 1163 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 1164 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 1165 } 1166 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 1167 BGE_APE_HOST_SEG_SIG_MAGIC); 1168 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 1169 BGE_APE_HOST_SEG_LEN_MAGIC); 1170 1171 /* Add some version info if bge(4) supports it. */ 1172 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 1173 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 1174 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 1175 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 1176 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 1177 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 1178 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1179 BGE_APE_HOST_DRVR_STATE_START); 1180 event = BGE_APE_EVENT_STATUS_STATE_START; 1181 break; 1182 case BGE_RESET_SHUTDOWN: 1183 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 1184 BGE_APE_HOST_DRVR_STATE_UNLOAD); 1185 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 1186 break; 1187 case BGE_RESET_SUSPEND: 1188 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 1189 break; 1190 default: 1191 return; 1192 } 1193 1194 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 1195 BGE_APE_EVENT_STATUS_STATE_CHNGE); 1196 } 1197 1198 static uint8_t 1199 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1200 { 1201 uint32_t access, byte = 0; 1202 int i; 1203 1204 /* Lock. */ 1205 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1206 for (i = 0; i < 8000; i++) { 1207 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1208 break; 1209 DELAY(20); 1210 } 1211 if (i == 8000) 1212 return 1; 1213 1214 /* Enable access. */ 1215 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1216 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1217 1218 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1219 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1220 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1221 DELAY(10); 1222 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1223 DELAY(10); 1224 break; 1225 } 1226 } 1227 1228 if (i == BGE_TIMEOUT * 10) { 1229 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 1230 return 1; 1231 } 1232 1233 /* Get result. */ 1234 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1235 1236 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1237 1238 /* Disable access. */ 1239 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1240 1241 /* Unlock. */ 1242 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1243 1244 return 0; 1245 } 1246 1247 /* 1248 * Read a sequence of bytes from NVRAM. 1249 */ 1250 static int 1251 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1252 { 1253 int error = 0, i; 1254 uint8_t byte = 0; 1255 1256 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1257 return 1; 1258 1259 for (i = 0; i < cnt; i++) { 1260 error = bge_nvram_getbyte(sc, off + i, &byte); 1261 if (error) 1262 break; 1263 *(dest + i) = byte; 1264 } 1265 1266 return (error ? 1 : 0); 1267 } 1268 1269 /* 1270 * Read a byte of data stored in the EEPROM at address 'addr.' The 1271 * BCM570x supports both the traditional bitbang interface and an 1272 * auto access interface for reading the EEPROM. We use the auto 1273 * access method. 1274 */ 1275 static uint8_t 1276 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1277 { 1278 int i; 1279 uint32_t byte = 0; 1280 1281 /* 1282 * Enable use of auto EEPROM access so we can avoid 1283 * having to use the bitbang method. 1284 */ 1285 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1286 1287 /* Reset the EEPROM, load the clock period. */ 1288 CSR_WRITE_4(sc, BGE_EE_ADDR, 1289 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1290 DELAY(20); 1291 1292 /* Issue the read EEPROM command. */ 1293 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1294 1295 /* Wait for completion */ 1296 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1297 DELAY(10); 1298 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1299 break; 1300 } 1301 1302 if (i == BGE_TIMEOUT * 10) { 1303 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1304 return 1; 1305 } 1306 1307 /* Get result. */ 1308 byte = CSR_READ_4(sc, BGE_EE_DATA); 1309 1310 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1311 1312 return 0; 1313 } 1314 1315 /* 1316 * Read a sequence of bytes from the EEPROM. 1317 */ 1318 static int 1319 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1320 { 1321 int error = 0, i; 1322 uint8_t byte = 0; 1323 char *dest = destv; 1324 1325 for (i = 0; i < cnt; i++) { 1326 error = bge_eeprom_getbyte(sc, off + i, &byte); 1327 if (error) 1328 break; 1329 *(dest + i) = byte; 1330 } 1331 1332 return (error ? 1 : 0); 1333 } 1334 1335 static int 1336 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1337 { 1338 struct bge_softc *sc = device_private(dev); 1339 uint32_t data; 1340 uint32_t autopoll; 1341 int rv = 0; 1342 int i; 1343 1344 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1345 return -1; 1346 1347 /* Reading with autopolling on may trigger PCI errors */ 1348 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1349 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1350 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1351 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1352 DELAY(80); 1353 } 1354 1355 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1356 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1357 1358 for (i = 0; i < BGE_TIMEOUT; i++) { 1359 delay(10); 1360 data = CSR_READ_4(sc, BGE_MI_COMM); 1361 if (!(data & BGE_MICOMM_BUSY)) { 1362 DELAY(5); 1363 data = CSR_READ_4(sc, BGE_MI_COMM); 1364 break; 1365 } 1366 } 1367 1368 if (i == BGE_TIMEOUT) { 1369 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1370 rv = ETIMEDOUT; 1371 } else if ((data & BGE_MICOMM_READFAIL) != 0) 1372 rv = -1; 1373 else 1374 *val = data & BGE_MICOMM_DATA; 1375 1376 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1377 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1378 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1379 DELAY(80); 1380 } 1381 1382 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1383 1384 return rv; 1385 } 1386 1387 static int 1388 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1389 { 1390 struct bge_softc *sc = device_private(dev); 1391 uint32_t autopoll; 1392 int i; 1393 1394 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1395 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1396 return 0; 1397 1398 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1399 return -1; 1400 1401 /* Reading with autopolling on may trigger PCI errors */ 1402 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1403 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1404 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1405 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1406 DELAY(80); 1407 } 1408 1409 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1410 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1411 1412 for (i = 0; i < BGE_TIMEOUT; i++) { 1413 delay(10); 1414 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1415 delay(5); 1416 CSR_READ_4(sc, BGE_MI_COMM); 1417 break; 1418 } 1419 } 1420 1421 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1422 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1423 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1424 delay(80); 1425 } 1426 1427 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1428 1429 if (i == BGE_TIMEOUT) { 1430 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1431 return ETIMEDOUT; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static void 1438 bge_miibus_statchg(struct ifnet *ifp) 1439 { 1440 struct bge_softc *sc = ifp->if_softc; 1441 struct mii_data *mii = &sc->bge_mii; 1442 uint32_t mac_mode, rx_mode, tx_mode; 1443 1444 /* 1445 * Get flow control negotiation result. 1446 */ 1447 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1448 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1449 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1450 1451 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1452 mii->mii_media_status & IFM_ACTIVE && 1453 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1454 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1455 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1456 (!(mii->mii_media_status & IFM_ACTIVE) || 1457 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1458 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1459 1460 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1461 return; 1462 1463 /* Set the port mode (MII/GMII) to match the link speed. */ 1464 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1465 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1466 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1467 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1468 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1469 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1470 mac_mode |= BGE_PORTMODE_GMII; 1471 else 1472 mac_mode |= BGE_PORTMODE_MII; 1473 1474 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1475 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1476 if ((mii->mii_media_active & IFM_FDX) != 0) { 1477 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1478 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1479 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1480 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1481 } else 1482 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1483 1484 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1485 DELAY(40); 1486 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1487 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1488 } 1489 1490 /* 1491 * Update rx threshold levels to values in a particular slot 1492 * of the interrupt-mitigation table bge_rx_threshes. 1493 */ 1494 static void 1495 bge_set_thresh(struct ifnet *ifp, int lvl) 1496 { 1497 struct bge_softc *sc = ifp->if_softc; 1498 int s; 1499 1500 /* For now, just save the new Rx-intr thresholds and record 1501 * that a threshold update is pending. Updating the hardware 1502 * registers here (even at splhigh()) is observed to 1503 * occasionaly cause glitches where Rx-interrupts are not 1504 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1505 */ 1506 s = splnet(); 1507 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1508 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1509 sc->bge_pending_rxintr_change = 1; 1510 splx(s); 1511 } 1512 1513 1514 /* 1515 * Update Rx thresholds of all bge devices 1516 */ 1517 static void 1518 bge_update_all_threshes(int lvl) 1519 { 1520 struct ifnet *ifp; 1521 const char * const namebuf = "bge"; 1522 int namelen; 1523 int s; 1524 1525 if (lvl < 0) 1526 lvl = 0; 1527 else if (lvl >= NBGE_RX_THRESH) 1528 lvl = NBGE_RX_THRESH - 1; 1529 1530 namelen = strlen(namebuf); 1531 /* 1532 * Now search all the interfaces for this name/number 1533 */ 1534 s = pserialize_read_enter(); 1535 IFNET_READER_FOREACH(ifp) { 1536 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1537 continue; 1538 /* We got a match: update if doing auto-threshold-tuning */ 1539 if (bge_auto_thresh) 1540 bge_set_thresh(ifp, lvl); 1541 } 1542 pserialize_read_exit(s); 1543 } 1544 1545 /* 1546 * Handle events that have triggered interrupts. 1547 */ 1548 static void 1549 bge_handle_events(struct bge_softc *sc) 1550 { 1551 1552 return; 1553 } 1554 1555 /* 1556 * Memory management for jumbo frames. 1557 */ 1558 1559 static int 1560 bge_alloc_jumbo_mem(struct bge_softc *sc) 1561 { 1562 char *ptr, *kva; 1563 bus_dma_segment_t seg; 1564 int i, rseg, state, error; 1565 struct bge_jpool_entry *entry; 1566 1567 state = error = 0; 1568 1569 /* Grab a big chunk o' storage. */ 1570 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1571 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1572 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1573 return ENOBUFS; 1574 } 1575 1576 state = 1; 1577 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1578 BUS_DMA_NOWAIT)) { 1579 aprint_error_dev(sc->bge_dev, 1580 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1581 error = ENOBUFS; 1582 goto out; 1583 } 1584 1585 state = 2; 1586 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1587 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1588 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1589 error = ENOBUFS; 1590 goto out; 1591 } 1592 1593 state = 3; 1594 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1595 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1596 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1597 error = ENOBUFS; 1598 goto out; 1599 } 1600 1601 state = 4; 1602 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1603 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1604 1605 SLIST_INIT(&sc->bge_jfree_listhead); 1606 SLIST_INIT(&sc->bge_jinuse_listhead); 1607 1608 /* 1609 * Now divide it up into 9K pieces and save the addresses 1610 * in an array. 1611 */ 1612 ptr = sc->bge_cdata.bge_jumbo_buf; 1613 for (i = 0; i < BGE_JSLOTS; i++) { 1614 sc->bge_cdata.bge_jslots[i] = ptr; 1615 ptr += BGE_JLEN; 1616 entry = malloc(sizeof(struct bge_jpool_entry), 1617 M_DEVBUF, M_NOWAIT); 1618 if (entry == NULL) { 1619 aprint_error_dev(sc->bge_dev, 1620 "no memory for jumbo buffer queue!\n"); 1621 error = ENOBUFS; 1622 goto out; 1623 } 1624 entry->slot = i; 1625 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1626 entry, jpool_entries); 1627 } 1628 out: 1629 if (error != 0) { 1630 switch (state) { 1631 case 4: 1632 bus_dmamap_unload(sc->bge_dmatag, 1633 sc->bge_cdata.bge_rx_jumbo_map); 1634 /* FALLTHROUGH */ 1635 case 3: 1636 bus_dmamap_destroy(sc->bge_dmatag, 1637 sc->bge_cdata.bge_rx_jumbo_map); 1638 /* FALLTHROUGH */ 1639 case 2: 1640 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1641 /* FALLTHROUGH */ 1642 case 1: 1643 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1644 break; 1645 default: 1646 break; 1647 } 1648 } 1649 1650 return error; 1651 } 1652 1653 /* 1654 * Allocate a jumbo buffer. 1655 */ 1656 static void * 1657 bge_jalloc(struct bge_softc *sc) 1658 { 1659 struct bge_jpool_entry *entry; 1660 1661 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1662 1663 if (entry == NULL) { 1664 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1665 return NULL; 1666 } 1667 1668 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1669 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1670 return (sc->bge_cdata.bge_jslots[entry->slot]); 1671 } 1672 1673 /* 1674 * Release a jumbo buffer. 1675 */ 1676 static void 1677 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1678 { 1679 struct bge_jpool_entry *entry; 1680 struct bge_softc *sc; 1681 int i, s; 1682 1683 /* Extract the softc struct pointer. */ 1684 sc = (struct bge_softc *)arg; 1685 1686 if (sc == NULL) 1687 panic("bge_jfree: can't find softc pointer!"); 1688 1689 /* calculate the slot this buffer belongs to */ 1690 1691 i = ((char *)buf 1692 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1693 1694 if ((i < 0) || (i >= BGE_JSLOTS)) 1695 panic("bge_jfree: asked to free buffer that we don't manage!"); 1696 1697 s = splvm(); 1698 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1699 if (entry == NULL) 1700 panic("bge_jfree: buffer not in use!"); 1701 entry->slot = i; 1702 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1703 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1704 1705 if (__predict_true(m != NULL)) 1706 pool_cache_put(mb_cache, m); 1707 splx(s); 1708 } 1709 1710 1711 /* 1712 * Initialize a standard receive ring descriptor. 1713 */ 1714 static int 1715 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1716 bus_dmamap_t dmamap) 1717 { 1718 struct mbuf *m_new = NULL; 1719 struct bge_rx_bd *r; 1720 int error; 1721 1722 if (dmamap == NULL) 1723 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1724 1725 if (dmamap == NULL) { 1726 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1727 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1728 if (error != 0) 1729 return error; 1730 } 1731 1732 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1733 1734 if (m == NULL) { 1735 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1736 if (m_new == NULL) 1737 return ENOBUFS; 1738 1739 MCLGET(m_new, M_DONTWAIT); 1740 if (!(m_new->m_flags & M_EXT)) { 1741 m_freem(m_new); 1742 return ENOBUFS; 1743 } 1744 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1745 1746 } else { 1747 m_new = m; 1748 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1749 m_new->m_data = m_new->m_ext.ext_buf; 1750 } 1751 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1752 m_adj(m_new, ETHER_ALIGN); 1753 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1754 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1755 m_freem(m_new); 1756 return ENOBUFS; 1757 } 1758 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1759 BUS_DMASYNC_PREREAD); 1760 1761 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1762 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1763 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1764 r->bge_flags = BGE_RXBDFLAG_END; 1765 r->bge_len = m_new->m_len; 1766 r->bge_idx = i; 1767 1768 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1769 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1770 i * sizeof (struct bge_rx_bd), 1771 sizeof (struct bge_rx_bd), 1772 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1773 1774 return 0; 1775 } 1776 1777 /* 1778 * Initialize a jumbo receive ring descriptor. This allocates 1779 * a jumbo buffer from the pool managed internally by the driver. 1780 */ 1781 static int 1782 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1783 { 1784 struct mbuf *m_new = NULL; 1785 struct bge_rx_bd *r; 1786 void *buf = NULL; 1787 1788 if (m == NULL) { 1789 1790 /* Allocate the mbuf. */ 1791 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1792 if (m_new == NULL) 1793 return ENOBUFS; 1794 1795 /* Allocate the jumbo buffer */ 1796 buf = bge_jalloc(sc); 1797 if (buf == NULL) { 1798 m_freem(m_new); 1799 aprint_error_dev(sc->bge_dev, 1800 "jumbo allocation failed -- packet dropped!\n"); 1801 return ENOBUFS; 1802 } 1803 1804 /* Attach the buffer to the mbuf. */ 1805 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1806 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1807 bge_jfree, sc); 1808 m_new->m_flags |= M_EXT_RW; 1809 } else { 1810 m_new = m; 1811 buf = m_new->m_data = m_new->m_ext.ext_buf; 1812 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1813 } 1814 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1815 m_adj(m_new, ETHER_ALIGN); 1816 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1817 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1818 BUS_DMASYNC_PREREAD); 1819 /* Set up the descriptor. */ 1820 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1821 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1822 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1823 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1824 r->bge_len = m_new->m_len; 1825 r->bge_idx = i; 1826 1827 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1828 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1829 i * sizeof (struct bge_rx_bd), 1830 sizeof (struct bge_rx_bd), 1831 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1832 1833 return 0; 1834 } 1835 1836 /* 1837 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1838 * that's 1MB or memory, which is a lot. For now, we fill only the first 1839 * 256 ring entries and hope that our CPU is fast enough to keep up with 1840 * the NIC. 1841 */ 1842 static int 1843 bge_init_rx_ring_std(struct bge_softc *sc) 1844 { 1845 int i; 1846 1847 if (sc->bge_flags & BGEF_RXRING_VALID) 1848 return 0; 1849 1850 for (i = 0; i < BGE_SSLOTS; i++) { 1851 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1852 return ENOBUFS; 1853 } 1854 1855 sc->bge_std = i - 1; 1856 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1857 1858 sc->bge_flags |= BGEF_RXRING_VALID; 1859 1860 return 0; 1861 } 1862 1863 static void 1864 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1865 { 1866 int i; 1867 1868 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1869 return; 1870 1871 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1872 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1873 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1874 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1875 if (disable) { 1876 bus_dmamap_destroy(sc->bge_dmatag, 1877 sc->bge_cdata.bge_rx_std_map[i]); 1878 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1879 } 1880 } 1881 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1882 sizeof(struct bge_rx_bd)); 1883 } 1884 1885 sc->bge_flags &= ~BGEF_RXRING_VALID; 1886 } 1887 1888 static int 1889 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1890 { 1891 int i; 1892 volatile struct bge_rcb *rcb; 1893 1894 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1895 return 0; 1896 1897 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1898 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1899 return ENOBUFS; 1900 } 1901 1902 sc->bge_jumbo = i - 1; 1903 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1904 1905 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1906 rcb->bge_maxlen_flags = 0; 1907 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1908 1909 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1910 1911 return 0; 1912 } 1913 1914 static void 1915 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1916 { 1917 int i; 1918 1919 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1920 return; 1921 1922 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1923 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1924 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1925 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1926 } 1927 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1928 sizeof(struct bge_rx_bd)); 1929 } 1930 1931 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1932 } 1933 1934 static void 1935 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1936 { 1937 int i; 1938 struct txdmamap_pool_entry *dma; 1939 1940 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1941 return; 1942 1943 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1944 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1945 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1946 sc->bge_cdata.bge_tx_chain[i] = NULL; 1947 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1948 link); 1949 sc->txdma[i] = 0; 1950 } 1951 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1952 sizeof(struct bge_tx_bd)); 1953 } 1954 1955 if (disable) { 1956 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1957 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1958 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1959 if (sc->bge_dma64) { 1960 bus_dmamap_destroy(sc->bge_dmatag32, 1961 dma->dmamap32); 1962 } 1963 free(dma, M_DEVBUF); 1964 } 1965 SLIST_INIT(&sc->txdma_list); 1966 } 1967 1968 sc->bge_flags &= ~BGEF_TXRING_VALID; 1969 } 1970 1971 static int 1972 bge_init_tx_ring(struct bge_softc *sc) 1973 { 1974 struct ifnet *ifp = &sc->ethercom.ec_if; 1975 int i; 1976 bus_dmamap_t dmamap, dmamap32; 1977 bus_size_t maxsegsz; 1978 struct txdmamap_pool_entry *dma; 1979 1980 if (sc->bge_flags & BGEF_TXRING_VALID) 1981 return 0; 1982 1983 sc->bge_txcnt = 0; 1984 sc->bge_tx_saved_considx = 0; 1985 1986 /* Initialize transmit producer index for host-memory send ring. */ 1987 sc->bge_tx_prodidx = 0; 1988 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1989 /* 5700 b2 errata */ 1990 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1991 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1992 1993 /* NIC-memory send ring not used; initialize to zero. */ 1994 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1995 /* 5700 b2 errata */ 1996 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1997 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1998 1999 /* Limit DMA segment size for some chips */ 2000 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 2001 (ifp->if_mtu <= ETHERMTU)) 2002 maxsegsz = 2048; 2003 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2004 maxsegsz = 4096; 2005 else 2006 maxsegsz = ETHER_MAX_LEN_JUMBO; 2007 2008 if (SLIST_FIRST(&sc->txdma_list) != NULL) 2009 goto alloc_done; 2010 2011 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2012 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 2013 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2014 &dmamap)) 2015 return ENOBUFS; 2016 if (dmamap == NULL) 2017 panic("dmamap NULL in bge_init_tx_ring"); 2018 if (sc->bge_dma64) { 2019 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 2020 BGE_NTXSEG, maxsegsz, 0, 2021 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2022 &dmamap32)) { 2023 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2024 return ENOBUFS; 2025 } 2026 if (dmamap32 == NULL) 2027 panic("dmamap32 NULL in bge_init_tx_ring"); 2028 } else 2029 dmamap32 = dmamap; 2030 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 2031 if (dma == NULL) { 2032 aprint_error_dev(sc->bge_dev, 2033 "can't alloc txdmamap_pool_entry\n"); 2034 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 2035 if (sc->bge_dma64) 2036 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 2037 return ENOMEM; 2038 } 2039 dma->dmamap = dmamap; 2040 dma->dmamap32 = dmamap32; 2041 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2042 } 2043 alloc_done: 2044 sc->bge_flags |= BGEF_TXRING_VALID; 2045 2046 return 0; 2047 } 2048 2049 static void 2050 bge_setmulti(struct bge_softc *sc) 2051 { 2052 struct ethercom *ac = &sc->ethercom; 2053 struct ifnet *ifp = &ac->ec_if; 2054 struct ether_multi *enm; 2055 struct ether_multistep step; 2056 uint32_t hashes[4] = { 0, 0, 0, 0 }; 2057 uint32_t h; 2058 int i; 2059 2060 if (ifp->if_flags & IFF_PROMISC) 2061 goto allmulti; 2062 2063 /* Now program new ones. */ 2064 ETHER_FIRST_MULTI(step, ac, enm); 2065 while (enm != NULL) { 2066 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2067 /* 2068 * We must listen to a range of multicast addresses. 2069 * For now, just accept all multicasts, rather than 2070 * trying to set only those filter bits needed to match 2071 * the range. (At this time, the only use of address 2072 * ranges is for IP multicast routing, for which the 2073 * range is big enough to require all bits set.) 2074 */ 2075 goto allmulti; 2076 } 2077 2078 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2079 2080 /* Just want the 7 least-significant bits. */ 2081 h &= 0x7f; 2082 2083 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 2084 ETHER_NEXT_MULTI(step, enm); 2085 } 2086 2087 ifp->if_flags &= ~IFF_ALLMULTI; 2088 goto setit; 2089 2090 allmulti: 2091 ifp->if_flags |= IFF_ALLMULTI; 2092 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 2093 2094 setit: 2095 for (i = 0; i < 4; i++) 2096 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 2097 } 2098 2099 static void 2100 bge_sig_pre_reset(struct bge_softc *sc, int type) 2101 { 2102 2103 /* 2104 * Some chips don't like this so only do this if ASF is enabled 2105 */ 2106 if (sc->bge_asf_mode) 2107 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 2108 2109 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2110 switch (type) { 2111 case BGE_RESET_START: 2112 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2113 BGE_FW_DRV_STATE_START); 2114 break; 2115 case BGE_RESET_SHUTDOWN: 2116 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2117 BGE_FW_DRV_STATE_UNLOAD); 2118 break; 2119 case BGE_RESET_SUSPEND: 2120 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2121 BGE_FW_DRV_STATE_SUSPEND); 2122 break; 2123 } 2124 } 2125 2126 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 2127 bge_ape_driver_state_change(sc, type); 2128 } 2129 2130 static void 2131 bge_sig_post_reset(struct bge_softc *sc, int type) 2132 { 2133 2134 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 2135 switch (type) { 2136 case BGE_RESET_START: 2137 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2138 BGE_FW_DRV_STATE_START_DONE); 2139 /* START DONE */ 2140 break; 2141 case BGE_RESET_SHUTDOWN: 2142 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2143 BGE_FW_DRV_STATE_UNLOAD_DONE); 2144 break; 2145 } 2146 } 2147 2148 if (type == BGE_RESET_SHUTDOWN) 2149 bge_ape_driver_state_change(sc, type); 2150 } 2151 2152 static void 2153 bge_sig_legacy(struct bge_softc *sc, int type) 2154 { 2155 2156 if (sc->bge_asf_mode) { 2157 switch (type) { 2158 case BGE_RESET_START: 2159 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2160 BGE_FW_DRV_STATE_START); 2161 break; 2162 case BGE_RESET_SHUTDOWN: 2163 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 2164 BGE_FW_DRV_STATE_UNLOAD); 2165 break; 2166 } 2167 } 2168 } 2169 2170 static void 2171 bge_wait_for_event_ack(struct bge_softc *sc) 2172 { 2173 int i; 2174 2175 /* wait up to 2500usec */ 2176 for (i = 0; i < 250; i++) { 2177 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 2178 BGE_RX_CPU_DRV_EVENT)) 2179 break; 2180 DELAY(10); 2181 } 2182 } 2183 2184 static void 2185 bge_stop_fw(struct bge_softc *sc) 2186 { 2187 2188 if (sc->bge_asf_mode) { 2189 bge_wait_for_event_ack(sc); 2190 2191 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 2192 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 2193 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 2194 2195 bge_wait_for_event_ack(sc); 2196 } 2197 } 2198 2199 static int 2200 bge_poll_fw(struct bge_softc *sc) 2201 { 2202 uint32_t val; 2203 int i; 2204 2205 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2206 for (i = 0; i < BGE_TIMEOUT; i++) { 2207 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2208 if (val & BGE_VCPU_STATUS_INIT_DONE) 2209 break; 2210 DELAY(100); 2211 } 2212 if (i >= BGE_TIMEOUT) { 2213 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2214 return -1; 2215 } 2216 } else { 2217 /* 2218 * Poll the value location we just wrote until 2219 * we see the 1's complement of the magic number. 2220 * This indicates that the firmware initialization 2221 * is complete. 2222 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2223 */ 2224 for (i = 0; i < BGE_TIMEOUT; i++) { 2225 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2226 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2227 break; 2228 DELAY(10); 2229 } 2230 2231 if ((i >= BGE_TIMEOUT) 2232 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2233 aprint_error_dev(sc->bge_dev, 2234 "firmware handshake timed out, val = %x\n", val); 2235 return -1; 2236 } 2237 } 2238 2239 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2240 /* tg3 says we have to wait extra time */ 2241 delay(10 * 1000); 2242 } 2243 2244 return 0; 2245 } 2246 2247 int 2248 bge_phy_addr(struct bge_softc *sc) 2249 { 2250 struct pci_attach_args *pa = &(sc->bge_pa); 2251 int phy_addr = 1; 2252 2253 /* 2254 * PHY address mapping for various devices. 2255 * 2256 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2257 * ---------+-------+-------+-------+-------+ 2258 * BCM57XX | 1 | X | X | X | 2259 * BCM5704 | 1 | X | 1 | X | 2260 * BCM5717 | 1 | 8 | 2 | 9 | 2261 * BCM5719 | 1 | 8 | 2 | 9 | 2262 * BCM5720 | 1 | 8 | 2 | 9 | 2263 * 2264 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2265 * ---------+-------+-------+-------+-------+ 2266 * BCM57XX | X | X | X | X | 2267 * BCM5704 | X | X | X | X | 2268 * BCM5717 | X | X | X | X | 2269 * BCM5719 | 3 | 10 | 4 | 11 | 2270 * BCM5720 | X | X | X | X | 2271 * 2272 * Other addresses may respond but they are not 2273 * IEEE compliant PHYs and should be ignored. 2274 */ 2275 switch (BGE_ASICREV(sc->bge_chipid)) { 2276 case BGE_ASICREV_BCM5717: 2277 case BGE_ASICREV_BCM5719: 2278 case BGE_ASICREV_BCM5720: 2279 phy_addr = pa->pa_function; 2280 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2281 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2282 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2283 } else { 2284 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2285 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2286 } 2287 } 2288 2289 return phy_addr; 2290 } 2291 2292 /* 2293 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2294 * self-test results. 2295 */ 2296 static int 2297 bge_chipinit(struct bge_softc *sc) 2298 { 2299 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2300 int i; 2301 2302 /* Set endianness before we access any non-PCI registers. */ 2303 misc_ctl = BGE_INIT; 2304 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2305 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2306 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2307 misc_ctl); 2308 2309 /* 2310 * Clear the MAC statistics block in the NIC's 2311 * internal memory. 2312 */ 2313 for (i = BGE_STATS_BLOCK; 2314 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2315 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2316 2317 for (i = BGE_STATUS_BLOCK; 2318 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2319 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2320 2321 /* 5717 workaround from tg3 */ 2322 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2323 /* Save */ 2324 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2325 2326 /* Temporary modify MODE_CTL to control TLP */ 2327 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2328 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2329 2330 /* Control TLP */ 2331 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2332 BGE_TLP_PHYCTL1); 2333 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2334 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2335 2336 /* Restore */ 2337 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2338 } 2339 2340 if (BGE_IS_57765_FAMILY(sc)) { 2341 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2342 /* Save */ 2343 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2344 2345 /* Temporary modify MODE_CTL to control TLP */ 2346 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2347 CSR_WRITE_4(sc, BGE_MODE_CTL, 2348 reg | BGE_MODECTL_PCIE_TLPADDR1); 2349 2350 /* Control TLP */ 2351 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2352 BGE_TLP_PHYCTL5); 2353 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2354 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2355 2356 /* Restore */ 2357 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2358 } 2359 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2360 /* 2361 * For the 57766 and non Ax versions of 57765, bootcode 2362 * needs to setup the PCIE Fast Training Sequence (FTS) 2363 * value to prevent transmit hangs. 2364 */ 2365 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2366 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2367 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2368 2369 /* Save */ 2370 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2371 2372 /* Temporary modify MODE_CTL to control TLP */ 2373 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2374 CSR_WRITE_4(sc, BGE_MODE_CTL, 2375 reg | BGE_MODECTL_PCIE_TLPADDR0); 2376 2377 /* Control TLP */ 2378 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2379 BGE_TLP_FTSMAX); 2380 reg &= ~BGE_TLP_FTSMAX_MSK; 2381 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2382 reg | BGE_TLP_FTSMAX_VAL); 2383 2384 /* Restore */ 2385 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2386 } 2387 2388 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2389 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2390 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2391 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2392 } 2393 2394 /* Set up the PCI DMA control register. */ 2395 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2396 if (sc->bge_flags & BGEF_PCIE) { 2397 /* Read watermark not used, 128 bytes for write. */ 2398 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2399 device_xname(sc->bge_dev))); 2400 if (sc->bge_mps >= 256) 2401 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2402 else 2403 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2404 } else if (sc->bge_flags & BGEF_PCIX) { 2405 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2406 device_xname(sc->bge_dev))); 2407 /* PCI-X bus */ 2408 if (BGE_IS_5714_FAMILY(sc)) { 2409 /* 256 bytes for read and write. */ 2410 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2411 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2412 2413 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2414 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2415 else 2416 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2417 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2418 /* 2419 * In the BCM5703, the DMA read watermark should 2420 * be set to less than or equal to the maximum 2421 * memory read byte count of the PCI-X command 2422 * register. 2423 */ 2424 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2425 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2426 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2427 /* 1536 bytes for read, 384 bytes for write. */ 2428 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2429 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2430 } else { 2431 /* 384 bytes for read and write. */ 2432 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2433 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2434 (0x0F); 2435 } 2436 2437 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2438 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2439 uint32_t tmp; 2440 2441 /* Set ONEDMA_ATONCE for hardware workaround. */ 2442 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2443 if (tmp == 6 || tmp == 7) 2444 dma_rw_ctl |= 2445 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2446 2447 /* Set PCI-X DMA write workaround. */ 2448 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2449 } 2450 } else { 2451 /* Conventional PCI bus: 256 bytes for read and write. */ 2452 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2453 device_xname(sc->bge_dev))); 2454 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2455 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2456 2457 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2458 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2459 dma_rw_ctl |= 0x0F; 2460 } 2461 2462 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2463 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2464 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2465 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2466 2467 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2468 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2469 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2470 2471 if (BGE_IS_57765_PLUS(sc)) { 2472 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2473 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2474 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2475 2476 /* 2477 * Enable HW workaround for controllers that misinterpret 2478 * a status tag update and leave interrupts permanently 2479 * disabled. 2480 */ 2481 if (!BGE_IS_57765_FAMILY(sc) && 2482 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2483 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2484 } 2485 2486 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2487 dma_rw_ctl); 2488 2489 /* 2490 * Set up general mode register. 2491 */ 2492 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2493 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2494 /* Retain Host-2-BMC settings written by APE firmware. */ 2495 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2496 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2497 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2498 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2499 } 2500 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2501 BGE_MODECTL_TX_NO_PHDR_CSUM; 2502 2503 /* 2504 * BCM5701 B5 have a bug causing data corruption when using 2505 * 64-bit DMA reads, which can be terminated early and then 2506 * completed later as 32-bit accesses, in combination with 2507 * certain bridges. 2508 */ 2509 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2510 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2511 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2512 2513 /* 2514 * Tell the firmware the driver is running 2515 */ 2516 if (sc->bge_asf_mode & ASF_STACKUP) 2517 mode_ctl |= BGE_MODECTL_STACKUP; 2518 2519 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2520 2521 /* 2522 * Disable memory write invalidate. Apparently it is not supported 2523 * properly by these devices. 2524 */ 2525 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2526 PCI_COMMAND_INVALIDATE_ENABLE); 2527 2528 #ifdef __brokenalpha__ 2529 /* 2530 * Must insure that we do not cross an 8K (bytes) boundary 2531 * for DMA reads. Our highest limit is 1K bytes. This is a 2532 * restriction on some ALPHA platforms with early revision 2533 * 21174 PCI chipsets, such as the AlphaPC 164lx 2534 */ 2535 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2536 #endif 2537 2538 /* Set the timer prescaler (always 66MHz) */ 2539 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2540 2541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2542 DELAY(40); /* XXX */ 2543 2544 /* Put PHY into ready state */ 2545 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2546 DELAY(40); 2547 } 2548 2549 return 0; 2550 } 2551 2552 static int 2553 bge_blockinit(struct bge_softc *sc) 2554 { 2555 volatile struct bge_rcb *rcb; 2556 bus_size_t rcb_addr; 2557 struct ifnet *ifp = &sc->ethercom.ec_if; 2558 bge_hostaddr taddr; 2559 uint32_t dmactl, mimode, val; 2560 int i, limit; 2561 2562 /* 2563 * Initialize the memory window pointer register so that 2564 * we can access the first 32K of internal NIC RAM. This will 2565 * allow us to set up the TX send ring RCBs and the RX return 2566 * ring RCBs, plus other things which live in NIC memory. 2567 */ 2568 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2569 2570 if (!BGE_IS_5705_PLUS(sc)) { 2571 /* 57XX step 33 */ 2572 /* Configure mbuf memory pool */ 2573 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2574 BGE_BUFFPOOL_1); 2575 2576 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2577 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2578 else 2579 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2580 2581 /* 57XX step 34 */ 2582 /* Configure DMA resource pool */ 2583 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2584 BGE_DMA_DESCRIPTORS); 2585 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2586 } 2587 2588 /* 5718 step 11, 57XX step 35 */ 2589 /* 2590 * Configure mbuf pool watermarks. New broadcom docs strongly 2591 * recommend these. 2592 */ 2593 if (BGE_IS_5717_PLUS(sc)) { 2594 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2595 if (ifp->if_mtu > ETHERMTU) { 2596 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2597 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2598 } else { 2599 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2600 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2601 } 2602 } else if (BGE_IS_5705_PLUS(sc)) { 2603 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2604 2605 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2606 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2607 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2608 } else { 2609 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2610 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2611 } 2612 } else { 2613 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2614 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2615 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2616 } 2617 2618 /* 57XX step 36 */ 2619 /* Configure DMA resource watermarks */ 2620 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2621 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2622 2623 /* 5718 step 13, 57XX step 38 */ 2624 /* Enable buffer manager */ 2625 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2626 /* 2627 * Change the arbitration algorithm of TXMBUF read request to 2628 * round-robin instead of priority based for BCM5719. When 2629 * TXFIFO is almost empty, RDMA will hold its request until 2630 * TXFIFO is not almost empty. 2631 */ 2632 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2633 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2634 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2635 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2636 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2637 val |= BGE_BMANMODE_LOMBUF_ATTN; 2638 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2639 2640 /* 57XX step 39 */ 2641 /* Poll for buffer manager start indication */ 2642 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2643 DELAY(10); 2644 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2645 break; 2646 } 2647 2648 if (i == BGE_TIMEOUT * 2) { 2649 aprint_error_dev(sc->bge_dev, 2650 "buffer manager failed to start\n"); 2651 return ENXIO; 2652 } 2653 2654 /* 57XX step 40 */ 2655 /* Enable flow-through queues */ 2656 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2657 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2658 2659 /* Wait until queue initialization is complete */ 2660 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2661 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2662 break; 2663 DELAY(10); 2664 } 2665 2666 if (i == BGE_TIMEOUT * 2) { 2667 aprint_error_dev(sc->bge_dev, 2668 "flow-through queue init failed\n"); 2669 return ENXIO; 2670 } 2671 2672 /* 2673 * Summary of rings supported by the controller: 2674 * 2675 * Standard Receive Producer Ring 2676 * - This ring is used to feed receive buffers for "standard" 2677 * sized frames (typically 1536 bytes) to the controller. 2678 * 2679 * Jumbo Receive Producer Ring 2680 * - This ring is used to feed receive buffers for jumbo sized 2681 * frames (i.e. anything bigger than the "standard" frames) 2682 * to the controller. 2683 * 2684 * Mini Receive Producer Ring 2685 * - This ring is used to feed receive buffers for "mini" 2686 * sized frames to the controller. 2687 * - This feature required external memory for the controller 2688 * but was never used in a production system. Should always 2689 * be disabled. 2690 * 2691 * Receive Return Ring 2692 * - After the controller has placed an incoming frame into a 2693 * receive buffer that buffer is moved into a receive return 2694 * ring. The driver is then responsible to passing the 2695 * buffer up to the stack. Many versions of the controller 2696 * support multiple RR rings. 2697 * 2698 * Send Ring 2699 * - This ring is used for outgoing frames. Many versions of 2700 * the controller support multiple send rings. 2701 */ 2702 2703 /* 5718 step 15, 57XX step 41 */ 2704 /* Initialize the standard RX ring control block */ 2705 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2706 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2707 /* 5718 step 16 */ 2708 if (BGE_IS_57765_PLUS(sc)) { 2709 /* 2710 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2711 * Bits 15-2 : Maximum RX frame size 2712 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2713 * Bit 0 : Reserved 2714 */ 2715 rcb->bge_maxlen_flags = 2716 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2717 } else if (BGE_IS_5705_PLUS(sc)) { 2718 /* 2719 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2720 * Bits 15-2 : Reserved (should be 0) 2721 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2722 * Bit 0 : Reserved 2723 */ 2724 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2725 } else { 2726 /* 2727 * Ring size is always XXX entries 2728 * Bits 31-16: Maximum RX frame size 2729 * Bits 15-2 : Reserved (should be 0) 2730 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2731 * Bit 0 : Reserved 2732 */ 2733 rcb->bge_maxlen_flags = 2734 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2735 } 2736 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2737 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2738 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2739 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2740 else 2741 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2742 /* Write the standard receive producer ring control block. */ 2743 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2744 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2745 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2746 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2747 2748 /* Reset the standard receive producer ring producer index. */ 2749 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2750 2751 /* 57XX step 42 */ 2752 /* 2753 * Initialize the jumbo RX ring control block 2754 * We set the 'ring disabled' bit in the flags 2755 * field until we're actually ready to start 2756 * using this ring (i.e. once we set the MTU 2757 * high enough to require it). 2758 */ 2759 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2760 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2761 BGE_HOSTADDR(rcb->bge_hostaddr, 2762 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2763 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2764 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2765 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2766 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2767 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2768 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2769 else 2770 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2771 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2772 rcb->bge_hostaddr.bge_addr_hi); 2773 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2774 rcb->bge_hostaddr.bge_addr_lo); 2775 /* Program the jumbo receive producer ring RCB parameters. */ 2776 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2777 rcb->bge_maxlen_flags); 2778 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2779 /* Reset the jumbo receive producer ring producer index. */ 2780 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2781 } 2782 2783 /* 57XX step 43 */ 2784 /* Disable the mini receive producer ring RCB. */ 2785 if (BGE_IS_5700_FAMILY(sc)) { 2786 /* Set up dummy disabled mini ring RCB */ 2787 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2788 rcb->bge_maxlen_flags = 2789 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2790 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2791 rcb->bge_maxlen_flags); 2792 /* Reset the mini receive producer ring producer index. */ 2793 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2794 2795 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2796 offsetof(struct bge_ring_data, bge_info), 2797 sizeof (struct bge_gib), 2798 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2799 } 2800 2801 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2802 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2803 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2804 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2805 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2806 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2807 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2808 } 2809 /* 5718 step 14, 57XX step 44 */ 2810 /* 2811 * The BD ring replenish thresholds control how often the 2812 * hardware fetches new BD's from the producer rings in host 2813 * memory. Setting the value too low on a busy system can 2814 * starve the hardware and recue the throughpout. 2815 * 2816 * Set the BD ring replenish thresholds. The recommended 2817 * values are 1/8th the number of descriptors allocated to 2818 * each ring, but since we try to avoid filling the entire 2819 * ring we set these to the minimal value of 8. This needs to 2820 * be done on several of the supported chip revisions anyway, 2821 * to work around HW bugs. 2822 */ 2823 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2824 if (BGE_IS_JUMBO_CAPABLE(sc)) 2825 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2826 2827 /* 5718 step 18 */ 2828 if (BGE_IS_5717_PLUS(sc)) { 2829 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2830 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2831 } 2832 2833 /* 57XX step 45 */ 2834 /* 2835 * Disable all send rings by setting the 'ring disabled' bit 2836 * in the flags field of all the TX send ring control blocks, 2837 * located in NIC memory. 2838 */ 2839 if (BGE_IS_5700_FAMILY(sc)) { 2840 /* 5700 to 5704 had 16 send rings. */ 2841 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2842 } else if (BGE_IS_5717_PLUS(sc)) { 2843 limit = BGE_TX_RINGS_5717_MAX; 2844 } else if (BGE_IS_57765_FAMILY(sc)) { 2845 limit = BGE_TX_RINGS_57765_MAX; 2846 } else 2847 limit = 1; 2848 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2849 for (i = 0; i < limit; i++) { 2850 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2851 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2852 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2853 rcb_addr += sizeof(struct bge_rcb); 2854 } 2855 2856 /* 57XX step 46 and 47 */ 2857 /* Configure send ring RCB 0 (we use only the first ring) */ 2858 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2859 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2860 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2861 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2862 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2863 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2864 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2865 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2866 else 2867 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2868 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2869 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2870 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2871 2872 /* 57XX step 48 */ 2873 /* 2874 * Disable all receive return rings by setting the 2875 * 'ring diabled' bit in the flags field of all the receive 2876 * return ring control blocks, located in NIC memory. 2877 */ 2878 if (BGE_IS_5717_PLUS(sc)) { 2879 /* Should be 17, use 16 until we get an SRAM map. */ 2880 limit = 16; 2881 } else if (BGE_IS_5700_FAMILY(sc)) 2882 limit = BGE_RX_RINGS_MAX; 2883 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2884 BGE_IS_57765_FAMILY(sc)) 2885 limit = 4; 2886 else 2887 limit = 1; 2888 /* Disable all receive return rings */ 2889 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2890 for (i = 0; i < limit; i++) { 2891 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2892 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2893 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2894 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2895 BGE_RCB_FLAG_RING_DISABLED)); 2896 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2897 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2898 (i * (sizeof(uint64_t))), 0); 2899 rcb_addr += sizeof(struct bge_rcb); 2900 } 2901 2902 /* 57XX step 49 */ 2903 /* 2904 * Set up receive return ring 0. Note that the NIC address 2905 * for RX return rings is 0x0. The return rings live entirely 2906 * within the host, so the nicaddr field in the RCB isn't used. 2907 */ 2908 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2909 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2910 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2911 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2912 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2913 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2914 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2915 2916 /* 5718 step 24, 57XX step 53 */ 2917 /* Set random backoff seed for TX */ 2918 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2919 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2920 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2921 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2922 BGE_TX_BACKOFF_SEED_MASK); 2923 2924 /* 5718 step 26, 57XX step 55 */ 2925 /* Set inter-packet gap */ 2926 val = 0x2620; 2927 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2928 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2929 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2930 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2931 2932 /* 5718 step 27, 57XX step 56 */ 2933 /* 2934 * Specify which ring to use for packets that don't match 2935 * any RX rules. 2936 */ 2937 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2938 2939 /* 5718 step 28, 57XX step 57 */ 2940 /* 2941 * Configure number of RX lists. One interrupt distribution 2942 * list, sixteen active lists, one bad frames class. 2943 */ 2944 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2945 2946 /* 5718 step 29, 57XX step 58 */ 2947 /* Inialize RX list placement stats mask. */ 2948 if (BGE_IS_575X_PLUS(sc)) { 2949 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2950 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2951 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2952 } else 2953 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2954 2955 /* 5718 step 30, 57XX step 59 */ 2956 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2957 2958 /* 5718 step 33, 57XX step 62 */ 2959 /* Disable host coalescing until we get it set up */ 2960 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2961 2962 /* 5718 step 34, 57XX step 63 */ 2963 /* Poll to make sure it's shut down. */ 2964 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2965 DELAY(10); 2966 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2967 break; 2968 } 2969 2970 if (i == BGE_TIMEOUT * 2) { 2971 aprint_error_dev(sc->bge_dev, 2972 "host coalescing engine failed to idle\n"); 2973 return ENXIO; 2974 } 2975 2976 /* 5718 step 35, 36, 37 */ 2977 /* Set up host coalescing defaults */ 2978 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2979 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2980 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2981 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2982 if (!(BGE_IS_5705_PLUS(sc))) { 2983 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2984 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2985 } 2986 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2987 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2988 2989 /* Set up address of statistics block */ 2990 if (BGE_IS_5700_FAMILY(sc)) { 2991 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2992 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2993 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2994 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2995 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2996 } 2997 2998 /* 5718 step 38 */ 2999 /* Set up address of status block */ 3000 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 3001 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 3002 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 3003 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 3004 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 3005 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 3006 3007 /* Set up status block size. */ 3008 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 3009 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 3010 val = BGE_STATBLKSZ_FULL; 3011 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 3012 } else { 3013 val = BGE_STATBLKSZ_32BYTE; 3014 bzero(&sc->bge_rdata->bge_status_block, 32); 3015 } 3016 3017 /* 5718 step 39, 57XX step 73 */ 3018 /* Turn on host coalescing state machine */ 3019 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 3020 3021 /* 5718 step 40, 57XX step 74 */ 3022 /* Turn on RX BD completion state machine and enable attentions */ 3023 CSR_WRITE_4(sc, BGE_RBDC_MODE, 3024 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 3025 3026 /* 5718 step 41, 57XX step 75 */ 3027 /* Turn on RX list placement state machine */ 3028 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3029 3030 /* 57XX step 76 */ 3031 /* Turn on RX list selector state machine. */ 3032 if (!(BGE_IS_5705_PLUS(sc))) 3033 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3034 3035 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 3036 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 3037 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 3038 BGE_MACMODE_FRMHDR_DMA_ENB; 3039 3040 if (sc->bge_flags & BGEF_FIBER_TBI) 3041 val |= BGE_PORTMODE_TBI; 3042 else if (sc->bge_flags & BGEF_FIBER_MII) 3043 val |= BGE_PORTMODE_GMII; 3044 else 3045 val |= BGE_PORTMODE_MII; 3046 3047 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 3048 /* Allow APE to send/receive frames. */ 3049 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3050 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3051 3052 /* Turn on DMA, clear stats */ 3053 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 3054 /* 5718 step 44 */ 3055 DELAY(40); 3056 3057 /* 5718 step 45, 57XX step 79 */ 3058 /* Set misc. local control, enable interrupts on attentions */ 3059 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 3060 if (BGE_IS_5717_PLUS(sc)) { 3061 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 3062 /* 5718 step 46 */ 3063 DELAY(100); 3064 } 3065 3066 /* 57XX step 81 */ 3067 /* Turn on DMA completion state machine */ 3068 if (!(BGE_IS_5705_PLUS(sc))) 3069 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3070 3071 /* 5718 step 47, 57XX step 82 */ 3072 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 3073 3074 /* 5718 step 48 */ 3075 /* Enable host coalescing bug fix. */ 3076 if (BGE_IS_5755_PLUS(sc)) 3077 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 3078 3079 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3080 val |= BGE_WDMAMODE_BURST_ALL_DATA; 3081 3082 /* Turn on write DMA state machine */ 3083 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 3084 /* 5718 step 49 */ 3085 DELAY(40); 3086 3087 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 3088 3089 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 3090 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 3091 3092 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3093 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3094 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3095 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 3096 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 3097 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 3098 3099 if (sc->bge_flags & BGEF_PCIE) 3100 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 3101 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 3102 if (ifp->if_mtu <= ETHERMTU) 3103 val |= BGE_RDMAMODE_JMB_2K_MMRR; 3104 } 3105 if (sc->bge_flags & BGEF_TSO) { 3106 val |= BGE_RDMAMODE_TSO4_ENABLE; 3107 if (BGE_IS_5717_PLUS(sc)) 3108 val |= BGE_RDMAMODE_TSO6_ENABLE; 3109 } 3110 3111 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3112 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 3113 BGE_RDMAMODE_H2BNC_VLAN_DET; 3114 /* 3115 * Allow multiple outstanding read requests from 3116 * non-LSO read DMA engine. 3117 */ 3118 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 3119 } 3120 3121 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3122 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3123 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3124 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 3125 BGE_IS_57765_PLUS(sc)) { 3126 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 3127 /* 3128 * Adjust tx margin to prevent TX data corruption and 3129 * fix internal FIFO overflow. 3130 */ 3131 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3132 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 3133 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 3134 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 3135 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 3136 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 3137 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 3138 } 3139 /* 3140 * Enable fix for read DMA FIFO overruns. 3141 * The fix is to limit the number of RX BDs 3142 * the hardware would fetch at a fime. 3143 */ 3144 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 3145 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 3146 } 3147 3148 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 3149 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3150 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3151 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 3152 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3153 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3154 /* 3155 * Allow 4KB burst length reads for non-LSO frames. 3156 * Enable 512B burst length reads for buffer descriptors. 3157 */ 3158 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 3159 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 3160 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 3161 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 3162 } 3163 /* Turn on read DMA state machine */ 3164 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 3165 /* 5718 step 52 */ 3166 delay(40); 3167 3168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3169 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3170 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 3171 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 3172 if ((val & 0xFFFF) > BGE_FRAMELEN) 3173 break; 3174 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 3175 break; 3176 } 3177 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 3178 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 3179 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 3180 val |= BGE_RDMA_TX_LENGTH_WA_5719; 3181 else 3182 val |= BGE_RDMA_TX_LENGTH_WA_5720; 3183 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 3184 } 3185 } 3186 3187 /* 5718 step 56, 57XX step 84 */ 3188 /* Turn on RX data completion state machine */ 3189 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3190 3191 /* Turn on RX data and RX BD initiator state machine */ 3192 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3193 3194 /* 57XX step 85 */ 3195 /* Turn on Mbuf cluster free state machine */ 3196 if (!BGE_IS_5705_PLUS(sc)) 3197 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3198 3199 /* 5718 step 57, 57XX step 86 */ 3200 /* Turn on send data completion state machine */ 3201 val = BGE_SDCMODE_ENABLE; 3202 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3203 val |= BGE_SDCMODE_CDELAY; 3204 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3205 3206 /* 5718 step 58 */ 3207 /* Turn on send BD completion state machine */ 3208 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3209 3210 /* 57XX step 88 */ 3211 /* Turn on RX BD initiator state machine */ 3212 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3213 3214 /* 5718 step 60, 57XX step 90 */ 3215 /* Turn on send data initiator state machine */ 3216 if (sc->bge_flags & BGEF_TSO) { 3217 /* XXX: magic value from Linux driver */ 3218 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3219 BGE_SDIMODE_HW_LSO_PRE_DMA); 3220 } else 3221 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3222 3223 /* 5718 step 61, 57XX step 91 */ 3224 /* Turn on send BD initiator state machine */ 3225 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3226 3227 /* 5718 step 62, 57XX step 92 */ 3228 /* Turn on send BD selector state machine */ 3229 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3230 3231 /* 5718 step 31, 57XX step 60 */ 3232 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3233 /* 5718 step 32, 57XX step 61 */ 3234 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3235 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3236 3237 /* ack/clear link change events */ 3238 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3239 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3240 BGE_MACSTAT_LINK_CHANGED); 3241 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3242 3243 /* 3244 * Enable attention when the link has changed state for 3245 * devices that use auto polling. 3246 */ 3247 if (sc->bge_flags & BGEF_FIBER_TBI) { 3248 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3249 } else { 3250 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3251 mimode = BGE_MIMODE_500KHZ_CONST; 3252 else 3253 mimode = BGE_MIMODE_BASE; 3254 /* 5718 step 68. 5718 step 69 (optionally). */ 3255 if (BGE_IS_5700_FAMILY(sc) || 3256 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3257 mimode |= BGE_MIMODE_AUTOPOLL; 3258 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3259 } 3260 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3261 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3262 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3263 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3264 BGE_EVTENB_MI_INTERRUPT); 3265 } 3266 3267 /* 3268 * Clear any pending link state attention. 3269 * Otherwise some link state change events may be lost until attention 3270 * is cleared by bge_intr() -> bge_link_upd() sequence. 3271 * It's not necessary on newer BCM chips - perhaps enabling link 3272 * state change attentions implies clearing pending attention. 3273 */ 3274 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3275 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3276 BGE_MACSTAT_LINK_CHANGED); 3277 3278 /* Enable link state change attentions. */ 3279 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3280 3281 return 0; 3282 } 3283 3284 static const struct bge_revision * 3285 bge_lookup_rev(uint32_t chipid) 3286 { 3287 const struct bge_revision *br; 3288 3289 for (br = bge_revisions; br->br_name != NULL; br++) { 3290 if (br->br_chipid == chipid) 3291 return br; 3292 } 3293 3294 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3295 if (br->br_chipid == BGE_ASICREV(chipid)) 3296 return br; 3297 } 3298 3299 return NULL; 3300 } 3301 3302 static const struct bge_product * 3303 bge_lookup(const struct pci_attach_args *pa) 3304 { 3305 const struct bge_product *bp; 3306 3307 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3308 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3309 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3310 return bp; 3311 } 3312 3313 return NULL; 3314 } 3315 3316 static uint32_t 3317 bge_chipid(const struct pci_attach_args *pa) 3318 { 3319 uint32_t id; 3320 3321 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3322 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3323 3324 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3325 switch (PCI_PRODUCT(pa->pa_id)) { 3326 case PCI_PRODUCT_BROADCOM_BCM5717: 3327 case PCI_PRODUCT_BROADCOM_BCM5718: 3328 case PCI_PRODUCT_BROADCOM_BCM5719: 3329 case PCI_PRODUCT_BROADCOM_BCM5720: 3330 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3331 BGE_PCI_GEN2_PRODID_ASICREV); 3332 break; 3333 case PCI_PRODUCT_BROADCOM_BCM57761: 3334 case PCI_PRODUCT_BROADCOM_BCM57762: 3335 case PCI_PRODUCT_BROADCOM_BCM57765: 3336 case PCI_PRODUCT_BROADCOM_BCM57766: 3337 case PCI_PRODUCT_BROADCOM_BCM57781: 3338 case PCI_PRODUCT_BROADCOM_BCM57782: 3339 case PCI_PRODUCT_BROADCOM_BCM57785: 3340 case PCI_PRODUCT_BROADCOM_BCM57786: 3341 case PCI_PRODUCT_BROADCOM_BCM57791: 3342 case PCI_PRODUCT_BROADCOM_BCM57795: 3343 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3344 BGE_PCI_GEN15_PRODID_ASICREV); 3345 break; 3346 default: 3347 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3348 BGE_PCI_PRODID_ASICREV); 3349 break; 3350 } 3351 } 3352 3353 return id; 3354 } 3355 3356 /* 3357 * Return true if MSI can be used with this device. 3358 */ 3359 static int 3360 bge_can_use_msi(struct bge_softc *sc) 3361 { 3362 int can_use_msi = 0; 3363 3364 switch (BGE_ASICREV(sc->bge_chipid)) { 3365 case BGE_ASICREV_BCM5714_A0: 3366 case BGE_ASICREV_BCM5714: 3367 /* 3368 * Apparently, MSI doesn't work when these chips are 3369 * configured in single-port mode. 3370 */ 3371 break; 3372 case BGE_ASICREV_BCM5750: 3373 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3374 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3375 can_use_msi = 1; 3376 break; 3377 default: 3378 if (BGE_IS_575X_PLUS(sc)) 3379 can_use_msi = 1; 3380 } 3381 return (can_use_msi); 3382 } 3383 3384 /* 3385 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3386 * against our list and return its name if we find a match. Note 3387 * that since the Broadcom controller contains VPD support, we 3388 * can get the device name string from the controller itself instead 3389 * of the compiled-in string. This is a little slow, but it guarantees 3390 * we'll always announce the right product name. 3391 */ 3392 static int 3393 bge_probe(device_t parent, cfdata_t match, void *aux) 3394 { 3395 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3396 3397 if (bge_lookup(pa) != NULL) 3398 return 1; 3399 3400 return 0; 3401 } 3402 3403 static void 3404 bge_attach(device_t parent, device_t self, void *aux) 3405 { 3406 struct bge_softc *sc = device_private(self); 3407 struct pci_attach_args *pa = aux; 3408 prop_dictionary_t dict; 3409 const struct bge_product *bp; 3410 const struct bge_revision *br; 3411 pci_chipset_tag_t pc; 3412 const char *intrstr = NULL; 3413 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3414 uint32_t command; 3415 struct ifnet *ifp; 3416 uint32_t misccfg, mimode; 3417 void * kva; 3418 u_char eaddr[ETHER_ADDR_LEN]; 3419 pcireg_t memtype, subid, reg; 3420 bus_addr_t memaddr; 3421 uint32_t pm_ctl; 3422 bool no_seeprom; 3423 int capmask; 3424 int mii_flags; 3425 int map_flags; 3426 char intrbuf[PCI_INTRSTR_LEN]; 3427 3428 bp = bge_lookup(pa); 3429 KASSERT(bp != NULL); 3430 3431 sc->sc_pc = pa->pa_pc; 3432 sc->sc_pcitag = pa->pa_tag; 3433 sc->bge_dev = self; 3434 3435 sc->bge_pa = *pa; 3436 pc = sc->sc_pc; 3437 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3438 3439 aprint_naive(": Ethernet controller\n"); 3440 aprint_normal(": %s\n", bp->bp_name); 3441 3442 /* 3443 * Map control/status registers. 3444 */ 3445 DPRINTFN(5, ("Map control/status regs\n")); 3446 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3447 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3448 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3449 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3450 3451 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3452 aprint_error_dev(sc->bge_dev, 3453 "failed to enable memory mapping!\n"); 3454 return; 3455 } 3456 3457 DPRINTFN(5, ("pci_mem_find\n")); 3458 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3459 switch (memtype) { 3460 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3461 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3462 #if 0 3463 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3464 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3465 &memaddr, &sc->bge_bsize) == 0) 3466 break; 3467 #else 3468 /* 3469 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3470 * system get NMI on boot (PR#48451). This problem might not be 3471 * the driver's bug but our PCI common part's bug. Until we 3472 * find a real reason, we ignore the prefetchable bit. 3473 */ 3474 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3475 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3476 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3477 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3478 map_flags, &sc->bge_bhandle) == 0) { 3479 sc->bge_btag = pa->pa_memt; 3480 break; 3481 } 3482 } 3483 #endif 3484 /* FALLTHROUGH */ 3485 default: 3486 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3487 return; 3488 } 3489 3490 /* Save various chip information. */ 3491 sc->bge_chipid = bge_chipid(pa); 3492 sc->bge_phy_addr = bge_phy_addr(sc); 3493 3494 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3495 &sc->bge_pciecap, NULL) != 0) { 3496 /* PCIe */ 3497 sc->bge_flags |= BGEF_PCIE; 3498 /* Extract supported maximum payload size. */ 3499 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3500 sc->bge_pciecap + PCIE_DCAP); 3501 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3502 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3503 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3504 sc->bge_expmrq = 2048; 3505 else 3506 sc->bge_expmrq = 4096; 3507 bge_set_max_readrq(sc); 3508 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3509 /* PCIe without PCIe cap */ 3510 sc->bge_flags |= BGEF_PCIE; 3511 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3512 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3513 /* PCI-X */ 3514 sc->bge_flags |= BGEF_PCIX; 3515 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3516 &sc->bge_pcixcap, NULL) == 0) 3517 aprint_error_dev(sc->bge_dev, 3518 "unable to find PCIX capability\n"); 3519 } 3520 3521 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3522 /* 3523 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3524 * can clobber the chip's PCI config-space power control 3525 * registers, leaving the card in D3 powersave state. We do 3526 * not have memory-mapped registers in this state, so force 3527 * device into D0 state before starting initialization. 3528 */ 3529 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3530 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3531 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3532 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3533 DELAY(1000); /* 27 usec is allegedly sufficent */ 3534 } 3535 3536 /* Save chipset family. */ 3537 switch (BGE_ASICREV(sc->bge_chipid)) { 3538 case BGE_ASICREV_BCM5717: 3539 case BGE_ASICREV_BCM5719: 3540 case BGE_ASICREV_BCM5720: 3541 sc->bge_flags |= BGEF_5717_PLUS; 3542 /* FALLTHROUGH */ 3543 case BGE_ASICREV_BCM57765: 3544 case BGE_ASICREV_BCM57766: 3545 if (!BGE_IS_5717_PLUS(sc)) 3546 sc->bge_flags |= BGEF_57765_FAMILY; 3547 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3548 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3549 /* Jumbo frame on BCM5719 A0 does not work. */ 3550 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3551 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3552 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3553 break; 3554 case BGE_ASICREV_BCM5755: 3555 case BGE_ASICREV_BCM5761: 3556 case BGE_ASICREV_BCM5784: 3557 case BGE_ASICREV_BCM5785: 3558 case BGE_ASICREV_BCM5787: 3559 case BGE_ASICREV_BCM57780: 3560 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3561 break; 3562 case BGE_ASICREV_BCM5700: 3563 case BGE_ASICREV_BCM5701: 3564 case BGE_ASICREV_BCM5703: 3565 case BGE_ASICREV_BCM5704: 3566 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3567 break; 3568 case BGE_ASICREV_BCM5714_A0: 3569 case BGE_ASICREV_BCM5780: 3570 case BGE_ASICREV_BCM5714: 3571 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3572 /* FALLTHROUGH */ 3573 case BGE_ASICREV_BCM5750: 3574 case BGE_ASICREV_BCM5752: 3575 case BGE_ASICREV_BCM5906: 3576 sc->bge_flags |= BGEF_575X_PLUS; 3577 /* FALLTHROUGH */ 3578 case BGE_ASICREV_BCM5705: 3579 sc->bge_flags |= BGEF_5705_PLUS; 3580 break; 3581 } 3582 3583 /* Identify chips with APE processor. */ 3584 switch (BGE_ASICREV(sc->bge_chipid)) { 3585 case BGE_ASICREV_BCM5717: 3586 case BGE_ASICREV_BCM5719: 3587 case BGE_ASICREV_BCM5720: 3588 case BGE_ASICREV_BCM5761: 3589 sc->bge_flags |= BGEF_APE; 3590 break; 3591 } 3592 3593 /* 3594 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3595 * not actually a MAC controller bug but an issue with the embedded 3596 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3597 */ 3598 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3599 sc->bge_flags |= BGEF_40BIT_BUG; 3600 3601 /* Chips with APE need BAR2 access for APE registers/memory. */ 3602 if ((sc->bge_flags & BGEF_APE) != 0) { 3603 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3604 #if 0 3605 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3606 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3607 &sc->bge_apesize)) { 3608 aprint_error_dev(sc->bge_dev, 3609 "couldn't map BAR2 memory\n"); 3610 return; 3611 } 3612 #else 3613 /* 3614 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3615 * system get NMI on boot (PR#48451). This problem might not be 3616 * the driver's bug but our PCI common part's bug. Until we 3617 * find a real reason, we ignore the prefetchable bit. 3618 */ 3619 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3620 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3621 aprint_error_dev(sc->bge_dev, 3622 "couldn't map BAR2 memory\n"); 3623 return; 3624 } 3625 3626 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3627 if (bus_space_map(pa->pa_memt, memaddr, 3628 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3629 aprint_error_dev(sc->bge_dev, 3630 "couldn't map BAR2 memory\n"); 3631 return; 3632 } 3633 sc->bge_apetag = pa->pa_memt; 3634 #endif 3635 3636 /* Enable APE register/memory access by host driver. */ 3637 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3638 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3639 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3640 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3641 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3642 3643 bge_ape_lock_init(sc); 3644 bge_ape_read_fw_ver(sc); 3645 } 3646 3647 /* Identify the chips that use an CPMU. */ 3648 if (BGE_IS_5717_PLUS(sc) || 3649 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3650 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3651 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3652 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3653 sc->bge_flags |= BGEF_CPMU_PRESENT; 3654 3655 /* Set MI_MODE */ 3656 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3657 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3658 mimode |= BGE_MIMODE_500KHZ_CONST; 3659 else 3660 mimode |= BGE_MIMODE_BASE; 3661 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3662 3663 /* 3664 * When using the BCM5701 in PCI-X mode, data corruption has 3665 * been observed in the first few bytes of some received packets. 3666 * Aligning the packet buffer in memory eliminates the corruption. 3667 * Unfortunately, this misaligns the packet payloads. On platforms 3668 * which do not support unaligned accesses, we will realign the 3669 * payloads by copying the received packets. 3670 */ 3671 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3672 sc->bge_flags & BGEF_PCIX) 3673 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3674 3675 if (BGE_IS_5700_FAMILY(sc)) 3676 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3677 3678 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3679 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3680 3681 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3682 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3683 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3684 sc->bge_flags |= BGEF_IS_5788; 3685 3686 /* 3687 * Some controllers seem to require a special firmware to use 3688 * TSO. But the firmware is not available to FreeBSD and Linux 3689 * claims that the TSO performed by the firmware is slower than 3690 * hardware based TSO. Moreover the firmware based TSO has one 3691 * known bug which can't handle TSO if ethernet header + IP/TCP 3692 * header is greater than 80 bytes. The workaround for the TSO 3693 * bug exist but it seems it's too expensive than not using 3694 * TSO at all. Some hardwares also have the TSO bug so limit 3695 * the TSO to the controllers that are not affected TSO issues 3696 * (e.g. 5755 or higher). 3697 */ 3698 if (BGE_IS_5755_PLUS(sc)) { 3699 /* 3700 * BCM5754 and BCM5787 shares the same ASIC id so 3701 * explicit device id check is required. 3702 */ 3703 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3704 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3705 sc->bge_flags |= BGEF_TSO; 3706 /* TSO on BCM5719 A0 does not work. */ 3707 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3708 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3709 sc->bge_flags &= ~BGEF_TSO; 3710 } 3711 3712 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3713 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3714 (misccfg == 0x4000 || misccfg == 0x8000)) || 3715 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3716 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3717 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3718 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3719 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3720 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3721 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3722 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3723 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3724 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3725 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3726 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3727 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3728 /* These chips are 10/100 only. */ 3729 capmask &= ~BMSR_EXTSTAT; 3730 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3731 } 3732 3733 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3734 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3735 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3736 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3737 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3738 3739 /* Set various PHY bug flags. */ 3740 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3741 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3742 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3743 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3744 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3745 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3746 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3747 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3748 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3749 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3750 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3751 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3752 if (BGE_IS_5705_PLUS(sc) && 3753 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3754 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3755 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3756 !BGE_IS_57765_PLUS(sc)) { 3757 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3758 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3759 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3760 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3761 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3762 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3763 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3764 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3765 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3766 } else 3767 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3768 } 3769 3770 /* 3771 * SEEPROM check. 3772 * First check if firmware knows we do not have SEEPROM. 3773 */ 3774 if (prop_dictionary_get_bool(device_properties(self), 3775 "without-seeprom", &no_seeprom) && no_seeprom) 3776 sc->bge_flags |= BGEF_NO_EEPROM; 3777 3778 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3779 sc->bge_flags |= BGEF_NO_EEPROM; 3780 3781 /* Now check the 'ROM failed' bit on the RX CPU */ 3782 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3783 sc->bge_flags |= BGEF_NO_EEPROM; 3784 3785 sc->bge_asf_mode = 0; 3786 /* No ASF if APE present. */ 3787 if ((sc->bge_flags & BGEF_APE) == 0) { 3788 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3789 BGE_SRAM_DATA_SIG_MAGIC)) { 3790 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3791 BGE_HWCFG_ASF) { 3792 sc->bge_asf_mode |= ASF_ENABLE; 3793 sc->bge_asf_mode |= ASF_STACKUP; 3794 if (BGE_IS_575X_PLUS(sc)) 3795 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3796 } 3797 } 3798 } 3799 3800 int counts[PCI_INTR_TYPE_SIZE] = { 3801 [PCI_INTR_TYPE_INTX] = 1, 3802 [PCI_INTR_TYPE_MSI] = 1, 3803 [PCI_INTR_TYPE_MSIX] = 1, 3804 }; 3805 int max_type = PCI_INTR_TYPE_MSIX; 3806 3807 if (!bge_can_use_msi(sc)) { 3808 /* MSI broken, allow only INTx */ 3809 max_type = PCI_INTR_TYPE_INTX; 3810 } 3811 3812 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3813 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3814 return; 3815 } 3816 3817 DPRINTFN(5, ("pci_intr_string\n")); 3818 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3819 sizeof(intrbuf)); 3820 DPRINTFN(5, ("pci_intr_establish\n")); 3821 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3822 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3823 if (sc->bge_intrhand == NULL) { 3824 pci_intr_release(pc, sc->bge_pihp, 1); 3825 sc->bge_pihp = NULL; 3826 3827 aprint_error_dev(self, "couldn't establish interrupt"); 3828 if (intrstr != NULL) 3829 aprint_error(" at %s", intrstr); 3830 aprint_error("\n"); 3831 return; 3832 } 3833 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3834 3835 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3836 case PCI_INTR_TYPE_MSIX: 3837 case PCI_INTR_TYPE_MSI: 3838 KASSERT(bge_can_use_msi(sc)); 3839 sc->bge_flags |= BGEF_MSI; 3840 break; 3841 default: 3842 /* nothing to do */ 3843 break; 3844 } 3845 3846 /* 3847 * All controllers except BCM5700 supports tagged status but 3848 * we use tagged status only for MSI case on BCM5717. Otherwise 3849 * MSI on BCM5717 does not work. 3850 */ 3851 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3852 sc->bge_flags |= BGEF_TAGGED_STATUS; 3853 3854 /* 3855 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3856 * lock in bge_reset(). 3857 */ 3858 CSR_WRITE_4(sc, BGE_EE_ADDR, 3859 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3860 delay(1000); 3861 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3862 3863 bge_stop_fw(sc); 3864 bge_sig_pre_reset(sc, BGE_RESET_START); 3865 if (bge_reset(sc)) 3866 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3867 3868 /* 3869 * Read the hardware config word in the first 32k of NIC internal 3870 * memory, or fall back to the config word in the EEPROM. 3871 * Note: on some BCM5700 cards, this value appears to be unset. 3872 */ 3873 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3874 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3875 BGE_SRAM_DATA_SIG_MAGIC) { 3876 uint32_t tmp; 3877 3878 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3879 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3880 BGE_SRAM_DATA_VER_SHIFT; 3881 if ((0 < tmp) && (tmp < 0x100)) 3882 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3883 if (sc->bge_flags & BGEF_PCIE) 3884 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3885 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3886 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3887 if (BGE_IS_5717_PLUS(sc)) 3888 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3889 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3890 bge_read_eeprom(sc, (void *)&hwcfg, 3891 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3892 hwcfg = be32toh(hwcfg); 3893 } 3894 aprint_normal_dev(sc->bge_dev, 3895 "HW config %08x, %08x, %08x, %08x %08x\n", 3896 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3897 3898 bge_sig_legacy(sc, BGE_RESET_START); 3899 bge_sig_post_reset(sc, BGE_RESET_START); 3900 3901 if (bge_chipinit(sc)) { 3902 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3903 bge_release_resources(sc); 3904 return; 3905 } 3906 3907 /* 3908 * Get station address from the EEPROM. 3909 */ 3910 if (bge_get_eaddr(sc, eaddr)) { 3911 aprint_error_dev(sc->bge_dev, 3912 "failed to read station address\n"); 3913 bge_release_resources(sc); 3914 return; 3915 } 3916 3917 br = bge_lookup_rev(sc->bge_chipid); 3918 3919 if (br == NULL) { 3920 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3921 sc->bge_chipid); 3922 } else { 3923 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3924 br->br_name, sc->bge_chipid); 3925 } 3926 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3927 3928 /* Allocate the general information block and ring buffers. */ 3929 if (pci_dma64_available(pa)) { 3930 sc->bge_dmatag = pa->pa_dmat64; 3931 sc->bge_dmatag32 = pa->pa_dmat; 3932 sc->bge_dma64 = true; 3933 } else { 3934 sc->bge_dmatag = pa->pa_dmat; 3935 sc->bge_dmatag32 = pa->pa_dmat; 3936 sc->bge_dma64 = false; 3937 } 3938 3939 /* 40bit DMA workaround */ 3940 if (sizeof(bus_addr_t) > 4) { 3941 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3942 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3943 3944 if (bus_dmatag_subregion(olddmatag, 0, 3945 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3946 BUS_DMA_NOWAIT) != 0) { 3947 aprint_error_dev(self, 3948 "WARNING: failed to restrict dma range," 3949 " falling back to parent bus dma range\n"); 3950 sc->bge_dmatag = olddmatag; 3951 } 3952 } 3953 } 3954 SLIST_INIT(&sc->txdma_list); 3955 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3956 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3957 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3958 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3959 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3960 return; 3961 } 3962 DPRINTFN(5, ("bus_dmamem_map\n")); 3963 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3964 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3965 BUS_DMA_NOWAIT)) { 3966 aprint_error_dev(sc->bge_dev, 3967 "can't map DMA buffers (%zu bytes)\n", 3968 sizeof(struct bge_ring_data)); 3969 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3970 sc->bge_ring_rseg); 3971 return; 3972 } 3973 DPRINTFN(5, ("bus_dmamem_create\n")); 3974 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3975 sizeof(struct bge_ring_data), 0, 3976 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3977 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3978 bus_dmamem_unmap(sc->bge_dmatag, kva, 3979 sizeof(struct bge_ring_data)); 3980 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3981 sc->bge_ring_rseg); 3982 return; 3983 } 3984 DPRINTFN(5, ("bus_dmamem_load\n")); 3985 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3986 sizeof(struct bge_ring_data), NULL, 3987 BUS_DMA_NOWAIT)) { 3988 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3989 bus_dmamem_unmap(sc->bge_dmatag, kva, 3990 sizeof(struct bge_ring_data)); 3991 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3992 sc->bge_ring_rseg); 3993 return; 3994 } 3995 3996 DPRINTFN(5, ("bzero\n")); 3997 sc->bge_rdata = (struct bge_ring_data *)kva; 3998 3999 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 4000 4001 /* Try to allocate memory for jumbo buffers. */ 4002 if (BGE_IS_JUMBO_CAPABLE(sc)) { 4003 if (bge_alloc_jumbo_mem(sc)) { 4004 aprint_error_dev(sc->bge_dev, 4005 "jumbo buffer allocation failed\n"); 4006 } else 4007 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 4008 } 4009 4010 /* Set default tuneable values. */ 4011 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 4012 sc->bge_rx_coal_ticks = 150; 4013 sc->bge_rx_max_coal_bds = 64; 4014 sc->bge_tx_coal_ticks = 300; 4015 sc->bge_tx_max_coal_bds = 400; 4016 if (BGE_IS_5705_PLUS(sc)) { 4017 sc->bge_tx_coal_ticks = (12 * 5); 4018 sc->bge_tx_max_coal_bds = (12 * 5); 4019 aprint_verbose_dev(sc->bge_dev, 4020 "setting short Tx thresholds\n"); 4021 } 4022 4023 if (BGE_IS_5717_PLUS(sc)) 4024 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 4025 else if (BGE_IS_5705_PLUS(sc)) 4026 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 4027 else 4028 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 4029 4030 /* Set up ifnet structure */ 4031 ifp = &sc->ethercom.ec_if; 4032 ifp->if_softc = sc; 4033 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 4034 ifp->if_ioctl = bge_ioctl; 4035 ifp->if_stop = bge_stop; 4036 ifp->if_start = bge_start; 4037 ifp->if_init = bge_init; 4038 ifp->if_watchdog = bge_watchdog; 4039 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 4040 IFQ_SET_READY(&ifp->if_snd); 4041 DPRINTFN(5, ("strcpy if_xname\n")); 4042 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 4043 4044 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 4045 sc->ethercom.ec_if.if_capabilities |= 4046 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 4047 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 4048 sc->ethercom.ec_if.if_capabilities |= 4049 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 4050 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 4051 #endif 4052 sc->ethercom.ec_capabilities |= 4053 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 4054 4055 if (sc->bge_flags & BGEF_TSO) 4056 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 4057 4058 /* 4059 * Do MII setup. 4060 */ 4061 DPRINTFN(5, ("mii setup\n")); 4062 sc->bge_mii.mii_ifp = ifp; 4063 sc->bge_mii.mii_readreg = bge_miibus_readreg; 4064 sc->bge_mii.mii_writereg = bge_miibus_writereg; 4065 sc->bge_mii.mii_statchg = bge_miibus_statchg; 4066 4067 /* 4068 * Figure out what sort of media we have by checking the hardware 4069 * config word. Note: on some BCM5700 cards, this value appears to be 4070 * unset. If that's the case, we have to rely on identifying the NIC 4071 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 4072 * The SysKonnect SK-9D41 is a 1000baseSX card. 4073 */ 4074 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 4075 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 4076 if (BGE_IS_5705_PLUS(sc)) { 4077 sc->bge_flags |= BGEF_FIBER_MII; 4078 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 4079 } else 4080 sc->bge_flags |= BGEF_FIBER_TBI; 4081 } 4082 4083 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 4084 if (BGE_IS_JUMBO_CAPABLE(sc)) 4085 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 4086 4087 /* set phyflags and chipid before mii_attach() */ 4088 dict = device_properties(self); 4089 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 4090 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 4091 4092 if (sc->bge_flags & BGEF_FIBER_TBI) { 4093 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 4094 bge_ifmedia_sts); 4095 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 4096 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 4097 0, NULL); 4098 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 4099 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 4100 /* Pretend the user requested this setting */ 4101 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 4102 } else { 4103 /* 4104 * Do transceiver setup and tell the firmware the 4105 * driver is down so we can try to get access the 4106 * probe if ASF is running. Retry a couple of times 4107 * if we get a conflict with the ASF firmware accessing 4108 * the PHY. 4109 */ 4110 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4111 bge_asf_driver_up(sc); 4112 4113 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 4114 bge_ifmedia_sts); 4115 mii_flags = MIIF_DOPAUSE; 4116 if (sc->bge_flags & BGEF_FIBER_MII) 4117 mii_flags |= MIIF_HAVEFIBER; 4118 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 4119 MII_OFFSET_ANY, mii_flags); 4120 4121 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 4122 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4123 ifmedia_add(&sc->bge_mii.mii_media, 4124 IFM_ETHER|IFM_MANUAL, 0, NULL); 4125 ifmedia_set(&sc->bge_mii.mii_media, 4126 IFM_ETHER|IFM_MANUAL); 4127 } else 4128 ifmedia_set(&sc->bge_mii.mii_media, 4129 IFM_ETHER|IFM_AUTO); 4130 4131 /* 4132 * Now tell the firmware we are going up after probing the PHY 4133 */ 4134 if (sc->bge_asf_mode & ASF_STACKUP) 4135 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4136 } 4137 4138 /* 4139 * Call MI attach routine. 4140 */ 4141 DPRINTFN(5, ("if_attach\n")); 4142 if_attach(ifp); 4143 if_deferred_start_init(ifp, NULL); 4144 DPRINTFN(5, ("ether_ifattach\n")); 4145 ether_ifattach(ifp, eaddr); 4146 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4147 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4148 RND_TYPE_NET, RND_FLAG_DEFAULT); 4149 #ifdef BGE_EVENT_COUNTERS 4150 /* 4151 * Attach event counters. 4152 */ 4153 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4154 NULL, device_xname(sc->bge_dev), "intr"); 4155 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4156 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4157 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4158 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4159 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4160 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4161 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4162 NULL, device_xname(sc->bge_dev), "tx_xon"); 4163 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4164 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4165 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4166 NULL, device_xname(sc->bge_dev), "rx_xon"); 4167 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4168 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4169 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4170 NULL, device_xname(sc->bge_dev), "xoffentered"); 4171 #endif /* BGE_EVENT_COUNTERS */ 4172 DPRINTFN(5, ("callout_init\n")); 4173 callout_init(&sc->bge_timeout, 0); 4174 4175 if (pmf_device_register(self, NULL, NULL)) 4176 pmf_class_network_register(self, ifp); 4177 else 4178 aprint_error_dev(self, "couldn't establish power handler\n"); 4179 4180 bge_sysctl_init(sc); 4181 4182 #ifdef BGE_DEBUG 4183 bge_debug_info(sc); 4184 #endif 4185 } 4186 4187 /* 4188 * Stop all chip I/O so that the kernel's probe routines don't 4189 * get confused by errant DMAs when rebooting. 4190 */ 4191 static int 4192 bge_detach(device_t self, int flags __unused) 4193 { 4194 struct bge_softc *sc = device_private(self); 4195 struct ifnet *ifp = &sc->ethercom.ec_if; 4196 int s; 4197 4198 s = splnet(); 4199 /* Stop the interface. Callouts are stopped in it. */ 4200 bge_stop(ifp, 1); 4201 splx(s); 4202 4203 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4204 4205 /* Delete all remaining media. */ 4206 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 4207 4208 ether_ifdetach(ifp); 4209 if_detach(ifp); 4210 4211 bge_release_resources(sc); 4212 4213 return 0; 4214 } 4215 4216 static void 4217 bge_release_resources(struct bge_softc *sc) 4218 { 4219 4220 /* Detach sysctl */ 4221 if (sc->bge_log != NULL) 4222 sysctl_teardown(&sc->bge_log); 4223 4224 #ifdef BGE_EVENT_COUNTERS 4225 /* Detach event counters. */ 4226 evcnt_detach(&sc->bge_ev_intr); 4227 evcnt_detach(&sc->bge_ev_intr_spurious); 4228 evcnt_detach(&sc->bge_ev_intr_spurious2); 4229 evcnt_detach(&sc->bge_ev_tx_xoff); 4230 evcnt_detach(&sc->bge_ev_tx_xon); 4231 evcnt_detach(&sc->bge_ev_rx_xoff); 4232 evcnt_detach(&sc->bge_ev_rx_xon); 4233 evcnt_detach(&sc->bge_ev_rx_macctl); 4234 evcnt_detach(&sc->bge_ev_xoffentered); 4235 #endif /* BGE_EVENT_COUNTERS */ 4236 4237 /* Disestablish the interrupt handler */ 4238 if (sc->bge_intrhand != NULL) { 4239 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4240 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4241 sc->bge_intrhand = NULL; 4242 } 4243 4244 if (sc->bge_dmatag != NULL) { 4245 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4246 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4247 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4248 sizeof(struct bge_ring_data)); 4249 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4250 sc->bge_ring_rseg); 4251 } 4252 4253 /* Unmap the device registers */ 4254 if (sc->bge_bsize != 0) { 4255 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4256 sc->bge_bsize = 0; 4257 } 4258 4259 /* Unmap the APE registers */ 4260 if (sc->bge_apesize != 0) { 4261 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4262 sc->bge_apesize); 4263 sc->bge_apesize = 0; 4264 } 4265 } 4266 4267 static int 4268 bge_reset(struct bge_softc *sc) 4269 { 4270 uint32_t cachesize, command; 4271 uint32_t reset, mac_mode, mac_mode_mask; 4272 pcireg_t devctl, reg; 4273 int i, val; 4274 void (*write_op)(struct bge_softc *, int, int); 4275 4276 /* Make mask for BGE_MAC_MODE register. */ 4277 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4278 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4279 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4280 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4281 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4282 4283 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4284 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4285 if (sc->bge_flags & BGEF_PCIE) 4286 write_op = bge_writemem_direct; 4287 else 4288 write_op = bge_writemem_ind; 4289 } else 4290 write_op = bge_writereg_ind; 4291 4292 /* 57XX step 4 */ 4293 /* Acquire the NVM lock */ 4294 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4295 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4296 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4297 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4298 for (i = 0; i < 8000; i++) { 4299 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4300 BGE_NVRAMSWARB_GNT1) 4301 break; 4302 DELAY(20); 4303 } 4304 if (i == 8000) { 4305 printf("%s: NVRAM lock timedout!\n", 4306 device_xname(sc->bge_dev)); 4307 } 4308 } 4309 4310 /* Take APE lock when performing reset. */ 4311 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4312 4313 /* 57XX step 3 */ 4314 /* Save some important PCI state. */ 4315 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4316 /* 5718 reset step 3 */ 4317 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4318 4319 /* 5718 reset step 5, 57XX step 5b-5d */ 4320 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4321 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4322 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4323 4324 /* XXX ???: Disable fastboot on controllers that support it. */ 4325 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4326 BGE_IS_5755_PLUS(sc)) 4327 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4328 4329 /* 5718 reset step 2, 57XX step 6 */ 4330 /* 4331 * Write the magic number to SRAM at offset 0xB50. 4332 * When firmware finishes its initialization it will 4333 * write ~BGE_MAGIC_NUMBER to the same location. 4334 */ 4335 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4336 4337 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4338 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4339 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4340 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4341 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4342 } 4343 4344 /* 5718 reset step 6, 57XX step 7 */ 4345 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4346 /* 4347 * XXX: from FreeBSD/Linux; no documentation 4348 */ 4349 if (sc->bge_flags & BGEF_PCIE) { 4350 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4351 !BGE_IS_57765_PLUS(sc) && 4352 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4353 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4354 /* PCI Express 1.0 system */ 4355 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4356 BGE_PHY_PCIE_SCRAM_MODE); 4357 } 4358 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4359 /* 4360 * Prevent PCI Express link training 4361 * during global reset. 4362 */ 4363 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4364 reset |= (1 << 29); 4365 } 4366 } 4367 4368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4369 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4370 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4371 i | BGE_VCPU_STATUS_DRV_RESET); 4372 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4373 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4374 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4375 } 4376 4377 /* 4378 * Set GPHY Power Down Override to leave GPHY 4379 * powered up in D0 uninitialized. 4380 */ 4381 if (BGE_IS_5705_PLUS(sc) && 4382 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4383 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4384 4385 /* Issue global reset */ 4386 write_op(sc, BGE_MISC_CFG, reset); 4387 4388 /* 5718 reset step 7, 57XX step 8 */ 4389 if (sc->bge_flags & BGEF_PCIE) 4390 delay(100*1000); /* too big */ 4391 else 4392 delay(1000); 4393 4394 if (sc->bge_flags & BGEF_PCIE) { 4395 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4396 DELAY(500000); 4397 /* XXX: Magic Numbers */ 4398 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4399 BGE_PCI_UNKNOWN0); 4400 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4401 BGE_PCI_UNKNOWN0, 4402 reg | (1 << 15)); 4403 } 4404 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4405 sc->bge_pciecap + PCIE_DCSR); 4406 /* Clear enable no snoop and disable relaxed ordering. */ 4407 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4408 PCIE_DCSR_ENA_NO_SNOOP); 4409 4410 /* Set PCIE max payload size to 128 for older PCIe devices */ 4411 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4412 devctl &= ~(0x00e0); 4413 /* Clear device status register. Write 1b to clear */ 4414 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4415 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4416 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4417 sc->bge_pciecap + PCIE_DCSR, devctl); 4418 bge_set_max_readrq(sc); 4419 } 4420 4421 /* From Linux: dummy read to flush PCI posted writes */ 4422 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4423 4424 /* 4425 * Reset some of the PCI state that got zapped by reset 4426 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4427 * set, too. 4428 */ 4429 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4430 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4431 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4432 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4433 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4434 (sc->bge_flags & BGEF_PCIX) != 0) 4435 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4436 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4437 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4438 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4439 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4440 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4441 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4442 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4443 4444 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4445 if (sc->bge_flags & BGEF_PCIX) { 4446 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4447 + PCIX_CMD); 4448 /* Set max memory read byte count to 2K */ 4449 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4450 reg &= ~PCIX_CMD_BYTECNT_MASK; 4451 reg |= PCIX_CMD_BCNT_2048; 4452 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4453 /* 4454 * For 5704, set max outstanding split transaction 4455 * field to 0 (0 means it supports 1 request) 4456 */ 4457 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4458 | PCIX_CMD_BYTECNT_MASK); 4459 reg |= PCIX_CMD_BCNT_2048; 4460 } 4461 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4462 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4463 } 4464 4465 /* 5718 reset step 10, 57XX step 12 */ 4466 /* Enable memory arbiter. */ 4467 if (BGE_IS_5714_FAMILY(sc)) { 4468 val = CSR_READ_4(sc, BGE_MARB_MODE); 4469 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4470 } else 4471 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4472 4473 /* XXX 5721, 5751 and 5752 */ 4474 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4475 /* Step 19: */ 4476 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4477 /* Step 20: */ 4478 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4479 } 4480 4481 /* 5718 reset step 12, 57XX step 15 and 16 */ 4482 /* Fix up byte swapping */ 4483 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4484 4485 /* 5718 reset step 13, 57XX step 17 */ 4486 /* Poll until the firmware initialization is complete */ 4487 bge_poll_fw(sc); 4488 4489 /* 57XX step 21 */ 4490 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4491 pcireg_t msidata; 4492 4493 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4494 BGE_PCI_MSI_DATA); 4495 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4496 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4497 msidata); 4498 } 4499 4500 /* 57XX step 18 */ 4501 /* Write mac mode. */ 4502 val = CSR_READ_4(sc, BGE_MAC_MODE); 4503 /* Restore mac_mode_mask's bits using mac_mode */ 4504 val = (val & ~mac_mode_mask) | mac_mode; 4505 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4506 DELAY(40); 4507 4508 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4509 4510 /* 4511 * The 5704 in TBI mode apparently needs some special 4512 * adjustment to insure the SERDES drive level is set 4513 * to 1.2V. 4514 */ 4515 if (sc->bge_flags & BGEF_FIBER_TBI && 4516 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4517 uint32_t serdescfg; 4518 4519 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4520 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4521 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4522 } 4523 4524 if (sc->bge_flags & BGEF_PCIE && 4525 !BGE_IS_57765_PLUS(sc) && 4526 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4527 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4528 uint32_t v; 4529 4530 /* Enable PCI Express bug fix */ 4531 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4532 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4533 v | BGE_TLP_DATA_FIFO_PROTECT); 4534 } 4535 4536 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4537 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4538 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4539 4540 return 0; 4541 } 4542 4543 /* 4544 * Frame reception handling. This is called if there's a frame 4545 * on the receive return list. 4546 * 4547 * Note: we have to be able to handle two possibilities here: 4548 * 1) the frame is from the jumbo receive ring 4549 * 2) the frame is from the standard receive ring 4550 */ 4551 4552 static void 4553 bge_rxeof(struct bge_softc *sc) 4554 { 4555 struct ifnet *ifp; 4556 uint16_t rx_prod, rx_cons; 4557 int stdcnt = 0, jumbocnt = 0; 4558 bus_dmamap_t dmamap; 4559 bus_addr_t offset, toff; 4560 bus_size_t tlen; 4561 int tosync; 4562 4563 rx_cons = sc->bge_rx_saved_considx; 4564 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4565 4566 /* Nothing to do */ 4567 if (rx_cons == rx_prod) 4568 return; 4569 4570 ifp = &sc->ethercom.ec_if; 4571 4572 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4573 offsetof(struct bge_ring_data, bge_status_block), 4574 sizeof (struct bge_status_block), 4575 BUS_DMASYNC_POSTREAD); 4576 4577 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4578 tosync = rx_prod - rx_cons; 4579 4580 if (tosync != 0) 4581 rnd_add_uint32(&sc->rnd_source, tosync); 4582 4583 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4584 4585 if (tosync < 0) { 4586 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4587 sizeof (struct bge_rx_bd); 4588 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4589 toff, tlen, BUS_DMASYNC_POSTREAD); 4590 tosync = -tosync; 4591 } 4592 4593 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4594 offset, tosync * sizeof (struct bge_rx_bd), 4595 BUS_DMASYNC_POSTREAD); 4596 4597 while (rx_cons != rx_prod) { 4598 struct bge_rx_bd *cur_rx; 4599 uint32_t rxidx; 4600 struct mbuf *m = NULL; 4601 4602 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4603 4604 rxidx = cur_rx->bge_idx; 4605 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4606 4607 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4608 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4609 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4610 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4611 jumbocnt++; 4612 bus_dmamap_sync(sc->bge_dmatag, 4613 sc->bge_cdata.bge_rx_jumbo_map, 4614 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4615 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4616 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4617 ifp->if_ierrors++; 4618 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4619 continue; 4620 } 4621 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4622 NULL)== ENOBUFS) { 4623 ifp->if_ierrors++; 4624 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4625 continue; 4626 } 4627 } else { 4628 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4629 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4630 4631 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4632 stdcnt++; 4633 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4634 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4635 if (dmamap == NULL) { 4636 ifp->if_ierrors++; 4637 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4638 continue; 4639 } 4640 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4641 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4642 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4643 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4644 ifp->if_ierrors++; 4645 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4646 continue; 4647 } 4648 if (bge_newbuf_std(sc, sc->bge_std, 4649 NULL, dmamap) == ENOBUFS) { 4650 ifp->if_ierrors++; 4651 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4652 continue; 4653 } 4654 } 4655 4656 #ifndef __NO_STRICT_ALIGNMENT 4657 /* 4658 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4659 * the Rx buffer has the layer-2 header unaligned. 4660 * If our CPU requires alignment, re-align by copying. 4661 */ 4662 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4663 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4664 cur_rx->bge_len); 4665 m->m_data += ETHER_ALIGN; 4666 } 4667 #endif 4668 4669 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4670 m_set_rcvif(m, ifp); 4671 4672 bge_rxcsum(sc, cur_rx, m); 4673 4674 /* 4675 * If we received a packet with a vlan tag, pass it 4676 * to vlan_input() instead of ether_input(). 4677 */ 4678 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4679 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4680 } 4681 4682 if_percpuq_enqueue(ifp->if_percpuq, m); 4683 } 4684 4685 sc->bge_rx_saved_considx = rx_cons; 4686 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4687 if (stdcnt) 4688 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4689 if (jumbocnt) 4690 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4691 } 4692 4693 static void 4694 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4695 { 4696 4697 if (BGE_IS_57765_PLUS(sc)) { 4698 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4699 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4700 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4701 if ((cur_rx->bge_error_flag & 4702 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4703 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4704 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4705 m->m_pkthdr.csum_data = 4706 cur_rx->bge_tcp_udp_csum; 4707 m->m_pkthdr.csum_flags |= 4708 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4709 M_CSUM_DATA); 4710 } 4711 } 4712 } else { 4713 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4714 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4715 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4716 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4717 /* 4718 * Rx transport checksum-offload may also 4719 * have bugs with packets which, when transmitted, 4720 * were `runts' requiring padding. 4721 */ 4722 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4723 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4724 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4725 m->m_pkthdr.csum_data = 4726 cur_rx->bge_tcp_udp_csum; 4727 m->m_pkthdr.csum_flags |= 4728 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4729 M_CSUM_DATA); 4730 } 4731 } 4732 } 4733 4734 static void 4735 bge_txeof(struct bge_softc *sc) 4736 { 4737 struct bge_tx_bd *cur_tx = NULL; 4738 struct ifnet *ifp; 4739 struct txdmamap_pool_entry *dma; 4740 bus_addr_t offset, toff; 4741 bus_size_t tlen; 4742 int tosync; 4743 struct mbuf *m; 4744 4745 ifp = &sc->ethercom.ec_if; 4746 4747 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4748 offsetof(struct bge_ring_data, bge_status_block), 4749 sizeof (struct bge_status_block), 4750 BUS_DMASYNC_POSTREAD); 4751 4752 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4753 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4754 sc->bge_tx_saved_considx; 4755 4756 if (tosync != 0) 4757 rnd_add_uint32(&sc->rnd_source, tosync); 4758 4759 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4760 4761 if (tosync < 0) { 4762 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4763 sizeof (struct bge_tx_bd); 4764 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4765 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4766 tosync = -tosync; 4767 } 4768 4769 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4770 offset, tosync * sizeof (struct bge_tx_bd), 4771 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4772 4773 /* 4774 * Go through our tx ring and free mbufs for those 4775 * frames that have been sent. 4776 */ 4777 while (sc->bge_tx_saved_considx != 4778 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4779 uint32_t idx = 0; 4780 4781 idx = sc->bge_tx_saved_considx; 4782 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4783 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4784 ifp->if_opackets++; 4785 m = sc->bge_cdata.bge_tx_chain[idx]; 4786 if (m != NULL) { 4787 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4788 dma = sc->txdma[idx]; 4789 if (dma->is_dma32) { 4790 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4791 0, dma->dmamap32->dm_mapsize, 4792 BUS_DMASYNC_POSTWRITE); 4793 bus_dmamap_unload( 4794 sc->bge_dmatag32, dma->dmamap32); 4795 } else { 4796 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4797 0, dma->dmamap->dm_mapsize, 4798 BUS_DMASYNC_POSTWRITE); 4799 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4800 } 4801 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4802 sc->txdma[idx] = NULL; 4803 4804 m_freem(m); 4805 } 4806 sc->bge_txcnt--; 4807 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4808 ifp->if_timer = 0; 4809 } 4810 4811 if (cur_tx != NULL) 4812 ifp->if_flags &= ~IFF_OACTIVE; 4813 } 4814 4815 static int 4816 bge_intr(void *xsc) 4817 { 4818 struct bge_softc *sc; 4819 struct ifnet *ifp; 4820 uint32_t pcistate, statusword, statustag; 4821 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4822 4823 sc = xsc; 4824 ifp = &sc->ethercom.ec_if; 4825 4826 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4827 if (BGE_IS_5717_PLUS(sc)) 4828 intrmask = 0; 4829 4830 /* It is possible for the interrupt to arrive before 4831 * the status block is updated prior to the interrupt. 4832 * Reading the PCI State register will confirm whether the 4833 * interrupt is ours and will flush the status block. 4834 */ 4835 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4836 4837 /* read status word from status block */ 4838 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4839 offsetof(struct bge_ring_data, bge_status_block), 4840 sizeof (struct bge_status_block), 4841 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4842 statusword = sc->bge_rdata->bge_status_block.bge_status; 4843 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4844 4845 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4846 if (sc->bge_lasttag == statustag && 4847 (~pcistate & intrmask)) { 4848 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4849 return (0); 4850 } 4851 sc->bge_lasttag = statustag; 4852 } else { 4853 if (!(statusword & BGE_STATFLAG_UPDATED) && 4854 !(~pcistate & intrmask)) { 4855 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4856 return (0); 4857 } 4858 statustag = 0; 4859 } 4860 /* Ack interrupt and stop others from occurring. */ 4861 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4862 BGE_EVCNT_INCR(sc->bge_ev_intr); 4863 4864 /* clear status word */ 4865 sc->bge_rdata->bge_status_block.bge_status = 0; 4866 4867 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4868 offsetof(struct bge_ring_data, bge_status_block), 4869 sizeof (struct bge_status_block), 4870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4871 4872 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4873 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4874 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4875 bge_link_upd(sc); 4876 4877 if (ifp->if_flags & IFF_RUNNING) { 4878 /* Check RX return ring producer/consumer */ 4879 bge_rxeof(sc); 4880 4881 /* Check TX ring producer/consumer */ 4882 bge_txeof(sc); 4883 } 4884 4885 if (sc->bge_pending_rxintr_change) { 4886 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4887 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4888 4889 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4890 DELAY(10); 4891 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4892 4893 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4894 DELAY(10); 4895 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4896 4897 sc->bge_pending_rxintr_change = 0; 4898 } 4899 bge_handle_events(sc); 4900 4901 /* Re-enable interrupts. */ 4902 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4903 4904 if (ifp->if_flags & IFF_RUNNING) 4905 if_schedule_deferred_start(ifp); 4906 4907 return 1; 4908 } 4909 4910 static void 4911 bge_asf_driver_up(struct bge_softc *sc) 4912 { 4913 if (sc->bge_asf_mode & ASF_STACKUP) { 4914 /* Send ASF heartbeat aprox. every 2s */ 4915 if (sc->bge_asf_count) 4916 sc->bge_asf_count --; 4917 else { 4918 sc->bge_asf_count = 2; 4919 4920 bge_wait_for_event_ack(sc); 4921 4922 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4923 BGE_FW_CMD_DRV_ALIVE3); 4924 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4925 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4926 BGE_FW_HB_TIMEOUT_SEC); 4927 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4928 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4929 BGE_RX_CPU_DRV_EVENT); 4930 } 4931 } 4932 } 4933 4934 static void 4935 bge_tick(void *xsc) 4936 { 4937 struct bge_softc *sc = xsc; 4938 struct mii_data *mii = &sc->bge_mii; 4939 int s; 4940 4941 s = splnet(); 4942 4943 if (BGE_IS_5705_PLUS(sc)) 4944 bge_stats_update_regs(sc); 4945 else 4946 bge_stats_update(sc); 4947 4948 if (sc->bge_flags & BGEF_FIBER_TBI) { 4949 /* 4950 * Since in TBI mode auto-polling can't be used we should poll 4951 * link status manually. Here we register pending link event 4952 * and trigger interrupt. 4953 */ 4954 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4955 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4956 } else { 4957 /* 4958 * Do not touch PHY if we have link up. This could break 4959 * IPMI/ASF mode or produce extra input errors. 4960 * (extra input errors was reported for bcm5701 & bcm5704). 4961 */ 4962 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4963 mii_tick(mii); 4964 } 4965 4966 bge_asf_driver_up(sc); 4967 4968 if (!sc->bge_detaching) 4969 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4970 4971 splx(s); 4972 } 4973 4974 static void 4975 bge_stats_update_regs(struct bge_softc *sc) 4976 { 4977 struct ifnet *ifp = &sc->ethercom.ec_if; 4978 4979 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4980 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4981 4982 /* 4983 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4984 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4985 * (silicon bug). There's no reliable workaround so just 4986 * ignore the counter 4987 */ 4988 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4989 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5719_A0 && 4990 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5720_A0) { 4991 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4992 } 4993 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4994 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4995 } 4996 4997 static void 4998 bge_stats_update(struct bge_softc *sc) 4999 { 5000 struct ifnet *ifp = &sc->ethercom.ec_if; 5001 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 5002 5003 #define READ_STAT(sc, stats, stat) \ 5004 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 5005 5006 ifp->if_collisions += 5007 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 5008 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 5009 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 5010 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 5011 ifp->if_collisions; 5012 5013 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 5014 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 5015 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 5016 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 5017 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 5018 READ_STAT(sc, stats, 5019 xoffPauseFramesReceived.bge_addr_lo)); 5020 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 5021 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 5022 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 5023 READ_STAT(sc, stats, 5024 macControlFramesReceived.bge_addr_lo)); 5025 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 5026 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 5027 5028 #undef READ_STAT 5029 5030 #ifdef notdef 5031 ifp->if_collisions += 5032 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 5033 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 5034 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 5035 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 5036 ifp->if_collisions; 5037 #endif 5038 } 5039 5040 /* 5041 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5042 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5043 * but when such padded frames employ the bge IP/TCP checksum offload, 5044 * the hardware checksum assist gives incorrect results (possibly 5045 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5046 * If we pad such runts with zeros, the onboard checksum comes out correct. 5047 */ 5048 static inline int 5049 bge_cksum_pad(struct mbuf *pkt) 5050 { 5051 struct mbuf *last = NULL; 5052 int padlen; 5053 5054 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 5055 5056 /* if there's only the packet-header and we can pad there, use it. */ 5057 if (pkt->m_pkthdr.len == pkt->m_len && 5058 M_TRAILINGSPACE(pkt) >= padlen) { 5059 last = pkt; 5060 } else { 5061 /* 5062 * Walk packet chain to find last mbuf. We will either 5063 * pad there, or append a new mbuf and pad it 5064 * (thus perhaps avoiding the bcm5700 dma-min bug). 5065 */ 5066 for (last = pkt; last->m_next != NULL; last = last->m_next) { 5067 continue; /* do nothing */ 5068 } 5069 5070 /* `last' now points to last in chain. */ 5071 if (M_TRAILINGSPACE(last) < padlen) { 5072 /* Allocate new empty mbuf, pad it. Compact later. */ 5073 struct mbuf *n; 5074 MGET(n, M_DONTWAIT, MT_DATA); 5075 if (n == NULL) 5076 return ENOBUFS; 5077 n->m_len = 0; 5078 last->m_next = n; 5079 last = n; 5080 } 5081 } 5082 5083 KDASSERT(!M_READONLY(last)); 5084 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 5085 5086 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 5087 memset(mtod(last, char *) + last->m_len, 0, padlen); 5088 last->m_len += padlen; 5089 pkt->m_pkthdr.len += padlen; 5090 return 0; 5091 } 5092 5093 /* 5094 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5095 */ 5096 static inline int 5097 bge_compact_dma_runt(struct mbuf *pkt) 5098 { 5099 struct mbuf *m, *prev; 5100 int totlen; 5101 5102 prev = NULL; 5103 totlen = 0; 5104 5105 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 5106 int mlen = m->m_len; 5107 int shortfall = 8 - mlen ; 5108 5109 totlen += mlen; 5110 if (mlen == 0) 5111 continue; 5112 if (mlen >= 8) 5113 continue; 5114 5115 /* If we get here, mbuf data is too small for DMA engine. 5116 * Try to fix by shuffling data to prev or next in chain. 5117 * If that fails, do a compacting deep-copy of the whole chain. 5118 */ 5119 5120 /* Internal frag. If fits in prev, copy it there. */ 5121 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5122 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5123 prev->m_len += mlen; 5124 m->m_len = 0; 5125 /* XXX stitch chain */ 5126 prev->m_next = m_free(m); 5127 m = prev; 5128 continue; 5129 } 5130 else if (m->m_next != NULL && 5131 M_TRAILINGSPACE(m) >= shortfall && 5132 m->m_next->m_len >= (8 + shortfall)) { 5133 /* m is writable and have enough data in next, pull up. */ 5134 5135 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5136 shortfall); 5137 m->m_len += shortfall; 5138 m->m_next->m_len -= shortfall; 5139 m->m_next->m_data += shortfall; 5140 } 5141 else if (m->m_next == NULL || 1) { 5142 /* Got a runt at the very end of the packet. 5143 * borrow data from the tail of the preceding mbuf and 5144 * update its length in-place. (The original data is still 5145 * valid, so we can do this even if prev is not writable.) 5146 */ 5147 5148 /* if we'd make prev a runt, just move all of its data. */ 5149 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5150 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5151 5152 if ((prev->m_len - shortfall) < 8) 5153 shortfall = prev->m_len; 5154 5155 #ifdef notyet /* just do the safe slow thing for now */ 5156 if (!M_READONLY(m)) { 5157 if (M_LEADINGSPACE(m) < shorfall) { 5158 void *m_dat; 5159 m_dat = (m->m_flags & M_PKTHDR) ? 5160 m->m_pktdat : m->dat; 5161 memmove(m_dat, mtod(m, void*), m->m_len); 5162 m->m_data = m_dat; 5163 } 5164 } else 5165 #endif /* just do the safe slow thing */ 5166 { 5167 struct mbuf * n = NULL; 5168 int newprevlen = prev->m_len - shortfall; 5169 5170 MGET(n, M_NOWAIT, MT_DATA); 5171 if (n == NULL) 5172 return ENOBUFS; 5173 KASSERT(m->m_len + shortfall < MLEN 5174 /*, 5175 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5176 5177 /* first copy the data we're stealing from prev */ 5178 memcpy(n->m_data, prev->m_data + newprevlen, 5179 shortfall); 5180 5181 /* update prev->m_len accordingly */ 5182 prev->m_len -= shortfall; 5183 5184 /* copy data from runt m */ 5185 memcpy(n->m_data + shortfall, m->m_data, 5186 m->m_len); 5187 5188 /* n holds what we stole from prev, plus m */ 5189 n->m_len = shortfall + m->m_len; 5190 5191 /* stitch n into chain and free m */ 5192 n->m_next = m->m_next; 5193 prev->m_next = n; 5194 /* KASSERT(m->m_next == NULL); */ 5195 m->m_next = NULL; 5196 m_free(m); 5197 m = n; /* for continuing loop */ 5198 } 5199 } 5200 } 5201 return 0; 5202 } 5203 5204 /* 5205 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5206 * pointers to descriptors. 5207 */ 5208 static int 5209 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5210 { 5211 struct ifnet *ifp = &sc->ethercom.ec_if; 5212 struct bge_tx_bd *f, *prev_f; 5213 uint32_t frag, cur; 5214 uint16_t csum_flags = 0; 5215 uint16_t txbd_tso_flags = 0; 5216 struct txdmamap_pool_entry *dma; 5217 bus_dmamap_t dmamap; 5218 bus_dma_tag_t dmatag; 5219 int i = 0; 5220 int use_tso, maxsegsize, error; 5221 bool have_vtag; 5222 uint16_t vtag; 5223 bool remap; 5224 5225 if (m_head->m_pkthdr.csum_flags) { 5226 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5227 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5228 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 5229 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5230 } 5231 5232 /* 5233 * If we were asked to do an outboard checksum, and the NIC 5234 * has the bug where it sometimes adds in the Ethernet padding, 5235 * explicitly pad with zeros so the cksum will be correct either way. 5236 * (For now, do this for all chip versions, until newer 5237 * are confirmed to not require the workaround.) 5238 */ 5239 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5240 #ifdef notyet 5241 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5242 #endif 5243 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5244 goto check_dma_bug; 5245 5246 if (bge_cksum_pad(m_head) != 0) 5247 return ENOBUFS; 5248 5249 check_dma_bug: 5250 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5251 goto doit; 5252 5253 /* 5254 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5255 * less than eight bytes. If we encounter a teeny mbuf 5256 * at the end of a chain, we can pad. Otherwise, copy. 5257 */ 5258 if (bge_compact_dma_runt(m_head) != 0) 5259 return ENOBUFS; 5260 5261 doit: 5262 dma = SLIST_FIRST(&sc->txdma_list); 5263 if (dma == NULL) { 5264 ifp->if_flags |= IFF_OACTIVE; 5265 return ENOBUFS; 5266 } 5267 dmamap = dma->dmamap; 5268 dmatag = sc->bge_dmatag; 5269 dma->is_dma32 = false; 5270 5271 /* 5272 * Set up any necessary TSO state before we start packing... 5273 */ 5274 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5275 if (!use_tso) { 5276 maxsegsize = 0; 5277 } else { /* TSO setup */ 5278 unsigned mss; 5279 struct ether_header *eh; 5280 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5281 unsigned bge_hlen; 5282 struct mbuf * m0 = m_head; 5283 struct ip *ip; 5284 struct tcphdr *th; 5285 int iphl, hlen; 5286 5287 /* 5288 * XXX It would be nice if the mbuf pkthdr had offset 5289 * fields for the protocol headers. 5290 */ 5291 5292 eh = mtod(m0, struct ether_header *); 5293 switch (htons(eh->ether_type)) { 5294 case ETHERTYPE_IP: 5295 offset = ETHER_HDR_LEN; 5296 break; 5297 5298 case ETHERTYPE_VLAN: 5299 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5300 break; 5301 5302 default: 5303 /* 5304 * Don't support this protocol or encapsulation. 5305 */ 5306 return ENOBUFS; 5307 } 5308 5309 /* 5310 * TCP/IP headers are in the first mbuf; we can do 5311 * this the easy way. 5312 */ 5313 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5314 hlen = iphl + offset; 5315 if (__predict_false(m0->m_len < 5316 (hlen + sizeof(struct tcphdr)))) { 5317 5318 aprint_error_dev(sc->bge_dev, 5319 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5320 "not handled yet\n", 5321 m0->m_len, hlen+ sizeof(struct tcphdr)); 5322 #ifdef NOTYET 5323 /* 5324 * XXX jonathan (at) NetBSD.org: untested. 5325 * how to force this branch to be taken? 5326 */ 5327 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5328 5329 m_copydata(m0, offset, sizeof(ip), &ip); 5330 m_copydata(m0, hlen, sizeof(th), &th); 5331 5332 ip.ip_len = 0; 5333 5334 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5335 sizeof(ip.ip_len), &ip.ip_len); 5336 5337 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5338 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5339 5340 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5341 sizeof(th.th_sum), &th.th_sum); 5342 5343 hlen += th.th_off << 2; 5344 iptcp_opt_words = hlen; 5345 #else 5346 /* 5347 * if_wm "hard" case not yet supported, can we not 5348 * mandate it out of existence? 5349 */ 5350 (void) ip; (void)th; (void) ip_tcp_hlen; 5351 5352 return ENOBUFS; 5353 #endif 5354 } else { 5355 ip = (struct ip *) (mtod(m0, char *) + offset); 5356 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5357 ip_tcp_hlen = iphl + (th->th_off << 2); 5358 5359 /* Total IP/TCP options, in 32-bit words */ 5360 iptcp_opt_words = (ip_tcp_hlen 5361 - sizeof(struct tcphdr) 5362 - sizeof(struct ip)) >> 2; 5363 } 5364 if (BGE_IS_575X_PLUS(sc)) { 5365 th->th_sum = 0; 5366 csum_flags = 0; 5367 } else { 5368 /* 5369 * XXX jonathan (at) NetBSD.org: 5705 untested. 5370 * Requires TSO firmware patch for 5701/5703/5704. 5371 */ 5372 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5373 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5374 } 5375 5376 mss = m_head->m_pkthdr.segsz; 5377 txbd_tso_flags |= 5378 BGE_TXBDFLAG_CPU_PRE_DMA | 5379 BGE_TXBDFLAG_CPU_POST_DMA; 5380 5381 /* 5382 * Our NIC TSO-assist assumes TSO has standard, optionless 5383 * IPv4 and TCP headers, which total 40 bytes. By default, 5384 * the NIC copies 40 bytes of IP/TCP header from the 5385 * supplied header into the IP/TCP header portion of 5386 * each post-TSO-segment. If the supplied packet has IP or 5387 * TCP options, we need to tell the NIC to copy those extra 5388 * bytes into each post-TSO header, in addition to the normal 5389 * 40-byte IP/TCP header (and to leave space accordingly). 5390 * Unfortunately, the driver encoding of option length 5391 * varies across different ASIC families. 5392 */ 5393 tcp_seg_flags = 0; 5394 bge_hlen = ip_tcp_hlen >> 2; 5395 if (BGE_IS_5717_PLUS(sc)) { 5396 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5397 txbd_tso_flags |= 5398 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5399 } else if (BGE_IS_5705_PLUS(sc)) { 5400 tcp_seg_flags = 5401 bge_hlen << 11; 5402 } else { 5403 /* XXX iptcp_opt_words or bge_hlen ? */ 5404 txbd_tso_flags |= 5405 iptcp_opt_words << 12; 5406 } 5407 maxsegsize = mss | tcp_seg_flags; 5408 ip->ip_len = htons(mss + ip_tcp_hlen); 5409 ip->ip_sum = 0; 5410 5411 } /* TSO setup */ 5412 5413 have_vtag = vlan_has_tag(m_head); 5414 if (have_vtag) 5415 vtag = vlan_get_tag(m_head); 5416 5417 /* 5418 * Start packing the mbufs in this chain into 5419 * the fragment pointers. Stop when we run out 5420 * of fragments or hit the end of the mbuf chain. 5421 */ 5422 remap = true; 5423 load_again: 5424 error = bus_dmamap_load_mbuf(dmatag, dmamap, 5425 m_head, BUS_DMA_NOWAIT); 5426 if (__predict_false(error)) { 5427 if (error == EFBIG && remap) { 5428 struct mbuf *m; 5429 remap = false; 5430 m = m_defrag(m_head, M_NOWAIT); 5431 if (m != NULL) { 5432 KASSERT(m == m_head); 5433 goto load_again; 5434 } 5435 } 5436 return error; 5437 } 5438 /* 5439 * Sanity check: avoid coming within 16 descriptors 5440 * of the end of the ring. 5441 */ 5442 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5443 BGE_TSO_PRINTF(("%s: " 5444 " dmamap_load_mbuf too close to ring wrap\n", 5445 device_xname(sc->bge_dev))); 5446 goto fail_unload; 5447 } 5448 5449 /* Iterate over dmap-map fragments. */ 5450 f = prev_f = NULL; 5451 cur = frag = *txidx; 5452 5453 for (i = 0; i < dmamap->dm_nsegs; i++) { 5454 f = &sc->bge_rdata->bge_tx_ring[frag]; 5455 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5456 break; 5457 5458 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5459 f->bge_len = dmamap->dm_segs[i].ds_len; 5460 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5461 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5462 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5463 (prev_f != NULL && 5464 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5465 ) { 5466 /* 5467 * watchdog timeout issue was observed with TSO, 5468 * limiting DMA address space to 32bits seems to 5469 * address the issue. 5470 */ 5471 bus_dmamap_unload(dmatag, dmamap); 5472 dmatag = sc->bge_dmatag32; 5473 dmamap = dma->dmamap32; 5474 dma->is_dma32 = true; 5475 remap = true; 5476 goto load_again; 5477 } 5478 5479 /* 5480 * For 5751 and follow-ons, for TSO we must turn 5481 * off checksum-assist flag in the tx-descr, and 5482 * supply the ASIC-revision-specific encoding 5483 * of TSO flags and segsize. 5484 */ 5485 if (use_tso) { 5486 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5487 f->bge_rsvd = maxsegsize; 5488 f->bge_flags = csum_flags | txbd_tso_flags; 5489 } else { 5490 f->bge_rsvd = 0; 5491 f->bge_flags = 5492 (csum_flags | txbd_tso_flags) & 0x0fff; 5493 } 5494 } else { 5495 f->bge_rsvd = 0; 5496 f->bge_flags = csum_flags; 5497 } 5498 5499 if (have_vtag) { 5500 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5501 f->bge_vlan_tag = vtag; 5502 } else { 5503 f->bge_vlan_tag = 0; 5504 } 5505 prev_f = f; 5506 cur = frag; 5507 BGE_INC(frag, BGE_TX_RING_CNT); 5508 } 5509 5510 if (i < dmamap->dm_nsegs) { 5511 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5512 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5513 goto fail_unload; 5514 } 5515 5516 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5517 BUS_DMASYNC_PREWRITE); 5518 5519 if (frag == sc->bge_tx_saved_considx) { 5520 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5521 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5522 5523 goto fail_unload; 5524 } 5525 5526 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5527 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5528 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5529 sc->txdma[cur] = dma; 5530 sc->bge_txcnt += dmamap->dm_nsegs; 5531 5532 *txidx = frag; 5533 5534 return 0; 5535 5536 fail_unload: 5537 bus_dmamap_unload(dmatag, dmamap); 5538 ifp->if_flags |= IFF_OACTIVE; 5539 5540 return ENOBUFS; 5541 } 5542 5543 /* 5544 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5545 * to the mbuf data regions directly in the transmit descriptors. 5546 */ 5547 static void 5548 bge_start(struct ifnet *ifp) 5549 { 5550 struct bge_softc *sc; 5551 struct mbuf *m_head = NULL; 5552 struct mbuf *m; 5553 uint32_t prodidx; 5554 int pkts = 0; 5555 int error; 5556 5557 sc = ifp->if_softc; 5558 5559 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5560 return; 5561 5562 prodidx = sc->bge_tx_prodidx; 5563 5564 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5565 IFQ_POLL(&ifp->if_snd, m_head); 5566 if (m_head == NULL) 5567 break; 5568 5569 #if 0 5570 /* 5571 * XXX 5572 * safety overkill. If this is a fragmented packet chain 5573 * with delayed TCP/UDP checksums, then only encapsulate 5574 * it if we have enough descriptors to handle the entire 5575 * chain at once. 5576 * (paranoia -- may not actually be needed) 5577 */ 5578 if (m_head->m_flags & M_FIRSTFRAG && 5579 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5580 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5581 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5582 ifp->if_flags |= IFF_OACTIVE; 5583 break; 5584 } 5585 } 5586 #endif 5587 5588 /* 5589 * Pack the data into the transmit ring. If we 5590 * don't have room, set the OACTIVE flag and wait 5591 * for the NIC to drain the ring. 5592 */ 5593 error = bge_encap(sc, m_head, &prodidx); 5594 if (__predict_false(error)) { 5595 if (ifp->if_flags & IFF_OACTIVE) { 5596 /* just wait for the transmit ring to drain */ 5597 break; 5598 } 5599 IFQ_DEQUEUE(&ifp->if_snd, m); 5600 KASSERT(m == m_head); 5601 m_freem(m_head); 5602 continue; 5603 } 5604 5605 /* now we are committed to transmit the packet */ 5606 IFQ_DEQUEUE(&ifp->if_snd, m); 5607 KASSERT(m == m_head); 5608 pkts++; 5609 5610 /* 5611 * If there's a BPF listener, bounce a copy of this frame 5612 * to him. 5613 */ 5614 bpf_mtap(ifp, m_head, BPF_D_OUT); 5615 } 5616 if (pkts == 0) 5617 return; 5618 5619 /* Transmit */ 5620 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5621 /* 5700 b2 errata */ 5622 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5623 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5624 5625 sc->bge_tx_prodidx = prodidx; 5626 5627 /* 5628 * Set a timeout in case the chip goes out to lunch. 5629 */ 5630 ifp->if_timer = 5; 5631 } 5632 5633 static int 5634 bge_init(struct ifnet *ifp) 5635 { 5636 struct bge_softc *sc = ifp->if_softc; 5637 const uint16_t *m; 5638 uint32_t mode, reg; 5639 int s, error = 0; 5640 5641 s = splnet(); 5642 5643 ifp = &sc->ethercom.ec_if; 5644 5645 /* Cancel pending I/O and flush buffers. */ 5646 bge_stop(ifp, 0); 5647 5648 bge_stop_fw(sc); 5649 bge_sig_pre_reset(sc, BGE_RESET_START); 5650 bge_reset(sc); 5651 bge_sig_legacy(sc, BGE_RESET_START); 5652 5653 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5654 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5655 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5656 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5657 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5658 5659 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5660 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5661 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5662 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5663 5664 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5665 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5666 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5667 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5668 5669 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5670 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5671 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5672 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5673 } 5674 5675 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5676 pcireg_t aercap; 5677 5678 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5679 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5680 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5681 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5682 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5683 5684 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5685 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5686 | BGE_PCIE_EIDLE_DELAY_13CLK; 5687 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5688 5689 /* Clear correctable error */ 5690 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5691 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5692 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5693 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5694 5695 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5696 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5697 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5698 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5699 } 5700 5701 bge_sig_post_reset(sc, BGE_RESET_START); 5702 5703 bge_chipinit(sc); 5704 5705 /* 5706 * Init the various state machines, ring 5707 * control blocks and firmware. 5708 */ 5709 error = bge_blockinit(sc); 5710 if (error != 0) { 5711 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5712 error); 5713 splx(s); 5714 return error; 5715 } 5716 5717 ifp = &sc->ethercom.ec_if; 5718 5719 /* 5718 step 25, 57XX step 54 */ 5720 /* Specify MTU. */ 5721 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5722 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5723 5724 /* 5718 step 23 */ 5725 /* Load our MAC address. */ 5726 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5727 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5728 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5729 5730 /* Enable or disable promiscuous mode as needed. */ 5731 if (ifp->if_flags & IFF_PROMISC) 5732 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5733 else 5734 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5735 5736 /* Program multicast filter. */ 5737 bge_setmulti(sc); 5738 5739 /* Init RX ring. */ 5740 bge_init_rx_ring_std(sc); 5741 5742 /* 5743 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5744 * memory to insure that the chip has in fact read the first 5745 * entry of the ring. 5746 */ 5747 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5748 uint32_t v, i; 5749 for (i = 0; i < 10; i++) { 5750 DELAY(20); 5751 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5752 if (v == (MCLBYTES - ETHER_ALIGN)) 5753 break; 5754 } 5755 if (i == 10) 5756 aprint_error_dev(sc->bge_dev, 5757 "5705 A0 chip failed to load RX ring\n"); 5758 } 5759 5760 /* Init jumbo RX ring. */ 5761 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5762 bge_init_rx_ring_jumbo(sc); 5763 5764 /* Init our RX return ring index */ 5765 sc->bge_rx_saved_considx = 0; 5766 5767 /* Init TX ring. */ 5768 bge_init_tx_ring(sc); 5769 5770 /* 5718 step 63, 57XX step 94 */ 5771 /* Enable TX MAC state machine lockup fix. */ 5772 mode = CSR_READ_4(sc, BGE_TX_MODE); 5773 if (BGE_IS_5755_PLUS(sc) || 5774 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5775 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5776 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5777 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5778 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5779 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5780 } 5781 5782 /* Turn on transmitter */ 5783 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5784 /* 5718 step 64 */ 5785 DELAY(100); 5786 5787 /* 5718 step 65, 57XX step 95 */ 5788 /* Turn on receiver */ 5789 mode = CSR_READ_4(sc, BGE_RX_MODE); 5790 if (BGE_IS_5755_PLUS(sc)) 5791 mode |= BGE_RXMODE_IPV6_ENABLE; 5792 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5793 /* 5718 step 66 */ 5794 DELAY(10); 5795 5796 /* 5718 step 12, 57XX step 37 */ 5797 /* 5798 * XXX Doucments of 5718 series and 577xx say the recommended value 5799 * is 1, but tg3 set 1 only on 57765 series. 5800 */ 5801 if (BGE_IS_57765_PLUS(sc)) 5802 reg = 1; 5803 else 5804 reg = 2; 5805 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5806 5807 /* Tell firmware we're alive. */ 5808 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5809 5810 /* Enable host interrupts. */ 5811 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5812 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5813 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5814 5815 if ((error = bge_ifmedia_upd(ifp)) != 0) 5816 goto out; 5817 5818 ifp->if_flags |= IFF_RUNNING; 5819 ifp->if_flags &= ~IFF_OACTIVE; 5820 5821 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5822 5823 out: 5824 sc->bge_if_flags = ifp->if_flags; 5825 splx(s); 5826 5827 return error; 5828 } 5829 5830 /* 5831 * Set media options. 5832 */ 5833 static int 5834 bge_ifmedia_upd(struct ifnet *ifp) 5835 { 5836 struct bge_softc *sc = ifp->if_softc; 5837 struct mii_data *mii = &sc->bge_mii; 5838 struct ifmedia *ifm = &sc->bge_ifmedia; 5839 int rc; 5840 5841 /* If this is a 1000baseX NIC, enable the TBI port. */ 5842 if (sc->bge_flags & BGEF_FIBER_TBI) { 5843 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5844 return EINVAL; 5845 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5846 case IFM_AUTO: 5847 /* 5848 * The BCM5704 ASIC appears to have a special 5849 * mechanism for programming the autoneg 5850 * advertisement registers in TBI mode. 5851 */ 5852 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5853 uint32_t sgdig; 5854 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5855 if (sgdig & BGE_SGDIGSTS_DONE) { 5856 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5857 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5858 sgdig |= BGE_SGDIGCFG_AUTO | 5859 BGE_SGDIGCFG_PAUSE_CAP | 5860 BGE_SGDIGCFG_ASYM_PAUSE; 5861 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5862 sgdig | BGE_SGDIGCFG_SEND); 5863 DELAY(5); 5864 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5865 sgdig); 5866 } 5867 } 5868 break; 5869 case IFM_1000_SX: 5870 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5871 BGE_CLRBIT(sc, BGE_MAC_MODE, 5872 BGE_MACMODE_HALF_DUPLEX); 5873 } else { 5874 BGE_SETBIT(sc, BGE_MAC_MODE, 5875 BGE_MACMODE_HALF_DUPLEX); 5876 } 5877 DELAY(40); 5878 break; 5879 default: 5880 return EINVAL; 5881 } 5882 /* XXX 802.3x flow control for 1000BASE-SX */ 5883 return 0; 5884 } 5885 5886 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5887 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5888 uint32_t reg; 5889 5890 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5891 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5892 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5893 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5894 } 5895 } 5896 5897 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5898 if ((rc = mii_mediachg(mii)) == ENXIO) 5899 return 0; 5900 5901 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5902 uint32_t reg; 5903 5904 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5905 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5906 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5907 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5908 delay(40); 5909 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5910 } 5911 } 5912 5913 /* 5914 * Force an interrupt so that we will call bge_link_upd 5915 * if needed and clear any pending link state attention. 5916 * Without this we are not getting any further interrupts 5917 * for link state changes and thus will not UP the link and 5918 * not be able to send in bge_start. The only way to get 5919 * things working was to receive a packet and get a RX intr. 5920 */ 5921 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5922 sc->bge_flags & BGEF_IS_5788) 5923 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5924 else 5925 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5926 5927 return rc; 5928 } 5929 5930 /* 5931 * Report current media status. 5932 */ 5933 static void 5934 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5935 { 5936 struct bge_softc *sc = ifp->if_softc; 5937 struct mii_data *mii = &sc->bge_mii; 5938 5939 if (sc->bge_flags & BGEF_FIBER_TBI) { 5940 ifmr->ifm_status = IFM_AVALID; 5941 ifmr->ifm_active = IFM_ETHER; 5942 if (CSR_READ_4(sc, BGE_MAC_STS) & 5943 BGE_MACSTAT_TBI_PCS_SYNCHED) 5944 ifmr->ifm_status |= IFM_ACTIVE; 5945 ifmr->ifm_active |= IFM_1000_SX; 5946 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5947 ifmr->ifm_active |= IFM_HDX; 5948 else 5949 ifmr->ifm_active |= IFM_FDX; 5950 return; 5951 } 5952 5953 mii_pollstat(mii); 5954 ifmr->ifm_status = mii->mii_media_status; 5955 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5956 sc->bge_flowflags; 5957 } 5958 5959 static int 5960 bge_ifflags_cb(struct ethercom *ec) 5961 { 5962 struct ifnet *ifp = &ec->ec_if; 5963 struct bge_softc *sc = ifp->if_softc; 5964 int change = ifp->if_flags ^ sc->bge_if_flags; 5965 5966 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5967 return ENETRESET; 5968 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5969 return 0; 5970 5971 if ((ifp->if_flags & IFF_PROMISC) == 0) 5972 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5973 else 5974 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5975 5976 bge_setmulti(sc); 5977 5978 sc->bge_if_flags = ifp->if_flags; 5979 return 0; 5980 } 5981 5982 static int 5983 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5984 { 5985 struct bge_softc *sc = ifp->if_softc; 5986 struct ifreq *ifr = (struct ifreq *) data; 5987 int s, error = 0; 5988 struct mii_data *mii; 5989 5990 s = splnet(); 5991 5992 switch (command) { 5993 case SIOCSIFMEDIA: 5994 /* XXX Flow control is not supported for 1000BASE-SX */ 5995 if (sc->bge_flags & BGEF_FIBER_TBI) { 5996 ifr->ifr_media &= ~IFM_ETH_FMASK; 5997 sc->bge_flowflags = 0; 5998 } 5999 6000 /* Flow control requires full-duplex mode. */ 6001 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 6002 (ifr->ifr_media & IFM_FDX) == 0) { 6003 ifr->ifr_media &= ~IFM_ETH_FMASK; 6004 } 6005 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 6006 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 6007 /* We can do both TXPAUSE and RXPAUSE. */ 6008 ifr->ifr_media |= 6009 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 6010 } 6011 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 6012 } 6013 /* FALLTHROUGH */ 6014 case SIOCGIFMEDIA: 6015 if (sc->bge_flags & BGEF_FIBER_TBI) { 6016 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 6017 command); 6018 } else { 6019 mii = &sc->bge_mii; 6020 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 6021 command); 6022 } 6023 break; 6024 default: 6025 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 6026 break; 6027 6028 error = 0; 6029 6030 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 6031 ; 6032 else if (ifp->if_flags & IFF_RUNNING) 6033 bge_setmulti(sc); 6034 break; 6035 } 6036 6037 splx(s); 6038 6039 return error; 6040 } 6041 6042 static void 6043 bge_watchdog(struct ifnet *ifp) 6044 { 6045 struct bge_softc *sc; 6046 uint32_t status; 6047 6048 sc = ifp->if_softc; 6049 6050 /* If pause frames are active then don't reset the hardware. */ 6051 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 6052 status = CSR_READ_4(sc, BGE_RX_STS); 6053 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 6054 /* 6055 * If link partner has us in XOFF state then wait for 6056 * the condition to clear. 6057 */ 6058 CSR_WRITE_4(sc, BGE_RX_STS, status); 6059 ifp->if_timer = 5; 6060 return; 6061 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 6062 (status & BGE_RXSTAT_RCVD_XON) != 0) { 6063 /* 6064 * If link partner has us in XOFF state then wait for 6065 * the condition to clear. 6066 */ 6067 CSR_WRITE_4(sc, BGE_RX_STS, status); 6068 ifp->if_timer = 5; 6069 return; 6070 } 6071 /* 6072 * Any other condition is unexpected and the controller 6073 * should be reset. 6074 */ 6075 } 6076 6077 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 6078 6079 ifp->if_flags &= ~IFF_RUNNING; 6080 bge_init(ifp); 6081 6082 ifp->if_oerrors++; 6083 } 6084 6085 static void 6086 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 6087 { 6088 int i; 6089 6090 BGE_CLRBIT_FLUSH(sc, reg, bit); 6091 6092 for (i = 0; i < 1000; i++) { 6093 delay(100); 6094 if ((CSR_READ_4(sc, reg) & bit) == 0) 6095 return; 6096 } 6097 6098 /* 6099 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 6100 * on some environment (and once after boot?) 6101 */ 6102 if (reg != BGE_SRS_MODE) 6103 aprint_error_dev(sc->bge_dev, 6104 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 6105 (u_long)reg, bit); 6106 } 6107 6108 /* 6109 * Stop the adapter and free any mbufs allocated to the 6110 * RX and TX lists. 6111 */ 6112 static void 6113 bge_stop(struct ifnet *ifp, int disable) 6114 { 6115 struct bge_softc *sc = ifp->if_softc; 6116 6117 if (disable) { 6118 sc->bge_detaching = 1; 6119 callout_halt(&sc->bge_timeout, NULL); 6120 } else 6121 callout_stop(&sc->bge_timeout); 6122 6123 /* Disable host interrupts. */ 6124 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6125 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6126 6127 /* 6128 * Tell firmware we're shutting down. 6129 */ 6130 bge_stop_fw(sc); 6131 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6132 6133 /* 6134 * Disable all of the receiver blocks. 6135 */ 6136 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6137 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6138 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6139 if (BGE_IS_5700_FAMILY(sc)) 6140 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6141 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6142 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6143 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6144 6145 /* 6146 * Disable all of the transmit blocks. 6147 */ 6148 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6149 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6150 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6151 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6152 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6153 if (BGE_IS_5700_FAMILY(sc)) 6154 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6155 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6156 6157 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6158 delay(40); 6159 6160 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6161 6162 /* 6163 * Shut down all of the memory managers and related 6164 * state machines. 6165 */ 6166 /* 5718 step 5a,5b */ 6167 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6168 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6169 if (BGE_IS_5700_FAMILY(sc)) 6170 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6171 6172 /* 5718 step 5c,5d */ 6173 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6174 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6175 6176 if (BGE_IS_5700_FAMILY(sc)) { 6177 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6178 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6179 } 6180 6181 bge_reset(sc); 6182 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6183 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6184 6185 /* 6186 * Keep the ASF firmware running if up. 6187 */ 6188 if (sc->bge_asf_mode & ASF_STACKUP) 6189 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6190 else 6191 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6192 6193 /* Free the RX lists. */ 6194 bge_free_rx_ring_std(sc, disable); 6195 6196 /* Free jumbo RX list. */ 6197 if (BGE_IS_JUMBO_CAPABLE(sc)) 6198 bge_free_rx_ring_jumbo(sc); 6199 6200 /* Free TX buffers. */ 6201 bge_free_tx_ring(sc, disable); 6202 6203 /* 6204 * Isolate/power down the PHY. 6205 */ 6206 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6207 mii_down(&sc->bge_mii); 6208 6209 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6210 6211 /* Clear MAC's link state (PHY may still have link UP). */ 6212 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6213 6214 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6215 } 6216 6217 static void 6218 bge_link_upd(struct bge_softc *sc) 6219 { 6220 struct ifnet *ifp = &sc->ethercom.ec_if; 6221 struct mii_data *mii = &sc->bge_mii; 6222 uint32_t status; 6223 uint16_t phyval; 6224 int link; 6225 6226 /* Clear 'pending link event' flag */ 6227 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6228 6229 /* 6230 * Process link state changes. 6231 * Grrr. The link status word in the status block does 6232 * not work correctly on the BCM5700 rev AX and BX chips, 6233 * according to all available information. Hence, we have 6234 * to enable MII interrupts in order to properly obtain 6235 * async link changes. Unfortunately, this also means that 6236 * we have to read the MAC status register to detect link 6237 * changes, thereby adding an additional register access to 6238 * the interrupt handler. 6239 */ 6240 6241 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6242 status = CSR_READ_4(sc, BGE_MAC_STS); 6243 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6244 mii_pollstat(mii); 6245 6246 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6247 mii->mii_media_status & IFM_ACTIVE && 6248 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6249 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6250 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6251 (!(mii->mii_media_status & IFM_ACTIVE) || 6252 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6253 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6254 6255 /* Clear the interrupt */ 6256 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6257 BGE_EVTENB_MI_INTERRUPT); 6258 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6259 BRGPHY_MII_ISR, &phyval); 6260 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6261 BRGPHY_MII_IMR, BRGPHY_INTRS); 6262 } 6263 return; 6264 } 6265 6266 if (sc->bge_flags & BGEF_FIBER_TBI) { 6267 status = CSR_READ_4(sc, BGE_MAC_STS); 6268 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6269 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6270 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6271 if (BGE_ASICREV(sc->bge_chipid) 6272 == BGE_ASICREV_BCM5704) { 6273 BGE_CLRBIT(sc, BGE_MAC_MODE, 6274 BGE_MACMODE_TBI_SEND_CFGS); 6275 DELAY(40); 6276 } 6277 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6278 if_link_state_change(ifp, LINK_STATE_UP); 6279 } 6280 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6281 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6282 if_link_state_change(ifp, LINK_STATE_DOWN); 6283 } 6284 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6285 /* 6286 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6287 * bit in status word always set. Workaround this bug by 6288 * reading PHY link status directly. 6289 */ 6290 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6291 BGE_STS_LINK : 0; 6292 6293 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6294 mii_pollstat(mii); 6295 6296 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6297 mii->mii_media_status & IFM_ACTIVE && 6298 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6299 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6300 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6301 (!(mii->mii_media_status & IFM_ACTIVE) || 6302 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6303 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6304 } 6305 } else { 6306 /* 6307 * For controllers that call mii_tick, we have to poll 6308 * link status. 6309 */ 6310 mii_pollstat(mii); 6311 } 6312 6313 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6314 uint32_t reg, scale; 6315 6316 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6317 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6318 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6319 scale = 65; 6320 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6321 scale = 6; 6322 else 6323 scale = 12; 6324 6325 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6326 ~BGE_MISCCFG_TIMER_PRESCALER; 6327 reg |= scale << 1; 6328 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6329 } 6330 /* Clear the attention */ 6331 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6332 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6333 BGE_MACSTAT_LINK_CHANGED); 6334 } 6335 6336 static int 6337 bge_sysctl_verify(SYSCTLFN_ARGS) 6338 { 6339 int error, t; 6340 struct sysctlnode node; 6341 6342 node = *rnode; 6343 t = *(int*)rnode->sysctl_data; 6344 node.sysctl_data = &t; 6345 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6346 if (error || newp == NULL) 6347 return error; 6348 6349 #if 0 6350 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6351 node.sysctl_num, rnode->sysctl_num)); 6352 #endif 6353 6354 if (node.sysctl_num == bge_rxthresh_nodenum) { 6355 if (t < 0 || t >= NBGE_RX_THRESH) 6356 return EINVAL; 6357 bge_update_all_threshes(t); 6358 } else 6359 return EINVAL; 6360 6361 *(int*)rnode->sysctl_data = t; 6362 6363 return 0; 6364 } 6365 6366 /* 6367 * Set up sysctl(3) MIB, hw.bge.*. 6368 */ 6369 static void 6370 bge_sysctl_init(struct bge_softc *sc) 6371 { 6372 int rc, bge_root_num; 6373 const struct sysctlnode *node; 6374 6375 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6376 0, CTLTYPE_NODE, "bge", 6377 SYSCTL_DESCR("BGE interface controls"), 6378 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6379 goto out; 6380 } 6381 6382 bge_root_num = node->sysctl_num; 6383 6384 /* BGE Rx interrupt mitigation level */ 6385 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6386 CTLFLAG_READWRITE, 6387 CTLTYPE_INT, "rx_lvl", 6388 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6389 bge_sysctl_verify, 0, 6390 &bge_rx_thresh_lvl, 6391 0, CTL_HW, bge_root_num, CTL_CREATE, 6392 CTL_EOL)) != 0) { 6393 goto out; 6394 } 6395 6396 bge_rxthresh_nodenum = node->sysctl_num; 6397 6398 return; 6399 6400 out: 6401 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6402 } 6403 6404 #ifdef BGE_DEBUG 6405 void 6406 bge_debug_info(struct bge_softc *sc) 6407 { 6408 6409 printf("Hardware Flags:\n"); 6410 if (BGE_IS_57765_PLUS(sc)) 6411 printf(" - 57765 Plus\n"); 6412 if (BGE_IS_5717_PLUS(sc)) 6413 printf(" - 5717 Plus\n"); 6414 if (BGE_IS_5755_PLUS(sc)) 6415 printf(" - 5755 Plus\n"); 6416 if (BGE_IS_575X_PLUS(sc)) 6417 printf(" - 575X Plus\n"); 6418 if (BGE_IS_5705_PLUS(sc)) 6419 printf(" - 5705 Plus\n"); 6420 if (BGE_IS_5714_FAMILY(sc)) 6421 printf(" - 5714 Family\n"); 6422 if (BGE_IS_5700_FAMILY(sc)) 6423 printf(" - 5700 Family\n"); 6424 if (sc->bge_flags & BGEF_IS_5788) 6425 printf(" - 5788\n"); 6426 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6427 printf(" - Supports Jumbo Frames\n"); 6428 if (sc->bge_flags & BGEF_NO_EEPROM) 6429 printf(" - No EEPROM\n"); 6430 if (sc->bge_flags & BGEF_PCIX) 6431 printf(" - PCI-X Bus\n"); 6432 if (sc->bge_flags & BGEF_PCIE) 6433 printf(" - PCI Express Bus\n"); 6434 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6435 printf(" - RX Alignment Bug\n"); 6436 if (sc->bge_flags & BGEF_APE) 6437 printf(" - APE\n"); 6438 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6439 printf(" - CPMU\n"); 6440 if (sc->bge_flags & BGEF_TSO) 6441 printf(" - TSO\n"); 6442 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6443 printf(" - TAGGED_STATUS\n"); 6444 6445 /* PHY related */ 6446 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6447 printf(" - No 3 LEDs\n"); 6448 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6449 printf(" - CRC bug\n"); 6450 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6451 printf(" - ADC bug\n"); 6452 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6453 printf(" - 5704 A0 bug\n"); 6454 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6455 printf(" - jitter bug\n"); 6456 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6457 printf(" - BER bug\n"); 6458 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6459 printf(" - adjust trim\n"); 6460 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6461 printf(" - no wirespeed\n"); 6462 6463 /* ASF related */ 6464 if (sc->bge_asf_mode & ASF_ENABLE) 6465 printf(" - ASF enable\n"); 6466 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6467 printf(" - ASF new handshake\n"); 6468 if (sc->bge_asf_mode & ASF_STACKUP) 6469 printf(" - ASF stackup\n"); 6470 } 6471 #endif /* BGE_DEBUG */ 6472 6473 static int 6474 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6475 { 6476 prop_dictionary_t dict; 6477 prop_data_t ea; 6478 6479 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6480 return 1; 6481 6482 dict = device_properties(sc->bge_dev); 6483 ea = prop_dictionary_get(dict, "mac-address"); 6484 if (ea != NULL) { 6485 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6486 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6487 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6488 return 0; 6489 } 6490 6491 return 1; 6492 } 6493 6494 static int 6495 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6496 { 6497 uint32_t mac_addr; 6498 6499 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6500 if ((mac_addr >> 16) == 0x484b) { 6501 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6502 ether_addr[1] = (uint8_t)mac_addr; 6503 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6504 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6505 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6506 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6507 ether_addr[5] = (uint8_t)mac_addr; 6508 return 0; 6509 } 6510 return 1; 6511 } 6512 6513 static int 6514 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6515 { 6516 int mac_offset = BGE_EE_MAC_OFFSET; 6517 6518 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6519 mac_offset = BGE_EE_MAC_OFFSET_5906; 6520 6521 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6522 ETHER_ADDR_LEN)); 6523 } 6524 6525 static int 6526 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6527 { 6528 6529 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6530 return 1; 6531 6532 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6533 ETHER_ADDR_LEN)); 6534 } 6535 6536 static int 6537 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6538 { 6539 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6540 /* NOTE: Order is critical */ 6541 bge_get_eaddr_fw, 6542 bge_get_eaddr_mem, 6543 bge_get_eaddr_nvram, 6544 bge_get_eaddr_eeprom, 6545 NULL 6546 }; 6547 const bge_eaddr_fcn_t *func; 6548 6549 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6550 if ((*func)(sc, eaddr) == 0) 6551 break; 6552 } 6553 return (*func == NULL ? ENXIO : 0); 6554 } 6555
Indexes created Tue Sep 23 07:09:52 GMT 2025