if_bge.c revision 1.325
1 /* $NetBSD: if_bge.c,v 1.325 2019/02/20 08:03:58 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.325 2019/02/20 08:03:58 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_can_use_msi(struct bge_softc *); 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static int bge_detach(device_t, int); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *m, bool); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 254 static int bge_miibus_writereg(device_t, int, int, uint16_t); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 301 /* 302 * The BCM5700 documentation seems to indicate that the hardware still has the 303 * Alteon vendor ID burned into it, though it should always be overridden by 304 * the value in the EEPROM. We'll check for it anyway. 305 */ 306 static const struct bge_product { 307 pci_vendor_id_t bp_vendor; 308 pci_product_id_t bp_product; 309 const char *bp_name; 310 } bge_products[] = { 311 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 312 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 313 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 314 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 315 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 316 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 317 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 319 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 320 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 321 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 323 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 324 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 348 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 349 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 353 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 354 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 362 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 363 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 364 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 365 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 367 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 368 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 369 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 370 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 371 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 372 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 373 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 374 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 375 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 376 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 377 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 378 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 379 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 380 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 381 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 382 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 383 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 395 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 396 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 397 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 398 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 399 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 400 { 0, 0, NULL }, 401 }; 402 403 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 404 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 405 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 406 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 407 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 408 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 409 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 410 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 411 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 412 413 static const struct bge_revision { 414 uint32_t br_chipid; 415 const char *br_name; 416 } bge_revisions[] = { 417 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 418 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 419 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 420 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 421 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 422 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 423 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 424 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 425 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 426 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 427 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 428 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 429 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 430 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 431 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 432 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 433 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 434 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 435 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 436 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 437 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 438 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 439 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 440 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 441 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 442 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 443 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 444 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 445 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 446 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 447 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 448 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 449 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 450 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 451 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 452 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 453 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 454 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 455 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 456 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 457 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 458 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 459 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 460 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 461 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 462 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 463 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 464 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 465 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 466 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 467 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 468 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 469 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 470 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 471 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 472 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 473 /* 5754 and 5787 share the same ASIC ID */ 474 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 475 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 476 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 477 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 478 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 479 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 480 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 481 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 482 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 483 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 484 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 485 486 { 0, NULL } 487 }; 488 489 /* 490 * Some defaults for major revisions, so that newer steppings 491 * that we don't know about have a shot at working. 492 */ 493 static const struct bge_revision bge_majorrevs[] = { 494 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 495 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 496 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 497 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 498 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 499 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 500 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 501 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 502 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 503 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 504 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 505 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 506 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 507 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 508 /* 5754 and 5787 share the same ASIC ID */ 509 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 510 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 511 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 512 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 513 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 514 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 515 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 516 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 517 518 { 0, NULL } 519 }; 520 521 static int bge_allow_asf = 1; 522 523 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 524 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 525 526 static uint32_t 527 bge_readmem_ind(struct bge_softc *sc, int off) 528 { 529 pcireg_t val; 530 531 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 532 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 533 return 0; 534 535 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 536 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 537 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 538 return val; 539 } 540 541 static void 542 bge_writemem_ind(struct bge_softc *sc, int off, int val) 543 { 544 545 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 546 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 547 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 548 } 549 550 /* 551 * PCI Express only 552 */ 553 static void 554 bge_set_max_readrq(struct bge_softc *sc) 555 { 556 pcireg_t val; 557 558 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 559 + PCIE_DCSR); 560 val &= ~PCIE_DCSR_MAX_READ_REQ; 561 switch (sc->bge_expmrq) { 562 case 2048: 563 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 564 break; 565 case 4096: 566 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 567 break; 568 default: 569 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 570 break; 571 } 572 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 573 + PCIE_DCSR, val); 574 } 575 576 #ifdef notdef 577 static uint32_t 578 bge_readreg_ind(struct bge_softc *sc, int off) 579 { 580 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 581 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 582 } 583 #endif 584 585 static void 586 bge_writereg_ind(struct bge_softc *sc, int off, int val) 587 { 588 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 589 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 590 } 591 592 static void 593 bge_writemem_direct(struct bge_softc *sc, int off, int val) 594 { 595 CSR_WRITE_4(sc, off, val); 596 } 597 598 static void 599 bge_writembx(struct bge_softc *sc, int off, int val) 600 { 601 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 602 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 603 604 CSR_WRITE_4(sc, off, val); 605 } 606 607 static void 608 bge_writembx_flush(struct bge_softc *sc, int off, int val) 609 { 610 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 611 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 612 613 CSR_WRITE_4_FLUSH(sc, off, val); 614 } 615 616 /* 617 * Clear all stale locks and select the lock for this driver instance. 618 */ 619 void 620 bge_ape_lock_init(struct bge_softc *sc) 621 { 622 struct pci_attach_args *pa = &(sc->bge_pa); 623 uint32_t bit, regbase; 624 int i; 625 626 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 627 regbase = BGE_APE_LOCK_GRANT; 628 else 629 regbase = BGE_APE_PER_LOCK_GRANT; 630 631 /* Clear any stale locks. */ 632 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 633 switch (i) { 634 case BGE_APE_LOCK_PHY0: 635 case BGE_APE_LOCK_PHY1: 636 case BGE_APE_LOCK_PHY2: 637 case BGE_APE_LOCK_PHY3: 638 bit = BGE_APE_LOCK_GRANT_DRIVER0; 639 break; 640 default: 641 if (pa->pa_function == 0) 642 bit = BGE_APE_LOCK_GRANT_DRIVER0; 643 else 644 bit = (1 << pa->pa_function); 645 } 646 APE_WRITE_4(sc, regbase + 4 * i, bit); 647 } 648 649 /* Select the PHY lock based on the device's function number. */ 650 switch (pa->pa_function) { 651 case 0: 652 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 653 break; 654 case 1: 655 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 656 break; 657 case 2: 658 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 659 break; 660 case 3: 661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 662 break; 663 default: 664 printf("%s: PHY lock not supported on function\n", 665 device_xname(sc->bge_dev)); 666 break; 667 } 668 } 669 670 /* 671 * Check for APE firmware, set flags, and print version info. 672 */ 673 void 674 bge_ape_read_fw_ver(struct bge_softc *sc) 675 { 676 const char *fwtype; 677 uint32_t apedata, features; 678 679 /* Check for a valid APE signature in shared memory. */ 680 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 681 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 682 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 683 return; 684 } 685 686 /* Check if APE firmware is running. */ 687 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 688 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 689 printf("%s: APE signature found but FW status not ready! " 690 "0x%08x\n", device_xname(sc->bge_dev), apedata); 691 return; 692 } 693 694 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 695 696 /* Fetch the APE firwmare type and version. */ 697 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 698 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 699 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 700 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 701 fwtype = "NCSI"; 702 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 703 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 704 fwtype = "DASH"; 705 } else 706 fwtype = "UNKN"; 707 708 /* Print the APE firmware version. */ 709 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 710 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 711 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 712 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 713 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 714 } 715 716 int 717 bge_ape_lock(struct bge_softc *sc, int locknum) 718 { 719 struct pci_attach_args *pa = &(sc->bge_pa); 720 uint32_t bit, gnt, req, status; 721 int i, off; 722 723 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 724 return (0); 725 726 /* Lock request/grant registers have different bases. */ 727 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 728 req = BGE_APE_LOCK_REQ; 729 gnt = BGE_APE_LOCK_GRANT; 730 } else { 731 req = BGE_APE_PER_LOCK_REQ; 732 gnt = BGE_APE_PER_LOCK_GRANT; 733 } 734 735 off = 4 * locknum; 736 737 switch (locknum) { 738 case BGE_APE_LOCK_GPIO: 739 /* Lock required when using GPIO. */ 740 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 741 return (0); 742 if (pa->pa_function == 0) 743 bit = BGE_APE_LOCK_REQ_DRIVER0; 744 else 745 bit = (1 << pa->pa_function); 746 break; 747 case BGE_APE_LOCK_GRC: 748 /* Lock required to reset the device. */ 749 if (pa->pa_function == 0) 750 bit = BGE_APE_LOCK_REQ_DRIVER0; 751 else 752 bit = (1 << pa->pa_function); 753 break; 754 case BGE_APE_LOCK_MEM: 755 /* Lock required when accessing certain APE memory. */ 756 if (pa->pa_function == 0) 757 bit = BGE_APE_LOCK_REQ_DRIVER0; 758 else 759 bit = (1 << pa->pa_function); 760 break; 761 case BGE_APE_LOCK_PHY0: 762 case BGE_APE_LOCK_PHY1: 763 case BGE_APE_LOCK_PHY2: 764 case BGE_APE_LOCK_PHY3: 765 /* Lock required when accessing PHYs. */ 766 bit = BGE_APE_LOCK_REQ_DRIVER0; 767 break; 768 default: 769 return (EINVAL); 770 } 771 772 /* Request a lock. */ 773 APE_WRITE_4_FLUSH(sc, req + off, bit); 774 775 /* Wait up to 1 second to acquire lock. */ 776 for (i = 0; i < 20000; i++) { 777 status = APE_READ_4(sc, gnt + off); 778 if (status == bit) 779 break; 780 DELAY(50); 781 } 782 783 /* Handle any errors. */ 784 if (status != bit) { 785 printf("%s: APE lock %d request failed! " 786 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 787 device_xname(sc->bge_dev), 788 locknum, req + off, bit & 0xFFFF, gnt + off, 789 status & 0xFFFF); 790 /* Revoke the lock request. */ 791 APE_WRITE_4(sc, gnt + off, bit); 792 return (EBUSY); 793 } 794 795 return (0); 796 } 797 798 void 799 bge_ape_unlock(struct bge_softc *sc, int locknum) 800 { 801 struct pci_attach_args *pa = &(sc->bge_pa); 802 uint32_t bit, gnt; 803 int off; 804 805 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 806 return; 807 808 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 809 gnt = BGE_APE_LOCK_GRANT; 810 else 811 gnt = BGE_APE_PER_LOCK_GRANT; 812 813 off = 4 * locknum; 814 815 switch (locknum) { 816 case BGE_APE_LOCK_GPIO: 817 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 818 return; 819 if (pa->pa_function == 0) 820 bit = BGE_APE_LOCK_GRANT_DRIVER0; 821 else 822 bit = (1 << pa->pa_function); 823 break; 824 case BGE_APE_LOCK_GRC: 825 if (pa->pa_function == 0) 826 bit = BGE_APE_LOCK_GRANT_DRIVER0; 827 else 828 bit = (1 << pa->pa_function); 829 break; 830 case BGE_APE_LOCK_MEM: 831 if (pa->pa_function == 0) 832 bit = BGE_APE_LOCK_GRANT_DRIVER0; 833 else 834 bit = (1 << pa->pa_function); 835 break; 836 case BGE_APE_LOCK_PHY0: 837 case BGE_APE_LOCK_PHY1: 838 case BGE_APE_LOCK_PHY2: 839 case BGE_APE_LOCK_PHY3: 840 bit = BGE_APE_LOCK_GRANT_DRIVER0; 841 break; 842 default: 843 return; 844 } 845 846 /* Write and flush for consecutive bge_ape_lock() */ 847 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 848 } 849 850 /* 851 * Send an event to the APE firmware. 852 */ 853 void 854 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 855 { 856 uint32_t apedata; 857 int i; 858 859 /* NCSI does not support APE events. */ 860 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 861 return; 862 863 /* Wait up to 1ms for APE to service previous event. */ 864 for (i = 10; i > 0; i--) { 865 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 866 break; 867 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 868 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 869 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 870 BGE_APE_EVENT_STATUS_EVENT_PENDING); 871 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 872 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 873 break; 874 } 875 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 876 DELAY(100); 877 } 878 if (i == 0) { 879 printf("%s: APE event 0x%08x send timed out\n", 880 device_xname(sc->bge_dev), event); 881 } 882 } 883 884 void 885 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 886 { 887 uint32_t apedata, event; 888 889 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 890 return; 891 892 switch (kind) { 893 case BGE_RESET_START: 894 /* If this is the first load, clear the load counter. */ 895 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 896 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 897 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 898 else { 899 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 900 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 901 } 902 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 903 BGE_APE_HOST_SEG_SIG_MAGIC); 904 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 905 BGE_APE_HOST_SEG_LEN_MAGIC); 906 907 /* Add some version info if bge(4) supports it. */ 908 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 909 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 910 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 911 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 912 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 913 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 914 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 915 BGE_APE_HOST_DRVR_STATE_START); 916 event = BGE_APE_EVENT_STATUS_STATE_START; 917 break; 918 case BGE_RESET_SHUTDOWN: 919 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 920 BGE_APE_HOST_DRVR_STATE_UNLOAD); 921 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 922 break; 923 case BGE_RESET_SUSPEND: 924 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 925 break; 926 default: 927 return; 928 } 929 930 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 931 BGE_APE_EVENT_STATUS_STATE_CHNGE); 932 } 933 934 static uint8_t 935 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 936 { 937 uint32_t access, byte = 0; 938 int i; 939 940 /* Lock. */ 941 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 942 for (i = 0; i < 8000; i++) { 943 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 944 break; 945 DELAY(20); 946 } 947 if (i == 8000) 948 return 1; 949 950 /* Enable access. */ 951 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 952 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 953 954 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 955 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 956 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 957 DELAY(10); 958 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 959 DELAY(10); 960 break; 961 } 962 } 963 964 if (i == BGE_TIMEOUT * 10) { 965 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 966 return 1; 967 } 968 969 /* Get result. */ 970 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 971 972 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 973 974 /* Disable access. */ 975 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 976 977 /* Unlock. */ 978 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 979 980 return 0; 981 } 982 983 /* 984 * Read a sequence of bytes from NVRAM. 985 */ 986 static int 987 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 988 { 989 int error = 0, i; 990 uint8_t byte = 0; 991 992 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 993 return 1; 994 995 for (i = 0; i < cnt; i++) { 996 error = bge_nvram_getbyte(sc, off + i, &byte); 997 if (error) 998 break; 999 *(dest + i) = byte; 1000 } 1001 1002 return (error ? 1 : 0); 1003 } 1004 1005 /* 1006 * Read a byte of data stored in the EEPROM at address 'addr.' The 1007 * BCM570x supports both the traditional bitbang interface and an 1008 * auto access interface for reading the EEPROM. We use the auto 1009 * access method. 1010 */ 1011 static uint8_t 1012 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1013 { 1014 int i; 1015 uint32_t byte = 0; 1016 1017 /* 1018 * Enable use of auto EEPROM access so we can avoid 1019 * having to use the bitbang method. 1020 */ 1021 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1022 1023 /* Reset the EEPROM, load the clock period. */ 1024 CSR_WRITE_4(sc, BGE_EE_ADDR, 1025 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1026 DELAY(20); 1027 1028 /* Issue the read EEPROM command. */ 1029 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1030 1031 /* Wait for completion */ 1032 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1033 DELAY(10); 1034 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1035 break; 1036 } 1037 1038 if (i == BGE_TIMEOUT * 10) { 1039 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1040 return 1; 1041 } 1042 1043 /* Get result. */ 1044 byte = CSR_READ_4(sc, BGE_EE_DATA); 1045 1046 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1047 1048 return 0; 1049 } 1050 1051 /* 1052 * Read a sequence of bytes from the EEPROM. 1053 */ 1054 static int 1055 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1056 { 1057 int error = 0, i; 1058 uint8_t byte = 0; 1059 char *dest = destv; 1060 1061 for (i = 0; i < cnt; i++) { 1062 error = bge_eeprom_getbyte(sc, off + i, &byte); 1063 if (error) 1064 break; 1065 *(dest + i) = byte; 1066 } 1067 1068 return (error ? 1 : 0); 1069 } 1070 1071 static int 1072 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1073 { 1074 struct bge_softc *sc = device_private(dev); 1075 uint32_t data; 1076 uint32_t autopoll; 1077 int rv = 0; 1078 int i; 1079 1080 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1081 return -1; 1082 1083 /* Reading with autopolling on may trigger PCI errors */ 1084 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1085 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1086 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1087 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1088 DELAY(80); 1089 } 1090 1091 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1092 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1093 1094 for (i = 0; i < BGE_TIMEOUT; i++) { 1095 delay(10); 1096 data = CSR_READ_4(sc, BGE_MI_COMM); 1097 if (!(data & BGE_MICOMM_BUSY)) { 1098 DELAY(5); 1099 data = CSR_READ_4(sc, BGE_MI_COMM); 1100 break; 1101 } 1102 } 1103 1104 if (i == BGE_TIMEOUT) { 1105 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1106 rv = ETIMEDOUT; 1107 } else if ((data & BGE_MICOMM_READFAIL) != 0) 1108 rv = -1; 1109 else 1110 *val = data & BGE_MICOMM_DATA; 1111 1112 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1113 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1114 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1115 DELAY(80); 1116 } 1117 1118 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1119 1120 return rv; 1121 } 1122 1123 static int 1124 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1125 { 1126 struct bge_softc *sc = device_private(dev); 1127 uint32_t autopoll; 1128 int i; 1129 1130 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1131 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1132 return 0; 1133 1134 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1135 return -1; 1136 1137 /* Reading with autopolling on may trigger PCI errors */ 1138 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1139 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1140 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1141 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1142 DELAY(80); 1143 } 1144 1145 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1146 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1147 1148 for (i = 0; i < BGE_TIMEOUT; i++) { 1149 delay(10); 1150 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1151 delay(5); 1152 CSR_READ_4(sc, BGE_MI_COMM); 1153 break; 1154 } 1155 } 1156 1157 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1158 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1159 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1160 delay(80); 1161 } 1162 1163 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1164 1165 if (i == BGE_TIMEOUT) { 1166 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1167 return ETIMEDOUT; 1168 } 1169 1170 return 0; 1171 } 1172 1173 static void 1174 bge_miibus_statchg(struct ifnet *ifp) 1175 { 1176 struct bge_softc *sc = ifp->if_softc; 1177 struct mii_data *mii = &sc->bge_mii; 1178 uint32_t mac_mode, rx_mode, tx_mode; 1179 1180 /* 1181 * Get flow control negotiation result. 1182 */ 1183 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1184 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1185 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1186 1187 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1188 mii->mii_media_status & IFM_ACTIVE && 1189 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1190 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1191 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1192 (!(mii->mii_media_status & IFM_ACTIVE) || 1193 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1194 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1195 1196 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1197 return; 1198 1199 /* Set the port mode (MII/GMII) to match the link speed. */ 1200 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1201 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1202 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1203 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1204 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1205 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1206 mac_mode |= BGE_PORTMODE_GMII; 1207 else 1208 mac_mode |= BGE_PORTMODE_MII; 1209 1210 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1211 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1212 if ((mii->mii_media_active & IFM_FDX) != 0) { 1213 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1214 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1215 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1216 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1217 } else 1218 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1219 1220 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1221 DELAY(40); 1222 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1223 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1224 } 1225 1226 /* 1227 * Update rx threshold levels to values in a particular slot 1228 * of the interrupt-mitigation table bge_rx_threshes. 1229 */ 1230 static void 1231 bge_set_thresh(struct ifnet *ifp, int lvl) 1232 { 1233 struct bge_softc *sc = ifp->if_softc; 1234 int s; 1235 1236 /* For now, just save the new Rx-intr thresholds and record 1237 * that a threshold update is pending. Updating the hardware 1238 * registers here (even at splhigh()) is observed to 1239 * occasionaly cause glitches where Rx-interrupts are not 1240 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1241 */ 1242 s = splnet(); 1243 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1244 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1245 sc->bge_pending_rxintr_change = 1; 1246 splx(s); 1247 } 1248 1249 1250 /* 1251 * Update Rx thresholds of all bge devices 1252 */ 1253 static void 1254 bge_update_all_threshes(int lvl) 1255 { 1256 struct ifnet *ifp; 1257 const char * const namebuf = "bge"; 1258 int namelen; 1259 int s; 1260 1261 if (lvl < 0) 1262 lvl = 0; 1263 else if (lvl >= NBGE_RX_THRESH) 1264 lvl = NBGE_RX_THRESH - 1; 1265 1266 namelen = strlen(namebuf); 1267 /* 1268 * Now search all the interfaces for this name/number 1269 */ 1270 s = pserialize_read_enter(); 1271 IFNET_READER_FOREACH(ifp) { 1272 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1273 continue; 1274 /* We got a match: update if doing auto-threshold-tuning */ 1275 if (bge_auto_thresh) 1276 bge_set_thresh(ifp, lvl); 1277 } 1278 pserialize_read_exit(s); 1279 } 1280 1281 /* 1282 * Handle events that have triggered interrupts. 1283 */ 1284 static void 1285 bge_handle_events(struct bge_softc *sc) 1286 { 1287 1288 return; 1289 } 1290 1291 /* 1292 * Memory management for jumbo frames. 1293 */ 1294 1295 static int 1296 bge_alloc_jumbo_mem(struct bge_softc *sc) 1297 { 1298 char *ptr, *kva; 1299 bus_dma_segment_t seg; 1300 int i, rseg, state, error; 1301 struct bge_jpool_entry *entry; 1302 1303 state = error = 0; 1304 1305 /* Grab a big chunk o' storage. */ 1306 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1307 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1308 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1309 return ENOBUFS; 1310 } 1311 1312 state = 1; 1313 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1314 BUS_DMA_NOWAIT)) { 1315 aprint_error_dev(sc->bge_dev, 1316 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1317 error = ENOBUFS; 1318 goto out; 1319 } 1320 1321 state = 2; 1322 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1323 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1324 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1325 error = ENOBUFS; 1326 goto out; 1327 } 1328 1329 state = 3; 1330 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1331 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1332 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1333 error = ENOBUFS; 1334 goto out; 1335 } 1336 1337 state = 4; 1338 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1339 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1340 1341 SLIST_INIT(&sc->bge_jfree_listhead); 1342 SLIST_INIT(&sc->bge_jinuse_listhead); 1343 1344 /* 1345 * Now divide it up into 9K pieces and save the addresses 1346 * in an array. 1347 */ 1348 ptr = sc->bge_cdata.bge_jumbo_buf; 1349 for (i = 0; i < BGE_JSLOTS; i++) { 1350 sc->bge_cdata.bge_jslots[i] = ptr; 1351 ptr += BGE_JLEN; 1352 entry = malloc(sizeof(struct bge_jpool_entry), 1353 M_DEVBUF, M_NOWAIT); 1354 if (entry == NULL) { 1355 aprint_error_dev(sc->bge_dev, 1356 "no memory for jumbo buffer queue!\n"); 1357 error = ENOBUFS; 1358 goto out; 1359 } 1360 entry->slot = i; 1361 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1362 entry, jpool_entries); 1363 } 1364 out: 1365 if (error != 0) { 1366 switch (state) { 1367 case 4: 1368 bus_dmamap_unload(sc->bge_dmatag, 1369 sc->bge_cdata.bge_rx_jumbo_map); 1370 /* FALLTHROUGH */ 1371 case 3: 1372 bus_dmamap_destroy(sc->bge_dmatag, 1373 sc->bge_cdata.bge_rx_jumbo_map); 1374 /* FALLTHROUGH */ 1375 case 2: 1376 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1377 /* FALLTHROUGH */ 1378 case 1: 1379 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1380 break; 1381 default: 1382 break; 1383 } 1384 } 1385 1386 return error; 1387 } 1388 1389 /* 1390 * Allocate a jumbo buffer. 1391 */ 1392 static void * 1393 bge_jalloc(struct bge_softc *sc) 1394 { 1395 struct bge_jpool_entry *entry; 1396 1397 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1398 1399 if (entry == NULL) { 1400 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1401 return NULL; 1402 } 1403 1404 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1405 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1406 return (sc->bge_cdata.bge_jslots[entry->slot]); 1407 } 1408 1409 /* 1410 * Release a jumbo buffer. 1411 */ 1412 static void 1413 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1414 { 1415 struct bge_jpool_entry *entry; 1416 struct bge_softc *sc; 1417 int i, s; 1418 1419 /* Extract the softc struct pointer. */ 1420 sc = (struct bge_softc *)arg; 1421 1422 if (sc == NULL) 1423 panic("bge_jfree: can't find softc pointer!"); 1424 1425 /* calculate the slot this buffer belongs to */ 1426 1427 i = ((char *)buf 1428 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1429 1430 if ((i < 0) || (i >= BGE_JSLOTS)) 1431 panic("bge_jfree: asked to free buffer that we don't manage!"); 1432 1433 s = splvm(); 1434 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1435 if (entry == NULL) 1436 panic("bge_jfree: buffer not in use!"); 1437 entry->slot = i; 1438 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1439 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1440 1441 if (__predict_true(m != NULL)) 1442 pool_cache_put(mb_cache, m); 1443 splx(s); 1444 } 1445 1446 1447 /* 1448 * Initialize a standard receive ring descriptor. 1449 */ 1450 static int 1451 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1452 bus_dmamap_t dmamap) 1453 { 1454 struct mbuf *m_new = NULL; 1455 struct bge_rx_bd *r; 1456 int error; 1457 1458 if (dmamap == NULL) 1459 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1460 1461 if (dmamap == NULL) { 1462 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1463 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1464 if (error != 0) 1465 return error; 1466 } 1467 1468 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1469 1470 if (m == NULL) { 1471 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1472 if (m_new == NULL) 1473 return ENOBUFS; 1474 1475 MCLGET(m_new, M_DONTWAIT); 1476 if (!(m_new->m_flags & M_EXT)) { 1477 m_freem(m_new); 1478 return ENOBUFS; 1479 } 1480 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1481 1482 } else { 1483 m_new = m; 1484 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1485 m_new->m_data = m_new->m_ext.ext_buf; 1486 } 1487 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1488 m_adj(m_new, ETHER_ALIGN); 1489 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1490 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1491 m_freem(m_new); 1492 return ENOBUFS; 1493 } 1494 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1495 BUS_DMASYNC_PREREAD); 1496 1497 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1498 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1499 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1500 r->bge_flags = BGE_RXBDFLAG_END; 1501 r->bge_len = m_new->m_len; 1502 r->bge_idx = i; 1503 1504 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1505 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1506 i * sizeof (struct bge_rx_bd), 1507 sizeof (struct bge_rx_bd), 1508 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1509 1510 return 0; 1511 } 1512 1513 /* 1514 * Initialize a jumbo receive ring descriptor. This allocates 1515 * a jumbo buffer from the pool managed internally by the driver. 1516 */ 1517 static int 1518 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1519 { 1520 struct mbuf *m_new = NULL; 1521 struct bge_rx_bd *r; 1522 void *buf = NULL; 1523 1524 if (m == NULL) { 1525 1526 /* Allocate the mbuf. */ 1527 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1528 if (m_new == NULL) 1529 return ENOBUFS; 1530 1531 /* Allocate the jumbo buffer */ 1532 buf = bge_jalloc(sc); 1533 if (buf == NULL) { 1534 m_freem(m_new); 1535 aprint_error_dev(sc->bge_dev, 1536 "jumbo allocation failed -- packet dropped!\n"); 1537 return ENOBUFS; 1538 } 1539 1540 /* Attach the buffer to the mbuf. */ 1541 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1542 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1543 bge_jfree, sc); 1544 m_new->m_flags |= M_EXT_RW; 1545 } else { 1546 m_new = m; 1547 buf = m_new->m_data = m_new->m_ext.ext_buf; 1548 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1549 } 1550 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1551 m_adj(m_new, ETHER_ALIGN); 1552 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1553 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1554 BUS_DMASYNC_PREREAD); 1555 /* Set up the descriptor. */ 1556 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1557 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1558 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1559 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1560 r->bge_len = m_new->m_len; 1561 r->bge_idx = i; 1562 1563 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1564 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1565 i * sizeof (struct bge_rx_bd), 1566 sizeof (struct bge_rx_bd), 1567 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1568 1569 return 0; 1570 } 1571 1572 /* 1573 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1574 * that's 1MB or memory, which is a lot. For now, we fill only the first 1575 * 256 ring entries and hope that our CPU is fast enough to keep up with 1576 * the NIC. 1577 */ 1578 static int 1579 bge_init_rx_ring_std(struct bge_softc *sc) 1580 { 1581 int i; 1582 1583 if (sc->bge_flags & BGEF_RXRING_VALID) 1584 return 0; 1585 1586 for (i = 0; i < BGE_SSLOTS; i++) { 1587 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1588 return ENOBUFS; 1589 } 1590 1591 sc->bge_std = i - 1; 1592 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1593 1594 sc->bge_flags |= BGEF_RXRING_VALID; 1595 1596 return 0; 1597 } 1598 1599 static void 1600 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1601 { 1602 int i; 1603 1604 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1605 return; 1606 1607 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1608 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1609 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1610 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1611 if (disable) { 1612 bus_dmamap_destroy(sc->bge_dmatag, 1613 sc->bge_cdata.bge_rx_std_map[i]); 1614 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1615 } 1616 } 1617 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1618 sizeof(struct bge_rx_bd)); 1619 } 1620 1621 sc->bge_flags &= ~BGEF_RXRING_VALID; 1622 } 1623 1624 static int 1625 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1626 { 1627 int i; 1628 volatile struct bge_rcb *rcb; 1629 1630 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1631 return 0; 1632 1633 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1634 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1635 return ENOBUFS; 1636 } 1637 1638 sc->bge_jumbo = i - 1; 1639 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1640 1641 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1642 rcb->bge_maxlen_flags = 0; 1643 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1644 1645 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1646 1647 return 0; 1648 } 1649 1650 static void 1651 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1652 { 1653 int i; 1654 1655 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1656 return; 1657 1658 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1659 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1660 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1661 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1662 } 1663 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1664 sizeof(struct bge_rx_bd)); 1665 } 1666 1667 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1668 } 1669 1670 static void 1671 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1672 { 1673 int i; 1674 struct txdmamap_pool_entry *dma; 1675 1676 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1677 return; 1678 1679 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1680 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1681 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1682 sc->bge_cdata.bge_tx_chain[i] = NULL; 1683 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1684 link); 1685 sc->txdma[i] = 0; 1686 } 1687 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1688 sizeof(struct bge_tx_bd)); 1689 } 1690 1691 if (disable) { 1692 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1693 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1694 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1695 if (sc->bge_dma64) { 1696 bus_dmamap_destroy(sc->bge_dmatag32, 1697 dma->dmamap32); 1698 } 1699 free(dma, M_DEVBUF); 1700 } 1701 SLIST_INIT(&sc->txdma_list); 1702 } 1703 1704 sc->bge_flags &= ~BGEF_TXRING_VALID; 1705 } 1706 1707 static int 1708 bge_init_tx_ring(struct bge_softc *sc) 1709 { 1710 struct ifnet *ifp = &sc->ethercom.ec_if; 1711 int i; 1712 bus_dmamap_t dmamap, dmamap32; 1713 bus_size_t maxsegsz; 1714 struct txdmamap_pool_entry *dma; 1715 1716 if (sc->bge_flags & BGEF_TXRING_VALID) 1717 return 0; 1718 1719 sc->bge_txcnt = 0; 1720 sc->bge_tx_saved_considx = 0; 1721 1722 /* Initialize transmit producer index for host-memory send ring. */ 1723 sc->bge_tx_prodidx = 0; 1724 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1725 /* 5700 b2 errata */ 1726 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1727 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1728 1729 /* NIC-memory send ring not used; initialize to zero. */ 1730 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1731 /* 5700 b2 errata */ 1732 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1733 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1734 1735 /* Limit DMA segment size for some chips */ 1736 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1737 (ifp->if_mtu <= ETHERMTU)) 1738 maxsegsz = 2048; 1739 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1740 maxsegsz = 4096; 1741 else 1742 maxsegsz = ETHER_MAX_LEN_JUMBO; 1743 1744 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1745 goto alloc_done; 1746 1747 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1748 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1749 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1750 &dmamap)) 1751 return ENOBUFS; 1752 if (dmamap == NULL) 1753 panic("dmamap NULL in bge_init_tx_ring"); 1754 if (sc->bge_dma64) { 1755 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1756 BGE_NTXSEG, maxsegsz, 0, 1757 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1758 &dmamap32)) { 1759 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1760 return ENOBUFS; 1761 } 1762 if (dmamap32 == NULL) 1763 panic("dmamap32 NULL in bge_init_tx_ring"); 1764 } else 1765 dmamap32 = dmamap; 1766 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1767 if (dma == NULL) { 1768 aprint_error_dev(sc->bge_dev, 1769 "can't alloc txdmamap_pool_entry\n"); 1770 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1771 if (sc->bge_dma64) 1772 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1773 return ENOMEM; 1774 } 1775 dma->dmamap = dmamap; 1776 dma->dmamap32 = dmamap32; 1777 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1778 } 1779 alloc_done: 1780 sc->bge_flags |= BGEF_TXRING_VALID; 1781 1782 return 0; 1783 } 1784 1785 static void 1786 bge_setmulti(struct bge_softc *sc) 1787 { 1788 struct ethercom *ac = &sc->ethercom; 1789 struct ifnet *ifp = &ac->ec_if; 1790 struct ether_multi *enm; 1791 struct ether_multistep step; 1792 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1793 uint32_t h; 1794 int i; 1795 1796 if (ifp->if_flags & IFF_PROMISC) 1797 goto allmulti; 1798 1799 /* Now program new ones. */ 1800 ETHER_FIRST_MULTI(step, ac, enm); 1801 while (enm != NULL) { 1802 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1803 /* 1804 * We must listen to a range of multicast addresses. 1805 * For now, just accept all multicasts, rather than 1806 * trying to set only those filter bits needed to match 1807 * the range. (At this time, the only use of address 1808 * ranges is for IP multicast routing, for which the 1809 * range is big enough to require all bits set.) 1810 */ 1811 goto allmulti; 1812 } 1813 1814 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1815 1816 /* Just want the 7 least-significant bits. */ 1817 h &= 0x7f; 1818 1819 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1820 ETHER_NEXT_MULTI(step, enm); 1821 } 1822 1823 ifp->if_flags &= ~IFF_ALLMULTI; 1824 goto setit; 1825 1826 allmulti: 1827 ifp->if_flags |= IFF_ALLMULTI; 1828 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1829 1830 setit: 1831 for (i = 0; i < 4; i++) 1832 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1833 } 1834 1835 static void 1836 bge_sig_pre_reset(struct bge_softc *sc, int type) 1837 { 1838 1839 /* 1840 * Some chips don't like this so only do this if ASF is enabled 1841 */ 1842 if (sc->bge_asf_mode) 1843 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1844 1845 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1846 switch (type) { 1847 case BGE_RESET_START: 1848 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1849 BGE_FW_DRV_STATE_START); 1850 break; 1851 case BGE_RESET_SHUTDOWN: 1852 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1853 BGE_FW_DRV_STATE_UNLOAD); 1854 break; 1855 case BGE_RESET_SUSPEND: 1856 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1857 BGE_FW_DRV_STATE_SUSPEND); 1858 break; 1859 } 1860 } 1861 1862 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1863 bge_ape_driver_state_change(sc, type); 1864 } 1865 1866 static void 1867 bge_sig_post_reset(struct bge_softc *sc, int type) 1868 { 1869 1870 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1871 switch (type) { 1872 case BGE_RESET_START: 1873 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1874 BGE_FW_DRV_STATE_START_DONE); 1875 /* START DONE */ 1876 break; 1877 case BGE_RESET_SHUTDOWN: 1878 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1879 BGE_FW_DRV_STATE_UNLOAD_DONE); 1880 break; 1881 } 1882 } 1883 1884 if (type == BGE_RESET_SHUTDOWN) 1885 bge_ape_driver_state_change(sc, type); 1886 } 1887 1888 static void 1889 bge_sig_legacy(struct bge_softc *sc, int type) 1890 { 1891 1892 if (sc->bge_asf_mode) { 1893 switch (type) { 1894 case BGE_RESET_START: 1895 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1896 BGE_FW_DRV_STATE_START); 1897 break; 1898 case BGE_RESET_SHUTDOWN: 1899 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1900 BGE_FW_DRV_STATE_UNLOAD); 1901 break; 1902 } 1903 } 1904 } 1905 1906 static void 1907 bge_wait_for_event_ack(struct bge_softc *sc) 1908 { 1909 int i; 1910 1911 /* wait up to 2500usec */ 1912 for (i = 0; i < 250; i++) { 1913 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1914 BGE_RX_CPU_DRV_EVENT)) 1915 break; 1916 DELAY(10); 1917 } 1918 } 1919 1920 static void 1921 bge_stop_fw(struct bge_softc *sc) 1922 { 1923 1924 if (sc->bge_asf_mode) { 1925 bge_wait_for_event_ack(sc); 1926 1927 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1928 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1929 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1930 1931 bge_wait_for_event_ack(sc); 1932 } 1933 } 1934 1935 static int 1936 bge_poll_fw(struct bge_softc *sc) 1937 { 1938 uint32_t val; 1939 int i; 1940 1941 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1942 for (i = 0; i < BGE_TIMEOUT; i++) { 1943 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1944 if (val & BGE_VCPU_STATUS_INIT_DONE) 1945 break; 1946 DELAY(100); 1947 } 1948 if (i >= BGE_TIMEOUT) { 1949 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1950 return -1; 1951 } 1952 } else { 1953 /* 1954 * Poll the value location we just wrote until 1955 * we see the 1's complement of the magic number. 1956 * This indicates that the firmware initialization 1957 * is complete. 1958 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1959 */ 1960 for (i = 0; i < BGE_TIMEOUT; i++) { 1961 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1962 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1963 break; 1964 DELAY(10); 1965 } 1966 1967 if ((i >= BGE_TIMEOUT) 1968 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1969 aprint_error_dev(sc->bge_dev, 1970 "firmware handshake timed out, val = %x\n", val); 1971 return -1; 1972 } 1973 } 1974 1975 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1976 /* tg3 says we have to wait extra time */ 1977 delay(10 * 1000); 1978 } 1979 1980 return 0; 1981 } 1982 1983 int 1984 bge_phy_addr(struct bge_softc *sc) 1985 { 1986 struct pci_attach_args *pa = &(sc->bge_pa); 1987 int phy_addr = 1; 1988 1989 /* 1990 * PHY address mapping for various devices. 1991 * 1992 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 1993 * ---------+-------+-------+-------+-------+ 1994 * BCM57XX | 1 | X | X | X | 1995 * BCM5704 | 1 | X | 1 | X | 1996 * BCM5717 | 1 | 8 | 2 | 9 | 1997 * BCM5719 | 1 | 8 | 2 | 9 | 1998 * BCM5720 | 1 | 8 | 2 | 9 | 1999 * 2000 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2001 * ---------+-------+-------+-------+-------+ 2002 * BCM57XX | X | X | X | X | 2003 * BCM5704 | X | X | X | X | 2004 * BCM5717 | X | X | X | X | 2005 * BCM5719 | 3 | 10 | 4 | 11 | 2006 * BCM5720 | X | X | X | X | 2007 * 2008 * Other addresses may respond but they are not 2009 * IEEE compliant PHYs and should be ignored. 2010 */ 2011 switch (BGE_ASICREV(sc->bge_chipid)) { 2012 case BGE_ASICREV_BCM5717: 2013 case BGE_ASICREV_BCM5719: 2014 case BGE_ASICREV_BCM5720: 2015 phy_addr = pa->pa_function; 2016 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2017 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2018 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2019 } else { 2020 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2021 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2022 } 2023 } 2024 2025 return phy_addr; 2026 } 2027 2028 /* 2029 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2030 * self-test results. 2031 */ 2032 static int 2033 bge_chipinit(struct bge_softc *sc) 2034 { 2035 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2036 int i; 2037 2038 /* Set endianness before we access any non-PCI registers. */ 2039 misc_ctl = BGE_INIT; 2040 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2041 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2042 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2043 misc_ctl); 2044 2045 /* 2046 * Clear the MAC statistics block in the NIC's 2047 * internal memory. 2048 */ 2049 for (i = BGE_STATS_BLOCK; 2050 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2051 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2052 2053 for (i = BGE_STATUS_BLOCK; 2054 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2055 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2056 2057 /* 5717 workaround from tg3 */ 2058 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2059 /* Save */ 2060 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2061 2062 /* Temporary modify MODE_CTL to control TLP */ 2063 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2064 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2065 2066 /* Control TLP */ 2067 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2068 BGE_TLP_PHYCTL1); 2069 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2070 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2071 2072 /* Restore */ 2073 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2074 } 2075 2076 if (BGE_IS_57765_FAMILY(sc)) { 2077 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2078 /* Save */ 2079 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2080 2081 /* Temporary modify MODE_CTL to control TLP */ 2082 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2083 CSR_WRITE_4(sc, BGE_MODE_CTL, 2084 reg | BGE_MODECTL_PCIE_TLPADDR1); 2085 2086 /* Control TLP */ 2087 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2088 BGE_TLP_PHYCTL5); 2089 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2090 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2091 2092 /* Restore */ 2093 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2094 } 2095 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2096 /* 2097 * For the 57766 and non Ax versions of 57765, bootcode 2098 * needs to setup the PCIE Fast Training Sequence (FTS) 2099 * value to prevent transmit hangs. 2100 */ 2101 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2102 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2103 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2104 2105 /* Save */ 2106 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2107 2108 /* Temporary modify MODE_CTL to control TLP */ 2109 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2110 CSR_WRITE_4(sc, BGE_MODE_CTL, 2111 reg | BGE_MODECTL_PCIE_TLPADDR0); 2112 2113 /* Control TLP */ 2114 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2115 BGE_TLP_FTSMAX); 2116 reg &= ~BGE_TLP_FTSMAX_MSK; 2117 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2118 reg | BGE_TLP_FTSMAX_VAL); 2119 2120 /* Restore */ 2121 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2122 } 2123 2124 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2125 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2126 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2127 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2128 } 2129 2130 /* Set up the PCI DMA control register. */ 2131 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2132 if (sc->bge_flags & BGEF_PCIE) { 2133 /* Read watermark not used, 128 bytes for write. */ 2134 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2135 device_xname(sc->bge_dev))); 2136 if (sc->bge_mps >= 256) 2137 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2138 else 2139 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2140 } else if (sc->bge_flags & BGEF_PCIX) { 2141 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2142 device_xname(sc->bge_dev))); 2143 /* PCI-X bus */ 2144 if (BGE_IS_5714_FAMILY(sc)) { 2145 /* 256 bytes for read and write. */ 2146 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2147 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2148 2149 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2150 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2151 else 2152 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2153 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2154 /* 2155 * In the BCM5703, the DMA read watermark should 2156 * be set to less than or equal to the maximum 2157 * memory read byte count of the PCI-X command 2158 * register. 2159 */ 2160 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2161 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2162 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2163 /* 1536 bytes for read, 384 bytes for write. */ 2164 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2165 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2166 } else { 2167 /* 384 bytes for read and write. */ 2168 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2169 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2170 (0x0F); 2171 } 2172 2173 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2174 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2175 uint32_t tmp; 2176 2177 /* Set ONEDMA_ATONCE for hardware workaround. */ 2178 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2179 if (tmp == 6 || tmp == 7) 2180 dma_rw_ctl |= 2181 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2182 2183 /* Set PCI-X DMA write workaround. */ 2184 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2185 } 2186 } else { 2187 /* Conventional PCI bus: 256 bytes for read and write. */ 2188 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2189 device_xname(sc->bge_dev))); 2190 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2191 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2192 2193 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2194 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2195 dma_rw_ctl |= 0x0F; 2196 } 2197 2198 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2199 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2200 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2201 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2202 2203 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2204 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2205 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2206 2207 if (BGE_IS_57765_PLUS(sc)) { 2208 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2209 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2210 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2211 2212 /* 2213 * Enable HW workaround for controllers that misinterpret 2214 * a status tag update and leave interrupts permanently 2215 * disabled. 2216 */ 2217 if (!BGE_IS_57765_FAMILY(sc) && 2218 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2219 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2220 } 2221 2222 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2223 dma_rw_ctl); 2224 2225 /* 2226 * Set up general mode register. 2227 */ 2228 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2229 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2230 /* Retain Host-2-BMC settings written by APE firmware. */ 2231 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2232 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2233 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2234 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2235 } 2236 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2237 BGE_MODECTL_TX_NO_PHDR_CSUM; 2238 2239 /* 2240 * BCM5701 B5 have a bug causing data corruption when using 2241 * 64-bit DMA reads, which can be terminated early and then 2242 * completed later as 32-bit accesses, in combination with 2243 * certain bridges. 2244 */ 2245 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2246 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2247 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2248 2249 /* 2250 * Tell the firmware the driver is running 2251 */ 2252 if (sc->bge_asf_mode & ASF_STACKUP) 2253 mode_ctl |= BGE_MODECTL_STACKUP; 2254 2255 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2256 2257 /* 2258 * Disable memory write invalidate. Apparently it is not supported 2259 * properly by these devices. 2260 */ 2261 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2262 PCI_COMMAND_INVALIDATE_ENABLE); 2263 2264 #ifdef __brokenalpha__ 2265 /* 2266 * Must insure that we do not cross an 8K (bytes) boundary 2267 * for DMA reads. Our highest limit is 1K bytes. This is a 2268 * restriction on some ALPHA platforms with early revision 2269 * 21174 PCI chipsets, such as the AlphaPC 164lx 2270 */ 2271 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2272 #endif 2273 2274 /* Set the timer prescaler (always 66MHz) */ 2275 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2276 2277 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2278 DELAY(40); /* XXX */ 2279 2280 /* Put PHY into ready state */ 2281 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2282 DELAY(40); 2283 } 2284 2285 return 0; 2286 } 2287 2288 static int 2289 bge_blockinit(struct bge_softc *sc) 2290 { 2291 volatile struct bge_rcb *rcb; 2292 bus_size_t rcb_addr; 2293 struct ifnet *ifp = &sc->ethercom.ec_if; 2294 bge_hostaddr taddr; 2295 uint32_t dmactl, mimode, val; 2296 int i, limit; 2297 2298 /* 2299 * Initialize the memory window pointer register so that 2300 * we can access the first 32K of internal NIC RAM. This will 2301 * allow us to set up the TX send ring RCBs and the RX return 2302 * ring RCBs, plus other things which live in NIC memory. 2303 */ 2304 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2305 2306 if (!BGE_IS_5705_PLUS(sc)) { 2307 /* 57XX step 33 */ 2308 /* Configure mbuf memory pool */ 2309 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2310 BGE_BUFFPOOL_1); 2311 2312 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2313 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2314 else 2315 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2316 2317 /* 57XX step 34 */ 2318 /* Configure DMA resource pool */ 2319 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2320 BGE_DMA_DESCRIPTORS); 2321 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2322 } 2323 2324 /* 5718 step 11, 57XX step 35 */ 2325 /* 2326 * Configure mbuf pool watermarks. New broadcom docs strongly 2327 * recommend these. 2328 */ 2329 if (BGE_IS_5717_PLUS(sc)) { 2330 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2331 if (ifp->if_mtu > ETHERMTU) { 2332 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2333 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2334 } else { 2335 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2336 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2337 } 2338 } else if (BGE_IS_5705_PLUS(sc)) { 2339 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2340 2341 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2342 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2344 } else { 2345 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2346 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2347 } 2348 } else { 2349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2351 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2352 } 2353 2354 /* 57XX step 36 */ 2355 /* Configure DMA resource watermarks */ 2356 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2357 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2358 2359 /* 5718 step 13, 57XX step 38 */ 2360 /* Enable buffer manager */ 2361 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2362 /* 2363 * Change the arbitration algorithm of TXMBUF read request to 2364 * round-robin instead of priority based for BCM5719. When 2365 * TXFIFO is almost empty, RDMA will hold its request until 2366 * TXFIFO is not almost empty. 2367 */ 2368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2369 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2370 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2371 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2372 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2373 val |= BGE_BMANMODE_LOMBUF_ATTN; 2374 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2375 2376 /* 57XX step 39 */ 2377 /* Poll for buffer manager start indication */ 2378 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2379 DELAY(10); 2380 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2381 break; 2382 } 2383 2384 if (i == BGE_TIMEOUT * 2) { 2385 aprint_error_dev(sc->bge_dev, 2386 "buffer manager failed to start\n"); 2387 return ENXIO; 2388 } 2389 2390 /* 57XX step 40 */ 2391 /* Enable flow-through queues */ 2392 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2393 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2394 2395 /* Wait until queue initialization is complete */ 2396 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2397 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2398 break; 2399 DELAY(10); 2400 } 2401 2402 if (i == BGE_TIMEOUT * 2) { 2403 aprint_error_dev(sc->bge_dev, 2404 "flow-through queue init failed\n"); 2405 return ENXIO; 2406 } 2407 2408 /* 2409 * Summary of rings supported by the controller: 2410 * 2411 * Standard Receive Producer Ring 2412 * - This ring is used to feed receive buffers for "standard" 2413 * sized frames (typically 1536 bytes) to the controller. 2414 * 2415 * Jumbo Receive Producer Ring 2416 * - This ring is used to feed receive buffers for jumbo sized 2417 * frames (i.e. anything bigger than the "standard" frames) 2418 * to the controller. 2419 * 2420 * Mini Receive Producer Ring 2421 * - This ring is used to feed receive buffers for "mini" 2422 * sized frames to the controller. 2423 * - This feature required external memory for the controller 2424 * but was never used in a production system. Should always 2425 * be disabled. 2426 * 2427 * Receive Return Ring 2428 * - After the controller has placed an incoming frame into a 2429 * receive buffer that buffer is moved into a receive return 2430 * ring. The driver is then responsible to passing the 2431 * buffer up to the stack. Many versions of the controller 2432 * support multiple RR rings. 2433 * 2434 * Send Ring 2435 * - This ring is used for outgoing frames. Many versions of 2436 * the controller support multiple send rings. 2437 */ 2438 2439 /* 5718 step 15, 57XX step 41 */ 2440 /* Initialize the standard RX ring control block */ 2441 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2442 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2443 /* 5718 step 16 */ 2444 if (BGE_IS_57765_PLUS(sc)) { 2445 /* 2446 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2447 * Bits 15-2 : Maximum RX frame size 2448 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2449 * Bit 0 : Reserved 2450 */ 2451 rcb->bge_maxlen_flags = 2452 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2453 } else if (BGE_IS_5705_PLUS(sc)) { 2454 /* 2455 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2456 * Bits 15-2 : Reserved (should be 0) 2457 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2458 * Bit 0 : Reserved 2459 */ 2460 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2461 } else { 2462 /* 2463 * Ring size is always XXX entries 2464 * Bits 31-16: Maximum RX frame size 2465 * Bits 15-2 : Reserved (should be 0) 2466 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2467 * Bit 0 : Reserved 2468 */ 2469 rcb->bge_maxlen_flags = 2470 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2471 } 2472 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2473 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2474 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2475 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2476 else 2477 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2478 /* Write the standard receive producer ring control block. */ 2479 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2480 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2481 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2482 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2483 2484 /* Reset the standard receive producer ring producer index. */ 2485 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2486 2487 /* 57XX step 42 */ 2488 /* 2489 * Initialize the jumbo RX ring control block 2490 * We set the 'ring disabled' bit in the flags 2491 * field until we're actually ready to start 2492 * using this ring (i.e. once we set the MTU 2493 * high enough to require it). 2494 */ 2495 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2496 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2497 BGE_HOSTADDR(rcb->bge_hostaddr, 2498 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2499 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2500 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2501 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2503 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2504 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2505 else 2506 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2507 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2508 rcb->bge_hostaddr.bge_addr_hi); 2509 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2510 rcb->bge_hostaddr.bge_addr_lo); 2511 /* Program the jumbo receive producer ring RCB parameters. */ 2512 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2513 rcb->bge_maxlen_flags); 2514 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2515 /* Reset the jumbo receive producer ring producer index. */ 2516 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2517 } 2518 2519 /* 57XX step 43 */ 2520 /* Disable the mini receive producer ring RCB. */ 2521 if (BGE_IS_5700_FAMILY(sc)) { 2522 /* Set up dummy disabled mini ring RCB */ 2523 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2524 rcb->bge_maxlen_flags = 2525 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2526 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2527 rcb->bge_maxlen_flags); 2528 /* Reset the mini receive producer ring producer index. */ 2529 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2530 2531 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2532 offsetof(struct bge_ring_data, bge_info), 2533 sizeof (struct bge_gib), 2534 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2535 } 2536 2537 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2538 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2539 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2540 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2541 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2542 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2543 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2544 } 2545 /* 5718 step 14, 57XX step 44 */ 2546 /* 2547 * The BD ring replenish thresholds control how often the 2548 * hardware fetches new BD's from the producer rings in host 2549 * memory. Setting the value too low on a busy system can 2550 * starve the hardware and recue the throughpout. 2551 * 2552 * Set the BD ring replenish thresholds. The recommended 2553 * values are 1/8th the number of descriptors allocated to 2554 * each ring, but since we try to avoid filling the entire 2555 * ring we set these to the minimal value of 8. This needs to 2556 * be done on several of the supported chip revisions anyway, 2557 * to work around HW bugs. 2558 */ 2559 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2560 if (BGE_IS_JUMBO_CAPABLE(sc)) 2561 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2562 2563 /* 5718 step 18 */ 2564 if (BGE_IS_5717_PLUS(sc)) { 2565 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2566 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2567 } 2568 2569 /* 57XX step 45 */ 2570 /* 2571 * Disable all send rings by setting the 'ring disabled' bit 2572 * in the flags field of all the TX send ring control blocks, 2573 * located in NIC memory. 2574 */ 2575 if (BGE_IS_5700_FAMILY(sc)) { 2576 /* 5700 to 5704 had 16 send rings. */ 2577 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2578 } else if (BGE_IS_5717_PLUS(sc)) { 2579 limit = BGE_TX_RINGS_5717_MAX; 2580 } else if (BGE_IS_57765_FAMILY(sc)) { 2581 limit = BGE_TX_RINGS_57765_MAX; 2582 } else 2583 limit = 1; 2584 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2585 for (i = 0; i < limit; i++) { 2586 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2587 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2588 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2589 rcb_addr += sizeof(struct bge_rcb); 2590 } 2591 2592 /* 57XX step 46 and 47 */ 2593 /* Configure send ring RCB 0 (we use only the first ring) */ 2594 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2595 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2596 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2597 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2598 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2599 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2600 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2601 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2602 else 2603 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2604 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2605 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2606 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2607 2608 /* 57XX step 48 */ 2609 /* 2610 * Disable all receive return rings by setting the 2611 * 'ring diabled' bit in the flags field of all the receive 2612 * return ring control blocks, located in NIC memory. 2613 */ 2614 if (BGE_IS_5717_PLUS(sc)) { 2615 /* Should be 17, use 16 until we get an SRAM map. */ 2616 limit = 16; 2617 } else if (BGE_IS_5700_FAMILY(sc)) 2618 limit = BGE_RX_RINGS_MAX; 2619 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2620 BGE_IS_57765_FAMILY(sc)) 2621 limit = 4; 2622 else 2623 limit = 1; 2624 /* Disable all receive return rings */ 2625 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2626 for (i = 0; i < limit; i++) { 2627 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2628 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2629 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2630 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2631 BGE_RCB_FLAG_RING_DISABLED)); 2632 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2633 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2634 (i * (sizeof(uint64_t))), 0); 2635 rcb_addr += sizeof(struct bge_rcb); 2636 } 2637 2638 /* 57XX step 49 */ 2639 /* 2640 * Set up receive return ring 0. Note that the NIC address 2641 * for RX return rings is 0x0. The return rings live entirely 2642 * within the host, so the nicaddr field in the RCB isn't used. 2643 */ 2644 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2645 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2646 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2647 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2648 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2649 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2650 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2651 2652 /* 5718 step 24, 57XX step 53 */ 2653 /* Set random backoff seed for TX */ 2654 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2655 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2656 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2657 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2658 BGE_TX_BACKOFF_SEED_MASK); 2659 2660 /* 5718 step 26, 57XX step 55 */ 2661 /* Set inter-packet gap */ 2662 val = 0x2620; 2663 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2664 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2665 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2666 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2667 2668 /* 5718 step 27, 57XX step 56 */ 2669 /* 2670 * Specify which ring to use for packets that don't match 2671 * any RX rules. 2672 */ 2673 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2674 2675 /* 5718 step 28, 57XX step 57 */ 2676 /* 2677 * Configure number of RX lists. One interrupt distribution 2678 * list, sixteen active lists, one bad frames class. 2679 */ 2680 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2681 2682 /* 5718 step 29, 57XX step 58 */ 2683 /* Inialize RX list placement stats mask. */ 2684 if (BGE_IS_575X_PLUS(sc)) { 2685 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2686 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2687 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2688 } else 2689 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2690 2691 /* 5718 step 30, 57XX step 59 */ 2692 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2693 2694 /* 5718 step 33, 57XX step 62 */ 2695 /* Disable host coalescing until we get it set up */ 2696 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2697 2698 /* 5718 step 34, 57XX step 63 */ 2699 /* Poll to make sure it's shut down. */ 2700 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2701 DELAY(10); 2702 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2703 break; 2704 } 2705 2706 if (i == BGE_TIMEOUT * 2) { 2707 aprint_error_dev(sc->bge_dev, 2708 "host coalescing engine failed to idle\n"); 2709 return ENXIO; 2710 } 2711 2712 /* 5718 step 35, 36, 37 */ 2713 /* Set up host coalescing defaults */ 2714 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2715 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2716 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2717 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2718 if (!(BGE_IS_5705_PLUS(sc))) { 2719 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2720 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2721 } 2722 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2723 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2724 2725 /* Set up address of statistics block */ 2726 if (BGE_IS_5700_FAMILY(sc)) { 2727 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2728 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2729 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2730 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2731 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2732 } 2733 2734 /* 5718 step 38 */ 2735 /* Set up address of status block */ 2736 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2737 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2738 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2739 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2740 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2741 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2742 2743 /* Set up status block size. */ 2744 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2745 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2746 val = BGE_STATBLKSZ_FULL; 2747 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2748 } else { 2749 val = BGE_STATBLKSZ_32BYTE; 2750 bzero(&sc->bge_rdata->bge_status_block, 32); 2751 } 2752 2753 /* 5718 step 39, 57XX step 73 */ 2754 /* Turn on host coalescing state machine */ 2755 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2756 2757 /* 5718 step 40, 57XX step 74 */ 2758 /* Turn on RX BD completion state machine and enable attentions */ 2759 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2760 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2761 2762 /* 5718 step 41, 57XX step 75 */ 2763 /* Turn on RX list placement state machine */ 2764 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2765 2766 /* 57XX step 76 */ 2767 /* Turn on RX list selector state machine. */ 2768 if (!(BGE_IS_5705_PLUS(sc))) 2769 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2770 2771 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2772 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2773 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2774 BGE_MACMODE_FRMHDR_DMA_ENB; 2775 2776 if (sc->bge_flags & BGEF_FIBER_TBI) 2777 val |= BGE_PORTMODE_TBI; 2778 else if (sc->bge_flags & BGEF_FIBER_MII) 2779 val |= BGE_PORTMODE_GMII; 2780 else 2781 val |= BGE_PORTMODE_MII; 2782 2783 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2784 /* Allow APE to send/receive frames. */ 2785 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2786 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2787 2788 /* Turn on DMA, clear stats */ 2789 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2790 /* 5718 step 44 */ 2791 DELAY(40); 2792 2793 /* 5718 step 45, 57XX step 79 */ 2794 /* Set misc. local control, enable interrupts on attentions */ 2795 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2796 if (BGE_IS_5717_PLUS(sc)) { 2797 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2798 /* 5718 step 46 */ 2799 DELAY(100); 2800 } 2801 2802 /* 57XX step 81 */ 2803 /* Turn on DMA completion state machine */ 2804 if (!(BGE_IS_5705_PLUS(sc))) 2805 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2806 2807 /* 5718 step 47, 57XX step 82 */ 2808 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2809 2810 /* 5718 step 48 */ 2811 /* Enable host coalescing bug fix. */ 2812 if (BGE_IS_5755_PLUS(sc)) 2813 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2814 2815 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2816 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2817 2818 /* Turn on write DMA state machine */ 2819 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2820 /* 5718 step 49 */ 2821 DELAY(40); 2822 2823 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2824 2825 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2826 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2827 2828 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2829 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2830 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2831 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2832 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2833 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2834 2835 if (sc->bge_flags & BGEF_PCIE) 2836 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2837 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2838 if (ifp->if_mtu <= ETHERMTU) 2839 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2840 } 2841 if (sc->bge_flags & BGEF_TSO) { 2842 val |= BGE_RDMAMODE_TSO4_ENABLE; 2843 if (BGE_IS_5717_PLUS(sc)) 2844 val |= BGE_RDMAMODE_TSO6_ENABLE; 2845 } 2846 2847 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2848 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2849 BGE_RDMAMODE_H2BNC_VLAN_DET; 2850 /* 2851 * Allow multiple outstanding read requests from 2852 * non-LSO read DMA engine. 2853 */ 2854 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2855 } 2856 2857 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2858 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2859 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2860 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2861 BGE_IS_57765_PLUS(sc)) { 2862 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2863 /* 2864 * Adjust tx margin to prevent TX data corruption and 2865 * fix internal FIFO overflow. 2866 */ 2867 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2868 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2869 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2870 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2871 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2872 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2873 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2874 } 2875 /* 2876 * Enable fix for read DMA FIFO overruns. 2877 * The fix is to limit the number of RX BDs 2878 * the hardware would fetch at a fime. 2879 */ 2880 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2881 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2882 } 2883 2884 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2885 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2886 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2887 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2888 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2889 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2890 /* 2891 * Allow 4KB burst length reads for non-LSO frames. 2892 * Enable 512B burst length reads for buffer descriptors. 2893 */ 2894 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2895 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2896 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2897 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2898 } 2899 /* Turn on read DMA state machine */ 2900 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2901 /* 5718 step 52 */ 2902 delay(40); 2903 2904 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2905 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2906 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2907 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2908 if ((val & 0xFFFF) > BGE_FRAMELEN) 2909 break; 2910 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2911 break; 2912 } 2913 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2914 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2915 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2916 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2917 else 2918 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2919 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2920 } 2921 } 2922 2923 /* 5718 step 56, 57XX step 84 */ 2924 /* Turn on RX data completion state machine */ 2925 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2926 2927 /* Turn on RX data and RX BD initiator state machine */ 2928 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2929 2930 /* 57XX step 85 */ 2931 /* Turn on Mbuf cluster free state machine */ 2932 if (!BGE_IS_5705_PLUS(sc)) 2933 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2934 2935 /* 5718 step 57, 57XX step 86 */ 2936 /* Turn on send data completion state machine */ 2937 val = BGE_SDCMODE_ENABLE; 2938 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2939 val |= BGE_SDCMODE_CDELAY; 2940 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2941 2942 /* 5718 step 58 */ 2943 /* Turn on send BD completion state machine */ 2944 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2945 2946 /* 57XX step 88 */ 2947 /* Turn on RX BD initiator state machine */ 2948 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2949 2950 /* 5718 step 60, 57XX step 90 */ 2951 /* Turn on send data initiator state machine */ 2952 if (sc->bge_flags & BGEF_TSO) { 2953 /* XXX: magic value from Linux driver */ 2954 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2955 BGE_SDIMODE_HW_LSO_PRE_DMA); 2956 } else 2957 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2958 2959 /* 5718 step 61, 57XX step 91 */ 2960 /* Turn on send BD initiator state machine */ 2961 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2962 2963 /* 5718 step 62, 57XX step 92 */ 2964 /* Turn on send BD selector state machine */ 2965 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2966 2967 /* 5718 step 31, 57XX step 60 */ 2968 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2969 /* 5718 step 32, 57XX step 61 */ 2970 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2971 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2972 2973 /* ack/clear link change events */ 2974 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2975 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2976 BGE_MACSTAT_LINK_CHANGED); 2977 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2978 2979 /* 2980 * Enable attention when the link has changed state for 2981 * devices that use auto polling. 2982 */ 2983 if (sc->bge_flags & BGEF_FIBER_TBI) { 2984 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2985 } else { 2986 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 2987 mimode = BGE_MIMODE_500KHZ_CONST; 2988 else 2989 mimode = BGE_MIMODE_BASE; 2990 /* 5718 step 68. 5718 step 69 (optionally). */ 2991 if (BGE_IS_5700_FAMILY(sc) || 2992 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 2993 mimode |= BGE_MIMODE_AUTOPOLL; 2994 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2995 } 2996 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 2997 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 2998 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2999 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3000 BGE_EVTENB_MI_INTERRUPT); 3001 } 3002 3003 /* 3004 * Clear any pending link state attention. 3005 * Otherwise some link state change events may be lost until attention 3006 * is cleared by bge_intr() -> bge_link_upd() sequence. 3007 * It's not necessary on newer BCM chips - perhaps enabling link 3008 * state change attentions implies clearing pending attention. 3009 */ 3010 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3011 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3012 BGE_MACSTAT_LINK_CHANGED); 3013 3014 /* Enable link state change attentions. */ 3015 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3016 3017 return 0; 3018 } 3019 3020 static const struct bge_revision * 3021 bge_lookup_rev(uint32_t chipid) 3022 { 3023 const struct bge_revision *br; 3024 3025 for (br = bge_revisions; br->br_name != NULL; br++) { 3026 if (br->br_chipid == chipid) 3027 return br; 3028 } 3029 3030 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3031 if (br->br_chipid == BGE_ASICREV(chipid)) 3032 return br; 3033 } 3034 3035 return NULL; 3036 } 3037 3038 static const struct bge_product * 3039 bge_lookup(const struct pci_attach_args *pa) 3040 { 3041 const struct bge_product *bp; 3042 3043 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3044 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3045 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3046 return bp; 3047 } 3048 3049 return NULL; 3050 } 3051 3052 static uint32_t 3053 bge_chipid(const struct pci_attach_args *pa) 3054 { 3055 uint32_t id; 3056 3057 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3058 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3059 3060 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3061 switch (PCI_PRODUCT(pa->pa_id)) { 3062 case PCI_PRODUCT_BROADCOM_BCM5717: 3063 case PCI_PRODUCT_BROADCOM_BCM5718: 3064 case PCI_PRODUCT_BROADCOM_BCM5719: 3065 case PCI_PRODUCT_BROADCOM_BCM5720: 3066 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3067 BGE_PCI_GEN2_PRODID_ASICREV); 3068 break; 3069 case PCI_PRODUCT_BROADCOM_BCM57761: 3070 case PCI_PRODUCT_BROADCOM_BCM57762: 3071 case PCI_PRODUCT_BROADCOM_BCM57765: 3072 case PCI_PRODUCT_BROADCOM_BCM57766: 3073 case PCI_PRODUCT_BROADCOM_BCM57781: 3074 case PCI_PRODUCT_BROADCOM_BCM57782: 3075 case PCI_PRODUCT_BROADCOM_BCM57785: 3076 case PCI_PRODUCT_BROADCOM_BCM57786: 3077 case PCI_PRODUCT_BROADCOM_BCM57791: 3078 case PCI_PRODUCT_BROADCOM_BCM57795: 3079 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3080 BGE_PCI_GEN15_PRODID_ASICREV); 3081 break; 3082 default: 3083 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3084 BGE_PCI_PRODID_ASICREV); 3085 break; 3086 } 3087 } 3088 3089 return id; 3090 } 3091 3092 /* 3093 * Return true if MSI can be used with this device. 3094 */ 3095 static int 3096 bge_can_use_msi(struct bge_softc *sc) 3097 { 3098 int can_use_msi = 0; 3099 3100 switch (BGE_ASICREV(sc->bge_chipid)) { 3101 case BGE_ASICREV_BCM5714_A0: 3102 case BGE_ASICREV_BCM5714: 3103 /* 3104 * Apparently, MSI doesn't work when these chips are 3105 * configured in single-port mode. 3106 */ 3107 break; 3108 case BGE_ASICREV_BCM5750: 3109 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3110 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3111 can_use_msi = 1; 3112 break; 3113 default: 3114 if (BGE_IS_575X_PLUS(sc)) 3115 can_use_msi = 1; 3116 } 3117 return (can_use_msi); 3118 } 3119 3120 /* 3121 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3122 * against our list and return its name if we find a match. Note 3123 * that since the Broadcom controller contains VPD support, we 3124 * can get the device name string from the controller itself instead 3125 * of the compiled-in string. This is a little slow, but it guarantees 3126 * we'll always announce the right product name. 3127 */ 3128 static int 3129 bge_probe(device_t parent, cfdata_t match, void *aux) 3130 { 3131 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3132 3133 if (bge_lookup(pa) != NULL) 3134 return 1; 3135 3136 return 0; 3137 } 3138 3139 static void 3140 bge_attach(device_t parent, device_t self, void *aux) 3141 { 3142 struct bge_softc *sc = device_private(self); 3143 struct pci_attach_args *pa = aux; 3144 prop_dictionary_t dict; 3145 const struct bge_product *bp; 3146 const struct bge_revision *br; 3147 pci_chipset_tag_t pc; 3148 const char *intrstr = NULL; 3149 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3150 uint32_t command; 3151 struct ifnet *ifp; 3152 uint32_t misccfg, mimode; 3153 void * kva; 3154 u_char eaddr[ETHER_ADDR_LEN]; 3155 pcireg_t memtype, subid, reg; 3156 bus_addr_t memaddr; 3157 uint32_t pm_ctl; 3158 bool no_seeprom; 3159 int capmask; 3160 int mii_flags; 3161 int map_flags; 3162 char intrbuf[PCI_INTRSTR_LEN]; 3163 3164 bp = bge_lookup(pa); 3165 KASSERT(bp != NULL); 3166 3167 sc->sc_pc = pa->pa_pc; 3168 sc->sc_pcitag = pa->pa_tag; 3169 sc->bge_dev = self; 3170 3171 sc->bge_pa = *pa; 3172 pc = sc->sc_pc; 3173 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3174 3175 aprint_naive(": Ethernet controller\n"); 3176 aprint_normal(": %s Ethernet\n", bp->bp_name); 3177 3178 /* 3179 * Map control/status registers. 3180 */ 3181 DPRINTFN(5, ("Map control/status regs\n")); 3182 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3183 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3184 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3185 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3186 3187 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3188 aprint_error_dev(sc->bge_dev, 3189 "failed to enable memory mapping!\n"); 3190 return; 3191 } 3192 3193 DPRINTFN(5, ("pci_mem_find\n")); 3194 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3195 switch (memtype) { 3196 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3197 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3198 #if 0 3199 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3200 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3201 &memaddr, &sc->bge_bsize) == 0) 3202 break; 3203 #else 3204 /* 3205 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3206 * system get NMI on boot (PR#48451). This problem might not be 3207 * the driver's bug but our PCI common part's bug. Until we 3208 * find a real reason, we ignore the prefetchable bit. 3209 */ 3210 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3211 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3212 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3213 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3214 map_flags, &sc->bge_bhandle) == 0) { 3215 sc->bge_btag = pa->pa_memt; 3216 break; 3217 } 3218 } 3219 #endif 3220 /* FALLTHROUGH */ 3221 default: 3222 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3223 return; 3224 } 3225 3226 /* Save various chip information. */ 3227 sc->bge_chipid = bge_chipid(pa); 3228 sc->bge_phy_addr = bge_phy_addr(sc); 3229 3230 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3231 &sc->bge_pciecap, NULL) != 0) { 3232 /* PCIe */ 3233 sc->bge_flags |= BGEF_PCIE; 3234 /* Extract supported maximum payload size. */ 3235 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3236 sc->bge_pciecap + PCIE_DCAP); 3237 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3238 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3239 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3240 sc->bge_expmrq = 2048; 3241 else 3242 sc->bge_expmrq = 4096; 3243 bge_set_max_readrq(sc); 3244 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3245 /* PCIe without PCIe cap */ 3246 sc->bge_flags |= BGEF_PCIE; 3247 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3248 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3249 /* PCI-X */ 3250 sc->bge_flags |= BGEF_PCIX; 3251 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3252 &sc->bge_pcixcap, NULL) == 0) 3253 aprint_error_dev(sc->bge_dev, 3254 "unable to find PCIX capability\n"); 3255 } 3256 3257 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3258 /* 3259 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3260 * can clobber the chip's PCI config-space power control 3261 * registers, leaving the card in D3 powersave state. We do 3262 * not have memory-mapped registers in this state, so force 3263 * device into D0 state before starting initialization. 3264 */ 3265 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3266 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3267 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3268 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3269 DELAY(1000); /* 27 usec is allegedly sufficent */ 3270 } 3271 3272 /* Save chipset family. */ 3273 switch (BGE_ASICREV(sc->bge_chipid)) { 3274 case BGE_ASICREV_BCM5717: 3275 case BGE_ASICREV_BCM5719: 3276 case BGE_ASICREV_BCM5720: 3277 sc->bge_flags |= BGEF_5717_PLUS; 3278 /* FALLTHROUGH */ 3279 case BGE_ASICREV_BCM57765: 3280 case BGE_ASICREV_BCM57766: 3281 if (!BGE_IS_5717_PLUS(sc)) 3282 sc->bge_flags |= BGEF_57765_FAMILY; 3283 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3284 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3285 /* Jumbo frame on BCM5719 A0 does not work. */ 3286 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3287 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3288 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3289 break; 3290 case BGE_ASICREV_BCM5755: 3291 case BGE_ASICREV_BCM5761: 3292 case BGE_ASICREV_BCM5784: 3293 case BGE_ASICREV_BCM5785: 3294 case BGE_ASICREV_BCM5787: 3295 case BGE_ASICREV_BCM57780: 3296 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3297 break; 3298 case BGE_ASICREV_BCM5700: 3299 case BGE_ASICREV_BCM5701: 3300 case BGE_ASICREV_BCM5703: 3301 case BGE_ASICREV_BCM5704: 3302 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3303 break; 3304 case BGE_ASICREV_BCM5714_A0: 3305 case BGE_ASICREV_BCM5780: 3306 case BGE_ASICREV_BCM5714: 3307 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3308 /* FALLTHROUGH */ 3309 case BGE_ASICREV_BCM5750: 3310 case BGE_ASICREV_BCM5752: 3311 case BGE_ASICREV_BCM5906: 3312 sc->bge_flags |= BGEF_575X_PLUS; 3313 /* FALLTHROUGH */ 3314 case BGE_ASICREV_BCM5705: 3315 sc->bge_flags |= BGEF_5705_PLUS; 3316 break; 3317 } 3318 3319 /* Identify chips with APE processor. */ 3320 switch (BGE_ASICREV(sc->bge_chipid)) { 3321 case BGE_ASICREV_BCM5717: 3322 case BGE_ASICREV_BCM5719: 3323 case BGE_ASICREV_BCM5720: 3324 case BGE_ASICREV_BCM5761: 3325 sc->bge_flags |= BGEF_APE; 3326 break; 3327 } 3328 3329 /* 3330 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3331 * not actually a MAC controller bug but an issue with the embedded 3332 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3333 */ 3334 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3335 sc->bge_flags |= BGEF_40BIT_BUG; 3336 3337 /* Chips with APE need BAR2 access for APE registers/memory. */ 3338 if ((sc->bge_flags & BGEF_APE) != 0) { 3339 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3340 #if 0 3341 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3342 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3343 &sc->bge_apesize)) { 3344 aprint_error_dev(sc->bge_dev, 3345 "couldn't map BAR2 memory\n"); 3346 return; 3347 } 3348 #else 3349 /* 3350 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3351 * system get NMI on boot (PR#48451). This problem might not be 3352 * the driver's bug but our PCI common part's bug. Until we 3353 * find a real reason, we ignore the prefetchable bit. 3354 */ 3355 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3356 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3357 aprint_error_dev(sc->bge_dev, 3358 "couldn't map BAR2 memory\n"); 3359 return; 3360 } 3361 3362 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3363 if (bus_space_map(pa->pa_memt, memaddr, 3364 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3365 aprint_error_dev(sc->bge_dev, 3366 "couldn't map BAR2 memory\n"); 3367 return; 3368 } 3369 sc->bge_apetag = pa->pa_memt; 3370 #endif 3371 3372 /* Enable APE register/memory access by host driver. */ 3373 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3374 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3375 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3376 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3377 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3378 3379 bge_ape_lock_init(sc); 3380 bge_ape_read_fw_ver(sc); 3381 } 3382 3383 /* Identify the chips that use an CPMU. */ 3384 if (BGE_IS_5717_PLUS(sc) || 3385 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3386 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3387 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3388 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3389 sc->bge_flags |= BGEF_CPMU_PRESENT; 3390 3391 /* Set MI_MODE */ 3392 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3393 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3394 mimode |= BGE_MIMODE_500KHZ_CONST; 3395 else 3396 mimode |= BGE_MIMODE_BASE; 3397 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3398 3399 /* 3400 * When using the BCM5701 in PCI-X mode, data corruption has 3401 * been observed in the first few bytes of some received packets. 3402 * Aligning the packet buffer in memory eliminates the corruption. 3403 * Unfortunately, this misaligns the packet payloads. On platforms 3404 * which do not support unaligned accesses, we will realign the 3405 * payloads by copying the received packets. 3406 */ 3407 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3408 sc->bge_flags & BGEF_PCIX) 3409 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3410 3411 if (BGE_IS_5700_FAMILY(sc)) 3412 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3413 3414 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3415 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3416 3417 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3418 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3419 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3420 sc->bge_flags |= BGEF_IS_5788; 3421 3422 /* 3423 * Some controllers seem to require a special firmware to use 3424 * TSO. But the firmware is not available to FreeBSD and Linux 3425 * claims that the TSO performed by the firmware is slower than 3426 * hardware based TSO. Moreover the firmware based TSO has one 3427 * known bug which can't handle TSO if ethernet header + IP/TCP 3428 * header is greater than 80 bytes. The workaround for the TSO 3429 * bug exist but it seems it's too expensive than not using 3430 * TSO at all. Some hardwares also have the TSO bug so limit 3431 * the TSO to the controllers that are not affected TSO issues 3432 * (e.g. 5755 or higher). 3433 */ 3434 if (BGE_IS_5755_PLUS(sc)) { 3435 /* 3436 * BCM5754 and BCM5787 shares the same ASIC id so 3437 * explicit device id check is required. 3438 */ 3439 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3440 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3441 sc->bge_flags |= BGEF_TSO; 3442 /* TSO on BCM5719 A0 does not work. */ 3443 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3444 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3445 sc->bge_flags &= ~BGEF_TSO; 3446 } 3447 3448 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3449 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3450 (misccfg == 0x4000 || misccfg == 0x8000)) || 3451 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3452 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3453 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3454 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3455 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3456 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3457 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3458 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3459 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3460 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3461 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3463 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3464 /* These chips are 10/100 only. */ 3465 capmask &= ~BMSR_EXTSTAT; 3466 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3467 } 3468 3469 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3470 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3471 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3472 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3473 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3474 3475 /* Set various PHY bug flags. */ 3476 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3477 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3478 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3479 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3480 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3481 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3482 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3483 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3484 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3486 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3487 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3488 if (BGE_IS_5705_PLUS(sc) && 3489 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3490 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3491 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3492 !BGE_IS_57765_PLUS(sc)) { 3493 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3494 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3495 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3496 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3497 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3498 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3499 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3500 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3501 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3502 } else 3503 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3504 } 3505 3506 /* 3507 * SEEPROM check. 3508 * First check if firmware knows we do not have SEEPROM. 3509 */ 3510 if (prop_dictionary_get_bool(device_properties(self), 3511 "without-seeprom", &no_seeprom) && no_seeprom) 3512 sc->bge_flags |= BGEF_NO_EEPROM; 3513 3514 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3515 sc->bge_flags |= BGEF_NO_EEPROM; 3516 3517 /* Now check the 'ROM failed' bit on the RX CPU */ 3518 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3519 sc->bge_flags |= BGEF_NO_EEPROM; 3520 3521 sc->bge_asf_mode = 0; 3522 /* No ASF if APE present. */ 3523 if ((sc->bge_flags & BGEF_APE) == 0) { 3524 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3525 BGE_SRAM_DATA_SIG_MAGIC)) { 3526 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3527 BGE_HWCFG_ASF) { 3528 sc->bge_asf_mode |= ASF_ENABLE; 3529 sc->bge_asf_mode |= ASF_STACKUP; 3530 if (BGE_IS_575X_PLUS(sc)) 3531 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3532 } 3533 } 3534 } 3535 3536 int counts[PCI_INTR_TYPE_SIZE] = { 3537 [PCI_INTR_TYPE_INTX] = 1, 3538 [PCI_INTR_TYPE_MSI] = 1, 3539 [PCI_INTR_TYPE_MSIX] = 1, 3540 }; 3541 int max_type = PCI_INTR_TYPE_MSIX; 3542 3543 if (!bge_can_use_msi(sc)) { 3544 /* MSI broken, allow only INTx */ 3545 max_type = PCI_INTR_TYPE_INTX; 3546 } 3547 3548 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3549 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3550 return; 3551 } 3552 3553 DPRINTFN(5, ("pci_intr_string\n")); 3554 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3555 sizeof(intrbuf)); 3556 DPRINTFN(5, ("pci_intr_establish\n")); 3557 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3558 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3559 if (sc->bge_intrhand == NULL) { 3560 pci_intr_release(pc, sc->bge_pihp, 1); 3561 sc->bge_pihp = NULL; 3562 3563 aprint_error_dev(self, "couldn't establish interrupt"); 3564 if (intrstr != NULL) 3565 aprint_error(" at %s", intrstr); 3566 aprint_error("\n"); 3567 return; 3568 } 3569 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3570 3571 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3572 case PCI_INTR_TYPE_MSIX: 3573 case PCI_INTR_TYPE_MSI: 3574 KASSERT(bge_can_use_msi(sc)); 3575 sc->bge_flags |= BGEF_MSI; 3576 break; 3577 default: 3578 /* nothing to do */ 3579 break; 3580 } 3581 3582 /* 3583 * All controllers except BCM5700 supports tagged status but 3584 * we use tagged status only for MSI case on BCM5717. Otherwise 3585 * MSI on BCM5717 does not work. 3586 */ 3587 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3588 sc->bge_flags |= BGEF_TAGGED_STATUS; 3589 3590 /* 3591 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3592 * lock in bge_reset(). 3593 */ 3594 CSR_WRITE_4(sc, BGE_EE_ADDR, 3595 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3596 delay(1000); 3597 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3598 3599 bge_stop_fw(sc); 3600 bge_sig_pre_reset(sc, BGE_RESET_START); 3601 if (bge_reset(sc)) 3602 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3603 3604 /* 3605 * Read the hardware config word in the first 32k of NIC internal 3606 * memory, or fall back to the config word in the EEPROM. 3607 * Note: on some BCM5700 cards, this value appears to be unset. 3608 */ 3609 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3610 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3611 BGE_SRAM_DATA_SIG_MAGIC) { 3612 uint32_t tmp; 3613 3614 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3615 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3616 BGE_SRAM_DATA_VER_SHIFT; 3617 if ((0 < tmp) && (tmp < 0x100)) 3618 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3619 if (sc->bge_flags & BGEF_PCIE) 3620 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3621 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3622 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3623 if (BGE_IS_5717_PLUS(sc)) 3624 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3625 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3626 bge_read_eeprom(sc, (void *)&hwcfg, 3627 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3628 hwcfg = be32toh(hwcfg); 3629 } 3630 aprint_normal_dev(sc->bge_dev, 3631 "HW config %08x, %08x, %08x, %08x %08x\n", 3632 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3633 3634 bge_sig_legacy(sc, BGE_RESET_START); 3635 bge_sig_post_reset(sc, BGE_RESET_START); 3636 3637 if (bge_chipinit(sc)) { 3638 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3639 bge_release_resources(sc); 3640 return; 3641 } 3642 3643 /* 3644 * Get station address from the EEPROM. 3645 */ 3646 if (bge_get_eaddr(sc, eaddr)) { 3647 aprint_error_dev(sc->bge_dev, 3648 "failed to read station address\n"); 3649 bge_release_resources(sc); 3650 return; 3651 } 3652 3653 br = bge_lookup_rev(sc->bge_chipid); 3654 3655 if (br == NULL) { 3656 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3657 sc->bge_chipid); 3658 } else { 3659 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3660 br->br_name, sc->bge_chipid); 3661 } 3662 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3663 3664 /* Allocate the general information block and ring buffers. */ 3665 if (pci_dma64_available(pa)) { 3666 sc->bge_dmatag = pa->pa_dmat64; 3667 sc->bge_dmatag32 = pa->pa_dmat; 3668 sc->bge_dma64 = true; 3669 } else { 3670 sc->bge_dmatag = pa->pa_dmat; 3671 sc->bge_dmatag32 = pa->pa_dmat; 3672 sc->bge_dma64 = false; 3673 } 3674 3675 /* 40bit DMA workaround */ 3676 if (sizeof(bus_addr_t) > 4) { 3677 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3678 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3679 3680 if (bus_dmatag_subregion(olddmatag, 0, 3681 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3682 BUS_DMA_NOWAIT) != 0) { 3683 aprint_error_dev(self, 3684 "WARNING: failed to restrict dma range," 3685 " falling back to parent bus dma range\n"); 3686 sc->bge_dmatag = olddmatag; 3687 } 3688 } 3689 } 3690 SLIST_INIT(&sc->txdma_list); 3691 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3692 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3693 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3694 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3695 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3696 return; 3697 } 3698 DPRINTFN(5, ("bus_dmamem_map\n")); 3699 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3700 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3701 BUS_DMA_NOWAIT)) { 3702 aprint_error_dev(sc->bge_dev, 3703 "can't map DMA buffers (%zu bytes)\n", 3704 sizeof(struct bge_ring_data)); 3705 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3706 sc->bge_ring_rseg); 3707 return; 3708 } 3709 DPRINTFN(5, ("bus_dmamem_create\n")); 3710 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3711 sizeof(struct bge_ring_data), 0, 3712 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3713 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3714 bus_dmamem_unmap(sc->bge_dmatag, kva, 3715 sizeof(struct bge_ring_data)); 3716 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3717 sc->bge_ring_rseg); 3718 return; 3719 } 3720 DPRINTFN(5, ("bus_dmamem_load\n")); 3721 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3722 sizeof(struct bge_ring_data), NULL, 3723 BUS_DMA_NOWAIT)) { 3724 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3725 bus_dmamem_unmap(sc->bge_dmatag, kva, 3726 sizeof(struct bge_ring_data)); 3727 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3728 sc->bge_ring_rseg); 3729 return; 3730 } 3731 3732 DPRINTFN(5, ("bzero\n")); 3733 sc->bge_rdata = (struct bge_ring_data *)kva; 3734 3735 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3736 3737 /* Try to allocate memory for jumbo buffers. */ 3738 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3739 if (bge_alloc_jumbo_mem(sc)) { 3740 aprint_error_dev(sc->bge_dev, 3741 "jumbo buffer allocation failed\n"); 3742 } else 3743 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3744 } 3745 3746 /* Set default tuneable values. */ 3747 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3748 sc->bge_rx_coal_ticks = 150; 3749 sc->bge_rx_max_coal_bds = 64; 3750 sc->bge_tx_coal_ticks = 300; 3751 sc->bge_tx_max_coal_bds = 400; 3752 if (BGE_IS_5705_PLUS(sc)) { 3753 sc->bge_tx_coal_ticks = (12 * 5); 3754 sc->bge_tx_max_coal_bds = (12 * 5); 3755 aprint_verbose_dev(sc->bge_dev, 3756 "setting short Tx thresholds\n"); 3757 } 3758 3759 if (BGE_IS_5717_PLUS(sc)) 3760 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3761 else if (BGE_IS_5705_PLUS(sc)) 3762 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3763 else 3764 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3765 3766 /* Set up ifnet structure */ 3767 ifp = &sc->ethercom.ec_if; 3768 ifp->if_softc = sc; 3769 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3770 ifp->if_ioctl = bge_ioctl; 3771 ifp->if_stop = bge_stop; 3772 ifp->if_start = bge_start; 3773 ifp->if_init = bge_init; 3774 ifp->if_watchdog = bge_watchdog; 3775 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3776 IFQ_SET_READY(&ifp->if_snd); 3777 DPRINTFN(5, ("strcpy if_xname\n")); 3778 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3779 3780 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3781 sc->ethercom.ec_if.if_capabilities |= 3782 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3783 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3784 sc->ethercom.ec_if.if_capabilities |= 3785 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3786 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3787 #endif 3788 sc->ethercom.ec_capabilities |= 3789 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3790 3791 if (sc->bge_flags & BGEF_TSO) 3792 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3793 3794 /* 3795 * Do MII setup. 3796 */ 3797 DPRINTFN(5, ("mii setup\n")); 3798 sc->bge_mii.mii_ifp = ifp; 3799 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3800 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3801 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3802 3803 /* 3804 * Figure out what sort of media we have by checking the hardware 3805 * config word. Note: on some BCM5700 cards, this value appears to be 3806 * unset. If that's the case, we have to rely on identifying the NIC 3807 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3808 * The SysKonnect SK-9D41 is a 1000baseSX card. 3809 */ 3810 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3811 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3812 if (BGE_IS_5705_PLUS(sc)) { 3813 sc->bge_flags |= BGEF_FIBER_MII; 3814 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3815 } else 3816 sc->bge_flags |= BGEF_FIBER_TBI; 3817 } 3818 3819 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3820 if (BGE_IS_JUMBO_CAPABLE(sc)) 3821 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3822 3823 /* set phyflags and chipid before mii_attach() */ 3824 dict = device_properties(self); 3825 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3826 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3827 3828 if (sc->bge_flags & BGEF_FIBER_TBI) { 3829 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3830 bge_ifmedia_sts); 3831 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3832 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3833 0, NULL); 3834 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3835 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3836 /* Pretend the user requested this setting */ 3837 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3838 } else { 3839 /* 3840 * Do transceiver setup and tell the firmware the 3841 * driver is down so we can try to get access the 3842 * probe if ASF is running. Retry a couple of times 3843 * if we get a conflict with the ASF firmware accessing 3844 * the PHY. 3845 */ 3846 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3847 bge_asf_driver_up(sc); 3848 3849 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3850 bge_ifmedia_sts); 3851 mii_flags = MIIF_DOPAUSE; 3852 if (sc->bge_flags & BGEF_FIBER_MII) 3853 mii_flags |= MIIF_HAVEFIBER; 3854 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 3855 MII_OFFSET_ANY, mii_flags); 3856 3857 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3858 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3859 ifmedia_add(&sc->bge_mii.mii_media, 3860 IFM_ETHER|IFM_MANUAL, 0, NULL); 3861 ifmedia_set(&sc->bge_mii.mii_media, 3862 IFM_ETHER|IFM_MANUAL); 3863 } else 3864 ifmedia_set(&sc->bge_mii.mii_media, 3865 IFM_ETHER|IFM_AUTO); 3866 3867 /* 3868 * Now tell the firmware we are going up after probing the PHY 3869 */ 3870 if (sc->bge_asf_mode & ASF_STACKUP) 3871 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3872 } 3873 3874 /* 3875 * Call MI attach routine. 3876 */ 3877 DPRINTFN(5, ("if_attach\n")); 3878 if_attach(ifp); 3879 if_deferred_start_init(ifp, NULL); 3880 DPRINTFN(5, ("ether_ifattach\n")); 3881 ether_ifattach(ifp, eaddr); 3882 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3883 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3884 RND_TYPE_NET, RND_FLAG_DEFAULT); 3885 #ifdef BGE_EVENT_COUNTERS 3886 /* 3887 * Attach event counters. 3888 */ 3889 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3890 NULL, device_xname(sc->bge_dev), "intr"); 3891 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3892 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3893 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3894 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3895 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3896 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3897 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3898 NULL, device_xname(sc->bge_dev), "tx_xon"); 3899 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3900 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3901 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3902 NULL, device_xname(sc->bge_dev), "rx_xon"); 3903 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3904 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3905 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3906 NULL, device_xname(sc->bge_dev), "xoffentered"); 3907 #endif /* BGE_EVENT_COUNTERS */ 3908 DPRINTFN(5, ("callout_init\n")); 3909 callout_init(&sc->bge_timeout, 0); 3910 3911 if (pmf_device_register(self, NULL, NULL)) 3912 pmf_class_network_register(self, ifp); 3913 else 3914 aprint_error_dev(self, "couldn't establish power handler\n"); 3915 3916 bge_sysctl_init(sc); 3917 3918 #ifdef BGE_DEBUG 3919 bge_debug_info(sc); 3920 #endif 3921 } 3922 3923 /* 3924 * Stop all chip I/O so that the kernel's probe routines don't 3925 * get confused by errant DMAs when rebooting. 3926 */ 3927 static int 3928 bge_detach(device_t self, int flags __unused) 3929 { 3930 struct bge_softc *sc = device_private(self); 3931 struct ifnet *ifp = &sc->ethercom.ec_if; 3932 int s; 3933 3934 s = splnet(); 3935 /* Stop the interface. Callouts are stopped in it. */ 3936 bge_stop(ifp, 1); 3937 splx(s); 3938 3939 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3940 3941 /* Delete all remaining media. */ 3942 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3943 3944 ether_ifdetach(ifp); 3945 if_detach(ifp); 3946 3947 bge_release_resources(sc); 3948 3949 return 0; 3950 } 3951 3952 static void 3953 bge_release_resources(struct bge_softc *sc) 3954 { 3955 3956 /* Detach sysctl */ 3957 if (sc->bge_log != NULL) 3958 sysctl_teardown(&sc->bge_log); 3959 3960 #ifdef BGE_EVENT_COUNTERS 3961 /* Detach event counters. */ 3962 evcnt_detach(&sc->bge_ev_intr); 3963 evcnt_detach(&sc->bge_ev_intr_spurious); 3964 evcnt_detach(&sc->bge_ev_intr_spurious2); 3965 evcnt_detach(&sc->bge_ev_tx_xoff); 3966 evcnt_detach(&sc->bge_ev_tx_xon); 3967 evcnt_detach(&sc->bge_ev_rx_xoff); 3968 evcnt_detach(&sc->bge_ev_rx_xon); 3969 evcnt_detach(&sc->bge_ev_rx_macctl); 3970 evcnt_detach(&sc->bge_ev_xoffentered); 3971 #endif /* BGE_EVENT_COUNTERS */ 3972 3973 /* Disestablish the interrupt handler */ 3974 if (sc->bge_intrhand != NULL) { 3975 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3976 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 3977 sc->bge_intrhand = NULL; 3978 } 3979 3980 if (sc->bge_dmatag != NULL) { 3981 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3982 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3983 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3984 sizeof(struct bge_ring_data)); 3985 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3986 sc->bge_ring_rseg); 3987 } 3988 3989 /* Unmap the device registers */ 3990 if (sc->bge_bsize != 0) { 3991 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3992 sc->bge_bsize = 0; 3993 } 3994 3995 /* Unmap the APE registers */ 3996 if (sc->bge_apesize != 0) { 3997 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3998 sc->bge_apesize); 3999 sc->bge_apesize = 0; 4000 } 4001 } 4002 4003 static int 4004 bge_reset(struct bge_softc *sc) 4005 { 4006 uint32_t cachesize, command; 4007 uint32_t reset, mac_mode, mac_mode_mask; 4008 pcireg_t devctl, reg; 4009 int i, val; 4010 void (*write_op)(struct bge_softc *, int, int); 4011 4012 /* Make mask for BGE_MAC_MODE register. */ 4013 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4014 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4015 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4016 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4017 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4018 4019 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4020 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4021 if (sc->bge_flags & BGEF_PCIE) 4022 write_op = bge_writemem_direct; 4023 else 4024 write_op = bge_writemem_ind; 4025 } else 4026 write_op = bge_writereg_ind; 4027 4028 /* 57XX step 4 */ 4029 /* Acquire the NVM lock */ 4030 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4031 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4032 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4033 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4034 for (i = 0; i < 8000; i++) { 4035 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4036 BGE_NVRAMSWARB_GNT1) 4037 break; 4038 DELAY(20); 4039 } 4040 if (i == 8000) { 4041 printf("%s: NVRAM lock timedout!\n", 4042 device_xname(sc->bge_dev)); 4043 } 4044 } 4045 4046 /* Take APE lock when performing reset. */ 4047 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4048 4049 /* 57XX step 3 */ 4050 /* Save some important PCI state. */ 4051 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4052 /* 5718 reset step 3 */ 4053 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4054 4055 /* 5718 reset step 5, 57XX step 5b-5d */ 4056 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4057 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4058 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4059 4060 /* XXX ???: Disable fastboot on controllers that support it. */ 4061 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4062 BGE_IS_5755_PLUS(sc)) 4063 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4064 4065 /* 5718 reset step 2, 57XX step 6 */ 4066 /* 4067 * Write the magic number to SRAM at offset 0xB50. 4068 * When firmware finishes its initialization it will 4069 * write ~BGE_MAGIC_NUMBER to the same location. 4070 */ 4071 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4072 4073 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4074 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4075 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4076 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4077 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4078 } 4079 4080 /* 5718 reset step 6, 57XX step 7 */ 4081 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4082 /* 4083 * XXX: from FreeBSD/Linux; no documentation 4084 */ 4085 if (sc->bge_flags & BGEF_PCIE) { 4086 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4087 !BGE_IS_57765_PLUS(sc) && 4088 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4089 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4090 /* PCI Express 1.0 system */ 4091 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4092 BGE_PHY_PCIE_SCRAM_MODE); 4093 } 4094 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4095 /* 4096 * Prevent PCI Express link training 4097 * during global reset. 4098 */ 4099 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4100 reset |= (1 << 29); 4101 } 4102 } 4103 4104 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4105 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4106 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4107 i | BGE_VCPU_STATUS_DRV_RESET); 4108 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4109 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4110 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4111 } 4112 4113 /* 4114 * Set GPHY Power Down Override to leave GPHY 4115 * powered up in D0 uninitialized. 4116 */ 4117 if (BGE_IS_5705_PLUS(sc) && 4118 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4119 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4120 4121 /* Issue global reset */ 4122 write_op(sc, BGE_MISC_CFG, reset); 4123 4124 /* 5718 reset step 7, 57XX step 8 */ 4125 if (sc->bge_flags & BGEF_PCIE) 4126 delay(100*1000); /* too big */ 4127 else 4128 delay(1000); 4129 4130 if (sc->bge_flags & BGEF_PCIE) { 4131 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4132 DELAY(500000); 4133 /* XXX: Magic Numbers */ 4134 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4135 BGE_PCI_UNKNOWN0); 4136 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4137 BGE_PCI_UNKNOWN0, 4138 reg | (1 << 15)); 4139 } 4140 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4141 sc->bge_pciecap + PCIE_DCSR); 4142 /* Clear enable no snoop and disable relaxed ordering. */ 4143 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4144 PCIE_DCSR_ENA_NO_SNOOP); 4145 4146 /* Set PCIE max payload size to 128 for older PCIe devices */ 4147 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4148 devctl &= ~(0x00e0); 4149 /* Clear device status register. Write 1b to clear */ 4150 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4151 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4152 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4153 sc->bge_pciecap + PCIE_DCSR, devctl); 4154 bge_set_max_readrq(sc); 4155 } 4156 4157 /* From Linux: dummy read to flush PCI posted writes */ 4158 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4159 4160 /* 4161 * Reset some of the PCI state that got zapped by reset 4162 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4163 * set, too. 4164 */ 4165 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4166 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4167 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4168 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4169 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4170 (sc->bge_flags & BGEF_PCIX) != 0) 4171 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4172 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4173 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4174 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4175 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4176 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4177 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4178 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4179 4180 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4181 if (sc->bge_flags & BGEF_PCIX) { 4182 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4183 + PCIX_CMD); 4184 /* Set max memory read byte count to 2K */ 4185 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4186 reg &= ~PCIX_CMD_BYTECNT_MASK; 4187 reg |= PCIX_CMD_BCNT_2048; 4188 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4189 /* 4190 * For 5704, set max outstanding split transaction 4191 * field to 0 (0 means it supports 1 request) 4192 */ 4193 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4194 | PCIX_CMD_BYTECNT_MASK); 4195 reg |= PCIX_CMD_BCNT_2048; 4196 } 4197 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4198 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4199 } 4200 4201 /* 5718 reset step 10, 57XX step 12 */ 4202 /* Enable memory arbiter. */ 4203 if (BGE_IS_5714_FAMILY(sc)) { 4204 val = CSR_READ_4(sc, BGE_MARB_MODE); 4205 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4206 } else 4207 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4208 4209 /* XXX 5721, 5751 and 5752 */ 4210 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4211 /* Step 19: */ 4212 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4213 /* Step 20: */ 4214 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4215 } 4216 4217 /* 5718 reset step 12, 57XX step 15 and 16 */ 4218 /* Fix up byte swapping */ 4219 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4220 4221 /* 5718 reset step 13, 57XX step 17 */ 4222 /* Poll until the firmware initialization is complete */ 4223 bge_poll_fw(sc); 4224 4225 /* 57XX step 21 */ 4226 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4227 pcireg_t msidata; 4228 4229 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4230 BGE_PCI_MSI_DATA); 4231 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4232 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4233 msidata); 4234 } 4235 4236 /* 57XX step 18 */ 4237 /* Write mac mode. */ 4238 val = CSR_READ_4(sc, BGE_MAC_MODE); 4239 /* Restore mac_mode_mask's bits using mac_mode */ 4240 val = (val & ~mac_mode_mask) | mac_mode; 4241 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4242 DELAY(40); 4243 4244 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4245 4246 /* 4247 * The 5704 in TBI mode apparently needs some special 4248 * adjustment to insure the SERDES drive level is set 4249 * to 1.2V. 4250 */ 4251 if (sc->bge_flags & BGEF_FIBER_TBI && 4252 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4253 uint32_t serdescfg; 4254 4255 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4256 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4257 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4258 } 4259 4260 if (sc->bge_flags & BGEF_PCIE && 4261 !BGE_IS_57765_PLUS(sc) && 4262 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4263 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4264 uint32_t v; 4265 4266 /* Enable PCI Express bug fix */ 4267 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4268 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4269 v | BGE_TLP_DATA_FIFO_PROTECT); 4270 } 4271 4272 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4273 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4274 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4275 4276 return 0; 4277 } 4278 4279 /* 4280 * Frame reception handling. This is called if there's a frame 4281 * on the receive return list. 4282 * 4283 * Note: we have to be able to handle two possibilities here: 4284 * 1) the frame is from the jumbo receive ring 4285 * 2) the frame is from the standard receive ring 4286 */ 4287 4288 static void 4289 bge_rxeof(struct bge_softc *sc) 4290 { 4291 struct ifnet *ifp; 4292 uint16_t rx_prod, rx_cons; 4293 int stdcnt = 0, jumbocnt = 0; 4294 bus_dmamap_t dmamap; 4295 bus_addr_t offset, toff; 4296 bus_size_t tlen; 4297 int tosync; 4298 4299 rx_cons = sc->bge_rx_saved_considx; 4300 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4301 4302 /* Nothing to do */ 4303 if (rx_cons == rx_prod) 4304 return; 4305 4306 ifp = &sc->ethercom.ec_if; 4307 4308 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4309 offsetof(struct bge_ring_data, bge_status_block), 4310 sizeof (struct bge_status_block), 4311 BUS_DMASYNC_POSTREAD); 4312 4313 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4314 tosync = rx_prod - rx_cons; 4315 4316 if (tosync != 0) 4317 rnd_add_uint32(&sc->rnd_source, tosync); 4318 4319 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4320 4321 if (tosync < 0) { 4322 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4323 sizeof (struct bge_rx_bd); 4324 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4325 toff, tlen, BUS_DMASYNC_POSTREAD); 4326 tosync = -tosync; 4327 } 4328 4329 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4330 offset, tosync * sizeof (struct bge_rx_bd), 4331 BUS_DMASYNC_POSTREAD); 4332 4333 while (rx_cons != rx_prod) { 4334 struct bge_rx_bd *cur_rx; 4335 uint32_t rxidx; 4336 struct mbuf *m = NULL; 4337 4338 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4339 4340 rxidx = cur_rx->bge_idx; 4341 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4342 4343 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4344 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4345 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4346 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4347 jumbocnt++; 4348 bus_dmamap_sync(sc->bge_dmatag, 4349 sc->bge_cdata.bge_rx_jumbo_map, 4350 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4351 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4352 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4353 ifp->if_ierrors++; 4354 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4355 continue; 4356 } 4357 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4358 NULL)== ENOBUFS) { 4359 ifp->if_ierrors++; 4360 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4361 continue; 4362 } 4363 } else { 4364 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4365 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4366 4367 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4368 stdcnt++; 4369 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4370 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4371 if (dmamap == NULL) { 4372 ifp->if_ierrors++; 4373 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4374 continue; 4375 } 4376 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4377 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4378 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4379 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4380 ifp->if_ierrors++; 4381 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4382 continue; 4383 } 4384 if (bge_newbuf_std(sc, sc->bge_std, 4385 NULL, dmamap) == ENOBUFS) { 4386 ifp->if_ierrors++; 4387 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4388 continue; 4389 } 4390 } 4391 4392 #ifndef __NO_STRICT_ALIGNMENT 4393 /* 4394 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4395 * the Rx buffer has the layer-2 header unaligned. 4396 * If our CPU requires alignment, re-align by copying. 4397 */ 4398 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4399 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4400 cur_rx->bge_len); 4401 m->m_data += ETHER_ALIGN; 4402 } 4403 #endif 4404 4405 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4406 m_set_rcvif(m, ifp); 4407 4408 bge_rxcsum(sc, cur_rx, m); 4409 4410 /* 4411 * If we received a packet with a vlan tag, pass it 4412 * to vlan_input() instead of ether_input(). 4413 */ 4414 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4415 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4416 } 4417 4418 if_percpuq_enqueue(ifp->if_percpuq, m); 4419 } 4420 4421 sc->bge_rx_saved_considx = rx_cons; 4422 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4423 if (stdcnt) 4424 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4425 if (jumbocnt) 4426 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4427 } 4428 4429 static void 4430 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4431 { 4432 4433 if (BGE_IS_57765_PLUS(sc)) { 4434 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4435 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4436 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4437 if ((cur_rx->bge_error_flag & 4438 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4439 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4440 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4441 m->m_pkthdr.csum_data = 4442 cur_rx->bge_tcp_udp_csum; 4443 m->m_pkthdr.csum_flags |= 4444 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4445 M_CSUM_DATA); 4446 } 4447 } 4448 } else { 4449 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4450 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4451 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4452 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4453 /* 4454 * Rx transport checksum-offload may also 4455 * have bugs with packets which, when transmitted, 4456 * were `runts' requiring padding. 4457 */ 4458 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4459 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4460 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4461 m->m_pkthdr.csum_data = 4462 cur_rx->bge_tcp_udp_csum; 4463 m->m_pkthdr.csum_flags |= 4464 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4465 M_CSUM_DATA); 4466 } 4467 } 4468 } 4469 4470 static void 4471 bge_txeof(struct bge_softc *sc) 4472 { 4473 struct bge_tx_bd *cur_tx = NULL; 4474 struct ifnet *ifp; 4475 struct txdmamap_pool_entry *dma; 4476 bus_addr_t offset, toff; 4477 bus_size_t tlen; 4478 int tosync; 4479 struct mbuf *m; 4480 4481 ifp = &sc->ethercom.ec_if; 4482 4483 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4484 offsetof(struct bge_ring_data, bge_status_block), 4485 sizeof (struct bge_status_block), 4486 BUS_DMASYNC_POSTREAD); 4487 4488 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4489 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4490 sc->bge_tx_saved_considx; 4491 4492 if (tosync != 0) 4493 rnd_add_uint32(&sc->rnd_source, tosync); 4494 4495 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4496 4497 if (tosync < 0) { 4498 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4499 sizeof (struct bge_tx_bd); 4500 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4501 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4502 tosync = -tosync; 4503 } 4504 4505 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4506 offset, tosync * sizeof (struct bge_tx_bd), 4507 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4508 4509 /* 4510 * Go through our tx ring and free mbufs for those 4511 * frames that have been sent. 4512 */ 4513 while (sc->bge_tx_saved_considx != 4514 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4515 uint32_t idx = 0; 4516 4517 idx = sc->bge_tx_saved_considx; 4518 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4519 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4520 ifp->if_opackets++; 4521 m = sc->bge_cdata.bge_tx_chain[idx]; 4522 if (m != NULL) { 4523 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4524 dma = sc->txdma[idx]; 4525 if (dma->is_dma32) { 4526 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4527 0, dma->dmamap32->dm_mapsize, 4528 BUS_DMASYNC_POSTWRITE); 4529 bus_dmamap_unload( 4530 sc->bge_dmatag32, dma->dmamap32); 4531 } else { 4532 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4533 0, dma->dmamap->dm_mapsize, 4534 BUS_DMASYNC_POSTWRITE); 4535 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4536 } 4537 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4538 sc->txdma[idx] = NULL; 4539 4540 m_freem(m); 4541 } 4542 sc->bge_txcnt--; 4543 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4544 ifp->if_timer = 0; 4545 } 4546 4547 if (cur_tx != NULL) 4548 ifp->if_flags &= ~IFF_OACTIVE; 4549 } 4550 4551 static int 4552 bge_intr(void *xsc) 4553 { 4554 struct bge_softc *sc; 4555 struct ifnet *ifp; 4556 uint32_t pcistate, statusword, statustag; 4557 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4558 4559 sc = xsc; 4560 ifp = &sc->ethercom.ec_if; 4561 4562 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4563 if (BGE_IS_5717_PLUS(sc)) 4564 intrmask = 0; 4565 4566 /* It is possible for the interrupt to arrive before 4567 * the status block is updated prior to the interrupt. 4568 * Reading the PCI State register will confirm whether the 4569 * interrupt is ours and will flush the status block. 4570 */ 4571 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4572 4573 /* read status word from status block */ 4574 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4575 offsetof(struct bge_ring_data, bge_status_block), 4576 sizeof (struct bge_status_block), 4577 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4578 statusword = sc->bge_rdata->bge_status_block.bge_status; 4579 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4580 4581 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4582 if (sc->bge_lasttag == statustag && 4583 (~pcistate & intrmask)) { 4584 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4585 return (0); 4586 } 4587 sc->bge_lasttag = statustag; 4588 } else { 4589 if (!(statusword & BGE_STATFLAG_UPDATED) && 4590 !(~pcistate & intrmask)) { 4591 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4592 return (0); 4593 } 4594 statustag = 0; 4595 } 4596 /* Ack interrupt and stop others from occurring. */ 4597 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4598 BGE_EVCNT_INCR(sc->bge_ev_intr); 4599 4600 /* clear status word */ 4601 sc->bge_rdata->bge_status_block.bge_status = 0; 4602 4603 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4604 offsetof(struct bge_ring_data, bge_status_block), 4605 sizeof (struct bge_status_block), 4606 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4607 4608 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4609 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4610 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4611 bge_link_upd(sc); 4612 4613 if (ifp->if_flags & IFF_RUNNING) { 4614 /* Check RX return ring producer/consumer */ 4615 bge_rxeof(sc); 4616 4617 /* Check TX ring producer/consumer */ 4618 bge_txeof(sc); 4619 } 4620 4621 if (sc->bge_pending_rxintr_change) { 4622 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4623 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4624 4625 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4626 DELAY(10); 4627 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4628 4629 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4630 DELAY(10); 4631 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4632 4633 sc->bge_pending_rxintr_change = 0; 4634 } 4635 bge_handle_events(sc); 4636 4637 /* Re-enable interrupts. */ 4638 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4639 4640 if (ifp->if_flags & IFF_RUNNING) 4641 if_schedule_deferred_start(ifp); 4642 4643 return 1; 4644 } 4645 4646 static void 4647 bge_asf_driver_up(struct bge_softc *sc) 4648 { 4649 if (sc->bge_asf_mode & ASF_STACKUP) { 4650 /* Send ASF heartbeat aprox. every 2s */ 4651 if (sc->bge_asf_count) 4652 sc->bge_asf_count --; 4653 else { 4654 sc->bge_asf_count = 2; 4655 4656 bge_wait_for_event_ack(sc); 4657 4658 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4659 BGE_FW_CMD_DRV_ALIVE3); 4660 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4661 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4662 BGE_FW_HB_TIMEOUT_SEC); 4663 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4664 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4665 BGE_RX_CPU_DRV_EVENT); 4666 } 4667 } 4668 } 4669 4670 static void 4671 bge_tick(void *xsc) 4672 { 4673 struct bge_softc *sc = xsc; 4674 struct mii_data *mii = &sc->bge_mii; 4675 int s; 4676 4677 s = splnet(); 4678 4679 if (BGE_IS_5705_PLUS(sc)) 4680 bge_stats_update_regs(sc); 4681 else 4682 bge_stats_update(sc); 4683 4684 if (sc->bge_flags & BGEF_FIBER_TBI) { 4685 /* 4686 * Since in TBI mode auto-polling can't be used we should poll 4687 * link status manually. Here we register pending link event 4688 * and trigger interrupt. 4689 */ 4690 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4691 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4692 } else { 4693 /* 4694 * Do not touch PHY if we have link up. This could break 4695 * IPMI/ASF mode or produce extra input errors. 4696 * (extra input errors was reported for bcm5701 & bcm5704). 4697 */ 4698 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4699 mii_tick(mii); 4700 } 4701 4702 bge_asf_driver_up(sc); 4703 4704 if (!sc->bge_detaching) 4705 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4706 4707 splx(s); 4708 } 4709 4710 static void 4711 bge_stats_update_regs(struct bge_softc *sc) 4712 { 4713 struct ifnet *ifp = &sc->ethercom.ec_if; 4714 4715 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4716 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4717 4718 /* 4719 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4720 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4721 * (silicon bug). There's no reliable workaround so just 4722 * ignore the counter 4723 */ 4724 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4725 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5719_A0 && 4726 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5720_A0) { 4727 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4728 } 4729 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4730 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4731 } 4732 4733 static void 4734 bge_stats_update(struct bge_softc *sc) 4735 { 4736 struct ifnet *ifp = &sc->ethercom.ec_if; 4737 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4738 4739 #define READ_STAT(sc, stats, stat) \ 4740 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4741 4742 ifp->if_collisions += 4743 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4744 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4745 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4746 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4747 ifp->if_collisions; 4748 4749 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4750 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4751 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4752 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4753 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4754 READ_STAT(sc, stats, 4755 xoffPauseFramesReceived.bge_addr_lo)); 4756 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4757 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4758 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4759 READ_STAT(sc, stats, 4760 macControlFramesReceived.bge_addr_lo)); 4761 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4762 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4763 4764 #undef READ_STAT 4765 4766 #ifdef notdef 4767 ifp->if_collisions += 4768 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4769 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4770 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4771 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4772 ifp->if_collisions; 4773 #endif 4774 } 4775 4776 /* 4777 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4778 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4779 * but when such padded frames employ the bge IP/TCP checksum offload, 4780 * the hardware checksum assist gives incorrect results (possibly 4781 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4782 * If we pad such runts with zeros, the onboard checksum comes out correct. 4783 */ 4784 static inline int 4785 bge_cksum_pad(struct mbuf *pkt) 4786 { 4787 struct mbuf *last = NULL; 4788 int padlen; 4789 4790 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4791 4792 /* if there's only the packet-header and we can pad there, use it. */ 4793 if (pkt->m_pkthdr.len == pkt->m_len && 4794 M_TRAILINGSPACE(pkt) >= padlen) { 4795 last = pkt; 4796 } else { 4797 /* 4798 * Walk packet chain to find last mbuf. We will either 4799 * pad there, or append a new mbuf and pad it 4800 * (thus perhaps avoiding the bcm5700 dma-min bug). 4801 */ 4802 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4803 continue; /* do nothing */ 4804 } 4805 4806 /* `last' now points to last in chain. */ 4807 if (M_TRAILINGSPACE(last) < padlen) { 4808 /* Allocate new empty mbuf, pad it. Compact later. */ 4809 struct mbuf *n; 4810 MGET(n, M_DONTWAIT, MT_DATA); 4811 if (n == NULL) 4812 return ENOBUFS; 4813 n->m_len = 0; 4814 last->m_next = n; 4815 last = n; 4816 } 4817 } 4818 4819 KDASSERT(!M_READONLY(last)); 4820 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4821 4822 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4823 memset(mtod(last, char *) + last->m_len, 0, padlen); 4824 last->m_len += padlen; 4825 pkt->m_pkthdr.len += padlen; 4826 return 0; 4827 } 4828 4829 /* 4830 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4831 */ 4832 static inline int 4833 bge_compact_dma_runt(struct mbuf *pkt) 4834 { 4835 struct mbuf *m, *prev; 4836 int totlen; 4837 4838 prev = NULL; 4839 totlen = 0; 4840 4841 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4842 int mlen = m->m_len; 4843 int shortfall = 8 - mlen ; 4844 4845 totlen += mlen; 4846 if (mlen == 0) 4847 continue; 4848 if (mlen >= 8) 4849 continue; 4850 4851 /* If we get here, mbuf data is too small for DMA engine. 4852 * Try to fix by shuffling data to prev or next in chain. 4853 * If that fails, do a compacting deep-copy of the whole chain. 4854 */ 4855 4856 /* Internal frag. If fits in prev, copy it there. */ 4857 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4858 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4859 prev->m_len += mlen; 4860 m->m_len = 0; 4861 /* XXX stitch chain */ 4862 prev->m_next = m_free(m); 4863 m = prev; 4864 continue; 4865 } 4866 else if (m->m_next != NULL && 4867 M_TRAILINGSPACE(m) >= shortfall && 4868 m->m_next->m_len >= (8 + shortfall)) { 4869 /* m is writable and have enough data in next, pull up. */ 4870 4871 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4872 shortfall); 4873 m->m_len += shortfall; 4874 m->m_next->m_len -= shortfall; 4875 m->m_next->m_data += shortfall; 4876 } 4877 else if (m->m_next == NULL || 1) { 4878 /* Got a runt at the very end of the packet. 4879 * borrow data from the tail of the preceding mbuf and 4880 * update its length in-place. (The original data is still 4881 * valid, so we can do this even if prev is not writable.) 4882 */ 4883 4884 /* if we'd make prev a runt, just move all of its data. */ 4885 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4886 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4887 4888 if ((prev->m_len - shortfall) < 8) 4889 shortfall = prev->m_len; 4890 4891 #ifdef notyet /* just do the safe slow thing for now */ 4892 if (!M_READONLY(m)) { 4893 if (M_LEADINGSPACE(m) < shorfall) { 4894 void *m_dat; 4895 m_dat = (m->m_flags & M_PKTHDR) ? 4896 m->m_pktdat : m->dat; 4897 memmove(m_dat, mtod(m, void*), m->m_len); 4898 m->m_data = m_dat; 4899 } 4900 } else 4901 #endif /* just do the safe slow thing */ 4902 { 4903 struct mbuf * n = NULL; 4904 int newprevlen = prev->m_len - shortfall; 4905 4906 MGET(n, M_NOWAIT, MT_DATA); 4907 if (n == NULL) 4908 return ENOBUFS; 4909 KASSERT(m->m_len + shortfall < MLEN 4910 /*, 4911 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4912 4913 /* first copy the data we're stealing from prev */ 4914 memcpy(n->m_data, prev->m_data + newprevlen, 4915 shortfall); 4916 4917 /* update prev->m_len accordingly */ 4918 prev->m_len -= shortfall; 4919 4920 /* copy data from runt m */ 4921 memcpy(n->m_data + shortfall, m->m_data, 4922 m->m_len); 4923 4924 /* n holds what we stole from prev, plus m */ 4925 n->m_len = shortfall + m->m_len; 4926 4927 /* stitch n into chain and free m */ 4928 n->m_next = m->m_next; 4929 prev->m_next = n; 4930 /* KASSERT(m->m_next == NULL); */ 4931 m->m_next = NULL; 4932 m_free(m); 4933 m = n; /* for continuing loop */ 4934 } 4935 } 4936 } 4937 return 0; 4938 } 4939 4940 /* 4941 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4942 * pointers to descriptors. 4943 */ 4944 static int 4945 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4946 { 4947 struct ifnet *ifp = &sc->ethercom.ec_if; 4948 struct bge_tx_bd *f, *prev_f; 4949 uint32_t frag, cur; 4950 uint16_t csum_flags = 0; 4951 uint16_t txbd_tso_flags = 0; 4952 struct txdmamap_pool_entry *dma; 4953 bus_dmamap_t dmamap; 4954 bus_dma_tag_t dmatag; 4955 int i = 0; 4956 int use_tso, maxsegsize, error; 4957 bool have_vtag; 4958 uint16_t vtag; 4959 bool remap; 4960 4961 if (m_head->m_pkthdr.csum_flags) { 4962 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4963 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4964 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4965 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4966 } 4967 4968 /* 4969 * If we were asked to do an outboard checksum, and the NIC 4970 * has the bug where it sometimes adds in the Ethernet padding, 4971 * explicitly pad with zeros so the cksum will be correct either way. 4972 * (For now, do this for all chip versions, until newer 4973 * are confirmed to not require the workaround.) 4974 */ 4975 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4976 #ifdef notyet 4977 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4978 #endif 4979 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4980 goto check_dma_bug; 4981 4982 if (bge_cksum_pad(m_head) != 0) 4983 return ENOBUFS; 4984 4985 check_dma_bug: 4986 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4987 goto doit; 4988 4989 /* 4990 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4991 * less than eight bytes. If we encounter a teeny mbuf 4992 * at the end of a chain, we can pad. Otherwise, copy. 4993 */ 4994 if (bge_compact_dma_runt(m_head) != 0) 4995 return ENOBUFS; 4996 4997 doit: 4998 dma = SLIST_FIRST(&sc->txdma_list); 4999 if (dma == NULL) { 5000 ifp->if_flags |= IFF_OACTIVE; 5001 return ENOBUFS; 5002 } 5003 dmamap = dma->dmamap; 5004 dmatag = sc->bge_dmatag; 5005 dma->is_dma32 = false; 5006 5007 /* 5008 * Set up any necessary TSO state before we start packing... 5009 */ 5010 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5011 if (!use_tso) { 5012 maxsegsize = 0; 5013 } else { /* TSO setup */ 5014 unsigned mss; 5015 struct ether_header *eh; 5016 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5017 unsigned bge_hlen; 5018 struct mbuf * m0 = m_head; 5019 struct ip *ip; 5020 struct tcphdr *th; 5021 int iphl, hlen; 5022 5023 /* 5024 * XXX It would be nice if the mbuf pkthdr had offset 5025 * fields for the protocol headers. 5026 */ 5027 5028 eh = mtod(m0, struct ether_header *); 5029 switch (htons(eh->ether_type)) { 5030 case ETHERTYPE_IP: 5031 offset = ETHER_HDR_LEN; 5032 break; 5033 5034 case ETHERTYPE_VLAN: 5035 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5036 break; 5037 5038 default: 5039 /* 5040 * Don't support this protocol or encapsulation. 5041 */ 5042 return ENOBUFS; 5043 } 5044 5045 /* 5046 * TCP/IP headers are in the first mbuf; we can do 5047 * this the easy way. 5048 */ 5049 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5050 hlen = iphl + offset; 5051 if (__predict_false(m0->m_len < 5052 (hlen + sizeof(struct tcphdr)))) { 5053 5054 aprint_error_dev(sc->bge_dev, 5055 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5056 "not handled yet\n", 5057 m0->m_len, hlen+ sizeof(struct tcphdr)); 5058 #ifdef NOTYET 5059 /* 5060 * XXX jonathan (at) NetBSD.org: untested. 5061 * how to force this branch to be taken? 5062 */ 5063 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5064 5065 m_copydata(m0, offset, sizeof(ip), &ip); 5066 m_copydata(m0, hlen, sizeof(th), &th); 5067 5068 ip.ip_len = 0; 5069 5070 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5071 sizeof(ip.ip_len), &ip.ip_len); 5072 5073 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5074 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5075 5076 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5077 sizeof(th.th_sum), &th.th_sum); 5078 5079 hlen += th.th_off << 2; 5080 iptcp_opt_words = hlen; 5081 #else 5082 /* 5083 * if_wm "hard" case not yet supported, can we not 5084 * mandate it out of existence? 5085 */ 5086 (void) ip; (void)th; (void) ip_tcp_hlen; 5087 5088 return ENOBUFS; 5089 #endif 5090 } else { 5091 ip = (struct ip *) (mtod(m0, char *) + offset); 5092 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5093 ip_tcp_hlen = iphl + (th->th_off << 2); 5094 5095 /* Total IP/TCP options, in 32-bit words */ 5096 iptcp_opt_words = (ip_tcp_hlen 5097 - sizeof(struct tcphdr) 5098 - sizeof(struct ip)) >> 2; 5099 } 5100 if (BGE_IS_575X_PLUS(sc)) { 5101 th->th_sum = 0; 5102 csum_flags = 0; 5103 } else { 5104 /* 5105 * XXX jonathan (at) NetBSD.org: 5705 untested. 5106 * Requires TSO firmware patch for 5701/5703/5704. 5107 */ 5108 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5109 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5110 } 5111 5112 mss = m_head->m_pkthdr.segsz; 5113 txbd_tso_flags |= 5114 BGE_TXBDFLAG_CPU_PRE_DMA | 5115 BGE_TXBDFLAG_CPU_POST_DMA; 5116 5117 /* 5118 * Our NIC TSO-assist assumes TSO has standard, optionless 5119 * IPv4 and TCP headers, which total 40 bytes. By default, 5120 * the NIC copies 40 bytes of IP/TCP header from the 5121 * supplied header into the IP/TCP header portion of 5122 * each post-TSO-segment. If the supplied packet has IP or 5123 * TCP options, we need to tell the NIC to copy those extra 5124 * bytes into each post-TSO header, in addition to the normal 5125 * 40-byte IP/TCP header (and to leave space accordingly). 5126 * Unfortunately, the driver encoding of option length 5127 * varies across different ASIC families. 5128 */ 5129 tcp_seg_flags = 0; 5130 bge_hlen = ip_tcp_hlen >> 2; 5131 if (BGE_IS_5717_PLUS(sc)) { 5132 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5133 txbd_tso_flags |= 5134 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5135 } else if (BGE_IS_5705_PLUS(sc)) { 5136 tcp_seg_flags = 5137 bge_hlen << 11; 5138 } else { 5139 /* XXX iptcp_opt_words or bge_hlen ? */ 5140 txbd_tso_flags |= 5141 iptcp_opt_words << 12; 5142 } 5143 maxsegsize = mss | tcp_seg_flags; 5144 ip->ip_len = htons(mss + ip_tcp_hlen); 5145 ip->ip_sum = 0; 5146 5147 } /* TSO setup */ 5148 5149 have_vtag = vlan_has_tag(m_head); 5150 if (have_vtag) 5151 vtag = vlan_get_tag(m_head); 5152 5153 /* 5154 * Start packing the mbufs in this chain into 5155 * the fragment pointers. Stop when we run out 5156 * of fragments or hit the end of the mbuf chain. 5157 */ 5158 remap = true; 5159 load_again: 5160 error = bus_dmamap_load_mbuf(dmatag, dmamap, 5161 m_head, BUS_DMA_NOWAIT); 5162 if (__predict_false(error)) { 5163 if (error == EFBIG && remap) { 5164 struct mbuf *m; 5165 remap = false; 5166 m = m_defrag(m_head, M_NOWAIT); 5167 if (m != NULL) { 5168 KASSERT(m == m_head); 5169 goto load_again; 5170 } 5171 } 5172 return error; 5173 } 5174 /* 5175 * Sanity check: avoid coming within 16 descriptors 5176 * of the end of the ring. 5177 */ 5178 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5179 BGE_TSO_PRINTF(("%s: " 5180 " dmamap_load_mbuf too close to ring wrap\n", 5181 device_xname(sc->bge_dev))); 5182 goto fail_unload; 5183 } 5184 5185 /* Iterate over dmap-map fragments. */ 5186 f = prev_f = NULL; 5187 cur = frag = *txidx; 5188 5189 for (i = 0; i < dmamap->dm_nsegs; i++) { 5190 f = &sc->bge_rdata->bge_tx_ring[frag]; 5191 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5192 break; 5193 5194 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5195 f->bge_len = dmamap->dm_segs[i].ds_len; 5196 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5197 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5198 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5199 (prev_f != NULL && 5200 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5201 ) { 5202 /* 5203 * watchdog timeout issue was observed with TSO, 5204 * limiting DMA address space to 32bits seems to 5205 * address the issue. 5206 */ 5207 bus_dmamap_unload(dmatag, dmamap); 5208 dmatag = sc->bge_dmatag32; 5209 dmamap = dma->dmamap32; 5210 dma->is_dma32 = true; 5211 remap = true; 5212 goto load_again; 5213 } 5214 5215 /* 5216 * For 5751 and follow-ons, for TSO we must turn 5217 * off checksum-assist flag in the tx-descr, and 5218 * supply the ASIC-revision-specific encoding 5219 * of TSO flags and segsize. 5220 */ 5221 if (use_tso) { 5222 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5223 f->bge_rsvd = maxsegsize; 5224 f->bge_flags = csum_flags | txbd_tso_flags; 5225 } else { 5226 f->bge_rsvd = 0; 5227 f->bge_flags = 5228 (csum_flags | txbd_tso_flags) & 0x0fff; 5229 } 5230 } else { 5231 f->bge_rsvd = 0; 5232 f->bge_flags = csum_flags; 5233 } 5234 5235 if (have_vtag) { 5236 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5237 f->bge_vlan_tag = vtag; 5238 } else { 5239 f->bge_vlan_tag = 0; 5240 } 5241 prev_f = f; 5242 cur = frag; 5243 BGE_INC(frag, BGE_TX_RING_CNT); 5244 } 5245 5246 if (i < dmamap->dm_nsegs) { 5247 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5248 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5249 goto fail_unload; 5250 } 5251 5252 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5253 BUS_DMASYNC_PREWRITE); 5254 5255 if (frag == sc->bge_tx_saved_considx) { 5256 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5257 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5258 5259 goto fail_unload; 5260 } 5261 5262 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5263 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5264 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5265 sc->txdma[cur] = dma; 5266 sc->bge_txcnt += dmamap->dm_nsegs; 5267 5268 *txidx = frag; 5269 5270 return 0; 5271 5272 fail_unload: 5273 bus_dmamap_unload(dmatag, dmamap); 5274 ifp->if_flags |= IFF_OACTIVE; 5275 5276 return ENOBUFS; 5277 } 5278 5279 /* 5280 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5281 * to the mbuf data regions directly in the transmit descriptors. 5282 */ 5283 static void 5284 bge_start(struct ifnet *ifp) 5285 { 5286 struct bge_softc *sc; 5287 struct mbuf *m_head = NULL; 5288 struct mbuf *m; 5289 uint32_t prodidx; 5290 int pkts = 0; 5291 int error; 5292 5293 sc = ifp->if_softc; 5294 5295 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5296 return; 5297 5298 prodidx = sc->bge_tx_prodidx; 5299 5300 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5301 IFQ_POLL(&ifp->if_snd, m_head); 5302 if (m_head == NULL) 5303 break; 5304 5305 #if 0 5306 /* 5307 * XXX 5308 * safety overkill. If this is a fragmented packet chain 5309 * with delayed TCP/UDP checksums, then only encapsulate 5310 * it if we have enough descriptors to handle the entire 5311 * chain at once. 5312 * (paranoia -- may not actually be needed) 5313 */ 5314 if (m_head->m_flags & M_FIRSTFRAG && 5315 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5316 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5317 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5318 ifp->if_flags |= IFF_OACTIVE; 5319 break; 5320 } 5321 } 5322 #endif 5323 5324 /* 5325 * Pack the data into the transmit ring. If we 5326 * don't have room, set the OACTIVE flag and wait 5327 * for the NIC to drain the ring. 5328 */ 5329 error = bge_encap(sc, m_head, &prodidx); 5330 if (__predict_false(error)) { 5331 if (ifp->if_flags & IFF_OACTIVE) { 5332 /* just wait for the transmit ring to drain */ 5333 break; 5334 } 5335 IFQ_DEQUEUE(&ifp->if_snd, m); 5336 KASSERT(m == m_head); 5337 m_freem(m_head); 5338 continue; 5339 } 5340 5341 /* now we are committed to transmit the packet */ 5342 IFQ_DEQUEUE(&ifp->if_snd, m); 5343 KASSERT(m == m_head); 5344 pkts++; 5345 5346 /* 5347 * If there's a BPF listener, bounce a copy of this frame 5348 * to him. 5349 */ 5350 bpf_mtap(ifp, m_head, BPF_D_OUT); 5351 } 5352 if (pkts == 0) 5353 return; 5354 5355 /* Transmit */ 5356 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5357 /* 5700 b2 errata */ 5358 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5359 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5360 5361 sc->bge_tx_prodidx = prodidx; 5362 5363 /* 5364 * Set a timeout in case the chip goes out to lunch. 5365 */ 5366 ifp->if_timer = 5; 5367 } 5368 5369 static int 5370 bge_init(struct ifnet *ifp) 5371 { 5372 struct bge_softc *sc = ifp->if_softc; 5373 const uint16_t *m; 5374 uint32_t mode, reg; 5375 int s, error = 0; 5376 5377 s = splnet(); 5378 5379 ifp = &sc->ethercom.ec_if; 5380 5381 /* Cancel pending I/O and flush buffers. */ 5382 bge_stop(ifp, 0); 5383 5384 bge_stop_fw(sc); 5385 bge_sig_pre_reset(sc, BGE_RESET_START); 5386 bge_reset(sc); 5387 bge_sig_legacy(sc, BGE_RESET_START); 5388 5389 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5390 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5391 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5392 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5393 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5394 5395 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5396 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5397 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5398 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5399 5400 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5401 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5402 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5403 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5404 5405 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5406 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5407 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5408 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5409 } 5410 5411 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5412 pcireg_t aercap; 5413 5414 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5415 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5416 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5417 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5418 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5419 5420 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5421 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5422 | BGE_PCIE_EIDLE_DELAY_13CLK; 5423 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5424 5425 /* Clear correctable error */ 5426 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5427 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5428 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5429 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5430 5431 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5432 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5433 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5434 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5435 } 5436 5437 bge_sig_post_reset(sc, BGE_RESET_START); 5438 5439 bge_chipinit(sc); 5440 5441 /* 5442 * Init the various state machines, ring 5443 * control blocks and firmware. 5444 */ 5445 error = bge_blockinit(sc); 5446 if (error != 0) { 5447 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5448 error); 5449 splx(s); 5450 return error; 5451 } 5452 5453 ifp = &sc->ethercom.ec_if; 5454 5455 /* 5718 step 25, 57XX step 54 */ 5456 /* Specify MTU. */ 5457 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5458 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5459 5460 /* 5718 step 23 */ 5461 /* Load our MAC address. */ 5462 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5463 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5464 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5465 5466 /* Enable or disable promiscuous mode as needed. */ 5467 if (ifp->if_flags & IFF_PROMISC) 5468 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5469 else 5470 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5471 5472 /* Program multicast filter. */ 5473 bge_setmulti(sc); 5474 5475 /* Init RX ring. */ 5476 bge_init_rx_ring_std(sc); 5477 5478 /* 5479 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5480 * memory to insure that the chip has in fact read the first 5481 * entry of the ring. 5482 */ 5483 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5484 uint32_t v, i; 5485 for (i = 0; i < 10; i++) { 5486 DELAY(20); 5487 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5488 if (v == (MCLBYTES - ETHER_ALIGN)) 5489 break; 5490 } 5491 if (i == 10) 5492 aprint_error_dev(sc->bge_dev, 5493 "5705 A0 chip failed to load RX ring\n"); 5494 } 5495 5496 /* Init jumbo RX ring. */ 5497 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5498 bge_init_rx_ring_jumbo(sc); 5499 5500 /* Init our RX return ring index */ 5501 sc->bge_rx_saved_considx = 0; 5502 5503 /* Init TX ring. */ 5504 bge_init_tx_ring(sc); 5505 5506 /* 5718 step 63, 57XX step 94 */ 5507 /* Enable TX MAC state machine lockup fix. */ 5508 mode = CSR_READ_4(sc, BGE_TX_MODE); 5509 if (BGE_IS_5755_PLUS(sc) || 5510 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5511 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5512 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5513 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5514 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5515 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5516 } 5517 5518 /* Turn on transmitter */ 5519 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5520 /* 5718 step 64 */ 5521 DELAY(100); 5522 5523 /* 5718 step 65, 57XX step 95 */ 5524 /* Turn on receiver */ 5525 mode = CSR_READ_4(sc, BGE_RX_MODE); 5526 if (BGE_IS_5755_PLUS(sc)) 5527 mode |= BGE_RXMODE_IPV6_ENABLE; 5528 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5529 /* 5718 step 66 */ 5530 DELAY(10); 5531 5532 /* 5718 step 12, 57XX step 37 */ 5533 /* 5534 * XXX Doucments of 5718 series and 577xx say the recommended value 5535 * is 1, but tg3 set 1 only on 57765 series. 5536 */ 5537 if (BGE_IS_57765_PLUS(sc)) 5538 reg = 1; 5539 else 5540 reg = 2; 5541 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5542 5543 /* Tell firmware we're alive. */ 5544 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5545 5546 /* Enable host interrupts. */ 5547 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5548 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5549 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5550 5551 if ((error = bge_ifmedia_upd(ifp)) != 0) 5552 goto out; 5553 5554 ifp->if_flags |= IFF_RUNNING; 5555 ifp->if_flags &= ~IFF_OACTIVE; 5556 5557 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5558 5559 out: 5560 sc->bge_if_flags = ifp->if_flags; 5561 splx(s); 5562 5563 return error; 5564 } 5565 5566 /* 5567 * Set media options. 5568 */ 5569 static int 5570 bge_ifmedia_upd(struct ifnet *ifp) 5571 { 5572 struct bge_softc *sc = ifp->if_softc; 5573 struct mii_data *mii = &sc->bge_mii; 5574 struct ifmedia *ifm = &sc->bge_ifmedia; 5575 int rc; 5576 5577 /* If this is a 1000baseX NIC, enable the TBI port. */ 5578 if (sc->bge_flags & BGEF_FIBER_TBI) { 5579 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5580 return EINVAL; 5581 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5582 case IFM_AUTO: 5583 /* 5584 * The BCM5704 ASIC appears to have a special 5585 * mechanism for programming the autoneg 5586 * advertisement registers in TBI mode. 5587 */ 5588 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5589 uint32_t sgdig; 5590 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5591 if (sgdig & BGE_SGDIGSTS_DONE) { 5592 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5593 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5594 sgdig |= BGE_SGDIGCFG_AUTO | 5595 BGE_SGDIGCFG_PAUSE_CAP | 5596 BGE_SGDIGCFG_ASYM_PAUSE; 5597 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5598 sgdig | BGE_SGDIGCFG_SEND); 5599 DELAY(5); 5600 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5601 sgdig); 5602 } 5603 } 5604 break; 5605 case IFM_1000_SX: 5606 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5607 BGE_CLRBIT(sc, BGE_MAC_MODE, 5608 BGE_MACMODE_HALF_DUPLEX); 5609 } else { 5610 BGE_SETBIT(sc, BGE_MAC_MODE, 5611 BGE_MACMODE_HALF_DUPLEX); 5612 } 5613 DELAY(40); 5614 break; 5615 default: 5616 return EINVAL; 5617 } 5618 /* XXX 802.3x flow control for 1000BASE-SX */ 5619 return 0; 5620 } 5621 5622 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5623 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5624 uint32_t reg; 5625 5626 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5627 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5628 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5629 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5630 } 5631 } 5632 5633 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5634 if ((rc = mii_mediachg(mii)) == ENXIO) 5635 return 0; 5636 5637 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5638 uint32_t reg; 5639 5640 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5641 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5642 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5643 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5644 delay(40); 5645 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5646 } 5647 } 5648 5649 /* 5650 * Force an interrupt so that we will call bge_link_upd 5651 * if needed and clear any pending link state attention. 5652 * Without this we are not getting any further interrupts 5653 * for link state changes and thus will not UP the link and 5654 * not be able to send in bge_start. The only way to get 5655 * things working was to receive a packet and get a RX intr. 5656 */ 5657 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5658 sc->bge_flags & BGEF_IS_5788) 5659 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5660 else 5661 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5662 5663 return rc; 5664 } 5665 5666 /* 5667 * Report current media status. 5668 */ 5669 static void 5670 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5671 { 5672 struct bge_softc *sc = ifp->if_softc; 5673 struct mii_data *mii = &sc->bge_mii; 5674 5675 if (sc->bge_flags & BGEF_FIBER_TBI) { 5676 ifmr->ifm_status = IFM_AVALID; 5677 ifmr->ifm_active = IFM_ETHER; 5678 if (CSR_READ_4(sc, BGE_MAC_STS) & 5679 BGE_MACSTAT_TBI_PCS_SYNCHED) 5680 ifmr->ifm_status |= IFM_ACTIVE; 5681 ifmr->ifm_active |= IFM_1000_SX; 5682 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5683 ifmr->ifm_active |= IFM_HDX; 5684 else 5685 ifmr->ifm_active |= IFM_FDX; 5686 return; 5687 } 5688 5689 mii_pollstat(mii); 5690 ifmr->ifm_status = mii->mii_media_status; 5691 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5692 sc->bge_flowflags; 5693 } 5694 5695 static int 5696 bge_ifflags_cb(struct ethercom *ec) 5697 { 5698 struct ifnet *ifp = &ec->ec_if; 5699 struct bge_softc *sc = ifp->if_softc; 5700 int change = ifp->if_flags ^ sc->bge_if_flags; 5701 5702 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5703 return ENETRESET; 5704 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5705 return 0; 5706 5707 if ((ifp->if_flags & IFF_PROMISC) == 0) 5708 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5709 else 5710 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5711 5712 bge_setmulti(sc); 5713 5714 sc->bge_if_flags = ifp->if_flags; 5715 return 0; 5716 } 5717 5718 static int 5719 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5720 { 5721 struct bge_softc *sc = ifp->if_softc; 5722 struct ifreq *ifr = (struct ifreq *) data; 5723 int s, error = 0; 5724 struct mii_data *mii; 5725 5726 s = splnet(); 5727 5728 switch (command) { 5729 case SIOCSIFMEDIA: 5730 /* XXX Flow control is not supported for 1000BASE-SX */ 5731 if (sc->bge_flags & BGEF_FIBER_TBI) { 5732 ifr->ifr_media &= ~IFM_ETH_FMASK; 5733 sc->bge_flowflags = 0; 5734 } 5735 5736 /* Flow control requires full-duplex mode. */ 5737 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5738 (ifr->ifr_media & IFM_FDX) == 0) { 5739 ifr->ifr_media &= ~IFM_ETH_FMASK; 5740 } 5741 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5742 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5743 /* We can do both TXPAUSE and RXPAUSE. */ 5744 ifr->ifr_media |= 5745 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5746 } 5747 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5748 } 5749 /* FALLTHROUGH */ 5750 case SIOCGIFMEDIA: 5751 if (sc->bge_flags & BGEF_FIBER_TBI) { 5752 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5753 command); 5754 } else { 5755 mii = &sc->bge_mii; 5756 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5757 command); 5758 } 5759 break; 5760 default: 5761 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5762 break; 5763 5764 error = 0; 5765 5766 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5767 ; 5768 else if (ifp->if_flags & IFF_RUNNING) 5769 bge_setmulti(sc); 5770 break; 5771 } 5772 5773 splx(s); 5774 5775 return error; 5776 } 5777 5778 static void 5779 bge_watchdog(struct ifnet *ifp) 5780 { 5781 struct bge_softc *sc; 5782 uint32_t status; 5783 5784 sc = ifp->if_softc; 5785 5786 /* If pause frames are active then don't reset the hardware. */ 5787 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5788 status = CSR_READ_4(sc, BGE_RX_STS); 5789 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5790 /* 5791 * If link partner has us in XOFF state then wait for 5792 * the condition to clear. 5793 */ 5794 CSR_WRITE_4(sc, BGE_RX_STS, status); 5795 ifp->if_timer = 5; 5796 return; 5797 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5798 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5799 /* 5800 * If link partner has us in XOFF state then wait for 5801 * the condition to clear. 5802 */ 5803 CSR_WRITE_4(sc, BGE_RX_STS, status); 5804 ifp->if_timer = 5; 5805 return; 5806 } 5807 /* 5808 * Any other condition is unexpected and the controller 5809 * should be reset. 5810 */ 5811 } 5812 5813 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5814 5815 ifp->if_flags &= ~IFF_RUNNING; 5816 bge_init(ifp); 5817 5818 ifp->if_oerrors++; 5819 } 5820 5821 static void 5822 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5823 { 5824 int i; 5825 5826 BGE_CLRBIT_FLUSH(sc, reg, bit); 5827 5828 for (i = 0; i < 1000; i++) { 5829 delay(100); 5830 if ((CSR_READ_4(sc, reg) & bit) == 0) 5831 return; 5832 } 5833 5834 /* 5835 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5836 * on some environment (and once after boot?) 5837 */ 5838 if (reg != BGE_SRS_MODE) 5839 aprint_error_dev(sc->bge_dev, 5840 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5841 (u_long)reg, bit); 5842 } 5843 5844 /* 5845 * Stop the adapter and free any mbufs allocated to the 5846 * RX and TX lists. 5847 */ 5848 static void 5849 bge_stop(struct ifnet *ifp, int disable) 5850 { 5851 struct bge_softc *sc = ifp->if_softc; 5852 5853 if (disable) { 5854 sc->bge_detaching = 1; 5855 callout_halt(&sc->bge_timeout, NULL); 5856 } else 5857 callout_stop(&sc->bge_timeout); 5858 5859 /* Disable host interrupts. */ 5860 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5861 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5862 5863 /* 5864 * Tell firmware we're shutting down. 5865 */ 5866 bge_stop_fw(sc); 5867 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5868 5869 /* 5870 * Disable all of the receiver blocks. 5871 */ 5872 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5873 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5874 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5875 if (BGE_IS_5700_FAMILY(sc)) 5876 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5877 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5878 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5879 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5880 5881 /* 5882 * Disable all of the transmit blocks. 5883 */ 5884 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5885 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5886 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5887 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5888 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5889 if (BGE_IS_5700_FAMILY(sc)) 5890 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5891 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5892 5893 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5894 delay(40); 5895 5896 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5897 5898 /* 5899 * Shut down all of the memory managers and related 5900 * state machines. 5901 */ 5902 /* 5718 step 5a,5b */ 5903 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5904 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5905 if (BGE_IS_5700_FAMILY(sc)) 5906 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5907 5908 /* 5718 step 5c,5d */ 5909 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5910 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5911 5912 if (BGE_IS_5700_FAMILY(sc)) { 5913 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5914 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5915 } 5916 5917 bge_reset(sc); 5918 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5919 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5920 5921 /* 5922 * Keep the ASF firmware running if up. 5923 */ 5924 if (sc->bge_asf_mode & ASF_STACKUP) 5925 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5926 else 5927 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5928 5929 /* Free the RX lists. */ 5930 bge_free_rx_ring_std(sc, disable); 5931 5932 /* Free jumbo RX list. */ 5933 if (BGE_IS_JUMBO_CAPABLE(sc)) 5934 bge_free_rx_ring_jumbo(sc); 5935 5936 /* Free TX buffers. */ 5937 bge_free_tx_ring(sc, disable); 5938 5939 /* 5940 * Isolate/power down the PHY. 5941 */ 5942 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 5943 mii_down(&sc->bge_mii); 5944 5945 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5946 5947 /* Clear MAC's link state (PHY may still have link UP). */ 5948 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5949 5950 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5951 } 5952 5953 static void 5954 bge_link_upd(struct bge_softc *sc) 5955 { 5956 struct ifnet *ifp = &sc->ethercom.ec_if; 5957 struct mii_data *mii = &sc->bge_mii; 5958 uint32_t status; 5959 uint16_t phyval; 5960 int link; 5961 5962 /* Clear 'pending link event' flag */ 5963 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5964 5965 /* 5966 * Process link state changes. 5967 * Grrr. The link status word in the status block does 5968 * not work correctly on the BCM5700 rev AX and BX chips, 5969 * according to all available information. Hence, we have 5970 * to enable MII interrupts in order to properly obtain 5971 * async link changes. Unfortunately, this also means that 5972 * we have to read the MAC status register to detect link 5973 * changes, thereby adding an additional register access to 5974 * the interrupt handler. 5975 */ 5976 5977 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5978 status = CSR_READ_4(sc, BGE_MAC_STS); 5979 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5980 mii_pollstat(mii); 5981 5982 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5983 mii->mii_media_status & IFM_ACTIVE && 5984 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5985 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5986 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5987 (!(mii->mii_media_status & IFM_ACTIVE) || 5988 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5989 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5990 5991 /* Clear the interrupt */ 5992 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5993 BGE_EVTENB_MI_INTERRUPT); 5994 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5995 BRGPHY_MII_ISR, &phyval); 5996 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5997 BRGPHY_MII_IMR, BRGPHY_INTRS); 5998 } 5999 return; 6000 } 6001 6002 if (sc->bge_flags & BGEF_FIBER_TBI) { 6003 status = CSR_READ_4(sc, BGE_MAC_STS); 6004 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6005 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6006 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6007 if (BGE_ASICREV(sc->bge_chipid) 6008 == BGE_ASICREV_BCM5704) { 6009 BGE_CLRBIT(sc, BGE_MAC_MODE, 6010 BGE_MACMODE_TBI_SEND_CFGS); 6011 DELAY(40); 6012 } 6013 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6014 if_link_state_change(ifp, LINK_STATE_UP); 6015 } 6016 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6017 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6018 if_link_state_change(ifp, LINK_STATE_DOWN); 6019 } 6020 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6021 /* 6022 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6023 * bit in status word always set. Workaround this bug by 6024 * reading PHY link status directly. 6025 */ 6026 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6027 BGE_STS_LINK : 0; 6028 6029 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6030 mii_pollstat(mii); 6031 6032 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6033 mii->mii_media_status & IFM_ACTIVE && 6034 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6035 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6036 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6037 (!(mii->mii_media_status & IFM_ACTIVE) || 6038 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6039 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6040 } 6041 } else { 6042 /* 6043 * For controllers that call mii_tick, we have to poll 6044 * link status. 6045 */ 6046 mii_pollstat(mii); 6047 } 6048 6049 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6050 uint32_t reg, scale; 6051 6052 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6053 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6054 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6055 scale = 65; 6056 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6057 scale = 6; 6058 else 6059 scale = 12; 6060 6061 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6062 ~BGE_MISCCFG_TIMER_PRESCALER; 6063 reg |= scale << 1; 6064 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6065 } 6066 /* Clear the attention */ 6067 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6068 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6069 BGE_MACSTAT_LINK_CHANGED); 6070 } 6071 6072 static int 6073 bge_sysctl_verify(SYSCTLFN_ARGS) 6074 { 6075 int error, t; 6076 struct sysctlnode node; 6077 6078 node = *rnode; 6079 t = *(int*)rnode->sysctl_data; 6080 node.sysctl_data = &t; 6081 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6082 if (error || newp == NULL) 6083 return error; 6084 6085 #if 0 6086 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6087 node.sysctl_num, rnode->sysctl_num)); 6088 #endif 6089 6090 if (node.sysctl_num == bge_rxthresh_nodenum) { 6091 if (t < 0 || t >= NBGE_RX_THRESH) 6092 return EINVAL; 6093 bge_update_all_threshes(t); 6094 } else 6095 return EINVAL; 6096 6097 *(int*)rnode->sysctl_data = t; 6098 6099 return 0; 6100 } 6101 6102 /* 6103 * Set up sysctl(3) MIB, hw.bge.*. 6104 */ 6105 static void 6106 bge_sysctl_init(struct bge_softc *sc) 6107 { 6108 int rc, bge_root_num; 6109 const struct sysctlnode *node; 6110 6111 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6112 0, CTLTYPE_NODE, "bge", 6113 SYSCTL_DESCR("BGE interface controls"), 6114 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6115 goto out; 6116 } 6117 6118 bge_root_num = node->sysctl_num; 6119 6120 /* BGE Rx interrupt mitigation level */ 6121 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6122 CTLFLAG_READWRITE, 6123 CTLTYPE_INT, "rx_lvl", 6124 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6125 bge_sysctl_verify, 0, 6126 &bge_rx_thresh_lvl, 6127 0, CTL_HW, bge_root_num, CTL_CREATE, 6128 CTL_EOL)) != 0) { 6129 goto out; 6130 } 6131 6132 bge_rxthresh_nodenum = node->sysctl_num; 6133 6134 return; 6135 6136 out: 6137 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6138 } 6139 6140 #ifdef BGE_DEBUG 6141 void 6142 bge_debug_info(struct bge_softc *sc) 6143 { 6144 6145 printf("Hardware Flags:\n"); 6146 if (BGE_IS_57765_PLUS(sc)) 6147 printf(" - 57765 Plus\n"); 6148 if (BGE_IS_5717_PLUS(sc)) 6149 printf(" - 5717 Plus\n"); 6150 if (BGE_IS_5755_PLUS(sc)) 6151 printf(" - 5755 Plus\n"); 6152 if (BGE_IS_575X_PLUS(sc)) 6153 printf(" - 575X Plus\n"); 6154 if (BGE_IS_5705_PLUS(sc)) 6155 printf(" - 5705 Plus\n"); 6156 if (BGE_IS_5714_FAMILY(sc)) 6157 printf(" - 5714 Family\n"); 6158 if (BGE_IS_5700_FAMILY(sc)) 6159 printf(" - 5700 Family\n"); 6160 if (sc->bge_flags & BGEF_IS_5788) 6161 printf(" - 5788\n"); 6162 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6163 printf(" - Supports Jumbo Frames\n"); 6164 if (sc->bge_flags & BGEF_NO_EEPROM) 6165 printf(" - No EEPROM\n"); 6166 if (sc->bge_flags & BGEF_PCIX) 6167 printf(" - PCI-X Bus\n"); 6168 if (sc->bge_flags & BGEF_PCIE) 6169 printf(" - PCI Express Bus\n"); 6170 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6171 printf(" - RX Alignment Bug\n"); 6172 if (sc->bge_flags & BGEF_APE) 6173 printf(" - APE\n"); 6174 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6175 printf(" - CPMU\n"); 6176 if (sc->bge_flags & BGEF_TSO) 6177 printf(" - TSO\n"); 6178 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6179 printf(" - TAGGED_STATUS\n"); 6180 6181 /* PHY related */ 6182 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6183 printf(" - No 3 LEDs\n"); 6184 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6185 printf(" - CRC bug\n"); 6186 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6187 printf(" - ADC bug\n"); 6188 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6189 printf(" - 5704 A0 bug\n"); 6190 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6191 printf(" - jitter bug\n"); 6192 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6193 printf(" - BER bug\n"); 6194 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6195 printf(" - adjust trim\n"); 6196 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6197 printf(" - no wirespeed\n"); 6198 6199 /* ASF related */ 6200 if (sc->bge_asf_mode & ASF_ENABLE) 6201 printf(" - ASF enable\n"); 6202 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6203 printf(" - ASF new handshake\n"); 6204 if (sc->bge_asf_mode & ASF_STACKUP) 6205 printf(" - ASF stackup\n"); 6206 } 6207 #endif /* BGE_DEBUG */ 6208 6209 static int 6210 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6211 { 6212 prop_dictionary_t dict; 6213 prop_data_t ea; 6214 6215 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6216 return 1; 6217 6218 dict = device_properties(sc->bge_dev); 6219 ea = prop_dictionary_get(dict, "mac-address"); 6220 if (ea != NULL) { 6221 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6222 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6223 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6224 return 0; 6225 } 6226 6227 return 1; 6228 } 6229 6230 static int 6231 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6232 { 6233 uint32_t mac_addr; 6234 6235 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6236 if ((mac_addr >> 16) == 0x484b) { 6237 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6238 ether_addr[1] = (uint8_t)mac_addr; 6239 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6240 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6241 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6242 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6243 ether_addr[5] = (uint8_t)mac_addr; 6244 return 0; 6245 } 6246 return 1; 6247 } 6248 6249 static int 6250 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6251 { 6252 int mac_offset = BGE_EE_MAC_OFFSET; 6253 6254 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6255 mac_offset = BGE_EE_MAC_OFFSET_5906; 6256 6257 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6258 ETHER_ADDR_LEN)); 6259 } 6260 6261 static int 6262 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6263 { 6264 6265 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6266 return 1; 6267 6268 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6269 ETHER_ADDR_LEN)); 6270 } 6271 6272 static int 6273 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6274 { 6275 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6276 /* NOTE: Order is critical */ 6277 bge_get_eaddr_fw, 6278 bge_get_eaddr_mem, 6279 bge_get_eaddr_nvram, 6280 bge_get_eaddr_eeprom, 6281 NULL 6282 }; 6283 const bge_eaddr_fcn_t *func; 6284 6285 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6286 if ((*func)(sc, eaddr) == 0) 6287 break; 6288 } 6289 return (*func == NULL ? ENXIO : 0); 6290 } 6291
Indexes created Wed Sep 24 05:09:52 GMT 2025