if_bge.c revision 1.326
1 /* $NetBSD: if_bge.c,v 1.326 2019/02/20 15:56:51 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.326 2019/02/20 15:56:51 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 95 #include <net/if.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_ether.h> 99 100 #include <sys/rndsource.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 116 #include <net/bpf.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 #include <dev/pci/pcidevs.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/miidevs.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/if_bgereg.h> 128 #include <dev/pci/if_bgevar.h> 129 130 #include <prop/proplib.h> 131 132 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 133 134 135 /* 136 * Tunable thresholds for rx-side bge interrupt mitigation. 137 */ 138 139 /* 140 * The pairs of values below were obtained from empirical measurement 141 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 142 * interrupt for every N packets received, where N is, approximately, 143 * the second value (rx_max_bds) in each pair. The values are chosen 144 * such that moving from one pair to the succeeding pair was observed 145 * to roughly halve interrupt rate under sustained input packet load. 146 * The values were empirically chosen to avoid overflowing internal 147 * limits on the bcm5700: increasing rx_ticks much beyond 600 148 * results in internal wrapping and higher interrupt rates. 149 * The limit of 46 frames was chosen to match NFS workloads. 150 * 151 * These values also work well on bcm5701, bcm5704C, and (less 152 * tested) bcm5703. On other chipsets, (including the Altima chip 153 * family), the larger values may overflow internal chip limits, 154 * leading to increasing interrupt rates rather than lower interrupt 155 * rates. 156 * 157 * Applications using heavy interrupt mitigation (interrupting every 158 * 32 or 46 frames) in both directions may need to increase the TCP 159 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 160 * full link bandwidth, due to ACKs and window updates lingering 161 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 162 */ 163 static const struct bge_load_rx_thresh { 164 int rx_ticks; 165 int rx_max_bds; } 166 bge_rx_threshes[] = { 167 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 168 { 32, 2 }, 169 { 50, 4 }, 170 { 100, 8 }, 171 { 192, 16 }, 172 { 416, 32 }, 173 { 598, 46 } 174 }; 175 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 176 177 /* XXX patchable; should be sysctl'able */ 178 static int bge_auto_thresh = 1; 179 static int bge_rx_thresh_lvl; 180 181 static int bge_rxthresh_nodenum; 182 183 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 184 185 static uint32_t bge_chipid(const struct pci_attach_args *); 186 static int bge_can_use_msi(struct bge_softc *); 187 static int bge_probe(device_t, cfdata_t, void *); 188 static void bge_attach(device_t, device_t, void *); 189 static int bge_detach(device_t, int); 190 static void bge_release_resources(struct bge_softc *); 191 192 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 197 198 static void bge_txeof(struct bge_softc *); 199 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *m, bool); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_phy_addr(struct bge_softc *); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writembx_flush(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 254 static int bge_miibus_writereg(device_t, int, int, uint16_t); 255 static void bge_miibus_statchg(struct ifnet *); 256 257 #define BGE_RESET_SHUTDOWN 0 258 #define BGE_RESET_START 1 259 #define BGE_RESET_SUSPEND 2 260 static void bge_sig_post_reset(struct bge_softc *, int); 261 static void bge_sig_legacy(struct bge_softc *, int); 262 static void bge_sig_pre_reset(struct bge_softc *, int); 263 static void bge_wait_for_event_ack(struct bge_softc *); 264 static void bge_stop_fw(struct bge_softc *); 265 static int bge_reset(struct bge_softc *); 266 static void bge_link_upd(struct bge_softc *); 267 static void bge_sysctl_init(struct bge_softc *); 268 static int bge_sysctl_verify(SYSCTLFN_PROTO); 269 270 static void bge_ape_lock_init(struct bge_softc *); 271 static void bge_ape_read_fw_ver(struct bge_softc *); 272 static int bge_ape_lock(struct bge_softc *, int); 273 static void bge_ape_unlock(struct bge_softc *, int); 274 static void bge_ape_send_event(struct bge_softc *, uint32_t); 275 static void bge_ape_driver_state_change(struct bge_softc *, int); 276 277 #ifdef BGE_DEBUG 278 #define DPRINTF(x) if (bgedebug) printf x 279 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 280 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 281 int bgedebug = 0; 282 int bge_tso_debug = 0; 283 void bge_debug_info(struct bge_softc *); 284 #else 285 #define DPRINTF(x) 286 #define DPRINTFN(n,x) 287 #define BGE_TSO_PRINTF(x) 288 #endif 289 290 #ifdef BGE_EVENT_COUNTERS 291 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 292 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 293 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 294 #else 295 #define BGE_EVCNT_INCR(ev) /* nothing */ 296 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 297 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 298 #endif 299 300 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 301 /* 302 * The BCM5700 documentation seems to indicate that the hardware still has the 303 * Alteon vendor ID burned into it, though it should always be overridden by 304 * the value in the EEPROM. We'll check for it anyway. 305 */ 306 static const struct bge_product { 307 pci_vendor_id_t bp_vendor; 308 pci_product_id_t bp_product; 309 const char *bp_name; 310 } bge_products[] = { 311 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 312 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 313 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 314 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 315 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 316 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 317 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 319 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 320 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 321 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 322 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 323 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 324 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 325 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 326 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 327 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 328 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 331 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 332 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 333 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 334 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 336 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 338 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 349 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 354 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 359 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 363 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 364 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 367 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 368 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 370 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 371 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 372 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 373 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 375 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 376 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 377 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 379 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 380 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 381 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 382 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 383 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 397 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 398 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 399 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 400 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 401 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 402 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 403 { 0, 0, NULL }, 404 }; 405 406 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 407 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 408 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 409 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 410 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 411 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 412 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 413 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 414 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 415 416 static const struct bge_revision { 417 uint32_t br_chipid; 418 const char *br_name; 419 } bge_revisions[] = { 420 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 421 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 422 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 423 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 424 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 425 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 426 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 427 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 428 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 429 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 430 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 431 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 432 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 433 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 434 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 435 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 436 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 437 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 438 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 439 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 440 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 441 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 442 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 443 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 444 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 445 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 446 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 447 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 448 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 449 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 450 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 451 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 452 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 453 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 454 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 455 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 456 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 457 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 458 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 459 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 460 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 461 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 462 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 463 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 464 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 465 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 466 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 467 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 468 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 469 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 470 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 471 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 472 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 473 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 474 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 475 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 476 /* 5754 and 5787 share the same ASIC ID */ 477 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 478 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 479 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 480 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 481 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 482 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 483 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 484 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 485 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 486 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 487 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 488 489 { 0, NULL } 490 }; 491 492 /* 493 * Some defaults for major revisions, so that newer steppings 494 * that we don't know about have a shot at working. 495 */ 496 static const struct bge_revision bge_majorrevs[] = { 497 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 498 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 499 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 500 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 501 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 502 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 503 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 504 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 505 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 506 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 507 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 508 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 509 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 510 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 511 /* 5754 and 5787 share the same ASIC ID */ 512 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 513 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 514 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 515 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 516 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 517 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 518 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 519 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 520 521 { 0, NULL } 522 }; 523 524 static int bge_allow_asf = 1; 525 526 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 527 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 528 529 static uint32_t 530 bge_readmem_ind(struct bge_softc *sc, int off) 531 { 532 pcireg_t val; 533 534 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 535 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 536 return 0; 537 538 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 539 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 540 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 541 return val; 542 } 543 544 static void 545 bge_writemem_ind(struct bge_softc *sc, int off, int val) 546 { 547 548 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 550 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 551 } 552 553 /* 554 * PCI Express only 555 */ 556 static void 557 bge_set_max_readrq(struct bge_softc *sc) 558 { 559 pcireg_t val; 560 561 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 562 + PCIE_DCSR); 563 val &= ~PCIE_DCSR_MAX_READ_REQ; 564 switch (sc->bge_expmrq) { 565 case 2048: 566 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 567 break; 568 case 4096: 569 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 570 break; 571 default: 572 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 573 break; 574 } 575 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 576 + PCIE_DCSR, val); 577 } 578 579 #ifdef notdef 580 static uint32_t 581 bge_readreg_ind(struct bge_softc *sc, int off) 582 { 583 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 584 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 585 } 586 #endif 587 588 static void 589 bge_writereg_ind(struct bge_softc *sc, int off, int val) 590 { 591 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 592 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 593 } 594 595 static void 596 bge_writemem_direct(struct bge_softc *sc, int off, int val) 597 { 598 CSR_WRITE_4(sc, off, val); 599 } 600 601 static void 602 bge_writembx(struct bge_softc *sc, int off, int val) 603 { 604 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 605 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 606 607 CSR_WRITE_4(sc, off, val); 608 } 609 610 static void 611 bge_writembx_flush(struct bge_softc *sc, int off, int val) 612 { 613 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 614 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 615 616 CSR_WRITE_4_FLUSH(sc, off, val); 617 } 618 619 /* 620 * Clear all stale locks and select the lock for this driver instance. 621 */ 622 void 623 bge_ape_lock_init(struct bge_softc *sc) 624 { 625 struct pci_attach_args *pa = &(sc->bge_pa); 626 uint32_t bit, regbase; 627 int i; 628 629 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 630 regbase = BGE_APE_LOCK_GRANT; 631 else 632 regbase = BGE_APE_PER_LOCK_GRANT; 633 634 /* Clear any stale locks. */ 635 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 636 switch (i) { 637 case BGE_APE_LOCK_PHY0: 638 case BGE_APE_LOCK_PHY1: 639 case BGE_APE_LOCK_PHY2: 640 case BGE_APE_LOCK_PHY3: 641 bit = BGE_APE_LOCK_GRANT_DRIVER0; 642 break; 643 default: 644 if (pa->pa_function == 0) 645 bit = BGE_APE_LOCK_GRANT_DRIVER0; 646 else 647 bit = (1 << pa->pa_function); 648 } 649 APE_WRITE_4(sc, regbase + 4 * i, bit); 650 } 651 652 /* Select the PHY lock based on the device's function number. */ 653 switch (pa->pa_function) { 654 case 0: 655 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 656 break; 657 case 1: 658 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 659 break; 660 case 2: 661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 662 break; 663 case 3: 664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 665 break; 666 default: 667 printf("%s: PHY lock not supported on function\n", 668 device_xname(sc->bge_dev)); 669 break; 670 } 671 } 672 673 /* 674 * Check for APE firmware, set flags, and print version info. 675 */ 676 void 677 bge_ape_read_fw_ver(struct bge_softc *sc) 678 { 679 const char *fwtype; 680 uint32_t apedata, features; 681 682 /* Check for a valid APE signature in shared memory. */ 683 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 684 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 685 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 686 return; 687 } 688 689 /* Check if APE firmware is running. */ 690 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 691 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 692 printf("%s: APE signature found but FW status not ready! " 693 "0x%08x\n", device_xname(sc->bge_dev), apedata); 694 return; 695 } 696 697 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 698 699 /* Fetch the APE firwmare type and version. */ 700 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 701 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 702 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 703 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 704 fwtype = "NCSI"; 705 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 706 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 707 fwtype = "DASH"; 708 } else 709 fwtype = "UNKN"; 710 711 /* Print the APE firmware version. */ 712 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 713 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 714 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 715 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 716 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 717 } 718 719 int 720 bge_ape_lock(struct bge_softc *sc, int locknum) 721 { 722 struct pci_attach_args *pa = &(sc->bge_pa); 723 uint32_t bit, gnt, req, status; 724 int i, off; 725 726 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 727 return (0); 728 729 /* Lock request/grant registers have different bases. */ 730 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 731 req = BGE_APE_LOCK_REQ; 732 gnt = BGE_APE_LOCK_GRANT; 733 } else { 734 req = BGE_APE_PER_LOCK_REQ; 735 gnt = BGE_APE_PER_LOCK_GRANT; 736 } 737 738 off = 4 * locknum; 739 740 switch (locknum) { 741 case BGE_APE_LOCK_GPIO: 742 /* Lock required when using GPIO. */ 743 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 744 return (0); 745 if (pa->pa_function == 0) 746 bit = BGE_APE_LOCK_REQ_DRIVER0; 747 else 748 bit = (1 << pa->pa_function); 749 break; 750 case BGE_APE_LOCK_GRC: 751 /* Lock required to reset the device. */ 752 if (pa->pa_function == 0) 753 bit = BGE_APE_LOCK_REQ_DRIVER0; 754 else 755 bit = (1 << pa->pa_function); 756 break; 757 case BGE_APE_LOCK_MEM: 758 /* Lock required when accessing certain APE memory. */ 759 if (pa->pa_function == 0) 760 bit = BGE_APE_LOCK_REQ_DRIVER0; 761 else 762 bit = (1 << pa->pa_function); 763 break; 764 case BGE_APE_LOCK_PHY0: 765 case BGE_APE_LOCK_PHY1: 766 case BGE_APE_LOCK_PHY2: 767 case BGE_APE_LOCK_PHY3: 768 /* Lock required when accessing PHYs. */ 769 bit = BGE_APE_LOCK_REQ_DRIVER0; 770 break; 771 default: 772 return (EINVAL); 773 } 774 775 /* Request a lock. */ 776 APE_WRITE_4_FLUSH(sc, req + off, bit); 777 778 /* Wait up to 1 second to acquire lock. */ 779 for (i = 0; i < 20000; i++) { 780 status = APE_READ_4(sc, gnt + off); 781 if (status == bit) 782 break; 783 DELAY(50); 784 } 785 786 /* Handle any errors. */ 787 if (status != bit) { 788 printf("%s: APE lock %d request failed! " 789 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 790 device_xname(sc->bge_dev), 791 locknum, req + off, bit & 0xFFFF, gnt + off, 792 status & 0xFFFF); 793 /* Revoke the lock request. */ 794 APE_WRITE_4(sc, gnt + off, bit); 795 return (EBUSY); 796 } 797 798 return (0); 799 } 800 801 void 802 bge_ape_unlock(struct bge_softc *sc, int locknum) 803 { 804 struct pci_attach_args *pa = &(sc->bge_pa); 805 uint32_t bit, gnt; 806 int off; 807 808 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 809 return; 810 811 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 812 gnt = BGE_APE_LOCK_GRANT; 813 else 814 gnt = BGE_APE_PER_LOCK_GRANT; 815 816 off = 4 * locknum; 817 818 switch (locknum) { 819 case BGE_APE_LOCK_GPIO: 820 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 821 return; 822 if (pa->pa_function == 0) 823 bit = BGE_APE_LOCK_GRANT_DRIVER0; 824 else 825 bit = (1 << pa->pa_function); 826 break; 827 case BGE_APE_LOCK_GRC: 828 if (pa->pa_function == 0) 829 bit = BGE_APE_LOCK_GRANT_DRIVER0; 830 else 831 bit = (1 << pa->pa_function); 832 break; 833 case BGE_APE_LOCK_MEM: 834 if (pa->pa_function == 0) 835 bit = BGE_APE_LOCK_GRANT_DRIVER0; 836 else 837 bit = (1 << pa->pa_function); 838 break; 839 case BGE_APE_LOCK_PHY0: 840 case BGE_APE_LOCK_PHY1: 841 case BGE_APE_LOCK_PHY2: 842 case BGE_APE_LOCK_PHY3: 843 bit = BGE_APE_LOCK_GRANT_DRIVER0; 844 break; 845 default: 846 return; 847 } 848 849 /* Write and flush for consecutive bge_ape_lock() */ 850 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 851 } 852 853 /* 854 * Send an event to the APE firmware. 855 */ 856 void 857 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 858 { 859 uint32_t apedata; 860 int i; 861 862 /* NCSI does not support APE events. */ 863 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 864 return; 865 866 /* Wait up to 1ms for APE to service previous event. */ 867 for (i = 10; i > 0; i--) { 868 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 869 break; 870 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 871 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 872 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 873 BGE_APE_EVENT_STATUS_EVENT_PENDING); 874 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 875 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 876 break; 877 } 878 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 879 DELAY(100); 880 } 881 if (i == 0) { 882 printf("%s: APE event 0x%08x send timed out\n", 883 device_xname(sc->bge_dev), event); 884 } 885 } 886 887 void 888 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 889 { 890 uint32_t apedata, event; 891 892 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 893 return; 894 895 switch (kind) { 896 case BGE_RESET_START: 897 /* If this is the first load, clear the load counter. */ 898 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 899 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 900 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 901 else { 902 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 903 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 904 } 905 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 906 BGE_APE_HOST_SEG_SIG_MAGIC); 907 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 908 BGE_APE_HOST_SEG_LEN_MAGIC); 909 910 /* Add some version info if bge(4) supports it. */ 911 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 912 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 913 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 914 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 915 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 916 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 917 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 918 BGE_APE_HOST_DRVR_STATE_START); 919 event = BGE_APE_EVENT_STATUS_STATE_START; 920 break; 921 case BGE_RESET_SHUTDOWN: 922 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 923 BGE_APE_HOST_DRVR_STATE_UNLOAD); 924 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 925 break; 926 case BGE_RESET_SUSPEND: 927 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 928 break; 929 default: 930 return; 931 } 932 933 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 934 BGE_APE_EVENT_STATUS_STATE_CHNGE); 935 } 936 937 static uint8_t 938 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 939 { 940 uint32_t access, byte = 0; 941 int i; 942 943 /* Lock. */ 944 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 945 for (i = 0; i < 8000; i++) { 946 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 947 break; 948 DELAY(20); 949 } 950 if (i == 8000) 951 return 1; 952 953 /* Enable access. */ 954 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 955 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 956 957 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 958 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 959 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 960 DELAY(10); 961 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 962 DELAY(10); 963 break; 964 } 965 } 966 967 if (i == BGE_TIMEOUT * 10) { 968 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 969 return 1; 970 } 971 972 /* Get result. */ 973 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 974 975 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 976 977 /* Disable access. */ 978 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 979 980 /* Unlock. */ 981 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 982 983 return 0; 984 } 985 986 /* 987 * Read a sequence of bytes from NVRAM. 988 */ 989 static int 990 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 991 { 992 int error = 0, i; 993 uint8_t byte = 0; 994 995 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 996 return 1; 997 998 for (i = 0; i < cnt; i++) { 999 error = bge_nvram_getbyte(sc, off + i, &byte); 1000 if (error) 1001 break; 1002 *(dest + i) = byte; 1003 } 1004 1005 return (error ? 1 : 0); 1006 } 1007 1008 /* 1009 * Read a byte of data stored in the EEPROM at address 'addr.' The 1010 * BCM570x supports both the traditional bitbang interface and an 1011 * auto access interface for reading the EEPROM. We use the auto 1012 * access method. 1013 */ 1014 static uint8_t 1015 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1016 { 1017 int i; 1018 uint32_t byte = 0; 1019 1020 /* 1021 * Enable use of auto EEPROM access so we can avoid 1022 * having to use the bitbang method. 1023 */ 1024 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1025 1026 /* Reset the EEPROM, load the clock period. */ 1027 CSR_WRITE_4(sc, BGE_EE_ADDR, 1028 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1029 DELAY(20); 1030 1031 /* Issue the read EEPROM command. */ 1032 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1033 1034 /* Wait for completion */ 1035 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1036 DELAY(10); 1037 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1038 break; 1039 } 1040 1041 if (i == BGE_TIMEOUT * 10) { 1042 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1043 return 1; 1044 } 1045 1046 /* Get result. */ 1047 byte = CSR_READ_4(sc, BGE_EE_DATA); 1048 1049 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1050 1051 return 0; 1052 } 1053 1054 /* 1055 * Read a sequence of bytes from the EEPROM. 1056 */ 1057 static int 1058 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1059 { 1060 int error = 0, i; 1061 uint8_t byte = 0; 1062 char *dest = destv; 1063 1064 for (i = 0; i < cnt; i++) { 1065 error = bge_eeprom_getbyte(sc, off + i, &byte); 1066 if (error) 1067 break; 1068 *(dest + i) = byte; 1069 } 1070 1071 return (error ? 1 : 0); 1072 } 1073 1074 static int 1075 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1076 { 1077 struct bge_softc *sc = device_private(dev); 1078 uint32_t data; 1079 uint32_t autopoll; 1080 int rv = 0; 1081 int i; 1082 1083 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1084 return -1; 1085 1086 /* Reading with autopolling on may trigger PCI errors */ 1087 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1088 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1089 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1090 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1091 DELAY(80); 1092 } 1093 1094 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1095 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1096 1097 for (i = 0; i < BGE_TIMEOUT; i++) { 1098 delay(10); 1099 data = CSR_READ_4(sc, BGE_MI_COMM); 1100 if (!(data & BGE_MICOMM_BUSY)) { 1101 DELAY(5); 1102 data = CSR_READ_4(sc, BGE_MI_COMM); 1103 break; 1104 } 1105 } 1106 1107 if (i == BGE_TIMEOUT) { 1108 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1109 rv = ETIMEDOUT; 1110 } else if ((data & BGE_MICOMM_READFAIL) != 0) 1111 rv = -1; 1112 else 1113 *val = data & BGE_MICOMM_DATA; 1114 1115 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1116 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1117 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1118 DELAY(80); 1119 } 1120 1121 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1122 1123 return rv; 1124 } 1125 1126 static int 1127 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1128 { 1129 struct bge_softc *sc = device_private(dev); 1130 uint32_t autopoll; 1131 int i; 1132 1133 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1134 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1135 return 0; 1136 1137 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1138 return -1; 1139 1140 /* Reading with autopolling on may trigger PCI errors */ 1141 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1142 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1143 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1144 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1145 DELAY(80); 1146 } 1147 1148 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1149 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1150 1151 for (i = 0; i < BGE_TIMEOUT; i++) { 1152 delay(10); 1153 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1154 delay(5); 1155 CSR_READ_4(sc, BGE_MI_COMM); 1156 break; 1157 } 1158 } 1159 1160 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1161 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1162 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1163 delay(80); 1164 } 1165 1166 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1167 1168 if (i == BGE_TIMEOUT) { 1169 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1170 return ETIMEDOUT; 1171 } 1172 1173 return 0; 1174 } 1175 1176 static void 1177 bge_miibus_statchg(struct ifnet *ifp) 1178 { 1179 struct bge_softc *sc = ifp->if_softc; 1180 struct mii_data *mii = &sc->bge_mii; 1181 uint32_t mac_mode, rx_mode, tx_mode; 1182 1183 /* 1184 * Get flow control negotiation result. 1185 */ 1186 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1187 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1188 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1189 1190 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1191 mii->mii_media_status & IFM_ACTIVE && 1192 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1193 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1194 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1195 (!(mii->mii_media_status & IFM_ACTIVE) || 1196 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1197 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1198 1199 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1200 return; 1201 1202 /* Set the port mode (MII/GMII) to match the link speed. */ 1203 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1204 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1205 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1206 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1207 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1208 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1209 mac_mode |= BGE_PORTMODE_GMII; 1210 else 1211 mac_mode |= BGE_PORTMODE_MII; 1212 1213 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1214 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1215 if ((mii->mii_media_active & IFM_FDX) != 0) { 1216 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1217 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1218 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1219 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1220 } else 1221 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1222 1223 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1224 DELAY(40); 1225 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1226 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1227 } 1228 1229 /* 1230 * Update rx threshold levels to values in a particular slot 1231 * of the interrupt-mitigation table bge_rx_threshes. 1232 */ 1233 static void 1234 bge_set_thresh(struct ifnet *ifp, int lvl) 1235 { 1236 struct bge_softc *sc = ifp->if_softc; 1237 int s; 1238 1239 /* For now, just save the new Rx-intr thresholds and record 1240 * that a threshold update is pending. Updating the hardware 1241 * registers here (even at splhigh()) is observed to 1242 * occasionaly cause glitches where Rx-interrupts are not 1243 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1244 */ 1245 s = splnet(); 1246 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1247 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1248 sc->bge_pending_rxintr_change = 1; 1249 splx(s); 1250 } 1251 1252 1253 /* 1254 * Update Rx thresholds of all bge devices 1255 */ 1256 static void 1257 bge_update_all_threshes(int lvl) 1258 { 1259 struct ifnet *ifp; 1260 const char * const namebuf = "bge"; 1261 int namelen; 1262 int s; 1263 1264 if (lvl < 0) 1265 lvl = 0; 1266 else if (lvl >= NBGE_RX_THRESH) 1267 lvl = NBGE_RX_THRESH - 1; 1268 1269 namelen = strlen(namebuf); 1270 /* 1271 * Now search all the interfaces for this name/number 1272 */ 1273 s = pserialize_read_enter(); 1274 IFNET_READER_FOREACH(ifp) { 1275 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1276 continue; 1277 /* We got a match: update if doing auto-threshold-tuning */ 1278 if (bge_auto_thresh) 1279 bge_set_thresh(ifp, lvl); 1280 } 1281 pserialize_read_exit(s); 1282 } 1283 1284 /* 1285 * Handle events that have triggered interrupts. 1286 */ 1287 static void 1288 bge_handle_events(struct bge_softc *sc) 1289 { 1290 1291 return; 1292 } 1293 1294 /* 1295 * Memory management for jumbo frames. 1296 */ 1297 1298 static int 1299 bge_alloc_jumbo_mem(struct bge_softc *sc) 1300 { 1301 char *ptr, *kva; 1302 bus_dma_segment_t seg; 1303 int i, rseg, state, error; 1304 struct bge_jpool_entry *entry; 1305 1306 state = error = 0; 1307 1308 /* Grab a big chunk o' storage. */ 1309 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1310 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1311 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1312 return ENOBUFS; 1313 } 1314 1315 state = 1; 1316 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1317 BUS_DMA_NOWAIT)) { 1318 aprint_error_dev(sc->bge_dev, 1319 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1320 error = ENOBUFS; 1321 goto out; 1322 } 1323 1324 state = 2; 1325 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1326 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1327 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1328 error = ENOBUFS; 1329 goto out; 1330 } 1331 1332 state = 3; 1333 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1334 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1335 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1336 error = ENOBUFS; 1337 goto out; 1338 } 1339 1340 state = 4; 1341 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1342 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1343 1344 SLIST_INIT(&sc->bge_jfree_listhead); 1345 SLIST_INIT(&sc->bge_jinuse_listhead); 1346 1347 /* 1348 * Now divide it up into 9K pieces and save the addresses 1349 * in an array. 1350 */ 1351 ptr = sc->bge_cdata.bge_jumbo_buf; 1352 for (i = 0; i < BGE_JSLOTS; i++) { 1353 sc->bge_cdata.bge_jslots[i] = ptr; 1354 ptr += BGE_JLEN; 1355 entry = malloc(sizeof(struct bge_jpool_entry), 1356 M_DEVBUF, M_NOWAIT); 1357 if (entry == NULL) { 1358 aprint_error_dev(sc->bge_dev, 1359 "no memory for jumbo buffer queue!\n"); 1360 error = ENOBUFS; 1361 goto out; 1362 } 1363 entry->slot = i; 1364 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1365 entry, jpool_entries); 1366 } 1367 out: 1368 if (error != 0) { 1369 switch (state) { 1370 case 4: 1371 bus_dmamap_unload(sc->bge_dmatag, 1372 sc->bge_cdata.bge_rx_jumbo_map); 1373 /* FALLTHROUGH */ 1374 case 3: 1375 bus_dmamap_destroy(sc->bge_dmatag, 1376 sc->bge_cdata.bge_rx_jumbo_map); 1377 /* FALLTHROUGH */ 1378 case 2: 1379 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1380 /* FALLTHROUGH */ 1381 case 1: 1382 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1383 break; 1384 default: 1385 break; 1386 } 1387 } 1388 1389 return error; 1390 } 1391 1392 /* 1393 * Allocate a jumbo buffer. 1394 */ 1395 static void * 1396 bge_jalloc(struct bge_softc *sc) 1397 { 1398 struct bge_jpool_entry *entry; 1399 1400 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1401 1402 if (entry == NULL) { 1403 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1404 return NULL; 1405 } 1406 1407 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1408 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1409 return (sc->bge_cdata.bge_jslots[entry->slot]); 1410 } 1411 1412 /* 1413 * Release a jumbo buffer. 1414 */ 1415 static void 1416 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1417 { 1418 struct bge_jpool_entry *entry; 1419 struct bge_softc *sc; 1420 int i, s; 1421 1422 /* Extract the softc struct pointer. */ 1423 sc = (struct bge_softc *)arg; 1424 1425 if (sc == NULL) 1426 panic("bge_jfree: can't find softc pointer!"); 1427 1428 /* calculate the slot this buffer belongs to */ 1429 1430 i = ((char *)buf 1431 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1432 1433 if ((i < 0) || (i >= BGE_JSLOTS)) 1434 panic("bge_jfree: asked to free buffer that we don't manage!"); 1435 1436 s = splvm(); 1437 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1438 if (entry == NULL) 1439 panic("bge_jfree: buffer not in use!"); 1440 entry->slot = i; 1441 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1442 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1443 1444 if (__predict_true(m != NULL)) 1445 pool_cache_put(mb_cache, m); 1446 splx(s); 1447 } 1448 1449 1450 /* 1451 * Initialize a standard receive ring descriptor. 1452 */ 1453 static int 1454 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1455 bus_dmamap_t dmamap) 1456 { 1457 struct mbuf *m_new = NULL; 1458 struct bge_rx_bd *r; 1459 int error; 1460 1461 if (dmamap == NULL) 1462 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1463 1464 if (dmamap == NULL) { 1465 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1466 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1467 if (error != 0) 1468 return error; 1469 } 1470 1471 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1472 1473 if (m == NULL) { 1474 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1475 if (m_new == NULL) 1476 return ENOBUFS; 1477 1478 MCLGET(m_new, M_DONTWAIT); 1479 if (!(m_new->m_flags & M_EXT)) { 1480 m_freem(m_new); 1481 return ENOBUFS; 1482 } 1483 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1484 1485 } else { 1486 m_new = m; 1487 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1488 m_new->m_data = m_new->m_ext.ext_buf; 1489 } 1490 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1491 m_adj(m_new, ETHER_ALIGN); 1492 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1493 BUS_DMA_READ|BUS_DMA_NOWAIT)) { 1494 m_freem(m_new); 1495 return ENOBUFS; 1496 } 1497 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1498 BUS_DMASYNC_PREREAD); 1499 1500 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1501 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1502 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1503 r->bge_flags = BGE_RXBDFLAG_END; 1504 r->bge_len = m_new->m_len; 1505 r->bge_idx = i; 1506 1507 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1508 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1509 i * sizeof (struct bge_rx_bd), 1510 sizeof (struct bge_rx_bd), 1511 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1512 1513 return 0; 1514 } 1515 1516 /* 1517 * Initialize a jumbo receive ring descriptor. This allocates 1518 * a jumbo buffer from the pool managed internally by the driver. 1519 */ 1520 static int 1521 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1522 { 1523 struct mbuf *m_new = NULL; 1524 struct bge_rx_bd *r; 1525 void *buf = NULL; 1526 1527 if (m == NULL) { 1528 1529 /* Allocate the mbuf. */ 1530 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1531 if (m_new == NULL) 1532 return ENOBUFS; 1533 1534 /* Allocate the jumbo buffer */ 1535 buf = bge_jalloc(sc); 1536 if (buf == NULL) { 1537 m_freem(m_new); 1538 aprint_error_dev(sc->bge_dev, 1539 "jumbo allocation failed -- packet dropped!\n"); 1540 return ENOBUFS; 1541 } 1542 1543 /* Attach the buffer to the mbuf. */ 1544 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1545 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1546 bge_jfree, sc); 1547 m_new->m_flags |= M_EXT_RW; 1548 } else { 1549 m_new = m; 1550 buf = m_new->m_data = m_new->m_ext.ext_buf; 1551 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1552 } 1553 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1554 m_adj(m_new, ETHER_ALIGN); 1555 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1556 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1557 BUS_DMASYNC_PREREAD); 1558 /* Set up the descriptor. */ 1559 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1560 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1561 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1562 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1563 r->bge_len = m_new->m_len; 1564 r->bge_idx = i; 1565 1566 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1567 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1568 i * sizeof (struct bge_rx_bd), 1569 sizeof (struct bge_rx_bd), 1570 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1571 1572 return 0; 1573 } 1574 1575 /* 1576 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1577 * that's 1MB or memory, which is a lot. For now, we fill only the first 1578 * 256 ring entries and hope that our CPU is fast enough to keep up with 1579 * the NIC. 1580 */ 1581 static int 1582 bge_init_rx_ring_std(struct bge_softc *sc) 1583 { 1584 int i; 1585 1586 if (sc->bge_flags & BGEF_RXRING_VALID) 1587 return 0; 1588 1589 for (i = 0; i < BGE_SSLOTS; i++) { 1590 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1591 return ENOBUFS; 1592 } 1593 1594 sc->bge_std = i - 1; 1595 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1596 1597 sc->bge_flags |= BGEF_RXRING_VALID; 1598 1599 return 0; 1600 } 1601 1602 static void 1603 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1604 { 1605 int i; 1606 1607 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1608 return; 1609 1610 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1611 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1612 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1613 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1614 if (disable) { 1615 bus_dmamap_destroy(sc->bge_dmatag, 1616 sc->bge_cdata.bge_rx_std_map[i]); 1617 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1618 } 1619 } 1620 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1621 sizeof(struct bge_rx_bd)); 1622 } 1623 1624 sc->bge_flags &= ~BGEF_RXRING_VALID; 1625 } 1626 1627 static int 1628 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1629 { 1630 int i; 1631 volatile struct bge_rcb *rcb; 1632 1633 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1634 return 0; 1635 1636 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1637 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1638 return ENOBUFS; 1639 } 1640 1641 sc->bge_jumbo = i - 1; 1642 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1643 1644 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1645 rcb->bge_maxlen_flags = 0; 1646 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1647 1648 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1649 1650 return 0; 1651 } 1652 1653 static void 1654 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1655 { 1656 int i; 1657 1658 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1659 return; 1660 1661 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1662 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1663 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1664 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1665 } 1666 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1667 sizeof(struct bge_rx_bd)); 1668 } 1669 1670 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1671 } 1672 1673 static void 1674 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1675 { 1676 int i; 1677 struct txdmamap_pool_entry *dma; 1678 1679 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1680 return; 1681 1682 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1683 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1684 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1685 sc->bge_cdata.bge_tx_chain[i] = NULL; 1686 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1687 link); 1688 sc->txdma[i] = 0; 1689 } 1690 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1691 sizeof(struct bge_tx_bd)); 1692 } 1693 1694 if (disable) { 1695 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1696 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1697 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1698 if (sc->bge_dma64) { 1699 bus_dmamap_destroy(sc->bge_dmatag32, 1700 dma->dmamap32); 1701 } 1702 free(dma, M_DEVBUF); 1703 } 1704 SLIST_INIT(&sc->txdma_list); 1705 } 1706 1707 sc->bge_flags &= ~BGEF_TXRING_VALID; 1708 } 1709 1710 static int 1711 bge_init_tx_ring(struct bge_softc *sc) 1712 { 1713 struct ifnet *ifp = &sc->ethercom.ec_if; 1714 int i; 1715 bus_dmamap_t dmamap, dmamap32; 1716 bus_size_t maxsegsz; 1717 struct txdmamap_pool_entry *dma; 1718 1719 if (sc->bge_flags & BGEF_TXRING_VALID) 1720 return 0; 1721 1722 sc->bge_txcnt = 0; 1723 sc->bge_tx_saved_considx = 0; 1724 1725 /* Initialize transmit producer index for host-memory send ring. */ 1726 sc->bge_tx_prodidx = 0; 1727 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1728 /* 5700 b2 errata */ 1729 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1730 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1731 1732 /* NIC-memory send ring not used; initialize to zero. */ 1733 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1734 /* 5700 b2 errata */ 1735 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1736 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1737 1738 /* Limit DMA segment size for some chips */ 1739 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1740 (ifp->if_mtu <= ETHERMTU)) 1741 maxsegsz = 2048; 1742 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1743 maxsegsz = 4096; 1744 else 1745 maxsegsz = ETHER_MAX_LEN_JUMBO; 1746 1747 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1748 goto alloc_done; 1749 1750 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1751 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1752 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1753 &dmamap)) 1754 return ENOBUFS; 1755 if (dmamap == NULL) 1756 panic("dmamap NULL in bge_init_tx_ring"); 1757 if (sc->bge_dma64) { 1758 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1759 BGE_NTXSEG, maxsegsz, 0, 1760 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1761 &dmamap32)) { 1762 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1763 return ENOBUFS; 1764 } 1765 if (dmamap32 == NULL) 1766 panic("dmamap32 NULL in bge_init_tx_ring"); 1767 } else 1768 dmamap32 = dmamap; 1769 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1770 if (dma == NULL) { 1771 aprint_error_dev(sc->bge_dev, 1772 "can't alloc txdmamap_pool_entry\n"); 1773 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1774 if (sc->bge_dma64) 1775 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1776 return ENOMEM; 1777 } 1778 dma->dmamap = dmamap; 1779 dma->dmamap32 = dmamap32; 1780 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1781 } 1782 alloc_done: 1783 sc->bge_flags |= BGEF_TXRING_VALID; 1784 1785 return 0; 1786 } 1787 1788 static void 1789 bge_setmulti(struct bge_softc *sc) 1790 { 1791 struct ethercom *ac = &sc->ethercom; 1792 struct ifnet *ifp = &ac->ec_if; 1793 struct ether_multi *enm; 1794 struct ether_multistep step; 1795 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1796 uint32_t h; 1797 int i; 1798 1799 if (ifp->if_flags & IFF_PROMISC) 1800 goto allmulti; 1801 1802 /* Now program new ones. */ 1803 ETHER_FIRST_MULTI(step, ac, enm); 1804 while (enm != NULL) { 1805 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1806 /* 1807 * We must listen to a range of multicast addresses. 1808 * For now, just accept all multicasts, rather than 1809 * trying to set only those filter bits needed to match 1810 * the range. (At this time, the only use of address 1811 * ranges is for IP multicast routing, for which the 1812 * range is big enough to require all bits set.) 1813 */ 1814 goto allmulti; 1815 } 1816 1817 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1818 1819 /* Just want the 7 least-significant bits. */ 1820 h &= 0x7f; 1821 1822 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1823 ETHER_NEXT_MULTI(step, enm); 1824 } 1825 1826 ifp->if_flags &= ~IFF_ALLMULTI; 1827 goto setit; 1828 1829 allmulti: 1830 ifp->if_flags |= IFF_ALLMULTI; 1831 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1832 1833 setit: 1834 for (i = 0; i < 4; i++) 1835 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1836 } 1837 1838 static void 1839 bge_sig_pre_reset(struct bge_softc *sc, int type) 1840 { 1841 1842 /* 1843 * Some chips don't like this so only do this if ASF is enabled 1844 */ 1845 if (sc->bge_asf_mode) 1846 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1847 1848 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1849 switch (type) { 1850 case BGE_RESET_START: 1851 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1852 BGE_FW_DRV_STATE_START); 1853 break; 1854 case BGE_RESET_SHUTDOWN: 1855 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1856 BGE_FW_DRV_STATE_UNLOAD); 1857 break; 1858 case BGE_RESET_SUSPEND: 1859 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1860 BGE_FW_DRV_STATE_SUSPEND); 1861 break; 1862 } 1863 } 1864 1865 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1866 bge_ape_driver_state_change(sc, type); 1867 } 1868 1869 static void 1870 bge_sig_post_reset(struct bge_softc *sc, int type) 1871 { 1872 1873 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1874 switch (type) { 1875 case BGE_RESET_START: 1876 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1877 BGE_FW_DRV_STATE_START_DONE); 1878 /* START DONE */ 1879 break; 1880 case BGE_RESET_SHUTDOWN: 1881 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1882 BGE_FW_DRV_STATE_UNLOAD_DONE); 1883 break; 1884 } 1885 } 1886 1887 if (type == BGE_RESET_SHUTDOWN) 1888 bge_ape_driver_state_change(sc, type); 1889 } 1890 1891 static void 1892 bge_sig_legacy(struct bge_softc *sc, int type) 1893 { 1894 1895 if (sc->bge_asf_mode) { 1896 switch (type) { 1897 case BGE_RESET_START: 1898 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1899 BGE_FW_DRV_STATE_START); 1900 break; 1901 case BGE_RESET_SHUTDOWN: 1902 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1903 BGE_FW_DRV_STATE_UNLOAD); 1904 break; 1905 } 1906 } 1907 } 1908 1909 static void 1910 bge_wait_for_event_ack(struct bge_softc *sc) 1911 { 1912 int i; 1913 1914 /* wait up to 2500usec */ 1915 for (i = 0; i < 250; i++) { 1916 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1917 BGE_RX_CPU_DRV_EVENT)) 1918 break; 1919 DELAY(10); 1920 } 1921 } 1922 1923 static void 1924 bge_stop_fw(struct bge_softc *sc) 1925 { 1926 1927 if (sc->bge_asf_mode) { 1928 bge_wait_for_event_ack(sc); 1929 1930 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1931 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1932 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1933 1934 bge_wait_for_event_ack(sc); 1935 } 1936 } 1937 1938 static int 1939 bge_poll_fw(struct bge_softc *sc) 1940 { 1941 uint32_t val; 1942 int i; 1943 1944 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1945 for (i = 0; i < BGE_TIMEOUT; i++) { 1946 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1947 if (val & BGE_VCPU_STATUS_INIT_DONE) 1948 break; 1949 DELAY(100); 1950 } 1951 if (i >= BGE_TIMEOUT) { 1952 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1953 return -1; 1954 } 1955 } else { 1956 /* 1957 * Poll the value location we just wrote until 1958 * we see the 1's complement of the magic number. 1959 * This indicates that the firmware initialization 1960 * is complete. 1961 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1962 */ 1963 for (i = 0; i < BGE_TIMEOUT; i++) { 1964 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1965 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1966 break; 1967 DELAY(10); 1968 } 1969 1970 if ((i >= BGE_TIMEOUT) 1971 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1972 aprint_error_dev(sc->bge_dev, 1973 "firmware handshake timed out, val = %x\n", val); 1974 return -1; 1975 } 1976 } 1977 1978 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1979 /* tg3 says we have to wait extra time */ 1980 delay(10 * 1000); 1981 } 1982 1983 return 0; 1984 } 1985 1986 int 1987 bge_phy_addr(struct bge_softc *sc) 1988 { 1989 struct pci_attach_args *pa = &(sc->bge_pa); 1990 int phy_addr = 1; 1991 1992 /* 1993 * PHY address mapping for various devices. 1994 * 1995 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 1996 * ---------+-------+-------+-------+-------+ 1997 * BCM57XX | 1 | X | X | X | 1998 * BCM5704 | 1 | X | 1 | X | 1999 * BCM5717 | 1 | 8 | 2 | 9 | 2000 * BCM5719 | 1 | 8 | 2 | 9 | 2001 * BCM5720 | 1 | 8 | 2 | 9 | 2002 * 2003 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2004 * ---------+-------+-------+-------+-------+ 2005 * BCM57XX | X | X | X | X | 2006 * BCM5704 | X | X | X | X | 2007 * BCM5717 | X | X | X | X | 2008 * BCM5719 | 3 | 10 | 4 | 11 | 2009 * BCM5720 | X | X | X | X | 2010 * 2011 * Other addresses may respond but they are not 2012 * IEEE compliant PHYs and should be ignored. 2013 */ 2014 switch (BGE_ASICREV(sc->bge_chipid)) { 2015 case BGE_ASICREV_BCM5717: 2016 case BGE_ASICREV_BCM5719: 2017 case BGE_ASICREV_BCM5720: 2018 phy_addr = pa->pa_function; 2019 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2020 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2021 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2022 } else { 2023 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2024 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2025 } 2026 } 2027 2028 return phy_addr; 2029 } 2030 2031 /* 2032 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2033 * self-test results. 2034 */ 2035 static int 2036 bge_chipinit(struct bge_softc *sc) 2037 { 2038 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2039 int i; 2040 2041 /* Set endianness before we access any non-PCI registers. */ 2042 misc_ctl = BGE_INIT; 2043 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2044 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2045 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2046 misc_ctl); 2047 2048 /* 2049 * Clear the MAC statistics block in the NIC's 2050 * internal memory. 2051 */ 2052 for (i = BGE_STATS_BLOCK; 2053 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2054 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2055 2056 for (i = BGE_STATUS_BLOCK; 2057 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2058 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2059 2060 /* 5717 workaround from tg3 */ 2061 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2062 /* Save */ 2063 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2064 2065 /* Temporary modify MODE_CTL to control TLP */ 2066 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2067 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2068 2069 /* Control TLP */ 2070 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2071 BGE_TLP_PHYCTL1); 2072 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2073 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2074 2075 /* Restore */ 2076 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2077 } 2078 2079 if (BGE_IS_57765_FAMILY(sc)) { 2080 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2081 /* Save */ 2082 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2083 2084 /* Temporary modify MODE_CTL to control TLP */ 2085 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2086 CSR_WRITE_4(sc, BGE_MODE_CTL, 2087 reg | BGE_MODECTL_PCIE_TLPADDR1); 2088 2089 /* Control TLP */ 2090 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2091 BGE_TLP_PHYCTL5); 2092 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2093 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2094 2095 /* Restore */ 2096 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2097 } 2098 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2099 /* 2100 * For the 57766 and non Ax versions of 57765, bootcode 2101 * needs to setup the PCIE Fast Training Sequence (FTS) 2102 * value to prevent transmit hangs. 2103 */ 2104 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2105 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2106 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2107 2108 /* Save */ 2109 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2110 2111 /* Temporary modify MODE_CTL to control TLP */ 2112 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2113 CSR_WRITE_4(sc, BGE_MODE_CTL, 2114 reg | BGE_MODECTL_PCIE_TLPADDR0); 2115 2116 /* Control TLP */ 2117 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2118 BGE_TLP_FTSMAX); 2119 reg &= ~BGE_TLP_FTSMAX_MSK; 2120 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2121 reg | BGE_TLP_FTSMAX_VAL); 2122 2123 /* Restore */ 2124 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2125 } 2126 2127 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2128 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2129 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2130 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2131 } 2132 2133 /* Set up the PCI DMA control register. */ 2134 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2135 if (sc->bge_flags & BGEF_PCIE) { 2136 /* Read watermark not used, 128 bytes for write. */ 2137 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2138 device_xname(sc->bge_dev))); 2139 if (sc->bge_mps >= 256) 2140 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2141 else 2142 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2143 } else if (sc->bge_flags & BGEF_PCIX) { 2144 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2145 device_xname(sc->bge_dev))); 2146 /* PCI-X bus */ 2147 if (BGE_IS_5714_FAMILY(sc)) { 2148 /* 256 bytes for read and write. */ 2149 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2150 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2151 2152 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2153 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2154 else 2155 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2156 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2157 /* 2158 * In the BCM5703, the DMA read watermark should 2159 * be set to less than or equal to the maximum 2160 * memory read byte count of the PCI-X command 2161 * register. 2162 */ 2163 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2164 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2165 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2166 /* 1536 bytes for read, 384 bytes for write. */ 2167 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2168 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2169 } else { 2170 /* 384 bytes for read and write. */ 2171 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2172 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2173 (0x0F); 2174 } 2175 2176 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2177 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2178 uint32_t tmp; 2179 2180 /* Set ONEDMA_ATONCE for hardware workaround. */ 2181 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2182 if (tmp == 6 || tmp == 7) 2183 dma_rw_ctl |= 2184 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2185 2186 /* Set PCI-X DMA write workaround. */ 2187 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2188 } 2189 } else { 2190 /* Conventional PCI bus: 256 bytes for read and write. */ 2191 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2192 device_xname(sc->bge_dev))); 2193 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2194 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2195 2196 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2197 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2198 dma_rw_ctl |= 0x0F; 2199 } 2200 2201 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2202 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2203 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2204 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2205 2206 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2207 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2208 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2209 2210 if (BGE_IS_57765_PLUS(sc)) { 2211 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2212 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2213 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2214 2215 /* 2216 * Enable HW workaround for controllers that misinterpret 2217 * a status tag update and leave interrupts permanently 2218 * disabled. 2219 */ 2220 if (!BGE_IS_57765_FAMILY(sc) && 2221 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) 2222 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2223 } 2224 2225 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2226 dma_rw_ctl); 2227 2228 /* 2229 * Set up general mode register. 2230 */ 2231 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2232 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2233 /* Retain Host-2-BMC settings written by APE firmware. */ 2234 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2235 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2236 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2237 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2238 } 2239 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2240 BGE_MODECTL_TX_NO_PHDR_CSUM; 2241 2242 /* 2243 * BCM5701 B5 have a bug causing data corruption when using 2244 * 64-bit DMA reads, which can be terminated early and then 2245 * completed later as 32-bit accesses, in combination with 2246 * certain bridges. 2247 */ 2248 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2249 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2250 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2251 2252 /* 2253 * Tell the firmware the driver is running 2254 */ 2255 if (sc->bge_asf_mode & ASF_STACKUP) 2256 mode_ctl |= BGE_MODECTL_STACKUP; 2257 2258 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2259 2260 /* 2261 * Disable memory write invalidate. Apparently it is not supported 2262 * properly by these devices. 2263 */ 2264 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2265 PCI_COMMAND_INVALIDATE_ENABLE); 2266 2267 #ifdef __brokenalpha__ 2268 /* 2269 * Must insure that we do not cross an 8K (bytes) boundary 2270 * for DMA reads. Our highest limit is 1K bytes. This is a 2271 * restriction on some ALPHA platforms with early revision 2272 * 21174 PCI chipsets, such as the AlphaPC 164lx 2273 */ 2274 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2275 #endif 2276 2277 /* Set the timer prescaler (always 66MHz) */ 2278 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2279 2280 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2281 DELAY(40); /* XXX */ 2282 2283 /* Put PHY into ready state */ 2284 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2285 DELAY(40); 2286 } 2287 2288 return 0; 2289 } 2290 2291 static int 2292 bge_blockinit(struct bge_softc *sc) 2293 { 2294 volatile struct bge_rcb *rcb; 2295 bus_size_t rcb_addr; 2296 struct ifnet *ifp = &sc->ethercom.ec_if; 2297 bge_hostaddr taddr; 2298 uint32_t dmactl, mimode, val; 2299 int i, limit; 2300 2301 /* 2302 * Initialize the memory window pointer register so that 2303 * we can access the first 32K of internal NIC RAM. This will 2304 * allow us to set up the TX send ring RCBs and the RX return 2305 * ring RCBs, plus other things which live in NIC memory. 2306 */ 2307 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2308 2309 if (!BGE_IS_5705_PLUS(sc)) { 2310 /* 57XX step 33 */ 2311 /* Configure mbuf memory pool */ 2312 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 2313 BGE_BUFFPOOL_1); 2314 2315 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2316 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2317 else 2318 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2319 2320 /* 57XX step 34 */ 2321 /* Configure DMA resource pool */ 2322 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2323 BGE_DMA_DESCRIPTORS); 2324 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2325 } 2326 2327 /* 5718 step 11, 57XX step 35 */ 2328 /* 2329 * Configure mbuf pool watermarks. New broadcom docs strongly 2330 * recommend these. 2331 */ 2332 if (BGE_IS_5717_PLUS(sc)) { 2333 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2334 if (ifp->if_mtu > ETHERMTU) { 2335 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2336 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2337 } else { 2338 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2339 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2340 } 2341 } else if (BGE_IS_5705_PLUS(sc)) { 2342 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2343 2344 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2345 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2346 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2347 } else { 2348 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2350 } 2351 } else { 2352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2354 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2355 } 2356 2357 /* 57XX step 36 */ 2358 /* Configure DMA resource watermarks */ 2359 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2360 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2361 2362 /* 5718 step 13, 57XX step 38 */ 2363 /* Enable buffer manager */ 2364 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2365 /* 2366 * Change the arbitration algorithm of TXMBUF read request to 2367 * round-robin instead of priority based for BCM5719. When 2368 * TXFIFO is almost empty, RDMA will hold its request until 2369 * TXFIFO is not almost empty. 2370 */ 2371 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2372 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2373 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2374 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2375 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2376 val |= BGE_BMANMODE_LOMBUF_ATTN; 2377 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2378 2379 /* 57XX step 39 */ 2380 /* Poll for buffer manager start indication */ 2381 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2382 DELAY(10); 2383 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2384 break; 2385 } 2386 2387 if (i == BGE_TIMEOUT * 2) { 2388 aprint_error_dev(sc->bge_dev, 2389 "buffer manager failed to start\n"); 2390 return ENXIO; 2391 } 2392 2393 /* 57XX step 40 */ 2394 /* Enable flow-through queues */ 2395 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2396 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2397 2398 /* Wait until queue initialization is complete */ 2399 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2400 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2401 break; 2402 DELAY(10); 2403 } 2404 2405 if (i == BGE_TIMEOUT * 2) { 2406 aprint_error_dev(sc->bge_dev, 2407 "flow-through queue init failed\n"); 2408 return ENXIO; 2409 } 2410 2411 /* 2412 * Summary of rings supported by the controller: 2413 * 2414 * Standard Receive Producer Ring 2415 * - This ring is used to feed receive buffers for "standard" 2416 * sized frames (typically 1536 bytes) to the controller. 2417 * 2418 * Jumbo Receive Producer Ring 2419 * - This ring is used to feed receive buffers for jumbo sized 2420 * frames (i.e. anything bigger than the "standard" frames) 2421 * to the controller. 2422 * 2423 * Mini Receive Producer Ring 2424 * - This ring is used to feed receive buffers for "mini" 2425 * sized frames to the controller. 2426 * - This feature required external memory for the controller 2427 * but was never used in a production system. Should always 2428 * be disabled. 2429 * 2430 * Receive Return Ring 2431 * - After the controller has placed an incoming frame into a 2432 * receive buffer that buffer is moved into a receive return 2433 * ring. The driver is then responsible to passing the 2434 * buffer up to the stack. Many versions of the controller 2435 * support multiple RR rings. 2436 * 2437 * Send Ring 2438 * - This ring is used for outgoing frames. Many versions of 2439 * the controller support multiple send rings. 2440 */ 2441 2442 /* 5718 step 15, 57XX step 41 */ 2443 /* Initialize the standard RX ring control block */ 2444 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2445 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2446 /* 5718 step 16 */ 2447 if (BGE_IS_57765_PLUS(sc)) { 2448 /* 2449 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2450 * Bits 15-2 : Maximum RX frame size 2451 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2452 * Bit 0 : Reserved 2453 */ 2454 rcb->bge_maxlen_flags = 2455 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2456 } else if (BGE_IS_5705_PLUS(sc)) { 2457 /* 2458 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2459 * Bits 15-2 : Reserved (should be 0) 2460 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2461 * Bit 0 : Reserved 2462 */ 2463 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2464 } else { 2465 /* 2466 * Ring size is always XXX entries 2467 * Bits 31-16: Maximum RX frame size 2468 * Bits 15-2 : Reserved (should be 0) 2469 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2470 * Bit 0 : Reserved 2471 */ 2472 rcb->bge_maxlen_flags = 2473 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2474 } 2475 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2476 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2477 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2478 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2479 else 2480 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2481 /* Write the standard receive producer ring control block. */ 2482 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2483 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2484 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2485 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2486 2487 /* Reset the standard receive producer ring producer index. */ 2488 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2489 2490 /* 57XX step 42 */ 2491 /* 2492 * Initialize the jumbo RX ring control block 2493 * We set the 'ring disabled' bit in the flags 2494 * field until we're actually ready to start 2495 * using this ring (i.e. once we set the MTU 2496 * high enough to require it). 2497 */ 2498 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2499 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2500 BGE_HOSTADDR(rcb->bge_hostaddr, 2501 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2502 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2503 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2504 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2505 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2506 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2507 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2508 else 2509 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2510 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2511 rcb->bge_hostaddr.bge_addr_hi); 2512 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2513 rcb->bge_hostaddr.bge_addr_lo); 2514 /* Program the jumbo receive producer ring RCB parameters. */ 2515 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2516 rcb->bge_maxlen_flags); 2517 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2518 /* Reset the jumbo receive producer ring producer index. */ 2519 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2520 } 2521 2522 /* 57XX step 43 */ 2523 /* Disable the mini receive producer ring RCB. */ 2524 if (BGE_IS_5700_FAMILY(sc)) { 2525 /* Set up dummy disabled mini ring RCB */ 2526 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2527 rcb->bge_maxlen_flags = 2528 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2529 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2530 rcb->bge_maxlen_flags); 2531 /* Reset the mini receive producer ring producer index. */ 2532 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2533 2534 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2535 offsetof(struct bge_ring_data, bge_info), 2536 sizeof (struct bge_gib), 2537 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2538 } 2539 2540 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2542 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2543 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2544 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2545 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2546 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2547 } 2548 /* 5718 step 14, 57XX step 44 */ 2549 /* 2550 * The BD ring replenish thresholds control how often the 2551 * hardware fetches new BD's from the producer rings in host 2552 * memory. Setting the value too low on a busy system can 2553 * starve the hardware and recue the throughpout. 2554 * 2555 * Set the BD ring replenish thresholds. The recommended 2556 * values are 1/8th the number of descriptors allocated to 2557 * each ring, but since we try to avoid filling the entire 2558 * ring we set these to the minimal value of 8. This needs to 2559 * be done on several of the supported chip revisions anyway, 2560 * to work around HW bugs. 2561 */ 2562 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2563 if (BGE_IS_JUMBO_CAPABLE(sc)) 2564 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2565 2566 /* 5718 step 18 */ 2567 if (BGE_IS_5717_PLUS(sc)) { 2568 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2569 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2570 } 2571 2572 /* 57XX step 45 */ 2573 /* 2574 * Disable all send rings by setting the 'ring disabled' bit 2575 * in the flags field of all the TX send ring control blocks, 2576 * located in NIC memory. 2577 */ 2578 if (BGE_IS_5700_FAMILY(sc)) { 2579 /* 5700 to 5704 had 16 send rings. */ 2580 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2581 } else if (BGE_IS_5717_PLUS(sc)) { 2582 limit = BGE_TX_RINGS_5717_MAX; 2583 } else if (BGE_IS_57765_FAMILY(sc)) { 2584 limit = BGE_TX_RINGS_57765_MAX; 2585 } else 2586 limit = 1; 2587 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2588 for (i = 0; i < limit; i++) { 2589 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2590 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2591 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2592 rcb_addr += sizeof(struct bge_rcb); 2593 } 2594 2595 /* 57XX step 46 and 47 */ 2596 /* Configure send ring RCB 0 (we use only the first ring) */ 2597 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2598 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2599 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2600 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2601 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2602 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2603 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2604 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2605 else 2606 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2607 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2608 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2609 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2610 2611 /* 57XX step 48 */ 2612 /* 2613 * Disable all receive return rings by setting the 2614 * 'ring diabled' bit in the flags field of all the receive 2615 * return ring control blocks, located in NIC memory. 2616 */ 2617 if (BGE_IS_5717_PLUS(sc)) { 2618 /* Should be 17, use 16 until we get an SRAM map. */ 2619 limit = 16; 2620 } else if (BGE_IS_5700_FAMILY(sc)) 2621 limit = BGE_RX_RINGS_MAX; 2622 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2623 BGE_IS_57765_FAMILY(sc)) 2624 limit = 4; 2625 else 2626 limit = 1; 2627 /* Disable all receive return rings */ 2628 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2629 for (i = 0; i < limit; i++) { 2630 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2631 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2632 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2633 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2634 BGE_RCB_FLAG_RING_DISABLED)); 2635 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2636 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2637 (i * (sizeof(uint64_t))), 0); 2638 rcb_addr += sizeof(struct bge_rcb); 2639 } 2640 2641 /* 57XX step 49 */ 2642 /* 2643 * Set up receive return ring 0. Note that the NIC address 2644 * for RX return rings is 0x0. The return rings live entirely 2645 * within the host, so the nicaddr field in the RCB isn't used. 2646 */ 2647 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2648 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2649 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2650 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2651 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2652 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2653 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2654 2655 /* 5718 step 24, 57XX step 53 */ 2656 /* Set random backoff seed for TX */ 2657 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2658 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2659 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2660 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2661 BGE_TX_BACKOFF_SEED_MASK); 2662 2663 /* 5718 step 26, 57XX step 55 */ 2664 /* Set inter-packet gap */ 2665 val = 0x2620; 2666 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2667 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2668 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2669 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2670 2671 /* 5718 step 27, 57XX step 56 */ 2672 /* 2673 * Specify which ring to use for packets that don't match 2674 * any RX rules. 2675 */ 2676 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2677 2678 /* 5718 step 28, 57XX step 57 */ 2679 /* 2680 * Configure number of RX lists. One interrupt distribution 2681 * list, sixteen active lists, one bad frames class. 2682 */ 2683 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2684 2685 /* 5718 step 29, 57XX step 58 */ 2686 /* Inialize RX list placement stats mask. */ 2687 if (BGE_IS_575X_PLUS(sc)) { 2688 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2689 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2690 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2691 } else 2692 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2693 2694 /* 5718 step 30, 57XX step 59 */ 2695 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2696 2697 /* 5718 step 33, 57XX step 62 */ 2698 /* Disable host coalescing until we get it set up */ 2699 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2700 2701 /* 5718 step 34, 57XX step 63 */ 2702 /* Poll to make sure it's shut down. */ 2703 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2704 DELAY(10); 2705 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2706 break; 2707 } 2708 2709 if (i == BGE_TIMEOUT * 2) { 2710 aprint_error_dev(sc->bge_dev, 2711 "host coalescing engine failed to idle\n"); 2712 return ENXIO; 2713 } 2714 2715 /* 5718 step 35, 36, 37 */ 2716 /* Set up host coalescing defaults */ 2717 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2718 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2719 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2720 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2721 if (!(BGE_IS_5705_PLUS(sc))) { 2722 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2723 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2724 } 2725 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2726 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2727 2728 /* Set up address of statistics block */ 2729 if (BGE_IS_5700_FAMILY(sc)) { 2730 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2731 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2732 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2733 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2734 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2735 } 2736 2737 /* 5718 step 38 */ 2738 /* Set up address of status block */ 2739 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2740 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2741 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2742 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2743 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2744 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2745 2746 /* Set up status block size. */ 2747 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2748 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2749 val = BGE_STATBLKSZ_FULL; 2750 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2751 } else { 2752 val = BGE_STATBLKSZ_32BYTE; 2753 bzero(&sc->bge_rdata->bge_status_block, 32); 2754 } 2755 2756 /* 5718 step 39, 57XX step 73 */ 2757 /* Turn on host coalescing state machine */ 2758 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2759 2760 /* 5718 step 40, 57XX step 74 */ 2761 /* Turn on RX BD completion state machine and enable attentions */ 2762 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2763 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2764 2765 /* 5718 step 41, 57XX step 75 */ 2766 /* Turn on RX list placement state machine */ 2767 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2768 2769 /* 57XX step 76 */ 2770 /* Turn on RX list selector state machine. */ 2771 if (!(BGE_IS_5705_PLUS(sc))) 2772 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2773 2774 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2775 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2776 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2777 BGE_MACMODE_FRMHDR_DMA_ENB; 2778 2779 if (sc->bge_flags & BGEF_FIBER_TBI) 2780 val |= BGE_PORTMODE_TBI; 2781 else if (sc->bge_flags & BGEF_FIBER_MII) 2782 val |= BGE_PORTMODE_GMII; 2783 else 2784 val |= BGE_PORTMODE_MII; 2785 2786 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2787 /* Allow APE to send/receive frames. */ 2788 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2789 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2790 2791 /* Turn on DMA, clear stats */ 2792 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2793 /* 5718 step 44 */ 2794 DELAY(40); 2795 2796 /* 5718 step 45, 57XX step 79 */ 2797 /* Set misc. local control, enable interrupts on attentions */ 2798 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2799 if (BGE_IS_5717_PLUS(sc)) { 2800 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2801 /* 5718 step 46 */ 2802 DELAY(100); 2803 } 2804 2805 /* 57XX step 81 */ 2806 /* Turn on DMA completion state machine */ 2807 if (!(BGE_IS_5705_PLUS(sc))) 2808 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2809 2810 /* 5718 step 47, 57XX step 82 */ 2811 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2812 2813 /* 5718 step 48 */ 2814 /* Enable host coalescing bug fix. */ 2815 if (BGE_IS_5755_PLUS(sc)) 2816 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2817 2818 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2819 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2820 2821 /* Turn on write DMA state machine */ 2822 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2823 /* 5718 step 49 */ 2824 DELAY(40); 2825 2826 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2827 2828 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2829 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2830 2831 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2832 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2833 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2834 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2835 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2836 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2837 2838 if (sc->bge_flags & BGEF_PCIE) 2839 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2840 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2841 if (ifp->if_mtu <= ETHERMTU) 2842 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2843 } 2844 if (sc->bge_flags & BGEF_TSO) { 2845 val |= BGE_RDMAMODE_TSO4_ENABLE; 2846 if (BGE_IS_5717_PLUS(sc)) 2847 val |= BGE_RDMAMODE_TSO6_ENABLE; 2848 } 2849 2850 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2851 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2852 BGE_RDMAMODE_H2BNC_VLAN_DET; 2853 /* 2854 * Allow multiple outstanding read requests from 2855 * non-LSO read DMA engine. 2856 */ 2857 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2858 } 2859 2860 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2861 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2862 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2863 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2864 BGE_IS_57765_PLUS(sc)) { 2865 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2866 /* 2867 * Adjust tx margin to prevent TX data corruption and 2868 * fix internal FIFO overflow. 2869 */ 2870 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2871 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2872 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2873 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2874 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2875 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2876 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2877 } 2878 /* 2879 * Enable fix for read DMA FIFO overruns. 2880 * The fix is to limit the number of RX BDs 2881 * the hardware would fetch at a fime. 2882 */ 2883 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2884 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2885 } 2886 2887 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2888 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2889 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2890 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2891 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2892 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2893 /* 2894 * Allow 4KB burst length reads for non-LSO frames. 2895 * Enable 512B burst length reads for buffer descriptors. 2896 */ 2897 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2898 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2899 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2900 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2901 } 2902 /* Turn on read DMA state machine */ 2903 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2904 /* 5718 step 52 */ 2905 delay(40); 2906 2907 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2908 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2909 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2910 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2911 if ((val & 0xFFFF) > BGE_FRAMELEN) 2912 break; 2913 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2914 break; 2915 } 2916 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2917 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2918 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2919 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2920 else 2921 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2922 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2923 } 2924 } 2925 2926 /* 5718 step 56, 57XX step 84 */ 2927 /* Turn on RX data completion state machine */ 2928 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2929 2930 /* Turn on RX data and RX BD initiator state machine */ 2931 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2932 2933 /* 57XX step 85 */ 2934 /* Turn on Mbuf cluster free state machine */ 2935 if (!BGE_IS_5705_PLUS(sc)) 2936 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2937 2938 /* 5718 step 57, 57XX step 86 */ 2939 /* Turn on send data completion state machine */ 2940 val = BGE_SDCMODE_ENABLE; 2941 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2942 val |= BGE_SDCMODE_CDELAY; 2943 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2944 2945 /* 5718 step 58 */ 2946 /* Turn on send BD completion state machine */ 2947 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2948 2949 /* 57XX step 88 */ 2950 /* Turn on RX BD initiator state machine */ 2951 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2952 2953 /* 5718 step 60, 57XX step 90 */ 2954 /* Turn on send data initiator state machine */ 2955 if (sc->bge_flags & BGEF_TSO) { 2956 /* XXX: magic value from Linux driver */ 2957 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2958 BGE_SDIMODE_HW_LSO_PRE_DMA); 2959 } else 2960 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2961 2962 /* 5718 step 61, 57XX step 91 */ 2963 /* Turn on send BD initiator state machine */ 2964 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2965 2966 /* 5718 step 62, 57XX step 92 */ 2967 /* Turn on send BD selector state machine */ 2968 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2969 2970 /* 5718 step 31, 57XX step 60 */ 2971 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2972 /* 5718 step 32, 57XX step 61 */ 2973 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2974 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2975 2976 /* ack/clear link change events */ 2977 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2978 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2979 BGE_MACSTAT_LINK_CHANGED); 2980 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2981 2982 /* 2983 * Enable attention when the link has changed state for 2984 * devices that use auto polling. 2985 */ 2986 if (sc->bge_flags & BGEF_FIBER_TBI) { 2987 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2988 } else { 2989 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 2990 mimode = BGE_MIMODE_500KHZ_CONST; 2991 else 2992 mimode = BGE_MIMODE_BASE; 2993 /* 5718 step 68. 5718 step 69 (optionally). */ 2994 if (BGE_IS_5700_FAMILY(sc) || 2995 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 2996 mimode |= BGE_MIMODE_AUTOPOLL; 2997 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2998 } 2999 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3000 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3001 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3002 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3003 BGE_EVTENB_MI_INTERRUPT); 3004 } 3005 3006 /* 3007 * Clear any pending link state attention. 3008 * Otherwise some link state change events may be lost until attention 3009 * is cleared by bge_intr() -> bge_link_upd() sequence. 3010 * It's not necessary on newer BCM chips - perhaps enabling link 3011 * state change attentions implies clearing pending attention. 3012 */ 3013 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3014 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3015 BGE_MACSTAT_LINK_CHANGED); 3016 3017 /* Enable link state change attentions. */ 3018 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3019 3020 return 0; 3021 } 3022 3023 static const struct bge_revision * 3024 bge_lookup_rev(uint32_t chipid) 3025 { 3026 const struct bge_revision *br; 3027 3028 for (br = bge_revisions; br->br_name != NULL; br++) { 3029 if (br->br_chipid == chipid) 3030 return br; 3031 } 3032 3033 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3034 if (br->br_chipid == BGE_ASICREV(chipid)) 3035 return br; 3036 } 3037 3038 return NULL; 3039 } 3040 3041 static const struct bge_product * 3042 bge_lookup(const struct pci_attach_args *pa) 3043 { 3044 const struct bge_product *bp; 3045 3046 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3047 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3048 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3049 return bp; 3050 } 3051 3052 return NULL; 3053 } 3054 3055 static uint32_t 3056 bge_chipid(const struct pci_attach_args *pa) 3057 { 3058 uint32_t id; 3059 3060 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3061 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3062 3063 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3064 switch (PCI_PRODUCT(pa->pa_id)) { 3065 case PCI_PRODUCT_BROADCOM_BCM5717: 3066 case PCI_PRODUCT_BROADCOM_BCM5718: 3067 case PCI_PRODUCT_BROADCOM_BCM5719: 3068 case PCI_PRODUCT_BROADCOM_BCM5720: 3069 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3070 BGE_PCI_GEN2_PRODID_ASICREV); 3071 break; 3072 case PCI_PRODUCT_BROADCOM_BCM57761: 3073 case PCI_PRODUCT_BROADCOM_BCM57762: 3074 case PCI_PRODUCT_BROADCOM_BCM57765: 3075 case PCI_PRODUCT_BROADCOM_BCM57766: 3076 case PCI_PRODUCT_BROADCOM_BCM57781: 3077 case PCI_PRODUCT_BROADCOM_BCM57782: 3078 case PCI_PRODUCT_BROADCOM_BCM57785: 3079 case PCI_PRODUCT_BROADCOM_BCM57786: 3080 case PCI_PRODUCT_BROADCOM_BCM57791: 3081 case PCI_PRODUCT_BROADCOM_BCM57795: 3082 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3083 BGE_PCI_GEN15_PRODID_ASICREV); 3084 break; 3085 default: 3086 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3087 BGE_PCI_PRODID_ASICREV); 3088 break; 3089 } 3090 } 3091 3092 return id; 3093 } 3094 3095 /* 3096 * Return true if MSI can be used with this device. 3097 */ 3098 static int 3099 bge_can_use_msi(struct bge_softc *sc) 3100 { 3101 int can_use_msi = 0; 3102 3103 switch (BGE_ASICREV(sc->bge_chipid)) { 3104 case BGE_ASICREV_BCM5714_A0: 3105 case BGE_ASICREV_BCM5714: 3106 /* 3107 * Apparently, MSI doesn't work when these chips are 3108 * configured in single-port mode. 3109 */ 3110 break; 3111 case BGE_ASICREV_BCM5750: 3112 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3113 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3114 can_use_msi = 1; 3115 break; 3116 default: 3117 if (BGE_IS_575X_PLUS(sc)) 3118 can_use_msi = 1; 3119 } 3120 return (can_use_msi); 3121 } 3122 3123 /* 3124 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3125 * against our list and return its name if we find a match. Note 3126 * that since the Broadcom controller contains VPD support, we 3127 * can get the device name string from the controller itself instead 3128 * of the compiled-in string. This is a little slow, but it guarantees 3129 * we'll always announce the right product name. 3130 */ 3131 static int 3132 bge_probe(device_t parent, cfdata_t match, void *aux) 3133 { 3134 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3135 3136 if (bge_lookup(pa) != NULL) 3137 return 1; 3138 3139 return 0; 3140 } 3141 3142 static void 3143 bge_attach(device_t parent, device_t self, void *aux) 3144 { 3145 struct bge_softc *sc = device_private(self); 3146 struct pci_attach_args *pa = aux; 3147 prop_dictionary_t dict; 3148 const struct bge_product *bp; 3149 const struct bge_revision *br; 3150 pci_chipset_tag_t pc; 3151 const char *intrstr = NULL; 3152 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3153 uint32_t command; 3154 struct ifnet *ifp; 3155 uint32_t misccfg, mimode; 3156 void * kva; 3157 u_char eaddr[ETHER_ADDR_LEN]; 3158 pcireg_t memtype, subid, reg; 3159 bus_addr_t memaddr; 3160 uint32_t pm_ctl; 3161 bool no_seeprom; 3162 int capmask; 3163 int mii_flags; 3164 int map_flags; 3165 char intrbuf[PCI_INTRSTR_LEN]; 3166 3167 bp = bge_lookup(pa); 3168 KASSERT(bp != NULL); 3169 3170 sc->sc_pc = pa->pa_pc; 3171 sc->sc_pcitag = pa->pa_tag; 3172 sc->bge_dev = self; 3173 3174 sc->bge_pa = *pa; 3175 pc = sc->sc_pc; 3176 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3177 3178 aprint_naive(": Ethernet controller\n"); 3179 aprint_normal(": %s Ethernet\n", bp->bp_name); 3180 3181 /* 3182 * Map control/status registers. 3183 */ 3184 DPRINTFN(5, ("Map control/status regs\n")); 3185 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3186 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3187 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3188 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3189 3190 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3191 aprint_error_dev(sc->bge_dev, 3192 "failed to enable memory mapping!\n"); 3193 return; 3194 } 3195 3196 DPRINTFN(5, ("pci_mem_find\n")); 3197 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3198 switch (memtype) { 3199 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3200 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3201 #if 0 3202 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3203 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3204 &memaddr, &sc->bge_bsize) == 0) 3205 break; 3206 #else 3207 /* 3208 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3209 * system get NMI on boot (PR#48451). This problem might not be 3210 * the driver's bug but our PCI common part's bug. Until we 3211 * find a real reason, we ignore the prefetchable bit. 3212 */ 3213 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3214 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3215 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3216 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3217 map_flags, &sc->bge_bhandle) == 0) { 3218 sc->bge_btag = pa->pa_memt; 3219 break; 3220 } 3221 } 3222 #endif 3223 /* FALLTHROUGH */ 3224 default: 3225 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3226 return; 3227 } 3228 3229 /* Save various chip information. */ 3230 sc->bge_chipid = bge_chipid(pa); 3231 sc->bge_phy_addr = bge_phy_addr(sc); 3232 3233 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3234 &sc->bge_pciecap, NULL) != 0) { 3235 /* PCIe */ 3236 sc->bge_flags |= BGEF_PCIE; 3237 /* Extract supported maximum payload size. */ 3238 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3239 sc->bge_pciecap + PCIE_DCAP); 3240 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3241 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3242 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3243 sc->bge_expmrq = 2048; 3244 else 3245 sc->bge_expmrq = 4096; 3246 bge_set_max_readrq(sc); 3247 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3248 /* PCIe without PCIe cap */ 3249 sc->bge_flags |= BGEF_PCIE; 3250 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3251 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3252 /* PCI-X */ 3253 sc->bge_flags |= BGEF_PCIX; 3254 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3255 &sc->bge_pcixcap, NULL) == 0) 3256 aprint_error_dev(sc->bge_dev, 3257 "unable to find PCIX capability\n"); 3258 } 3259 3260 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3261 /* 3262 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3263 * can clobber the chip's PCI config-space power control 3264 * registers, leaving the card in D3 powersave state. We do 3265 * not have memory-mapped registers in this state, so force 3266 * device into D0 state before starting initialization. 3267 */ 3268 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3269 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 3270 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3271 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3272 DELAY(1000); /* 27 usec is allegedly sufficent */ 3273 } 3274 3275 /* Save chipset family. */ 3276 switch (BGE_ASICREV(sc->bge_chipid)) { 3277 case BGE_ASICREV_BCM5717: 3278 case BGE_ASICREV_BCM5719: 3279 case BGE_ASICREV_BCM5720: 3280 sc->bge_flags |= BGEF_5717_PLUS; 3281 /* FALLTHROUGH */ 3282 case BGE_ASICREV_BCM57765: 3283 case BGE_ASICREV_BCM57766: 3284 if (!BGE_IS_5717_PLUS(sc)) 3285 sc->bge_flags |= BGEF_57765_FAMILY; 3286 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3287 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3288 /* Jumbo frame on BCM5719 A0 does not work. */ 3289 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3290 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3291 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3292 break; 3293 case BGE_ASICREV_BCM5755: 3294 case BGE_ASICREV_BCM5761: 3295 case BGE_ASICREV_BCM5784: 3296 case BGE_ASICREV_BCM5785: 3297 case BGE_ASICREV_BCM5787: 3298 case BGE_ASICREV_BCM57780: 3299 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3300 break; 3301 case BGE_ASICREV_BCM5700: 3302 case BGE_ASICREV_BCM5701: 3303 case BGE_ASICREV_BCM5703: 3304 case BGE_ASICREV_BCM5704: 3305 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3306 break; 3307 case BGE_ASICREV_BCM5714_A0: 3308 case BGE_ASICREV_BCM5780: 3309 case BGE_ASICREV_BCM5714: 3310 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3311 /* FALLTHROUGH */ 3312 case BGE_ASICREV_BCM5750: 3313 case BGE_ASICREV_BCM5752: 3314 case BGE_ASICREV_BCM5906: 3315 sc->bge_flags |= BGEF_575X_PLUS; 3316 /* FALLTHROUGH */ 3317 case BGE_ASICREV_BCM5705: 3318 sc->bge_flags |= BGEF_5705_PLUS; 3319 break; 3320 } 3321 3322 /* Identify chips with APE processor. */ 3323 switch (BGE_ASICREV(sc->bge_chipid)) { 3324 case BGE_ASICREV_BCM5717: 3325 case BGE_ASICREV_BCM5719: 3326 case BGE_ASICREV_BCM5720: 3327 case BGE_ASICREV_BCM5761: 3328 sc->bge_flags |= BGEF_APE; 3329 break; 3330 } 3331 3332 /* 3333 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3334 * not actually a MAC controller bug but an issue with the embedded 3335 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3336 */ 3337 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3338 sc->bge_flags |= BGEF_40BIT_BUG; 3339 3340 /* Chips with APE need BAR2 access for APE registers/memory. */ 3341 if ((sc->bge_flags & BGEF_APE) != 0) { 3342 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3343 #if 0 3344 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3345 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3346 &sc->bge_apesize)) { 3347 aprint_error_dev(sc->bge_dev, 3348 "couldn't map BAR2 memory\n"); 3349 return; 3350 } 3351 #else 3352 /* 3353 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3354 * system get NMI on boot (PR#48451). This problem might not be 3355 * the driver's bug but our PCI common part's bug. Until we 3356 * find a real reason, we ignore the prefetchable bit. 3357 */ 3358 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3359 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3360 aprint_error_dev(sc->bge_dev, 3361 "couldn't map BAR2 memory\n"); 3362 return; 3363 } 3364 3365 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3366 if (bus_space_map(pa->pa_memt, memaddr, 3367 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3368 aprint_error_dev(sc->bge_dev, 3369 "couldn't map BAR2 memory\n"); 3370 return; 3371 } 3372 sc->bge_apetag = pa->pa_memt; 3373 #endif 3374 3375 /* Enable APE register/memory access by host driver. */ 3376 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3377 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3378 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3379 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3380 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3381 3382 bge_ape_lock_init(sc); 3383 bge_ape_read_fw_ver(sc); 3384 } 3385 3386 /* Identify the chips that use an CPMU. */ 3387 if (BGE_IS_5717_PLUS(sc) || 3388 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3389 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3390 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3391 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3392 sc->bge_flags |= BGEF_CPMU_PRESENT; 3393 3394 /* Set MI_MODE */ 3395 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3396 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3397 mimode |= BGE_MIMODE_500KHZ_CONST; 3398 else 3399 mimode |= BGE_MIMODE_BASE; 3400 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3401 3402 /* 3403 * When using the BCM5701 in PCI-X mode, data corruption has 3404 * been observed in the first few bytes of some received packets. 3405 * Aligning the packet buffer in memory eliminates the corruption. 3406 * Unfortunately, this misaligns the packet payloads. On platforms 3407 * which do not support unaligned accesses, we will realign the 3408 * payloads by copying the received packets. 3409 */ 3410 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3411 sc->bge_flags & BGEF_PCIX) 3412 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3413 3414 if (BGE_IS_5700_FAMILY(sc)) 3415 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3416 3417 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3418 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3419 3420 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3421 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3422 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3423 sc->bge_flags |= BGEF_IS_5788; 3424 3425 /* 3426 * Some controllers seem to require a special firmware to use 3427 * TSO. But the firmware is not available to FreeBSD and Linux 3428 * claims that the TSO performed by the firmware is slower than 3429 * hardware based TSO. Moreover the firmware based TSO has one 3430 * known bug which can't handle TSO if ethernet header + IP/TCP 3431 * header is greater than 80 bytes. The workaround for the TSO 3432 * bug exist but it seems it's too expensive than not using 3433 * TSO at all. Some hardwares also have the TSO bug so limit 3434 * the TSO to the controllers that are not affected TSO issues 3435 * (e.g. 5755 or higher). 3436 */ 3437 if (BGE_IS_5755_PLUS(sc)) { 3438 /* 3439 * BCM5754 and BCM5787 shares the same ASIC id so 3440 * explicit device id check is required. 3441 */ 3442 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3443 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3444 sc->bge_flags |= BGEF_TSO; 3445 /* TSO on BCM5719 A0 does not work. */ 3446 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3447 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3448 sc->bge_flags &= ~BGEF_TSO; 3449 } 3450 3451 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3452 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3453 (misccfg == 0x4000 || misccfg == 0x8000)) || 3454 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3455 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3456 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3457 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3458 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3459 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3460 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3461 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3462 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3463 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3464 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3465 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3466 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3467 /* These chips are 10/100 only. */ 3468 capmask &= ~BMSR_EXTSTAT; 3469 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3470 } 3471 3472 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3473 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3474 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3475 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3476 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3477 3478 /* Set various PHY bug flags. */ 3479 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3480 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3481 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3482 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3483 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3484 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3485 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3486 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3487 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3488 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3489 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3490 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3491 if (BGE_IS_5705_PLUS(sc) && 3492 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3493 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3494 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3495 !BGE_IS_57765_PLUS(sc)) { 3496 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3497 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3498 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3499 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3500 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3501 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3502 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3503 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3504 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3505 } else 3506 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3507 } 3508 3509 /* 3510 * SEEPROM check. 3511 * First check if firmware knows we do not have SEEPROM. 3512 */ 3513 if (prop_dictionary_get_bool(device_properties(self), 3514 "without-seeprom", &no_seeprom) && no_seeprom) 3515 sc->bge_flags |= BGEF_NO_EEPROM; 3516 3517 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3518 sc->bge_flags |= BGEF_NO_EEPROM; 3519 3520 /* Now check the 'ROM failed' bit on the RX CPU */ 3521 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3522 sc->bge_flags |= BGEF_NO_EEPROM; 3523 3524 sc->bge_asf_mode = 0; 3525 /* No ASF if APE present. */ 3526 if ((sc->bge_flags & BGEF_APE) == 0) { 3527 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3528 BGE_SRAM_DATA_SIG_MAGIC)) { 3529 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3530 BGE_HWCFG_ASF) { 3531 sc->bge_asf_mode |= ASF_ENABLE; 3532 sc->bge_asf_mode |= ASF_STACKUP; 3533 if (BGE_IS_575X_PLUS(sc)) 3534 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3535 } 3536 } 3537 } 3538 3539 int counts[PCI_INTR_TYPE_SIZE] = { 3540 [PCI_INTR_TYPE_INTX] = 1, 3541 [PCI_INTR_TYPE_MSI] = 1, 3542 [PCI_INTR_TYPE_MSIX] = 1, 3543 }; 3544 int max_type = PCI_INTR_TYPE_MSIX; 3545 3546 if (!bge_can_use_msi(sc)) { 3547 /* MSI broken, allow only INTx */ 3548 max_type = PCI_INTR_TYPE_INTX; 3549 } 3550 3551 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3552 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3553 return; 3554 } 3555 3556 DPRINTFN(5, ("pci_intr_string\n")); 3557 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3558 sizeof(intrbuf)); 3559 DPRINTFN(5, ("pci_intr_establish\n")); 3560 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3561 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3562 if (sc->bge_intrhand == NULL) { 3563 pci_intr_release(pc, sc->bge_pihp, 1); 3564 sc->bge_pihp = NULL; 3565 3566 aprint_error_dev(self, "couldn't establish interrupt"); 3567 if (intrstr != NULL) 3568 aprint_error(" at %s", intrstr); 3569 aprint_error("\n"); 3570 return; 3571 } 3572 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3573 3574 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3575 case PCI_INTR_TYPE_MSIX: 3576 case PCI_INTR_TYPE_MSI: 3577 KASSERT(bge_can_use_msi(sc)); 3578 sc->bge_flags |= BGEF_MSI; 3579 break; 3580 default: 3581 /* nothing to do */ 3582 break; 3583 } 3584 3585 /* 3586 * All controllers except BCM5700 supports tagged status but 3587 * we use tagged status only for MSI case on BCM5717. Otherwise 3588 * MSI on BCM5717 does not work. 3589 */ 3590 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3591 sc->bge_flags |= BGEF_TAGGED_STATUS; 3592 3593 /* 3594 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3595 * lock in bge_reset(). 3596 */ 3597 CSR_WRITE_4(sc, BGE_EE_ADDR, 3598 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3599 delay(1000); 3600 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3601 3602 bge_stop_fw(sc); 3603 bge_sig_pre_reset(sc, BGE_RESET_START); 3604 if (bge_reset(sc)) 3605 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3606 3607 /* 3608 * Read the hardware config word in the first 32k of NIC internal 3609 * memory, or fall back to the config word in the EEPROM. 3610 * Note: on some BCM5700 cards, this value appears to be unset. 3611 */ 3612 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3613 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3614 BGE_SRAM_DATA_SIG_MAGIC) { 3615 uint32_t tmp; 3616 3617 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3618 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3619 BGE_SRAM_DATA_VER_SHIFT; 3620 if ((0 < tmp) && (tmp < 0x100)) 3621 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3622 if (sc->bge_flags & BGEF_PCIE) 3623 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3624 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3625 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3626 if (BGE_IS_5717_PLUS(sc)) 3627 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3628 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3629 bge_read_eeprom(sc, (void *)&hwcfg, 3630 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3631 hwcfg = be32toh(hwcfg); 3632 } 3633 aprint_normal_dev(sc->bge_dev, 3634 "HW config %08x, %08x, %08x, %08x %08x\n", 3635 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3636 3637 bge_sig_legacy(sc, BGE_RESET_START); 3638 bge_sig_post_reset(sc, BGE_RESET_START); 3639 3640 if (bge_chipinit(sc)) { 3641 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3642 bge_release_resources(sc); 3643 return; 3644 } 3645 3646 /* 3647 * Get station address from the EEPROM. 3648 */ 3649 if (bge_get_eaddr(sc, eaddr)) { 3650 aprint_error_dev(sc->bge_dev, 3651 "failed to read station address\n"); 3652 bge_release_resources(sc); 3653 return; 3654 } 3655 3656 br = bge_lookup_rev(sc->bge_chipid); 3657 3658 if (br == NULL) { 3659 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3660 sc->bge_chipid); 3661 } else { 3662 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3663 br->br_name, sc->bge_chipid); 3664 } 3665 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3666 3667 /* Allocate the general information block and ring buffers. */ 3668 if (pci_dma64_available(pa)) { 3669 sc->bge_dmatag = pa->pa_dmat64; 3670 sc->bge_dmatag32 = pa->pa_dmat; 3671 sc->bge_dma64 = true; 3672 } else { 3673 sc->bge_dmatag = pa->pa_dmat; 3674 sc->bge_dmatag32 = pa->pa_dmat; 3675 sc->bge_dma64 = false; 3676 } 3677 3678 /* 40bit DMA workaround */ 3679 if (sizeof(bus_addr_t) > 4) { 3680 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3681 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3682 3683 if (bus_dmatag_subregion(olddmatag, 0, 3684 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3685 BUS_DMA_NOWAIT) != 0) { 3686 aprint_error_dev(self, 3687 "WARNING: failed to restrict dma range," 3688 " falling back to parent bus dma range\n"); 3689 sc->bge_dmatag = olddmatag; 3690 } 3691 } 3692 } 3693 SLIST_INIT(&sc->txdma_list); 3694 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3695 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3696 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3697 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3698 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3699 return; 3700 } 3701 DPRINTFN(5, ("bus_dmamem_map\n")); 3702 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3703 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3704 BUS_DMA_NOWAIT)) { 3705 aprint_error_dev(sc->bge_dev, 3706 "can't map DMA buffers (%zu bytes)\n", 3707 sizeof(struct bge_ring_data)); 3708 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3709 sc->bge_ring_rseg); 3710 return; 3711 } 3712 DPRINTFN(5, ("bus_dmamem_create\n")); 3713 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3714 sizeof(struct bge_ring_data), 0, 3715 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3716 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3717 bus_dmamem_unmap(sc->bge_dmatag, kva, 3718 sizeof(struct bge_ring_data)); 3719 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3720 sc->bge_ring_rseg); 3721 return; 3722 } 3723 DPRINTFN(5, ("bus_dmamem_load\n")); 3724 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3725 sizeof(struct bge_ring_data), NULL, 3726 BUS_DMA_NOWAIT)) { 3727 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3728 bus_dmamem_unmap(sc->bge_dmatag, kva, 3729 sizeof(struct bge_ring_data)); 3730 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3731 sc->bge_ring_rseg); 3732 return; 3733 } 3734 3735 DPRINTFN(5, ("bzero\n")); 3736 sc->bge_rdata = (struct bge_ring_data *)kva; 3737 3738 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3739 3740 /* Try to allocate memory for jumbo buffers. */ 3741 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3742 if (bge_alloc_jumbo_mem(sc)) { 3743 aprint_error_dev(sc->bge_dev, 3744 "jumbo buffer allocation failed\n"); 3745 } else 3746 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3747 } 3748 3749 /* Set default tuneable values. */ 3750 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3751 sc->bge_rx_coal_ticks = 150; 3752 sc->bge_rx_max_coal_bds = 64; 3753 sc->bge_tx_coal_ticks = 300; 3754 sc->bge_tx_max_coal_bds = 400; 3755 if (BGE_IS_5705_PLUS(sc)) { 3756 sc->bge_tx_coal_ticks = (12 * 5); 3757 sc->bge_tx_max_coal_bds = (12 * 5); 3758 aprint_verbose_dev(sc->bge_dev, 3759 "setting short Tx thresholds\n"); 3760 } 3761 3762 if (BGE_IS_5717_PLUS(sc)) 3763 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3764 else if (BGE_IS_5705_PLUS(sc)) 3765 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3766 else 3767 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3768 3769 /* Set up ifnet structure */ 3770 ifp = &sc->ethercom.ec_if; 3771 ifp->if_softc = sc; 3772 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3773 ifp->if_ioctl = bge_ioctl; 3774 ifp->if_stop = bge_stop; 3775 ifp->if_start = bge_start; 3776 ifp->if_init = bge_init; 3777 ifp->if_watchdog = bge_watchdog; 3778 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3779 IFQ_SET_READY(&ifp->if_snd); 3780 DPRINTFN(5, ("strcpy if_xname\n")); 3781 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3782 3783 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3784 sc->ethercom.ec_if.if_capabilities |= 3785 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3786 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3787 sc->ethercom.ec_if.if_capabilities |= 3788 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3789 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3790 #endif 3791 sc->ethercom.ec_capabilities |= 3792 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3793 3794 if (sc->bge_flags & BGEF_TSO) 3795 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3796 3797 /* 3798 * Do MII setup. 3799 */ 3800 DPRINTFN(5, ("mii setup\n")); 3801 sc->bge_mii.mii_ifp = ifp; 3802 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3803 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3804 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3805 3806 /* 3807 * Figure out what sort of media we have by checking the hardware 3808 * config word. Note: on some BCM5700 cards, this value appears to be 3809 * unset. If that's the case, we have to rely on identifying the NIC 3810 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3811 * The SysKonnect SK-9D41 is a 1000baseSX card. 3812 */ 3813 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3814 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3815 if (BGE_IS_5705_PLUS(sc)) { 3816 sc->bge_flags |= BGEF_FIBER_MII; 3817 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3818 } else 3819 sc->bge_flags |= BGEF_FIBER_TBI; 3820 } 3821 3822 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3823 if (BGE_IS_JUMBO_CAPABLE(sc)) 3824 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3825 3826 /* set phyflags and chipid before mii_attach() */ 3827 dict = device_properties(self); 3828 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3829 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3830 3831 if (sc->bge_flags & BGEF_FIBER_TBI) { 3832 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3833 bge_ifmedia_sts); 3834 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3835 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 3836 0, NULL); 3837 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3838 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3839 /* Pretend the user requested this setting */ 3840 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3841 } else { 3842 /* 3843 * Do transceiver setup and tell the firmware the 3844 * driver is down so we can try to get access the 3845 * probe if ASF is running. Retry a couple of times 3846 * if we get a conflict with the ASF firmware accessing 3847 * the PHY. 3848 */ 3849 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3850 bge_asf_driver_up(sc); 3851 3852 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3853 bge_ifmedia_sts); 3854 mii_flags = MIIF_DOPAUSE; 3855 if (sc->bge_flags & BGEF_FIBER_MII) 3856 mii_flags |= MIIF_HAVEFIBER; 3857 mii_attach(sc->bge_dev, &sc->bge_mii, capmask, sc->bge_phy_addr, 3858 MII_OFFSET_ANY, mii_flags); 3859 3860 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3861 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3862 ifmedia_add(&sc->bge_mii.mii_media, 3863 IFM_ETHER|IFM_MANUAL, 0, NULL); 3864 ifmedia_set(&sc->bge_mii.mii_media, 3865 IFM_ETHER|IFM_MANUAL); 3866 } else 3867 ifmedia_set(&sc->bge_mii.mii_media, 3868 IFM_ETHER|IFM_AUTO); 3869 3870 /* 3871 * Now tell the firmware we are going up after probing the PHY 3872 */ 3873 if (sc->bge_asf_mode & ASF_STACKUP) 3874 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3875 } 3876 3877 /* 3878 * Call MI attach routine. 3879 */ 3880 DPRINTFN(5, ("if_attach\n")); 3881 if_attach(ifp); 3882 if_deferred_start_init(ifp, NULL); 3883 DPRINTFN(5, ("ether_ifattach\n")); 3884 ether_ifattach(ifp, eaddr); 3885 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3886 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3887 RND_TYPE_NET, RND_FLAG_DEFAULT); 3888 #ifdef BGE_EVENT_COUNTERS 3889 /* 3890 * Attach event counters. 3891 */ 3892 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3893 NULL, device_xname(sc->bge_dev), "intr"); 3894 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3895 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3896 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3897 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3898 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3899 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3900 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3901 NULL, device_xname(sc->bge_dev), "tx_xon"); 3902 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3903 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3904 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3905 NULL, device_xname(sc->bge_dev), "rx_xon"); 3906 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3907 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3908 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3909 NULL, device_xname(sc->bge_dev), "xoffentered"); 3910 #endif /* BGE_EVENT_COUNTERS */ 3911 DPRINTFN(5, ("callout_init\n")); 3912 callout_init(&sc->bge_timeout, 0); 3913 3914 if (pmf_device_register(self, NULL, NULL)) 3915 pmf_class_network_register(self, ifp); 3916 else 3917 aprint_error_dev(self, "couldn't establish power handler\n"); 3918 3919 bge_sysctl_init(sc); 3920 3921 #ifdef BGE_DEBUG 3922 bge_debug_info(sc); 3923 #endif 3924 } 3925 3926 /* 3927 * Stop all chip I/O so that the kernel's probe routines don't 3928 * get confused by errant DMAs when rebooting. 3929 */ 3930 static int 3931 bge_detach(device_t self, int flags __unused) 3932 { 3933 struct bge_softc *sc = device_private(self); 3934 struct ifnet *ifp = &sc->ethercom.ec_if; 3935 int s; 3936 3937 s = splnet(); 3938 /* Stop the interface. Callouts are stopped in it. */ 3939 bge_stop(ifp, 1); 3940 splx(s); 3941 3942 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3943 3944 /* Delete all remaining media. */ 3945 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3946 3947 ether_ifdetach(ifp); 3948 if_detach(ifp); 3949 3950 bge_release_resources(sc); 3951 3952 return 0; 3953 } 3954 3955 static void 3956 bge_release_resources(struct bge_softc *sc) 3957 { 3958 3959 /* Detach sysctl */ 3960 if (sc->bge_log != NULL) 3961 sysctl_teardown(&sc->bge_log); 3962 3963 #ifdef BGE_EVENT_COUNTERS 3964 /* Detach event counters. */ 3965 evcnt_detach(&sc->bge_ev_intr); 3966 evcnt_detach(&sc->bge_ev_intr_spurious); 3967 evcnt_detach(&sc->bge_ev_intr_spurious2); 3968 evcnt_detach(&sc->bge_ev_tx_xoff); 3969 evcnt_detach(&sc->bge_ev_tx_xon); 3970 evcnt_detach(&sc->bge_ev_rx_xoff); 3971 evcnt_detach(&sc->bge_ev_rx_xon); 3972 evcnt_detach(&sc->bge_ev_rx_macctl); 3973 evcnt_detach(&sc->bge_ev_xoffentered); 3974 #endif /* BGE_EVENT_COUNTERS */ 3975 3976 /* Disestablish the interrupt handler */ 3977 if (sc->bge_intrhand != NULL) { 3978 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 3979 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 3980 sc->bge_intrhand = NULL; 3981 } 3982 3983 if (sc->bge_dmatag != NULL) { 3984 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3985 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3986 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 3987 sizeof(struct bge_ring_data)); 3988 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3989 sc->bge_ring_rseg); 3990 } 3991 3992 /* Unmap the device registers */ 3993 if (sc->bge_bsize != 0) { 3994 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3995 sc->bge_bsize = 0; 3996 } 3997 3998 /* Unmap the APE registers */ 3999 if (sc->bge_apesize != 0) { 4000 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4001 sc->bge_apesize); 4002 sc->bge_apesize = 0; 4003 } 4004 } 4005 4006 static int 4007 bge_reset(struct bge_softc *sc) 4008 { 4009 uint32_t cachesize, command; 4010 uint32_t reset, mac_mode, mac_mode_mask; 4011 pcireg_t devctl, reg; 4012 int i, val; 4013 void (*write_op)(struct bge_softc *, int, int); 4014 4015 /* Make mask for BGE_MAC_MODE register. */ 4016 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4017 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4018 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4019 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4020 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4021 4022 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4023 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4024 if (sc->bge_flags & BGEF_PCIE) 4025 write_op = bge_writemem_direct; 4026 else 4027 write_op = bge_writemem_ind; 4028 } else 4029 write_op = bge_writereg_ind; 4030 4031 /* 57XX step 4 */ 4032 /* Acquire the NVM lock */ 4033 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4034 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4035 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4036 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4037 for (i = 0; i < 8000; i++) { 4038 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4039 BGE_NVRAMSWARB_GNT1) 4040 break; 4041 DELAY(20); 4042 } 4043 if (i == 8000) { 4044 printf("%s: NVRAM lock timedout!\n", 4045 device_xname(sc->bge_dev)); 4046 } 4047 } 4048 4049 /* Take APE lock when performing reset. */ 4050 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4051 4052 /* 57XX step 3 */ 4053 /* Save some important PCI state. */ 4054 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4055 /* 5718 reset step 3 */ 4056 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4057 4058 /* 5718 reset step 5, 57XX step 5b-5d */ 4059 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4060 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4061 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4062 4063 /* XXX ???: Disable fastboot on controllers that support it. */ 4064 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4065 BGE_IS_5755_PLUS(sc)) 4066 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4067 4068 /* 5718 reset step 2, 57XX step 6 */ 4069 /* 4070 * Write the magic number to SRAM at offset 0xB50. 4071 * When firmware finishes its initialization it will 4072 * write ~BGE_MAGIC_NUMBER to the same location. 4073 */ 4074 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4075 4076 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4077 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4078 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4079 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4080 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4081 } 4082 4083 /* 5718 reset step 6, 57XX step 7 */ 4084 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4085 /* 4086 * XXX: from FreeBSD/Linux; no documentation 4087 */ 4088 if (sc->bge_flags & BGEF_PCIE) { 4089 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4090 !BGE_IS_57765_PLUS(sc) && 4091 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4092 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4093 /* PCI Express 1.0 system */ 4094 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4095 BGE_PHY_PCIE_SCRAM_MODE); 4096 } 4097 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4098 /* 4099 * Prevent PCI Express link training 4100 * during global reset. 4101 */ 4102 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4103 reset |= (1 << 29); 4104 } 4105 } 4106 4107 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4108 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4109 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4110 i | BGE_VCPU_STATUS_DRV_RESET); 4111 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4112 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4113 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4114 } 4115 4116 /* 4117 * Set GPHY Power Down Override to leave GPHY 4118 * powered up in D0 uninitialized. 4119 */ 4120 if (BGE_IS_5705_PLUS(sc) && 4121 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4122 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4123 4124 /* Issue global reset */ 4125 write_op(sc, BGE_MISC_CFG, reset); 4126 4127 /* 5718 reset step 7, 57XX step 8 */ 4128 if (sc->bge_flags & BGEF_PCIE) 4129 delay(100*1000); /* too big */ 4130 else 4131 delay(1000); 4132 4133 if (sc->bge_flags & BGEF_PCIE) { 4134 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4135 DELAY(500000); 4136 /* XXX: Magic Numbers */ 4137 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4138 BGE_PCI_UNKNOWN0); 4139 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4140 BGE_PCI_UNKNOWN0, 4141 reg | (1 << 15)); 4142 } 4143 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4144 sc->bge_pciecap + PCIE_DCSR); 4145 /* Clear enable no snoop and disable relaxed ordering. */ 4146 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4147 PCIE_DCSR_ENA_NO_SNOOP); 4148 4149 /* Set PCIE max payload size to 128 for older PCIe devices */ 4150 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4151 devctl &= ~(0x00e0); 4152 /* Clear device status register. Write 1b to clear */ 4153 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4154 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4155 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4156 sc->bge_pciecap + PCIE_DCSR, devctl); 4157 bge_set_max_readrq(sc); 4158 } 4159 4160 /* From Linux: dummy read to flush PCI posted writes */ 4161 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4162 4163 /* 4164 * Reset some of the PCI state that got zapped by reset 4165 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4166 * set, too. 4167 */ 4168 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4169 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4170 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4171 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4172 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4173 (sc->bge_flags & BGEF_PCIX) != 0) 4174 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4175 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4176 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4177 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4178 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4179 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4180 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4181 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4182 4183 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4184 if (sc->bge_flags & BGEF_PCIX) { 4185 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4186 + PCIX_CMD); 4187 /* Set max memory read byte count to 2K */ 4188 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4189 reg &= ~PCIX_CMD_BYTECNT_MASK; 4190 reg |= PCIX_CMD_BCNT_2048; 4191 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4192 /* 4193 * For 5704, set max outstanding split transaction 4194 * field to 0 (0 means it supports 1 request) 4195 */ 4196 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4197 | PCIX_CMD_BYTECNT_MASK); 4198 reg |= PCIX_CMD_BCNT_2048; 4199 } 4200 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4201 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4202 } 4203 4204 /* 5718 reset step 10, 57XX step 12 */ 4205 /* Enable memory arbiter. */ 4206 if (BGE_IS_5714_FAMILY(sc)) { 4207 val = CSR_READ_4(sc, BGE_MARB_MODE); 4208 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4209 } else 4210 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4211 4212 /* XXX 5721, 5751 and 5752 */ 4213 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4214 /* Step 19: */ 4215 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4216 /* Step 20: */ 4217 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4218 } 4219 4220 /* 5718 reset step 12, 57XX step 15 and 16 */ 4221 /* Fix up byte swapping */ 4222 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4223 4224 /* 5718 reset step 13, 57XX step 17 */ 4225 /* Poll until the firmware initialization is complete */ 4226 bge_poll_fw(sc); 4227 4228 /* 57XX step 21 */ 4229 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4230 pcireg_t msidata; 4231 4232 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4233 BGE_PCI_MSI_DATA); 4234 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4235 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4236 msidata); 4237 } 4238 4239 /* 57XX step 18 */ 4240 /* Write mac mode. */ 4241 val = CSR_READ_4(sc, BGE_MAC_MODE); 4242 /* Restore mac_mode_mask's bits using mac_mode */ 4243 val = (val & ~mac_mode_mask) | mac_mode; 4244 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4245 DELAY(40); 4246 4247 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4248 4249 /* 4250 * The 5704 in TBI mode apparently needs some special 4251 * adjustment to insure the SERDES drive level is set 4252 * to 1.2V. 4253 */ 4254 if (sc->bge_flags & BGEF_FIBER_TBI && 4255 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4256 uint32_t serdescfg; 4257 4258 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4259 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4260 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4261 } 4262 4263 if (sc->bge_flags & BGEF_PCIE && 4264 !BGE_IS_57765_PLUS(sc) && 4265 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4266 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4267 uint32_t v; 4268 4269 /* Enable PCI Express bug fix */ 4270 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4271 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4272 v | BGE_TLP_DATA_FIFO_PROTECT); 4273 } 4274 4275 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4276 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4277 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4278 4279 return 0; 4280 } 4281 4282 /* 4283 * Frame reception handling. This is called if there's a frame 4284 * on the receive return list. 4285 * 4286 * Note: we have to be able to handle two possibilities here: 4287 * 1) the frame is from the jumbo receive ring 4288 * 2) the frame is from the standard receive ring 4289 */ 4290 4291 static void 4292 bge_rxeof(struct bge_softc *sc) 4293 { 4294 struct ifnet *ifp; 4295 uint16_t rx_prod, rx_cons; 4296 int stdcnt = 0, jumbocnt = 0; 4297 bus_dmamap_t dmamap; 4298 bus_addr_t offset, toff; 4299 bus_size_t tlen; 4300 int tosync; 4301 4302 rx_cons = sc->bge_rx_saved_considx; 4303 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4304 4305 /* Nothing to do */ 4306 if (rx_cons == rx_prod) 4307 return; 4308 4309 ifp = &sc->ethercom.ec_if; 4310 4311 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4312 offsetof(struct bge_ring_data, bge_status_block), 4313 sizeof (struct bge_status_block), 4314 BUS_DMASYNC_POSTREAD); 4315 4316 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4317 tosync = rx_prod - rx_cons; 4318 4319 if (tosync != 0) 4320 rnd_add_uint32(&sc->rnd_source, tosync); 4321 4322 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4323 4324 if (tosync < 0) { 4325 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4326 sizeof (struct bge_rx_bd); 4327 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4328 toff, tlen, BUS_DMASYNC_POSTREAD); 4329 tosync = -tosync; 4330 } 4331 4332 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4333 offset, tosync * sizeof (struct bge_rx_bd), 4334 BUS_DMASYNC_POSTREAD); 4335 4336 while (rx_cons != rx_prod) { 4337 struct bge_rx_bd *cur_rx; 4338 uint32_t rxidx; 4339 struct mbuf *m = NULL; 4340 4341 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4342 4343 rxidx = cur_rx->bge_idx; 4344 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4345 4346 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4347 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4348 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4349 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4350 jumbocnt++; 4351 bus_dmamap_sync(sc->bge_dmatag, 4352 sc->bge_cdata.bge_rx_jumbo_map, 4353 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4354 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4355 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4356 ifp->if_ierrors++; 4357 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4358 continue; 4359 } 4360 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4361 NULL)== ENOBUFS) { 4362 ifp->if_ierrors++; 4363 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4364 continue; 4365 } 4366 } else { 4367 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4368 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4369 4370 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4371 stdcnt++; 4372 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4373 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4374 if (dmamap == NULL) { 4375 ifp->if_ierrors++; 4376 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4377 continue; 4378 } 4379 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4380 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4381 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4382 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4383 ifp->if_ierrors++; 4384 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4385 continue; 4386 } 4387 if (bge_newbuf_std(sc, sc->bge_std, 4388 NULL, dmamap) == ENOBUFS) { 4389 ifp->if_ierrors++; 4390 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4391 continue; 4392 } 4393 } 4394 4395 #ifndef __NO_STRICT_ALIGNMENT 4396 /* 4397 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4398 * the Rx buffer has the layer-2 header unaligned. 4399 * If our CPU requires alignment, re-align by copying. 4400 */ 4401 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4402 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4403 cur_rx->bge_len); 4404 m->m_data += ETHER_ALIGN; 4405 } 4406 #endif 4407 4408 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4409 m_set_rcvif(m, ifp); 4410 4411 bge_rxcsum(sc, cur_rx, m); 4412 4413 /* 4414 * If we received a packet with a vlan tag, pass it 4415 * to vlan_input() instead of ether_input(). 4416 */ 4417 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4418 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4419 } 4420 4421 if_percpuq_enqueue(ifp->if_percpuq, m); 4422 } 4423 4424 sc->bge_rx_saved_considx = rx_cons; 4425 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4426 if (stdcnt) 4427 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4428 if (jumbocnt) 4429 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4430 } 4431 4432 static void 4433 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4434 { 4435 4436 if (BGE_IS_57765_PLUS(sc)) { 4437 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4438 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4439 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4440 if ((cur_rx->bge_error_flag & 4441 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4442 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4443 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4444 m->m_pkthdr.csum_data = 4445 cur_rx->bge_tcp_udp_csum; 4446 m->m_pkthdr.csum_flags |= 4447 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4448 M_CSUM_DATA); 4449 } 4450 } 4451 } else { 4452 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4453 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4454 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4455 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4456 /* 4457 * Rx transport checksum-offload may also 4458 * have bugs with packets which, when transmitted, 4459 * were `runts' requiring padding. 4460 */ 4461 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4462 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4463 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4464 m->m_pkthdr.csum_data = 4465 cur_rx->bge_tcp_udp_csum; 4466 m->m_pkthdr.csum_flags |= 4467 (M_CSUM_TCPv4|M_CSUM_UDPv4| 4468 M_CSUM_DATA); 4469 } 4470 } 4471 } 4472 4473 static void 4474 bge_txeof(struct bge_softc *sc) 4475 { 4476 struct bge_tx_bd *cur_tx = NULL; 4477 struct ifnet *ifp; 4478 struct txdmamap_pool_entry *dma; 4479 bus_addr_t offset, toff; 4480 bus_size_t tlen; 4481 int tosync; 4482 struct mbuf *m; 4483 4484 ifp = &sc->ethercom.ec_if; 4485 4486 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4487 offsetof(struct bge_ring_data, bge_status_block), 4488 sizeof (struct bge_status_block), 4489 BUS_DMASYNC_POSTREAD); 4490 4491 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4492 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4493 sc->bge_tx_saved_considx; 4494 4495 if (tosync != 0) 4496 rnd_add_uint32(&sc->rnd_source, tosync); 4497 4498 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4499 4500 if (tosync < 0) { 4501 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4502 sizeof (struct bge_tx_bd); 4503 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4504 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4505 tosync = -tosync; 4506 } 4507 4508 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4509 offset, tosync * sizeof (struct bge_tx_bd), 4510 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4511 4512 /* 4513 * Go through our tx ring and free mbufs for those 4514 * frames that have been sent. 4515 */ 4516 while (sc->bge_tx_saved_considx != 4517 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4518 uint32_t idx = 0; 4519 4520 idx = sc->bge_tx_saved_considx; 4521 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4522 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4523 ifp->if_opackets++; 4524 m = sc->bge_cdata.bge_tx_chain[idx]; 4525 if (m != NULL) { 4526 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4527 dma = sc->txdma[idx]; 4528 if (dma->is_dma32) { 4529 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4530 0, dma->dmamap32->dm_mapsize, 4531 BUS_DMASYNC_POSTWRITE); 4532 bus_dmamap_unload( 4533 sc->bge_dmatag32, dma->dmamap32); 4534 } else { 4535 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4536 0, dma->dmamap->dm_mapsize, 4537 BUS_DMASYNC_POSTWRITE); 4538 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4539 } 4540 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4541 sc->txdma[idx] = NULL; 4542 4543 m_freem(m); 4544 } 4545 sc->bge_txcnt--; 4546 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4547 ifp->if_timer = 0; 4548 } 4549 4550 if (cur_tx != NULL) 4551 ifp->if_flags &= ~IFF_OACTIVE; 4552 } 4553 4554 static int 4555 bge_intr(void *xsc) 4556 { 4557 struct bge_softc *sc; 4558 struct ifnet *ifp; 4559 uint32_t pcistate, statusword, statustag; 4560 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4561 4562 sc = xsc; 4563 ifp = &sc->ethercom.ec_if; 4564 4565 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4566 if (BGE_IS_5717_PLUS(sc)) 4567 intrmask = 0; 4568 4569 /* It is possible for the interrupt to arrive before 4570 * the status block is updated prior to the interrupt. 4571 * Reading the PCI State register will confirm whether the 4572 * interrupt is ours and will flush the status block. 4573 */ 4574 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4575 4576 /* read status word from status block */ 4577 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4578 offsetof(struct bge_ring_data, bge_status_block), 4579 sizeof (struct bge_status_block), 4580 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4581 statusword = sc->bge_rdata->bge_status_block.bge_status; 4582 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4583 4584 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4585 if (sc->bge_lasttag == statustag && 4586 (~pcistate & intrmask)) { 4587 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4588 return (0); 4589 } 4590 sc->bge_lasttag = statustag; 4591 } else { 4592 if (!(statusword & BGE_STATFLAG_UPDATED) && 4593 !(~pcistate & intrmask)) { 4594 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4595 return (0); 4596 } 4597 statustag = 0; 4598 } 4599 /* Ack interrupt and stop others from occurring. */ 4600 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4601 BGE_EVCNT_INCR(sc->bge_ev_intr); 4602 4603 /* clear status word */ 4604 sc->bge_rdata->bge_status_block.bge_status = 0; 4605 4606 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4607 offsetof(struct bge_ring_data, bge_status_block), 4608 sizeof (struct bge_status_block), 4609 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4610 4611 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4612 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4613 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4614 bge_link_upd(sc); 4615 4616 if (ifp->if_flags & IFF_RUNNING) { 4617 /* Check RX return ring producer/consumer */ 4618 bge_rxeof(sc); 4619 4620 /* Check TX ring producer/consumer */ 4621 bge_txeof(sc); 4622 } 4623 4624 if (sc->bge_pending_rxintr_change) { 4625 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4626 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4627 4628 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4629 DELAY(10); 4630 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4631 4632 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4633 DELAY(10); 4634 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4635 4636 sc->bge_pending_rxintr_change = 0; 4637 } 4638 bge_handle_events(sc); 4639 4640 /* Re-enable interrupts. */ 4641 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4642 4643 if (ifp->if_flags & IFF_RUNNING) 4644 if_schedule_deferred_start(ifp); 4645 4646 return 1; 4647 } 4648 4649 static void 4650 bge_asf_driver_up(struct bge_softc *sc) 4651 { 4652 if (sc->bge_asf_mode & ASF_STACKUP) { 4653 /* Send ASF heartbeat aprox. every 2s */ 4654 if (sc->bge_asf_count) 4655 sc->bge_asf_count --; 4656 else { 4657 sc->bge_asf_count = 2; 4658 4659 bge_wait_for_event_ack(sc); 4660 4661 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4662 BGE_FW_CMD_DRV_ALIVE3); 4663 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4664 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4665 BGE_FW_HB_TIMEOUT_SEC); 4666 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4667 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4668 BGE_RX_CPU_DRV_EVENT); 4669 } 4670 } 4671 } 4672 4673 static void 4674 bge_tick(void *xsc) 4675 { 4676 struct bge_softc *sc = xsc; 4677 struct mii_data *mii = &sc->bge_mii; 4678 int s; 4679 4680 s = splnet(); 4681 4682 if (BGE_IS_5705_PLUS(sc)) 4683 bge_stats_update_regs(sc); 4684 else 4685 bge_stats_update(sc); 4686 4687 if (sc->bge_flags & BGEF_FIBER_TBI) { 4688 /* 4689 * Since in TBI mode auto-polling can't be used we should poll 4690 * link status manually. Here we register pending link event 4691 * and trigger interrupt. 4692 */ 4693 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4694 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4695 } else { 4696 /* 4697 * Do not touch PHY if we have link up. This could break 4698 * IPMI/ASF mode or produce extra input errors. 4699 * (extra input errors was reported for bcm5701 & bcm5704). 4700 */ 4701 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4702 mii_tick(mii); 4703 } 4704 4705 bge_asf_driver_up(sc); 4706 4707 if (!sc->bge_detaching) 4708 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4709 4710 splx(s); 4711 } 4712 4713 static void 4714 bge_stats_update_regs(struct bge_softc *sc) 4715 { 4716 struct ifnet *ifp = &sc->ethercom.ec_if; 4717 4718 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4719 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4720 4721 /* 4722 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4723 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4724 * (silicon bug). There's no reliable workaround so just 4725 * ignore the counter 4726 */ 4727 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4728 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5719_A0 && 4729 BGE_ASICREV(sc->bge_chipid) != BGE_CHIPID_BCM5720_A0) { 4730 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4731 } 4732 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4733 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4734 } 4735 4736 static void 4737 bge_stats_update(struct bge_softc *sc) 4738 { 4739 struct ifnet *ifp = &sc->ethercom.ec_if; 4740 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4741 4742 #define READ_STAT(sc, stats, stat) \ 4743 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4744 4745 ifp->if_collisions += 4746 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4747 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4748 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4749 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4750 ifp->if_collisions; 4751 4752 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4753 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4754 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4755 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4756 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4757 READ_STAT(sc, stats, 4758 xoffPauseFramesReceived.bge_addr_lo)); 4759 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4760 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4761 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4762 READ_STAT(sc, stats, 4763 macControlFramesReceived.bge_addr_lo)); 4764 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4765 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4766 4767 #undef READ_STAT 4768 4769 #ifdef notdef 4770 ifp->if_collisions += 4771 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4772 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4773 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4774 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4775 ifp->if_collisions; 4776 #endif 4777 } 4778 4779 /* 4780 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4781 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4782 * but when such padded frames employ the bge IP/TCP checksum offload, 4783 * the hardware checksum assist gives incorrect results (possibly 4784 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4785 * If we pad such runts with zeros, the onboard checksum comes out correct. 4786 */ 4787 static inline int 4788 bge_cksum_pad(struct mbuf *pkt) 4789 { 4790 struct mbuf *last = NULL; 4791 int padlen; 4792 4793 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4794 4795 /* if there's only the packet-header and we can pad there, use it. */ 4796 if (pkt->m_pkthdr.len == pkt->m_len && 4797 M_TRAILINGSPACE(pkt) >= padlen) { 4798 last = pkt; 4799 } else { 4800 /* 4801 * Walk packet chain to find last mbuf. We will either 4802 * pad there, or append a new mbuf and pad it 4803 * (thus perhaps avoiding the bcm5700 dma-min bug). 4804 */ 4805 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4806 continue; /* do nothing */ 4807 } 4808 4809 /* `last' now points to last in chain. */ 4810 if (M_TRAILINGSPACE(last) < padlen) { 4811 /* Allocate new empty mbuf, pad it. Compact later. */ 4812 struct mbuf *n; 4813 MGET(n, M_DONTWAIT, MT_DATA); 4814 if (n == NULL) 4815 return ENOBUFS; 4816 n->m_len = 0; 4817 last->m_next = n; 4818 last = n; 4819 } 4820 } 4821 4822 KDASSERT(!M_READONLY(last)); 4823 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4824 4825 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4826 memset(mtod(last, char *) + last->m_len, 0, padlen); 4827 last->m_len += padlen; 4828 pkt->m_pkthdr.len += padlen; 4829 return 0; 4830 } 4831 4832 /* 4833 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4834 */ 4835 static inline int 4836 bge_compact_dma_runt(struct mbuf *pkt) 4837 { 4838 struct mbuf *m, *prev; 4839 int totlen; 4840 4841 prev = NULL; 4842 totlen = 0; 4843 4844 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 4845 int mlen = m->m_len; 4846 int shortfall = 8 - mlen ; 4847 4848 totlen += mlen; 4849 if (mlen == 0) 4850 continue; 4851 if (mlen >= 8) 4852 continue; 4853 4854 /* If we get here, mbuf data is too small for DMA engine. 4855 * Try to fix by shuffling data to prev or next in chain. 4856 * If that fails, do a compacting deep-copy of the whole chain. 4857 */ 4858 4859 /* Internal frag. If fits in prev, copy it there. */ 4860 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4861 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4862 prev->m_len += mlen; 4863 m->m_len = 0; 4864 /* XXX stitch chain */ 4865 prev->m_next = m_free(m); 4866 m = prev; 4867 continue; 4868 } 4869 else if (m->m_next != NULL && 4870 M_TRAILINGSPACE(m) >= shortfall && 4871 m->m_next->m_len >= (8 + shortfall)) { 4872 /* m is writable and have enough data in next, pull up. */ 4873 4874 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4875 shortfall); 4876 m->m_len += shortfall; 4877 m->m_next->m_len -= shortfall; 4878 m->m_next->m_data += shortfall; 4879 } 4880 else if (m->m_next == NULL || 1) { 4881 /* Got a runt at the very end of the packet. 4882 * borrow data from the tail of the preceding mbuf and 4883 * update its length in-place. (The original data is still 4884 * valid, so we can do this even if prev is not writable.) 4885 */ 4886 4887 /* if we'd make prev a runt, just move all of its data. */ 4888 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4889 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4890 4891 if ((prev->m_len - shortfall) < 8) 4892 shortfall = prev->m_len; 4893 4894 #ifdef notyet /* just do the safe slow thing for now */ 4895 if (!M_READONLY(m)) { 4896 if (M_LEADINGSPACE(m) < shorfall) { 4897 void *m_dat; 4898 m_dat = (m->m_flags & M_PKTHDR) ? 4899 m->m_pktdat : m->dat; 4900 memmove(m_dat, mtod(m, void*), m->m_len); 4901 m->m_data = m_dat; 4902 } 4903 } else 4904 #endif /* just do the safe slow thing */ 4905 { 4906 struct mbuf * n = NULL; 4907 int newprevlen = prev->m_len - shortfall; 4908 4909 MGET(n, M_NOWAIT, MT_DATA); 4910 if (n == NULL) 4911 return ENOBUFS; 4912 KASSERT(m->m_len + shortfall < MLEN 4913 /*, 4914 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4915 4916 /* first copy the data we're stealing from prev */ 4917 memcpy(n->m_data, prev->m_data + newprevlen, 4918 shortfall); 4919 4920 /* update prev->m_len accordingly */ 4921 prev->m_len -= shortfall; 4922 4923 /* copy data from runt m */ 4924 memcpy(n->m_data + shortfall, m->m_data, 4925 m->m_len); 4926 4927 /* n holds what we stole from prev, plus m */ 4928 n->m_len = shortfall + m->m_len; 4929 4930 /* stitch n into chain and free m */ 4931 n->m_next = m->m_next; 4932 prev->m_next = n; 4933 /* KASSERT(m->m_next == NULL); */ 4934 m->m_next = NULL; 4935 m_free(m); 4936 m = n; /* for continuing loop */ 4937 } 4938 } 4939 } 4940 return 0; 4941 } 4942 4943 /* 4944 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4945 * pointers to descriptors. 4946 */ 4947 static int 4948 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 4949 { 4950 struct ifnet *ifp = &sc->ethercom.ec_if; 4951 struct bge_tx_bd *f, *prev_f; 4952 uint32_t frag, cur; 4953 uint16_t csum_flags = 0; 4954 uint16_t txbd_tso_flags = 0; 4955 struct txdmamap_pool_entry *dma; 4956 bus_dmamap_t dmamap; 4957 bus_dma_tag_t dmatag; 4958 int i = 0; 4959 int use_tso, maxsegsize, error; 4960 bool have_vtag; 4961 uint16_t vtag; 4962 bool remap; 4963 4964 if (m_head->m_pkthdr.csum_flags) { 4965 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 4966 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4967 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 4968 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4969 } 4970 4971 /* 4972 * If we were asked to do an outboard checksum, and the NIC 4973 * has the bug where it sometimes adds in the Ethernet padding, 4974 * explicitly pad with zeros so the cksum will be correct either way. 4975 * (For now, do this for all chip versions, until newer 4976 * are confirmed to not require the workaround.) 4977 */ 4978 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 4979 #ifdef notyet 4980 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 4981 #endif 4982 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 4983 goto check_dma_bug; 4984 4985 if (bge_cksum_pad(m_head) != 0) 4986 return ENOBUFS; 4987 4988 check_dma_bug: 4989 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4990 goto doit; 4991 4992 /* 4993 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4994 * less than eight bytes. If we encounter a teeny mbuf 4995 * at the end of a chain, we can pad. Otherwise, copy. 4996 */ 4997 if (bge_compact_dma_runt(m_head) != 0) 4998 return ENOBUFS; 4999 5000 doit: 5001 dma = SLIST_FIRST(&sc->txdma_list); 5002 if (dma == NULL) { 5003 ifp->if_flags |= IFF_OACTIVE; 5004 return ENOBUFS; 5005 } 5006 dmamap = dma->dmamap; 5007 dmatag = sc->bge_dmatag; 5008 dma->is_dma32 = false; 5009 5010 /* 5011 * Set up any necessary TSO state before we start packing... 5012 */ 5013 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5014 if (!use_tso) { 5015 maxsegsize = 0; 5016 } else { /* TSO setup */ 5017 unsigned mss; 5018 struct ether_header *eh; 5019 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5020 unsigned bge_hlen; 5021 struct mbuf * m0 = m_head; 5022 struct ip *ip; 5023 struct tcphdr *th; 5024 int iphl, hlen; 5025 5026 /* 5027 * XXX It would be nice if the mbuf pkthdr had offset 5028 * fields for the protocol headers. 5029 */ 5030 5031 eh = mtod(m0, struct ether_header *); 5032 switch (htons(eh->ether_type)) { 5033 case ETHERTYPE_IP: 5034 offset = ETHER_HDR_LEN; 5035 break; 5036 5037 case ETHERTYPE_VLAN: 5038 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5039 break; 5040 5041 default: 5042 /* 5043 * Don't support this protocol or encapsulation. 5044 */ 5045 return ENOBUFS; 5046 } 5047 5048 /* 5049 * TCP/IP headers are in the first mbuf; we can do 5050 * this the easy way. 5051 */ 5052 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5053 hlen = iphl + offset; 5054 if (__predict_false(m0->m_len < 5055 (hlen + sizeof(struct tcphdr)))) { 5056 5057 aprint_error_dev(sc->bge_dev, 5058 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5059 "not handled yet\n", 5060 m0->m_len, hlen+ sizeof(struct tcphdr)); 5061 #ifdef NOTYET 5062 /* 5063 * XXX jonathan (at) NetBSD.org: untested. 5064 * how to force this branch to be taken? 5065 */ 5066 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5067 5068 m_copydata(m0, offset, sizeof(ip), &ip); 5069 m_copydata(m0, hlen, sizeof(th), &th); 5070 5071 ip.ip_len = 0; 5072 5073 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5074 sizeof(ip.ip_len), &ip.ip_len); 5075 5076 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5077 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5078 5079 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5080 sizeof(th.th_sum), &th.th_sum); 5081 5082 hlen += th.th_off << 2; 5083 iptcp_opt_words = hlen; 5084 #else 5085 /* 5086 * if_wm "hard" case not yet supported, can we not 5087 * mandate it out of existence? 5088 */ 5089 (void) ip; (void)th; (void) ip_tcp_hlen; 5090 5091 return ENOBUFS; 5092 #endif 5093 } else { 5094 ip = (struct ip *) (mtod(m0, char *) + offset); 5095 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5096 ip_tcp_hlen = iphl + (th->th_off << 2); 5097 5098 /* Total IP/TCP options, in 32-bit words */ 5099 iptcp_opt_words = (ip_tcp_hlen 5100 - sizeof(struct tcphdr) 5101 - sizeof(struct ip)) >> 2; 5102 } 5103 if (BGE_IS_575X_PLUS(sc)) { 5104 th->th_sum = 0; 5105 csum_flags = 0; 5106 } else { 5107 /* 5108 * XXX jonathan (at) NetBSD.org: 5705 untested. 5109 * Requires TSO firmware patch for 5701/5703/5704. 5110 */ 5111 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5112 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5113 } 5114 5115 mss = m_head->m_pkthdr.segsz; 5116 txbd_tso_flags |= 5117 BGE_TXBDFLAG_CPU_PRE_DMA | 5118 BGE_TXBDFLAG_CPU_POST_DMA; 5119 5120 /* 5121 * Our NIC TSO-assist assumes TSO has standard, optionless 5122 * IPv4 and TCP headers, which total 40 bytes. By default, 5123 * the NIC copies 40 bytes of IP/TCP header from the 5124 * supplied header into the IP/TCP header portion of 5125 * each post-TSO-segment. If the supplied packet has IP or 5126 * TCP options, we need to tell the NIC to copy those extra 5127 * bytes into each post-TSO header, in addition to the normal 5128 * 40-byte IP/TCP header (and to leave space accordingly). 5129 * Unfortunately, the driver encoding of option length 5130 * varies across different ASIC families. 5131 */ 5132 tcp_seg_flags = 0; 5133 bge_hlen = ip_tcp_hlen >> 2; 5134 if (BGE_IS_5717_PLUS(sc)) { 5135 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5136 txbd_tso_flags |= 5137 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5138 } else if (BGE_IS_5705_PLUS(sc)) { 5139 tcp_seg_flags = 5140 bge_hlen << 11; 5141 } else { 5142 /* XXX iptcp_opt_words or bge_hlen ? */ 5143 txbd_tso_flags |= 5144 iptcp_opt_words << 12; 5145 } 5146 maxsegsize = mss | tcp_seg_flags; 5147 ip->ip_len = htons(mss + ip_tcp_hlen); 5148 ip->ip_sum = 0; 5149 5150 } /* TSO setup */ 5151 5152 have_vtag = vlan_has_tag(m_head); 5153 if (have_vtag) 5154 vtag = vlan_get_tag(m_head); 5155 5156 /* 5157 * Start packing the mbufs in this chain into 5158 * the fragment pointers. Stop when we run out 5159 * of fragments or hit the end of the mbuf chain. 5160 */ 5161 remap = true; 5162 load_again: 5163 error = bus_dmamap_load_mbuf(dmatag, dmamap, 5164 m_head, BUS_DMA_NOWAIT); 5165 if (__predict_false(error)) { 5166 if (error == EFBIG && remap) { 5167 struct mbuf *m; 5168 remap = false; 5169 m = m_defrag(m_head, M_NOWAIT); 5170 if (m != NULL) { 5171 KASSERT(m == m_head); 5172 goto load_again; 5173 } 5174 } 5175 return error; 5176 } 5177 /* 5178 * Sanity check: avoid coming within 16 descriptors 5179 * of the end of the ring. 5180 */ 5181 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5182 BGE_TSO_PRINTF(("%s: " 5183 " dmamap_load_mbuf too close to ring wrap\n", 5184 device_xname(sc->bge_dev))); 5185 goto fail_unload; 5186 } 5187 5188 /* Iterate over dmap-map fragments. */ 5189 f = prev_f = NULL; 5190 cur = frag = *txidx; 5191 5192 for (i = 0; i < dmamap->dm_nsegs; i++) { 5193 f = &sc->bge_rdata->bge_tx_ring[frag]; 5194 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5195 break; 5196 5197 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5198 f->bge_len = dmamap->dm_segs[i].ds_len; 5199 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5200 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5201 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5202 (prev_f != NULL && 5203 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5204 ) { 5205 /* 5206 * watchdog timeout issue was observed with TSO, 5207 * limiting DMA address space to 32bits seems to 5208 * address the issue. 5209 */ 5210 bus_dmamap_unload(dmatag, dmamap); 5211 dmatag = sc->bge_dmatag32; 5212 dmamap = dma->dmamap32; 5213 dma->is_dma32 = true; 5214 remap = true; 5215 goto load_again; 5216 } 5217 5218 /* 5219 * For 5751 and follow-ons, for TSO we must turn 5220 * off checksum-assist flag in the tx-descr, and 5221 * supply the ASIC-revision-specific encoding 5222 * of TSO flags and segsize. 5223 */ 5224 if (use_tso) { 5225 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5226 f->bge_rsvd = maxsegsize; 5227 f->bge_flags = csum_flags | txbd_tso_flags; 5228 } else { 5229 f->bge_rsvd = 0; 5230 f->bge_flags = 5231 (csum_flags | txbd_tso_flags) & 0x0fff; 5232 } 5233 } else { 5234 f->bge_rsvd = 0; 5235 f->bge_flags = csum_flags; 5236 } 5237 5238 if (have_vtag) { 5239 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5240 f->bge_vlan_tag = vtag; 5241 } else { 5242 f->bge_vlan_tag = 0; 5243 } 5244 prev_f = f; 5245 cur = frag; 5246 BGE_INC(frag, BGE_TX_RING_CNT); 5247 } 5248 5249 if (i < dmamap->dm_nsegs) { 5250 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5251 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5252 goto fail_unload; 5253 } 5254 5255 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5256 BUS_DMASYNC_PREWRITE); 5257 5258 if (frag == sc->bge_tx_saved_considx) { 5259 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5260 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5261 5262 goto fail_unload; 5263 } 5264 5265 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5266 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5267 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5268 sc->txdma[cur] = dma; 5269 sc->bge_txcnt += dmamap->dm_nsegs; 5270 5271 *txidx = frag; 5272 5273 return 0; 5274 5275 fail_unload: 5276 bus_dmamap_unload(dmatag, dmamap); 5277 ifp->if_flags |= IFF_OACTIVE; 5278 5279 return ENOBUFS; 5280 } 5281 5282 /* 5283 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5284 * to the mbuf data regions directly in the transmit descriptors. 5285 */ 5286 static void 5287 bge_start(struct ifnet *ifp) 5288 { 5289 struct bge_softc *sc; 5290 struct mbuf *m_head = NULL; 5291 struct mbuf *m; 5292 uint32_t prodidx; 5293 int pkts = 0; 5294 int error; 5295 5296 sc = ifp->if_softc; 5297 5298 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 5299 return; 5300 5301 prodidx = sc->bge_tx_prodidx; 5302 5303 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5304 IFQ_POLL(&ifp->if_snd, m_head); 5305 if (m_head == NULL) 5306 break; 5307 5308 #if 0 5309 /* 5310 * XXX 5311 * safety overkill. If this is a fragmented packet chain 5312 * with delayed TCP/UDP checksums, then only encapsulate 5313 * it if we have enough descriptors to handle the entire 5314 * chain at once. 5315 * (paranoia -- may not actually be needed) 5316 */ 5317 if (m_head->m_flags & M_FIRSTFRAG && 5318 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5319 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5320 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5321 ifp->if_flags |= IFF_OACTIVE; 5322 break; 5323 } 5324 } 5325 #endif 5326 5327 /* 5328 * Pack the data into the transmit ring. If we 5329 * don't have room, set the OACTIVE flag and wait 5330 * for the NIC to drain the ring. 5331 */ 5332 error = bge_encap(sc, m_head, &prodidx); 5333 if (__predict_false(error)) { 5334 if (ifp->if_flags & IFF_OACTIVE) { 5335 /* just wait for the transmit ring to drain */ 5336 break; 5337 } 5338 IFQ_DEQUEUE(&ifp->if_snd, m); 5339 KASSERT(m == m_head); 5340 m_freem(m_head); 5341 continue; 5342 } 5343 5344 /* now we are committed to transmit the packet */ 5345 IFQ_DEQUEUE(&ifp->if_snd, m); 5346 KASSERT(m == m_head); 5347 pkts++; 5348 5349 /* 5350 * If there's a BPF listener, bounce a copy of this frame 5351 * to him. 5352 */ 5353 bpf_mtap(ifp, m_head, BPF_D_OUT); 5354 } 5355 if (pkts == 0) 5356 return; 5357 5358 /* Transmit */ 5359 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5360 /* 5700 b2 errata */ 5361 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5362 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5363 5364 sc->bge_tx_prodidx = prodidx; 5365 5366 /* 5367 * Set a timeout in case the chip goes out to lunch. 5368 */ 5369 ifp->if_timer = 5; 5370 } 5371 5372 static int 5373 bge_init(struct ifnet *ifp) 5374 { 5375 struct bge_softc *sc = ifp->if_softc; 5376 const uint16_t *m; 5377 uint32_t mode, reg; 5378 int s, error = 0; 5379 5380 s = splnet(); 5381 5382 ifp = &sc->ethercom.ec_if; 5383 5384 /* Cancel pending I/O and flush buffers. */ 5385 bge_stop(ifp, 0); 5386 5387 bge_stop_fw(sc); 5388 bge_sig_pre_reset(sc, BGE_RESET_START); 5389 bge_reset(sc); 5390 bge_sig_legacy(sc, BGE_RESET_START); 5391 5392 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5393 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5394 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5395 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5396 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5397 5398 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5399 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5400 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5401 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5402 5403 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5404 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5405 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5406 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5407 5408 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5409 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5410 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5411 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5412 } 5413 5414 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5415 pcireg_t aercap; 5416 5417 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5418 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5419 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5420 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5421 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5422 5423 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5424 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5425 | BGE_PCIE_EIDLE_DELAY_13CLK; 5426 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5427 5428 /* Clear correctable error */ 5429 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5430 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5431 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5432 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5433 5434 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5435 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5436 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5437 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5438 } 5439 5440 bge_sig_post_reset(sc, BGE_RESET_START); 5441 5442 bge_chipinit(sc); 5443 5444 /* 5445 * Init the various state machines, ring 5446 * control blocks and firmware. 5447 */ 5448 error = bge_blockinit(sc); 5449 if (error != 0) { 5450 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5451 error); 5452 splx(s); 5453 return error; 5454 } 5455 5456 ifp = &sc->ethercom.ec_if; 5457 5458 /* 5718 step 25, 57XX step 54 */ 5459 /* Specify MTU. */ 5460 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5461 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5462 5463 /* 5718 step 23 */ 5464 /* Load our MAC address. */ 5465 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5466 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5467 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5468 5469 /* Enable or disable promiscuous mode as needed. */ 5470 if (ifp->if_flags & IFF_PROMISC) 5471 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5472 else 5473 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5474 5475 /* Program multicast filter. */ 5476 bge_setmulti(sc); 5477 5478 /* Init RX ring. */ 5479 bge_init_rx_ring_std(sc); 5480 5481 /* 5482 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5483 * memory to insure that the chip has in fact read the first 5484 * entry of the ring. 5485 */ 5486 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5487 uint32_t v, i; 5488 for (i = 0; i < 10; i++) { 5489 DELAY(20); 5490 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5491 if (v == (MCLBYTES - ETHER_ALIGN)) 5492 break; 5493 } 5494 if (i == 10) 5495 aprint_error_dev(sc->bge_dev, 5496 "5705 A0 chip failed to load RX ring\n"); 5497 } 5498 5499 /* Init jumbo RX ring. */ 5500 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5501 bge_init_rx_ring_jumbo(sc); 5502 5503 /* Init our RX return ring index */ 5504 sc->bge_rx_saved_considx = 0; 5505 5506 /* Init TX ring. */ 5507 bge_init_tx_ring(sc); 5508 5509 /* 5718 step 63, 57XX step 94 */ 5510 /* Enable TX MAC state machine lockup fix. */ 5511 mode = CSR_READ_4(sc, BGE_TX_MODE); 5512 if (BGE_IS_5755_PLUS(sc) || 5513 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5514 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5515 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 5516 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5517 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5518 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5519 } 5520 5521 /* Turn on transmitter */ 5522 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5523 /* 5718 step 64 */ 5524 DELAY(100); 5525 5526 /* 5718 step 65, 57XX step 95 */ 5527 /* Turn on receiver */ 5528 mode = CSR_READ_4(sc, BGE_RX_MODE); 5529 if (BGE_IS_5755_PLUS(sc)) 5530 mode |= BGE_RXMODE_IPV6_ENABLE; 5531 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5532 /* 5718 step 66 */ 5533 DELAY(10); 5534 5535 /* 5718 step 12, 57XX step 37 */ 5536 /* 5537 * XXX Doucments of 5718 series and 577xx say the recommended value 5538 * is 1, but tg3 set 1 only on 57765 series. 5539 */ 5540 if (BGE_IS_57765_PLUS(sc)) 5541 reg = 1; 5542 else 5543 reg = 2; 5544 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5545 5546 /* Tell firmware we're alive. */ 5547 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5548 5549 /* Enable host interrupts. */ 5550 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5551 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5552 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5553 5554 if ((error = bge_ifmedia_upd(ifp)) != 0) 5555 goto out; 5556 5557 ifp->if_flags |= IFF_RUNNING; 5558 ifp->if_flags &= ~IFF_OACTIVE; 5559 5560 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5561 5562 out: 5563 sc->bge_if_flags = ifp->if_flags; 5564 splx(s); 5565 5566 return error; 5567 } 5568 5569 /* 5570 * Set media options. 5571 */ 5572 static int 5573 bge_ifmedia_upd(struct ifnet *ifp) 5574 { 5575 struct bge_softc *sc = ifp->if_softc; 5576 struct mii_data *mii = &sc->bge_mii; 5577 struct ifmedia *ifm = &sc->bge_ifmedia; 5578 int rc; 5579 5580 /* If this is a 1000baseX NIC, enable the TBI port. */ 5581 if (sc->bge_flags & BGEF_FIBER_TBI) { 5582 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5583 return EINVAL; 5584 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5585 case IFM_AUTO: 5586 /* 5587 * The BCM5704 ASIC appears to have a special 5588 * mechanism for programming the autoneg 5589 * advertisement registers in TBI mode. 5590 */ 5591 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5592 uint32_t sgdig; 5593 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5594 if (sgdig & BGE_SGDIGSTS_DONE) { 5595 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5596 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5597 sgdig |= BGE_SGDIGCFG_AUTO | 5598 BGE_SGDIGCFG_PAUSE_CAP | 5599 BGE_SGDIGCFG_ASYM_PAUSE; 5600 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5601 sgdig | BGE_SGDIGCFG_SEND); 5602 DELAY(5); 5603 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5604 sgdig); 5605 } 5606 } 5607 break; 5608 case IFM_1000_SX: 5609 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5610 BGE_CLRBIT(sc, BGE_MAC_MODE, 5611 BGE_MACMODE_HALF_DUPLEX); 5612 } else { 5613 BGE_SETBIT(sc, BGE_MAC_MODE, 5614 BGE_MACMODE_HALF_DUPLEX); 5615 } 5616 DELAY(40); 5617 break; 5618 default: 5619 return EINVAL; 5620 } 5621 /* XXX 802.3x flow control for 1000BASE-SX */ 5622 return 0; 5623 } 5624 5625 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5626 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5627 uint32_t reg; 5628 5629 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5630 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5631 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5632 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5633 } 5634 } 5635 5636 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5637 if ((rc = mii_mediachg(mii)) == ENXIO) 5638 return 0; 5639 5640 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5641 uint32_t reg; 5642 5643 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5644 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5645 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5646 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5647 delay(40); 5648 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5649 } 5650 } 5651 5652 /* 5653 * Force an interrupt so that we will call bge_link_upd 5654 * if needed and clear any pending link state attention. 5655 * Without this we are not getting any further interrupts 5656 * for link state changes and thus will not UP the link and 5657 * not be able to send in bge_start. The only way to get 5658 * things working was to receive a packet and get a RX intr. 5659 */ 5660 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5661 sc->bge_flags & BGEF_IS_5788) 5662 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5663 else 5664 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5665 5666 return rc; 5667 } 5668 5669 /* 5670 * Report current media status. 5671 */ 5672 static void 5673 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5674 { 5675 struct bge_softc *sc = ifp->if_softc; 5676 struct mii_data *mii = &sc->bge_mii; 5677 5678 if (sc->bge_flags & BGEF_FIBER_TBI) { 5679 ifmr->ifm_status = IFM_AVALID; 5680 ifmr->ifm_active = IFM_ETHER; 5681 if (CSR_READ_4(sc, BGE_MAC_STS) & 5682 BGE_MACSTAT_TBI_PCS_SYNCHED) 5683 ifmr->ifm_status |= IFM_ACTIVE; 5684 ifmr->ifm_active |= IFM_1000_SX; 5685 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5686 ifmr->ifm_active |= IFM_HDX; 5687 else 5688 ifmr->ifm_active |= IFM_FDX; 5689 return; 5690 } 5691 5692 mii_pollstat(mii); 5693 ifmr->ifm_status = mii->mii_media_status; 5694 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5695 sc->bge_flowflags; 5696 } 5697 5698 static int 5699 bge_ifflags_cb(struct ethercom *ec) 5700 { 5701 struct ifnet *ifp = &ec->ec_if; 5702 struct bge_softc *sc = ifp->if_softc; 5703 int change = ifp->if_flags ^ sc->bge_if_flags; 5704 5705 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 5706 return ENETRESET; 5707 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5708 return 0; 5709 5710 if ((ifp->if_flags & IFF_PROMISC) == 0) 5711 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5712 else 5713 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5714 5715 bge_setmulti(sc); 5716 5717 sc->bge_if_flags = ifp->if_flags; 5718 return 0; 5719 } 5720 5721 static int 5722 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5723 { 5724 struct bge_softc *sc = ifp->if_softc; 5725 struct ifreq *ifr = (struct ifreq *) data; 5726 int s, error = 0; 5727 struct mii_data *mii; 5728 5729 s = splnet(); 5730 5731 switch (command) { 5732 case SIOCSIFMEDIA: 5733 /* XXX Flow control is not supported for 1000BASE-SX */ 5734 if (sc->bge_flags & BGEF_FIBER_TBI) { 5735 ifr->ifr_media &= ~IFM_ETH_FMASK; 5736 sc->bge_flowflags = 0; 5737 } 5738 5739 /* Flow control requires full-duplex mode. */ 5740 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5741 (ifr->ifr_media & IFM_FDX) == 0) { 5742 ifr->ifr_media &= ~IFM_ETH_FMASK; 5743 } 5744 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5745 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5746 /* We can do both TXPAUSE and RXPAUSE. */ 5747 ifr->ifr_media |= 5748 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5749 } 5750 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5751 } 5752 /* FALLTHROUGH */ 5753 case SIOCGIFMEDIA: 5754 if (sc->bge_flags & BGEF_FIBER_TBI) { 5755 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5756 command); 5757 } else { 5758 mii = &sc->bge_mii; 5759 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5760 command); 5761 } 5762 break; 5763 default: 5764 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5765 break; 5766 5767 error = 0; 5768 5769 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5770 ; 5771 else if (ifp->if_flags & IFF_RUNNING) 5772 bge_setmulti(sc); 5773 break; 5774 } 5775 5776 splx(s); 5777 5778 return error; 5779 } 5780 5781 static void 5782 bge_watchdog(struct ifnet *ifp) 5783 { 5784 struct bge_softc *sc; 5785 uint32_t status; 5786 5787 sc = ifp->if_softc; 5788 5789 /* If pause frames are active then don't reset the hardware. */ 5790 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5791 status = CSR_READ_4(sc, BGE_RX_STS); 5792 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5793 /* 5794 * If link partner has us in XOFF state then wait for 5795 * the condition to clear. 5796 */ 5797 CSR_WRITE_4(sc, BGE_RX_STS, status); 5798 ifp->if_timer = 5; 5799 return; 5800 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5801 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5802 /* 5803 * If link partner has us in XOFF state then wait for 5804 * the condition to clear. 5805 */ 5806 CSR_WRITE_4(sc, BGE_RX_STS, status); 5807 ifp->if_timer = 5; 5808 return; 5809 } 5810 /* 5811 * Any other condition is unexpected and the controller 5812 * should be reset. 5813 */ 5814 } 5815 5816 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5817 5818 ifp->if_flags &= ~IFF_RUNNING; 5819 bge_init(ifp); 5820 5821 ifp->if_oerrors++; 5822 } 5823 5824 static void 5825 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5826 { 5827 int i; 5828 5829 BGE_CLRBIT_FLUSH(sc, reg, bit); 5830 5831 for (i = 0; i < 1000; i++) { 5832 delay(100); 5833 if ((CSR_READ_4(sc, reg) & bit) == 0) 5834 return; 5835 } 5836 5837 /* 5838 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5839 * on some environment (and once after boot?) 5840 */ 5841 if (reg != BGE_SRS_MODE) 5842 aprint_error_dev(sc->bge_dev, 5843 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5844 (u_long)reg, bit); 5845 } 5846 5847 /* 5848 * Stop the adapter and free any mbufs allocated to the 5849 * RX and TX lists. 5850 */ 5851 static void 5852 bge_stop(struct ifnet *ifp, int disable) 5853 { 5854 struct bge_softc *sc = ifp->if_softc; 5855 5856 if (disable) { 5857 sc->bge_detaching = 1; 5858 callout_halt(&sc->bge_timeout, NULL); 5859 } else 5860 callout_stop(&sc->bge_timeout); 5861 5862 /* Disable host interrupts. */ 5863 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5864 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5865 5866 /* 5867 * Tell firmware we're shutting down. 5868 */ 5869 bge_stop_fw(sc); 5870 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5871 5872 /* 5873 * Disable all of the receiver blocks. 5874 */ 5875 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5876 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5877 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5878 if (BGE_IS_5700_FAMILY(sc)) 5879 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5880 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5881 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5882 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5883 5884 /* 5885 * Disable all of the transmit blocks. 5886 */ 5887 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5888 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5889 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5890 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5891 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5892 if (BGE_IS_5700_FAMILY(sc)) 5893 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5894 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5895 5896 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5897 delay(40); 5898 5899 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5900 5901 /* 5902 * Shut down all of the memory managers and related 5903 * state machines. 5904 */ 5905 /* 5718 step 5a,5b */ 5906 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5907 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5908 if (BGE_IS_5700_FAMILY(sc)) 5909 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5910 5911 /* 5718 step 5c,5d */ 5912 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5913 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5914 5915 if (BGE_IS_5700_FAMILY(sc)) { 5916 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5917 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5918 } 5919 5920 bge_reset(sc); 5921 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5922 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5923 5924 /* 5925 * Keep the ASF firmware running if up. 5926 */ 5927 if (sc->bge_asf_mode & ASF_STACKUP) 5928 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5929 else 5930 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5931 5932 /* Free the RX lists. */ 5933 bge_free_rx_ring_std(sc, disable); 5934 5935 /* Free jumbo RX list. */ 5936 if (BGE_IS_JUMBO_CAPABLE(sc)) 5937 bge_free_rx_ring_jumbo(sc); 5938 5939 /* Free TX buffers. */ 5940 bge_free_tx_ring(sc, disable); 5941 5942 /* 5943 * Isolate/power down the PHY. 5944 */ 5945 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 5946 mii_down(&sc->bge_mii); 5947 5948 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5949 5950 /* Clear MAC's link state (PHY may still have link UP). */ 5951 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5952 5953 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5954 } 5955 5956 static void 5957 bge_link_upd(struct bge_softc *sc) 5958 { 5959 struct ifnet *ifp = &sc->ethercom.ec_if; 5960 struct mii_data *mii = &sc->bge_mii; 5961 uint32_t status; 5962 uint16_t phyval; 5963 int link; 5964 5965 /* Clear 'pending link event' flag */ 5966 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 5967 5968 /* 5969 * Process link state changes. 5970 * Grrr. The link status word in the status block does 5971 * not work correctly on the BCM5700 rev AX and BX chips, 5972 * according to all available information. Hence, we have 5973 * to enable MII interrupts in order to properly obtain 5974 * async link changes. Unfortunately, this also means that 5975 * we have to read the MAC status register to detect link 5976 * changes, thereby adding an additional register access to 5977 * the interrupt handler. 5978 */ 5979 5980 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 5981 status = CSR_READ_4(sc, BGE_MAC_STS); 5982 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5983 mii_pollstat(mii); 5984 5985 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 5986 mii->mii_media_status & IFM_ACTIVE && 5987 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 5988 BGE_STS_SETBIT(sc, BGE_STS_LINK); 5989 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 5990 (!(mii->mii_media_status & IFM_ACTIVE) || 5991 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 5992 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 5993 5994 /* Clear the interrupt */ 5995 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5996 BGE_EVTENB_MI_INTERRUPT); 5997 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5998 BRGPHY_MII_ISR, &phyval); 5999 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6000 BRGPHY_MII_IMR, BRGPHY_INTRS); 6001 } 6002 return; 6003 } 6004 6005 if (sc->bge_flags & BGEF_FIBER_TBI) { 6006 status = CSR_READ_4(sc, BGE_MAC_STS); 6007 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6008 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6009 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6010 if (BGE_ASICREV(sc->bge_chipid) 6011 == BGE_ASICREV_BCM5704) { 6012 BGE_CLRBIT(sc, BGE_MAC_MODE, 6013 BGE_MACMODE_TBI_SEND_CFGS); 6014 DELAY(40); 6015 } 6016 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6017 if_link_state_change(ifp, LINK_STATE_UP); 6018 } 6019 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6020 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6021 if_link_state_change(ifp, LINK_STATE_DOWN); 6022 } 6023 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6024 /* 6025 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6026 * bit in status word always set. Workaround this bug by 6027 * reading PHY link status directly. 6028 */ 6029 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6030 BGE_STS_LINK : 0; 6031 6032 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6033 mii_pollstat(mii); 6034 6035 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6036 mii->mii_media_status & IFM_ACTIVE && 6037 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6038 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6039 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6040 (!(mii->mii_media_status & IFM_ACTIVE) || 6041 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6042 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6043 } 6044 } else { 6045 /* 6046 * For controllers that call mii_tick, we have to poll 6047 * link status. 6048 */ 6049 mii_pollstat(mii); 6050 } 6051 6052 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6053 uint32_t reg, scale; 6054 6055 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6056 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6057 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6058 scale = 65; 6059 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6060 scale = 6; 6061 else 6062 scale = 12; 6063 6064 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6065 ~BGE_MISCCFG_TIMER_PRESCALER; 6066 reg |= scale << 1; 6067 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6068 } 6069 /* Clear the attention */ 6070 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 6071 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 6072 BGE_MACSTAT_LINK_CHANGED); 6073 } 6074 6075 static int 6076 bge_sysctl_verify(SYSCTLFN_ARGS) 6077 { 6078 int error, t; 6079 struct sysctlnode node; 6080 6081 node = *rnode; 6082 t = *(int*)rnode->sysctl_data; 6083 node.sysctl_data = &t; 6084 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6085 if (error || newp == NULL) 6086 return error; 6087 6088 #if 0 6089 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6090 node.sysctl_num, rnode->sysctl_num)); 6091 #endif 6092 6093 if (node.sysctl_num == bge_rxthresh_nodenum) { 6094 if (t < 0 || t >= NBGE_RX_THRESH) 6095 return EINVAL; 6096 bge_update_all_threshes(t); 6097 } else 6098 return EINVAL; 6099 6100 *(int*)rnode->sysctl_data = t; 6101 6102 return 0; 6103 } 6104 6105 /* 6106 * Set up sysctl(3) MIB, hw.bge.*. 6107 */ 6108 static void 6109 bge_sysctl_init(struct bge_softc *sc) 6110 { 6111 int rc, bge_root_num; 6112 const struct sysctlnode *node; 6113 6114 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6115 0, CTLTYPE_NODE, "bge", 6116 SYSCTL_DESCR("BGE interface controls"), 6117 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6118 goto out; 6119 } 6120 6121 bge_root_num = node->sysctl_num; 6122 6123 /* BGE Rx interrupt mitigation level */ 6124 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6125 CTLFLAG_READWRITE, 6126 CTLTYPE_INT, "rx_lvl", 6127 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6128 bge_sysctl_verify, 0, 6129 &bge_rx_thresh_lvl, 6130 0, CTL_HW, bge_root_num, CTL_CREATE, 6131 CTL_EOL)) != 0) { 6132 goto out; 6133 } 6134 6135 bge_rxthresh_nodenum = node->sysctl_num; 6136 6137 return; 6138 6139 out: 6140 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6141 } 6142 6143 #ifdef BGE_DEBUG 6144 void 6145 bge_debug_info(struct bge_softc *sc) 6146 { 6147 6148 printf("Hardware Flags:\n"); 6149 if (BGE_IS_57765_PLUS(sc)) 6150 printf(" - 57765 Plus\n"); 6151 if (BGE_IS_5717_PLUS(sc)) 6152 printf(" - 5717 Plus\n"); 6153 if (BGE_IS_5755_PLUS(sc)) 6154 printf(" - 5755 Plus\n"); 6155 if (BGE_IS_575X_PLUS(sc)) 6156 printf(" - 575X Plus\n"); 6157 if (BGE_IS_5705_PLUS(sc)) 6158 printf(" - 5705 Plus\n"); 6159 if (BGE_IS_5714_FAMILY(sc)) 6160 printf(" - 5714 Family\n"); 6161 if (BGE_IS_5700_FAMILY(sc)) 6162 printf(" - 5700 Family\n"); 6163 if (sc->bge_flags & BGEF_IS_5788) 6164 printf(" - 5788\n"); 6165 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6166 printf(" - Supports Jumbo Frames\n"); 6167 if (sc->bge_flags & BGEF_NO_EEPROM) 6168 printf(" - No EEPROM\n"); 6169 if (sc->bge_flags & BGEF_PCIX) 6170 printf(" - PCI-X Bus\n"); 6171 if (sc->bge_flags & BGEF_PCIE) 6172 printf(" - PCI Express Bus\n"); 6173 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6174 printf(" - RX Alignment Bug\n"); 6175 if (sc->bge_flags & BGEF_APE) 6176 printf(" - APE\n"); 6177 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6178 printf(" - CPMU\n"); 6179 if (sc->bge_flags & BGEF_TSO) 6180 printf(" - TSO\n"); 6181 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6182 printf(" - TAGGED_STATUS\n"); 6183 6184 /* PHY related */ 6185 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6186 printf(" - No 3 LEDs\n"); 6187 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6188 printf(" - CRC bug\n"); 6189 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6190 printf(" - ADC bug\n"); 6191 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6192 printf(" - 5704 A0 bug\n"); 6193 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6194 printf(" - jitter bug\n"); 6195 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6196 printf(" - BER bug\n"); 6197 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6198 printf(" - adjust trim\n"); 6199 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6200 printf(" - no wirespeed\n"); 6201 6202 /* ASF related */ 6203 if (sc->bge_asf_mode & ASF_ENABLE) 6204 printf(" - ASF enable\n"); 6205 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6206 printf(" - ASF new handshake\n"); 6207 if (sc->bge_asf_mode & ASF_STACKUP) 6208 printf(" - ASF stackup\n"); 6209 } 6210 #endif /* BGE_DEBUG */ 6211 6212 static int 6213 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6214 { 6215 prop_dictionary_t dict; 6216 prop_data_t ea; 6217 6218 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6219 return 1; 6220 6221 dict = device_properties(sc->bge_dev); 6222 ea = prop_dictionary_get(dict, "mac-address"); 6223 if (ea != NULL) { 6224 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6225 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6226 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6227 return 0; 6228 } 6229 6230 return 1; 6231 } 6232 6233 static int 6234 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6235 { 6236 uint32_t mac_addr; 6237 6238 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6239 if ((mac_addr >> 16) == 0x484b) { 6240 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6241 ether_addr[1] = (uint8_t)mac_addr; 6242 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6243 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6244 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6245 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6246 ether_addr[5] = (uint8_t)mac_addr; 6247 return 0; 6248 } 6249 return 1; 6250 } 6251 6252 static int 6253 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6254 { 6255 int mac_offset = BGE_EE_MAC_OFFSET; 6256 6257 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6258 mac_offset = BGE_EE_MAC_OFFSET_5906; 6259 6260 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6261 ETHER_ADDR_LEN)); 6262 } 6263 6264 static int 6265 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6266 { 6267 6268 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6269 return 1; 6270 6271 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6272 ETHER_ADDR_LEN)); 6273 } 6274 6275 static int 6276 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6277 { 6278 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6279 /* NOTE: Order is critical */ 6280 bge_get_eaddr_fw, 6281 bge_get_eaddr_mem, 6282 bge_get_eaddr_nvram, 6283 bge_get_eaddr_eeprom, 6284 NULL 6285 }; 6286 const bge_eaddr_fcn_t *func; 6287 6288 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6289 if ((*func)(sc, eaddr) == 0) 6290 break; 6291 } 6292 return (*func == NULL ? ENXIO : 0); 6293 } 6294
Indexes created Wed Sep 24 05:09:52 GMT 2025