if_bge.c revision 1.332
1 /* $NetBSD: if_bge.c,v 1.332 2019/05/24 05:57:35 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.332 2019/05/24 05:57:35 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 #include <sys/rndsource.h> 95 96 #include <net/if.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_ether.h> 100 #include <net/bpf.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 #include <dev/pci/pcireg.h> 116 #include <dev/pci/pcivar.h> 117 #include <dev/pci/pcidevs.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/miidevs.h> 122 #include <dev/mii/brgphyreg.h> 123 124 #include <dev/pci/if_bgereg.h> 125 #include <dev/pci/if_bgevar.h> 126 127 #include <prop/proplib.h> 128 129 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 130 131 132 /* 133 * Tunable thresholds for rx-side bge interrupt mitigation. 134 */ 135 136 /* 137 * The pairs of values below were obtained from empirical measurement 138 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 139 * interrupt for every N packets received, where N is, approximately, 140 * the second value (rx_max_bds) in each pair. The values are chosen 141 * such that moving from one pair to the succeeding pair was observed 142 * to roughly halve interrupt rate under sustained input packet load. 143 * The values were empirically chosen to avoid overflowing internal 144 * limits on the bcm5700: increasing rx_ticks much beyond 600 145 * results in internal wrapping and higher interrupt rates. 146 * The limit of 46 frames was chosen to match NFS workloads. 147 * 148 * These values also work well on bcm5701, bcm5704C, and (less 149 * tested) bcm5703. On other chipsets, (including the Altima chip 150 * family), the larger values may overflow internal chip limits, 151 * leading to increasing interrupt rates rather than lower interrupt 152 * rates. 153 * 154 * Applications using heavy interrupt mitigation (interrupting every 155 * 32 or 46 frames) in both directions may need to increase the TCP 156 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 157 * full link bandwidth, due to ACKs and window updates lingering 158 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 159 */ 160 static const struct bge_load_rx_thresh { 161 int rx_ticks; 162 int rx_max_bds; } 163 bge_rx_threshes[] = { 164 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 165 { 32, 2 }, 166 { 50, 4 }, 167 { 100, 8 }, 168 { 192, 16 }, 169 { 416, 32 }, 170 { 598, 46 } 171 }; 172 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 173 174 /* XXX patchable; should be sysctl'able */ 175 static int bge_auto_thresh = 1; 176 static int bge_rx_thresh_lvl; 177 178 static int bge_rxthresh_nodenum; 179 180 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 181 182 static uint32_t bge_chipid(const struct pci_attach_args *); 183 static int bge_can_use_msi(struct bge_softc *); 184 static int bge_probe(device_t, cfdata_t, void *); 185 static void bge_attach(device_t, device_t, void *); 186 static int bge_detach(device_t, int); 187 static void bge_release_resources(struct bge_softc *); 188 189 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 190 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 191 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 194 195 static void bge_txeof(struct bge_softc *); 196 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 197 static void bge_rxeof(struct bge_softc *); 198 199 static void bge_asf_driver_up (struct bge_softc *); 200 static void bge_tick(void *); 201 static void bge_stats_update(struct bge_softc *); 202 static void bge_stats_update_regs(struct bge_softc *); 203 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 204 205 static int bge_intr(void *); 206 static void bge_start(struct ifnet *); 207 static int bge_ifflags_cb(struct ethercom *); 208 static int bge_ioctl(struct ifnet *, u_long, void *); 209 static int bge_init(struct ifnet *); 210 static void bge_stop(struct ifnet *, int); 211 static void bge_watchdog(struct ifnet *); 212 static int bge_ifmedia_upd(struct ifnet *); 213 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 214 215 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 216 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 217 218 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 220 static void bge_setmulti(struct bge_softc *); 221 222 static void bge_handle_events(struct bge_softc *); 223 static int bge_alloc_jumbo_mem(struct bge_softc *); 224 #if 0 /* XXX */ 225 static void bge_free_jumbo_mem(struct bge_softc *); 226 #endif 227 static void *bge_jalloc(struct bge_softc *); 228 static void bge_jfree(struct mbuf *, void *, size_t, void *); 229 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 230 bus_dmamap_t); 231 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 232 static int bge_init_rx_ring_std(struct bge_softc *); 233 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 234 static int bge_init_rx_ring_jumbo(struct bge_softc *); 235 static void bge_free_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_tx_ring(struct bge_softc *m, bool); 237 static int bge_init_tx_ring(struct bge_softc *); 238 239 static int bge_chipinit(struct bge_softc *); 240 static int bge_blockinit(struct bge_softc *); 241 static int bge_phy_addr(struct bge_softc *); 242 static uint32_t bge_readmem_ind(struct bge_softc *, int); 243 static void bge_writemem_ind(struct bge_softc *, int, int); 244 static void bge_writembx(struct bge_softc *, int, int); 245 static void bge_writembx_flush(struct bge_softc *, int, int); 246 static void bge_writemem_direct(struct bge_softc *, int, int); 247 static void bge_writereg_ind(struct bge_softc *, int, int); 248 static void bge_set_max_readrq(struct bge_softc *); 249 250 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 251 static int bge_miibus_writereg(device_t, int, int, uint16_t); 252 static void bge_miibus_statchg(struct ifnet *); 253 254 #define BGE_RESET_SHUTDOWN 0 255 #define BGE_RESET_START 1 256 #define BGE_RESET_SUSPEND 2 257 static void bge_sig_post_reset(struct bge_softc *, int); 258 static void bge_sig_legacy(struct bge_softc *, int); 259 static void bge_sig_pre_reset(struct bge_softc *, int); 260 static void bge_wait_for_event_ack(struct bge_softc *); 261 static void bge_stop_fw(struct bge_softc *); 262 static int bge_reset(struct bge_softc *); 263 static void bge_link_upd(struct bge_softc *); 264 static void bge_sysctl_init(struct bge_softc *); 265 static int bge_sysctl_verify(SYSCTLFN_PROTO); 266 267 static void bge_ape_lock_init(struct bge_softc *); 268 static void bge_ape_read_fw_ver(struct bge_softc *); 269 static int bge_ape_lock(struct bge_softc *, int); 270 static void bge_ape_unlock(struct bge_softc *, int); 271 static void bge_ape_send_event(struct bge_softc *, uint32_t); 272 static void bge_ape_driver_state_change(struct bge_softc *, int); 273 274 #ifdef BGE_DEBUG 275 #define DPRINTF(x) if (bgedebug) printf x 276 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 277 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 278 int bgedebug = 0; 279 int bge_tso_debug = 0; 280 void bge_debug_info(struct bge_softc *); 281 #else 282 #define DPRINTF(x) 283 #define DPRINTFN(n, x) 284 #define BGE_TSO_PRINTF(x) 285 #endif 286 287 #ifdef BGE_EVENT_COUNTERS 288 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 289 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 290 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 291 #else 292 #define BGE_EVCNT_INCR(ev) /* nothing */ 293 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 294 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 295 #endif 296 297 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 298 /* 299 * The BCM5700 documentation seems to indicate that the hardware still has the 300 * Alteon vendor ID burned into it, though it should always be overridden by 301 * the value in the EEPROM. We'll check for it anyway. 302 */ 303 static const struct bge_product { 304 pci_vendor_id_t bp_vendor; 305 pci_product_id_t bp_product; 306 const char *bp_name; 307 } bge_products[] = { 308 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 309 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 310 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 311 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 312 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 313 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 314 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 315 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 319 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 320 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 323 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 333 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 335 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 349 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 351 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 354 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 356 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 358 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 363 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 364 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 367 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 368 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 370 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 371 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 372 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 373 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 375 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 376 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 377 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 379 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 380 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 381 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 382 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 383 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 399 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 400 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 401 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 402 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 403 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 404 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 405 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 406 { 0, 0, NULL }, 407 }; 408 409 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 410 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 411 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 412 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 413 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 414 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 415 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 416 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 417 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 418 419 static const struct bge_revision { 420 uint32_t br_chipid; 421 const char *br_name; 422 } bge_revisions[] = { 423 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 424 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 425 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 426 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 427 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 428 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 429 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 430 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 431 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 432 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 433 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 434 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 435 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 436 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 437 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 438 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 439 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 440 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 441 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 442 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 443 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 444 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 445 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 446 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 447 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 448 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 449 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 450 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 451 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 452 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 453 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 454 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 455 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 456 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 457 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 458 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 459 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 460 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 461 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 462 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 463 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 464 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 465 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 466 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 467 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 468 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 469 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 470 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 471 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 472 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 473 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 474 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 475 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 476 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 477 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 478 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 479 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 480 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 481 /* 5754 and 5787 share the same ASIC ID */ 482 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 483 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 484 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 485 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 486 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 487 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 488 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 489 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 490 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 491 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 492 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 493 494 { 0, NULL } 495 }; 496 497 /* 498 * Some defaults for major revisions, so that newer steppings 499 * that we don't know about have a shot at working. 500 */ 501 static const struct bge_revision bge_majorrevs[] = { 502 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 503 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 504 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 505 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 506 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 507 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 508 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 509 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 510 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 511 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 512 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 513 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 514 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 515 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 516 /* 5754 and 5787 share the same ASIC ID */ 517 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 518 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 519 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 520 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 521 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 522 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 523 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 524 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 525 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 526 527 { 0, NULL } 528 }; 529 530 static int bge_allow_asf = 1; 531 532 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 533 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 534 535 static uint32_t 536 bge_readmem_ind(struct bge_softc *sc, int off) 537 { 538 pcireg_t val; 539 540 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 541 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 542 return 0; 543 544 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 545 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 546 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 547 return val; 548 } 549 550 static void 551 bge_writemem_ind(struct bge_softc *sc, int off, int val) 552 { 553 554 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 556 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 557 } 558 559 /* 560 * PCI Express only 561 */ 562 static void 563 bge_set_max_readrq(struct bge_softc *sc) 564 { 565 pcireg_t val; 566 567 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 568 + PCIE_DCSR); 569 val &= ~PCIE_DCSR_MAX_READ_REQ; 570 switch (sc->bge_expmrq) { 571 case 2048: 572 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 573 break; 574 case 4096: 575 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 576 break; 577 default: 578 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 579 break; 580 } 581 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 582 + PCIE_DCSR, val); 583 } 584 585 #ifdef notdef 586 static uint32_t 587 bge_readreg_ind(struct bge_softc *sc, int off) 588 { 589 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 590 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 591 } 592 #endif 593 594 static void 595 bge_writereg_ind(struct bge_softc *sc, int off, int val) 596 { 597 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 599 } 600 601 static void 602 bge_writemem_direct(struct bge_softc *sc, int off, int val) 603 { 604 CSR_WRITE_4(sc, off, val); 605 } 606 607 static void 608 bge_writembx(struct bge_softc *sc, int off, int val) 609 { 610 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 611 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 612 613 CSR_WRITE_4(sc, off, val); 614 } 615 616 static void 617 bge_writembx_flush(struct bge_softc *sc, int off, int val) 618 { 619 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 620 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 621 622 CSR_WRITE_4_FLUSH(sc, off, val); 623 } 624 625 /* 626 * Clear all stale locks and select the lock for this driver instance. 627 */ 628 void 629 bge_ape_lock_init(struct bge_softc *sc) 630 { 631 struct pci_attach_args *pa = &(sc->bge_pa); 632 uint32_t bit, regbase; 633 int i; 634 635 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 636 regbase = BGE_APE_LOCK_GRANT; 637 else 638 regbase = BGE_APE_PER_LOCK_GRANT; 639 640 /* Clear any stale locks. */ 641 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 642 switch (i) { 643 case BGE_APE_LOCK_PHY0: 644 case BGE_APE_LOCK_PHY1: 645 case BGE_APE_LOCK_PHY2: 646 case BGE_APE_LOCK_PHY3: 647 bit = BGE_APE_LOCK_GRANT_DRIVER0; 648 break; 649 default: 650 if (pa->pa_function == 0) 651 bit = BGE_APE_LOCK_GRANT_DRIVER0; 652 else 653 bit = (1 << pa->pa_function); 654 } 655 APE_WRITE_4(sc, regbase + 4 * i, bit); 656 } 657 658 /* Select the PHY lock based on the device's function number. */ 659 switch (pa->pa_function) { 660 case 0: 661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 662 break; 663 case 1: 664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 665 break; 666 case 2: 667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 668 break; 669 case 3: 670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 671 break; 672 default: 673 printf("%s: PHY lock not supported on function\n", 674 device_xname(sc->bge_dev)); 675 break; 676 } 677 } 678 679 /* 680 * Check for APE firmware, set flags, and print version info. 681 */ 682 void 683 bge_ape_read_fw_ver(struct bge_softc *sc) 684 { 685 const char *fwtype; 686 uint32_t apedata, features; 687 688 /* Check for a valid APE signature in shared memory. */ 689 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 690 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 691 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 692 return; 693 } 694 695 /* Check if APE firmware is running. */ 696 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 697 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 698 printf("%s: APE signature found but FW status not ready! " 699 "0x%08x\n", device_xname(sc->bge_dev), apedata); 700 return; 701 } 702 703 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 704 705 /* Fetch the APE firwmare type and version. */ 706 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 707 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 708 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 709 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 710 fwtype = "NCSI"; 711 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 712 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 713 fwtype = "DASH"; 714 } else 715 fwtype = "UNKN"; 716 717 /* Print the APE firmware version. */ 718 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 719 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 720 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 721 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 722 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 723 } 724 725 int 726 bge_ape_lock(struct bge_softc *sc, int locknum) 727 { 728 struct pci_attach_args *pa = &(sc->bge_pa); 729 uint32_t bit, gnt, req, status; 730 int i, off; 731 732 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 733 return (0); 734 735 /* Lock request/grant registers have different bases. */ 736 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 737 req = BGE_APE_LOCK_REQ; 738 gnt = BGE_APE_LOCK_GRANT; 739 } else { 740 req = BGE_APE_PER_LOCK_REQ; 741 gnt = BGE_APE_PER_LOCK_GRANT; 742 } 743 744 off = 4 * locknum; 745 746 switch (locknum) { 747 case BGE_APE_LOCK_GPIO: 748 /* Lock required when using GPIO. */ 749 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 750 return (0); 751 if (pa->pa_function == 0) 752 bit = BGE_APE_LOCK_REQ_DRIVER0; 753 else 754 bit = (1 << pa->pa_function); 755 break; 756 case BGE_APE_LOCK_GRC: 757 /* Lock required to reset the device. */ 758 if (pa->pa_function == 0) 759 bit = BGE_APE_LOCK_REQ_DRIVER0; 760 else 761 bit = (1 << pa->pa_function); 762 break; 763 case BGE_APE_LOCK_MEM: 764 /* Lock required when accessing certain APE memory. */ 765 if (pa->pa_function == 0) 766 bit = BGE_APE_LOCK_REQ_DRIVER0; 767 else 768 bit = (1 << pa->pa_function); 769 break; 770 case BGE_APE_LOCK_PHY0: 771 case BGE_APE_LOCK_PHY1: 772 case BGE_APE_LOCK_PHY2: 773 case BGE_APE_LOCK_PHY3: 774 /* Lock required when accessing PHYs. */ 775 bit = BGE_APE_LOCK_REQ_DRIVER0; 776 break; 777 default: 778 return (EINVAL); 779 } 780 781 /* Request a lock. */ 782 APE_WRITE_4_FLUSH(sc, req + off, bit); 783 784 /* Wait up to 1 second to acquire lock. */ 785 for (i = 0; i < 20000; i++) { 786 status = APE_READ_4(sc, gnt + off); 787 if (status == bit) 788 break; 789 DELAY(50); 790 } 791 792 /* Handle any errors. */ 793 if (status != bit) { 794 printf("%s: APE lock %d request failed! " 795 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 796 device_xname(sc->bge_dev), 797 locknum, req + off, bit & 0xFFFF, gnt + off, 798 status & 0xFFFF); 799 /* Revoke the lock request. */ 800 APE_WRITE_4(sc, gnt + off, bit); 801 return (EBUSY); 802 } 803 804 return (0); 805 } 806 807 void 808 bge_ape_unlock(struct bge_softc *sc, int locknum) 809 { 810 struct pci_attach_args *pa = &(sc->bge_pa); 811 uint32_t bit, gnt; 812 int off; 813 814 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 815 return; 816 817 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 818 gnt = BGE_APE_LOCK_GRANT; 819 else 820 gnt = BGE_APE_PER_LOCK_GRANT; 821 822 off = 4 * locknum; 823 824 switch (locknum) { 825 case BGE_APE_LOCK_GPIO: 826 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 827 return; 828 if (pa->pa_function == 0) 829 bit = BGE_APE_LOCK_GRANT_DRIVER0; 830 else 831 bit = (1 << pa->pa_function); 832 break; 833 case BGE_APE_LOCK_GRC: 834 if (pa->pa_function == 0) 835 bit = BGE_APE_LOCK_GRANT_DRIVER0; 836 else 837 bit = (1 << pa->pa_function); 838 break; 839 case BGE_APE_LOCK_MEM: 840 if (pa->pa_function == 0) 841 bit = BGE_APE_LOCK_GRANT_DRIVER0; 842 else 843 bit = (1 << pa->pa_function); 844 break; 845 case BGE_APE_LOCK_PHY0: 846 case BGE_APE_LOCK_PHY1: 847 case BGE_APE_LOCK_PHY2: 848 case BGE_APE_LOCK_PHY3: 849 bit = BGE_APE_LOCK_GRANT_DRIVER0; 850 break; 851 default: 852 return; 853 } 854 855 /* Write and flush for consecutive bge_ape_lock() */ 856 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 857 } 858 859 /* 860 * Send an event to the APE firmware. 861 */ 862 void 863 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 864 { 865 uint32_t apedata; 866 int i; 867 868 /* NCSI does not support APE events. */ 869 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 870 return; 871 872 /* Wait up to 1ms for APE to service previous event. */ 873 for (i = 10; i > 0; i--) { 874 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 875 break; 876 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 877 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 878 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 879 BGE_APE_EVENT_STATUS_EVENT_PENDING); 880 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 881 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 882 break; 883 } 884 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 885 DELAY(100); 886 } 887 if (i == 0) { 888 printf("%s: APE event 0x%08x send timed out\n", 889 device_xname(sc->bge_dev), event); 890 } 891 } 892 893 void 894 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 895 { 896 uint32_t apedata, event; 897 898 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 899 return; 900 901 switch (kind) { 902 case BGE_RESET_START: 903 /* If this is the first load, clear the load counter. */ 904 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 905 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 906 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 907 else { 908 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 909 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 910 } 911 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 912 BGE_APE_HOST_SEG_SIG_MAGIC); 913 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 914 BGE_APE_HOST_SEG_LEN_MAGIC); 915 916 /* Add some version info if bge(4) supports it. */ 917 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 918 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 919 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 920 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 921 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 922 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 923 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 924 BGE_APE_HOST_DRVR_STATE_START); 925 event = BGE_APE_EVENT_STATUS_STATE_START; 926 break; 927 case BGE_RESET_SHUTDOWN: 928 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 929 BGE_APE_HOST_DRVR_STATE_UNLOAD); 930 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 931 break; 932 case BGE_RESET_SUSPEND: 933 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 934 break; 935 default: 936 return; 937 } 938 939 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 940 BGE_APE_EVENT_STATUS_STATE_CHNGE); 941 } 942 943 static uint8_t 944 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 945 { 946 uint32_t access, byte = 0; 947 int i; 948 949 /* Lock. */ 950 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 951 for (i = 0; i < 8000; i++) { 952 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 953 break; 954 DELAY(20); 955 } 956 if (i == 8000) 957 return 1; 958 959 /* Enable access. */ 960 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 961 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 962 963 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 964 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 965 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 966 DELAY(10); 967 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 968 DELAY(10); 969 break; 970 } 971 } 972 973 if (i == BGE_TIMEOUT * 10) { 974 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 975 return 1; 976 } 977 978 /* Get result. */ 979 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 980 981 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 982 983 /* Disable access. */ 984 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 985 986 /* Unlock. */ 987 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 988 989 return 0; 990 } 991 992 /* 993 * Read a sequence of bytes from NVRAM. 994 */ 995 static int 996 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 997 { 998 int error = 0, i; 999 uint8_t byte = 0; 1000 1001 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1002 return 1; 1003 1004 for (i = 0; i < cnt; i++) { 1005 error = bge_nvram_getbyte(sc, off + i, &byte); 1006 if (error) 1007 break; 1008 *(dest + i) = byte; 1009 } 1010 1011 return (error ? 1 : 0); 1012 } 1013 1014 /* 1015 * Read a byte of data stored in the EEPROM at address 'addr.' The 1016 * BCM570x supports both the traditional bitbang interface and an 1017 * auto access interface for reading the EEPROM. We use the auto 1018 * access method. 1019 */ 1020 static uint8_t 1021 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1022 { 1023 int i; 1024 uint32_t byte = 0; 1025 1026 /* 1027 * Enable use of auto EEPROM access so we can avoid 1028 * having to use the bitbang method. 1029 */ 1030 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1031 1032 /* Reset the EEPROM, load the clock period. */ 1033 CSR_WRITE_4(sc, BGE_EE_ADDR, 1034 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1035 DELAY(20); 1036 1037 /* Issue the read EEPROM command. */ 1038 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1039 1040 /* Wait for completion */ 1041 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1042 DELAY(10); 1043 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1044 break; 1045 } 1046 1047 if (i == BGE_TIMEOUT * 10) { 1048 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1049 return 1; 1050 } 1051 1052 /* Get result. */ 1053 byte = CSR_READ_4(sc, BGE_EE_DATA); 1054 1055 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1056 1057 return 0; 1058 } 1059 1060 /* 1061 * Read a sequence of bytes from the EEPROM. 1062 */ 1063 static int 1064 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1065 { 1066 int error = 0, i; 1067 uint8_t byte = 0; 1068 char *dest = destv; 1069 1070 for (i = 0; i < cnt; i++) { 1071 error = bge_eeprom_getbyte(sc, off + i, &byte); 1072 if (error) 1073 break; 1074 *(dest + i) = byte; 1075 } 1076 1077 return (error ? 1 : 0); 1078 } 1079 1080 static int 1081 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1082 { 1083 struct bge_softc *sc = device_private(dev); 1084 uint32_t data; 1085 uint32_t autopoll; 1086 int rv = 0; 1087 int i; 1088 1089 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1090 return -1; 1091 1092 /* Reading with autopolling on may trigger PCI errors */ 1093 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1094 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1095 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1096 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1097 DELAY(80); 1098 } 1099 1100 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1101 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1102 1103 for (i = 0; i < BGE_TIMEOUT; i++) { 1104 delay(10); 1105 data = CSR_READ_4(sc, BGE_MI_COMM); 1106 if (!(data & BGE_MICOMM_BUSY)) { 1107 DELAY(5); 1108 data = CSR_READ_4(sc, BGE_MI_COMM); 1109 break; 1110 } 1111 } 1112 1113 if (i == BGE_TIMEOUT) { 1114 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1115 rv = ETIMEDOUT; 1116 } else if ((data & BGE_MICOMM_READFAIL) != 0) 1117 rv = -1; 1118 else 1119 *val = data & BGE_MICOMM_DATA; 1120 1121 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1122 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1123 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1124 DELAY(80); 1125 } 1126 1127 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1128 1129 return rv; 1130 } 1131 1132 static int 1133 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1134 { 1135 struct bge_softc *sc = device_private(dev); 1136 uint32_t autopoll; 1137 int i; 1138 1139 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1140 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1141 return 0; 1142 1143 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1144 return -1; 1145 1146 /* Reading with autopolling on may trigger PCI errors */ 1147 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1148 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1149 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1150 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1151 DELAY(80); 1152 } 1153 1154 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1155 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1156 1157 for (i = 0; i < BGE_TIMEOUT; i++) { 1158 delay(10); 1159 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1160 delay(5); 1161 CSR_READ_4(sc, BGE_MI_COMM); 1162 break; 1163 } 1164 } 1165 1166 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1167 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1168 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1169 delay(80); 1170 } 1171 1172 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1173 1174 if (i == BGE_TIMEOUT) { 1175 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1176 return ETIMEDOUT; 1177 } 1178 1179 return 0; 1180 } 1181 1182 static void 1183 bge_miibus_statchg(struct ifnet *ifp) 1184 { 1185 struct bge_softc *sc = ifp->if_softc; 1186 struct mii_data *mii = &sc->bge_mii; 1187 uint32_t mac_mode, rx_mode, tx_mode; 1188 1189 /* 1190 * Get flow control negotiation result. 1191 */ 1192 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1193 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1194 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1195 1196 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1197 mii->mii_media_status & IFM_ACTIVE && 1198 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1199 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1200 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1201 (!(mii->mii_media_status & IFM_ACTIVE) || 1202 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1203 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1204 1205 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1206 return; 1207 1208 /* Set the port mode (MII/GMII) to match the link speed. */ 1209 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1210 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1211 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1212 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1213 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1214 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1215 mac_mode |= BGE_PORTMODE_GMII; 1216 else 1217 mac_mode |= BGE_PORTMODE_MII; 1218 1219 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1220 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1221 if ((mii->mii_media_active & IFM_FDX) != 0) { 1222 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1223 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1224 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1225 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1226 } else 1227 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1228 1229 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1230 DELAY(40); 1231 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1232 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1233 } 1234 1235 /* 1236 * Update rx threshold levels to values in a particular slot 1237 * of the interrupt-mitigation table bge_rx_threshes. 1238 */ 1239 static void 1240 bge_set_thresh(struct ifnet *ifp, int lvl) 1241 { 1242 struct bge_softc *sc = ifp->if_softc; 1243 int s; 1244 1245 /* For now, just save the new Rx-intr thresholds and record 1246 * that a threshold update is pending. Updating the hardware 1247 * registers here (even at splhigh()) is observed to 1248 * occasionaly cause glitches where Rx-interrupts are not 1249 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1250 */ 1251 s = splnet(); 1252 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1253 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1254 sc->bge_pending_rxintr_change = 1; 1255 splx(s); 1256 } 1257 1258 1259 /* 1260 * Update Rx thresholds of all bge devices 1261 */ 1262 static void 1263 bge_update_all_threshes(int lvl) 1264 { 1265 struct ifnet *ifp; 1266 const char * const namebuf = "bge"; 1267 int namelen; 1268 int s; 1269 1270 if (lvl < 0) 1271 lvl = 0; 1272 else if (lvl >= NBGE_RX_THRESH) 1273 lvl = NBGE_RX_THRESH - 1; 1274 1275 namelen = strlen(namebuf); 1276 /* 1277 * Now search all the interfaces for this name/number 1278 */ 1279 s = pserialize_read_enter(); 1280 IFNET_READER_FOREACH(ifp) { 1281 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1282 continue; 1283 /* We got a match: update if doing auto-threshold-tuning */ 1284 if (bge_auto_thresh) 1285 bge_set_thresh(ifp, lvl); 1286 } 1287 pserialize_read_exit(s); 1288 } 1289 1290 /* 1291 * Handle events that have triggered interrupts. 1292 */ 1293 static void 1294 bge_handle_events(struct bge_softc *sc) 1295 { 1296 1297 return; 1298 } 1299 1300 /* 1301 * Memory management for jumbo frames. 1302 */ 1303 1304 static int 1305 bge_alloc_jumbo_mem(struct bge_softc *sc) 1306 { 1307 char *ptr, *kva; 1308 bus_dma_segment_t seg; 1309 int i, rseg, state, error; 1310 struct bge_jpool_entry *entry; 1311 1312 state = error = 0; 1313 1314 /* Grab a big chunk o' storage. */ 1315 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1316 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1317 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1318 return ENOBUFS; 1319 } 1320 1321 state = 1; 1322 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1323 BUS_DMA_NOWAIT)) { 1324 aprint_error_dev(sc->bge_dev, 1325 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1326 error = ENOBUFS; 1327 goto out; 1328 } 1329 1330 state = 2; 1331 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1332 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1333 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1334 error = ENOBUFS; 1335 goto out; 1336 } 1337 1338 state = 3; 1339 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1340 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1341 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1342 error = ENOBUFS; 1343 goto out; 1344 } 1345 1346 state = 4; 1347 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1348 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1349 1350 SLIST_INIT(&sc->bge_jfree_listhead); 1351 SLIST_INIT(&sc->bge_jinuse_listhead); 1352 1353 /* 1354 * Now divide it up into 9K pieces and save the addresses 1355 * in an array. 1356 */ 1357 ptr = sc->bge_cdata.bge_jumbo_buf; 1358 for (i = 0; i < BGE_JSLOTS; i++) { 1359 sc->bge_cdata.bge_jslots[i] = ptr; 1360 ptr += BGE_JLEN; 1361 entry = malloc(sizeof(struct bge_jpool_entry), 1362 M_DEVBUF, M_NOWAIT); 1363 if (entry == NULL) { 1364 aprint_error_dev(sc->bge_dev, 1365 "no memory for jumbo buffer queue!\n"); 1366 error = ENOBUFS; 1367 goto out; 1368 } 1369 entry->slot = i; 1370 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1371 entry, jpool_entries); 1372 } 1373 out: 1374 if (error != 0) { 1375 switch (state) { 1376 case 4: 1377 bus_dmamap_unload(sc->bge_dmatag, 1378 sc->bge_cdata.bge_rx_jumbo_map); 1379 /* FALLTHROUGH */ 1380 case 3: 1381 bus_dmamap_destroy(sc->bge_dmatag, 1382 sc->bge_cdata.bge_rx_jumbo_map); 1383 /* FALLTHROUGH */ 1384 case 2: 1385 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1386 /* FALLTHROUGH */ 1387 case 1: 1388 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1389 break; 1390 default: 1391 break; 1392 } 1393 } 1394 1395 return error; 1396 } 1397 1398 /* 1399 * Allocate a jumbo buffer. 1400 */ 1401 static void * 1402 bge_jalloc(struct bge_softc *sc) 1403 { 1404 struct bge_jpool_entry *entry; 1405 1406 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1407 1408 if (entry == NULL) { 1409 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1410 return NULL; 1411 } 1412 1413 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1414 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1415 return (sc->bge_cdata.bge_jslots[entry->slot]); 1416 } 1417 1418 /* 1419 * Release a jumbo buffer. 1420 */ 1421 static void 1422 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1423 { 1424 struct bge_jpool_entry *entry; 1425 struct bge_softc *sc; 1426 int i, s; 1427 1428 /* Extract the softc struct pointer. */ 1429 sc = (struct bge_softc *)arg; 1430 1431 if (sc == NULL) 1432 panic("bge_jfree: can't find softc pointer!"); 1433 1434 /* calculate the slot this buffer belongs to */ 1435 1436 i = ((char *)buf 1437 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1438 1439 if ((i < 0) || (i >= BGE_JSLOTS)) 1440 panic("bge_jfree: asked to free buffer that we don't manage!"); 1441 1442 s = splvm(); 1443 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1444 if (entry == NULL) 1445 panic("bge_jfree: buffer not in use!"); 1446 entry->slot = i; 1447 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1448 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1449 1450 if (__predict_true(m != NULL)) 1451 pool_cache_put(mb_cache, m); 1452 splx(s); 1453 } 1454 1455 1456 /* 1457 * Initialize a standard receive ring descriptor. 1458 */ 1459 static int 1460 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1461 bus_dmamap_t dmamap) 1462 { 1463 struct mbuf *m_new = NULL; 1464 struct bge_rx_bd *r; 1465 int error; 1466 1467 if (dmamap == NULL) 1468 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1469 1470 if (dmamap == NULL) { 1471 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1472 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1473 if (error != 0) 1474 return error; 1475 } 1476 1477 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1478 1479 if (m == NULL) { 1480 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1481 if (m_new == NULL) 1482 return ENOBUFS; 1483 1484 MCLGET(m_new, M_DONTWAIT); 1485 if (!(m_new->m_flags & M_EXT)) { 1486 m_freem(m_new); 1487 return ENOBUFS; 1488 } 1489 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1490 1491 } else { 1492 m_new = m; 1493 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1494 m_new->m_data = m_new->m_ext.ext_buf; 1495 } 1496 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1497 m_adj(m_new, ETHER_ALIGN); 1498 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1499 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1500 m_freem(m_new); 1501 return ENOBUFS; 1502 } 1503 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1504 BUS_DMASYNC_PREREAD); 1505 1506 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1507 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1508 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1509 r->bge_flags = BGE_RXBDFLAG_END; 1510 r->bge_len = m_new->m_len; 1511 r->bge_idx = i; 1512 1513 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1514 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1515 i * sizeof (struct bge_rx_bd), 1516 sizeof (struct bge_rx_bd), 1517 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1518 1519 return 0; 1520 } 1521 1522 /* 1523 * Initialize a jumbo receive ring descriptor. This allocates 1524 * a jumbo buffer from the pool managed internally by the driver. 1525 */ 1526 static int 1527 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1528 { 1529 struct mbuf *m_new = NULL; 1530 struct bge_rx_bd *r; 1531 void *buf = NULL; 1532 1533 if (m == NULL) { 1534 1535 /* Allocate the mbuf. */ 1536 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1537 if (m_new == NULL) 1538 return ENOBUFS; 1539 1540 /* Allocate the jumbo buffer */ 1541 buf = bge_jalloc(sc); 1542 if (buf == NULL) { 1543 m_freem(m_new); 1544 aprint_error_dev(sc->bge_dev, 1545 "jumbo allocation failed -- packet dropped!\n"); 1546 return ENOBUFS; 1547 } 1548 1549 /* Attach the buffer to the mbuf. */ 1550 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1551 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1552 bge_jfree, sc); 1553 m_new->m_flags |= M_EXT_RW; 1554 } else { 1555 m_new = m; 1556 buf = m_new->m_data = m_new->m_ext.ext_buf; 1557 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1558 } 1559 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1560 m_adj(m_new, ETHER_ALIGN); 1561 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1562 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1563 BGE_JLEN, BUS_DMASYNC_PREREAD); 1564 /* Set up the descriptor. */ 1565 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1566 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1567 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1568 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1569 r->bge_len = m_new->m_len; 1570 r->bge_idx = i; 1571 1572 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1573 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1574 i * sizeof (struct bge_rx_bd), 1575 sizeof (struct bge_rx_bd), 1576 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1577 1578 return 0; 1579 } 1580 1581 /* 1582 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1583 * that's 1MB or memory, which is a lot. For now, we fill only the first 1584 * 256 ring entries and hope that our CPU is fast enough to keep up with 1585 * the NIC. 1586 */ 1587 static int 1588 bge_init_rx_ring_std(struct bge_softc *sc) 1589 { 1590 int i; 1591 1592 if (sc->bge_flags & BGEF_RXRING_VALID) 1593 return 0; 1594 1595 for (i = 0; i < BGE_SSLOTS; i++) { 1596 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1597 return ENOBUFS; 1598 } 1599 1600 sc->bge_std = i - 1; 1601 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1602 1603 sc->bge_flags |= BGEF_RXRING_VALID; 1604 1605 return 0; 1606 } 1607 1608 static void 1609 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1610 { 1611 int i; 1612 1613 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1614 return; 1615 1616 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1617 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1618 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1619 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1620 if (disable) { 1621 bus_dmamap_destroy(sc->bge_dmatag, 1622 sc->bge_cdata.bge_rx_std_map[i]); 1623 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1624 } 1625 } 1626 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1627 sizeof(struct bge_rx_bd)); 1628 } 1629 1630 sc->bge_flags &= ~BGEF_RXRING_VALID; 1631 } 1632 1633 static int 1634 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1635 { 1636 int i; 1637 volatile struct bge_rcb *rcb; 1638 1639 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1640 return 0; 1641 1642 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1643 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1644 return ENOBUFS; 1645 } 1646 1647 sc->bge_jumbo = i - 1; 1648 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1649 1650 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1651 rcb->bge_maxlen_flags = 0; 1652 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1653 1654 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1655 1656 return 0; 1657 } 1658 1659 static void 1660 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1661 { 1662 int i; 1663 1664 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1665 return; 1666 1667 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1668 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1669 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1670 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1671 } 1672 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1673 sizeof(struct bge_rx_bd)); 1674 } 1675 1676 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1677 } 1678 1679 static void 1680 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1681 { 1682 int i; 1683 struct txdmamap_pool_entry *dma; 1684 1685 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1686 return; 1687 1688 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1689 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1690 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1691 sc->bge_cdata.bge_tx_chain[i] = NULL; 1692 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1693 link); 1694 sc->txdma[i] = 0; 1695 } 1696 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1697 sizeof(struct bge_tx_bd)); 1698 } 1699 1700 if (disable) { 1701 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1702 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1703 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1704 if (sc->bge_dma64) { 1705 bus_dmamap_destroy(sc->bge_dmatag32, 1706 dma->dmamap32); 1707 } 1708 free(dma, M_DEVBUF); 1709 } 1710 SLIST_INIT(&sc->txdma_list); 1711 } 1712 1713 sc->bge_flags &= ~BGEF_TXRING_VALID; 1714 } 1715 1716 static int 1717 bge_init_tx_ring(struct bge_softc *sc) 1718 { 1719 struct ifnet *ifp = &sc->ethercom.ec_if; 1720 int i; 1721 bus_dmamap_t dmamap, dmamap32; 1722 bus_size_t maxsegsz; 1723 struct txdmamap_pool_entry *dma; 1724 1725 if (sc->bge_flags & BGEF_TXRING_VALID) 1726 return 0; 1727 1728 sc->bge_txcnt = 0; 1729 sc->bge_tx_saved_considx = 0; 1730 1731 /* Initialize transmit producer index for host-memory send ring. */ 1732 sc->bge_tx_prodidx = 0; 1733 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1734 /* 5700 b2 errata */ 1735 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1736 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1737 1738 /* NIC-memory send ring not used; initialize to zero. */ 1739 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1740 /* 5700 b2 errata */ 1741 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1742 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1743 1744 /* Limit DMA segment size for some chips */ 1745 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1746 (ifp->if_mtu <= ETHERMTU)) 1747 maxsegsz = 2048; 1748 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1749 maxsegsz = 4096; 1750 else 1751 maxsegsz = ETHER_MAX_LEN_JUMBO; 1752 1753 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1754 goto alloc_done; 1755 1756 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1757 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1758 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1759 &dmamap)) 1760 return ENOBUFS; 1761 if (dmamap == NULL) 1762 panic("dmamap NULL in bge_init_tx_ring"); 1763 if (sc->bge_dma64) { 1764 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1765 BGE_NTXSEG, maxsegsz, 0, 1766 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1767 &dmamap32)) { 1768 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1769 return ENOBUFS; 1770 } 1771 if (dmamap32 == NULL) 1772 panic("dmamap32 NULL in bge_init_tx_ring"); 1773 } else 1774 dmamap32 = dmamap; 1775 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1776 if (dma == NULL) { 1777 aprint_error_dev(sc->bge_dev, 1778 "can't alloc txdmamap_pool_entry\n"); 1779 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1780 if (sc->bge_dma64) 1781 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1782 return ENOMEM; 1783 } 1784 dma->dmamap = dmamap; 1785 dma->dmamap32 = dmamap32; 1786 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1787 } 1788 alloc_done: 1789 sc->bge_flags |= BGEF_TXRING_VALID; 1790 1791 return 0; 1792 } 1793 1794 static void 1795 bge_setmulti(struct bge_softc *sc) 1796 { 1797 struct ethercom *ec = &sc->ethercom; 1798 struct ifnet *ifp = &ec->ec_if; 1799 struct ether_multi *enm; 1800 struct ether_multistep step; 1801 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1802 uint32_t h; 1803 int i; 1804 1805 if (ifp->if_flags & IFF_PROMISC) 1806 goto allmulti; 1807 1808 /* Now program new ones. */ 1809 ETHER_FIRST_MULTI(step, ec, enm); 1810 while (enm != NULL) { 1811 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1812 /* 1813 * We must listen to a range of multicast addresses. 1814 * For now, just accept all multicasts, rather than 1815 * trying to set only those filter bits needed to match 1816 * the range. (At this time, the only use of address 1817 * ranges is for IP multicast routing, for which the 1818 * range is big enough to require all bits set.) 1819 */ 1820 goto allmulti; 1821 } 1822 1823 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1824 1825 /* Just want the 7 least-significant bits. */ 1826 h &= 0x7f; 1827 1828 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1829 ETHER_NEXT_MULTI(step, enm); 1830 } 1831 1832 ifp->if_flags &= ~IFF_ALLMULTI; 1833 goto setit; 1834 1835 allmulti: 1836 ifp->if_flags |= IFF_ALLMULTI; 1837 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1838 1839 setit: 1840 for (i = 0; i < 4; i++) 1841 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1842 } 1843 1844 static void 1845 bge_sig_pre_reset(struct bge_softc *sc, int type) 1846 { 1847 1848 /* 1849 * Some chips don't like this so only do this if ASF is enabled 1850 */ 1851 if (sc->bge_asf_mode) 1852 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1853 1854 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1855 switch (type) { 1856 case BGE_RESET_START: 1857 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1858 BGE_FW_DRV_STATE_START); 1859 break; 1860 case BGE_RESET_SHUTDOWN: 1861 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1862 BGE_FW_DRV_STATE_UNLOAD); 1863 break; 1864 case BGE_RESET_SUSPEND: 1865 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1866 BGE_FW_DRV_STATE_SUSPEND); 1867 break; 1868 } 1869 } 1870 1871 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1872 bge_ape_driver_state_change(sc, type); 1873 } 1874 1875 static void 1876 bge_sig_post_reset(struct bge_softc *sc, int type) 1877 { 1878 1879 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1880 switch (type) { 1881 case BGE_RESET_START: 1882 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1883 BGE_FW_DRV_STATE_START_DONE); 1884 /* START DONE */ 1885 break; 1886 case BGE_RESET_SHUTDOWN: 1887 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1888 BGE_FW_DRV_STATE_UNLOAD_DONE); 1889 break; 1890 } 1891 } 1892 1893 if (type == BGE_RESET_SHUTDOWN) 1894 bge_ape_driver_state_change(sc, type); 1895 } 1896 1897 static void 1898 bge_sig_legacy(struct bge_softc *sc, int type) 1899 { 1900 1901 if (sc->bge_asf_mode) { 1902 switch (type) { 1903 case BGE_RESET_START: 1904 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1905 BGE_FW_DRV_STATE_START); 1906 break; 1907 case BGE_RESET_SHUTDOWN: 1908 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1909 BGE_FW_DRV_STATE_UNLOAD); 1910 break; 1911 } 1912 } 1913 } 1914 1915 static void 1916 bge_wait_for_event_ack(struct bge_softc *sc) 1917 { 1918 int i; 1919 1920 /* wait up to 2500usec */ 1921 for (i = 0; i < 250; i++) { 1922 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1923 BGE_RX_CPU_DRV_EVENT)) 1924 break; 1925 DELAY(10); 1926 } 1927 } 1928 1929 static void 1930 bge_stop_fw(struct bge_softc *sc) 1931 { 1932 1933 if (sc->bge_asf_mode) { 1934 bge_wait_for_event_ack(sc); 1935 1936 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1937 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1938 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1939 1940 bge_wait_for_event_ack(sc); 1941 } 1942 } 1943 1944 static int 1945 bge_poll_fw(struct bge_softc *sc) 1946 { 1947 uint32_t val; 1948 int i; 1949 1950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1951 for (i = 0; i < BGE_TIMEOUT; i++) { 1952 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1953 if (val & BGE_VCPU_STATUS_INIT_DONE) 1954 break; 1955 DELAY(100); 1956 } 1957 if (i >= BGE_TIMEOUT) { 1958 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1959 return -1; 1960 } 1961 } else { 1962 /* 1963 * Poll the value location we just wrote until 1964 * we see the 1's complement of the magic number. 1965 * This indicates that the firmware initialization 1966 * is complete. 1967 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1968 */ 1969 for (i = 0; i < BGE_TIMEOUT; i++) { 1970 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1971 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1972 break; 1973 DELAY(10); 1974 } 1975 1976 if ((i >= BGE_TIMEOUT) 1977 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1978 aprint_error_dev(sc->bge_dev, 1979 "firmware handshake timed out, val = %x\n", val); 1980 return -1; 1981 } 1982 } 1983 1984 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1985 /* tg3 says we have to wait extra time */ 1986 delay(10 * 1000); 1987 } 1988 1989 return 0; 1990 } 1991 1992 int 1993 bge_phy_addr(struct bge_softc *sc) 1994 { 1995 struct pci_attach_args *pa = &(sc->bge_pa); 1996 int phy_addr = 1; 1997 1998 /* 1999 * PHY address mapping for various devices. 2000 * 2001 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2002 * ---------+-------+-------+-------+-------+ 2003 * BCM57XX | 1 | X | X | X | 2004 * BCM5704 | 1 | X | 1 | X | 2005 * BCM5717 | 1 | 8 | 2 | 9 | 2006 * BCM5719 | 1 | 8 | 2 | 9 | 2007 * BCM5720 | 1 | 8 | 2 | 9 | 2008 * 2009 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2010 * ---------+-------+-------+-------+-------+ 2011 * BCM57XX | X | X | X | X | 2012 * BCM5704 | X | X | X | X | 2013 * BCM5717 | X | X | X | X | 2014 * BCM5719 | 3 | 10 | 4 | 11 | 2015 * BCM5720 | X | X | X | X | 2016 * 2017 * Other addresses may respond but they are not 2018 * IEEE compliant PHYs and should be ignored. 2019 */ 2020 switch (BGE_ASICREV(sc->bge_chipid)) { 2021 case BGE_ASICREV_BCM5717: 2022 case BGE_ASICREV_BCM5719: 2023 case BGE_ASICREV_BCM5720: 2024 phy_addr = pa->pa_function; 2025 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2026 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2027 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2028 } else { 2029 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2030 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2031 } 2032 } 2033 2034 return phy_addr; 2035 } 2036 2037 /* 2038 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2039 * self-test results. 2040 */ 2041 static int 2042 bge_chipinit(struct bge_softc *sc) 2043 { 2044 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2045 int i; 2046 2047 /* Set endianness before we access any non-PCI registers. */ 2048 misc_ctl = BGE_INIT; 2049 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2050 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2051 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2052 misc_ctl); 2053 2054 /* 2055 * Clear the MAC statistics block in the NIC's 2056 * internal memory. 2057 */ 2058 for (i = BGE_STATS_BLOCK; 2059 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2060 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2061 2062 for (i = BGE_STATUS_BLOCK; 2063 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2064 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2065 2066 /* 5717 workaround from tg3 */ 2067 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2068 /* Save */ 2069 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2070 2071 /* Temporary modify MODE_CTL to control TLP */ 2072 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2073 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2074 2075 /* Control TLP */ 2076 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2077 BGE_TLP_PHYCTL1); 2078 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2079 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2080 2081 /* Restore */ 2082 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2083 } 2084 2085 if (BGE_IS_57765_FAMILY(sc)) { 2086 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2087 /* Save */ 2088 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2089 2090 /* Temporary modify MODE_CTL to control TLP */ 2091 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2092 CSR_WRITE_4(sc, BGE_MODE_CTL, 2093 reg | BGE_MODECTL_PCIE_TLPADDR1); 2094 2095 /* Control TLP */ 2096 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2097 BGE_TLP_PHYCTL5); 2098 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2099 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2100 2101 /* Restore */ 2102 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2103 } 2104 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2105 /* 2106 * For the 57766 and non Ax versions of 57765, bootcode 2107 * needs to setup the PCIE Fast Training Sequence (FTS) 2108 * value to prevent transmit hangs. 2109 */ 2110 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2111 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2112 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2113 2114 /* Save */ 2115 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2116 2117 /* Temporary modify MODE_CTL to control TLP */ 2118 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2119 CSR_WRITE_4(sc, BGE_MODE_CTL, 2120 reg | BGE_MODECTL_PCIE_TLPADDR0); 2121 2122 /* Control TLP */ 2123 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2124 BGE_TLP_FTSMAX); 2125 reg &= ~BGE_TLP_FTSMAX_MSK; 2126 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2127 reg | BGE_TLP_FTSMAX_VAL); 2128 2129 /* Restore */ 2130 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2131 } 2132 2133 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2134 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2135 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2136 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2137 } 2138 2139 /* Set up the PCI DMA control register. */ 2140 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2141 if (sc->bge_flags & BGEF_PCIE) { 2142 /* Read watermark not used, 128 bytes for write. */ 2143 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2144 device_xname(sc->bge_dev))); 2145 if (sc->bge_mps >= 256) 2146 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2147 else 2148 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2149 } else if (sc->bge_flags & BGEF_PCIX) { 2150 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2151 device_xname(sc->bge_dev))); 2152 /* PCI-X bus */ 2153 if (BGE_IS_5714_FAMILY(sc)) { 2154 /* 256 bytes for read and write. */ 2155 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2156 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2157 2158 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2159 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2160 else 2161 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2162 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2163 /* 2164 * In the BCM5703, the DMA read watermark should 2165 * be set to less than or equal to the maximum 2166 * memory read byte count of the PCI-X command 2167 * register. 2168 */ 2169 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2170 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2171 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2172 /* 1536 bytes for read, 384 bytes for write. */ 2173 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2174 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2175 } else { 2176 /* 384 bytes for read and write. */ 2177 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2178 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2179 (0x0F); 2180 } 2181 2182 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2183 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2184 uint32_t tmp; 2185 2186 /* Set ONEDMA_ATONCE for hardware workaround. */ 2187 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2188 if (tmp == 6 || tmp == 7) 2189 dma_rw_ctl |= 2190 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2191 2192 /* Set PCI-X DMA write workaround. */ 2193 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2194 } 2195 } else { 2196 /* Conventional PCI bus: 256 bytes for read and write. */ 2197 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2198 device_xname(sc->bge_dev))); 2199 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2200 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2201 2202 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2203 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2204 dma_rw_ctl |= 0x0F; 2205 } 2206 2207 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2208 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2209 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2210 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2211 2212 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2213 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2214 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2215 2216 if (BGE_IS_57765_PLUS(sc)) { 2217 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2218 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2219 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2220 2221 /* 2222 * Enable HW workaround for controllers that misinterpret 2223 * a status tag update and leave interrupts permanently 2224 * disabled. 2225 */ 2226 if (!BGE_IS_57765_FAMILY(sc) && 2227 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2228 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2229 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2230 } 2231 2232 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2233 dma_rw_ctl); 2234 2235 /* 2236 * Set up general mode register. 2237 */ 2238 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2239 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2240 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2241 /* Retain Host-2-BMC settings written by APE firmware. */ 2242 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2243 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2244 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2245 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2246 } 2247 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2248 BGE_MODECTL_TX_NO_PHDR_CSUM; 2249 2250 /* 2251 * BCM5701 B5 have a bug causing data corruption when using 2252 * 64-bit DMA reads, which can be terminated early and then 2253 * completed later as 32-bit accesses, in combination with 2254 * certain bridges. 2255 */ 2256 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2257 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2258 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2259 2260 /* 2261 * Tell the firmware the driver is running 2262 */ 2263 if (sc->bge_asf_mode & ASF_STACKUP) 2264 mode_ctl |= BGE_MODECTL_STACKUP; 2265 2266 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2267 2268 /* 2269 * Disable memory write invalidate. Apparently it is not supported 2270 * properly by these devices. 2271 */ 2272 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2273 PCI_COMMAND_INVALIDATE_ENABLE); 2274 2275 #ifdef __brokenalpha__ 2276 /* 2277 * Must insure that we do not cross an 8K (bytes) boundary 2278 * for DMA reads. Our highest limit is 1K bytes. This is a 2279 * restriction on some ALPHA platforms with early revision 2280 * 21174 PCI chipsets, such as the AlphaPC 164lx 2281 */ 2282 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2283 #endif 2284 2285 /* Set the timer prescaler (always 66MHz) */ 2286 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2287 2288 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2289 DELAY(40); /* XXX */ 2290 2291 /* Put PHY into ready state */ 2292 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2293 DELAY(40); 2294 } 2295 2296 return 0; 2297 } 2298 2299 static int 2300 bge_blockinit(struct bge_softc *sc) 2301 { 2302 volatile struct bge_rcb *rcb; 2303 bus_size_t rcb_addr; 2304 struct ifnet *ifp = &sc->ethercom.ec_if; 2305 bge_hostaddr taddr; 2306 uint32_t dmactl, rdmareg, mimode, val; 2307 int i, limit; 2308 2309 /* 2310 * Initialize the memory window pointer register so that 2311 * we can access the first 32K of internal NIC RAM. This will 2312 * allow us to set up the TX send ring RCBs and the RX return 2313 * ring RCBs, plus other things which live in NIC memory. 2314 */ 2315 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2316 2317 if (!BGE_IS_5705_PLUS(sc)) { 2318 /* 57XX step 33 */ 2319 /* Configure mbuf memory pool */ 2320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2321 2322 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2323 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2324 else 2325 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2326 2327 /* 57XX step 34 */ 2328 /* Configure DMA resource pool */ 2329 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2330 BGE_DMA_DESCRIPTORS); 2331 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2332 } 2333 2334 /* 5718 step 11, 57XX step 35 */ 2335 /* 2336 * Configure mbuf pool watermarks. New broadcom docs strongly 2337 * recommend these. 2338 */ 2339 if (BGE_IS_5717_PLUS(sc)) { 2340 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2341 if (ifp->if_mtu > ETHERMTU) { 2342 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2344 } else { 2345 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2346 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2347 } 2348 } else if (BGE_IS_5705_PLUS(sc)) { 2349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2350 2351 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2354 } else { 2355 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2356 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2357 } 2358 } else { 2359 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2360 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2362 } 2363 2364 /* 57XX step 36 */ 2365 /* Configure DMA resource watermarks */ 2366 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2367 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2368 2369 /* 5718 step 13, 57XX step 38 */ 2370 /* Enable buffer manager */ 2371 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2372 /* 2373 * Change the arbitration algorithm of TXMBUF read request to 2374 * round-robin instead of priority based for BCM5719. When 2375 * TXFIFO is almost empty, RDMA will hold its request until 2376 * TXFIFO is not almost empty. 2377 */ 2378 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2379 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2380 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2381 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2382 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2383 val |= BGE_BMANMODE_LOMBUF_ATTN; 2384 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2385 2386 /* 57XX step 39 */ 2387 /* Poll for buffer manager start indication */ 2388 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2389 DELAY(10); 2390 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2391 break; 2392 } 2393 2394 if (i == BGE_TIMEOUT * 2) { 2395 aprint_error_dev(sc->bge_dev, 2396 "buffer manager failed to start\n"); 2397 return ENXIO; 2398 } 2399 2400 /* 57XX step 40 */ 2401 /* Enable flow-through queues */ 2402 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2403 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2404 2405 /* Wait until queue initialization is complete */ 2406 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2407 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2408 break; 2409 DELAY(10); 2410 } 2411 2412 if (i == BGE_TIMEOUT * 2) { 2413 aprint_error_dev(sc->bge_dev, 2414 "flow-through queue init failed\n"); 2415 return ENXIO; 2416 } 2417 2418 /* 2419 * Summary of rings supported by the controller: 2420 * 2421 * Standard Receive Producer Ring 2422 * - This ring is used to feed receive buffers for "standard" 2423 * sized frames (typically 1536 bytes) to the controller. 2424 * 2425 * Jumbo Receive Producer Ring 2426 * - This ring is used to feed receive buffers for jumbo sized 2427 * frames (i.e. anything bigger than the "standard" frames) 2428 * to the controller. 2429 * 2430 * Mini Receive Producer Ring 2431 * - This ring is used to feed receive buffers for "mini" 2432 * sized frames to the controller. 2433 * - This feature required external memory for the controller 2434 * but was never used in a production system. Should always 2435 * be disabled. 2436 * 2437 * Receive Return Ring 2438 * - After the controller has placed an incoming frame into a 2439 * receive buffer that buffer is moved into a receive return 2440 * ring. The driver is then responsible to passing the 2441 * buffer up to the stack. Many versions of the controller 2442 * support multiple RR rings. 2443 * 2444 * Send Ring 2445 * - This ring is used for outgoing frames. Many versions of 2446 * the controller support multiple send rings. 2447 */ 2448 2449 /* 5718 step 15, 57XX step 41 */ 2450 /* Initialize the standard RX ring control block */ 2451 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2452 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2453 /* 5718 step 16 */ 2454 if (BGE_IS_57765_PLUS(sc)) { 2455 /* 2456 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2457 * Bits 15-2 : Maximum RX frame size 2458 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2459 * Bit 0 : Reserved 2460 */ 2461 rcb->bge_maxlen_flags = 2462 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2463 } else if (BGE_IS_5705_PLUS(sc)) { 2464 /* 2465 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2466 * Bits 15-2 : Reserved (should be 0) 2467 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2468 * Bit 0 : Reserved 2469 */ 2470 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2471 } else { 2472 /* 2473 * Ring size is always XXX entries 2474 * Bits 31-16: Maximum RX frame size 2475 * Bits 15-2 : Reserved (should be 0) 2476 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2477 * Bit 0 : Reserved 2478 */ 2479 rcb->bge_maxlen_flags = 2480 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2481 } 2482 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2483 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2485 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2486 else 2487 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2488 /* Write the standard receive producer ring control block. */ 2489 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2490 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2491 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2492 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2493 2494 /* Reset the standard receive producer ring producer index. */ 2495 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2496 2497 /* 57XX step 42 */ 2498 /* 2499 * Initialize the jumbo RX ring control block 2500 * We set the 'ring disabled' bit in the flags 2501 * field until we're actually ready to start 2502 * using this ring (i.e. once we set the MTU 2503 * high enough to require it). 2504 */ 2505 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2506 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2507 BGE_HOSTADDR(rcb->bge_hostaddr, 2508 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2509 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2510 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2511 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2512 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2513 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2514 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2515 else 2516 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2517 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2518 rcb->bge_hostaddr.bge_addr_hi); 2519 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2520 rcb->bge_hostaddr.bge_addr_lo); 2521 /* Program the jumbo receive producer ring RCB parameters. */ 2522 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2523 rcb->bge_maxlen_flags); 2524 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2525 /* Reset the jumbo receive producer ring producer index. */ 2526 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2527 } 2528 2529 /* 57XX step 43 */ 2530 /* Disable the mini receive producer ring RCB. */ 2531 if (BGE_IS_5700_FAMILY(sc)) { 2532 /* Set up dummy disabled mini ring RCB */ 2533 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2534 rcb->bge_maxlen_flags = 2535 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2536 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2537 rcb->bge_maxlen_flags); 2538 /* Reset the mini receive producer ring producer index. */ 2539 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2540 2541 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2542 offsetof(struct bge_ring_data, bge_info), 2543 sizeof (struct bge_gib), 2544 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2545 } 2546 2547 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2548 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2549 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2550 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2551 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2552 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2553 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2554 } 2555 /* 5718 step 14, 57XX step 44 */ 2556 /* 2557 * The BD ring replenish thresholds control how often the 2558 * hardware fetches new BD's from the producer rings in host 2559 * memory. Setting the value too low on a busy system can 2560 * starve the hardware and recue the throughpout. 2561 * 2562 * Set the BD ring replenish thresholds. The recommended 2563 * values are 1/8th the number of descriptors allocated to 2564 * each ring, but since we try to avoid filling the entire 2565 * ring we set these to the minimal value of 8. This needs to 2566 * be done on several of the supported chip revisions anyway, 2567 * to work around HW bugs. 2568 */ 2569 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2570 if (BGE_IS_JUMBO_CAPABLE(sc)) 2571 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2572 2573 /* 5718 step 18 */ 2574 if (BGE_IS_5717_PLUS(sc)) { 2575 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2576 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2577 } 2578 2579 /* 57XX step 45 */ 2580 /* 2581 * Disable all send rings by setting the 'ring disabled' bit 2582 * in the flags field of all the TX send ring control blocks, 2583 * located in NIC memory. 2584 */ 2585 if (BGE_IS_5700_FAMILY(sc)) { 2586 /* 5700 to 5704 had 16 send rings. */ 2587 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2588 } else if (BGE_IS_5717_PLUS(sc)) { 2589 limit = BGE_TX_RINGS_5717_MAX; 2590 } else if (BGE_IS_57765_FAMILY(sc) || 2591 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2592 limit = BGE_TX_RINGS_57765_MAX; 2593 } else 2594 limit = 1; 2595 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2596 for (i = 0; i < limit; i++) { 2597 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2598 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2599 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2600 rcb_addr += sizeof(struct bge_rcb); 2601 } 2602 2603 /* 57XX step 46 and 47 */ 2604 /* Configure send ring RCB 0 (we use only the first ring) */ 2605 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2606 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2607 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2608 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2609 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2610 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2611 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2612 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2613 else 2614 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2615 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2616 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2617 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2618 2619 /* 57XX step 48 */ 2620 /* 2621 * Disable all receive return rings by setting the 2622 * 'ring diabled' bit in the flags field of all the receive 2623 * return ring control blocks, located in NIC memory. 2624 */ 2625 if (BGE_IS_5717_PLUS(sc)) { 2626 /* Should be 17, use 16 until we get an SRAM map. */ 2627 limit = 16; 2628 } else if (BGE_IS_5700_FAMILY(sc)) 2629 limit = BGE_RX_RINGS_MAX; 2630 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2631 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2632 BGE_IS_57765_FAMILY(sc)) 2633 limit = 4; 2634 else 2635 limit = 1; 2636 /* Disable all receive return rings */ 2637 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2638 for (i = 0; i < limit; i++) { 2639 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2640 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2641 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2642 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2643 BGE_RCB_FLAG_RING_DISABLED)); 2644 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2645 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2646 (i * (sizeof(uint64_t))), 0); 2647 rcb_addr += sizeof(struct bge_rcb); 2648 } 2649 2650 /* 57XX step 49 */ 2651 /* 2652 * Set up receive return ring 0. Note that the NIC address 2653 * for RX return rings is 0x0. The return rings live entirely 2654 * within the host, so the nicaddr field in the RCB isn't used. 2655 */ 2656 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2657 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2658 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2659 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2660 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2661 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2662 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2663 2664 /* 5718 step 24, 57XX step 53 */ 2665 /* Set random backoff seed for TX */ 2666 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2667 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2668 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2669 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2670 BGE_TX_BACKOFF_SEED_MASK); 2671 2672 /* 5718 step 26, 57XX step 55 */ 2673 /* Set inter-packet gap */ 2674 val = 0x2620; 2675 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2676 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2677 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2678 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2679 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2680 2681 /* 5718 step 27, 57XX step 56 */ 2682 /* 2683 * Specify which ring to use for packets that don't match 2684 * any RX rules. 2685 */ 2686 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2687 2688 /* 5718 step 28, 57XX step 57 */ 2689 /* 2690 * Configure number of RX lists. One interrupt distribution 2691 * list, sixteen active lists, one bad frames class. 2692 */ 2693 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2694 2695 /* 5718 step 29, 57XX step 58 */ 2696 /* Inialize RX list placement stats mask. */ 2697 if (BGE_IS_575X_PLUS(sc)) { 2698 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2699 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2700 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2701 } else 2702 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2703 2704 /* 5718 step 30, 57XX step 59 */ 2705 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2706 2707 /* 5718 step 33, 57XX step 62 */ 2708 /* Disable host coalescing until we get it set up */ 2709 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2710 2711 /* 5718 step 34, 57XX step 63 */ 2712 /* Poll to make sure it's shut down. */ 2713 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2714 DELAY(10); 2715 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2716 break; 2717 } 2718 2719 if (i == BGE_TIMEOUT * 2) { 2720 aprint_error_dev(sc->bge_dev, 2721 "host coalescing engine failed to idle\n"); 2722 return ENXIO; 2723 } 2724 2725 /* 5718 step 35, 36, 37 */ 2726 /* Set up host coalescing defaults */ 2727 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2728 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2729 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2730 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2731 if (!(BGE_IS_5705_PLUS(sc))) { 2732 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2733 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2734 } 2735 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2736 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2737 2738 /* Set up address of statistics block */ 2739 if (BGE_IS_5700_FAMILY(sc)) { 2740 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2741 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2742 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2743 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2744 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2745 } 2746 2747 /* 5718 step 38 */ 2748 /* Set up address of status block */ 2749 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2750 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2751 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2752 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2753 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2754 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2755 2756 /* Set up status block size. */ 2757 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2758 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2759 val = BGE_STATBLKSZ_FULL; 2760 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2761 } else { 2762 val = BGE_STATBLKSZ_32BYTE; 2763 bzero(&sc->bge_rdata->bge_status_block, 32); 2764 } 2765 2766 /* 5718 step 39, 57XX step 73 */ 2767 /* Turn on host coalescing state machine */ 2768 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2769 2770 /* 5718 step 40, 57XX step 74 */ 2771 /* Turn on RX BD completion state machine and enable attentions */ 2772 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2773 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2774 2775 /* 5718 step 41, 57XX step 75 */ 2776 /* Turn on RX list placement state machine */ 2777 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2778 2779 /* 57XX step 76 */ 2780 /* Turn on RX list selector state machine. */ 2781 if (!(BGE_IS_5705_PLUS(sc))) 2782 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2783 2784 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2785 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2786 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2787 BGE_MACMODE_FRMHDR_DMA_ENB; 2788 2789 if (sc->bge_flags & BGEF_FIBER_TBI) 2790 val |= BGE_PORTMODE_TBI; 2791 else if (sc->bge_flags & BGEF_FIBER_MII) 2792 val |= BGE_PORTMODE_GMII; 2793 else 2794 val |= BGE_PORTMODE_MII; 2795 2796 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2797 /* Allow APE to send/receive frames. */ 2798 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2799 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2800 2801 /* Turn on DMA, clear stats */ 2802 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2803 /* 5718 step 44 */ 2804 DELAY(40); 2805 2806 /* 5718 step 45, 57XX step 79 */ 2807 /* Set misc. local control, enable interrupts on attentions */ 2808 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2809 if (BGE_IS_5717_PLUS(sc)) { 2810 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2811 /* 5718 step 46 */ 2812 DELAY(100); 2813 } 2814 2815 /* 57XX step 81 */ 2816 /* Turn on DMA completion state machine */ 2817 if (!(BGE_IS_5705_PLUS(sc))) 2818 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2819 2820 /* 5718 step 47, 57XX step 82 */ 2821 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2822 2823 /* 5718 step 48 */ 2824 /* Enable host coalescing bug fix. */ 2825 if (BGE_IS_5755_PLUS(sc)) 2826 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2827 2828 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2829 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2830 2831 /* Turn on write DMA state machine */ 2832 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2833 /* 5718 step 49 */ 2834 DELAY(40); 2835 2836 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2837 2838 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2839 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2840 2841 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2842 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2843 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2844 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2845 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2846 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2847 2848 if (sc->bge_flags & BGEF_PCIE) 2849 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2850 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2851 if (ifp->if_mtu <= ETHERMTU) 2852 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2853 } 2854 if (sc->bge_flags & BGEF_TSO) { 2855 val |= BGE_RDMAMODE_TSO4_ENABLE; 2856 if (BGE_IS_5717_PLUS(sc)) 2857 val |= BGE_RDMAMODE_TSO6_ENABLE; 2858 } 2859 2860 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2861 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2862 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2863 BGE_RDMAMODE_H2BNC_VLAN_DET; 2864 /* 2865 * Allow multiple outstanding read requests from 2866 * non-LSO read DMA engine. 2867 */ 2868 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2869 } 2870 2871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2872 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2873 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2874 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2875 BGE_IS_57765_PLUS(sc)) { 2876 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2877 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2878 else 2879 rdmareg = BGE_RDMA_RSRVCTRL; 2880 dmactl = CSR_READ_4(sc, rdmareg); 2881 /* 2882 * Adjust tx margin to prevent TX data corruption and 2883 * fix internal FIFO overflow. 2884 */ 2885 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2886 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2887 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2888 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2889 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2890 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2891 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2892 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2893 } 2894 /* 2895 * Enable fix for read DMA FIFO overruns. 2896 * The fix is to limit the number of RX BDs 2897 * the hardware would fetch at a fime. 2898 */ 2899 CSR_WRITE_4(sc, rdmareg, dmactl | 2900 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2901 } 2902 2903 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2904 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2905 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2906 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2907 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2908 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2909 /* 2910 * Allow 4KB burst length reads for non-LSO frames. 2911 * Enable 512B burst length reads for buffer descriptors. 2912 */ 2913 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2914 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2915 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2916 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2917 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2918 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2919 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2920 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2921 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2922 } 2923 /* Turn on read DMA state machine */ 2924 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2925 /* 5718 step 52 */ 2926 delay(40); 2927 2928 if (sc->bge_flags & BGEF_RDMA_BUG) { 2929 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2930 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2931 if ((val & 0xFFFF) > BGE_FRAMELEN) 2932 break; 2933 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2934 break; 2935 } 2936 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2937 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2938 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2939 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2940 else 2941 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2942 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2943 } 2944 } 2945 2946 /* 5718 step 56, 57XX step 84 */ 2947 /* Turn on RX data completion state machine */ 2948 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2949 2950 /* Turn on RX data and RX BD initiator state machine */ 2951 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2952 2953 /* 57XX step 85 */ 2954 /* Turn on Mbuf cluster free state machine */ 2955 if (!BGE_IS_5705_PLUS(sc)) 2956 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2957 2958 /* 5718 step 57, 57XX step 86 */ 2959 /* Turn on send data completion state machine */ 2960 val = BGE_SDCMODE_ENABLE; 2961 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2962 val |= BGE_SDCMODE_CDELAY; 2963 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2964 2965 /* 5718 step 58 */ 2966 /* Turn on send BD completion state machine */ 2967 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2968 2969 /* 57XX step 88 */ 2970 /* Turn on RX BD initiator state machine */ 2971 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2972 2973 /* 5718 step 60, 57XX step 90 */ 2974 /* Turn on send data initiator state machine */ 2975 if (sc->bge_flags & BGEF_TSO) { 2976 /* XXX: magic value from Linux driver */ 2977 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2978 BGE_SDIMODE_HW_LSO_PRE_DMA); 2979 } else 2980 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2981 2982 /* 5718 step 61, 57XX step 91 */ 2983 /* Turn on send BD initiator state machine */ 2984 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2985 2986 /* 5718 step 62, 57XX step 92 */ 2987 /* Turn on send BD selector state machine */ 2988 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2989 2990 /* 5718 step 31, 57XX step 60 */ 2991 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2992 /* 5718 step 32, 57XX step 61 */ 2993 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2994 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2995 2996 /* ack/clear link change events */ 2997 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2998 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2999 BGE_MACSTAT_LINK_CHANGED); 3000 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3001 3002 /* 3003 * Enable attention when the link has changed state for 3004 * devices that use auto polling. 3005 */ 3006 if (sc->bge_flags & BGEF_FIBER_TBI) { 3007 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3008 } else { 3009 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3010 mimode = BGE_MIMODE_500KHZ_CONST; 3011 else 3012 mimode = BGE_MIMODE_BASE; 3013 /* 5718 step 68. 5718 step 69 (optionally). */ 3014 if (BGE_IS_5700_FAMILY(sc) || 3015 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3016 mimode |= BGE_MIMODE_AUTOPOLL; 3017 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3018 } 3019 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3020 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3021 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3022 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3023 BGE_EVTENB_MI_INTERRUPT); 3024 } 3025 3026 /* 3027 * Clear any pending link state attention. 3028 * Otherwise some link state change events may be lost until attention 3029 * is cleared by bge_intr() -> bge_link_upd() sequence. 3030 * It's not necessary on newer BCM chips - perhaps enabling link 3031 * state change attentions implies clearing pending attention. 3032 */ 3033 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3034 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3035 BGE_MACSTAT_LINK_CHANGED); 3036 3037 /* Enable link state change attentions. */ 3038 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3039 3040 return 0; 3041 } 3042 3043 static const struct bge_revision * 3044 bge_lookup_rev(uint32_t chipid) 3045 { 3046 const struct bge_revision *br; 3047 3048 for (br = bge_revisions; br->br_name != NULL; br++) { 3049 if (br->br_chipid == chipid) 3050 return br; 3051 } 3052 3053 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3054 if (br->br_chipid == BGE_ASICREV(chipid)) 3055 return br; 3056 } 3057 3058 return NULL; 3059 } 3060 3061 static const struct bge_product * 3062 bge_lookup(const struct pci_attach_args *pa) 3063 { 3064 const struct bge_product *bp; 3065 3066 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3067 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3068 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3069 return bp; 3070 } 3071 3072 return NULL; 3073 } 3074 3075 static uint32_t 3076 bge_chipid(const struct pci_attach_args *pa) 3077 { 3078 uint32_t id; 3079 3080 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3081 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3082 3083 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3084 switch (PCI_PRODUCT(pa->pa_id)) { 3085 case PCI_PRODUCT_BROADCOM_BCM5717: 3086 case PCI_PRODUCT_BROADCOM_BCM5718: 3087 case PCI_PRODUCT_BROADCOM_BCM5719: 3088 case PCI_PRODUCT_BROADCOM_BCM5720: 3089 case PCI_PRODUCT_BROADCOM_BCM5725: 3090 case PCI_PRODUCT_BROADCOM_BCM5727: 3091 case PCI_PRODUCT_BROADCOM_BCM5762: 3092 case PCI_PRODUCT_BROADCOM_BCM57764: 3093 case PCI_PRODUCT_BROADCOM_BCM57767: 3094 case PCI_PRODUCT_BROADCOM_BCM57787: 3095 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3096 BGE_PCI_GEN2_PRODID_ASICREV); 3097 break; 3098 case PCI_PRODUCT_BROADCOM_BCM57761: 3099 case PCI_PRODUCT_BROADCOM_BCM57762: 3100 case PCI_PRODUCT_BROADCOM_BCM57765: 3101 case PCI_PRODUCT_BROADCOM_BCM57766: 3102 case PCI_PRODUCT_BROADCOM_BCM57781: 3103 case PCI_PRODUCT_BROADCOM_BCM57782: 3104 case PCI_PRODUCT_BROADCOM_BCM57785: 3105 case PCI_PRODUCT_BROADCOM_BCM57786: 3106 case PCI_PRODUCT_BROADCOM_BCM57791: 3107 case PCI_PRODUCT_BROADCOM_BCM57795: 3108 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3109 BGE_PCI_GEN15_PRODID_ASICREV); 3110 break; 3111 default: 3112 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3113 BGE_PCI_PRODID_ASICREV); 3114 break; 3115 } 3116 } 3117 3118 return id; 3119 } 3120 3121 /* 3122 * Return true if MSI can be used with this device. 3123 */ 3124 static int 3125 bge_can_use_msi(struct bge_softc *sc) 3126 { 3127 int can_use_msi = 0; 3128 3129 switch (BGE_ASICREV(sc->bge_chipid)) { 3130 case BGE_ASICREV_BCM5714_A0: 3131 case BGE_ASICREV_BCM5714: 3132 /* 3133 * Apparently, MSI doesn't work when these chips are 3134 * configured in single-port mode. 3135 */ 3136 break; 3137 case BGE_ASICREV_BCM5750: 3138 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3139 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3140 can_use_msi = 1; 3141 break; 3142 default: 3143 if (BGE_IS_575X_PLUS(sc)) 3144 can_use_msi = 1; 3145 } 3146 return (can_use_msi); 3147 } 3148 3149 /* 3150 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3151 * against our list and return its name if we find a match. Note 3152 * that since the Broadcom controller contains VPD support, we 3153 * can get the device name string from the controller itself instead 3154 * of the compiled-in string. This is a little slow, but it guarantees 3155 * we'll always announce the right product name. 3156 */ 3157 static int 3158 bge_probe(device_t parent, cfdata_t match, void *aux) 3159 { 3160 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3161 3162 if (bge_lookup(pa) != NULL) 3163 return 1; 3164 3165 return 0; 3166 } 3167 3168 static void 3169 bge_attach(device_t parent, device_t self, void *aux) 3170 { 3171 struct bge_softc *sc = device_private(self); 3172 struct pci_attach_args *pa = aux; 3173 prop_dictionary_t dict; 3174 const struct bge_product *bp; 3175 const struct bge_revision *br; 3176 pci_chipset_tag_t pc; 3177 const char *intrstr = NULL; 3178 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3179 uint32_t command; 3180 struct ifnet *ifp; 3181 struct mii_data * const mii = &sc->bge_mii; 3182 uint32_t misccfg, mimode; 3183 void * kva; 3184 u_char eaddr[ETHER_ADDR_LEN]; 3185 pcireg_t memtype, subid, reg; 3186 bus_addr_t memaddr; 3187 uint32_t pm_ctl; 3188 bool no_seeprom; 3189 int capmask; 3190 int mii_flags; 3191 int map_flags; 3192 char intrbuf[PCI_INTRSTR_LEN]; 3193 3194 bp = bge_lookup(pa); 3195 KASSERT(bp != NULL); 3196 3197 sc->sc_pc = pa->pa_pc; 3198 sc->sc_pcitag = pa->pa_tag; 3199 sc->bge_dev = self; 3200 3201 sc->bge_pa = *pa; 3202 pc = sc->sc_pc; 3203 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3204 3205 aprint_naive(": Ethernet controller\n"); 3206 aprint_normal(": %s Ethernet\n", bp->bp_name); 3207 3208 /* 3209 * Map control/status registers. 3210 */ 3211 DPRINTFN(5, ("Map control/status regs\n")); 3212 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3213 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3214 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3215 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3216 3217 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3218 aprint_error_dev(sc->bge_dev, 3219 "failed to enable memory mapping!\n"); 3220 return; 3221 } 3222 3223 DPRINTFN(5, ("pci_mem_find\n")); 3224 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3225 switch (memtype) { 3226 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3227 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3228 #if 0 3229 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3230 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3231 &memaddr, &sc->bge_bsize) == 0) 3232 break; 3233 #else 3234 /* 3235 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3236 * system get NMI on boot (PR#48451). This problem might not be 3237 * the driver's bug but our PCI common part's bug. Until we 3238 * find a real reason, we ignore the prefetchable bit. 3239 */ 3240 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3241 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3242 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3243 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3244 map_flags, &sc->bge_bhandle) == 0) { 3245 sc->bge_btag = pa->pa_memt; 3246 break; 3247 } 3248 } 3249 #endif 3250 /* FALLTHROUGH */ 3251 default: 3252 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3253 return; 3254 } 3255 3256 /* Save various chip information. */ 3257 sc->bge_chipid = bge_chipid(pa); 3258 sc->bge_phy_addr = bge_phy_addr(sc); 3259 3260 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3261 &sc->bge_pciecap, NULL) != 0) { 3262 /* PCIe */ 3263 sc->bge_flags |= BGEF_PCIE; 3264 /* Extract supported maximum payload size. */ 3265 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3266 sc->bge_pciecap + PCIE_DCAP); 3267 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3268 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3269 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3270 sc->bge_expmrq = 2048; 3271 else 3272 sc->bge_expmrq = 4096; 3273 bge_set_max_readrq(sc); 3274 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3275 /* PCIe without PCIe cap */ 3276 sc->bge_flags |= BGEF_PCIE; 3277 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3278 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3279 /* PCI-X */ 3280 sc->bge_flags |= BGEF_PCIX; 3281 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3282 &sc->bge_pcixcap, NULL) == 0) 3283 aprint_error_dev(sc->bge_dev, 3284 "unable to find PCIX capability\n"); 3285 } 3286 3287 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3288 /* 3289 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3290 * can clobber the chip's PCI config-space power control 3291 * registers, leaving the card in D3 powersave state. We do 3292 * not have memory-mapped registers in this state, so force 3293 * device into D0 state before starting initialization. 3294 */ 3295 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3296 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3297 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3298 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3299 DELAY(1000); /* 27 usec is allegedly sufficent */ 3300 } 3301 3302 /* Save chipset family. */ 3303 switch (BGE_ASICREV(sc->bge_chipid)) { 3304 case BGE_ASICREV_BCM5717: 3305 case BGE_ASICREV_BCM5719: 3306 case BGE_ASICREV_BCM5720: 3307 sc->bge_flags |= BGEF_5717_PLUS; 3308 /* FALLTHROUGH */ 3309 case BGE_ASICREV_BCM5762: 3310 case BGE_ASICREV_BCM57765: 3311 case BGE_ASICREV_BCM57766: 3312 if (!BGE_IS_5717_PLUS(sc)) 3313 sc->bge_flags |= BGEF_57765_FAMILY; 3314 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3315 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3316 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3317 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3318 /* 3319 * Enable work around for DMA engine miscalculation 3320 * of TXMBUF available space. 3321 */ 3322 sc->bge_flags |= BGEF_RDMA_BUG; 3323 3324 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3325 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3326 /* Jumbo frame on BCM5719 A0 does not work. */ 3327 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3328 } 3329 } 3330 break; 3331 case BGE_ASICREV_BCM5755: 3332 case BGE_ASICREV_BCM5761: 3333 case BGE_ASICREV_BCM5784: 3334 case BGE_ASICREV_BCM5785: 3335 case BGE_ASICREV_BCM5787: 3336 case BGE_ASICREV_BCM57780: 3337 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3338 break; 3339 case BGE_ASICREV_BCM5700: 3340 case BGE_ASICREV_BCM5701: 3341 case BGE_ASICREV_BCM5703: 3342 case BGE_ASICREV_BCM5704: 3343 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3344 break; 3345 case BGE_ASICREV_BCM5714_A0: 3346 case BGE_ASICREV_BCM5780: 3347 case BGE_ASICREV_BCM5714: 3348 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3349 /* FALLTHROUGH */ 3350 case BGE_ASICREV_BCM5750: 3351 case BGE_ASICREV_BCM5752: 3352 case BGE_ASICREV_BCM5906: 3353 sc->bge_flags |= BGEF_575X_PLUS; 3354 /* FALLTHROUGH */ 3355 case BGE_ASICREV_BCM5705: 3356 sc->bge_flags |= BGEF_5705_PLUS; 3357 break; 3358 } 3359 3360 /* Identify chips with APE processor. */ 3361 switch (BGE_ASICREV(sc->bge_chipid)) { 3362 case BGE_ASICREV_BCM5717: 3363 case BGE_ASICREV_BCM5719: 3364 case BGE_ASICREV_BCM5720: 3365 case BGE_ASICREV_BCM5761: 3366 case BGE_ASICREV_BCM5762: 3367 sc->bge_flags |= BGEF_APE; 3368 break; 3369 } 3370 3371 /* 3372 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3373 * not actually a MAC controller bug but an issue with the embedded 3374 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3375 */ 3376 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3377 sc->bge_flags |= BGEF_40BIT_BUG; 3378 3379 /* Chips with APE need BAR2 access for APE registers/memory. */ 3380 if ((sc->bge_flags & BGEF_APE) != 0) { 3381 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3382 #if 0 3383 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3384 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3385 &sc->bge_apesize)) { 3386 aprint_error_dev(sc->bge_dev, 3387 "couldn't map BAR2 memory\n"); 3388 return; 3389 } 3390 #else 3391 /* 3392 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3393 * system get NMI on boot (PR#48451). This problem might not be 3394 * the driver's bug but our PCI common part's bug. Until we 3395 * find a real reason, we ignore the prefetchable bit. 3396 */ 3397 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3398 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3399 aprint_error_dev(sc->bge_dev, 3400 "couldn't map BAR2 memory\n"); 3401 return; 3402 } 3403 3404 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3405 if (bus_space_map(pa->pa_memt, memaddr, 3406 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3407 aprint_error_dev(sc->bge_dev, 3408 "couldn't map BAR2 memory\n"); 3409 return; 3410 } 3411 sc->bge_apetag = pa->pa_memt; 3412 #endif 3413 3414 /* Enable APE register/memory access by host driver. */ 3415 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3416 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3417 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3418 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3419 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3420 3421 bge_ape_lock_init(sc); 3422 bge_ape_read_fw_ver(sc); 3423 } 3424 3425 /* Identify the chips that use an CPMU. */ 3426 if (BGE_IS_5717_PLUS(sc) || 3427 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3428 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3429 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3430 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3431 sc->bge_flags |= BGEF_CPMU_PRESENT; 3432 3433 /* Set MI_MODE */ 3434 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3435 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3436 mimode |= BGE_MIMODE_500KHZ_CONST; 3437 else 3438 mimode |= BGE_MIMODE_BASE; 3439 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3440 3441 /* 3442 * When using the BCM5701 in PCI-X mode, data corruption has 3443 * been observed in the first few bytes of some received packets. 3444 * Aligning the packet buffer in memory eliminates the corruption. 3445 * Unfortunately, this misaligns the packet payloads. On platforms 3446 * which do not support unaligned accesses, we will realign the 3447 * payloads by copying the received packets. 3448 */ 3449 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3450 sc->bge_flags & BGEF_PCIX) 3451 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3452 3453 if (BGE_IS_5700_FAMILY(sc)) 3454 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3455 3456 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3457 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3458 3459 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3460 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3461 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3462 sc->bge_flags |= BGEF_IS_5788; 3463 3464 /* 3465 * Some controllers seem to require a special firmware to use 3466 * TSO. But the firmware is not available to FreeBSD and Linux 3467 * claims that the TSO performed by the firmware is slower than 3468 * hardware based TSO. Moreover the firmware based TSO has one 3469 * known bug which can't handle TSO if ethernet header + IP/TCP 3470 * header is greater than 80 bytes. The workaround for the TSO 3471 * bug exist but it seems it's too expensive than not using 3472 * TSO at all. Some hardwares also have the TSO bug so limit 3473 * the TSO to the controllers that are not affected TSO issues 3474 * (e.g. 5755 or higher). 3475 */ 3476 if (BGE_IS_5755_PLUS(sc)) { 3477 /* 3478 * BCM5754 and BCM5787 shares the same ASIC id so 3479 * explicit device id check is required. 3480 */ 3481 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3482 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3483 sc->bge_flags |= BGEF_TSO; 3484 /* TSO on BCM5719 A0 does not work. */ 3485 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3486 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3487 sc->bge_flags &= ~BGEF_TSO; 3488 } 3489 3490 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3491 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3492 (misccfg == 0x4000 || misccfg == 0x8000)) || 3493 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3494 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3495 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3496 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3497 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3498 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3499 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3500 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3501 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3502 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3503 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3504 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3505 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3506 /* These chips are 10/100 only. */ 3507 capmask &= ~BMSR_EXTSTAT; 3508 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3509 } 3510 3511 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3512 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3513 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3514 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3515 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3516 3517 /* Set various PHY bug flags. */ 3518 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3519 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3520 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3521 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3522 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3523 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3524 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3525 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3526 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3527 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3528 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3529 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3530 if (BGE_IS_5705_PLUS(sc) && 3531 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3532 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3533 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3534 !BGE_IS_57765_PLUS(sc)) { 3535 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3536 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3537 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3538 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3539 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3540 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3541 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3542 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3543 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3544 } else 3545 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3546 } 3547 3548 /* 3549 * SEEPROM check. 3550 * First check if firmware knows we do not have SEEPROM. 3551 */ 3552 if (prop_dictionary_get_bool(device_properties(self), 3553 "without-seeprom", &no_seeprom) && no_seeprom) 3554 sc->bge_flags |= BGEF_NO_EEPROM; 3555 3556 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3557 sc->bge_flags |= BGEF_NO_EEPROM; 3558 3559 /* Now check the 'ROM failed' bit on the RX CPU */ 3560 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3561 sc->bge_flags |= BGEF_NO_EEPROM; 3562 3563 sc->bge_asf_mode = 0; 3564 /* No ASF if APE present. */ 3565 if ((sc->bge_flags & BGEF_APE) == 0) { 3566 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3567 BGE_SRAM_DATA_SIG_MAGIC)) { 3568 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3569 BGE_HWCFG_ASF) { 3570 sc->bge_asf_mode |= ASF_ENABLE; 3571 sc->bge_asf_mode |= ASF_STACKUP; 3572 if (BGE_IS_575X_PLUS(sc)) 3573 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3574 } 3575 } 3576 } 3577 3578 int counts[PCI_INTR_TYPE_SIZE] = { 3579 [PCI_INTR_TYPE_INTX] = 1, 3580 [PCI_INTR_TYPE_MSI] = 1, 3581 [PCI_INTR_TYPE_MSIX] = 1, 3582 }; 3583 int max_type = PCI_INTR_TYPE_MSIX; 3584 3585 if (!bge_can_use_msi(sc)) { 3586 /* MSI broken, allow only INTx */ 3587 max_type = PCI_INTR_TYPE_INTX; 3588 } 3589 3590 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3591 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3592 return; 3593 } 3594 3595 DPRINTFN(5, ("pci_intr_string\n")); 3596 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3597 sizeof(intrbuf)); 3598 DPRINTFN(5, ("pci_intr_establish\n")); 3599 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3600 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3601 if (sc->bge_intrhand == NULL) { 3602 pci_intr_release(pc, sc->bge_pihp, 1); 3603 sc->bge_pihp = NULL; 3604 3605 aprint_error_dev(self, "couldn't establish interrupt"); 3606 if (intrstr != NULL) 3607 aprint_error(" at %s", intrstr); 3608 aprint_error("\n"); 3609 return; 3610 } 3611 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3612 3613 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3614 case PCI_INTR_TYPE_MSIX: 3615 case PCI_INTR_TYPE_MSI: 3616 KASSERT(bge_can_use_msi(sc)); 3617 sc->bge_flags |= BGEF_MSI; 3618 break; 3619 default: 3620 /* nothing to do */ 3621 break; 3622 } 3623 3624 /* 3625 * All controllers except BCM5700 supports tagged status but 3626 * we use tagged status only for MSI case on BCM5717. Otherwise 3627 * MSI on BCM5717 does not work. 3628 */ 3629 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3630 sc->bge_flags |= BGEF_TAGGED_STATUS; 3631 3632 /* 3633 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3634 * lock in bge_reset(). 3635 */ 3636 CSR_WRITE_4(sc, BGE_EE_ADDR, 3637 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3638 delay(1000); 3639 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3640 3641 bge_stop_fw(sc); 3642 bge_sig_pre_reset(sc, BGE_RESET_START); 3643 if (bge_reset(sc)) 3644 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3645 3646 /* 3647 * Read the hardware config word in the first 32k of NIC internal 3648 * memory, or fall back to the config word in the EEPROM. 3649 * Note: on some BCM5700 cards, this value appears to be unset. 3650 */ 3651 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3652 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3653 BGE_SRAM_DATA_SIG_MAGIC) { 3654 uint32_t tmp; 3655 3656 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3657 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3658 BGE_SRAM_DATA_VER_SHIFT; 3659 if ((0 < tmp) && (tmp < 0x100)) 3660 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3661 if (sc->bge_flags & BGEF_PCIE) 3662 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3663 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3664 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3665 if (BGE_IS_5717_PLUS(sc)) 3666 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3667 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3668 bge_read_eeprom(sc, (void *)&hwcfg, 3669 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3670 hwcfg = be32toh(hwcfg); 3671 } 3672 aprint_normal_dev(sc->bge_dev, 3673 "HW config %08x, %08x, %08x, %08x %08x\n", 3674 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3675 3676 bge_sig_legacy(sc, BGE_RESET_START); 3677 bge_sig_post_reset(sc, BGE_RESET_START); 3678 3679 if (bge_chipinit(sc)) { 3680 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3681 bge_release_resources(sc); 3682 return; 3683 } 3684 3685 /* 3686 * Get station address from the EEPROM. 3687 */ 3688 if (bge_get_eaddr(sc, eaddr)) { 3689 aprint_error_dev(sc->bge_dev, 3690 "failed to read station address\n"); 3691 bge_release_resources(sc); 3692 return; 3693 } 3694 3695 br = bge_lookup_rev(sc->bge_chipid); 3696 3697 if (br == NULL) { 3698 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3699 sc->bge_chipid); 3700 } else { 3701 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3702 br->br_name, sc->bge_chipid); 3703 } 3704 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3705 3706 /* Allocate the general information block and ring buffers. */ 3707 if (pci_dma64_available(pa)) { 3708 sc->bge_dmatag = pa->pa_dmat64; 3709 sc->bge_dmatag32 = pa->pa_dmat; 3710 sc->bge_dma64 = true; 3711 } else { 3712 sc->bge_dmatag = pa->pa_dmat; 3713 sc->bge_dmatag32 = pa->pa_dmat; 3714 sc->bge_dma64 = false; 3715 } 3716 3717 /* 40bit DMA workaround */ 3718 if (sizeof(bus_addr_t) > 4) { 3719 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3720 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3721 3722 if (bus_dmatag_subregion(olddmatag, 0, 3723 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3724 BUS_DMA_NOWAIT) != 0) { 3725 aprint_error_dev(self, 3726 "WARNING: failed to restrict dma range," 3727 " falling back to parent bus dma range\n"); 3728 sc->bge_dmatag = olddmatag; 3729 } 3730 } 3731 } 3732 SLIST_INIT(&sc->txdma_list); 3733 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3734 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3735 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3736 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3737 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3738 return; 3739 } 3740 DPRINTFN(5, ("bus_dmamem_map\n")); 3741 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3742 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3743 BUS_DMA_NOWAIT)) { 3744 aprint_error_dev(sc->bge_dev, 3745 "can't map DMA buffers (%zu bytes)\n", 3746 sizeof(struct bge_ring_data)); 3747 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3748 sc->bge_ring_rseg); 3749 return; 3750 } 3751 DPRINTFN(5, ("bus_dmamem_create\n")); 3752 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3753 sizeof(struct bge_ring_data), 0, 3754 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3755 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3756 bus_dmamem_unmap(sc->bge_dmatag, kva, 3757 sizeof(struct bge_ring_data)); 3758 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3759 sc->bge_ring_rseg); 3760 return; 3761 } 3762 DPRINTFN(5, ("bus_dmamem_load\n")); 3763 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3764 sizeof(struct bge_ring_data), NULL, 3765 BUS_DMA_NOWAIT)) { 3766 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3767 bus_dmamem_unmap(sc->bge_dmatag, kva, 3768 sizeof(struct bge_ring_data)); 3769 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3770 sc->bge_ring_rseg); 3771 return; 3772 } 3773 3774 DPRINTFN(5, ("bzero\n")); 3775 sc->bge_rdata = (struct bge_ring_data *)kva; 3776 3777 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3778 3779 /* Try to allocate memory for jumbo buffers. */ 3780 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3781 if (bge_alloc_jumbo_mem(sc)) { 3782 aprint_error_dev(sc->bge_dev, 3783 "jumbo buffer allocation failed\n"); 3784 } else 3785 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3786 } 3787 3788 /* Set default tuneable values. */ 3789 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3790 sc->bge_rx_coal_ticks = 150; 3791 sc->bge_rx_max_coal_bds = 64; 3792 sc->bge_tx_coal_ticks = 300; 3793 sc->bge_tx_max_coal_bds = 400; 3794 if (BGE_IS_5705_PLUS(sc)) { 3795 sc->bge_tx_coal_ticks = (12 * 5); 3796 sc->bge_tx_max_coal_bds = (12 * 5); 3797 aprint_verbose_dev(sc->bge_dev, 3798 "setting short Tx thresholds\n"); 3799 } 3800 3801 if (BGE_IS_5717_PLUS(sc)) 3802 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3803 else if (BGE_IS_5705_PLUS(sc)) 3804 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3805 else 3806 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3807 3808 /* Set up ifnet structure */ 3809 ifp = &sc->ethercom.ec_if; 3810 ifp->if_softc = sc; 3811 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3812 ifp->if_ioctl = bge_ioctl; 3813 ifp->if_stop = bge_stop; 3814 ifp->if_start = bge_start; 3815 ifp->if_init = bge_init; 3816 ifp->if_watchdog = bge_watchdog; 3817 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3818 IFQ_SET_READY(&ifp->if_snd); 3819 DPRINTFN(5, ("strcpy if_xname\n")); 3820 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3821 3822 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3823 sc->ethercom.ec_if.if_capabilities |= 3824 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3825 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3826 sc->ethercom.ec_if.if_capabilities |= 3827 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3828 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3829 #endif 3830 sc->ethercom.ec_capabilities |= 3831 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3832 3833 if (sc->bge_flags & BGEF_TSO) 3834 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3835 3836 /* 3837 * Do MII setup. 3838 */ 3839 DPRINTFN(5, ("mii setup\n")); 3840 mii->mii_ifp = ifp; 3841 mii->mii_readreg = bge_miibus_readreg; 3842 mii->mii_writereg = bge_miibus_writereg; 3843 mii->mii_statchg = bge_miibus_statchg; 3844 3845 /* 3846 * Figure out what sort of media we have by checking the hardware 3847 * config word. Note: on some BCM5700 cards, this value appears to be 3848 * unset. If that's the case, we have to rely on identifying the NIC 3849 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3850 * The SysKonnect SK-9D41 is a 1000baseSX card. 3851 */ 3852 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 3853 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3854 if (BGE_IS_5705_PLUS(sc)) { 3855 sc->bge_flags |= BGEF_FIBER_MII; 3856 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3857 } else 3858 sc->bge_flags |= BGEF_FIBER_TBI; 3859 } 3860 3861 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3862 if (BGE_IS_JUMBO_CAPABLE(sc)) 3863 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3864 3865 /* set phyflags and chipid before mii_attach() */ 3866 dict = device_properties(self); 3867 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3868 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3869 3870 if (sc->bge_flags & BGEF_FIBER_TBI) { 3871 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3872 bge_ifmedia_sts); 3873 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3874 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3875 0, NULL); 3876 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3877 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3878 /* Pretend the user requested this setting */ 3879 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3880 } else { 3881 /* 3882 * Do transceiver setup and tell the firmware the 3883 * driver is down so we can try to get access the 3884 * probe if ASF is running. Retry a couple of times 3885 * if we get a conflict with the ASF firmware accessing 3886 * the PHY. 3887 */ 3888 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3889 bge_asf_driver_up(sc); 3890 3891 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3892 bge_ifmedia_sts); 3893 mii_flags = MIIF_DOPAUSE; 3894 if (sc->bge_flags & BGEF_FIBER_MII) 3895 mii_flags |= MIIF_HAVEFIBER; 3896 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 3897 MII_OFFSET_ANY, mii_flags); 3898 3899 if (LIST_EMPTY(&mii->mii_phys)) { 3900 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3901 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 3902 0, NULL); 3903 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 3904 } else 3905 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 3906 3907 /* 3908 * Now tell the firmware we are going up after probing the PHY 3909 */ 3910 if (sc->bge_asf_mode & ASF_STACKUP) 3911 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3912 } 3913 3914 /* 3915 * Call MI attach routine. 3916 */ 3917 DPRINTFN(5, ("if_attach\n")); 3918 if_attach(ifp); 3919 if_deferred_start_init(ifp, NULL); 3920 DPRINTFN(5, ("ether_ifattach\n")); 3921 ether_ifattach(ifp, eaddr); 3922 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3923 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3924 RND_TYPE_NET, RND_FLAG_DEFAULT); 3925 #ifdef BGE_EVENT_COUNTERS 3926 /* 3927 * Attach event counters. 3928 */ 3929 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3930 NULL, device_xname(sc->bge_dev), "intr"); 3931 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3932 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3933 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3934 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3935 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3936 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3937 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3938 NULL, device_xname(sc->bge_dev), "tx_xon"); 3939 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3940 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3941 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3942 NULL, device_xname(sc->bge_dev), "rx_xon"); 3943 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3944 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3945 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3946 NULL, device_xname(sc->bge_dev), "xoffentered"); 3947 #endif /* BGE_EVENT_COUNTERS */ 3948 DPRINTFN(5, ("callout_init\n")); 3949 callout_init(&sc->bge_timeout, 0); 3950 3951 if (pmf_device_register(self, NULL, NULL)) 3952 pmf_class_network_register(self, ifp); 3953 else 3954 aprint_error_dev(self, "couldn't establish power handler\n"); 3955 3956 bge_sysctl_init(sc); 3957 3958 #ifdef BGE_DEBUG 3959 bge_debug_info(sc); 3960 #endif 3961 } 3962 3963 /* 3964 * Stop all chip I/O so that the kernel's probe routines don't 3965 * get confused by errant DMAs when rebooting. 3966 */ 3967 static int 3968 bge_detach(device_t self, int flags __unused) 3969 { 3970 struct bge_softc *sc = device_private(self); 3971 struct ifnet *ifp = &sc->ethercom.ec_if; 3972 int s; 3973 3974 s = splnet(); 3975 /* Stop the interface. Callouts are stopped in it. */ 3976 bge_stop(ifp, 1); 3977 splx(s); 3978 3979 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3980 3981 /* Delete all remaining media. */ 3982 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3983 3984 ether_ifdetach(ifp); 3985 if_detach(ifp); 3986 3987 bge_release_resources(sc); 3988 3989 return 0; 3990 } 3991 3992 static void 3993 bge_release_resources(struct bge_softc *sc) 3994 { 3995 3996 /* Detach sysctl */ 3997 if (sc->bge_log != NULL) 3998 sysctl_teardown(&sc->bge_log); 3999 4000 #ifdef BGE_EVENT_COUNTERS 4001 /* Detach event counters. */ 4002 evcnt_detach(&sc->bge_ev_intr); 4003 evcnt_detach(&sc->bge_ev_intr_spurious); 4004 evcnt_detach(&sc->bge_ev_intr_spurious2); 4005 evcnt_detach(&sc->bge_ev_tx_xoff); 4006 evcnt_detach(&sc->bge_ev_tx_xon); 4007 evcnt_detach(&sc->bge_ev_rx_xoff); 4008 evcnt_detach(&sc->bge_ev_rx_xon); 4009 evcnt_detach(&sc->bge_ev_rx_macctl); 4010 evcnt_detach(&sc->bge_ev_xoffentered); 4011 #endif /* BGE_EVENT_COUNTERS */ 4012 4013 /* Disestablish the interrupt handler */ 4014 if (sc->bge_intrhand != NULL) { 4015 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4016 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4017 sc->bge_intrhand = NULL; 4018 } 4019 4020 if (sc->bge_dmatag != NULL) { 4021 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4022 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4023 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4024 sizeof(struct bge_ring_data)); 4025 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4026 sc->bge_ring_rseg); 4027 } 4028 4029 /* Unmap the device registers */ 4030 if (sc->bge_bsize != 0) { 4031 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4032 sc->bge_bsize = 0; 4033 } 4034 4035 /* Unmap the APE registers */ 4036 if (sc->bge_apesize != 0) { 4037 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4038 sc->bge_apesize); 4039 sc->bge_apesize = 0; 4040 } 4041 } 4042 4043 static int 4044 bge_reset(struct bge_softc *sc) 4045 { 4046 uint32_t cachesize, command; 4047 uint32_t reset, mac_mode, mac_mode_mask; 4048 pcireg_t devctl, reg; 4049 int i, val; 4050 void (*write_op)(struct bge_softc *, int, int); 4051 4052 /* Make mask for BGE_MAC_MODE register. */ 4053 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4054 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4055 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4056 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4057 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4058 4059 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4060 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4061 if (sc->bge_flags & BGEF_PCIE) 4062 write_op = bge_writemem_direct; 4063 else 4064 write_op = bge_writemem_ind; 4065 } else 4066 write_op = bge_writereg_ind; 4067 4068 /* 57XX step 4 */ 4069 /* Acquire the NVM lock */ 4070 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4071 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4072 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4073 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4074 for (i = 0; i < 8000; i++) { 4075 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4076 BGE_NVRAMSWARB_GNT1) 4077 break; 4078 DELAY(20); 4079 } 4080 if (i == 8000) { 4081 printf("%s: NVRAM lock timedout!\n", 4082 device_xname(sc->bge_dev)); 4083 } 4084 } 4085 4086 /* Take APE lock when performing reset. */ 4087 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4088 4089 /* 57XX step 3 */ 4090 /* Save some important PCI state. */ 4091 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4092 /* 5718 reset step 3 */ 4093 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4094 4095 /* 5718 reset step 5, 57XX step 5b-5d */ 4096 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4097 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4098 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4099 4100 /* XXX ???: Disable fastboot on controllers that support it. */ 4101 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4102 BGE_IS_5755_PLUS(sc)) 4103 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4104 4105 /* 5718 reset step 2, 57XX step 6 */ 4106 /* 4107 * Write the magic number to SRAM at offset 0xB50. 4108 * When firmware finishes its initialization it will 4109 * write ~BGE_MAGIC_NUMBER to the same location. 4110 */ 4111 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4112 4113 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4114 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4115 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4116 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4117 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4118 } 4119 4120 /* 5718 reset step 6, 57XX step 7 */ 4121 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4122 /* 4123 * XXX: from FreeBSD/Linux; no documentation 4124 */ 4125 if (sc->bge_flags & BGEF_PCIE) { 4126 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4127 !BGE_IS_57765_PLUS(sc) && 4128 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4129 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4130 /* PCI Express 1.0 system */ 4131 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4132 BGE_PHY_PCIE_SCRAM_MODE); 4133 } 4134 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4135 /* 4136 * Prevent PCI Express link training 4137 * during global reset. 4138 */ 4139 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4140 reset |= (1 << 29); 4141 } 4142 } 4143 4144 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4145 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4146 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4147 i | BGE_VCPU_STATUS_DRV_RESET); 4148 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4149 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4150 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4151 } 4152 4153 /* 4154 * Set GPHY Power Down Override to leave GPHY 4155 * powered up in D0 uninitialized. 4156 */ 4157 if (BGE_IS_5705_PLUS(sc) && 4158 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4159 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4160 4161 /* Issue global reset */ 4162 write_op(sc, BGE_MISC_CFG, reset); 4163 4164 /* 5718 reset step 7, 57XX step 8 */ 4165 if (sc->bge_flags & BGEF_PCIE) 4166 delay(100*1000); /* too big */ 4167 else 4168 delay(1000); 4169 4170 if (sc->bge_flags & BGEF_PCIE) { 4171 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4172 DELAY(500000); 4173 /* XXX: Magic Numbers */ 4174 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4175 BGE_PCI_UNKNOWN0); 4176 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4177 BGE_PCI_UNKNOWN0, 4178 reg | (1 << 15)); 4179 } 4180 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4181 sc->bge_pciecap + PCIE_DCSR); 4182 /* Clear enable no snoop and disable relaxed ordering. */ 4183 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4184 PCIE_DCSR_ENA_NO_SNOOP); 4185 4186 /* Set PCIE max payload size to 128 for older PCIe devices */ 4187 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4188 devctl &= ~(0x00e0); 4189 /* Clear device status register. Write 1b to clear */ 4190 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4191 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4192 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4193 sc->bge_pciecap + PCIE_DCSR, devctl); 4194 bge_set_max_readrq(sc); 4195 } 4196 4197 /* From Linux: dummy read to flush PCI posted writes */ 4198 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4199 4200 /* 4201 * Reset some of the PCI state that got zapped by reset 4202 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4203 * set, too. 4204 */ 4205 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4206 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4207 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4208 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4209 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4210 (sc->bge_flags & BGEF_PCIX) != 0) 4211 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4212 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4213 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4214 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4215 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4216 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4217 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4218 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4219 4220 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4221 if (sc->bge_flags & BGEF_PCIX) { 4222 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4223 + PCIX_CMD); 4224 /* Set max memory read byte count to 2K */ 4225 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4226 reg &= ~PCIX_CMD_BYTECNT_MASK; 4227 reg |= PCIX_CMD_BCNT_2048; 4228 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4229 /* 4230 * For 5704, set max outstanding split transaction 4231 * field to 0 (0 means it supports 1 request) 4232 */ 4233 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4234 | PCIX_CMD_BYTECNT_MASK); 4235 reg |= PCIX_CMD_BCNT_2048; 4236 } 4237 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4238 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4239 } 4240 4241 /* 5718 reset step 10, 57XX step 12 */ 4242 /* Enable memory arbiter. */ 4243 if (BGE_IS_5714_FAMILY(sc)) { 4244 val = CSR_READ_4(sc, BGE_MARB_MODE); 4245 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4246 } else 4247 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4248 4249 /* XXX 5721, 5751 and 5752 */ 4250 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4251 /* Step 19: */ 4252 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4253 /* Step 20: */ 4254 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4255 } 4256 4257 /* 5718 reset step 12, 57XX step 15 and 16 */ 4258 /* Fix up byte swapping */ 4259 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4260 4261 /* 5718 reset step 13, 57XX step 17 */ 4262 /* Poll until the firmware initialization is complete */ 4263 bge_poll_fw(sc); 4264 4265 /* 57XX step 21 */ 4266 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4267 pcireg_t msidata; 4268 4269 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4270 BGE_PCI_MSI_DATA); 4271 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4272 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4273 msidata); 4274 } 4275 4276 /* 57XX step 18 */ 4277 /* Write mac mode. */ 4278 val = CSR_READ_4(sc, BGE_MAC_MODE); 4279 /* Restore mac_mode_mask's bits using mac_mode */ 4280 val = (val & ~mac_mode_mask) | mac_mode; 4281 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4282 DELAY(40); 4283 4284 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4285 4286 /* 4287 * The 5704 in TBI mode apparently needs some special 4288 * adjustment to insure the SERDES drive level is set 4289 * to 1.2V. 4290 */ 4291 if (sc->bge_flags & BGEF_FIBER_TBI && 4292 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4293 uint32_t serdescfg; 4294 4295 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4296 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4297 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4298 } 4299 4300 if (sc->bge_flags & BGEF_PCIE && 4301 !BGE_IS_57765_PLUS(sc) && 4302 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4303 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4304 uint32_t v; 4305 4306 /* Enable PCI Express bug fix */ 4307 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4308 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4309 v | BGE_TLP_DATA_FIFO_PROTECT); 4310 } 4311 4312 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4313 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4314 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4315 4316 return 0; 4317 } 4318 4319 /* 4320 * Frame reception handling. This is called if there's a frame 4321 * on the receive return list. 4322 * 4323 * Note: we have to be able to handle two possibilities here: 4324 * 1) the frame is from the jumbo receive ring 4325 * 2) the frame is from the standard receive ring 4326 */ 4327 4328 static void 4329 bge_rxeof(struct bge_softc *sc) 4330 { 4331 struct ifnet *ifp; 4332 uint16_t rx_prod, rx_cons; 4333 int stdcnt = 0, jumbocnt = 0; 4334 bus_dmamap_t dmamap; 4335 bus_addr_t offset, toff; 4336 bus_size_t tlen; 4337 int tosync; 4338 4339 rx_cons = sc->bge_rx_saved_considx; 4340 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4341 4342 /* Nothing to do */ 4343 if (rx_cons == rx_prod) 4344 return; 4345 4346 ifp = &sc->ethercom.ec_if; 4347 4348 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4349 offsetof(struct bge_ring_data, bge_status_block), 4350 sizeof (struct bge_status_block), 4351 BUS_DMASYNC_POSTREAD); 4352 4353 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4354 tosync = rx_prod - rx_cons; 4355 4356 if (tosync != 0) 4357 rnd_add_uint32(&sc->rnd_source, tosync); 4358 4359 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4360 4361 if (tosync < 0) { 4362 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4363 sizeof (struct bge_rx_bd); 4364 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4365 toff, tlen, BUS_DMASYNC_POSTREAD); 4366 tosync = -tosync; 4367 } 4368 4369 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4370 offset, tosync * sizeof (struct bge_rx_bd), 4371 BUS_DMASYNC_POSTREAD); 4372 4373 while (rx_cons != rx_prod) { 4374 struct bge_rx_bd *cur_rx; 4375 uint32_t rxidx; 4376 struct mbuf *m = NULL; 4377 4378 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4379 4380 rxidx = cur_rx->bge_idx; 4381 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4382 4383 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4384 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4385 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4386 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4387 jumbocnt++; 4388 bus_dmamap_sync(sc->bge_dmatag, 4389 sc->bge_cdata.bge_rx_jumbo_map, 4390 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4391 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4392 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4393 ifp->if_ierrors++; 4394 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4395 continue; 4396 } 4397 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4398 NULL)== ENOBUFS) { 4399 ifp->if_ierrors++; 4400 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4401 continue; 4402 } 4403 } else { 4404 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4405 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4406 4407 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4408 stdcnt++; 4409 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4410 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4411 if (dmamap == NULL) { 4412 ifp->if_ierrors++; 4413 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4414 continue; 4415 } 4416 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4417 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4418 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4419 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4420 ifp->if_ierrors++; 4421 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4422 continue; 4423 } 4424 if (bge_newbuf_std(sc, sc->bge_std, 4425 NULL, dmamap) == ENOBUFS) { 4426 ifp->if_ierrors++; 4427 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4428 continue; 4429 } 4430 } 4431 4432 #ifndef __NO_STRICT_ALIGNMENT 4433 /* 4434 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4435 * the Rx buffer has the layer-2 header unaligned. 4436 * If our CPU requires alignment, re-align by copying. 4437 */ 4438 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4439 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4440 cur_rx->bge_len); 4441 m->m_data += ETHER_ALIGN; 4442 } 4443 #endif 4444 4445 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4446 m_set_rcvif(m, ifp); 4447 4448 bge_rxcsum(sc, cur_rx, m); 4449 4450 /* 4451 * If we received a packet with a vlan tag, pass it 4452 * to vlan_input() instead of ether_input(). 4453 */ 4454 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4455 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4456 4457 if_percpuq_enqueue(ifp->if_percpuq, m); 4458 } 4459 4460 sc->bge_rx_saved_considx = rx_cons; 4461 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4462 if (stdcnt) 4463 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4464 if (jumbocnt) 4465 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4466 } 4467 4468 static void 4469 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4470 { 4471 4472 if (BGE_IS_57765_PLUS(sc)) { 4473 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4474 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4475 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4476 if ((cur_rx->bge_error_flag & 4477 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4478 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4479 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4480 m->m_pkthdr.csum_data = 4481 cur_rx->bge_tcp_udp_csum; 4482 m->m_pkthdr.csum_flags |= 4483 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4484 } 4485 } 4486 } else { 4487 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4488 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4489 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4490 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4491 /* 4492 * Rx transport checksum-offload may also 4493 * have bugs with packets which, when transmitted, 4494 * were `runts' requiring padding. 4495 */ 4496 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4497 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4498 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4499 m->m_pkthdr.csum_data = 4500 cur_rx->bge_tcp_udp_csum; 4501 m->m_pkthdr.csum_flags |= 4502 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4503 } 4504 } 4505 } 4506 4507 static void 4508 bge_txeof(struct bge_softc *sc) 4509 { 4510 struct bge_tx_bd *cur_tx = NULL; 4511 struct ifnet *ifp; 4512 struct txdmamap_pool_entry *dma; 4513 bus_addr_t offset, toff; 4514 bus_size_t tlen; 4515 int tosync; 4516 struct mbuf *m; 4517 4518 ifp = &sc->ethercom.ec_if; 4519 4520 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4521 offsetof(struct bge_ring_data, bge_status_block), 4522 sizeof (struct bge_status_block), 4523 BUS_DMASYNC_POSTREAD); 4524 4525 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4526 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4527 sc->bge_tx_saved_considx; 4528 4529 if (tosync != 0) 4530 rnd_add_uint32(&sc->rnd_source, tosync); 4531 4532 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4533 4534 if (tosync < 0) { 4535 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4536 sizeof (struct bge_tx_bd); 4537 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4538 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4539 tosync = -tosync; 4540 } 4541 4542 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4543 offset, tosync * sizeof (struct bge_tx_bd), 4544 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4545 4546 /* 4547 * Go through our tx ring and free mbufs for those 4548 * frames that have been sent. 4549 */ 4550 while (sc->bge_tx_saved_considx != 4551 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4552 uint32_t idx = 0; 4553 4554 idx = sc->bge_tx_saved_considx; 4555 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4556 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4557 ifp->if_opackets++; 4558 m = sc->bge_cdata.bge_tx_chain[idx]; 4559 if (m != NULL) { 4560 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4561 dma = sc->txdma[idx]; 4562 if (dma->is_dma32) { 4563 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4564 0, dma->dmamap32->dm_mapsize, 4565 BUS_DMASYNC_POSTWRITE); 4566 bus_dmamap_unload( 4567 sc->bge_dmatag32, dma->dmamap32); 4568 } else { 4569 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4570 0, dma->dmamap->dm_mapsize, 4571 BUS_DMASYNC_POSTWRITE); 4572 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4573 } 4574 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4575 sc->txdma[idx] = NULL; 4576 4577 m_freem(m); 4578 } 4579 sc->bge_txcnt--; 4580 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4581 ifp->if_timer = 0; 4582 } 4583 4584 if (cur_tx != NULL) 4585 ifp->if_flags &= ~IFF_OACTIVE; 4586 } 4587 4588 static int 4589 bge_intr(void *xsc) 4590 { 4591 struct bge_softc *sc; 4592 struct ifnet *ifp; 4593 uint32_t pcistate, statusword, statustag; 4594 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4595 4596 sc = xsc; 4597 ifp = &sc->ethercom.ec_if; 4598 4599 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4600 if (BGE_IS_5717_PLUS(sc)) 4601 intrmask = 0; 4602 4603 /* It is possible for the interrupt to arrive before 4604 * the status block is updated prior to the interrupt. 4605 * Reading the PCI State register will confirm whether the 4606 * interrupt is ours and will flush the status block. 4607 */ 4608 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4609 4610 /* read status word from status block */ 4611 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4612 offsetof(struct bge_ring_data, bge_status_block), 4613 sizeof (struct bge_status_block), 4614 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4615 statusword = sc->bge_rdata->bge_status_block.bge_status; 4616 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4617 4618 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4619 if (sc->bge_lasttag == statustag && 4620 (~pcistate & intrmask)) { 4621 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4622 return (0); 4623 } 4624 sc->bge_lasttag = statustag; 4625 } else { 4626 if (!(statusword & BGE_STATFLAG_UPDATED) && 4627 !(~pcistate & intrmask)) { 4628 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4629 return (0); 4630 } 4631 statustag = 0; 4632 } 4633 /* Ack interrupt and stop others from occurring. */ 4634 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4635 BGE_EVCNT_INCR(sc->bge_ev_intr); 4636 4637 /* clear status word */ 4638 sc->bge_rdata->bge_status_block.bge_status = 0; 4639 4640 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4641 offsetof(struct bge_ring_data, bge_status_block), 4642 sizeof (struct bge_status_block), 4643 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4644 4645 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4646 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4647 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4648 bge_link_upd(sc); 4649 4650 if (ifp->if_flags & IFF_RUNNING) { 4651 /* Check RX return ring producer/consumer */ 4652 bge_rxeof(sc); 4653 4654 /* Check TX ring producer/consumer */ 4655 bge_txeof(sc); 4656 } 4657 4658 if (sc->bge_pending_rxintr_change) { 4659 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4660 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4661 4662 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4663 DELAY(10); 4664 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4665 4666 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4667 DELAY(10); 4668 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4669 4670 sc->bge_pending_rxintr_change = 0; 4671 } 4672 bge_handle_events(sc); 4673 4674 /* Re-enable interrupts. */ 4675 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4676 4677 if (ifp->if_flags & IFF_RUNNING) 4678 if_schedule_deferred_start(ifp); 4679 4680 return 1; 4681 } 4682 4683 static void 4684 bge_asf_driver_up(struct bge_softc *sc) 4685 { 4686 if (sc->bge_asf_mode & ASF_STACKUP) { 4687 /* Send ASF heartbeat aprox. every 2s */ 4688 if (sc->bge_asf_count) 4689 sc->bge_asf_count --; 4690 else { 4691 sc->bge_asf_count = 2; 4692 4693 bge_wait_for_event_ack(sc); 4694 4695 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4696 BGE_FW_CMD_DRV_ALIVE3); 4697 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4698 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4699 BGE_FW_HB_TIMEOUT_SEC); 4700 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4701 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4702 BGE_RX_CPU_DRV_EVENT); 4703 } 4704 } 4705 } 4706 4707 static void 4708 bge_tick(void *xsc) 4709 { 4710 struct bge_softc *sc = xsc; 4711 struct mii_data *mii = &sc->bge_mii; 4712 int s; 4713 4714 s = splnet(); 4715 4716 if (BGE_IS_5705_PLUS(sc)) 4717 bge_stats_update_regs(sc); 4718 else 4719 bge_stats_update(sc); 4720 4721 if (sc->bge_flags & BGEF_FIBER_TBI) { 4722 /* 4723 * Since in TBI mode auto-polling can't be used we should poll 4724 * link status manually. Here we register pending link event 4725 * and trigger interrupt. 4726 */ 4727 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4728 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4729 } else { 4730 /* 4731 * Do not touch PHY if we have link up. This could break 4732 * IPMI/ASF mode or produce extra input errors. 4733 * (extra input errors was reported for bcm5701 & bcm5704). 4734 */ 4735 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4736 mii_tick(mii); 4737 } 4738 4739 bge_asf_driver_up(sc); 4740 4741 if (!sc->bge_detaching) 4742 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4743 4744 splx(s); 4745 } 4746 4747 static void 4748 bge_stats_update_regs(struct bge_softc *sc) 4749 { 4750 struct ifnet *ifp = &sc->ethercom.ec_if; 4751 4752 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4753 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4754 4755 /* 4756 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4757 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4758 * (silicon bug). There's no reliable workaround so just 4759 * ignore the counter 4760 */ 4761 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4762 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4763 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4764 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4765 } 4766 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4767 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4768 4769 if (sc->bge_flags & BGEF_RDMA_BUG) { 4770 uint32_t val, ucast, mcast, bcast; 4771 4772 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4773 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4774 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4775 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4776 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4777 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4778 4779 /* 4780 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4781 * frames, it's safe to disable workaround for DMA engine's 4782 * miscalculation of TXMBUF space. 4783 */ 4784 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4785 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4786 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4787 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4788 else 4789 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4790 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4791 sc->bge_flags &= ~BGEF_RDMA_BUG; 4792 } 4793 } 4794 } 4795 4796 static void 4797 bge_stats_update(struct bge_softc *sc) 4798 { 4799 struct ifnet *ifp = &sc->ethercom.ec_if; 4800 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4801 4802 #define READ_STAT(sc, stats, stat) \ 4803 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4804 4805 ifp->if_collisions += 4806 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4807 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4808 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4809 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4810 ifp->if_collisions; 4811 4812 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4813 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4814 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4815 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4816 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4817 READ_STAT(sc, stats, 4818 xoffPauseFramesReceived.bge_addr_lo)); 4819 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4820 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4821 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4822 READ_STAT(sc, stats, 4823 macControlFramesReceived.bge_addr_lo)); 4824 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4825 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4826 4827 #undef READ_STAT 4828 4829 #ifdef notdef 4830 ifp->if_collisions += 4831 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4832 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4833 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4834 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4835 ifp->if_collisions; 4836 #endif 4837 } 4838 4839 /* 4840 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4841 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4842 * but when such padded frames employ the bge IP/TCP checksum offload, 4843 * the hardware checksum assist gives incorrect results (possibly 4844 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4845 * If we pad such runts with zeros, the onboard checksum comes out correct. 4846 */ 4847 static inline int 4848 bge_cksum_pad(struct mbuf *pkt) 4849 { 4850 struct mbuf *last = NULL; 4851 int padlen; 4852 4853 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4854 4855 /* if there's only the packet-header and we can pad there, use it. */ 4856 if (pkt->m_pkthdr.len == pkt->m_len && 4857 M_TRAILINGSPACE(pkt) >= padlen) { 4858 last = pkt; 4859 } else { 4860 /* 4861 * Walk packet chain to find last mbuf. We will either 4862 * pad there, or append a new mbuf and pad it 4863 * (thus perhaps avoiding the bcm5700 dma-min bug). 4864 */ 4865 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4866 continue; /* do nothing */ 4867 } 4868 4869 /* `last' now points to last in chain. */ 4870 if (M_TRAILINGSPACE(last) < padlen) { 4871 /* Allocate new empty mbuf, pad it. Compact later. */ 4872 struct mbuf *n; 4873 MGET(n, M_DONTWAIT, MT_DATA); 4874 if (n == NULL) 4875 return ENOBUFS; 4876 n->m_len = 0; 4877 last->m_next = n; 4878 last = n; 4879 } 4880 } 4881 4882 KDASSERT(!M_READONLY(last)); 4883 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4884 4885 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4886 memset(mtod(last, char *) + last->m_len, 0, padlen); 4887 last->m_len += padlen; 4888 pkt->m_pkthdr.len += padlen; 4889 return 0; 4890 } 4891 4892 /* 4893 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4894 */ 4895 static inline int 4896 bge_compact_dma_runt(struct mbuf *pkt) 4897 { 4898 struct mbuf *m, *prev; 4899 int totlen; 4900 4901 prev = NULL; 4902 totlen = 0; 4903 4904 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 4905 int mlen = m->m_len; 4906 int shortfall = 8 - mlen ; 4907 4908 totlen += mlen; 4909 if (mlen == 0) 4910 continue; 4911 if (mlen >= 8) 4912 continue; 4913 4914 /* If we get here, mbuf data is too small for DMA engine. 4915 * Try to fix by shuffling data to prev or next in chain. 4916 * If that fails, do a compacting deep-copy of the whole chain. 4917 */ 4918 4919 /* Internal frag. If fits in prev, copy it there. */ 4920 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4921 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4922 prev->m_len += mlen; 4923 m->m_len = 0; 4924 /* XXX stitch chain */ 4925 prev->m_next = m_free(m); 4926 m = prev; 4927 continue; 4928 } else if (m->m_next != NULL && 4929 M_TRAILINGSPACE(m) >= shortfall && 4930 m->m_next->m_len >= (8 + shortfall)) { 4931 /* m is writable and have enough data in next, pull up. */ 4932 4933 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4934 shortfall); 4935 m->m_len += shortfall; 4936 m->m_next->m_len -= shortfall; 4937 m->m_next->m_data += shortfall; 4938 } else if (m->m_next == NULL || 1) { 4939 /* Got a runt at the very end of the packet. 4940 * borrow data from the tail of the preceding mbuf and 4941 * update its length in-place. (The original data is 4942 * still valid, so we can do this even if prev is not 4943 * writable.) 4944 */ 4945 4946 /* 4947 * If we'd make prev a runt, just move all of its data. 4948 */ 4949 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4950 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4951 4952 if ((prev->m_len - shortfall) < 8) 4953 shortfall = prev->m_len; 4954 4955 #ifdef notyet /* just do the safe slow thing for now */ 4956 if (!M_READONLY(m)) { 4957 if (M_LEADINGSPACE(m) < shorfall) { 4958 void *m_dat; 4959 m_dat = (m->m_flags & M_PKTHDR) ? 4960 m->m_pktdat : m->dat; 4961 memmove(m_dat, mtod(m, void*), 4962 m->m_len); 4963 m->m_data = m_dat; 4964 } 4965 } else 4966 #endif /* just do the safe slow thing */ 4967 { 4968 struct mbuf * n = NULL; 4969 int newprevlen = prev->m_len - shortfall; 4970 4971 MGET(n, M_NOWAIT, MT_DATA); 4972 if (n == NULL) 4973 return ENOBUFS; 4974 KASSERT(m->m_len + shortfall < MLEN 4975 /*, 4976 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4977 4978 /* first copy the data we're stealing from prev */ 4979 memcpy(n->m_data, prev->m_data + newprevlen, 4980 shortfall); 4981 4982 /* update prev->m_len accordingly */ 4983 prev->m_len -= shortfall; 4984 4985 /* copy data from runt m */ 4986 memcpy(n->m_data + shortfall, m->m_data, 4987 m->m_len); 4988 4989 /* n holds what we stole from prev, plus m */ 4990 n->m_len = shortfall + m->m_len; 4991 4992 /* stitch n into chain and free m */ 4993 n->m_next = m->m_next; 4994 prev->m_next = n; 4995 /* KASSERT(m->m_next == NULL); */ 4996 m->m_next = NULL; 4997 m_free(m); 4998 m = n; /* for continuing loop */ 4999 } 5000 } 5001 } 5002 return 0; 5003 } 5004 5005 /* 5006 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5007 * pointers to descriptors. 5008 */ 5009 static int 5010 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5011 { 5012 struct ifnet *ifp = &sc->ethercom.ec_if; 5013 struct bge_tx_bd *f, *prev_f; 5014 uint32_t frag, cur; 5015 uint16_t csum_flags = 0; 5016 uint16_t txbd_tso_flags = 0; 5017 struct txdmamap_pool_entry *dma; 5018 bus_dmamap_t dmamap; 5019 bus_dma_tag_t dmatag; 5020 int i = 0; 5021 int use_tso, maxsegsize, error; 5022 bool have_vtag; 5023 uint16_t vtag; 5024 bool remap; 5025 5026 if (m_head->m_pkthdr.csum_flags) { 5027 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5028 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5029 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5030 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5031 } 5032 5033 /* 5034 * If we were asked to do an outboard checksum, and the NIC 5035 * has the bug where it sometimes adds in the Ethernet padding, 5036 * explicitly pad with zeros so the cksum will be correct either way. 5037 * (For now, do this for all chip versions, until newer 5038 * are confirmed to not require the workaround.) 5039 */ 5040 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5041 #ifdef notyet 5042 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5043 #endif 5044 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5045 goto check_dma_bug; 5046 5047 if (bge_cksum_pad(m_head) != 0) 5048 return ENOBUFS; 5049 5050 check_dma_bug: 5051 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5052 goto doit; 5053 5054 /* 5055 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5056 * less than eight bytes. If we encounter a teeny mbuf 5057 * at the end of a chain, we can pad. Otherwise, copy. 5058 */ 5059 if (bge_compact_dma_runt(m_head) != 0) 5060 return ENOBUFS; 5061 5062 doit: 5063 dma = SLIST_FIRST(&sc->txdma_list); 5064 if (dma == NULL) { 5065 ifp->if_flags |= IFF_OACTIVE; 5066 return ENOBUFS; 5067 } 5068 dmamap = dma->dmamap; 5069 dmatag = sc->bge_dmatag; 5070 dma->is_dma32 = false; 5071 5072 /* 5073 * Set up any necessary TSO state before we start packing... 5074 */ 5075 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5076 if (!use_tso) { 5077 maxsegsize = 0; 5078 } else { /* TSO setup */ 5079 unsigned mss; 5080 struct ether_header *eh; 5081 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5082 unsigned bge_hlen; 5083 struct mbuf * m0 = m_head; 5084 struct ip *ip; 5085 struct tcphdr *th; 5086 int iphl, hlen; 5087 5088 /* 5089 * XXX It would be nice if the mbuf pkthdr had offset 5090 * fields for the protocol headers. 5091 */ 5092 5093 eh = mtod(m0, struct ether_header *); 5094 switch (htons(eh->ether_type)) { 5095 case ETHERTYPE_IP: 5096 offset = ETHER_HDR_LEN; 5097 break; 5098 5099 case ETHERTYPE_VLAN: 5100 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5101 break; 5102 5103 default: 5104 /* 5105 * Don't support this protocol or encapsulation. 5106 */ 5107 return ENOBUFS; 5108 } 5109 5110 /* 5111 * TCP/IP headers are in the first mbuf; we can do 5112 * this the easy way. 5113 */ 5114 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5115 hlen = iphl + offset; 5116 if (__predict_false(m0->m_len < 5117 (hlen + sizeof(struct tcphdr)))) { 5118 5119 aprint_error_dev(sc->bge_dev, 5120 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5121 "not handled yet\n", 5122 m0->m_len, hlen+ sizeof(struct tcphdr)); 5123 #ifdef NOTYET 5124 /* 5125 * XXX jonathan (at) NetBSD.org: untested. 5126 * how to force this branch to be taken? 5127 */ 5128 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5129 5130 m_copydata(m0, offset, sizeof(ip), &ip); 5131 m_copydata(m0, hlen, sizeof(th), &th); 5132 5133 ip.ip_len = 0; 5134 5135 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5136 sizeof(ip.ip_len), &ip.ip_len); 5137 5138 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5139 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5140 5141 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5142 sizeof(th.th_sum), &th.th_sum); 5143 5144 hlen += th.th_off << 2; 5145 iptcp_opt_words = hlen; 5146 #else 5147 /* 5148 * if_wm "hard" case not yet supported, can we not 5149 * mandate it out of existence? 5150 */ 5151 (void) ip; (void)th; (void) ip_tcp_hlen; 5152 5153 return ENOBUFS; 5154 #endif 5155 } else { 5156 ip = (struct ip *) (mtod(m0, char *) + offset); 5157 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5158 ip_tcp_hlen = iphl + (th->th_off << 2); 5159 5160 /* Total IP/TCP options, in 32-bit words */ 5161 iptcp_opt_words = (ip_tcp_hlen 5162 - sizeof(struct tcphdr) 5163 - sizeof(struct ip)) >> 2; 5164 } 5165 if (BGE_IS_575X_PLUS(sc)) { 5166 th->th_sum = 0; 5167 csum_flags = 0; 5168 } else { 5169 /* 5170 * XXX jonathan (at) NetBSD.org: 5705 untested. 5171 * Requires TSO firmware patch for 5701/5703/5704. 5172 */ 5173 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5174 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5175 } 5176 5177 mss = m_head->m_pkthdr.segsz; 5178 txbd_tso_flags |= 5179 BGE_TXBDFLAG_CPU_PRE_DMA | 5180 BGE_TXBDFLAG_CPU_POST_DMA; 5181 5182 /* 5183 * Our NIC TSO-assist assumes TSO has standard, optionless 5184 * IPv4 and TCP headers, which total 40 bytes. By default, 5185 * the NIC copies 40 bytes of IP/TCP header from the 5186 * supplied header into the IP/TCP header portion of 5187 * each post-TSO-segment. If the supplied packet has IP or 5188 * TCP options, we need to tell the NIC to copy those extra 5189 * bytes into each post-TSO header, in addition to the normal 5190 * 40-byte IP/TCP header (and to leave space accordingly). 5191 * Unfortunately, the driver encoding of option length 5192 * varies across different ASIC families. 5193 */ 5194 tcp_seg_flags = 0; 5195 bge_hlen = ip_tcp_hlen >> 2; 5196 if (BGE_IS_5717_PLUS(sc)) { 5197 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5198 txbd_tso_flags |= 5199 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5200 } else if (BGE_IS_5705_PLUS(sc)) { 5201 tcp_seg_flags = bge_hlen << 11; 5202 } else { 5203 /* XXX iptcp_opt_words or bge_hlen ? */ 5204 txbd_tso_flags |= iptcp_opt_words << 12; 5205 } 5206 maxsegsize = mss | tcp_seg_flags; 5207 ip->ip_len = htons(mss + ip_tcp_hlen); 5208 ip->ip_sum = 0; 5209 5210 } /* TSO setup */ 5211 5212 have_vtag = vlan_has_tag(m_head); 5213 if (have_vtag) 5214 vtag = vlan_get_tag(m_head); 5215 5216 /* 5217 * Start packing the mbufs in this chain into 5218 * the fragment pointers. Stop when we run out 5219 * of fragments or hit the end of the mbuf chain. 5220 */ 5221 remap = true; 5222 load_again: 5223 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5224 if (__predict_false(error)) { 5225 if (error == EFBIG && remap) { 5226 struct mbuf *m; 5227 remap = false; 5228 m = m_defrag(m_head, M_NOWAIT); 5229 if (m != NULL) { 5230 KASSERT(m == m_head); 5231 goto load_again; 5232 } 5233 } 5234 return error; 5235 } 5236 /* 5237 * Sanity check: avoid coming within 16 descriptors 5238 * of the end of the ring. 5239 */ 5240 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5241 BGE_TSO_PRINTF(("%s: " 5242 " dmamap_load_mbuf too close to ring wrap\n", 5243 device_xname(sc->bge_dev))); 5244 goto fail_unload; 5245 } 5246 5247 /* Iterate over dmap-map fragments. */ 5248 f = prev_f = NULL; 5249 cur = frag = *txidx; 5250 5251 for (i = 0; i < dmamap->dm_nsegs; i++) { 5252 f = &sc->bge_rdata->bge_tx_ring[frag]; 5253 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5254 break; 5255 5256 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5257 f->bge_len = dmamap->dm_segs[i].ds_len; 5258 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5259 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5260 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5261 (prev_f != NULL && 5262 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5263 ) { 5264 /* 5265 * watchdog timeout issue was observed with TSO, 5266 * limiting DMA address space to 32bits seems to 5267 * address the issue. 5268 */ 5269 bus_dmamap_unload(dmatag, dmamap); 5270 dmatag = sc->bge_dmatag32; 5271 dmamap = dma->dmamap32; 5272 dma->is_dma32 = true; 5273 remap = true; 5274 goto load_again; 5275 } 5276 5277 /* 5278 * For 5751 and follow-ons, for TSO we must turn 5279 * off checksum-assist flag in the tx-descr, and 5280 * supply the ASIC-revision-specific encoding 5281 * of TSO flags and segsize. 5282 */ 5283 if (use_tso) { 5284 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5285 f->bge_rsvd = maxsegsize; 5286 f->bge_flags = csum_flags | txbd_tso_flags; 5287 } else { 5288 f->bge_rsvd = 0; 5289 f->bge_flags = 5290 (csum_flags | txbd_tso_flags) & 0x0fff; 5291 } 5292 } else { 5293 f->bge_rsvd = 0; 5294 f->bge_flags = csum_flags; 5295 } 5296 5297 if (have_vtag) { 5298 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5299 f->bge_vlan_tag = vtag; 5300 } else { 5301 f->bge_vlan_tag = 0; 5302 } 5303 prev_f = f; 5304 cur = frag; 5305 BGE_INC(frag, BGE_TX_RING_CNT); 5306 } 5307 5308 if (i < dmamap->dm_nsegs) { 5309 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5310 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5311 goto fail_unload; 5312 } 5313 5314 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5315 BUS_DMASYNC_PREWRITE); 5316 5317 if (frag == sc->bge_tx_saved_considx) { 5318 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5319 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5320 5321 goto fail_unload; 5322 } 5323 5324 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5325 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5326 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5327 sc->txdma[cur] = dma; 5328 sc->bge_txcnt += dmamap->dm_nsegs; 5329 5330 *txidx = frag; 5331 5332 return 0; 5333 5334 fail_unload: 5335 bus_dmamap_unload(dmatag, dmamap); 5336 ifp->if_flags |= IFF_OACTIVE; 5337 5338 return ENOBUFS; 5339 } 5340 5341 /* 5342 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5343 * to the mbuf data regions directly in the transmit descriptors. 5344 */ 5345 static void 5346 bge_start(struct ifnet *ifp) 5347 { 5348 struct bge_softc *sc; 5349 struct mbuf *m_head = NULL; 5350 struct mbuf *m; 5351 uint32_t prodidx; 5352 int pkts = 0; 5353 int error; 5354 5355 sc = ifp->if_softc; 5356 5357 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5358 return; 5359 5360 prodidx = sc->bge_tx_prodidx; 5361 5362 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5363 IFQ_POLL(&ifp->if_snd, m_head); 5364 if (m_head == NULL) 5365 break; 5366 5367 #if 0 5368 /* 5369 * XXX 5370 * safety overkill. If this is a fragmented packet chain 5371 * with delayed TCP/UDP checksums, then only encapsulate 5372 * it if we have enough descriptors to handle the entire 5373 * chain at once. 5374 * (paranoia -- may not actually be needed) 5375 */ 5376 if (m_head->m_flags & M_FIRSTFRAG && 5377 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5378 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5379 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5380 ifp->if_flags |= IFF_OACTIVE; 5381 break; 5382 } 5383 } 5384 #endif 5385 5386 /* 5387 * Pack the data into the transmit ring. If we 5388 * don't have room, set the OACTIVE flag and wait 5389 * for the NIC to drain the ring. 5390 */ 5391 error = bge_encap(sc, m_head, &prodidx); 5392 if (__predict_false(error)) { 5393 if (ifp->if_flags & IFF_OACTIVE) { 5394 /* just wait for the transmit ring to drain */ 5395 break; 5396 } 5397 IFQ_DEQUEUE(&ifp->if_snd, m); 5398 KASSERT(m == m_head); 5399 m_freem(m_head); 5400 continue; 5401 } 5402 5403 /* now we are committed to transmit the packet */ 5404 IFQ_DEQUEUE(&ifp->if_snd, m); 5405 KASSERT(m == m_head); 5406 pkts++; 5407 5408 /* 5409 * If there's a BPF listener, bounce a copy of this frame 5410 * to him. 5411 */ 5412 bpf_mtap(ifp, m_head, BPF_D_OUT); 5413 } 5414 if (pkts == 0) 5415 return; 5416 5417 /* Transmit */ 5418 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5419 /* 5700 b2 errata */ 5420 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5421 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5422 5423 sc->bge_tx_prodidx = prodidx; 5424 5425 /* 5426 * Set a timeout in case the chip goes out to lunch. 5427 */ 5428 ifp->if_timer = 5; 5429 } 5430 5431 static int 5432 bge_init(struct ifnet *ifp) 5433 { 5434 struct bge_softc *sc = ifp->if_softc; 5435 const uint16_t *m; 5436 uint32_t mode, reg; 5437 int s, error = 0; 5438 5439 s = splnet(); 5440 5441 ifp = &sc->ethercom.ec_if; 5442 5443 /* Cancel pending I/O and flush buffers. */ 5444 bge_stop(ifp, 0); 5445 5446 bge_stop_fw(sc); 5447 bge_sig_pre_reset(sc, BGE_RESET_START); 5448 bge_reset(sc); 5449 bge_sig_legacy(sc, BGE_RESET_START); 5450 5451 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5452 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5453 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5454 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5455 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5456 5457 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5458 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5459 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5460 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5461 5462 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5463 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5464 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5465 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5466 5467 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5468 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5469 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5470 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5471 } 5472 5473 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5474 pcireg_t aercap; 5475 5476 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5477 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5478 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5479 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5480 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5481 5482 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5483 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5484 | BGE_PCIE_EIDLE_DELAY_13CLK; 5485 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5486 5487 /* Clear correctable error */ 5488 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5489 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5490 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5491 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5492 5493 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5494 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5495 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5496 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5497 } 5498 5499 bge_sig_post_reset(sc, BGE_RESET_START); 5500 5501 bge_chipinit(sc); 5502 5503 /* 5504 * Init the various state machines, ring 5505 * control blocks and firmware. 5506 */ 5507 error = bge_blockinit(sc); 5508 if (error != 0) { 5509 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5510 error); 5511 splx(s); 5512 return error; 5513 } 5514 5515 ifp = &sc->ethercom.ec_if; 5516 5517 /* 5718 step 25, 57XX step 54 */ 5518 /* Specify MTU. */ 5519 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5520 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5521 5522 /* 5718 step 23 */ 5523 /* Load our MAC address. */ 5524 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5525 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5526 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5527 5528 /* Enable or disable promiscuous mode as needed. */ 5529 if (ifp->if_flags & IFF_PROMISC) 5530 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5531 else 5532 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5533 5534 /* Program multicast filter. */ 5535 bge_setmulti(sc); 5536 5537 /* Init RX ring. */ 5538 bge_init_rx_ring_std(sc); 5539 5540 /* 5541 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5542 * memory to insure that the chip has in fact read the first 5543 * entry of the ring. 5544 */ 5545 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5546 uint32_t v, i; 5547 for (i = 0; i < 10; i++) { 5548 DELAY(20); 5549 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5550 if (v == (MCLBYTES - ETHER_ALIGN)) 5551 break; 5552 } 5553 if (i == 10) 5554 aprint_error_dev(sc->bge_dev, 5555 "5705 A0 chip failed to load RX ring\n"); 5556 } 5557 5558 /* Init jumbo RX ring. */ 5559 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5560 bge_init_rx_ring_jumbo(sc); 5561 5562 /* Init our RX return ring index */ 5563 sc->bge_rx_saved_considx = 0; 5564 5565 /* Init TX ring. */ 5566 bge_init_tx_ring(sc); 5567 5568 /* 5718 step 63, 57XX step 94 */ 5569 /* Enable TX MAC state machine lockup fix. */ 5570 mode = CSR_READ_4(sc, BGE_TX_MODE); 5571 if (BGE_IS_5755_PLUS(sc) || 5572 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5573 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5574 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5575 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5576 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5577 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5578 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5579 } 5580 5581 /* Turn on transmitter */ 5582 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5583 /* 5718 step 64 */ 5584 DELAY(100); 5585 5586 /* 5718 step 65, 57XX step 95 */ 5587 /* Turn on receiver */ 5588 mode = CSR_READ_4(sc, BGE_RX_MODE); 5589 if (BGE_IS_5755_PLUS(sc)) 5590 mode |= BGE_RXMODE_IPV6_ENABLE; 5591 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5592 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5593 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5594 /* 5718 step 66 */ 5595 DELAY(10); 5596 5597 /* 5718 step 12, 57XX step 37 */ 5598 /* 5599 * XXX Doucments of 5718 series and 577xx say the recommended value 5600 * is 1, but tg3 set 1 only on 57765 series. 5601 */ 5602 if (BGE_IS_57765_PLUS(sc)) 5603 reg = 1; 5604 else 5605 reg = 2; 5606 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5607 5608 /* Tell firmware we're alive. */ 5609 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5610 5611 /* Enable host interrupts. */ 5612 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5613 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5614 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5615 5616 if ((error = bge_ifmedia_upd(ifp)) != 0) 5617 goto out; 5618 5619 ifp->if_flags |= IFF_RUNNING; 5620 ifp->if_flags &= ~IFF_OACTIVE; 5621 5622 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5623 5624 out: 5625 sc->bge_if_flags = ifp->if_flags; 5626 splx(s); 5627 5628 return error; 5629 } 5630 5631 /* 5632 * Set media options. 5633 */ 5634 static int 5635 bge_ifmedia_upd(struct ifnet *ifp) 5636 { 5637 struct bge_softc *sc = ifp->if_softc; 5638 struct mii_data *mii = &sc->bge_mii; 5639 struct ifmedia *ifm = &sc->bge_ifmedia; 5640 int rc; 5641 5642 /* If this is a 1000baseX NIC, enable the TBI port. */ 5643 if (sc->bge_flags & BGEF_FIBER_TBI) { 5644 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5645 return EINVAL; 5646 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5647 case IFM_AUTO: 5648 /* 5649 * The BCM5704 ASIC appears to have a special 5650 * mechanism for programming the autoneg 5651 * advertisement registers in TBI mode. 5652 */ 5653 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5654 uint32_t sgdig; 5655 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5656 if (sgdig & BGE_SGDIGSTS_DONE) { 5657 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5658 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5659 sgdig |= BGE_SGDIGCFG_AUTO | 5660 BGE_SGDIGCFG_PAUSE_CAP | 5661 BGE_SGDIGCFG_ASYM_PAUSE; 5662 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5663 sgdig | BGE_SGDIGCFG_SEND); 5664 DELAY(5); 5665 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5666 sgdig); 5667 } 5668 } 5669 break; 5670 case IFM_1000_SX: 5671 if ((ifm->ifm_media & IFM_FDX) != 0) { 5672 BGE_CLRBIT(sc, BGE_MAC_MODE, 5673 BGE_MACMODE_HALF_DUPLEX); 5674 } else { 5675 BGE_SETBIT(sc, BGE_MAC_MODE, 5676 BGE_MACMODE_HALF_DUPLEX); 5677 } 5678 DELAY(40); 5679 break; 5680 default: 5681 return EINVAL; 5682 } 5683 /* XXX 802.3x flow control for 1000BASE-SX */ 5684 return 0; 5685 } 5686 5687 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5688 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5689 uint32_t reg; 5690 5691 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5692 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5693 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5694 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5695 } 5696 } 5697 5698 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5699 if ((rc = mii_mediachg(mii)) == ENXIO) 5700 return 0; 5701 5702 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5703 uint32_t reg; 5704 5705 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5706 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5707 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5708 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5709 delay(40); 5710 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5711 } 5712 } 5713 5714 /* 5715 * Force an interrupt so that we will call bge_link_upd 5716 * if needed and clear any pending link state attention. 5717 * Without this we are not getting any further interrupts 5718 * for link state changes and thus will not UP the link and 5719 * not be able to send in bge_start. The only way to get 5720 * things working was to receive a packet and get a RX intr. 5721 */ 5722 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5723 sc->bge_flags & BGEF_IS_5788) 5724 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5725 else 5726 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5727 5728 return rc; 5729 } 5730 5731 /* 5732 * Report current media status. 5733 */ 5734 static void 5735 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5736 { 5737 struct bge_softc *sc = ifp->if_softc; 5738 struct mii_data *mii = &sc->bge_mii; 5739 5740 if (sc->bge_flags & BGEF_FIBER_TBI) { 5741 ifmr->ifm_status = IFM_AVALID; 5742 ifmr->ifm_active = IFM_ETHER; 5743 if (CSR_READ_4(sc, BGE_MAC_STS) & 5744 BGE_MACSTAT_TBI_PCS_SYNCHED) 5745 ifmr->ifm_status |= IFM_ACTIVE; 5746 ifmr->ifm_active |= IFM_1000_SX; 5747 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5748 ifmr->ifm_active |= IFM_HDX; 5749 else 5750 ifmr->ifm_active |= IFM_FDX; 5751 return; 5752 } 5753 5754 mii_pollstat(mii); 5755 ifmr->ifm_status = mii->mii_media_status; 5756 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5757 sc->bge_flowflags; 5758 } 5759 5760 static int 5761 bge_ifflags_cb(struct ethercom *ec) 5762 { 5763 struct ifnet *ifp = &ec->ec_if; 5764 struct bge_softc *sc = ifp->if_softc; 5765 int change = ifp->if_flags ^ sc->bge_if_flags; 5766 5767 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 5768 return ENETRESET; 5769 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5770 return 0; 5771 5772 if ((ifp->if_flags & IFF_PROMISC) == 0) 5773 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5774 else 5775 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5776 5777 bge_setmulti(sc); 5778 5779 sc->bge_if_flags = ifp->if_flags; 5780 return 0; 5781 } 5782 5783 static int 5784 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5785 { 5786 struct bge_softc *sc = ifp->if_softc; 5787 struct ifreq *ifr = (struct ifreq *) data; 5788 int s, error = 0; 5789 struct mii_data *mii; 5790 5791 s = splnet(); 5792 5793 switch (command) { 5794 case SIOCSIFMEDIA: 5795 /* XXX Flow control is not supported for 1000BASE-SX */ 5796 if (sc->bge_flags & BGEF_FIBER_TBI) { 5797 ifr->ifr_media &= ~IFM_ETH_FMASK; 5798 sc->bge_flowflags = 0; 5799 } 5800 5801 /* Flow control requires full-duplex mode. */ 5802 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5803 (ifr->ifr_media & IFM_FDX) == 0) { 5804 ifr->ifr_media &= ~IFM_ETH_FMASK; 5805 } 5806 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5807 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5808 /* We can do both TXPAUSE and RXPAUSE. */ 5809 ifr->ifr_media |= 5810 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5811 } 5812 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5813 } 5814 /* FALLTHROUGH */ 5815 case SIOCGIFMEDIA: 5816 if (sc->bge_flags & BGEF_FIBER_TBI) { 5817 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5818 command); 5819 } else { 5820 mii = &sc->bge_mii; 5821 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5822 command); 5823 } 5824 break; 5825 default: 5826 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5827 break; 5828 5829 error = 0; 5830 5831 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5832 ; 5833 else if (ifp->if_flags & IFF_RUNNING) 5834 bge_setmulti(sc); 5835 break; 5836 } 5837 5838 splx(s); 5839 5840 return error; 5841 } 5842 5843 static void 5844 bge_watchdog(struct ifnet *ifp) 5845 { 5846 struct bge_softc *sc; 5847 uint32_t status; 5848 5849 sc = ifp->if_softc; 5850 5851 /* If pause frames are active then don't reset the hardware. */ 5852 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5853 status = CSR_READ_4(sc, BGE_RX_STS); 5854 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5855 /* 5856 * If link partner has us in XOFF state then wait for 5857 * the condition to clear. 5858 */ 5859 CSR_WRITE_4(sc, BGE_RX_STS, status); 5860 ifp->if_timer = 5; 5861 return; 5862 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5863 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5864 /* 5865 * If link partner has us in XOFF state then wait for 5866 * the condition to clear. 5867 */ 5868 CSR_WRITE_4(sc, BGE_RX_STS, status); 5869 ifp->if_timer = 5; 5870 return; 5871 } 5872 /* 5873 * Any other condition is unexpected and the controller 5874 * should be reset. 5875 */ 5876 } 5877 5878 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5879 5880 ifp->if_flags &= ~IFF_RUNNING; 5881 bge_init(ifp); 5882 5883 ifp->if_oerrors++; 5884 } 5885 5886 static void 5887 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5888 { 5889 int i; 5890 5891 BGE_CLRBIT_FLUSH(sc, reg, bit); 5892 5893 for (i = 0; i < 1000; i++) { 5894 delay(100); 5895 if ((CSR_READ_4(sc, reg) & bit) == 0) 5896 return; 5897 } 5898 5899 /* 5900 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5901 * on some environment (and once after boot?) 5902 */ 5903 if (reg != BGE_SRS_MODE) 5904 aprint_error_dev(sc->bge_dev, 5905 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5906 (u_long)reg, bit); 5907 } 5908 5909 /* 5910 * Stop the adapter and free any mbufs allocated to the 5911 * RX and TX lists. 5912 */ 5913 static void 5914 bge_stop(struct ifnet *ifp, int disable) 5915 { 5916 struct bge_softc *sc = ifp->if_softc; 5917 5918 if (disable) { 5919 sc->bge_detaching = 1; 5920 callout_halt(&sc->bge_timeout, NULL); 5921 } else 5922 callout_stop(&sc->bge_timeout); 5923 5924 /* Disable host interrupts. */ 5925 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5926 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5927 5928 /* 5929 * Tell firmware we're shutting down. 5930 */ 5931 bge_stop_fw(sc); 5932 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5933 5934 /* 5935 * Disable all of the receiver blocks. 5936 */ 5937 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5938 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5939 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5940 if (BGE_IS_5700_FAMILY(sc)) 5941 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5942 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5943 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5944 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5945 5946 /* 5947 * Disable all of the transmit blocks. 5948 */ 5949 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5950 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5951 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5952 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5953 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5954 if (BGE_IS_5700_FAMILY(sc)) 5955 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5956 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5957 5958 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5959 delay(40); 5960 5961 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5962 5963 /* 5964 * Shut down all of the memory managers and related 5965 * state machines. 5966 */ 5967 /* 5718 step 5a,5b */ 5968 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5969 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5970 if (BGE_IS_5700_FAMILY(sc)) 5971 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5972 5973 /* 5718 step 5c,5d */ 5974 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5975 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5976 5977 if (BGE_IS_5700_FAMILY(sc)) { 5978 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5979 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5980 } 5981 5982 bge_reset(sc); 5983 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5984 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5985 5986 /* 5987 * Keep the ASF firmware running if up. 5988 */ 5989 if (sc->bge_asf_mode & ASF_STACKUP) 5990 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5991 else 5992 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5993 5994 /* Free the RX lists. */ 5995 bge_free_rx_ring_std(sc, disable); 5996 5997 /* Free jumbo RX list. */ 5998 if (BGE_IS_JUMBO_CAPABLE(sc)) 5999 bge_free_rx_ring_jumbo(sc); 6000 6001 /* Free TX buffers. */ 6002 bge_free_tx_ring(sc, disable); 6003 6004 /* 6005 * Isolate/power down the PHY. 6006 */ 6007 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6008 mii_down(&sc->bge_mii); 6009 6010 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6011 6012 /* Clear MAC's link state (PHY may still have link UP). */ 6013 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6014 6015 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6016 } 6017 6018 static void 6019 bge_link_upd(struct bge_softc *sc) 6020 { 6021 struct ifnet *ifp = &sc->ethercom.ec_if; 6022 struct mii_data *mii = &sc->bge_mii; 6023 uint32_t status; 6024 uint16_t phyval; 6025 int link; 6026 6027 /* Clear 'pending link event' flag */ 6028 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6029 6030 /* 6031 * Process link state changes. 6032 * Grrr. The link status word in the status block does 6033 * not work correctly on the BCM5700 rev AX and BX chips, 6034 * according to all available information. Hence, we have 6035 * to enable MII interrupts in order to properly obtain 6036 * async link changes. Unfortunately, this also means that 6037 * we have to read the MAC status register to detect link 6038 * changes, thereby adding an additional register access to 6039 * the interrupt handler. 6040 */ 6041 6042 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6043 status = CSR_READ_4(sc, BGE_MAC_STS); 6044 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6045 mii_pollstat(mii); 6046 6047 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6048 mii->mii_media_status & IFM_ACTIVE && 6049 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6050 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6051 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6052 (!(mii->mii_media_status & IFM_ACTIVE) || 6053 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6054 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6055 6056 /* Clear the interrupt */ 6057 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6058 BGE_EVTENB_MI_INTERRUPT); 6059 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6060 BRGPHY_MII_ISR, &phyval); 6061 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6062 BRGPHY_MII_IMR, BRGPHY_INTRS); 6063 } 6064 return; 6065 } 6066 6067 if (sc->bge_flags & BGEF_FIBER_TBI) { 6068 status = CSR_READ_4(sc, BGE_MAC_STS); 6069 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6070 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6071 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6072 if (BGE_ASICREV(sc->bge_chipid) 6073 == BGE_ASICREV_BCM5704) { 6074 BGE_CLRBIT(sc, BGE_MAC_MODE, 6075 BGE_MACMODE_TBI_SEND_CFGS); 6076 DELAY(40); 6077 } 6078 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6079 if_link_state_change(ifp, LINK_STATE_UP); 6080 } 6081 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6082 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6083 if_link_state_change(ifp, LINK_STATE_DOWN); 6084 } 6085 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6086 /* 6087 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6088 * bit in status word always set. Workaround this bug by 6089 * reading PHY link status directly. 6090 */ 6091 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6092 BGE_STS_LINK : 0; 6093 6094 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6095 mii_pollstat(mii); 6096 6097 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6098 mii->mii_media_status & IFM_ACTIVE && 6099 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6100 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6101 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6102 (!(mii->mii_media_status & IFM_ACTIVE) || 6103 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6104 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6105 } 6106 } else { 6107 /* 6108 * For controllers that call mii_tick, we have to poll 6109 * link status. 6110 */ 6111 mii_pollstat(mii); 6112 } 6113 6114 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6115 uint32_t reg, scale; 6116 6117 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6118 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6119 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6120 scale = 65; 6121 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6122 scale = 6; 6123 else 6124 scale = 12; 6125 6126 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6127 ~BGE_MISCCFG_TIMER_PRESCALER; 6128 reg |= scale << 1; 6129 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6130 } 6131 /* Clear the attention */ 6132 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6133 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6134 BGE_MACSTAT_LINK_CHANGED); 6135 } 6136 6137 static int 6138 bge_sysctl_verify(SYSCTLFN_ARGS) 6139 { 6140 int error, t; 6141 struct sysctlnode node; 6142 6143 node = *rnode; 6144 t = *(int*)rnode->sysctl_data; 6145 node.sysctl_data = &t; 6146 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6147 if (error || newp == NULL) 6148 return error; 6149 6150 #if 0 6151 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6152 node.sysctl_num, rnode->sysctl_num)); 6153 #endif 6154 6155 if (node.sysctl_num == bge_rxthresh_nodenum) { 6156 if (t < 0 || t >= NBGE_RX_THRESH) 6157 return EINVAL; 6158 bge_update_all_threshes(t); 6159 } else 6160 return EINVAL; 6161 6162 *(int*)rnode->sysctl_data = t; 6163 6164 return 0; 6165 } 6166 6167 /* 6168 * Set up sysctl(3) MIB, hw.bge.*. 6169 */ 6170 static void 6171 bge_sysctl_init(struct bge_softc *sc) 6172 { 6173 int rc, bge_root_num; 6174 const struct sysctlnode *node; 6175 6176 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6177 0, CTLTYPE_NODE, "bge", 6178 SYSCTL_DESCR("BGE interface controls"), 6179 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6180 goto out; 6181 } 6182 6183 bge_root_num = node->sysctl_num; 6184 6185 /* BGE Rx interrupt mitigation level */ 6186 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6187 CTLFLAG_READWRITE, 6188 CTLTYPE_INT, "rx_lvl", 6189 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6190 bge_sysctl_verify, 0, 6191 &bge_rx_thresh_lvl, 6192 0, CTL_HW, bge_root_num, CTL_CREATE, 6193 CTL_EOL)) != 0) { 6194 goto out; 6195 } 6196 6197 bge_rxthresh_nodenum = node->sysctl_num; 6198 6199 return; 6200 6201 out: 6202 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6203 } 6204 6205 #ifdef BGE_DEBUG 6206 void 6207 bge_debug_info(struct bge_softc *sc) 6208 { 6209 6210 printf("Hardware Flags:\n"); 6211 if (BGE_IS_57765_PLUS(sc)) 6212 printf(" - 57765 Plus\n"); 6213 if (BGE_IS_5717_PLUS(sc)) 6214 printf(" - 5717 Plus\n"); 6215 if (BGE_IS_5755_PLUS(sc)) 6216 printf(" - 5755 Plus\n"); 6217 if (BGE_IS_575X_PLUS(sc)) 6218 printf(" - 575X Plus\n"); 6219 if (BGE_IS_5705_PLUS(sc)) 6220 printf(" - 5705 Plus\n"); 6221 if (BGE_IS_5714_FAMILY(sc)) 6222 printf(" - 5714 Family\n"); 6223 if (BGE_IS_5700_FAMILY(sc)) 6224 printf(" - 5700 Family\n"); 6225 if (sc->bge_flags & BGEF_IS_5788) 6226 printf(" - 5788\n"); 6227 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6228 printf(" - Supports Jumbo Frames\n"); 6229 if (sc->bge_flags & BGEF_NO_EEPROM) 6230 printf(" - No EEPROM\n"); 6231 if (sc->bge_flags & BGEF_PCIX) 6232 printf(" - PCI-X Bus\n"); 6233 if (sc->bge_flags & BGEF_PCIE) 6234 printf(" - PCI Express Bus\n"); 6235 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6236 printf(" - RX Alignment Bug\n"); 6237 if (sc->bge_flags & BGEF_APE) 6238 printf(" - APE\n"); 6239 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6240 printf(" - CPMU\n"); 6241 if (sc->bge_flags & BGEF_TSO) 6242 printf(" - TSO\n"); 6243 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6244 printf(" - TAGGED_STATUS\n"); 6245 6246 /* PHY related */ 6247 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6248 printf(" - No 3 LEDs\n"); 6249 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6250 printf(" - CRC bug\n"); 6251 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6252 printf(" - ADC bug\n"); 6253 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6254 printf(" - 5704 A0 bug\n"); 6255 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6256 printf(" - jitter bug\n"); 6257 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6258 printf(" - BER bug\n"); 6259 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6260 printf(" - adjust trim\n"); 6261 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6262 printf(" - no wirespeed\n"); 6263 6264 /* ASF related */ 6265 if (sc->bge_asf_mode & ASF_ENABLE) 6266 printf(" - ASF enable\n"); 6267 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6268 printf(" - ASF new handshake\n"); 6269 if (sc->bge_asf_mode & ASF_STACKUP) 6270 printf(" - ASF stackup\n"); 6271 } 6272 #endif /* BGE_DEBUG */ 6273 6274 static int 6275 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6276 { 6277 prop_dictionary_t dict; 6278 prop_data_t ea; 6279 6280 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6281 return 1; 6282 6283 dict = device_properties(sc->bge_dev); 6284 ea = prop_dictionary_get(dict, "mac-address"); 6285 if (ea != NULL) { 6286 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6287 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6288 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6289 return 0; 6290 } 6291 6292 return 1; 6293 } 6294 6295 static int 6296 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6297 { 6298 uint32_t mac_addr; 6299 6300 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6301 if ((mac_addr >> 16) == 0x484b) { 6302 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6303 ether_addr[1] = (uint8_t)mac_addr; 6304 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6305 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6306 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6307 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6308 ether_addr[5] = (uint8_t)mac_addr; 6309 return 0; 6310 } 6311 return 1; 6312 } 6313 6314 static int 6315 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6316 { 6317 int mac_offset = BGE_EE_MAC_OFFSET; 6318 6319 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6320 mac_offset = BGE_EE_MAC_OFFSET_5906; 6321 6322 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6323 ETHER_ADDR_LEN)); 6324 } 6325 6326 static int 6327 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6328 { 6329 6330 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6331 return 1; 6332 6333 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6334 ETHER_ADDR_LEN)); 6335 } 6336 6337 static int 6338 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6339 { 6340 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6341 /* NOTE: Order is critical */ 6342 bge_get_eaddr_fw, 6343 bge_get_eaddr_mem, 6344 bge_get_eaddr_nvram, 6345 bge_get_eaddr_eeprom, 6346 NULL 6347 }; 6348 const bge_eaddr_fcn_t *func; 6349 6350 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6351 if ((*func)(sc, eaddr) == 0) 6352 break; 6353 } 6354 return (*func == NULL ? ENXIO : 0); 6355 } 6356
Indexes created Tue Sep 23 14:10:03 GMT 2025