if_bge.c revision 1.340
1 /* $NetBSD: if_bge.c,v 1.340 2019/11/25 04:52:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.340 2019/11/25 04:52:27 msaitoh Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/callout.h> 87 #include <sys/sockio.h> 88 #include <sys/mbuf.h> 89 #include <sys/malloc.h> 90 #include <sys/kernel.h> 91 #include <sys/device.h> 92 #include <sys/socket.h> 93 #include <sys/sysctl.h> 94 #include <sys/rndsource.h> 95 96 #include <net/if.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_ether.h> 100 #include <net/bpf.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 /* Headers for TCP Segmentation Offload (TSO) */ 110 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 111 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 112 #include <netinet/ip.h> /* for struct ip */ 113 #include <netinet/tcp.h> /* for struct tcphdr */ 114 115 #include <dev/pci/pcireg.h> 116 #include <dev/pci/pcivar.h> 117 #include <dev/pci/pcidevs.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/miidevs.h> 122 #include <dev/mii/brgphyreg.h> 123 124 #include <dev/pci/if_bgereg.h> 125 #include <dev/pci/if_bgevar.h> 126 127 #include <prop/proplib.h> 128 129 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 130 131 132 /* 133 * Tunable thresholds for rx-side bge interrupt mitigation. 134 */ 135 136 /* 137 * The pairs of values below were obtained from empirical measurement 138 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 139 * interrupt for every N packets received, where N is, approximately, 140 * the second value (rx_max_bds) in each pair. The values are chosen 141 * such that moving from one pair to the succeeding pair was observed 142 * to roughly halve interrupt rate under sustained input packet load. 143 * The values were empirically chosen to avoid overflowing internal 144 * limits on the bcm5700: increasing rx_ticks much beyond 600 145 * results in internal wrapping and higher interrupt rates. 146 * The limit of 46 frames was chosen to match NFS workloads. 147 * 148 * These values also work well on bcm5701, bcm5704C, and (less 149 * tested) bcm5703. On other chipsets, (including the Altima chip 150 * family), the larger values may overflow internal chip limits, 151 * leading to increasing interrupt rates rather than lower interrupt 152 * rates. 153 * 154 * Applications using heavy interrupt mitigation (interrupting every 155 * 32 or 46 frames) in both directions may need to increase the TCP 156 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 157 * full link bandwidth, due to ACKs and window updates lingering 158 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 159 */ 160 static const struct bge_load_rx_thresh { 161 int rx_ticks; 162 int rx_max_bds; } 163 bge_rx_threshes[] = { 164 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 165 { 32, 2 }, 166 { 50, 4 }, 167 { 100, 8 }, 168 { 192, 16 }, 169 { 416, 32 }, 170 { 598, 46 } 171 }; 172 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 173 174 /* XXX patchable; should be sysctl'able */ 175 static int bge_auto_thresh = 1; 176 static int bge_rx_thresh_lvl; 177 178 static int bge_rxthresh_nodenum; 179 180 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 181 182 static uint32_t bge_chipid(const struct pci_attach_args *); 183 static int bge_can_use_msi(struct bge_softc *); 184 static int bge_probe(device_t, cfdata_t, void *); 185 static void bge_attach(device_t, device_t, void *); 186 static int bge_detach(device_t, int); 187 static void bge_release_resources(struct bge_softc *); 188 189 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 190 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 191 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 194 195 static void bge_txeof(struct bge_softc *); 196 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 197 static void bge_rxeof(struct bge_softc *); 198 199 static void bge_asf_driver_up (struct bge_softc *); 200 static void bge_tick(void *); 201 static void bge_stats_update(struct bge_softc *); 202 static void bge_stats_update_regs(struct bge_softc *); 203 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 204 205 static int bge_intr(void *); 206 static void bge_start(struct ifnet *); 207 static int bge_ifflags_cb(struct ethercom *); 208 static int bge_ioctl(struct ifnet *, u_long, void *); 209 static int bge_init(struct ifnet *); 210 static void bge_stop(struct ifnet *, int); 211 static void bge_watchdog(struct ifnet *); 212 static int bge_ifmedia_upd(struct ifnet *); 213 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 214 215 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 216 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 217 218 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 220 static void bge_setmulti(struct bge_softc *); 221 222 static void bge_handle_events(struct bge_softc *); 223 static int bge_alloc_jumbo_mem(struct bge_softc *); 224 #if 0 /* XXX */ 225 static void bge_free_jumbo_mem(struct bge_softc *); 226 #endif 227 static void *bge_jalloc(struct bge_softc *); 228 static void bge_jfree(struct mbuf *, void *, size_t, void *); 229 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 230 bus_dmamap_t); 231 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 232 static int bge_init_rx_ring_std(struct bge_softc *); 233 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 234 static int bge_init_rx_ring_jumbo(struct bge_softc *); 235 static void bge_free_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_tx_ring(struct bge_softc *m, bool); 237 static int bge_init_tx_ring(struct bge_softc *); 238 239 static int bge_chipinit(struct bge_softc *); 240 static int bge_blockinit(struct bge_softc *); 241 static int bge_phy_addr(struct bge_softc *); 242 static uint32_t bge_readmem_ind(struct bge_softc *, int); 243 static void bge_writemem_ind(struct bge_softc *, int, int); 244 static void bge_writembx(struct bge_softc *, int, int); 245 static void bge_writembx_flush(struct bge_softc *, int, int); 246 static void bge_writemem_direct(struct bge_softc *, int, int); 247 static void bge_writereg_ind(struct bge_softc *, int, int); 248 static void bge_set_max_readrq(struct bge_softc *); 249 250 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 251 static int bge_miibus_writereg(device_t, int, int, uint16_t); 252 static void bge_miibus_statchg(struct ifnet *); 253 254 #define BGE_RESET_SHUTDOWN 0 255 #define BGE_RESET_START 1 256 #define BGE_RESET_SUSPEND 2 257 static void bge_sig_post_reset(struct bge_softc *, int); 258 static void bge_sig_legacy(struct bge_softc *, int); 259 static void bge_sig_pre_reset(struct bge_softc *, int); 260 static void bge_wait_for_event_ack(struct bge_softc *); 261 static void bge_stop_fw(struct bge_softc *); 262 static int bge_reset(struct bge_softc *); 263 static void bge_link_upd(struct bge_softc *); 264 static void bge_sysctl_init(struct bge_softc *); 265 static int bge_sysctl_verify(SYSCTLFN_PROTO); 266 267 static void bge_ape_lock_init(struct bge_softc *); 268 static void bge_ape_read_fw_ver(struct bge_softc *); 269 static int bge_ape_lock(struct bge_softc *, int); 270 static void bge_ape_unlock(struct bge_softc *, int); 271 static void bge_ape_send_event(struct bge_softc *, uint32_t); 272 static void bge_ape_driver_state_change(struct bge_softc *, int); 273 274 #ifdef BGE_DEBUG 275 #define DPRINTF(x) if (bgedebug) printf x 276 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 277 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 278 int bgedebug = 0; 279 int bge_tso_debug = 0; 280 void bge_debug_info(struct bge_softc *); 281 #else 282 #define DPRINTF(x) 283 #define DPRINTFN(n, x) 284 #define BGE_TSO_PRINTF(x) 285 #endif 286 287 #ifdef BGE_EVENT_COUNTERS 288 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 289 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 290 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 291 #else 292 #define BGE_EVCNT_INCR(ev) /* nothing */ 293 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 294 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 295 #endif 296 297 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 298 /* 299 * The BCM5700 documentation seems to indicate that the hardware still has the 300 * Alteon vendor ID burned into it, though it should always be overridden by 301 * the value in the EEPROM. We'll check for it anyway. 302 */ 303 static const struct bge_product { 304 pci_vendor_id_t bp_vendor; 305 pci_product_id_t bp_product; 306 const char *bp_name; 307 } bge_products[] = { 308 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 309 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 310 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 311 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 312 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 313 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 314 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 315 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 319 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 320 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 323 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 333 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 335 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 349 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 351 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 354 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 356 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 358 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 363 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 364 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 367 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 368 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 370 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 371 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 372 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 373 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 375 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 376 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 377 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 379 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 380 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 381 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 382 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 383 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 399 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 400 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 401 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 402 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 403 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 404 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 405 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 406 { 0, 0, NULL }, 407 }; 408 409 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 410 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 411 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 412 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 413 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 414 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 415 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 416 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 417 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 418 419 static const struct bge_revision { 420 uint32_t br_chipid; 421 const char *br_name; 422 } bge_revisions[] = { 423 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 424 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 425 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 426 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 427 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 428 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 429 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 430 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 431 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 432 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 433 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 434 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 435 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 436 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 437 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 438 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 439 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 440 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 441 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 442 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 443 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 444 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 445 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 446 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 447 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 448 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 449 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 450 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 451 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 452 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 453 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 454 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 455 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 456 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 457 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 458 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 459 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 460 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 461 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 462 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 463 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 464 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 465 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 466 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 467 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 468 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 469 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 470 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 471 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 472 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 473 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 474 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 475 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 476 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 477 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 478 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 479 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 480 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 481 /* 5754 and 5787 share the same ASIC ID */ 482 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 483 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 484 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 485 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 486 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 487 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 488 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 489 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 490 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 491 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 492 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 493 494 { 0, NULL } 495 }; 496 497 /* 498 * Some defaults for major revisions, so that newer steppings 499 * that we don't know about have a shot at working. 500 */ 501 static const struct bge_revision bge_majorrevs[] = { 502 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 503 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 504 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 505 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 506 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 507 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 508 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 509 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 510 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 511 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 512 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 513 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 514 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 515 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 516 /* 5754 and 5787 share the same ASIC ID */ 517 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 518 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 519 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 520 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 521 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 522 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 523 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 524 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 525 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 526 527 { 0, NULL } 528 }; 529 530 static int bge_allow_asf = 1; 531 532 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 533 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 534 535 static uint32_t 536 bge_readmem_ind(struct bge_softc *sc, int off) 537 { 538 pcireg_t val; 539 540 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 541 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 542 return 0; 543 544 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 545 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 546 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 547 return val; 548 } 549 550 static void 551 bge_writemem_ind(struct bge_softc *sc, int off, int val) 552 { 553 554 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 556 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 557 } 558 559 /* 560 * PCI Express only 561 */ 562 static void 563 bge_set_max_readrq(struct bge_softc *sc) 564 { 565 pcireg_t val; 566 567 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 568 + PCIE_DCSR); 569 val &= ~PCIE_DCSR_MAX_READ_REQ; 570 switch (sc->bge_expmrq) { 571 case 2048: 572 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 573 break; 574 case 4096: 575 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 576 break; 577 default: 578 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 579 break; 580 } 581 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 582 + PCIE_DCSR, val); 583 } 584 585 #ifdef notdef 586 static uint32_t 587 bge_readreg_ind(struct bge_softc *sc, int off) 588 { 589 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 590 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 591 } 592 #endif 593 594 static void 595 bge_writereg_ind(struct bge_softc *sc, int off, int val) 596 { 597 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 599 } 600 601 static void 602 bge_writemem_direct(struct bge_softc *sc, int off, int val) 603 { 604 CSR_WRITE_4(sc, off, val); 605 } 606 607 static void 608 bge_writembx(struct bge_softc *sc, int off, int val) 609 { 610 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 611 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 612 613 CSR_WRITE_4(sc, off, val); 614 } 615 616 static void 617 bge_writembx_flush(struct bge_softc *sc, int off, int val) 618 { 619 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 620 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 621 622 CSR_WRITE_4_FLUSH(sc, off, val); 623 } 624 625 /* 626 * Clear all stale locks and select the lock for this driver instance. 627 */ 628 void 629 bge_ape_lock_init(struct bge_softc *sc) 630 { 631 struct pci_attach_args *pa = &(sc->bge_pa); 632 uint32_t bit, regbase; 633 int i; 634 635 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 636 regbase = BGE_APE_LOCK_GRANT; 637 else 638 regbase = BGE_APE_PER_LOCK_GRANT; 639 640 /* Clear any stale locks. */ 641 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 642 switch (i) { 643 case BGE_APE_LOCK_PHY0: 644 case BGE_APE_LOCK_PHY1: 645 case BGE_APE_LOCK_PHY2: 646 case BGE_APE_LOCK_PHY3: 647 bit = BGE_APE_LOCK_GRANT_DRIVER0; 648 break; 649 default: 650 if (pa->pa_function == 0) 651 bit = BGE_APE_LOCK_GRANT_DRIVER0; 652 else 653 bit = (1 << pa->pa_function); 654 } 655 APE_WRITE_4(sc, regbase + 4 * i, bit); 656 } 657 658 /* Select the PHY lock based on the device's function number. */ 659 switch (pa->pa_function) { 660 case 0: 661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 662 break; 663 case 1: 664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 665 break; 666 case 2: 667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 668 break; 669 case 3: 670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 671 break; 672 default: 673 printf("%s: PHY lock not supported on function\n", 674 device_xname(sc->bge_dev)); 675 break; 676 } 677 } 678 679 /* 680 * Check for APE firmware, set flags, and print version info. 681 */ 682 void 683 bge_ape_read_fw_ver(struct bge_softc *sc) 684 { 685 const char *fwtype; 686 uint32_t apedata, features; 687 688 /* Check for a valid APE signature in shared memory. */ 689 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 690 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 691 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 692 return; 693 } 694 695 /* Check if APE firmware is running. */ 696 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 697 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 698 printf("%s: APE signature found but FW status not ready! " 699 "0x%08x\n", device_xname(sc->bge_dev), apedata); 700 return; 701 } 702 703 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 704 705 /* Fetch the APE firwmare type and version. */ 706 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 707 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 708 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 709 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 710 fwtype = "NCSI"; 711 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 712 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 713 fwtype = "DASH"; 714 } else 715 fwtype = "UNKN"; 716 717 /* Print the APE firmware version. */ 718 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 719 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 720 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 721 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 722 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 723 } 724 725 int 726 bge_ape_lock(struct bge_softc *sc, int locknum) 727 { 728 struct pci_attach_args *pa = &(sc->bge_pa); 729 uint32_t bit, gnt, req, status; 730 int i, off; 731 732 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 733 return (0); 734 735 /* Lock request/grant registers have different bases. */ 736 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 737 req = BGE_APE_LOCK_REQ; 738 gnt = BGE_APE_LOCK_GRANT; 739 } else { 740 req = BGE_APE_PER_LOCK_REQ; 741 gnt = BGE_APE_PER_LOCK_GRANT; 742 } 743 744 off = 4 * locknum; 745 746 switch (locknum) { 747 case BGE_APE_LOCK_GPIO: 748 /* Lock required when using GPIO. */ 749 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 750 return (0); 751 if (pa->pa_function == 0) 752 bit = BGE_APE_LOCK_REQ_DRIVER0; 753 else 754 bit = (1 << pa->pa_function); 755 break; 756 case BGE_APE_LOCK_GRC: 757 /* Lock required to reset the device. */ 758 if (pa->pa_function == 0) 759 bit = BGE_APE_LOCK_REQ_DRIVER0; 760 else 761 bit = (1 << pa->pa_function); 762 break; 763 case BGE_APE_LOCK_MEM: 764 /* Lock required when accessing certain APE memory. */ 765 if (pa->pa_function == 0) 766 bit = BGE_APE_LOCK_REQ_DRIVER0; 767 else 768 bit = (1 << pa->pa_function); 769 break; 770 case BGE_APE_LOCK_PHY0: 771 case BGE_APE_LOCK_PHY1: 772 case BGE_APE_LOCK_PHY2: 773 case BGE_APE_LOCK_PHY3: 774 /* Lock required when accessing PHYs. */ 775 bit = BGE_APE_LOCK_REQ_DRIVER0; 776 break; 777 default: 778 return (EINVAL); 779 } 780 781 /* Request a lock. */ 782 APE_WRITE_4_FLUSH(sc, req + off, bit); 783 784 /* Wait up to 1 second to acquire lock. */ 785 for (i = 0; i < 20000; i++) { 786 status = APE_READ_4(sc, gnt + off); 787 if (status == bit) 788 break; 789 DELAY(50); 790 } 791 792 /* Handle any errors. */ 793 if (status != bit) { 794 printf("%s: APE lock %d request failed! " 795 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 796 device_xname(sc->bge_dev), 797 locknum, req + off, bit & 0xFFFF, gnt + off, 798 status & 0xFFFF); 799 /* Revoke the lock request. */ 800 APE_WRITE_4(sc, gnt + off, bit); 801 return (EBUSY); 802 } 803 804 return (0); 805 } 806 807 void 808 bge_ape_unlock(struct bge_softc *sc, int locknum) 809 { 810 struct pci_attach_args *pa = &(sc->bge_pa); 811 uint32_t bit, gnt; 812 int off; 813 814 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 815 return; 816 817 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 818 gnt = BGE_APE_LOCK_GRANT; 819 else 820 gnt = BGE_APE_PER_LOCK_GRANT; 821 822 off = 4 * locknum; 823 824 switch (locknum) { 825 case BGE_APE_LOCK_GPIO: 826 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 827 return; 828 if (pa->pa_function == 0) 829 bit = BGE_APE_LOCK_GRANT_DRIVER0; 830 else 831 bit = (1 << pa->pa_function); 832 break; 833 case BGE_APE_LOCK_GRC: 834 if (pa->pa_function == 0) 835 bit = BGE_APE_LOCK_GRANT_DRIVER0; 836 else 837 bit = (1 << pa->pa_function); 838 break; 839 case BGE_APE_LOCK_MEM: 840 if (pa->pa_function == 0) 841 bit = BGE_APE_LOCK_GRANT_DRIVER0; 842 else 843 bit = (1 << pa->pa_function); 844 break; 845 case BGE_APE_LOCK_PHY0: 846 case BGE_APE_LOCK_PHY1: 847 case BGE_APE_LOCK_PHY2: 848 case BGE_APE_LOCK_PHY3: 849 bit = BGE_APE_LOCK_GRANT_DRIVER0; 850 break; 851 default: 852 return; 853 } 854 855 /* Write and flush for consecutive bge_ape_lock() */ 856 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 857 } 858 859 /* 860 * Send an event to the APE firmware. 861 */ 862 void 863 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 864 { 865 uint32_t apedata; 866 int i; 867 868 /* NCSI does not support APE events. */ 869 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 870 return; 871 872 /* Wait up to 1ms for APE to service previous event. */ 873 for (i = 10; i > 0; i--) { 874 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 875 break; 876 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 877 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 878 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 879 BGE_APE_EVENT_STATUS_EVENT_PENDING); 880 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 881 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 882 break; 883 } 884 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 885 DELAY(100); 886 } 887 if (i == 0) { 888 printf("%s: APE event 0x%08x send timed out\n", 889 device_xname(sc->bge_dev), event); 890 } 891 } 892 893 void 894 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 895 { 896 uint32_t apedata, event; 897 898 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 899 return; 900 901 switch (kind) { 902 case BGE_RESET_START: 903 /* If this is the first load, clear the load counter. */ 904 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 905 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 906 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 907 else { 908 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 909 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 910 } 911 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 912 BGE_APE_HOST_SEG_SIG_MAGIC); 913 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 914 BGE_APE_HOST_SEG_LEN_MAGIC); 915 916 /* Add some version info if bge(4) supports it. */ 917 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 918 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 919 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 920 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 921 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 922 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 923 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 924 BGE_APE_HOST_DRVR_STATE_START); 925 event = BGE_APE_EVENT_STATUS_STATE_START; 926 break; 927 case BGE_RESET_SHUTDOWN: 928 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 929 BGE_APE_HOST_DRVR_STATE_UNLOAD); 930 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 931 break; 932 case BGE_RESET_SUSPEND: 933 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 934 break; 935 default: 936 return; 937 } 938 939 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 940 BGE_APE_EVENT_STATUS_STATE_CHNGE); 941 } 942 943 static uint8_t 944 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 945 { 946 uint32_t access, byte = 0; 947 int i; 948 949 /* Lock. */ 950 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 951 for (i = 0; i < 8000; i++) { 952 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 953 break; 954 DELAY(20); 955 } 956 if (i == 8000) 957 return 1; 958 959 /* Enable access. */ 960 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 961 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 962 963 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 964 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 965 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 966 DELAY(10); 967 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 968 DELAY(10); 969 break; 970 } 971 } 972 973 if (i == BGE_TIMEOUT * 10) { 974 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 975 return 1; 976 } 977 978 /* Get result. */ 979 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 980 981 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 982 983 /* Disable access. */ 984 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 985 986 /* Unlock. */ 987 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 988 989 return 0; 990 } 991 992 /* 993 * Read a sequence of bytes from NVRAM. 994 */ 995 static int 996 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 997 { 998 int error = 0, i; 999 uint8_t byte = 0; 1000 1001 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1002 return 1; 1003 1004 for (i = 0; i < cnt; i++) { 1005 error = bge_nvram_getbyte(sc, off + i, &byte); 1006 if (error) 1007 break; 1008 *(dest + i) = byte; 1009 } 1010 1011 return (error ? 1 : 0); 1012 } 1013 1014 /* 1015 * Read a byte of data stored in the EEPROM at address 'addr.' The 1016 * BCM570x supports both the traditional bitbang interface and an 1017 * auto access interface for reading the EEPROM. We use the auto 1018 * access method. 1019 */ 1020 static uint8_t 1021 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1022 { 1023 int i; 1024 uint32_t byte = 0; 1025 1026 /* 1027 * Enable use of auto EEPROM access so we can avoid 1028 * having to use the bitbang method. 1029 */ 1030 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1031 1032 /* Reset the EEPROM, load the clock period. */ 1033 CSR_WRITE_4(sc, BGE_EE_ADDR, 1034 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1035 DELAY(20); 1036 1037 /* Issue the read EEPROM command. */ 1038 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1039 1040 /* Wait for completion */ 1041 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1042 DELAY(10); 1043 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1044 break; 1045 } 1046 1047 if (i == BGE_TIMEOUT * 10) { 1048 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1049 return 1; 1050 } 1051 1052 /* Get result. */ 1053 byte = CSR_READ_4(sc, BGE_EE_DATA); 1054 1055 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1056 1057 return 0; 1058 } 1059 1060 /* 1061 * Read a sequence of bytes from the EEPROM. 1062 */ 1063 static int 1064 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1065 { 1066 int error = 0, i; 1067 uint8_t byte = 0; 1068 char *dest = destv; 1069 1070 for (i = 0; i < cnt; i++) { 1071 error = bge_eeprom_getbyte(sc, off + i, &byte); 1072 if (error) 1073 break; 1074 *(dest + i) = byte; 1075 } 1076 1077 return (error ? 1 : 0); 1078 } 1079 1080 static int 1081 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1082 { 1083 struct bge_softc *sc = device_private(dev); 1084 uint32_t data; 1085 uint32_t autopoll; 1086 int rv = 0; 1087 int i; 1088 1089 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1090 return -1; 1091 1092 /* Reading with autopolling on may trigger PCI errors */ 1093 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1094 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1095 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1096 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1097 DELAY(80); 1098 } 1099 1100 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1101 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1102 1103 for (i = 0; i < BGE_TIMEOUT; i++) { 1104 delay(10); 1105 data = CSR_READ_4(sc, BGE_MI_COMM); 1106 if (!(data & BGE_MICOMM_BUSY)) { 1107 DELAY(5); 1108 data = CSR_READ_4(sc, BGE_MI_COMM); 1109 break; 1110 } 1111 } 1112 1113 if (i == BGE_TIMEOUT) { 1114 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1115 rv = ETIMEDOUT; 1116 } else if ((data & BGE_MICOMM_READFAIL) != 0) 1117 rv = -1; 1118 else 1119 *val = data & BGE_MICOMM_DATA; 1120 1121 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1122 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1123 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1124 DELAY(80); 1125 } 1126 1127 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1128 1129 return rv; 1130 } 1131 1132 static int 1133 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1134 { 1135 struct bge_softc *sc = device_private(dev); 1136 uint32_t autopoll; 1137 int i; 1138 1139 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1140 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1141 return 0; 1142 1143 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1144 return -1; 1145 1146 /* Reading with autopolling on may trigger PCI errors */ 1147 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1148 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1149 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1150 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1151 DELAY(80); 1152 } 1153 1154 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1155 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1156 1157 for (i = 0; i < BGE_TIMEOUT; i++) { 1158 delay(10); 1159 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1160 delay(5); 1161 CSR_READ_4(sc, BGE_MI_COMM); 1162 break; 1163 } 1164 } 1165 1166 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1167 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1168 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1169 delay(80); 1170 } 1171 1172 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1173 1174 if (i == BGE_TIMEOUT) { 1175 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1176 return ETIMEDOUT; 1177 } 1178 1179 return 0; 1180 } 1181 1182 static void 1183 bge_miibus_statchg(struct ifnet *ifp) 1184 { 1185 struct bge_softc *sc = ifp->if_softc; 1186 struct mii_data *mii = &sc->bge_mii; 1187 uint32_t mac_mode, rx_mode, tx_mode; 1188 1189 /* 1190 * Get flow control negotiation result. 1191 */ 1192 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1193 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1194 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1195 1196 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1197 mii->mii_media_status & IFM_ACTIVE && 1198 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1199 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1200 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1201 (!(mii->mii_media_status & IFM_ACTIVE) || 1202 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1203 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1204 1205 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1206 return; 1207 1208 /* Set the port mode (MII/GMII) to match the link speed. */ 1209 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1210 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1211 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1212 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1213 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1214 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1215 mac_mode |= BGE_PORTMODE_GMII; 1216 else 1217 mac_mode |= BGE_PORTMODE_MII; 1218 1219 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1220 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1221 if ((mii->mii_media_active & IFM_FDX) != 0) { 1222 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1223 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1224 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1225 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1226 } else 1227 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1228 1229 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1230 DELAY(40); 1231 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1232 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1233 } 1234 1235 /* 1236 * Update rx threshold levels to values in a particular slot 1237 * of the interrupt-mitigation table bge_rx_threshes. 1238 */ 1239 static void 1240 bge_set_thresh(struct ifnet *ifp, int lvl) 1241 { 1242 struct bge_softc *sc = ifp->if_softc; 1243 int s; 1244 1245 /* For now, just save the new Rx-intr thresholds and record 1246 * that a threshold update is pending. Updating the hardware 1247 * registers here (even at splhigh()) is observed to 1248 * occasionaly cause glitches where Rx-interrupts are not 1249 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1250 */ 1251 s = splnet(); 1252 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1253 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1254 sc->bge_pending_rxintr_change = 1; 1255 splx(s); 1256 } 1257 1258 1259 /* 1260 * Update Rx thresholds of all bge devices 1261 */ 1262 static void 1263 bge_update_all_threshes(int lvl) 1264 { 1265 struct ifnet *ifp; 1266 const char * const namebuf = "bge"; 1267 int namelen; 1268 int s; 1269 1270 if (lvl < 0) 1271 lvl = 0; 1272 else if (lvl >= NBGE_RX_THRESH) 1273 lvl = NBGE_RX_THRESH - 1; 1274 1275 namelen = strlen(namebuf); 1276 /* 1277 * Now search all the interfaces for this name/number 1278 */ 1279 s = pserialize_read_enter(); 1280 IFNET_READER_FOREACH(ifp) { 1281 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1282 continue; 1283 /* We got a match: update if doing auto-threshold-tuning */ 1284 if (bge_auto_thresh) 1285 bge_set_thresh(ifp, lvl); 1286 } 1287 pserialize_read_exit(s); 1288 } 1289 1290 /* 1291 * Handle events that have triggered interrupts. 1292 */ 1293 static void 1294 bge_handle_events(struct bge_softc *sc) 1295 { 1296 1297 return; 1298 } 1299 1300 /* 1301 * Memory management for jumbo frames. 1302 */ 1303 1304 static int 1305 bge_alloc_jumbo_mem(struct bge_softc *sc) 1306 { 1307 char *ptr, *kva; 1308 bus_dma_segment_t seg; 1309 int i, rseg, state, error; 1310 struct bge_jpool_entry *entry; 1311 1312 state = error = 0; 1313 1314 /* Grab a big chunk o' storage. */ 1315 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1316 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1317 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1318 return ENOBUFS; 1319 } 1320 1321 state = 1; 1322 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1323 BUS_DMA_NOWAIT)) { 1324 aprint_error_dev(sc->bge_dev, 1325 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1326 error = ENOBUFS; 1327 goto out; 1328 } 1329 1330 state = 2; 1331 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1332 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1333 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1334 error = ENOBUFS; 1335 goto out; 1336 } 1337 1338 state = 3; 1339 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1340 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1341 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1342 error = ENOBUFS; 1343 goto out; 1344 } 1345 1346 state = 4; 1347 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1348 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1349 1350 SLIST_INIT(&sc->bge_jfree_listhead); 1351 SLIST_INIT(&sc->bge_jinuse_listhead); 1352 1353 /* 1354 * Now divide it up into 9K pieces and save the addresses 1355 * in an array. 1356 */ 1357 ptr = sc->bge_cdata.bge_jumbo_buf; 1358 for (i = 0; i < BGE_JSLOTS; i++) { 1359 sc->bge_cdata.bge_jslots[i] = ptr; 1360 ptr += BGE_JLEN; 1361 entry = malloc(sizeof(struct bge_jpool_entry), 1362 M_DEVBUF, M_WAITOK); 1363 entry->slot = i; 1364 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1365 entry, jpool_entries); 1366 } 1367 out: 1368 if (error != 0) { 1369 switch (state) { 1370 case 4: 1371 bus_dmamap_unload(sc->bge_dmatag, 1372 sc->bge_cdata.bge_rx_jumbo_map); 1373 /* FALLTHROUGH */ 1374 case 3: 1375 bus_dmamap_destroy(sc->bge_dmatag, 1376 sc->bge_cdata.bge_rx_jumbo_map); 1377 /* FALLTHROUGH */ 1378 case 2: 1379 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1380 /* FALLTHROUGH */ 1381 case 1: 1382 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1383 break; 1384 default: 1385 break; 1386 } 1387 } 1388 1389 return error; 1390 } 1391 1392 /* 1393 * Allocate a jumbo buffer. 1394 */ 1395 static void * 1396 bge_jalloc(struct bge_softc *sc) 1397 { 1398 struct bge_jpool_entry *entry; 1399 1400 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1401 1402 if (entry == NULL) { 1403 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1404 return NULL; 1405 } 1406 1407 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1408 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1409 return (sc->bge_cdata.bge_jslots[entry->slot]); 1410 } 1411 1412 /* 1413 * Release a jumbo buffer. 1414 */ 1415 static void 1416 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1417 { 1418 struct bge_jpool_entry *entry; 1419 struct bge_softc *sc; 1420 int i, s; 1421 1422 /* Extract the softc struct pointer. */ 1423 sc = (struct bge_softc *)arg; 1424 1425 if (sc == NULL) 1426 panic("bge_jfree: can't find softc pointer!"); 1427 1428 /* calculate the slot this buffer belongs to */ 1429 1430 i = ((char *)buf 1431 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1432 1433 if ((i < 0) || (i >= BGE_JSLOTS)) 1434 panic("bge_jfree: asked to free buffer that we don't manage!"); 1435 1436 s = splvm(); 1437 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1438 if (entry == NULL) 1439 panic("bge_jfree: buffer not in use!"); 1440 entry->slot = i; 1441 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1442 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1443 1444 if (__predict_true(m != NULL)) 1445 pool_cache_put(mb_cache, m); 1446 splx(s); 1447 } 1448 1449 1450 /* 1451 * Initialize a standard receive ring descriptor. 1452 */ 1453 static int 1454 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1455 bus_dmamap_t dmamap) 1456 { 1457 struct mbuf *m_new = NULL; 1458 struct bge_rx_bd *r; 1459 int error; 1460 1461 if (dmamap == NULL) 1462 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1463 1464 if (dmamap == NULL) { 1465 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1466 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1467 if (error != 0) 1468 return error; 1469 } 1470 1471 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1472 1473 if (m == NULL) { 1474 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1475 if (m_new == NULL) 1476 return ENOBUFS; 1477 1478 MCLGET(m_new, M_DONTWAIT); 1479 if (!(m_new->m_flags & M_EXT)) { 1480 m_freem(m_new); 1481 return ENOBUFS; 1482 } 1483 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1484 1485 } else { 1486 m_new = m; 1487 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1488 m_new->m_data = m_new->m_ext.ext_buf; 1489 } 1490 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1491 m_adj(m_new, ETHER_ALIGN); 1492 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1493 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1494 m_freem(m_new); 1495 return ENOBUFS; 1496 } 1497 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1498 BUS_DMASYNC_PREREAD); 1499 1500 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1501 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1502 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1503 r->bge_flags = BGE_RXBDFLAG_END; 1504 r->bge_len = m_new->m_len; 1505 r->bge_idx = i; 1506 1507 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1508 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1509 i * sizeof (struct bge_rx_bd), 1510 sizeof (struct bge_rx_bd), 1511 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1512 1513 return 0; 1514 } 1515 1516 /* 1517 * Initialize a jumbo receive ring descriptor. This allocates 1518 * a jumbo buffer from the pool managed internally by the driver. 1519 */ 1520 static int 1521 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1522 { 1523 struct mbuf *m_new = NULL; 1524 struct bge_rx_bd *r; 1525 void *buf = NULL; 1526 1527 if (m == NULL) { 1528 1529 /* Allocate the mbuf. */ 1530 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1531 if (m_new == NULL) 1532 return ENOBUFS; 1533 1534 /* Allocate the jumbo buffer */ 1535 buf = bge_jalloc(sc); 1536 if (buf == NULL) { 1537 m_freem(m_new); 1538 aprint_error_dev(sc->bge_dev, 1539 "jumbo allocation failed -- packet dropped!\n"); 1540 return ENOBUFS; 1541 } 1542 1543 /* Attach the buffer to the mbuf. */ 1544 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1545 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1546 bge_jfree, sc); 1547 m_new->m_flags |= M_EXT_RW; 1548 } else { 1549 m_new = m; 1550 buf = m_new->m_data = m_new->m_ext.ext_buf; 1551 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1552 } 1553 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1554 m_adj(m_new, ETHER_ALIGN); 1555 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1556 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1557 BGE_JLEN, BUS_DMASYNC_PREREAD); 1558 /* Set up the descriptor. */ 1559 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1560 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1561 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1562 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1563 r->bge_len = m_new->m_len; 1564 r->bge_idx = i; 1565 1566 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1567 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1568 i * sizeof (struct bge_rx_bd), 1569 sizeof (struct bge_rx_bd), 1570 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1571 1572 return 0; 1573 } 1574 1575 /* 1576 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1577 * that's 1MB or memory, which is a lot. For now, we fill only the first 1578 * 256 ring entries and hope that our CPU is fast enough to keep up with 1579 * the NIC. 1580 */ 1581 static int 1582 bge_init_rx_ring_std(struct bge_softc *sc) 1583 { 1584 int i; 1585 1586 if (sc->bge_flags & BGEF_RXRING_VALID) 1587 return 0; 1588 1589 for (i = 0; i < BGE_SSLOTS; i++) { 1590 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1591 return ENOBUFS; 1592 } 1593 1594 sc->bge_std = i - 1; 1595 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1596 1597 sc->bge_flags |= BGEF_RXRING_VALID; 1598 1599 return 0; 1600 } 1601 1602 static void 1603 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1604 { 1605 int i; 1606 1607 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1608 return; 1609 1610 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1611 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1612 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1613 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1614 if (disable) { 1615 bus_dmamap_destroy(sc->bge_dmatag, 1616 sc->bge_cdata.bge_rx_std_map[i]); 1617 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1618 } 1619 } 1620 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1621 sizeof(struct bge_rx_bd)); 1622 } 1623 1624 sc->bge_flags &= ~BGEF_RXRING_VALID; 1625 } 1626 1627 static int 1628 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1629 { 1630 int i; 1631 volatile struct bge_rcb *rcb; 1632 1633 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1634 return 0; 1635 1636 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1637 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1638 return ENOBUFS; 1639 } 1640 1641 sc->bge_jumbo = i - 1; 1642 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1643 1644 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1645 rcb->bge_maxlen_flags = 0; 1646 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1647 1648 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1649 1650 return 0; 1651 } 1652 1653 static void 1654 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1655 { 1656 int i; 1657 1658 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1659 return; 1660 1661 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1662 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1663 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1664 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1665 } 1666 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1667 sizeof(struct bge_rx_bd)); 1668 } 1669 1670 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1671 } 1672 1673 static void 1674 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1675 { 1676 int i; 1677 struct txdmamap_pool_entry *dma; 1678 1679 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1680 return; 1681 1682 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1683 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1684 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1685 sc->bge_cdata.bge_tx_chain[i] = NULL; 1686 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1687 link); 1688 sc->txdma[i] = 0; 1689 } 1690 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1691 sizeof(struct bge_tx_bd)); 1692 } 1693 1694 if (disable) { 1695 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1696 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1697 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1698 if (sc->bge_dma64) { 1699 bus_dmamap_destroy(sc->bge_dmatag32, 1700 dma->dmamap32); 1701 } 1702 free(dma, M_DEVBUF); 1703 } 1704 SLIST_INIT(&sc->txdma_list); 1705 } 1706 1707 sc->bge_flags &= ~BGEF_TXRING_VALID; 1708 } 1709 1710 static int 1711 bge_init_tx_ring(struct bge_softc *sc) 1712 { 1713 struct ifnet *ifp = &sc->ethercom.ec_if; 1714 int i; 1715 bus_dmamap_t dmamap, dmamap32; 1716 bus_size_t maxsegsz; 1717 struct txdmamap_pool_entry *dma; 1718 1719 if (sc->bge_flags & BGEF_TXRING_VALID) 1720 return 0; 1721 1722 sc->bge_txcnt = 0; 1723 sc->bge_tx_saved_considx = 0; 1724 1725 /* Initialize transmit producer index for host-memory send ring. */ 1726 sc->bge_tx_prodidx = 0; 1727 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1728 /* 5700 b2 errata */ 1729 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1730 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1731 1732 /* NIC-memory send ring not used; initialize to zero. */ 1733 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1734 /* 5700 b2 errata */ 1735 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1736 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1737 1738 /* Limit DMA segment size for some chips */ 1739 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1740 (ifp->if_mtu <= ETHERMTU)) 1741 maxsegsz = 2048; 1742 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1743 maxsegsz = 4096; 1744 else 1745 maxsegsz = ETHER_MAX_LEN_JUMBO; 1746 1747 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1748 goto alloc_done; 1749 1750 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1751 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1752 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1753 &dmamap)) 1754 return ENOBUFS; 1755 if (dmamap == NULL) 1756 panic("dmamap NULL in bge_init_tx_ring"); 1757 if (sc->bge_dma64) { 1758 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1759 BGE_NTXSEG, maxsegsz, 0, 1760 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1761 &dmamap32)) { 1762 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1763 return ENOBUFS; 1764 } 1765 if (dmamap32 == NULL) 1766 panic("dmamap32 NULL in bge_init_tx_ring"); 1767 } else 1768 dmamap32 = dmamap; 1769 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1770 if (dma == NULL) { 1771 aprint_error_dev(sc->bge_dev, 1772 "can't alloc txdmamap_pool_entry\n"); 1773 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1774 if (sc->bge_dma64) 1775 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1776 return ENOMEM; 1777 } 1778 dma->dmamap = dmamap; 1779 dma->dmamap32 = dmamap32; 1780 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1781 } 1782 alloc_done: 1783 sc->bge_flags |= BGEF_TXRING_VALID; 1784 1785 return 0; 1786 } 1787 1788 static void 1789 bge_setmulti(struct bge_softc *sc) 1790 { 1791 struct ethercom *ec = &sc->ethercom; 1792 struct ifnet *ifp = &ec->ec_if; 1793 struct ether_multi *enm; 1794 struct ether_multistep step; 1795 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1796 uint32_t h; 1797 int i; 1798 1799 if (ifp->if_flags & IFF_PROMISC) 1800 goto allmulti; 1801 1802 /* Now program new ones. */ 1803 ETHER_LOCK(ec); 1804 ETHER_FIRST_MULTI(step, ec, enm); 1805 while (enm != NULL) { 1806 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1807 /* 1808 * We must listen to a range of multicast addresses. 1809 * For now, just accept all multicasts, rather than 1810 * trying to set only those filter bits needed to match 1811 * the range. (At this time, the only use of address 1812 * ranges is for IP multicast routing, for which the 1813 * range is big enough to require all bits set.) 1814 */ 1815 ETHER_UNLOCK(ec); 1816 goto allmulti; 1817 } 1818 1819 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1820 1821 /* Just want the 7 least-significant bits. */ 1822 h &= 0x7f; 1823 1824 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1825 ETHER_NEXT_MULTI(step, enm); 1826 } 1827 ETHER_UNLOCK(ec); 1828 1829 ifp->if_flags &= ~IFF_ALLMULTI; 1830 goto setit; 1831 1832 allmulti: 1833 ifp->if_flags |= IFF_ALLMULTI; 1834 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1835 1836 setit: 1837 for (i = 0; i < 4; i++) 1838 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1839 } 1840 1841 static void 1842 bge_sig_pre_reset(struct bge_softc *sc, int type) 1843 { 1844 1845 /* 1846 * Some chips don't like this so only do this if ASF is enabled 1847 */ 1848 if (sc->bge_asf_mode) 1849 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1850 1851 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1852 switch (type) { 1853 case BGE_RESET_START: 1854 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1855 BGE_FW_DRV_STATE_START); 1856 break; 1857 case BGE_RESET_SHUTDOWN: 1858 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1859 BGE_FW_DRV_STATE_UNLOAD); 1860 break; 1861 case BGE_RESET_SUSPEND: 1862 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1863 BGE_FW_DRV_STATE_SUSPEND); 1864 break; 1865 } 1866 } 1867 1868 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1869 bge_ape_driver_state_change(sc, type); 1870 } 1871 1872 static void 1873 bge_sig_post_reset(struct bge_softc *sc, int type) 1874 { 1875 1876 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1877 switch (type) { 1878 case BGE_RESET_START: 1879 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1880 BGE_FW_DRV_STATE_START_DONE); 1881 /* START DONE */ 1882 break; 1883 case BGE_RESET_SHUTDOWN: 1884 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1885 BGE_FW_DRV_STATE_UNLOAD_DONE); 1886 break; 1887 } 1888 } 1889 1890 if (type == BGE_RESET_SHUTDOWN) 1891 bge_ape_driver_state_change(sc, type); 1892 } 1893 1894 static void 1895 bge_sig_legacy(struct bge_softc *sc, int type) 1896 { 1897 1898 if (sc->bge_asf_mode) { 1899 switch (type) { 1900 case BGE_RESET_START: 1901 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1902 BGE_FW_DRV_STATE_START); 1903 break; 1904 case BGE_RESET_SHUTDOWN: 1905 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1906 BGE_FW_DRV_STATE_UNLOAD); 1907 break; 1908 } 1909 } 1910 } 1911 1912 static void 1913 bge_wait_for_event_ack(struct bge_softc *sc) 1914 { 1915 int i; 1916 1917 /* wait up to 2500usec */ 1918 for (i = 0; i < 250; i++) { 1919 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1920 BGE_RX_CPU_DRV_EVENT)) 1921 break; 1922 DELAY(10); 1923 } 1924 } 1925 1926 static void 1927 bge_stop_fw(struct bge_softc *sc) 1928 { 1929 1930 if (sc->bge_asf_mode) { 1931 bge_wait_for_event_ack(sc); 1932 1933 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1934 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1935 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1936 1937 bge_wait_for_event_ack(sc); 1938 } 1939 } 1940 1941 static int 1942 bge_poll_fw(struct bge_softc *sc) 1943 { 1944 uint32_t val; 1945 int i; 1946 1947 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1948 for (i = 0; i < BGE_TIMEOUT; i++) { 1949 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1950 if (val & BGE_VCPU_STATUS_INIT_DONE) 1951 break; 1952 DELAY(100); 1953 } 1954 if (i >= BGE_TIMEOUT) { 1955 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1956 return -1; 1957 } 1958 } else { 1959 /* 1960 * Poll the value location we just wrote until 1961 * we see the 1's complement of the magic number. 1962 * This indicates that the firmware initialization 1963 * is complete. 1964 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1965 */ 1966 for (i = 0; i < BGE_TIMEOUT; i++) { 1967 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1968 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1969 break; 1970 DELAY(10); 1971 } 1972 1973 if ((i >= BGE_TIMEOUT) 1974 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1975 aprint_error_dev(sc->bge_dev, 1976 "firmware handshake timed out, val = %x\n", val); 1977 return -1; 1978 } 1979 } 1980 1981 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1982 /* tg3 says we have to wait extra time */ 1983 delay(10 * 1000); 1984 } 1985 1986 return 0; 1987 } 1988 1989 int 1990 bge_phy_addr(struct bge_softc *sc) 1991 { 1992 struct pci_attach_args *pa = &(sc->bge_pa); 1993 int phy_addr = 1; 1994 1995 /* 1996 * PHY address mapping for various devices. 1997 * 1998 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 1999 * ---------+-------+-------+-------+-------+ 2000 * BCM57XX | 1 | X | X | X | 2001 * BCM5704 | 1 | X | 1 | X | 2002 * BCM5717 | 1 | 8 | 2 | 9 | 2003 * BCM5719 | 1 | 8 | 2 | 9 | 2004 * BCM5720 | 1 | 8 | 2 | 9 | 2005 * 2006 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2007 * ---------+-------+-------+-------+-------+ 2008 * BCM57XX | X | X | X | X | 2009 * BCM5704 | X | X | X | X | 2010 * BCM5717 | X | X | X | X | 2011 * BCM5719 | 3 | 10 | 4 | 11 | 2012 * BCM5720 | X | X | X | X | 2013 * 2014 * Other addresses may respond but they are not 2015 * IEEE compliant PHYs and should be ignored. 2016 */ 2017 switch (BGE_ASICREV(sc->bge_chipid)) { 2018 case BGE_ASICREV_BCM5717: 2019 case BGE_ASICREV_BCM5719: 2020 case BGE_ASICREV_BCM5720: 2021 phy_addr = pa->pa_function; 2022 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2023 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2024 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2025 } else { 2026 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2027 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2028 } 2029 } 2030 2031 return phy_addr; 2032 } 2033 2034 /* 2035 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2036 * self-test results. 2037 */ 2038 static int 2039 bge_chipinit(struct bge_softc *sc) 2040 { 2041 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2042 int i; 2043 2044 /* Set endianness before we access any non-PCI registers. */ 2045 misc_ctl = BGE_INIT; 2046 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2047 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2048 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2049 misc_ctl); 2050 2051 /* 2052 * Clear the MAC statistics block in the NIC's 2053 * internal memory. 2054 */ 2055 for (i = BGE_STATS_BLOCK; 2056 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2057 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2058 2059 for (i = BGE_STATUS_BLOCK; 2060 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2061 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2062 2063 /* 5717 workaround from tg3 */ 2064 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2065 /* Save */ 2066 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2067 2068 /* Temporary modify MODE_CTL to control TLP */ 2069 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2070 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2071 2072 /* Control TLP */ 2073 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2074 BGE_TLP_PHYCTL1); 2075 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2076 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2077 2078 /* Restore */ 2079 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2080 } 2081 2082 if (BGE_IS_57765_FAMILY(sc)) { 2083 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2084 /* Save */ 2085 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2086 2087 /* Temporary modify MODE_CTL to control TLP */ 2088 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2089 CSR_WRITE_4(sc, BGE_MODE_CTL, 2090 reg | BGE_MODECTL_PCIE_TLPADDR1); 2091 2092 /* Control TLP */ 2093 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2094 BGE_TLP_PHYCTL5); 2095 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2096 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2097 2098 /* Restore */ 2099 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2100 } 2101 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2102 /* 2103 * For the 57766 and non Ax versions of 57765, bootcode 2104 * needs to setup the PCIE Fast Training Sequence (FTS) 2105 * value to prevent transmit hangs. 2106 */ 2107 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2108 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2109 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2110 2111 /* Save */ 2112 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2113 2114 /* Temporary modify MODE_CTL to control TLP */ 2115 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2116 CSR_WRITE_4(sc, BGE_MODE_CTL, 2117 reg | BGE_MODECTL_PCIE_TLPADDR0); 2118 2119 /* Control TLP */ 2120 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2121 BGE_TLP_FTSMAX); 2122 reg &= ~BGE_TLP_FTSMAX_MSK; 2123 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2124 reg | BGE_TLP_FTSMAX_VAL); 2125 2126 /* Restore */ 2127 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2128 } 2129 2130 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2131 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2132 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2133 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2134 } 2135 2136 /* Set up the PCI DMA control register. */ 2137 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2138 if (sc->bge_flags & BGEF_PCIE) { 2139 /* Read watermark not used, 128 bytes for write. */ 2140 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2141 device_xname(sc->bge_dev))); 2142 if (sc->bge_mps >= 256) 2143 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2144 else 2145 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2146 } else if (sc->bge_flags & BGEF_PCIX) { 2147 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2148 device_xname(sc->bge_dev))); 2149 /* PCI-X bus */ 2150 if (BGE_IS_5714_FAMILY(sc)) { 2151 /* 256 bytes for read and write. */ 2152 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2153 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2154 2155 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2156 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2157 else 2158 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2159 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2160 /* 2161 * In the BCM5703, the DMA read watermark should 2162 * be set to less than or equal to the maximum 2163 * memory read byte count of the PCI-X command 2164 * register. 2165 */ 2166 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2167 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2168 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2169 /* 1536 bytes for read, 384 bytes for write. */ 2170 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2171 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2172 } else { 2173 /* 384 bytes for read and write. */ 2174 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2175 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2176 (0x0F); 2177 } 2178 2179 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2180 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2181 uint32_t tmp; 2182 2183 /* Set ONEDMA_ATONCE for hardware workaround. */ 2184 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2185 if (tmp == 6 || tmp == 7) 2186 dma_rw_ctl |= 2187 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2188 2189 /* Set PCI-X DMA write workaround. */ 2190 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2191 } 2192 } else { 2193 /* Conventional PCI bus: 256 bytes for read and write. */ 2194 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2195 device_xname(sc->bge_dev))); 2196 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2197 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2198 2199 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2200 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2201 dma_rw_ctl |= 0x0F; 2202 } 2203 2204 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2205 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2206 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2207 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2208 2209 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2210 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2211 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2212 2213 if (BGE_IS_57765_PLUS(sc)) { 2214 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2215 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2216 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2217 2218 /* 2219 * Enable HW workaround for controllers that misinterpret 2220 * a status tag update and leave interrupts permanently 2221 * disabled. 2222 */ 2223 if (!BGE_IS_57765_FAMILY(sc) && 2224 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2225 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2226 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2227 } 2228 2229 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2230 dma_rw_ctl); 2231 2232 /* 2233 * Set up general mode register. 2234 */ 2235 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2236 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2237 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2238 /* Retain Host-2-BMC settings written by APE firmware. */ 2239 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2240 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2241 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2242 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2243 } 2244 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2245 BGE_MODECTL_TX_NO_PHDR_CSUM; 2246 2247 /* 2248 * BCM5701 B5 have a bug causing data corruption when using 2249 * 64-bit DMA reads, which can be terminated early and then 2250 * completed later as 32-bit accesses, in combination with 2251 * certain bridges. 2252 */ 2253 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2254 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2255 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2256 2257 /* 2258 * Tell the firmware the driver is running 2259 */ 2260 if (sc->bge_asf_mode & ASF_STACKUP) 2261 mode_ctl |= BGE_MODECTL_STACKUP; 2262 2263 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2264 2265 /* 2266 * Disable memory write invalidate. Apparently it is not supported 2267 * properly by these devices. 2268 */ 2269 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2270 PCI_COMMAND_INVALIDATE_ENABLE); 2271 2272 #ifdef __brokenalpha__ 2273 /* 2274 * Must insure that we do not cross an 8K (bytes) boundary 2275 * for DMA reads. Our highest limit is 1K bytes. This is a 2276 * restriction on some ALPHA platforms with early revision 2277 * 21174 PCI chipsets, such as the AlphaPC 164lx 2278 */ 2279 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2280 #endif 2281 2282 /* Set the timer prescaler (always 66MHz) */ 2283 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2284 2285 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2286 DELAY(40); /* XXX */ 2287 2288 /* Put PHY into ready state */ 2289 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2290 DELAY(40); 2291 } 2292 2293 return 0; 2294 } 2295 2296 static int 2297 bge_blockinit(struct bge_softc *sc) 2298 { 2299 volatile struct bge_rcb *rcb; 2300 bus_size_t rcb_addr; 2301 struct ifnet *ifp = &sc->ethercom.ec_if; 2302 bge_hostaddr taddr; 2303 uint32_t dmactl, rdmareg, mimode, val; 2304 int i, limit; 2305 2306 /* 2307 * Initialize the memory window pointer register so that 2308 * we can access the first 32K of internal NIC RAM. This will 2309 * allow us to set up the TX send ring RCBs and the RX return 2310 * ring RCBs, plus other things which live in NIC memory. 2311 */ 2312 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2313 2314 if (!BGE_IS_5705_PLUS(sc)) { 2315 /* 57XX step 33 */ 2316 /* Configure mbuf memory pool */ 2317 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2318 2319 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2321 else 2322 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2323 2324 /* 57XX step 34 */ 2325 /* Configure DMA resource pool */ 2326 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2327 BGE_DMA_DESCRIPTORS); 2328 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2329 } 2330 2331 /* 5718 step 11, 57XX step 35 */ 2332 /* 2333 * Configure mbuf pool watermarks. New broadcom docs strongly 2334 * recommend these. 2335 */ 2336 if (BGE_IS_5717_PLUS(sc)) { 2337 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2338 if (ifp->if_mtu > ETHERMTU) { 2339 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2340 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2341 } else { 2342 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2344 } 2345 } else if (BGE_IS_5705_PLUS(sc)) { 2346 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2347 2348 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2351 } else { 2352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2354 } 2355 } else { 2356 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2357 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2358 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2359 } 2360 2361 /* 57XX step 36 */ 2362 /* Configure DMA resource watermarks */ 2363 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2364 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2365 2366 /* 5718 step 13, 57XX step 38 */ 2367 /* Enable buffer manager */ 2368 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2369 /* 2370 * Change the arbitration algorithm of TXMBUF read request to 2371 * round-robin instead of priority based for BCM5719. When 2372 * TXFIFO is almost empty, RDMA will hold its request until 2373 * TXFIFO is not almost empty. 2374 */ 2375 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2376 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2377 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2378 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2379 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2380 val |= BGE_BMANMODE_LOMBUF_ATTN; 2381 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2382 2383 /* 57XX step 39 */ 2384 /* Poll for buffer manager start indication */ 2385 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2386 DELAY(10); 2387 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2388 break; 2389 } 2390 2391 if (i == BGE_TIMEOUT * 2) { 2392 aprint_error_dev(sc->bge_dev, 2393 "buffer manager failed to start\n"); 2394 return ENXIO; 2395 } 2396 2397 /* 57XX step 40 */ 2398 /* Enable flow-through queues */ 2399 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2400 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2401 2402 /* Wait until queue initialization is complete */ 2403 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2404 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2405 break; 2406 DELAY(10); 2407 } 2408 2409 if (i == BGE_TIMEOUT * 2) { 2410 aprint_error_dev(sc->bge_dev, 2411 "flow-through queue init failed\n"); 2412 return ENXIO; 2413 } 2414 2415 /* 2416 * Summary of rings supported by the controller: 2417 * 2418 * Standard Receive Producer Ring 2419 * - This ring is used to feed receive buffers for "standard" 2420 * sized frames (typically 1536 bytes) to the controller. 2421 * 2422 * Jumbo Receive Producer Ring 2423 * - This ring is used to feed receive buffers for jumbo sized 2424 * frames (i.e. anything bigger than the "standard" frames) 2425 * to the controller. 2426 * 2427 * Mini Receive Producer Ring 2428 * - This ring is used to feed receive buffers for "mini" 2429 * sized frames to the controller. 2430 * - This feature required external memory for the controller 2431 * but was never used in a production system. Should always 2432 * be disabled. 2433 * 2434 * Receive Return Ring 2435 * - After the controller has placed an incoming frame into a 2436 * receive buffer that buffer is moved into a receive return 2437 * ring. The driver is then responsible to passing the 2438 * buffer up to the stack. Many versions of the controller 2439 * support multiple RR rings. 2440 * 2441 * Send Ring 2442 * - This ring is used for outgoing frames. Many versions of 2443 * the controller support multiple send rings. 2444 */ 2445 2446 /* 5718 step 15, 57XX step 41 */ 2447 /* Initialize the standard RX ring control block */ 2448 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2449 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2450 /* 5718 step 16 */ 2451 if (BGE_IS_57765_PLUS(sc)) { 2452 /* 2453 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2454 * Bits 15-2 : Maximum RX frame size 2455 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2456 * Bit 0 : Reserved 2457 */ 2458 rcb->bge_maxlen_flags = 2459 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2460 } else if (BGE_IS_5705_PLUS(sc)) { 2461 /* 2462 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2463 * Bits 15-2 : Reserved (should be 0) 2464 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2465 * Bit 0 : Reserved 2466 */ 2467 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2468 } else { 2469 /* 2470 * Ring size is always XXX entries 2471 * Bits 31-16: Maximum RX frame size 2472 * Bits 15-2 : Reserved (should be 0) 2473 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2474 * Bit 0 : Reserved 2475 */ 2476 rcb->bge_maxlen_flags = 2477 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2478 } 2479 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2480 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2481 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2482 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2483 else 2484 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2485 /* Write the standard receive producer ring control block. */ 2486 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2487 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2488 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2489 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2490 2491 /* Reset the standard receive producer ring producer index. */ 2492 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2493 2494 /* 57XX step 42 */ 2495 /* 2496 * Initialize the jumbo RX ring control block 2497 * We set the 'ring disabled' bit in the flags 2498 * field until we're actually ready to start 2499 * using this ring (i.e. once we set the MTU 2500 * high enough to require it). 2501 */ 2502 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2503 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2504 BGE_HOSTADDR(rcb->bge_hostaddr, 2505 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2506 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2507 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2508 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2509 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2510 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2511 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2512 else 2513 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2514 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2515 rcb->bge_hostaddr.bge_addr_hi); 2516 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2517 rcb->bge_hostaddr.bge_addr_lo); 2518 /* Program the jumbo receive producer ring RCB parameters. */ 2519 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2520 rcb->bge_maxlen_flags); 2521 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2522 /* Reset the jumbo receive producer ring producer index. */ 2523 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2524 } 2525 2526 /* 57XX step 43 */ 2527 /* Disable the mini receive producer ring RCB. */ 2528 if (BGE_IS_5700_FAMILY(sc)) { 2529 /* Set up dummy disabled mini ring RCB */ 2530 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2531 rcb->bge_maxlen_flags = 2532 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2533 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2534 rcb->bge_maxlen_flags); 2535 /* Reset the mini receive producer ring producer index. */ 2536 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2537 2538 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2539 offsetof(struct bge_ring_data, bge_info), 2540 sizeof (struct bge_gib), 2541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2542 } 2543 2544 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2546 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2547 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2548 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2549 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2550 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2551 } 2552 /* 5718 step 14, 57XX step 44 */ 2553 /* 2554 * The BD ring replenish thresholds control how often the 2555 * hardware fetches new BD's from the producer rings in host 2556 * memory. Setting the value too low on a busy system can 2557 * starve the hardware and recue the throughpout. 2558 * 2559 * Set the BD ring replenish thresholds. The recommended 2560 * values are 1/8th the number of descriptors allocated to 2561 * each ring, but since we try to avoid filling the entire 2562 * ring we set these to the minimal value of 8. This needs to 2563 * be done on several of the supported chip revisions anyway, 2564 * to work around HW bugs. 2565 */ 2566 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2567 if (BGE_IS_JUMBO_CAPABLE(sc)) 2568 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2569 2570 /* 5718 step 18 */ 2571 if (BGE_IS_5717_PLUS(sc)) { 2572 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2573 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2574 } 2575 2576 /* 57XX step 45 */ 2577 /* 2578 * Disable all send rings by setting the 'ring disabled' bit 2579 * in the flags field of all the TX send ring control blocks, 2580 * located in NIC memory. 2581 */ 2582 if (BGE_IS_5700_FAMILY(sc)) { 2583 /* 5700 to 5704 had 16 send rings. */ 2584 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2585 } else if (BGE_IS_5717_PLUS(sc)) { 2586 limit = BGE_TX_RINGS_5717_MAX; 2587 } else if (BGE_IS_57765_FAMILY(sc) || 2588 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2589 limit = BGE_TX_RINGS_57765_MAX; 2590 } else 2591 limit = 1; 2592 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2593 for (i = 0; i < limit; i++) { 2594 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2595 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2596 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2597 rcb_addr += sizeof(struct bge_rcb); 2598 } 2599 2600 /* 57XX step 46 and 47 */ 2601 /* Configure send ring RCB 0 (we use only the first ring) */ 2602 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2603 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2604 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2605 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2606 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2607 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2608 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2609 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2610 else 2611 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2612 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2613 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2614 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2615 2616 /* 57XX step 48 */ 2617 /* 2618 * Disable all receive return rings by setting the 2619 * 'ring diabled' bit in the flags field of all the receive 2620 * return ring control blocks, located in NIC memory. 2621 */ 2622 if (BGE_IS_5717_PLUS(sc)) { 2623 /* Should be 17, use 16 until we get an SRAM map. */ 2624 limit = 16; 2625 } else if (BGE_IS_5700_FAMILY(sc)) 2626 limit = BGE_RX_RINGS_MAX; 2627 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2628 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2629 BGE_IS_57765_FAMILY(sc)) 2630 limit = 4; 2631 else 2632 limit = 1; 2633 /* Disable all receive return rings */ 2634 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2635 for (i = 0; i < limit; i++) { 2636 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2637 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2638 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2639 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2640 BGE_RCB_FLAG_RING_DISABLED)); 2641 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2642 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2643 (i * (sizeof(uint64_t))), 0); 2644 rcb_addr += sizeof(struct bge_rcb); 2645 } 2646 2647 /* 57XX step 49 */ 2648 /* 2649 * Set up receive return ring 0. Note that the NIC address 2650 * for RX return rings is 0x0. The return rings live entirely 2651 * within the host, so the nicaddr field in the RCB isn't used. 2652 */ 2653 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2654 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2655 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2656 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2657 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2658 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2659 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2660 2661 /* 5718 step 24, 57XX step 53 */ 2662 /* Set random backoff seed for TX */ 2663 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2664 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2665 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2666 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2667 BGE_TX_BACKOFF_SEED_MASK); 2668 2669 /* 5718 step 26, 57XX step 55 */ 2670 /* Set inter-packet gap */ 2671 val = 0x2620; 2672 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2674 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2675 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2676 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2677 2678 /* 5718 step 27, 57XX step 56 */ 2679 /* 2680 * Specify which ring to use for packets that don't match 2681 * any RX rules. 2682 */ 2683 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2684 2685 /* 5718 step 28, 57XX step 57 */ 2686 /* 2687 * Configure number of RX lists. One interrupt distribution 2688 * list, sixteen active lists, one bad frames class. 2689 */ 2690 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2691 2692 /* 5718 step 29, 57XX step 58 */ 2693 /* Inialize RX list placement stats mask. */ 2694 if (BGE_IS_575X_PLUS(sc)) { 2695 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2696 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2697 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2698 } else 2699 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2700 2701 /* 5718 step 30, 57XX step 59 */ 2702 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2703 2704 /* 5718 step 33, 57XX step 62 */ 2705 /* Disable host coalescing until we get it set up */ 2706 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2707 2708 /* 5718 step 34, 57XX step 63 */ 2709 /* Poll to make sure it's shut down. */ 2710 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2711 DELAY(10); 2712 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2713 break; 2714 } 2715 2716 if (i == BGE_TIMEOUT * 2) { 2717 aprint_error_dev(sc->bge_dev, 2718 "host coalescing engine failed to idle\n"); 2719 return ENXIO; 2720 } 2721 2722 /* 5718 step 35, 36, 37 */ 2723 /* Set up host coalescing defaults */ 2724 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2725 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2726 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2727 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2728 if (!(BGE_IS_5705_PLUS(sc))) { 2729 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2730 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2731 } 2732 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2733 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2734 2735 /* Set up address of statistics block */ 2736 if (BGE_IS_5700_FAMILY(sc)) { 2737 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2738 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2739 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2740 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2741 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2742 } 2743 2744 /* 5718 step 38 */ 2745 /* Set up address of status block */ 2746 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2747 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2748 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2749 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2750 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2751 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2752 2753 /* Set up status block size. */ 2754 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2755 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2756 val = BGE_STATBLKSZ_FULL; 2757 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2758 } else { 2759 val = BGE_STATBLKSZ_32BYTE; 2760 bzero(&sc->bge_rdata->bge_status_block, 32); 2761 } 2762 2763 /* 5718 step 39, 57XX step 73 */ 2764 /* Turn on host coalescing state machine */ 2765 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2766 2767 /* 5718 step 40, 57XX step 74 */ 2768 /* Turn on RX BD completion state machine and enable attentions */ 2769 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2770 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2771 2772 /* 5718 step 41, 57XX step 75 */ 2773 /* Turn on RX list placement state machine */ 2774 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2775 2776 /* 57XX step 76 */ 2777 /* Turn on RX list selector state machine. */ 2778 if (!(BGE_IS_5705_PLUS(sc))) 2779 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2780 2781 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2782 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2783 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2784 BGE_MACMODE_FRMHDR_DMA_ENB; 2785 2786 if (sc->bge_flags & BGEF_FIBER_TBI) 2787 val |= BGE_PORTMODE_TBI; 2788 else if (sc->bge_flags & BGEF_FIBER_MII) 2789 val |= BGE_PORTMODE_GMII; 2790 else 2791 val |= BGE_PORTMODE_MII; 2792 2793 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2794 /* Allow APE to send/receive frames. */ 2795 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2796 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2797 2798 /* Turn on DMA, clear stats */ 2799 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2800 /* 5718 step 44 */ 2801 DELAY(40); 2802 2803 /* 5718 step 45, 57XX step 79 */ 2804 /* Set misc. local control, enable interrupts on attentions */ 2805 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2806 if (BGE_IS_5717_PLUS(sc)) { 2807 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2808 /* 5718 step 46 */ 2809 DELAY(100); 2810 } 2811 2812 /* 57XX step 81 */ 2813 /* Turn on DMA completion state machine */ 2814 if (!(BGE_IS_5705_PLUS(sc))) 2815 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2816 2817 /* 5718 step 47, 57XX step 82 */ 2818 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2819 2820 /* 5718 step 48 */ 2821 /* Enable host coalescing bug fix. */ 2822 if (BGE_IS_5755_PLUS(sc)) 2823 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2824 2825 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2826 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2827 2828 /* Turn on write DMA state machine */ 2829 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2830 /* 5718 step 49 */ 2831 DELAY(40); 2832 2833 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2834 2835 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2836 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2837 2838 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2839 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2840 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2841 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2842 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2843 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2844 2845 if (sc->bge_flags & BGEF_PCIE) 2846 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2847 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2848 if (ifp->if_mtu <= ETHERMTU) 2849 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2850 } 2851 if (sc->bge_flags & BGEF_TSO) { 2852 val |= BGE_RDMAMODE_TSO4_ENABLE; 2853 if (BGE_IS_5717_PLUS(sc)) 2854 val |= BGE_RDMAMODE_TSO6_ENABLE; 2855 } 2856 2857 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2858 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2859 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2860 BGE_RDMAMODE_H2BNC_VLAN_DET; 2861 /* 2862 * Allow multiple outstanding read requests from 2863 * non-LSO read DMA engine. 2864 */ 2865 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2866 } 2867 2868 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2869 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2870 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2871 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2872 BGE_IS_57765_PLUS(sc)) { 2873 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2874 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2875 else 2876 rdmareg = BGE_RDMA_RSRVCTRL; 2877 dmactl = CSR_READ_4(sc, rdmareg); 2878 /* 2879 * Adjust tx margin to prevent TX data corruption and 2880 * fix internal FIFO overflow. 2881 */ 2882 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2883 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2884 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2885 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2886 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2887 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2888 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2889 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2890 } 2891 /* 2892 * Enable fix for read DMA FIFO overruns. 2893 * The fix is to limit the number of RX BDs 2894 * the hardware would fetch at a fime. 2895 */ 2896 CSR_WRITE_4(sc, rdmareg, dmactl | 2897 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2898 } 2899 2900 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2901 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2902 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2903 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2904 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2905 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2906 /* 2907 * Allow 4KB burst length reads for non-LSO frames. 2908 * Enable 512B burst length reads for buffer descriptors. 2909 */ 2910 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2911 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2912 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2913 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2914 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2915 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2916 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2917 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2918 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2919 } 2920 /* Turn on read DMA state machine */ 2921 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2922 /* 5718 step 52 */ 2923 delay(40); 2924 2925 if (sc->bge_flags & BGEF_RDMA_BUG) { 2926 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2927 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2928 if ((val & 0xFFFF) > BGE_FRAMELEN) 2929 break; 2930 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2931 break; 2932 } 2933 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2934 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2935 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2936 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2937 else 2938 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2939 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2940 } 2941 } 2942 2943 /* 5718 step 56, 57XX step 84 */ 2944 /* Turn on RX data completion state machine */ 2945 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2946 2947 /* Turn on RX data and RX BD initiator state machine */ 2948 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2949 2950 /* 57XX step 85 */ 2951 /* Turn on Mbuf cluster free state machine */ 2952 if (!BGE_IS_5705_PLUS(sc)) 2953 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2954 2955 /* 5718 step 57, 57XX step 86 */ 2956 /* Turn on send data completion state machine */ 2957 val = BGE_SDCMODE_ENABLE; 2958 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2959 val |= BGE_SDCMODE_CDELAY; 2960 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2961 2962 /* 5718 step 58 */ 2963 /* Turn on send BD completion state machine */ 2964 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2965 2966 /* 57XX step 88 */ 2967 /* Turn on RX BD initiator state machine */ 2968 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2969 2970 /* 5718 step 60, 57XX step 90 */ 2971 /* Turn on send data initiator state machine */ 2972 if (sc->bge_flags & BGEF_TSO) { 2973 /* XXX: magic value from Linux driver */ 2974 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2975 BGE_SDIMODE_HW_LSO_PRE_DMA); 2976 } else 2977 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2978 2979 /* 5718 step 61, 57XX step 91 */ 2980 /* Turn on send BD initiator state machine */ 2981 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2982 2983 /* 5718 step 62, 57XX step 92 */ 2984 /* Turn on send BD selector state machine */ 2985 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2986 2987 /* 5718 step 31, 57XX step 60 */ 2988 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2989 /* 5718 step 32, 57XX step 61 */ 2990 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2991 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2992 2993 /* ack/clear link change events */ 2994 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2995 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2996 BGE_MACSTAT_LINK_CHANGED); 2997 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2998 2999 /* 3000 * Enable attention when the link has changed state for 3001 * devices that use auto polling. 3002 */ 3003 if (sc->bge_flags & BGEF_FIBER_TBI) { 3004 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3005 } else { 3006 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3007 mimode = BGE_MIMODE_500KHZ_CONST; 3008 else 3009 mimode = BGE_MIMODE_BASE; 3010 /* 5718 step 68. 5718 step 69 (optionally). */ 3011 if (BGE_IS_5700_FAMILY(sc) || 3012 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3013 mimode |= BGE_MIMODE_AUTOPOLL; 3014 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3015 } 3016 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3017 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3018 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3019 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3020 BGE_EVTENB_MI_INTERRUPT); 3021 } 3022 3023 /* 3024 * Clear any pending link state attention. 3025 * Otherwise some link state change events may be lost until attention 3026 * is cleared by bge_intr() -> bge_link_upd() sequence. 3027 * It's not necessary on newer BCM chips - perhaps enabling link 3028 * state change attentions implies clearing pending attention. 3029 */ 3030 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3031 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3032 BGE_MACSTAT_LINK_CHANGED); 3033 3034 /* Enable link state change attentions. */ 3035 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3036 3037 return 0; 3038 } 3039 3040 static const struct bge_revision * 3041 bge_lookup_rev(uint32_t chipid) 3042 { 3043 const struct bge_revision *br; 3044 3045 for (br = bge_revisions; br->br_name != NULL; br++) { 3046 if (br->br_chipid == chipid) 3047 return br; 3048 } 3049 3050 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3051 if (br->br_chipid == BGE_ASICREV(chipid)) 3052 return br; 3053 } 3054 3055 return NULL; 3056 } 3057 3058 static const struct bge_product * 3059 bge_lookup(const struct pci_attach_args *pa) 3060 { 3061 const struct bge_product *bp; 3062 3063 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3064 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3065 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3066 return bp; 3067 } 3068 3069 return NULL; 3070 } 3071 3072 static uint32_t 3073 bge_chipid(const struct pci_attach_args *pa) 3074 { 3075 uint32_t id; 3076 3077 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3078 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3079 3080 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3081 switch (PCI_PRODUCT(pa->pa_id)) { 3082 case PCI_PRODUCT_BROADCOM_BCM5717: 3083 case PCI_PRODUCT_BROADCOM_BCM5718: 3084 case PCI_PRODUCT_BROADCOM_BCM5719: 3085 case PCI_PRODUCT_BROADCOM_BCM5720: 3086 case PCI_PRODUCT_BROADCOM_BCM5725: 3087 case PCI_PRODUCT_BROADCOM_BCM5727: 3088 case PCI_PRODUCT_BROADCOM_BCM5762: 3089 case PCI_PRODUCT_BROADCOM_BCM57764: 3090 case PCI_PRODUCT_BROADCOM_BCM57767: 3091 case PCI_PRODUCT_BROADCOM_BCM57787: 3092 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3093 BGE_PCI_GEN2_PRODID_ASICREV); 3094 break; 3095 case PCI_PRODUCT_BROADCOM_BCM57761: 3096 case PCI_PRODUCT_BROADCOM_BCM57762: 3097 case PCI_PRODUCT_BROADCOM_BCM57765: 3098 case PCI_PRODUCT_BROADCOM_BCM57766: 3099 case PCI_PRODUCT_BROADCOM_BCM57781: 3100 case PCI_PRODUCT_BROADCOM_BCM57782: 3101 case PCI_PRODUCT_BROADCOM_BCM57785: 3102 case PCI_PRODUCT_BROADCOM_BCM57786: 3103 case PCI_PRODUCT_BROADCOM_BCM57791: 3104 case PCI_PRODUCT_BROADCOM_BCM57795: 3105 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3106 BGE_PCI_GEN15_PRODID_ASICREV); 3107 break; 3108 default: 3109 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3110 BGE_PCI_PRODID_ASICREV); 3111 break; 3112 } 3113 } 3114 3115 return id; 3116 } 3117 3118 /* 3119 * Return true if MSI can be used with this device. 3120 */ 3121 static int 3122 bge_can_use_msi(struct bge_softc *sc) 3123 { 3124 int can_use_msi = 0; 3125 3126 switch (BGE_ASICREV(sc->bge_chipid)) { 3127 case BGE_ASICREV_BCM5714_A0: 3128 case BGE_ASICREV_BCM5714: 3129 /* 3130 * Apparently, MSI doesn't work when these chips are 3131 * configured in single-port mode. 3132 */ 3133 break; 3134 case BGE_ASICREV_BCM5750: 3135 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3136 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3137 can_use_msi = 1; 3138 break; 3139 default: 3140 if (BGE_IS_575X_PLUS(sc)) 3141 can_use_msi = 1; 3142 } 3143 return (can_use_msi); 3144 } 3145 3146 /* 3147 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3148 * against our list and return its name if we find a match. Note 3149 * that since the Broadcom controller contains VPD support, we 3150 * can get the device name string from the controller itself instead 3151 * of the compiled-in string. This is a little slow, but it guarantees 3152 * we'll always announce the right product name. 3153 */ 3154 static int 3155 bge_probe(device_t parent, cfdata_t match, void *aux) 3156 { 3157 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3158 3159 if (bge_lookup(pa) != NULL) 3160 return 1; 3161 3162 return 0; 3163 } 3164 3165 static void 3166 bge_attach(device_t parent, device_t self, void *aux) 3167 { 3168 struct bge_softc *sc = device_private(self); 3169 struct pci_attach_args *pa = aux; 3170 prop_dictionary_t dict; 3171 const struct bge_product *bp; 3172 const struct bge_revision *br; 3173 pci_chipset_tag_t pc; 3174 const char *intrstr = NULL; 3175 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3176 uint32_t command; 3177 struct ifnet *ifp; 3178 struct mii_data * const mii = &sc->bge_mii; 3179 uint32_t misccfg, mimode; 3180 void * kva; 3181 u_char eaddr[ETHER_ADDR_LEN]; 3182 pcireg_t memtype, subid, reg; 3183 bus_addr_t memaddr; 3184 uint32_t pm_ctl; 3185 bool no_seeprom; 3186 int capmask; 3187 int mii_flags; 3188 int map_flags; 3189 char intrbuf[PCI_INTRSTR_LEN]; 3190 3191 bp = bge_lookup(pa); 3192 KASSERT(bp != NULL); 3193 3194 sc->sc_pc = pa->pa_pc; 3195 sc->sc_pcitag = pa->pa_tag; 3196 sc->bge_dev = self; 3197 3198 sc->bge_pa = *pa; 3199 pc = sc->sc_pc; 3200 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3201 3202 aprint_naive(": Ethernet controller\n"); 3203 aprint_normal(": %s Ethernet\n", bp->bp_name); 3204 3205 /* 3206 * Map control/status registers. 3207 */ 3208 DPRINTFN(5, ("Map control/status regs\n")); 3209 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3210 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3211 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3212 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3213 3214 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3215 aprint_error_dev(sc->bge_dev, 3216 "failed to enable memory mapping!\n"); 3217 return; 3218 } 3219 3220 DPRINTFN(5, ("pci_mem_find\n")); 3221 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3222 switch (memtype) { 3223 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3224 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3225 #if 0 3226 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3227 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3228 &memaddr, &sc->bge_bsize) == 0) 3229 break; 3230 #else 3231 /* 3232 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3233 * system get NMI on boot (PR#48451). This problem might not be 3234 * the driver's bug but our PCI common part's bug. Until we 3235 * find a real reason, we ignore the prefetchable bit. 3236 */ 3237 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3238 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3239 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3240 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3241 map_flags, &sc->bge_bhandle) == 0) { 3242 sc->bge_btag = pa->pa_memt; 3243 break; 3244 } 3245 } 3246 #endif 3247 /* FALLTHROUGH */ 3248 default: 3249 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3250 return; 3251 } 3252 3253 /* Save various chip information. */ 3254 sc->bge_chipid = bge_chipid(pa); 3255 sc->bge_phy_addr = bge_phy_addr(sc); 3256 3257 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3258 &sc->bge_pciecap, NULL) != 0) { 3259 /* PCIe */ 3260 sc->bge_flags |= BGEF_PCIE; 3261 /* Extract supported maximum payload size. */ 3262 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3263 sc->bge_pciecap + PCIE_DCAP); 3264 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3265 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3266 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3267 sc->bge_expmrq = 2048; 3268 else 3269 sc->bge_expmrq = 4096; 3270 bge_set_max_readrq(sc); 3271 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3272 /* PCIe without PCIe cap */ 3273 sc->bge_flags |= BGEF_PCIE; 3274 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3275 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3276 /* PCI-X */ 3277 sc->bge_flags |= BGEF_PCIX; 3278 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3279 &sc->bge_pcixcap, NULL) == 0) 3280 aprint_error_dev(sc->bge_dev, 3281 "unable to find PCIX capability\n"); 3282 } 3283 3284 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3285 /* 3286 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3287 * can clobber the chip's PCI config-space power control 3288 * registers, leaving the card in D3 powersave state. We do 3289 * not have memory-mapped registers in this state, so force 3290 * device into D0 state before starting initialization. 3291 */ 3292 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3293 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3294 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3295 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3296 DELAY(1000); /* 27 usec is allegedly sufficent */ 3297 } 3298 3299 /* Save chipset family. */ 3300 switch (BGE_ASICREV(sc->bge_chipid)) { 3301 case BGE_ASICREV_BCM5717: 3302 case BGE_ASICREV_BCM5719: 3303 case BGE_ASICREV_BCM5720: 3304 sc->bge_flags |= BGEF_5717_PLUS; 3305 /* FALLTHROUGH */ 3306 case BGE_ASICREV_BCM5762: 3307 case BGE_ASICREV_BCM57765: 3308 case BGE_ASICREV_BCM57766: 3309 if (!BGE_IS_5717_PLUS(sc)) 3310 sc->bge_flags |= BGEF_57765_FAMILY; 3311 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3312 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3313 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3314 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3315 /* 3316 * Enable work around for DMA engine miscalculation 3317 * of TXMBUF available space. 3318 */ 3319 sc->bge_flags |= BGEF_RDMA_BUG; 3320 3321 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3322 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3323 /* Jumbo frame on BCM5719 A0 does not work. */ 3324 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3325 } 3326 } 3327 break; 3328 case BGE_ASICREV_BCM5755: 3329 case BGE_ASICREV_BCM5761: 3330 case BGE_ASICREV_BCM5784: 3331 case BGE_ASICREV_BCM5785: 3332 case BGE_ASICREV_BCM5787: 3333 case BGE_ASICREV_BCM57780: 3334 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3335 break; 3336 case BGE_ASICREV_BCM5700: 3337 case BGE_ASICREV_BCM5701: 3338 case BGE_ASICREV_BCM5703: 3339 case BGE_ASICREV_BCM5704: 3340 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3341 break; 3342 case BGE_ASICREV_BCM5714_A0: 3343 case BGE_ASICREV_BCM5780: 3344 case BGE_ASICREV_BCM5714: 3345 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3346 /* FALLTHROUGH */ 3347 case BGE_ASICREV_BCM5750: 3348 case BGE_ASICREV_BCM5752: 3349 case BGE_ASICREV_BCM5906: 3350 sc->bge_flags |= BGEF_575X_PLUS; 3351 /* FALLTHROUGH */ 3352 case BGE_ASICREV_BCM5705: 3353 sc->bge_flags |= BGEF_5705_PLUS; 3354 break; 3355 } 3356 3357 /* Identify chips with APE processor. */ 3358 switch (BGE_ASICREV(sc->bge_chipid)) { 3359 case BGE_ASICREV_BCM5717: 3360 case BGE_ASICREV_BCM5719: 3361 case BGE_ASICREV_BCM5720: 3362 case BGE_ASICREV_BCM5761: 3363 case BGE_ASICREV_BCM5762: 3364 sc->bge_flags |= BGEF_APE; 3365 break; 3366 } 3367 3368 /* 3369 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3370 * not actually a MAC controller bug but an issue with the embedded 3371 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3372 */ 3373 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3374 sc->bge_flags |= BGEF_40BIT_BUG; 3375 3376 /* Chips with APE need BAR2 access for APE registers/memory. */ 3377 if ((sc->bge_flags & BGEF_APE) != 0) { 3378 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3379 #if 0 3380 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3381 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3382 &sc->bge_apesize)) { 3383 aprint_error_dev(sc->bge_dev, 3384 "couldn't map BAR2 memory\n"); 3385 return; 3386 } 3387 #else 3388 /* 3389 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3390 * system get NMI on boot (PR#48451). This problem might not be 3391 * the driver's bug but our PCI common part's bug. Until we 3392 * find a real reason, we ignore the prefetchable bit. 3393 */ 3394 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3395 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3396 aprint_error_dev(sc->bge_dev, 3397 "couldn't map BAR2 memory\n"); 3398 return; 3399 } 3400 3401 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3402 if (bus_space_map(pa->pa_memt, memaddr, 3403 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3404 aprint_error_dev(sc->bge_dev, 3405 "couldn't map BAR2 memory\n"); 3406 return; 3407 } 3408 sc->bge_apetag = pa->pa_memt; 3409 #endif 3410 3411 /* Enable APE register/memory access by host driver. */ 3412 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3413 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3414 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3415 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3416 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3417 3418 bge_ape_lock_init(sc); 3419 bge_ape_read_fw_ver(sc); 3420 } 3421 3422 /* Identify the chips that use an CPMU. */ 3423 if (BGE_IS_5717_PLUS(sc) || 3424 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3425 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3426 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3427 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3428 sc->bge_flags |= BGEF_CPMU_PRESENT; 3429 3430 /* Set MI_MODE */ 3431 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3432 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3433 mimode |= BGE_MIMODE_500KHZ_CONST; 3434 else 3435 mimode |= BGE_MIMODE_BASE; 3436 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3437 3438 /* 3439 * When using the BCM5701 in PCI-X mode, data corruption has 3440 * been observed in the first few bytes of some received packets. 3441 * Aligning the packet buffer in memory eliminates the corruption. 3442 * Unfortunately, this misaligns the packet payloads. On platforms 3443 * which do not support unaligned accesses, we will realign the 3444 * payloads by copying the received packets. 3445 */ 3446 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3447 sc->bge_flags & BGEF_PCIX) 3448 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3449 3450 if (BGE_IS_5700_FAMILY(sc)) 3451 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3452 3453 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3454 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3455 3456 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3457 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3458 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3459 sc->bge_flags |= BGEF_IS_5788; 3460 3461 /* 3462 * Some controllers seem to require a special firmware to use 3463 * TSO. But the firmware is not available to FreeBSD and Linux 3464 * claims that the TSO performed by the firmware is slower than 3465 * hardware based TSO. Moreover the firmware based TSO has one 3466 * known bug which can't handle TSO if ethernet header + IP/TCP 3467 * header is greater than 80 bytes. The workaround for the TSO 3468 * bug exist but it seems it's too expensive than not using 3469 * TSO at all. Some hardwares also have the TSO bug so limit 3470 * the TSO to the controllers that are not affected TSO issues 3471 * (e.g. 5755 or higher). 3472 */ 3473 if (BGE_IS_5755_PLUS(sc)) { 3474 /* 3475 * BCM5754 and BCM5787 shares the same ASIC id so 3476 * explicit device id check is required. 3477 */ 3478 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3479 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3480 sc->bge_flags |= BGEF_TSO; 3481 /* TSO on BCM5719 A0 does not work. */ 3482 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3483 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3484 sc->bge_flags &= ~BGEF_TSO; 3485 } 3486 3487 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3488 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3489 (misccfg == 0x4000 || misccfg == 0x8000)) || 3490 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3491 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3492 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3493 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3494 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3495 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3496 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3497 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3498 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3499 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3500 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3501 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3503 /* These chips are 10/100 only. */ 3504 capmask &= ~BMSR_EXTSTAT; 3505 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3506 } 3507 3508 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3509 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3510 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3511 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3512 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3513 3514 /* Set various PHY bug flags. */ 3515 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3516 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3517 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3518 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3519 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3520 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3521 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3522 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3523 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3524 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3525 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3526 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3527 if (BGE_IS_5705_PLUS(sc) && 3528 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3529 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3530 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3531 !BGE_IS_57765_PLUS(sc)) { 3532 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3533 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3534 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3535 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3536 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3537 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3538 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3539 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3540 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3541 } else 3542 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3543 } 3544 3545 /* 3546 * SEEPROM check. 3547 * First check if firmware knows we do not have SEEPROM. 3548 */ 3549 if (prop_dictionary_get_bool(device_properties(self), 3550 "without-seeprom", &no_seeprom) && no_seeprom) 3551 sc->bge_flags |= BGEF_NO_EEPROM; 3552 3553 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3554 sc->bge_flags |= BGEF_NO_EEPROM; 3555 3556 /* Now check the 'ROM failed' bit on the RX CPU */ 3557 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3558 sc->bge_flags |= BGEF_NO_EEPROM; 3559 3560 sc->bge_asf_mode = 0; 3561 /* No ASF if APE present. */ 3562 if ((sc->bge_flags & BGEF_APE) == 0) { 3563 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3564 BGE_SRAM_DATA_SIG_MAGIC)) { 3565 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3566 BGE_HWCFG_ASF) { 3567 sc->bge_asf_mode |= ASF_ENABLE; 3568 sc->bge_asf_mode |= ASF_STACKUP; 3569 if (BGE_IS_575X_PLUS(sc)) 3570 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3571 } 3572 } 3573 } 3574 3575 int counts[PCI_INTR_TYPE_SIZE] = { 3576 [PCI_INTR_TYPE_INTX] = 1, 3577 [PCI_INTR_TYPE_MSI] = 1, 3578 [PCI_INTR_TYPE_MSIX] = 1, 3579 }; 3580 int max_type = PCI_INTR_TYPE_MSIX; 3581 3582 if (!bge_can_use_msi(sc)) { 3583 /* MSI broken, allow only INTx */ 3584 max_type = PCI_INTR_TYPE_INTX; 3585 } 3586 3587 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3588 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3589 return; 3590 } 3591 3592 DPRINTFN(5, ("pci_intr_string\n")); 3593 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3594 sizeof(intrbuf)); 3595 DPRINTFN(5, ("pci_intr_establish\n")); 3596 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3597 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3598 if (sc->bge_intrhand == NULL) { 3599 pci_intr_release(pc, sc->bge_pihp, 1); 3600 sc->bge_pihp = NULL; 3601 3602 aprint_error_dev(self, "couldn't establish interrupt"); 3603 if (intrstr != NULL) 3604 aprint_error(" at %s", intrstr); 3605 aprint_error("\n"); 3606 return; 3607 } 3608 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3609 3610 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3611 case PCI_INTR_TYPE_MSIX: 3612 case PCI_INTR_TYPE_MSI: 3613 KASSERT(bge_can_use_msi(sc)); 3614 sc->bge_flags |= BGEF_MSI; 3615 break; 3616 default: 3617 /* nothing to do */ 3618 break; 3619 } 3620 3621 /* 3622 * All controllers except BCM5700 supports tagged status but 3623 * we use tagged status only for MSI case on BCM5717. Otherwise 3624 * MSI on BCM5717 does not work. 3625 */ 3626 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3627 sc->bge_flags |= BGEF_TAGGED_STATUS; 3628 3629 /* 3630 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3631 * lock in bge_reset(). 3632 */ 3633 CSR_WRITE_4(sc, BGE_EE_ADDR, 3634 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3635 delay(1000); 3636 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3637 3638 bge_stop_fw(sc); 3639 bge_sig_pre_reset(sc, BGE_RESET_START); 3640 if (bge_reset(sc)) 3641 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3642 3643 /* 3644 * Read the hardware config word in the first 32k of NIC internal 3645 * memory, or fall back to the config word in the EEPROM. 3646 * Note: on some BCM5700 cards, this value appears to be unset. 3647 */ 3648 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3649 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3650 BGE_SRAM_DATA_SIG_MAGIC) { 3651 uint32_t tmp; 3652 3653 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3654 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3655 BGE_SRAM_DATA_VER_SHIFT; 3656 if ((0 < tmp) && (tmp < 0x100)) 3657 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3658 if (sc->bge_flags & BGEF_PCIE) 3659 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3660 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3661 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3662 if (BGE_IS_5717_PLUS(sc)) 3663 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3664 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3665 bge_read_eeprom(sc, (void *)&hwcfg, 3666 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3667 hwcfg = be32toh(hwcfg); 3668 } 3669 aprint_normal_dev(sc->bge_dev, 3670 "HW config %08x, %08x, %08x, %08x %08x\n", 3671 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3672 3673 bge_sig_legacy(sc, BGE_RESET_START); 3674 bge_sig_post_reset(sc, BGE_RESET_START); 3675 3676 if (bge_chipinit(sc)) { 3677 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3678 bge_release_resources(sc); 3679 return; 3680 } 3681 3682 /* 3683 * Get station address from the EEPROM. 3684 */ 3685 if (bge_get_eaddr(sc, eaddr)) { 3686 aprint_error_dev(sc->bge_dev, 3687 "failed to read station address\n"); 3688 bge_release_resources(sc); 3689 return; 3690 } 3691 3692 br = bge_lookup_rev(sc->bge_chipid); 3693 3694 if (br == NULL) { 3695 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3696 sc->bge_chipid); 3697 } else { 3698 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3699 br->br_name, sc->bge_chipid); 3700 } 3701 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3702 3703 /* Allocate the general information block and ring buffers. */ 3704 if (pci_dma64_available(pa)) { 3705 sc->bge_dmatag = pa->pa_dmat64; 3706 sc->bge_dmatag32 = pa->pa_dmat; 3707 sc->bge_dma64 = true; 3708 } else { 3709 sc->bge_dmatag = pa->pa_dmat; 3710 sc->bge_dmatag32 = pa->pa_dmat; 3711 sc->bge_dma64 = false; 3712 } 3713 3714 /* 40bit DMA workaround */ 3715 if (sizeof(bus_addr_t) > 4) { 3716 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3717 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3718 3719 if (bus_dmatag_subregion(olddmatag, 0, 3720 (bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), 3721 BUS_DMA_NOWAIT) != 0) { 3722 aprint_error_dev(self, 3723 "WARNING: failed to restrict dma range," 3724 " falling back to parent bus dma range\n"); 3725 sc->bge_dmatag = olddmatag; 3726 } 3727 } 3728 } 3729 SLIST_INIT(&sc->txdma_list); 3730 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3731 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3732 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3733 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3734 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3735 return; 3736 } 3737 DPRINTFN(5, ("bus_dmamem_map\n")); 3738 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3739 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3740 BUS_DMA_NOWAIT)) { 3741 aprint_error_dev(sc->bge_dev, 3742 "can't map DMA buffers (%zu bytes)\n", 3743 sizeof(struct bge_ring_data)); 3744 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3745 sc->bge_ring_rseg); 3746 return; 3747 } 3748 DPRINTFN(5, ("bus_dmamem_create\n")); 3749 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3750 sizeof(struct bge_ring_data), 0, 3751 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3752 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3753 bus_dmamem_unmap(sc->bge_dmatag, kva, 3754 sizeof(struct bge_ring_data)); 3755 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3756 sc->bge_ring_rseg); 3757 return; 3758 } 3759 DPRINTFN(5, ("bus_dmamem_load\n")); 3760 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3761 sizeof(struct bge_ring_data), NULL, 3762 BUS_DMA_NOWAIT)) { 3763 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3764 bus_dmamem_unmap(sc->bge_dmatag, kva, 3765 sizeof(struct bge_ring_data)); 3766 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3767 sc->bge_ring_rseg); 3768 return; 3769 } 3770 3771 DPRINTFN(5, ("bzero\n")); 3772 sc->bge_rdata = (struct bge_ring_data *)kva; 3773 3774 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3775 3776 /* Try to allocate memory for jumbo buffers. */ 3777 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3778 if (bge_alloc_jumbo_mem(sc)) { 3779 aprint_error_dev(sc->bge_dev, 3780 "jumbo buffer allocation failed\n"); 3781 } else 3782 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3783 } 3784 3785 /* Set default tuneable values. */ 3786 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3787 sc->bge_rx_coal_ticks = 150; 3788 sc->bge_rx_max_coal_bds = 64; 3789 sc->bge_tx_coal_ticks = 300; 3790 sc->bge_tx_max_coal_bds = 400; 3791 if (BGE_IS_5705_PLUS(sc)) { 3792 sc->bge_tx_coal_ticks = (12 * 5); 3793 sc->bge_tx_max_coal_bds = (12 * 5); 3794 aprint_verbose_dev(sc->bge_dev, 3795 "setting short Tx thresholds\n"); 3796 } 3797 3798 if (BGE_IS_5717_PLUS(sc)) 3799 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3800 else if (BGE_IS_5705_PLUS(sc)) 3801 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3802 else 3803 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3804 3805 /* Set up ifnet structure */ 3806 ifp = &sc->ethercom.ec_if; 3807 ifp->if_softc = sc; 3808 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3809 ifp->if_ioctl = bge_ioctl; 3810 ifp->if_stop = bge_stop; 3811 ifp->if_start = bge_start; 3812 ifp->if_init = bge_init; 3813 ifp->if_watchdog = bge_watchdog; 3814 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3815 IFQ_SET_READY(&ifp->if_snd); 3816 DPRINTFN(5, ("strcpy if_xname\n")); 3817 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3818 3819 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3820 sc->ethercom.ec_if.if_capabilities |= 3821 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3822 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3823 sc->ethercom.ec_if.if_capabilities |= 3824 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3825 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3826 #endif 3827 sc->ethercom.ec_capabilities |= 3828 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3829 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3830 3831 if (sc->bge_flags & BGEF_TSO) 3832 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3833 3834 /* 3835 * Do MII setup. 3836 */ 3837 DPRINTFN(5, ("mii setup\n")); 3838 mii->mii_ifp = ifp; 3839 mii->mii_readreg = bge_miibus_readreg; 3840 mii->mii_writereg = bge_miibus_writereg; 3841 mii->mii_statchg = bge_miibus_statchg; 3842 3843 /* 3844 * Figure out what sort of media we have by checking the hardware 3845 * config word. Note: on some BCM5700 cards, this value appears to be 3846 * unset. If that's the case, we have to rely on identifying the NIC 3847 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3848 * The SysKonnect SK-9D41 is a 1000baseSX card. 3849 */ 3850 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3851 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3852 if (BGE_IS_5705_PLUS(sc)) { 3853 sc->bge_flags |= BGEF_FIBER_MII; 3854 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3855 } else 3856 sc->bge_flags |= BGEF_FIBER_TBI; 3857 } 3858 3859 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3860 if (BGE_IS_JUMBO_CAPABLE(sc)) 3861 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3862 3863 /* set phyflags and chipid before mii_attach() */ 3864 dict = device_properties(self); 3865 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3866 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3867 3868 /* Initialize ifmedia structures. */ 3869 if (sc->bge_flags & BGEF_FIBER_TBI) { 3870 sc->ethercom.ec_ifmedia = &sc->bge_ifmedia; 3871 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3872 bge_ifmedia_sts); 3873 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3874 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3875 0, NULL); 3876 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3877 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3878 /* Pretend the user requested this setting */ 3879 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3880 } else { 3881 /* 3882 * Do transceiver setup and tell the firmware the 3883 * driver is down so we can try to get access the 3884 * probe if ASF is running. Retry a couple of times 3885 * if we get a conflict with the ASF firmware accessing 3886 * the PHY. 3887 */ 3888 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3889 bge_asf_driver_up(sc); 3890 3891 sc->ethercom.ec_mii = mii; 3892 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3893 bge_ifmedia_sts); 3894 mii_flags = MIIF_DOPAUSE; 3895 if (sc->bge_flags & BGEF_FIBER_MII) 3896 mii_flags |= MIIF_HAVEFIBER; 3897 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 3898 MII_OFFSET_ANY, mii_flags); 3899 3900 if (LIST_EMPTY(&mii->mii_phys)) { 3901 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3902 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 3903 0, NULL); 3904 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 3905 } else 3906 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 3907 3908 /* 3909 * Now tell the firmware we are going up after probing the PHY 3910 */ 3911 if (sc->bge_asf_mode & ASF_STACKUP) 3912 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3913 } 3914 3915 /* 3916 * Call MI attach routine. 3917 */ 3918 DPRINTFN(5, ("if_attach\n")); 3919 if_attach(ifp); 3920 if_deferred_start_init(ifp, NULL); 3921 DPRINTFN(5, ("ether_ifattach\n")); 3922 ether_ifattach(ifp, eaddr); 3923 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3924 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3925 RND_TYPE_NET, RND_FLAG_DEFAULT); 3926 #ifdef BGE_EVENT_COUNTERS 3927 /* 3928 * Attach event counters. 3929 */ 3930 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3931 NULL, device_xname(sc->bge_dev), "intr"); 3932 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3933 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3934 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3935 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3936 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3937 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3938 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3939 NULL, device_xname(sc->bge_dev), "tx_xon"); 3940 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3941 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3942 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3943 NULL, device_xname(sc->bge_dev), "rx_xon"); 3944 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3945 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3946 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3947 NULL, device_xname(sc->bge_dev), "xoffentered"); 3948 #endif /* BGE_EVENT_COUNTERS */ 3949 DPRINTFN(5, ("callout_init\n")); 3950 callout_init(&sc->bge_timeout, 0); 3951 3952 if (pmf_device_register(self, NULL, NULL)) 3953 pmf_class_network_register(self, ifp); 3954 else 3955 aprint_error_dev(self, "couldn't establish power handler\n"); 3956 3957 bge_sysctl_init(sc); 3958 3959 #ifdef BGE_DEBUG 3960 bge_debug_info(sc); 3961 #endif 3962 } 3963 3964 /* 3965 * Stop all chip I/O so that the kernel's probe routines don't 3966 * get confused by errant DMAs when rebooting. 3967 */ 3968 static int 3969 bge_detach(device_t self, int flags __unused) 3970 { 3971 struct bge_softc *sc = device_private(self); 3972 struct ifnet *ifp = &sc->ethercom.ec_if; 3973 int s; 3974 3975 s = splnet(); 3976 /* Stop the interface. Callouts are stopped in it. */ 3977 bge_stop(ifp, 1); 3978 splx(s); 3979 3980 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3981 3982 /* Delete all remaining media. */ 3983 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3984 3985 ether_ifdetach(ifp); 3986 if_detach(ifp); 3987 3988 bge_release_resources(sc); 3989 3990 return 0; 3991 } 3992 3993 static void 3994 bge_release_resources(struct bge_softc *sc) 3995 { 3996 3997 /* Detach sysctl */ 3998 if (sc->bge_log != NULL) 3999 sysctl_teardown(&sc->bge_log); 4000 4001 #ifdef BGE_EVENT_COUNTERS 4002 /* Detach event counters. */ 4003 evcnt_detach(&sc->bge_ev_intr); 4004 evcnt_detach(&sc->bge_ev_intr_spurious); 4005 evcnt_detach(&sc->bge_ev_intr_spurious2); 4006 evcnt_detach(&sc->bge_ev_tx_xoff); 4007 evcnt_detach(&sc->bge_ev_tx_xon); 4008 evcnt_detach(&sc->bge_ev_rx_xoff); 4009 evcnt_detach(&sc->bge_ev_rx_xon); 4010 evcnt_detach(&sc->bge_ev_rx_macctl); 4011 evcnt_detach(&sc->bge_ev_xoffentered); 4012 #endif /* BGE_EVENT_COUNTERS */ 4013 4014 /* Disestablish the interrupt handler */ 4015 if (sc->bge_intrhand != NULL) { 4016 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4017 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4018 sc->bge_intrhand = NULL; 4019 } 4020 4021 if (sc->bge_dmatag != NULL) { 4022 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4023 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4024 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4025 sizeof(struct bge_ring_data)); 4026 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4027 sc->bge_ring_rseg); 4028 } 4029 4030 /* Unmap the device registers */ 4031 if (sc->bge_bsize != 0) { 4032 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4033 sc->bge_bsize = 0; 4034 } 4035 4036 /* Unmap the APE registers */ 4037 if (sc->bge_apesize != 0) { 4038 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4039 sc->bge_apesize); 4040 sc->bge_apesize = 0; 4041 } 4042 } 4043 4044 static int 4045 bge_reset(struct bge_softc *sc) 4046 { 4047 uint32_t cachesize, command; 4048 uint32_t reset, mac_mode, mac_mode_mask; 4049 pcireg_t devctl, reg; 4050 int i, val; 4051 void (*write_op)(struct bge_softc *, int, int); 4052 4053 /* Make mask for BGE_MAC_MODE register. */ 4054 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4055 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4056 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4057 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4058 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4059 4060 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4061 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4062 if (sc->bge_flags & BGEF_PCIE) 4063 write_op = bge_writemem_direct; 4064 else 4065 write_op = bge_writemem_ind; 4066 } else 4067 write_op = bge_writereg_ind; 4068 4069 /* 57XX step 4 */ 4070 /* Acquire the NVM lock */ 4071 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4072 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4073 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4074 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4075 for (i = 0; i < 8000; i++) { 4076 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4077 BGE_NVRAMSWARB_GNT1) 4078 break; 4079 DELAY(20); 4080 } 4081 if (i == 8000) { 4082 printf("%s: NVRAM lock timedout!\n", 4083 device_xname(sc->bge_dev)); 4084 } 4085 } 4086 4087 /* Take APE lock when performing reset. */ 4088 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4089 4090 /* 57XX step 3 */ 4091 /* Save some important PCI state. */ 4092 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4093 /* 5718 reset step 3 */ 4094 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4095 4096 /* 5718 reset step 5, 57XX step 5b-5d */ 4097 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4098 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4099 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4100 4101 /* XXX ???: Disable fastboot on controllers that support it. */ 4102 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4103 BGE_IS_5755_PLUS(sc)) 4104 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4105 4106 /* 5718 reset step 2, 57XX step 6 */ 4107 /* 4108 * Write the magic number to SRAM at offset 0xB50. 4109 * When firmware finishes its initialization it will 4110 * write ~BGE_MAGIC_NUMBER to the same location. 4111 */ 4112 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4113 4114 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4115 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4116 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4117 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4118 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4119 } 4120 4121 /* 5718 reset step 6, 57XX step 7 */ 4122 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4123 /* 4124 * XXX: from FreeBSD/Linux; no documentation 4125 */ 4126 if (sc->bge_flags & BGEF_PCIE) { 4127 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4128 !BGE_IS_57765_PLUS(sc) && 4129 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4130 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4131 /* PCI Express 1.0 system */ 4132 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4133 BGE_PHY_PCIE_SCRAM_MODE); 4134 } 4135 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4136 /* 4137 * Prevent PCI Express link training 4138 * during global reset. 4139 */ 4140 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4141 reset |= (1 << 29); 4142 } 4143 } 4144 4145 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4146 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4147 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4148 i | BGE_VCPU_STATUS_DRV_RESET); 4149 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4150 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4151 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4152 } 4153 4154 /* 4155 * Set GPHY Power Down Override to leave GPHY 4156 * powered up in D0 uninitialized. 4157 */ 4158 if (BGE_IS_5705_PLUS(sc) && 4159 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4160 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4161 4162 /* Issue global reset */ 4163 write_op(sc, BGE_MISC_CFG, reset); 4164 4165 /* 5718 reset step 7, 57XX step 8 */ 4166 if (sc->bge_flags & BGEF_PCIE) 4167 delay(100*1000); /* too big */ 4168 else 4169 delay(1000); 4170 4171 if (sc->bge_flags & BGEF_PCIE) { 4172 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4173 DELAY(500000); 4174 /* XXX: Magic Numbers */ 4175 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4176 BGE_PCI_UNKNOWN0); 4177 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4178 BGE_PCI_UNKNOWN0, 4179 reg | (1 << 15)); 4180 } 4181 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4182 sc->bge_pciecap + PCIE_DCSR); 4183 /* Clear enable no snoop and disable relaxed ordering. */ 4184 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4185 PCIE_DCSR_ENA_NO_SNOOP); 4186 4187 /* Set PCIE max payload size to 128 for older PCIe devices */ 4188 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4189 devctl &= ~(0x00e0); 4190 /* Clear device status register. Write 1b to clear */ 4191 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4192 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4193 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4194 sc->bge_pciecap + PCIE_DCSR, devctl); 4195 bge_set_max_readrq(sc); 4196 } 4197 4198 /* From Linux: dummy read to flush PCI posted writes */ 4199 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4200 4201 /* 4202 * Reset some of the PCI state that got zapped by reset 4203 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4204 * set, too. 4205 */ 4206 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4207 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4208 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4209 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4210 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4211 (sc->bge_flags & BGEF_PCIX) != 0) 4212 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4213 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4214 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4215 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4216 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4217 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4218 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4219 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4220 4221 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4222 if (sc->bge_flags & BGEF_PCIX) { 4223 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4224 + PCIX_CMD); 4225 /* Set max memory read byte count to 2K */ 4226 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4227 reg &= ~PCIX_CMD_BYTECNT_MASK; 4228 reg |= PCIX_CMD_BCNT_2048; 4229 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4230 /* 4231 * For 5704, set max outstanding split transaction 4232 * field to 0 (0 means it supports 1 request) 4233 */ 4234 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4235 | PCIX_CMD_BYTECNT_MASK); 4236 reg |= PCIX_CMD_BCNT_2048; 4237 } 4238 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4239 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4240 } 4241 4242 /* 5718 reset step 10, 57XX step 12 */ 4243 /* Enable memory arbiter. */ 4244 if (BGE_IS_5714_FAMILY(sc)) { 4245 val = CSR_READ_4(sc, BGE_MARB_MODE); 4246 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4247 } else 4248 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4249 4250 /* XXX 5721, 5751 and 5752 */ 4251 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4252 /* Step 19: */ 4253 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4254 /* Step 20: */ 4255 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4256 } 4257 4258 /* 5718 reset step 12, 57XX step 15 and 16 */ 4259 /* Fix up byte swapping */ 4260 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4261 4262 /* 5718 reset step 13, 57XX step 17 */ 4263 /* Poll until the firmware initialization is complete */ 4264 bge_poll_fw(sc); 4265 4266 /* 57XX step 21 */ 4267 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4268 pcireg_t msidata; 4269 4270 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4271 BGE_PCI_MSI_DATA); 4272 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4273 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4274 msidata); 4275 } 4276 4277 /* 57XX step 18 */ 4278 /* Write mac mode. */ 4279 val = CSR_READ_4(sc, BGE_MAC_MODE); 4280 /* Restore mac_mode_mask's bits using mac_mode */ 4281 val = (val & ~mac_mode_mask) | mac_mode; 4282 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4283 DELAY(40); 4284 4285 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4286 4287 /* 4288 * The 5704 in TBI mode apparently needs some special 4289 * adjustment to insure the SERDES drive level is set 4290 * to 1.2V. 4291 */ 4292 if (sc->bge_flags & BGEF_FIBER_TBI && 4293 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4294 uint32_t serdescfg; 4295 4296 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4297 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4298 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4299 } 4300 4301 if (sc->bge_flags & BGEF_PCIE && 4302 !BGE_IS_57765_PLUS(sc) && 4303 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4304 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4305 uint32_t v; 4306 4307 /* Enable PCI Express bug fix */ 4308 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4309 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4310 v | BGE_TLP_DATA_FIFO_PROTECT); 4311 } 4312 4313 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4314 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4315 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4316 4317 return 0; 4318 } 4319 4320 /* 4321 * Frame reception handling. This is called if there's a frame 4322 * on the receive return list. 4323 * 4324 * Note: we have to be able to handle two possibilities here: 4325 * 1) the frame is from the jumbo receive ring 4326 * 2) the frame is from the standard receive ring 4327 */ 4328 4329 static void 4330 bge_rxeof(struct bge_softc *sc) 4331 { 4332 struct ifnet *ifp; 4333 uint16_t rx_prod, rx_cons; 4334 int stdcnt = 0, jumbocnt = 0; 4335 bus_dmamap_t dmamap; 4336 bus_addr_t offset, toff; 4337 bus_size_t tlen; 4338 int tosync; 4339 4340 rx_cons = sc->bge_rx_saved_considx; 4341 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4342 4343 /* Nothing to do */ 4344 if (rx_cons == rx_prod) 4345 return; 4346 4347 ifp = &sc->ethercom.ec_if; 4348 4349 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4350 offsetof(struct bge_ring_data, bge_status_block), 4351 sizeof (struct bge_status_block), 4352 BUS_DMASYNC_POSTREAD); 4353 4354 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4355 tosync = rx_prod - rx_cons; 4356 4357 if (tosync != 0) 4358 rnd_add_uint32(&sc->rnd_source, tosync); 4359 4360 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4361 4362 if (tosync < 0) { 4363 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4364 sizeof (struct bge_rx_bd); 4365 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4366 toff, tlen, BUS_DMASYNC_POSTREAD); 4367 tosync = -tosync; 4368 } 4369 4370 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4371 offset, tosync * sizeof (struct bge_rx_bd), 4372 BUS_DMASYNC_POSTREAD); 4373 4374 while (rx_cons != rx_prod) { 4375 struct bge_rx_bd *cur_rx; 4376 uint32_t rxidx; 4377 struct mbuf *m = NULL; 4378 4379 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4380 4381 rxidx = cur_rx->bge_idx; 4382 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4383 4384 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4385 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4386 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4387 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4388 jumbocnt++; 4389 bus_dmamap_sync(sc->bge_dmatag, 4390 sc->bge_cdata.bge_rx_jumbo_map, 4391 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4392 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4393 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4394 ifp->if_ierrors++; 4395 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4396 continue; 4397 } 4398 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4399 NULL)== ENOBUFS) { 4400 ifp->if_ierrors++; 4401 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4402 continue; 4403 } 4404 } else { 4405 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4406 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4407 4408 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4409 stdcnt++; 4410 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4411 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4412 if (dmamap == NULL) { 4413 ifp->if_ierrors++; 4414 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4415 continue; 4416 } 4417 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4418 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4419 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4420 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4421 ifp->if_ierrors++; 4422 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4423 continue; 4424 } 4425 if (bge_newbuf_std(sc, sc->bge_std, 4426 NULL, dmamap) == ENOBUFS) { 4427 ifp->if_ierrors++; 4428 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4429 continue; 4430 } 4431 } 4432 4433 #ifndef __NO_STRICT_ALIGNMENT 4434 /* 4435 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4436 * the Rx buffer has the layer-2 header unaligned. 4437 * If our CPU requires alignment, re-align by copying. 4438 */ 4439 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4440 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4441 cur_rx->bge_len); 4442 m->m_data += ETHER_ALIGN; 4443 } 4444 #endif 4445 4446 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4447 m_set_rcvif(m, ifp); 4448 4449 bge_rxcsum(sc, cur_rx, m); 4450 4451 /* 4452 * If we received a packet with a vlan tag, pass it 4453 * to vlan_input() instead of ether_input(). 4454 */ 4455 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4456 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4457 4458 if_percpuq_enqueue(ifp->if_percpuq, m); 4459 } 4460 4461 sc->bge_rx_saved_considx = rx_cons; 4462 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4463 if (stdcnt) 4464 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4465 if (jumbocnt) 4466 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4467 } 4468 4469 static void 4470 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4471 { 4472 4473 if (BGE_IS_57765_PLUS(sc)) { 4474 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4475 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4476 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4477 if ((cur_rx->bge_error_flag & 4478 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4479 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4480 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4481 m->m_pkthdr.csum_data = 4482 cur_rx->bge_tcp_udp_csum; 4483 m->m_pkthdr.csum_flags |= 4484 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4485 } 4486 } 4487 } else { 4488 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4489 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4490 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4491 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4492 /* 4493 * Rx transport checksum-offload may also 4494 * have bugs with packets which, when transmitted, 4495 * were `runts' requiring padding. 4496 */ 4497 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4498 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4499 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4500 m->m_pkthdr.csum_data = 4501 cur_rx->bge_tcp_udp_csum; 4502 m->m_pkthdr.csum_flags |= 4503 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4504 } 4505 } 4506 } 4507 4508 static void 4509 bge_txeof(struct bge_softc *sc) 4510 { 4511 struct bge_tx_bd *cur_tx = NULL; 4512 struct ifnet *ifp; 4513 struct txdmamap_pool_entry *dma; 4514 bus_addr_t offset, toff; 4515 bus_size_t tlen; 4516 int tosync; 4517 struct mbuf *m; 4518 4519 ifp = &sc->ethercom.ec_if; 4520 4521 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4522 offsetof(struct bge_ring_data, bge_status_block), 4523 sizeof (struct bge_status_block), 4524 BUS_DMASYNC_POSTREAD); 4525 4526 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4527 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4528 sc->bge_tx_saved_considx; 4529 4530 if (tosync != 0) 4531 rnd_add_uint32(&sc->rnd_source, tosync); 4532 4533 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4534 4535 if (tosync < 0) { 4536 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4537 sizeof (struct bge_tx_bd); 4538 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4539 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4540 tosync = -tosync; 4541 } 4542 4543 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4544 offset, tosync * sizeof (struct bge_tx_bd), 4545 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4546 4547 /* 4548 * Go through our tx ring and free mbufs for those 4549 * frames that have been sent. 4550 */ 4551 while (sc->bge_tx_saved_considx != 4552 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4553 uint32_t idx = 0; 4554 4555 idx = sc->bge_tx_saved_considx; 4556 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4557 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4558 ifp->if_opackets++; 4559 m = sc->bge_cdata.bge_tx_chain[idx]; 4560 if (m != NULL) { 4561 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4562 dma = sc->txdma[idx]; 4563 if (dma->is_dma32) { 4564 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4565 0, dma->dmamap32->dm_mapsize, 4566 BUS_DMASYNC_POSTWRITE); 4567 bus_dmamap_unload( 4568 sc->bge_dmatag32, dma->dmamap32); 4569 } else { 4570 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4571 0, dma->dmamap->dm_mapsize, 4572 BUS_DMASYNC_POSTWRITE); 4573 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4574 } 4575 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4576 sc->txdma[idx] = NULL; 4577 4578 m_freem(m); 4579 } 4580 sc->bge_txcnt--; 4581 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4582 ifp->if_timer = 0; 4583 } 4584 4585 if (cur_tx != NULL) 4586 ifp->if_flags &= ~IFF_OACTIVE; 4587 } 4588 4589 static int 4590 bge_intr(void *xsc) 4591 { 4592 struct bge_softc *sc; 4593 struct ifnet *ifp; 4594 uint32_t pcistate, statusword, statustag; 4595 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4596 4597 sc = xsc; 4598 ifp = &sc->ethercom.ec_if; 4599 4600 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4601 if (BGE_IS_5717_PLUS(sc)) 4602 intrmask = 0; 4603 4604 /* It is possible for the interrupt to arrive before 4605 * the status block is updated prior to the interrupt. 4606 * Reading the PCI State register will confirm whether the 4607 * interrupt is ours and will flush the status block. 4608 */ 4609 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4610 4611 /* read status word from status block */ 4612 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4613 offsetof(struct bge_ring_data, bge_status_block), 4614 sizeof (struct bge_status_block), 4615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4616 statusword = sc->bge_rdata->bge_status_block.bge_status; 4617 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4618 4619 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4620 if (sc->bge_lasttag == statustag && 4621 (~pcistate & intrmask)) { 4622 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4623 return (0); 4624 } 4625 sc->bge_lasttag = statustag; 4626 } else { 4627 if (!(statusword & BGE_STATFLAG_UPDATED) && 4628 !(~pcistate & intrmask)) { 4629 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4630 return (0); 4631 } 4632 statustag = 0; 4633 } 4634 /* Ack interrupt and stop others from occurring. */ 4635 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4636 BGE_EVCNT_INCR(sc->bge_ev_intr); 4637 4638 /* clear status word */ 4639 sc->bge_rdata->bge_status_block.bge_status = 0; 4640 4641 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4642 offsetof(struct bge_ring_data, bge_status_block), 4643 sizeof (struct bge_status_block), 4644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4645 4646 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4647 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4648 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4649 bge_link_upd(sc); 4650 4651 if (ifp->if_flags & IFF_RUNNING) { 4652 /* Check RX return ring producer/consumer */ 4653 bge_rxeof(sc); 4654 4655 /* Check TX ring producer/consumer */ 4656 bge_txeof(sc); 4657 } 4658 4659 if (sc->bge_pending_rxintr_change) { 4660 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4661 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4662 4663 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4664 DELAY(10); 4665 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4666 4667 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4668 DELAY(10); 4669 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4670 4671 sc->bge_pending_rxintr_change = 0; 4672 } 4673 bge_handle_events(sc); 4674 4675 /* Re-enable interrupts. */ 4676 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4677 4678 if (ifp->if_flags & IFF_RUNNING) 4679 if_schedule_deferred_start(ifp); 4680 4681 return 1; 4682 } 4683 4684 static void 4685 bge_asf_driver_up(struct bge_softc *sc) 4686 { 4687 if (sc->bge_asf_mode & ASF_STACKUP) { 4688 /* Send ASF heartbeat aprox. every 2s */ 4689 if (sc->bge_asf_count) 4690 sc->bge_asf_count --; 4691 else { 4692 sc->bge_asf_count = 2; 4693 4694 bge_wait_for_event_ack(sc); 4695 4696 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4697 BGE_FW_CMD_DRV_ALIVE3); 4698 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4699 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4700 BGE_FW_HB_TIMEOUT_SEC); 4701 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4702 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4703 BGE_RX_CPU_DRV_EVENT); 4704 } 4705 } 4706 } 4707 4708 static void 4709 bge_tick(void *xsc) 4710 { 4711 struct bge_softc *sc = xsc; 4712 struct mii_data *mii = &sc->bge_mii; 4713 int s; 4714 4715 s = splnet(); 4716 4717 if (BGE_IS_5705_PLUS(sc)) 4718 bge_stats_update_regs(sc); 4719 else 4720 bge_stats_update(sc); 4721 4722 if (sc->bge_flags & BGEF_FIBER_TBI) { 4723 /* 4724 * Since in TBI mode auto-polling can't be used we should poll 4725 * link status manually. Here we register pending link event 4726 * and trigger interrupt. 4727 */ 4728 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4729 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4730 } else { 4731 /* 4732 * Do not touch PHY if we have link up. This could break 4733 * IPMI/ASF mode or produce extra input errors. 4734 * (extra input errors was reported for bcm5701 & bcm5704). 4735 */ 4736 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4737 mii_tick(mii); 4738 } 4739 4740 bge_asf_driver_up(sc); 4741 4742 if (!sc->bge_detaching) 4743 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4744 4745 splx(s); 4746 } 4747 4748 static void 4749 bge_stats_update_regs(struct bge_softc *sc) 4750 { 4751 struct ifnet *ifp = &sc->ethercom.ec_if; 4752 4753 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 4754 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 4755 4756 /* 4757 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4758 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4759 * (silicon bug). There's no reliable workaround so just 4760 * ignore the counter 4761 */ 4762 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4763 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4764 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4765 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4766 } 4767 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4768 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4769 4770 if (sc->bge_flags & BGEF_RDMA_BUG) { 4771 uint32_t val, ucast, mcast, bcast; 4772 4773 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4774 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4775 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4776 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4777 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4778 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4779 4780 /* 4781 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4782 * frames, it's safe to disable workaround for DMA engine's 4783 * miscalculation of TXMBUF space. 4784 */ 4785 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4786 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4787 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4788 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4789 else 4790 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4791 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4792 sc->bge_flags &= ~BGEF_RDMA_BUG; 4793 } 4794 } 4795 } 4796 4797 static void 4798 bge_stats_update(struct bge_softc *sc) 4799 { 4800 struct ifnet *ifp = &sc->ethercom.ec_if; 4801 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4802 4803 #define READ_STAT(sc, stats, stat) \ 4804 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4805 4806 ifp->if_collisions += 4807 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4808 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4809 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4810 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 4811 ifp->if_collisions; 4812 4813 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4814 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4815 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4816 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4817 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4818 READ_STAT(sc, stats, 4819 xoffPauseFramesReceived.bge_addr_lo)); 4820 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4821 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4822 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4823 READ_STAT(sc, stats, 4824 macControlFramesReceived.bge_addr_lo)); 4825 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4826 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4827 4828 #undef READ_STAT 4829 4830 #ifdef notdef 4831 ifp->if_collisions += 4832 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4833 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4834 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4835 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4836 ifp->if_collisions; 4837 #endif 4838 } 4839 4840 /* 4841 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4842 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4843 * but when such padded frames employ the bge IP/TCP checksum offload, 4844 * the hardware checksum assist gives incorrect results (possibly 4845 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4846 * If we pad such runts with zeros, the onboard checksum comes out correct. 4847 */ 4848 static inline int 4849 bge_cksum_pad(struct mbuf *pkt) 4850 { 4851 struct mbuf *last = NULL; 4852 int padlen; 4853 4854 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4855 4856 /* if there's only the packet-header and we can pad there, use it. */ 4857 if (pkt->m_pkthdr.len == pkt->m_len && 4858 M_TRAILINGSPACE(pkt) >= padlen) { 4859 last = pkt; 4860 } else { 4861 /* 4862 * Walk packet chain to find last mbuf. We will either 4863 * pad there, or append a new mbuf and pad it 4864 * (thus perhaps avoiding the bcm5700 dma-min bug). 4865 */ 4866 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4867 continue; /* do nothing */ 4868 } 4869 4870 /* `last' now points to last in chain. */ 4871 if (M_TRAILINGSPACE(last) < padlen) { 4872 /* Allocate new empty mbuf, pad it. Compact later. */ 4873 struct mbuf *n; 4874 MGET(n, M_DONTWAIT, MT_DATA); 4875 if (n == NULL) 4876 return ENOBUFS; 4877 n->m_len = 0; 4878 last->m_next = n; 4879 last = n; 4880 } 4881 } 4882 4883 KDASSERT(!M_READONLY(last)); 4884 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4885 4886 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4887 memset(mtod(last, char *) + last->m_len, 0, padlen); 4888 last->m_len += padlen; 4889 pkt->m_pkthdr.len += padlen; 4890 return 0; 4891 } 4892 4893 /* 4894 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4895 */ 4896 static inline int 4897 bge_compact_dma_runt(struct mbuf *pkt) 4898 { 4899 struct mbuf *m, *prev; 4900 int totlen; 4901 4902 prev = NULL; 4903 totlen = 0; 4904 4905 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 4906 int mlen = m->m_len; 4907 int shortfall = 8 - mlen ; 4908 4909 totlen += mlen; 4910 if (mlen == 0) 4911 continue; 4912 if (mlen >= 8) 4913 continue; 4914 4915 /* If we get here, mbuf data is too small for DMA engine. 4916 * Try to fix by shuffling data to prev or next in chain. 4917 * If that fails, do a compacting deep-copy of the whole chain. 4918 */ 4919 4920 /* Internal frag. If fits in prev, copy it there. */ 4921 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4922 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4923 prev->m_len += mlen; 4924 m->m_len = 0; 4925 /* XXX stitch chain */ 4926 prev->m_next = m_free(m); 4927 m = prev; 4928 continue; 4929 } else if (m->m_next != NULL && 4930 M_TRAILINGSPACE(m) >= shortfall && 4931 m->m_next->m_len >= (8 + shortfall)) { 4932 /* m is writable and have enough data in next, pull up. */ 4933 4934 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4935 shortfall); 4936 m->m_len += shortfall; 4937 m->m_next->m_len -= shortfall; 4938 m->m_next->m_data += shortfall; 4939 } else if (m->m_next == NULL || 1) { 4940 /* Got a runt at the very end of the packet. 4941 * borrow data from the tail of the preceding mbuf and 4942 * update its length in-place. (The original data is 4943 * still valid, so we can do this even if prev is not 4944 * writable.) 4945 */ 4946 4947 /* 4948 * If we'd make prev a runt, just move all of its data. 4949 */ 4950 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 4951 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 4952 4953 if ((prev->m_len - shortfall) < 8) 4954 shortfall = prev->m_len; 4955 4956 #ifdef notyet /* just do the safe slow thing for now */ 4957 if (!M_READONLY(m)) { 4958 if (M_LEADINGSPACE(m) < shorfall) { 4959 void *m_dat; 4960 m_dat = M_BUFADDR(m); 4961 memmove(m_dat, mtod(m, void*), 4962 m->m_len); 4963 m->m_data = m_dat; 4964 } 4965 } else 4966 #endif /* just do the safe slow thing */ 4967 { 4968 struct mbuf * n = NULL; 4969 int newprevlen = prev->m_len - shortfall; 4970 4971 MGET(n, M_NOWAIT, MT_DATA); 4972 if (n == NULL) 4973 return ENOBUFS; 4974 KASSERT(m->m_len + shortfall < MLEN 4975 /*, 4976 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 4977 4978 /* first copy the data we're stealing from prev */ 4979 memcpy(n->m_data, prev->m_data + newprevlen, 4980 shortfall); 4981 4982 /* update prev->m_len accordingly */ 4983 prev->m_len -= shortfall; 4984 4985 /* copy data from runt m */ 4986 memcpy(n->m_data + shortfall, m->m_data, 4987 m->m_len); 4988 4989 /* n holds what we stole from prev, plus m */ 4990 n->m_len = shortfall + m->m_len; 4991 4992 /* stitch n into chain and free m */ 4993 n->m_next = m->m_next; 4994 prev->m_next = n; 4995 /* KASSERT(m->m_next == NULL); */ 4996 m->m_next = NULL; 4997 m_free(m); 4998 m = n; /* for continuing loop */ 4999 } 5000 } 5001 } 5002 return 0; 5003 } 5004 5005 /* 5006 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5007 * pointers to descriptors. 5008 */ 5009 static int 5010 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5011 { 5012 struct ifnet *ifp = &sc->ethercom.ec_if; 5013 struct bge_tx_bd *f, *prev_f; 5014 uint32_t frag, cur; 5015 uint16_t csum_flags = 0; 5016 uint16_t txbd_tso_flags = 0; 5017 struct txdmamap_pool_entry *dma; 5018 bus_dmamap_t dmamap; 5019 bus_dma_tag_t dmatag; 5020 int i = 0; 5021 int use_tso, maxsegsize, error; 5022 bool have_vtag; 5023 uint16_t vtag; 5024 bool remap; 5025 5026 if (m_head->m_pkthdr.csum_flags) { 5027 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5028 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5029 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5030 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5031 } 5032 5033 /* 5034 * If we were asked to do an outboard checksum, and the NIC 5035 * has the bug where it sometimes adds in the Ethernet padding, 5036 * explicitly pad with zeros so the cksum will be correct either way. 5037 * (For now, do this for all chip versions, until newer 5038 * are confirmed to not require the workaround.) 5039 */ 5040 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5041 #ifdef notyet 5042 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5043 #endif 5044 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5045 goto check_dma_bug; 5046 5047 if (bge_cksum_pad(m_head) != 0) 5048 return ENOBUFS; 5049 5050 check_dma_bug: 5051 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5052 goto doit; 5053 5054 /* 5055 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5056 * less than eight bytes. If we encounter a teeny mbuf 5057 * at the end of a chain, we can pad. Otherwise, copy. 5058 */ 5059 if (bge_compact_dma_runt(m_head) != 0) 5060 return ENOBUFS; 5061 5062 doit: 5063 dma = SLIST_FIRST(&sc->txdma_list); 5064 if (dma == NULL) { 5065 ifp->if_flags |= IFF_OACTIVE; 5066 return ENOBUFS; 5067 } 5068 dmamap = dma->dmamap; 5069 dmatag = sc->bge_dmatag; 5070 dma->is_dma32 = false; 5071 5072 /* 5073 * Set up any necessary TSO state before we start packing... 5074 */ 5075 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5076 if (!use_tso) { 5077 maxsegsize = 0; 5078 } else { /* TSO setup */ 5079 unsigned mss; 5080 struct ether_header *eh; 5081 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5082 unsigned bge_hlen; 5083 struct mbuf * m0 = m_head; 5084 struct ip *ip; 5085 struct tcphdr *th; 5086 int iphl, hlen; 5087 5088 /* 5089 * XXX It would be nice if the mbuf pkthdr had offset 5090 * fields for the protocol headers. 5091 */ 5092 5093 eh = mtod(m0, struct ether_header *); 5094 switch (htons(eh->ether_type)) { 5095 case ETHERTYPE_IP: 5096 offset = ETHER_HDR_LEN; 5097 break; 5098 5099 case ETHERTYPE_VLAN: 5100 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5101 break; 5102 5103 default: 5104 /* 5105 * Don't support this protocol or encapsulation. 5106 */ 5107 return ENOBUFS; 5108 } 5109 5110 /* 5111 * TCP/IP headers are in the first mbuf; we can do 5112 * this the easy way. 5113 */ 5114 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5115 hlen = iphl + offset; 5116 if (__predict_false(m0->m_len < 5117 (hlen + sizeof(struct tcphdr)))) { 5118 5119 aprint_error_dev(sc->bge_dev, 5120 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5121 "not handled yet\n", 5122 m0->m_len, hlen+ sizeof(struct tcphdr)); 5123 #ifdef NOTYET 5124 /* 5125 * XXX jonathan (at) NetBSD.org: untested. 5126 * how to force this branch to be taken? 5127 */ 5128 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5129 5130 m_copydata(m0, offset, sizeof(ip), &ip); 5131 m_copydata(m0, hlen, sizeof(th), &th); 5132 5133 ip.ip_len = 0; 5134 5135 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5136 sizeof(ip.ip_len), &ip.ip_len); 5137 5138 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5139 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5140 5141 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5142 sizeof(th.th_sum), &th.th_sum); 5143 5144 hlen += th.th_off << 2; 5145 iptcp_opt_words = hlen; 5146 #else 5147 /* 5148 * if_wm "hard" case not yet supported, can we not 5149 * mandate it out of existence? 5150 */ 5151 (void) ip; (void)th; (void) ip_tcp_hlen; 5152 5153 return ENOBUFS; 5154 #endif 5155 } else { 5156 ip = (struct ip *) (mtod(m0, char *) + offset); 5157 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5158 ip_tcp_hlen = iphl + (th->th_off << 2); 5159 5160 /* Total IP/TCP options, in 32-bit words */ 5161 iptcp_opt_words = (ip_tcp_hlen 5162 - sizeof(struct tcphdr) 5163 - sizeof(struct ip)) >> 2; 5164 } 5165 if (BGE_IS_575X_PLUS(sc)) { 5166 th->th_sum = 0; 5167 csum_flags = 0; 5168 } else { 5169 /* 5170 * XXX jonathan (at) NetBSD.org: 5705 untested. 5171 * Requires TSO firmware patch for 5701/5703/5704. 5172 */ 5173 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5174 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5175 } 5176 5177 mss = m_head->m_pkthdr.segsz; 5178 txbd_tso_flags |= 5179 BGE_TXBDFLAG_CPU_PRE_DMA | 5180 BGE_TXBDFLAG_CPU_POST_DMA; 5181 5182 /* 5183 * Our NIC TSO-assist assumes TSO has standard, optionless 5184 * IPv4 and TCP headers, which total 40 bytes. By default, 5185 * the NIC copies 40 bytes of IP/TCP header from the 5186 * supplied header into the IP/TCP header portion of 5187 * each post-TSO-segment. If the supplied packet has IP or 5188 * TCP options, we need to tell the NIC to copy those extra 5189 * bytes into each post-TSO header, in addition to the normal 5190 * 40-byte IP/TCP header (and to leave space accordingly). 5191 * Unfortunately, the driver encoding of option length 5192 * varies across different ASIC families. 5193 */ 5194 tcp_seg_flags = 0; 5195 bge_hlen = ip_tcp_hlen >> 2; 5196 if (BGE_IS_5717_PLUS(sc)) { 5197 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5198 txbd_tso_flags |= 5199 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5200 } else if (BGE_IS_5705_PLUS(sc)) { 5201 tcp_seg_flags = bge_hlen << 11; 5202 } else { 5203 /* XXX iptcp_opt_words or bge_hlen ? */ 5204 txbd_tso_flags |= iptcp_opt_words << 12; 5205 } 5206 maxsegsize = mss | tcp_seg_flags; 5207 ip->ip_len = htons(mss + ip_tcp_hlen); 5208 ip->ip_sum = 0; 5209 5210 } /* TSO setup */ 5211 5212 have_vtag = vlan_has_tag(m_head); 5213 if (have_vtag) 5214 vtag = vlan_get_tag(m_head); 5215 5216 /* 5217 * Start packing the mbufs in this chain into 5218 * the fragment pointers. Stop when we run out 5219 * of fragments or hit the end of the mbuf chain. 5220 */ 5221 remap = true; 5222 load_again: 5223 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5224 if (__predict_false(error)) { 5225 if (error == EFBIG && remap) { 5226 struct mbuf *m; 5227 remap = false; 5228 m = m_defrag(m_head, M_NOWAIT); 5229 if (m != NULL) { 5230 KASSERT(m == m_head); 5231 goto load_again; 5232 } 5233 } 5234 return error; 5235 } 5236 /* 5237 * Sanity check: avoid coming within 16 descriptors 5238 * of the end of the ring. 5239 */ 5240 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5241 BGE_TSO_PRINTF(("%s: " 5242 " dmamap_load_mbuf too close to ring wrap\n", 5243 device_xname(sc->bge_dev))); 5244 goto fail_unload; 5245 } 5246 5247 /* Iterate over dmap-map fragments. */ 5248 f = prev_f = NULL; 5249 cur = frag = *txidx; 5250 5251 for (i = 0; i < dmamap->dm_nsegs; i++) { 5252 f = &sc->bge_rdata->bge_tx_ring[frag]; 5253 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5254 break; 5255 5256 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5257 f->bge_len = dmamap->dm_segs[i].ds_len; 5258 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5259 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5260 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5261 (prev_f != NULL && 5262 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5263 ) { 5264 /* 5265 * watchdog timeout issue was observed with TSO, 5266 * limiting DMA address space to 32bits seems to 5267 * address the issue. 5268 */ 5269 bus_dmamap_unload(dmatag, dmamap); 5270 dmatag = sc->bge_dmatag32; 5271 dmamap = dma->dmamap32; 5272 dma->is_dma32 = true; 5273 remap = true; 5274 goto load_again; 5275 } 5276 5277 /* 5278 * For 5751 and follow-ons, for TSO we must turn 5279 * off checksum-assist flag in the tx-descr, and 5280 * supply the ASIC-revision-specific encoding 5281 * of TSO flags and segsize. 5282 */ 5283 if (use_tso) { 5284 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5285 f->bge_rsvd = maxsegsize; 5286 f->bge_flags = csum_flags | txbd_tso_flags; 5287 } else { 5288 f->bge_rsvd = 0; 5289 f->bge_flags = 5290 (csum_flags | txbd_tso_flags) & 0x0fff; 5291 } 5292 } else { 5293 f->bge_rsvd = 0; 5294 f->bge_flags = csum_flags; 5295 } 5296 5297 if (have_vtag) { 5298 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5299 f->bge_vlan_tag = vtag; 5300 } else { 5301 f->bge_vlan_tag = 0; 5302 } 5303 prev_f = f; 5304 cur = frag; 5305 BGE_INC(frag, BGE_TX_RING_CNT); 5306 } 5307 5308 if (i < dmamap->dm_nsegs) { 5309 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5310 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5311 goto fail_unload; 5312 } 5313 5314 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5315 BUS_DMASYNC_PREWRITE); 5316 5317 if (frag == sc->bge_tx_saved_considx) { 5318 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5319 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5320 5321 goto fail_unload; 5322 } 5323 5324 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5325 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5326 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5327 sc->txdma[cur] = dma; 5328 sc->bge_txcnt += dmamap->dm_nsegs; 5329 5330 *txidx = frag; 5331 5332 return 0; 5333 5334 fail_unload: 5335 bus_dmamap_unload(dmatag, dmamap); 5336 ifp->if_flags |= IFF_OACTIVE; 5337 5338 return ENOBUFS; 5339 } 5340 5341 /* 5342 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5343 * to the mbuf data regions directly in the transmit descriptors. 5344 */ 5345 static void 5346 bge_start(struct ifnet *ifp) 5347 { 5348 struct bge_softc *sc; 5349 struct mbuf *m_head = NULL; 5350 struct mbuf *m; 5351 uint32_t prodidx; 5352 int pkts = 0; 5353 int error; 5354 5355 sc = ifp->if_softc; 5356 5357 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5358 return; 5359 5360 prodidx = sc->bge_tx_prodidx; 5361 5362 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5363 IFQ_POLL(&ifp->if_snd, m_head); 5364 if (m_head == NULL) 5365 break; 5366 5367 #if 0 5368 /* 5369 * XXX 5370 * safety overkill. If this is a fragmented packet chain 5371 * with delayed TCP/UDP checksums, then only encapsulate 5372 * it if we have enough descriptors to handle the entire 5373 * chain at once. 5374 * (paranoia -- may not actually be needed) 5375 */ 5376 if (m_head->m_flags & M_FIRSTFRAG && 5377 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5378 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5379 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5380 ifp->if_flags |= IFF_OACTIVE; 5381 break; 5382 } 5383 } 5384 #endif 5385 5386 /* 5387 * Pack the data into the transmit ring. If we 5388 * don't have room, set the OACTIVE flag and wait 5389 * for the NIC to drain the ring. 5390 */ 5391 error = bge_encap(sc, m_head, &prodidx); 5392 if (__predict_false(error)) { 5393 if (ifp->if_flags & IFF_OACTIVE) { 5394 /* just wait for the transmit ring to drain */ 5395 break; 5396 } 5397 IFQ_DEQUEUE(&ifp->if_snd, m); 5398 KASSERT(m == m_head); 5399 m_freem(m_head); 5400 continue; 5401 } 5402 5403 /* now we are committed to transmit the packet */ 5404 IFQ_DEQUEUE(&ifp->if_snd, m); 5405 KASSERT(m == m_head); 5406 pkts++; 5407 5408 /* 5409 * If there's a BPF listener, bounce a copy of this frame 5410 * to him. 5411 */ 5412 bpf_mtap(ifp, m_head, BPF_D_OUT); 5413 } 5414 if (pkts == 0) 5415 return; 5416 5417 /* Transmit */ 5418 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5419 /* 5700 b2 errata */ 5420 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5421 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5422 5423 sc->bge_tx_prodidx = prodidx; 5424 5425 /* 5426 * Set a timeout in case the chip goes out to lunch. 5427 */ 5428 ifp->if_timer = 5; 5429 } 5430 5431 static int 5432 bge_init(struct ifnet *ifp) 5433 { 5434 struct bge_softc *sc = ifp->if_softc; 5435 const uint16_t *m; 5436 uint32_t mode, reg; 5437 int s, error = 0; 5438 5439 s = splnet(); 5440 5441 ifp = &sc->ethercom.ec_if; 5442 5443 /* Cancel pending I/O and flush buffers. */ 5444 bge_stop(ifp, 0); 5445 5446 bge_stop_fw(sc); 5447 bge_sig_pre_reset(sc, BGE_RESET_START); 5448 bge_reset(sc); 5449 bge_sig_legacy(sc, BGE_RESET_START); 5450 5451 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5452 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5453 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5454 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5455 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5456 5457 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5458 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5459 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5460 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5461 5462 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5463 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5464 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5465 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5466 5467 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5468 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5469 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5470 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5471 } 5472 5473 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5474 pcireg_t aercap; 5475 5476 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5477 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5478 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5479 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5480 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5481 5482 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5483 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5484 | BGE_PCIE_EIDLE_DELAY_13CLK; 5485 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5486 5487 /* Clear correctable error */ 5488 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5489 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5490 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5491 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5492 5493 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5494 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5495 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5496 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5497 } 5498 5499 bge_sig_post_reset(sc, BGE_RESET_START); 5500 5501 bge_chipinit(sc); 5502 5503 /* 5504 * Init the various state machines, ring 5505 * control blocks and firmware. 5506 */ 5507 error = bge_blockinit(sc); 5508 if (error != 0) { 5509 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5510 error); 5511 splx(s); 5512 return error; 5513 } 5514 5515 ifp = &sc->ethercom.ec_if; 5516 5517 /* 5718 step 25, 57XX step 54 */ 5518 /* Specify MTU. */ 5519 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5520 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5521 5522 /* 5718 step 23 */ 5523 /* Load our MAC address. */ 5524 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5525 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5526 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5527 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5528 5529 /* Enable or disable promiscuous mode as needed. */ 5530 if (ifp->if_flags & IFF_PROMISC) 5531 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5532 else 5533 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5534 5535 /* Program multicast filter. */ 5536 bge_setmulti(sc); 5537 5538 /* Init RX ring. */ 5539 bge_init_rx_ring_std(sc); 5540 5541 /* 5542 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5543 * memory to insure that the chip has in fact read the first 5544 * entry of the ring. 5545 */ 5546 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5547 uint32_t v, i; 5548 for (i = 0; i < 10; i++) { 5549 DELAY(20); 5550 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5551 if (v == (MCLBYTES - ETHER_ALIGN)) 5552 break; 5553 } 5554 if (i == 10) 5555 aprint_error_dev(sc->bge_dev, 5556 "5705 A0 chip failed to load RX ring\n"); 5557 } 5558 5559 /* Init jumbo RX ring. */ 5560 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5561 bge_init_rx_ring_jumbo(sc); 5562 5563 /* Init our RX return ring index */ 5564 sc->bge_rx_saved_considx = 0; 5565 5566 /* Init TX ring. */ 5567 bge_init_tx_ring(sc); 5568 5569 /* 5718 step 63, 57XX step 94 */ 5570 /* Enable TX MAC state machine lockup fix. */ 5571 mode = CSR_READ_4(sc, BGE_TX_MODE); 5572 if (BGE_IS_5755_PLUS(sc) || 5573 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5574 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5575 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5576 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5577 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5578 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5579 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5580 } 5581 5582 /* Turn on transmitter */ 5583 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5584 /* 5718 step 64 */ 5585 DELAY(100); 5586 5587 /* 5718 step 65, 57XX step 95 */ 5588 /* Turn on receiver */ 5589 mode = CSR_READ_4(sc, BGE_RX_MODE); 5590 if (BGE_IS_5755_PLUS(sc)) 5591 mode |= BGE_RXMODE_IPV6_ENABLE; 5592 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5593 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5594 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5595 /* 5718 step 66 */ 5596 DELAY(10); 5597 5598 /* 5718 step 12, 57XX step 37 */ 5599 /* 5600 * XXX Doucments of 5718 series and 577xx say the recommended value 5601 * is 1, but tg3 set 1 only on 57765 series. 5602 */ 5603 if (BGE_IS_57765_PLUS(sc)) 5604 reg = 1; 5605 else 5606 reg = 2; 5607 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5608 5609 /* Tell firmware we're alive. */ 5610 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5611 5612 /* Enable host interrupts. */ 5613 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5614 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5615 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5616 5617 if ((error = bge_ifmedia_upd(ifp)) != 0) 5618 goto out; 5619 5620 ifp->if_flags |= IFF_RUNNING; 5621 ifp->if_flags &= ~IFF_OACTIVE; 5622 5623 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 5624 5625 out: 5626 sc->bge_if_flags = ifp->if_flags; 5627 splx(s); 5628 5629 return error; 5630 } 5631 5632 /* 5633 * Set media options. 5634 */ 5635 static int 5636 bge_ifmedia_upd(struct ifnet *ifp) 5637 { 5638 struct bge_softc *sc = ifp->if_softc; 5639 struct mii_data *mii = &sc->bge_mii; 5640 struct ifmedia *ifm = &sc->bge_ifmedia; 5641 int rc; 5642 5643 /* If this is a 1000baseX NIC, enable the TBI port. */ 5644 if (sc->bge_flags & BGEF_FIBER_TBI) { 5645 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5646 return EINVAL; 5647 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5648 case IFM_AUTO: 5649 /* 5650 * The BCM5704 ASIC appears to have a special 5651 * mechanism for programming the autoneg 5652 * advertisement registers in TBI mode. 5653 */ 5654 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5655 uint32_t sgdig; 5656 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5657 if (sgdig & BGE_SGDIGSTS_DONE) { 5658 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5659 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5660 sgdig |= BGE_SGDIGCFG_AUTO | 5661 BGE_SGDIGCFG_PAUSE_CAP | 5662 BGE_SGDIGCFG_ASYM_PAUSE; 5663 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5664 sgdig | BGE_SGDIGCFG_SEND); 5665 DELAY(5); 5666 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5667 sgdig); 5668 } 5669 } 5670 break; 5671 case IFM_1000_SX: 5672 if ((ifm->ifm_media & IFM_FDX) != 0) { 5673 BGE_CLRBIT(sc, BGE_MAC_MODE, 5674 BGE_MACMODE_HALF_DUPLEX); 5675 } else { 5676 BGE_SETBIT(sc, BGE_MAC_MODE, 5677 BGE_MACMODE_HALF_DUPLEX); 5678 } 5679 DELAY(40); 5680 break; 5681 default: 5682 return EINVAL; 5683 } 5684 /* XXX 802.3x flow control for 1000BASE-SX */ 5685 return 0; 5686 } 5687 5688 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5689 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5690 uint32_t reg; 5691 5692 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5693 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5694 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5695 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5696 } 5697 } 5698 5699 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5700 if ((rc = mii_mediachg(mii)) == ENXIO) 5701 return 0; 5702 5703 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5704 uint32_t reg; 5705 5706 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5707 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5708 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5709 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5710 delay(40); 5711 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5712 } 5713 } 5714 5715 /* 5716 * Force an interrupt so that we will call bge_link_upd 5717 * if needed and clear any pending link state attention. 5718 * Without this we are not getting any further interrupts 5719 * for link state changes and thus will not UP the link and 5720 * not be able to send in bge_start. The only way to get 5721 * things working was to receive a packet and get a RX intr. 5722 */ 5723 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5724 sc->bge_flags & BGEF_IS_5788) 5725 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5726 else 5727 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5728 5729 return rc; 5730 } 5731 5732 /* 5733 * Report current media status. 5734 */ 5735 static void 5736 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5737 { 5738 struct bge_softc *sc = ifp->if_softc; 5739 struct mii_data *mii = &sc->bge_mii; 5740 5741 if (sc->bge_flags & BGEF_FIBER_TBI) { 5742 ifmr->ifm_status = IFM_AVALID; 5743 ifmr->ifm_active = IFM_ETHER; 5744 if (CSR_READ_4(sc, BGE_MAC_STS) & 5745 BGE_MACSTAT_TBI_PCS_SYNCHED) 5746 ifmr->ifm_status |= IFM_ACTIVE; 5747 ifmr->ifm_active |= IFM_1000_SX; 5748 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5749 ifmr->ifm_active |= IFM_HDX; 5750 else 5751 ifmr->ifm_active |= IFM_FDX; 5752 return; 5753 } 5754 5755 mii_pollstat(mii); 5756 ifmr->ifm_status = mii->mii_media_status; 5757 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5758 sc->bge_flowflags; 5759 } 5760 5761 static int 5762 bge_ifflags_cb(struct ethercom *ec) 5763 { 5764 struct ifnet *ifp = &ec->ec_if; 5765 struct bge_softc *sc = ifp->if_softc; 5766 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5767 5768 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 5769 return ENETRESET; 5770 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5771 return 0; 5772 5773 if ((ifp->if_flags & IFF_PROMISC) == 0) 5774 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5775 else 5776 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5777 5778 bge_setmulti(sc); 5779 5780 sc->bge_if_flags = ifp->if_flags; 5781 return 0; 5782 } 5783 5784 static int 5785 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5786 { 5787 struct bge_softc *sc = ifp->if_softc; 5788 struct ifreq *ifr = (struct ifreq *) data; 5789 int s, error = 0; 5790 struct mii_data *mii; 5791 5792 s = splnet(); 5793 5794 switch (command) { 5795 case SIOCSIFMEDIA: 5796 /* XXX Flow control is not supported for 1000BASE-SX */ 5797 if (sc->bge_flags & BGEF_FIBER_TBI) { 5798 ifr->ifr_media &= ~IFM_ETH_FMASK; 5799 sc->bge_flowflags = 0; 5800 } 5801 5802 /* Flow control requires full-duplex mode. */ 5803 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5804 (ifr->ifr_media & IFM_FDX) == 0) { 5805 ifr->ifr_media &= ~IFM_ETH_FMASK; 5806 } 5807 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5808 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5809 /* We can do both TXPAUSE and RXPAUSE. */ 5810 ifr->ifr_media |= 5811 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5812 } 5813 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5814 } 5815 5816 if (sc->bge_flags & BGEF_FIBER_TBI) { 5817 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5818 command); 5819 } else { 5820 mii = &sc->bge_mii; 5821 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5822 command); 5823 } 5824 break; 5825 default: 5826 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5827 break; 5828 5829 error = 0; 5830 5831 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5832 ; 5833 else if (ifp->if_flags & IFF_RUNNING) 5834 bge_setmulti(sc); 5835 break; 5836 } 5837 5838 splx(s); 5839 5840 return error; 5841 } 5842 5843 static void 5844 bge_watchdog(struct ifnet *ifp) 5845 { 5846 struct bge_softc *sc; 5847 uint32_t status; 5848 5849 sc = ifp->if_softc; 5850 5851 /* If pause frames are active then don't reset the hardware. */ 5852 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5853 status = CSR_READ_4(sc, BGE_RX_STS); 5854 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5855 /* 5856 * If link partner has us in XOFF state then wait for 5857 * the condition to clear. 5858 */ 5859 CSR_WRITE_4(sc, BGE_RX_STS, status); 5860 ifp->if_timer = 5; 5861 return; 5862 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5863 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5864 /* 5865 * If link partner has us in XOFF state then wait for 5866 * the condition to clear. 5867 */ 5868 CSR_WRITE_4(sc, BGE_RX_STS, status); 5869 ifp->if_timer = 5; 5870 return; 5871 } 5872 /* 5873 * Any other condition is unexpected and the controller 5874 * should be reset. 5875 */ 5876 } 5877 5878 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5879 5880 ifp->if_flags &= ~IFF_RUNNING; 5881 bge_init(ifp); 5882 5883 ifp->if_oerrors++; 5884 } 5885 5886 static void 5887 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5888 { 5889 int i; 5890 5891 BGE_CLRBIT_FLUSH(sc, reg, bit); 5892 5893 for (i = 0; i < 1000; i++) { 5894 delay(100); 5895 if ((CSR_READ_4(sc, reg) & bit) == 0) 5896 return; 5897 } 5898 5899 /* 5900 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5901 * on some environment (and once after boot?) 5902 */ 5903 if (reg != BGE_SRS_MODE) 5904 aprint_error_dev(sc->bge_dev, 5905 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5906 (u_long)reg, bit); 5907 } 5908 5909 /* 5910 * Stop the adapter and free any mbufs allocated to the 5911 * RX and TX lists. 5912 */ 5913 static void 5914 bge_stop(struct ifnet *ifp, int disable) 5915 { 5916 struct bge_softc *sc = ifp->if_softc; 5917 5918 if (disable) { 5919 sc->bge_detaching = 1; 5920 callout_halt(&sc->bge_timeout, NULL); 5921 } else 5922 callout_stop(&sc->bge_timeout); 5923 5924 /* Disable host interrupts. */ 5925 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5926 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5927 5928 /* 5929 * Tell firmware we're shutting down. 5930 */ 5931 bge_stop_fw(sc); 5932 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5933 5934 /* 5935 * Disable all of the receiver blocks. 5936 */ 5937 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5938 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5939 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5940 if (BGE_IS_5700_FAMILY(sc)) 5941 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5942 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5943 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5944 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5945 5946 /* 5947 * Disable all of the transmit blocks. 5948 */ 5949 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5950 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5951 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5952 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5953 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5954 if (BGE_IS_5700_FAMILY(sc)) 5955 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5956 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5957 5958 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 5959 delay(40); 5960 5961 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 5962 5963 /* 5964 * Shut down all of the memory managers and related 5965 * state machines. 5966 */ 5967 /* 5718 step 5a,5b */ 5968 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5969 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5970 if (BGE_IS_5700_FAMILY(sc)) 5971 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5972 5973 /* 5718 step 5c,5d */ 5974 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5975 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5976 5977 if (BGE_IS_5700_FAMILY(sc)) { 5978 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5979 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5980 } 5981 5982 bge_reset(sc); 5983 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5984 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5985 5986 /* 5987 * Keep the ASF firmware running if up. 5988 */ 5989 if (sc->bge_asf_mode & ASF_STACKUP) 5990 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5991 else 5992 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5993 5994 /* Free the RX lists. */ 5995 bge_free_rx_ring_std(sc, disable); 5996 5997 /* Free jumbo RX list. */ 5998 if (BGE_IS_JUMBO_CAPABLE(sc)) 5999 bge_free_rx_ring_jumbo(sc); 6000 6001 /* Free TX buffers. */ 6002 bge_free_tx_ring(sc, disable); 6003 6004 /* 6005 * Isolate/power down the PHY. 6006 */ 6007 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6008 mii_down(&sc->bge_mii); 6009 6010 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6011 6012 /* Clear MAC's link state (PHY may still have link UP). */ 6013 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6014 6015 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6016 } 6017 6018 static void 6019 bge_link_upd(struct bge_softc *sc) 6020 { 6021 struct ifnet *ifp = &sc->ethercom.ec_if; 6022 struct mii_data *mii = &sc->bge_mii; 6023 uint32_t status; 6024 uint16_t phyval; 6025 int link; 6026 6027 /* Clear 'pending link event' flag */ 6028 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6029 6030 /* 6031 * Process link state changes. 6032 * Grrr. The link status word in the status block does 6033 * not work correctly on the BCM5700 rev AX and BX chips, 6034 * according to all available information. Hence, we have 6035 * to enable MII interrupts in order to properly obtain 6036 * async link changes. Unfortunately, this also means that 6037 * we have to read the MAC status register to detect link 6038 * changes, thereby adding an additional register access to 6039 * the interrupt handler. 6040 */ 6041 6042 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6043 status = CSR_READ_4(sc, BGE_MAC_STS); 6044 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6045 mii_pollstat(mii); 6046 6047 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6048 mii->mii_media_status & IFM_ACTIVE && 6049 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6050 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6051 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6052 (!(mii->mii_media_status & IFM_ACTIVE) || 6053 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6054 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6055 6056 /* Clear the interrupt */ 6057 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6058 BGE_EVTENB_MI_INTERRUPT); 6059 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6060 BRGPHY_MII_ISR, &phyval); 6061 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6062 BRGPHY_MII_IMR, BRGPHY_INTRS); 6063 } 6064 return; 6065 } 6066 6067 if (sc->bge_flags & BGEF_FIBER_TBI) { 6068 status = CSR_READ_4(sc, BGE_MAC_STS); 6069 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6070 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6071 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6072 if (BGE_ASICREV(sc->bge_chipid) 6073 == BGE_ASICREV_BCM5704) { 6074 BGE_CLRBIT(sc, BGE_MAC_MODE, 6075 BGE_MACMODE_TBI_SEND_CFGS); 6076 DELAY(40); 6077 } 6078 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6079 if_link_state_change(ifp, LINK_STATE_UP); 6080 } 6081 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6082 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6083 if_link_state_change(ifp, LINK_STATE_DOWN); 6084 } 6085 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6086 /* 6087 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6088 * bit in status word always set. Workaround this bug by 6089 * reading PHY link status directly. 6090 */ 6091 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6092 BGE_STS_LINK : 0; 6093 6094 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6095 mii_pollstat(mii); 6096 6097 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6098 mii->mii_media_status & IFM_ACTIVE && 6099 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6100 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6101 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6102 (!(mii->mii_media_status & IFM_ACTIVE) || 6103 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6104 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6105 } 6106 } else { 6107 /* 6108 * For controllers that call mii_tick, we have to poll 6109 * link status. 6110 */ 6111 mii_pollstat(mii); 6112 } 6113 6114 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6115 uint32_t reg, scale; 6116 6117 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6118 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6119 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6120 scale = 65; 6121 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6122 scale = 6; 6123 else 6124 scale = 12; 6125 6126 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6127 ~BGE_MISCCFG_TIMER_PRESCALER; 6128 reg |= scale << 1; 6129 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6130 } 6131 /* Clear the attention */ 6132 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6133 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6134 BGE_MACSTAT_LINK_CHANGED); 6135 } 6136 6137 static int 6138 bge_sysctl_verify(SYSCTLFN_ARGS) 6139 { 6140 int error, t; 6141 struct sysctlnode node; 6142 6143 node = *rnode; 6144 t = *(int*)rnode->sysctl_data; 6145 node.sysctl_data = &t; 6146 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6147 if (error || newp == NULL) 6148 return error; 6149 6150 #if 0 6151 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6152 node.sysctl_num, rnode->sysctl_num)); 6153 #endif 6154 6155 if (node.sysctl_num == bge_rxthresh_nodenum) { 6156 if (t < 0 || t >= NBGE_RX_THRESH) 6157 return EINVAL; 6158 bge_update_all_threshes(t); 6159 } else 6160 return EINVAL; 6161 6162 *(int*)rnode->sysctl_data = t; 6163 6164 return 0; 6165 } 6166 6167 /* 6168 * Set up sysctl(3) MIB, hw.bge.*. 6169 */ 6170 static void 6171 bge_sysctl_init(struct bge_softc *sc) 6172 { 6173 int rc, bge_root_num; 6174 const struct sysctlnode *node; 6175 6176 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6177 0, CTLTYPE_NODE, "bge", 6178 SYSCTL_DESCR("BGE interface controls"), 6179 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6180 goto out; 6181 } 6182 6183 bge_root_num = node->sysctl_num; 6184 6185 /* BGE Rx interrupt mitigation level */ 6186 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6187 CTLFLAG_READWRITE, 6188 CTLTYPE_INT, "rx_lvl", 6189 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6190 bge_sysctl_verify, 0, 6191 &bge_rx_thresh_lvl, 6192 0, CTL_HW, bge_root_num, CTL_CREATE, 6193 CTL_EOL)) != 0) { 6194 goto out; 6195 } 6196 6197 bge_rxthresh_nodenum = node->sysctl_num; 6198 6199 return; 6200 6201 out: 6202 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6203 } 6204 6205 #ifdef BGE_DEBUG 6206 void 6207 bge_debug_info(struct bge_softc *sc) 6208 { 6209 6210 printf("Hardware Flags:\n"); 6211 if (BGE_IS_57765_PLUS(sc)) 6212 printf(" - 57765 Plus\n"); 6213 if (BGE_IS_5717_PLUS(sc)) 6214 printf(" - 5717 Plus\n"); 6215 if (BGE_IS_5755_PLUS(sc)) 6216 printf(" - 5755 Plus\n"); 6217 if (BGE_IS_575X_PLUS(sc)) 6218 printf(" - 575X Plus\n"); 6219 if (BGE_IS_5705_PLUS(sc)) 6220 printf(" - 5705 Plus\n"); 6221 if (BGE_IS_5714_FAMILY(sc)) 6222 printf(" - 5714 Family\n"); 6223 if (BGE_IS_5700_FAMILY(sc)) 6224 printf(" - 5700 Family\n"); 6225 if (sc->bge_flags & BGEF_IS_5788) 6226 printf(" - 5788\n"); 6227 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6228 printf(" - Supports Jumbo Frames\n"); 6229 if (sc->bge_flags & BGEF_NO_EEPROM) 6230 printf(" - No EEPROM\n"); 6231 if (sc->bge_flags & BGEF_PCIX) 6232 printf(" - PCI-X Bus\n"); 6233 if (sc->bge_flags & BGEF_PCIE) 6234 printf(" - PCI Express Bus\n"); 6235 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6236 printf(" - RX Alignment Bug\n"); 6237 if (sc->bge_flags & BGEF_APE) 6238 printf(" - APE\n"); 6239 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6240 printf(" - CPMU\n"); 6241 if (sc->bge_flags & BGEF_TSO) 6242 printf(" - TSO\n"); 6243 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6244 printf(" - TAGGED_STATUS\n"); 6245 6246 /* PHY related */ 6247 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6248 printf(" - No 3 LEDs\n"); 6249 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6250 printf(" - CRC bug\n"); 6251 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6252 printf(" - ADC bug\n"); 6253 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6254 printf(" - 5704 A0 bug\n"); 6255 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6256 printf(" - jitter bug\n"); 6257 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6258 printf(" - BER bug\n"); 6259 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6260 printf(" - adjust trim\n"); 6261 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6262 printf(" - no wirespeed\n"); 6263 6264 /* ASF related */ 6265 if (sc->bge_asf_mode & ASF_ENABLE) 6266 printf(" - ASF enable\n"); 6267 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6268 printf(" - ASF new handshake\n"); 6269 if (sc->bge_asf_mode & ASF_STACKUP) 6270 printf(" - ASF stackup\n"); 6271 } 6272 #endif /* BGE_DEBUG */ 6273 6274 static int 6275 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6276 { 6277 prop_dictionary_t dict; 6278 prop_data_t ea; 6279 6280 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6281 return 1; 6282 6283 dict = device_properties(sc->bge_dev); 6284 ea = prop_dictionary_get(dict, "mac-address"); 6285 if (ea != NULL) { 6286 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6287 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6288 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 6289 return 0; 6290 } 6291 6292 return 1; 6293 } 6294 6295 static int 6296 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6297 { 6298 uint32_t mac_addr; 6299 6300 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6301 if ((mac_addr >> 16) == 0x484b) { 6302 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6303 ether_addr[1] = (uint8_t)mac_addr; 6304 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6305 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6306 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6307 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6308 ether_addr[5] = (uint8_t)mac_addr; 6309 return 0; 6310 } 6311 return 1; 6312 } 6313 6314 static int 6315 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6316 { 6317 int mac_offset = BGE_EE_MAC_OFFSET; 6318 6319 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6320 mac_offset = BGE_EE_MAC_OFFSET_5906; 6321 6322 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6323 ETHER_ADDR_LEN)); 6324 } 6325 6326 static int 6327 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6328 { 6329 6330 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6331 return 1; 6332 6333 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6334 ETHER_ADDR_LEN)); 6335 } 6336 6337 static int 6338 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6339 { 6340 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6341 /* NOTE: Order is critical */ 6342 bge_get_eaddr_fw, 6343 bge_get_eaddr_mem, 6344 bge_get_eaddr_nvram, 6345 bge_get_eaddr_eeprom, 6346 NULL 6347 }; 6348 const bge_eaddr_fcn_t *func; 6349 6350 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6351 if ((*func)(sc, eaddr) == 0) 6352 break; 6353 } 6354 return (*func == NULL ? ENXIO : 0); 6355 } 6356
Indexes created Tue Sep 23 22:09:46 GMT 2025