if_bge.c revision 1.355
1 /* $NetBSD: if_bge.c,v 1.355 2022/06/30 16:36:11 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.355 2022/06/30 16:36:11 skrll Exp $"); 83 84 #include <sys/param.h> 85 86 #include <sys/callout.h> 87 #include <sys/device.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/kernel.h> 91 #include <sys/rndsource.h> 92 #include <sys/socket.h> 93 #include <sys/sockio.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 #include <net/bpf.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 #include <dev/mii/miidevs.h> 123 #include <dev/mii/brgphyreg.h> 124 125 #include <dev/pci/if_bgereg.h> 126 #include <dev/pci/if_bgevar.h> 127 128 #include <prop/proplib.h> 129 130 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 131 132 133 /* 134 * Tunable thresholds for rx-side bge interrupt mitigation. 135 */ 136 137 /* 138 * The pairs of values below were obtained from empirical measurement 139 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 140 * interrupt for every N packets received, where N is, approximately, 141 * the second value (rx_max_bds) in each pair. The values are chosen 142 * such that moving from one pair to the succeeding pair was observed 143 * to roughly halve interrupt rate under sustained input packet load. 144 * The values were empirically chosen to avoid overflowing internal 145 * limits on the bcm5700: increasing rx_ticks much beyond 600 146 * results in internal wrapping and higher interrupt rates. 147 * The limit of 46 frames was chosen to match NFS workloads. 148 * 149 * These values also work well on bcm5701, bcm5704C, and (less 150 * tested) bcm5703. On other chipsets, (including the Altima chip 151 * family), the larger values may overflow internal chip limits, 152 * leading to increasing interrupt rates rather than lower interrupt 153 * rates. 154 * 155 * Applications using heavy interrupt mitigation (interrupting every 156 * 32 or 46 frames) in both directions may need to increase the TCP 157 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 158 * full link bandwidth, due to ACKs and window updates lingering 159 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 160 */ 161 static const struct bge_load_rx_thresh { 162 int rx_ticks; 163 int rx_max_bds; } 164 bge_rx_threshes[] = { 165 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 166 { 32, 2 }, 167 { 50, 4 }, 168 { 100, 8 }, 169 { 192, 16 }, 170 { 416, 32 }, 171 { 598, 46 } 172 }; 173 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 174 175 /* XXX patchable; should be sysctl'able */ 176 static int bge_auto_thresh = 1; 177 static int bge_rx_thresh_lvl; 178 179 static int bge_rxthresh_nodenum; 180 181 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 182 183 static uint32_t bge_chipid(const struct pci_attach_args *); 184 static int bge_can_use_msi(struct bge_softc *); 185 static int bge_probe(device_t, cfdata_t, void *); 186 static void bge_attach(device_t, device_t, void *); 187 static int bge_detach(device_t, int); 188 static void bge_release_resources(struct bge_softc *); 189 190 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 191 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 195 196 static void bge_txeof(struct bge_softc *); 197 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *m, bool); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_phy_addr(struct bge_softc *); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writembx_flush(struct bge_softc *, int, int); 247 static void bge_writemem_direct(struct bge_softc *, int, int); 248 static void bge_writereg_ind(struct bge_softc *, int, int); 249 static void bge_set_max_readrq(struct bge_softc *); 250 251 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 252 static int bge_miibus_writereg(device_t, int, int, uint16_t); 253 static void bge_miibus_statchg(struct ifnet *); 254 255 #define BGE_RESET_SHUTDOWN 0 256 #define BGE_RESET_START 1 257 #define BGE_RESET_SUSPEND 2 258 static void bge_sig_post_reset(struct bge_softc *, int); 259 static void bge_sig_legacy(struct bge_softc *, int); 260 static void bge_sig_pre_reset(struct bge_softc *, int); 261 static void bge_wait_for_event_ack(struct bge_softc *); 262 static void bge_stop_fw(struct bge_softc *); 263 static int bge_reset(struct bge_softc *); 264 static void bge_link_upd(struct bge_softc *); 265 static void bge_sysctl_init(struct bge_softc *); 266 static int bge_sysctl_verify(SYSCTLFN_PROTO); 267 268 static void bge_ape_lock_init(struct bge_softc *); 269 static void bge_ape_read_fw_ver(struct bge_softc *); 270 static int bge_ape_lock(struct bge_softc *, int); 271 static void bge_ape_unlock(struct bge_softc *, int); 272 static void bge_ape_send_event(struct bge_softc *, uint32_t); 273 static void bge_ape_driver_state_change(struct bge_softc *, int); 274 275 #ifdef BGE_DEBUG 276 #define DPRINTF(x) if (bgedebug) printf x 277 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 278 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 279 int bgedebug = 0; 280 int bge_tso_debug = 0; 281 void bge_debug_info(struct bge_softc *); 282 #else 283 #define DPRINTF(x) 284 #define DPRINTFN(n, x) 285 #define BGE_TSO_PRINTF(x) 286 #endif 287 288 #ifdef BGE_EVENT_COUNTERS 289 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 290 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 291 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 292 #else 293 #define BGE_EVCNT_INCR(ev) /* nothing */ 294 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 295 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 296 #endif 297 298 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 299 /* 300 * The BCM5700 documentation seems to indicate that the hardware still has the 301 * Alteon vendor ID burned into it, though it should always be overridden by 302 * the value in the EEPROM. We'll check for it anyway. 303 */ 304 static const struct bge_product { 305 pci_vendor_id_t bp_vendor; 306 pci_product_id_t bp_product; 307 const char *bp_name; 308 } bge_products[] = { 309 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 310 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 311 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 312 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 313 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 314 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 315 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 319 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 320 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 323 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 349 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 354 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 359 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 363 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 364 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 367 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 368 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 370 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 371 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 372 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 373 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 375 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 376 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 377 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 379 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 380 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 381 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 382 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 383 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 384 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 399 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 400 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 401 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 402 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 403 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 404 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 405 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 406 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 407 { 0, 0, NULL }, 408 }; 409 410 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 411 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 412 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 413 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 414 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 415 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 416 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 417 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 418 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 419 420 static const struct bge_revision { 421 uint32_t br_chipid; 422 const char *br_name; 423 } bge_revisions[] = { 424 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 425 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 426 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 427 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 428 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 429 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 430 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 431 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 432 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 433 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 434 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 435 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 436 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 437 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 438 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 439 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 440 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 441 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 442 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 443 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 444 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 445 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 446 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 447 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 448 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 449 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 450 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 451 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 452 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 453 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 454 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 455 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 456 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 457 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 458 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 459 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 460 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 461 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 462 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 463 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 464 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 465 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 466 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 467 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 468 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 469 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 470 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 471 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 472 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 473 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 474 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 475 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 476 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 477 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 478 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 479 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 480 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 481 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 482 /* 5754 and 5787 share the same ASIC ID */ 483 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 484 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 485 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 486 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 487 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 488 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 489 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 490 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 491 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 492 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 493 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 494 495 { 0, NULL } 496 }; 497 498 /* 499 * Some defaults for major revisions, so that newer steppings 500 * that we don't know about have a shot at working. 501 */ 502 static const struct bge_revision bge_majorrevs[] = { 503 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 504 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 505 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 506 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 507 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 508 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 509 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 510 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 511 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 512 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 513 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 514 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 515 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 516 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 517 /* 5754 and 5787 share the same ASIC ID */ 518 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 519 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 520 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 521 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 522 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 523 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 524 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 525 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 526 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 527 528 { 0, NULL } 529 }; 530 531 static int bge_allow_asf = 1; 532 533 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 534 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 535 536 static uint32_t 537 bge_readmem_ind(struct bge_softc *sc, int off) 538 { 539 pcireg_t val; 540 541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 542 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 543 return 0; 544 545 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 546 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 547 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 548 return val; 549 } 550 551 static void 552 bge_writemem_ind(struct bge_softc *sc, int off, int val) 553 { 554 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 556 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 557 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 558 } 559 560 /* 561 * PCI Express only 562 */ 563 static void 564 bge_set_max_readrq(struct bge_softc *sc) 565 { 566 pcireg_t val; 567 568 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 569 + PCIE_DCSR); 570 val &= ~PCIE_DCSR_MAX_READ_REQ; 571 switch (sc->bge_expmrq) { 572 case 2048: 573 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 574 break; 575 case 4096: 576 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 577 break; 578 default: 579 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 580 break; 581 } 582 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 583 + PCIE_DCSR, val); 584 } 585 586 #ifdef notdef 587 static uint32_t 588 bge_readreg_ind(struct bge_softc *sc, int off) 589 { 590 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 591 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 592 } 593 #endif 594 595 static void 596 bge_writereg_ind(struct bge_softc *sc, int off, int val) 597 { 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 599 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 600 } 601 602 static void 603 bge_writemem_direct(struct bge_softc *sc, int off, int val) 604 { 605 CSR_WRITE_4(sc, off, val); 606 } 607 608 static void 609 bge_writembx(struct bge_softc *sc, int off, int val) 610 { 611 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 612 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 613 614 CSR_WRITE_4(sc, off, val); 615 } 616 617 static void 618 bge_writembx_flush(struct bge_softc *sc, int off, int val) 619 { 620 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 621 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 622 623 CSR_WRITE_4_FLUSH(sc, off, val); 624 } 625 626 /* 627 * Clear all stale locks and select the lock for this driver instance. 628 */ 629 void 630 bge_ape_lock_init(struct bge_softc *sc) 631 { 632 struct pci_attach_args *pa = &(sc->bge_pa); 633 uint32_t bit, regbase; 634 int i; 635 636 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 637 regbase = BGE_APE_LOCK_GRANT; 638 else 639 regbase = BGE_APE_PER_LOCK_GRANT; 640 641 /* Clear any stale locks. */ 642 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 643 switch (i) { 644 case BGE_APE_LOCK_PHY0: 645 case BGE_APE_LOCK_PHY1: 646 case BGE_APE_LOCK_PHY2: 647 case BGE_APE_LOCK_PHY3: 648 bit = BGE_APE_LOCK_GRANT_DRIVER0; 649 break; 650 default: 651 if (pa->pa_function == 0) 652 bit = BGE_APE_LOCK_GRANT_DRIVER0; 653 else 654 bit = (1 << pa->pa_function); 655 } 656 APE_WRITE_4(sc, regbase + 4 * i, bit); 657 } 658 659 /* Select the PHY lock based on the device's function number. */ 660 switch (pa->pa_function) { 661 case 0: 662 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 663 break; 664 case 1: 665 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 666 break; 667 case 2: 668 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 669 break; 670 case 3: 671 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 672 break; 673 default: 674 printf("%s: PHY lock not supported on function\n", 675 device_xname(sc->bge_dev)); 676 break; 677 } 678 } 679 680 /* 681 * Check for APE firmware, set flags, and print version info. 682 */ 683 void 684 bge_ape_read_fw_ver(struct bge_softc *sc) 685 { 686 const char *fwtype; 687 uint32_t apedata, features; 688 689 /* Check for a valid APE signature in shared memory. */ 690 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 691 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 692 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 693 return; 694 } 695 696 /* Check if APE firmware is running. */ 697 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 698 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 699 printf("%s: APE signature found but FW status not ready! " 700 "0x%08x\n", device_xname(sc->bge_dev), apedata); 701 return; 702 } 703 704 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 705 706 /* Fetch the APE firwmare type and version. */ 707 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 708 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 709 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 710 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 711 fwtype = "NCSI"; 712 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 713 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 714 fwtype = "DASH"; 715 } else 716 fwtype = "UNKN"; 717 718 /* Print the APE firmware version. */ 719 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 720 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 721 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 722 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 723 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 724 } 725 726 int 727 bge_ape_lock(struct bge_softc *sc, int locknum) 728 { 729 struct pci_attach_args *pa = &(sc->bge_pa); 730 uint32_t bit, gnt, req, status; 731 int i, off; 732 733 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 734 return (0); 735 736 /* Lock request/grant registers have different bases. */ 737 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 738 req = BGE_APE_LOCK_REQ; 739 gnt = BGE_APE_LOCK_GRANT; 740 } else { 741 req = BGE_APE_PER_LOCK_REQ; 742 gnt = BGE_APE_PER_LOCK_GRANT; 743 } 744 745 off = 4 * locknum; 746 747 switch (locknum) { 748 case BGE_APE_LOCK_GPIO: 749 /* Lock required when using GPIO. */ 750 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 751 return (0); 752 if (pa->pa_function == 0) 753 bit = BGE_APE_LOCK_REQ_DRIVER0; 754 else 755 bit = (1 << pa->pa_function); 756 break; 757 case BGE_APE_LOCK_GRC: 758 /* Lock required to reset the device. */ 759 if (pa->pa_function == 0) 760 bit = BGE_APE_LOCK_REQ_DRIVER0; 761 else 762 bit = (1 << pa->pa_function); 763 break; 764 case BGE_APE_LOCK_MEM: 765 /* Lock required when accessing certain APE memory. */ 766 if (pa->pa_function == 0) 767 bit = BGE_APE_LOCK_REQ_DRIVER0; 768 else 769 bit = (1 << pa->pa_function); 770 break; 771 case BGE_APE_LOCK_PHY0: 772 case BGE_APE_LOCK_PHY1: 773 case BGE_APE_LOCK_PHY2: 774 case BGE_APE_LOCK_PHY3: 775 /* Lock required when accessing PHYs. */ 776 bit = BGE_APE_LOCK_REQ_DRIVER0; 777 break; 778 default: 779 return (EINVAL); 780 } 781 782 /* Request a lock. */ 783 APE_WRITE_4_FLUSH(sc, req + off, bit); 784 785 /* Wait up to 1 second to acquire lock. */ 786 for (i = 0; i < 20000; i++) { 787 status = APE_READ_4(sc, gnt + off); 788 if (status == bit) 789 break; 790 DELAY(50); 791 } 792 793 /* Handle any errors. */ 794 if (status != bit) { 795 printf("%s: APE lock %d request failed! " 796 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 797 device_xname(sc->bge_dev), 798 locknum, req + off, bit & 0xFFFF, gnt + off, 799 status & 0xFFFF); 800 /* Revoke the lock request. */ 801 APE_WRITE_4(sc, gnt + off, bit); 802 return (EBUSY); 803 } 804 805 return (0); 806 } 807 808 void 809 bge_ape_unlock(struct bge_softc *sc, int locknum) 810 { 811 struct pci_attach_args *pa = &(sc->bge_pa); 812 uint32_t bit, gnt; 813 int off; 814 815 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 816 return; 817 818 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 819 gnt = BGE_APE_LOCK_GRANT; 820 else 821 gnt = BGE_APE_PER_LOCK_GRANT; 822 823 off = 4 * locknum; 824 825 switch (locknum) { 826 case BGE_APE_LOCK_GPIO: 827 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 828 return; 829 if (pa->pa_function == 0) 830 bit = BGE_APE_LOCK_GRANT_DRIVER0; 831 else 832 bit = (1 << pa->pa_function); 833 break; 834 case BGE_APE_LOCK_GRC: 835 if (pa->pa_function == 0) 836 bit = BGE_APE_LOCK_GRANT_DRIVER0; 837 else 838 bit = (1 << pa->pa_function); 839 break; 840 case BGE_APE_LOCK_MEM: 841 if (pa->pa_function == 0) 842 bit = BGE_APE_LOCK_GRANT_DRIVER0; 843 else 844 bit = (1 << pa->pa_function); 845 break; 846 case BGE_APE_LOCK_PHY0: 847 case BGE_APE_LOCK_PHY1: 848 case BGE_APE_LOCK_PHY2: 849 case BGE_APE_LOCK_PHY3: 850 bit = BGE_APE_LOCK_GRANT_DRIVER0; 851 break; 852 default: 853 return; 854 } 855 856 /* Write and flush for consecutive bge_ape_lock() */ 857 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 858 } 859 860 /* 861 * Send an event to the APE firmware. 862 */ 863 void 864 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 865 { 866 uint32_t apedata; 867 int i; 868 869 /* NCSI does not support APE events. */ 870 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 871 return; 872 873 /* Wait up to 1ms for APE to service previous event. */ 874 for (i = 10; i > 0; i--) { 875 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 876 break; 877 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 878 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 879 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 880 BGE_APE_EVENT_STATUS_EVENT_PENDING); 881 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 882 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 883 break; 884 } 885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 886 DELAY(100); 887 } 888 if (i == 0) { 889 printf("%s: APE event 0x%08x send timed out\n", 890 device_xname(sc->bge_dev), event); 891 } 892 } 893 894 void 895 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 896 { 897 uint32_t apedata, event; 898 899 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 900 return; 901 902 switch (kind) { 903 case BGE_RESET_START: 904 /* If this is the first load, clear the load counter. */ 905 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 906 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 907 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 908 else { 909 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 910 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 911 } 912 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 913 BGE_APE_HOST_SEG_SIG_MAGIC); 914 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 915 BGE_APE_HOST_SEG_LEN_MAGIC); 916 917 /* Add some version info if bge(4) supports it. */ 918 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 919 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 920 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 921 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 922 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 923 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 924 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 925 BGE_APE_HOST_DRVR_STATE_START); 926 event = BGE_APE_EVENT_STATUS_STATE_START; 927 break; 928 case BGE_RESET_SHUTDOWN: 929 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 930 BGE_APE_HOST_DRVR_STATE_UNLOAD); 931 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 932 break; 933 case BGE_RESET_SUSPEND: 934 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 935 break; 936 default: 937 return; 938 } 939 940 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 941 BGE_APE_EVENT_STATUS_STATE_CHNGE); 942 } 943 944 static uint8_t 945 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 946 { 947 uint32_t access, byte = 0; 948 int i; 949 950 /* Lock. */ 951 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 952 for (i = 0; i < 8000; i++) { 953 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 954 break; 955 DELAY(20); 956 } 957 if (i == 8000) 958 return 1; 959 960 /* Enable access. */ 961 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 962 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 963 964 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 965 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 966 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 967 DELAY(10); 968 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 969 DELAY(10); 970 break; 971 } 972 } 973 974 if (i == BGE_TIMEOUT * 10) { 975 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 976 return 1; 977 } 978 979 /* Get result. */ 980 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 981 982 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 983 984 /* Disable access. */ 985 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 986 987 /* Unlock. */ 988 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 989 990 return 0; 991 } 992 993 /* 994 * Read a sequence of bytes from NVRAM. 995 */ 996 static int 997 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 998 { 999 int error = 0, i; 1000 uint8_t byte = 0; 1001 1002 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1003 return 1; 1004 1005 for (i = 0; i < cnt; i++) { 1006 error = bge_nvram_getbyte(sc, off + i, &byte); 1007 if (error) 1008 break; 1009 *(dest + i) = byte; 1010 } 1011 1012 return (error ? 1 : 0); 1013 } 1014 1015 /* 1016 * Read a byte of data stored in the EEPROM at address 'addr.' The 1017 * BCM570x supports both the traditional bitbang interface and an 1018 * auto access interface for reading the EEPROM. We use the auto 1019 * access method. 1020 */ 1021 static uint8_t 1022 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1023 { 1024 int i; 1025 uint32_t byte = 0; 1026 1027 /* 1028 * Enable use of auto EEPROM access so we can avoid 1029 * having to use the bitbang method. 1030 */ 1031 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1032 1033 /* Reset the EEPROM, load the clock period. */ 1034 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1035 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1036 DELAY(20); 1037 1038 /* Issue the read EEPROM command. */ 1039 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1040 1041 /* Wait for completion */ 1042 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1043 DELAY(10); 1044 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1045 break; 1046 } 1047 1048 if (i == BGE_TIMEOUT * 10) { 1049 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1050 return 1; 1051 } 1052 1053 /* Get result. */ 1054 byte = CSR_READ_4(sc, BGE_EE_DATA); 1055 1056 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1057 1058 return 0; 1059 } 1060 1061 /* 1062 * Read a sequence of bytes from the EEPROM. 1063 */ 1064 static int 1065 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1066 { 1067 int error = 0, i; 1068 uint8_t byte = 0; 1069 char *dest = destv; 1070 1071 for (i = 0; i < cnt; i++) { 1072 error = bge_eeprom_getbyte(sc, off + i, &byte); 1073 if (error) 1074 break; 1075 *(dest + i) = byte; 1076 } 1077 1078 return (error ? 1 : 0); 1079 } 1080 1081 static int 1082 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1083 { 1084 struct bge_softc * const sc = device_private(dev); 1085 uint32_t data; 1086 uint32_t autopoll; 1087 int rv = 0; 1088 int i; 1089 1090 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1091 return -1; 1092 1093 /* Reading with autopolling on may trigger PCI errors */ 1094 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1095 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1096 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1097 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1098 DELAY(80); 1099 } 1100 1101 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1102 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1103 1104 for (i = 0; i < BGE_TIMEOUT; i++) { 1105 delay(10); 1106 data = CSR_READ_4(sc, BGE_MI_COMM); 1107 if (!(data & BGE_MICOMM_BUSY)) { 1108 DELAY(5); 1109 data = CSR_READ_4(sc, BGE_MI_COMM); 1110 break; 1111 } 1112 } 1113 1114 if (i == BGE_TIMEOUT) { 1115 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1116 rv = ETIMEDOUT; 1117 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1118 /* XXX This error occurs on some devices while attaching. */ 1119 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1120 rv = EIO; 1121 } else 1122 *val = data & BGE_MICOMM_DATA; 1123 1124 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1125 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1126 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1127 DELAY(80); 1128 } 1129 1130 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1131 1132 return rv; 1133 } 1134 1135 static int 1136 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1137 { 1138 struct bge_softc * const sc = device_private(dev); 1139 uint32_t data, autopoll; 1140 int rv = 0; 1141 int i; 1142 1143 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1144 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1145 return 0; 1146 1147 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1148 return -1; 1149 1150 /* Reading with autopolling on may trigger PCI errors */ 1151 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1152 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1153 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1154 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1155 DELAY(80); 1156 } 1157 1158 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1159 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1160 1161 for (i = 0; i < BGE_TIMEOUT; i++) { 1162 delay(10); 1163 data = CSR_READ_4(sc, BGE_MI_COMM); 1164 if (!(data & BGE_MICOMM_BUSY)) { 1165 delay(5); 1166 data = CSR_READ_4(sc, BGE_MI_COMM); 1167 break; 1168 } 1169 } 1170 1171 if (i == BGE_TIMEOUT) { 1172 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1173 rv = ETIMEDOUT; 1174 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1175 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1176 rv = EIO; 1177 } 1178 1179 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1180 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1181 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1182 delay(80); 1183 } 1184 1185 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1186 1187 if (i == BGE_TIMEOUT) { 1188 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1189 return ETIMEDOUT; 1190 } 1191 1192 return rv; 1193 } 1194 1195 static void 1196 bge_miibus_statchg(struct ifnet *ifp) 1197 { 1198 struct bge_softc * const sc = ifp->if_softc; 1199 struct mii_data *mii = &sc->bge_mii; 1200 uint32_t mac_mode, rx_mode, tx_mode; 1201 1202 /* 1203 * Get flow control negotiation result. 1204 */ 1205 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1206 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1207 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1208 1209 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1210 mii->mii_media_status & IFM_ACTIVE && 1211 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1212 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1213 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1214 (!(mii->mii_media_status & IFM_ACTIVE) || 1215 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1216 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1217 1218 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1219 return; 1220 1221 /* Set the port mode (MII/GMII) to match the link speed. */ 1222 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1223 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1224 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1225 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1226 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1227 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1228 mac_mode |= BGE_PORTMODE_GMII; 1229 else 1230 mac_mode |= BGE_PORTMODE_MII; 1231 1232 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1233 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1234 if ((mii->mii_media_active & IFM_FDX) != 0) { 1235 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1236 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1237 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1238 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1239 } else 1240 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1241 1242 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1243 DELAY(40); 1244 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1245 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1246 } 1247 1248 /* 1249 * Update rx threshold levels to values in a particular slot 1250 * of the interrupt-mitigation table bge_rx_threshes. 1251 */ 1252 static void 1253 bge_set_thresh(struct ifnet *ifp, int lvl) 1254 { 1255 struct bge_softc * const sc = ifp->if_softc; 1256 int s; 1257 1258 /* For now, just save the new Rx-intr thresholds and record 1259 * that a threshold update is pending. Updating the hardware 1260 * registers here (even at splhigh()) is observed to 1261 * occasionally cause glitches where Rx-interrupts are not 1262 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1263 */ 1264 s = splnet(); 1265 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1266 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1267 sc->bge_pending_rxintr_change = 1; 1268 splx(s); 1269 } 1270 1271 1272 /* 1273 * Update Rx thresholds of all bge devices 1274 */ 1275 static void 1276 bge_update_all_threshes(int lvl) 1277 { 1278 struct ifnet *ifp; 1279 const char * const namebuf = "bge"; 1280 int namelen; 1281 int s; 1282 1283 if (lvl < 0) 1284 lvl = 0; 1285 else if (lvl >= NBGE_RX_THRESH) 1286 lvl = NBGE_RX_THRESH - 1; 1287 1288 namelen = strlen(namebuf); 1289 /* 1290 * Now search all the interfaces for this name/number 1291 */ 1292 s = pserialize_read_enter(); 1293 IFNET_READER_FOREACH(ifp) { 1294 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1295 continue; 1296 /* We got a match: update if doing auto-threshold-tuning */ 1297 if (bge_auto_thresh) 1298 bge_set_thresh(ifp, lvl); 1299 } 1300 pserialize_read_exit(s); 1301 } 1302 1303 /* 1304 * Handle events that have triggered interrupts. 1305 */ 1306 static void 1307 bge_handle_events(struct bge_softc *sc) 1308 { 1309 1310 return; 1311 } 1312 1313 /* 1314 * Memory management for jumbo frames. 1315 */ 1316 1317 static int 1318 bge_alloc_jumbo_mem(struct bge_softc *sc) 1319 { 1320 char *ptr, *kva; 1321 bus_dma_segment_t seg; 1322 int i, rseg, state, error; 1323 struct bge_jpool_entry *entry; 1324 1325 state = error = 0; 1326 1327 /* Grab a big chunk o' storage. */ 1328 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1329 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1330 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1331 return ENOBUFS; 1332 } 1333 1334 state = 1; 1335 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1336 BUS_DMA_NOWAIT)) { 1337 aprint_error_dev(sc->bge_dev, 1338 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1339 error = ENOBUFS; 1340 goto out; 1341 } 1342 1343 state = 2; 1344 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1345 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1346 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1347 error = ENOBUFS; 1348 goto out; 1349 } 1350 1351 state = 3; 1352 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1353 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1354 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1355 error = ENOBUFS; 1356 goto out; 1357 } 1358 1359 state = 4; 1360 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1361 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1362 1363 SLIST_INIT(&sc->bge_jfree_listhead); 1364 SLIST_INIT(&sc->bge_jinuse_listhead); 1365 1366 /* 1367 * Now divide it up into 9K pieces and save the addresses 1368 * in an array. 1369 */ 1370 ptr = sc->bge_cdata.bge_jumbo_buf; 1371 for (i = 0; i < BGE_JSLOTS; i++) { 1372 sc->bge_cdata.bge_jslots[i] = ptr; 1373 ptr += BGE_JLEN; 1374 entry = malloc(sizeof(struct bge_jpool_entry), 1375 M_DEVBUF, M_WAITOK); 1376 entry->slot = i; 1377 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1378 entry, jpool_entries); 1379 } 1380 out: 1381 if (error != 0) { 1382 switch (state) { 1383 case 4: 1384 bus_dmamap_unload(sc->bge_dmatag, 1385 sc->bge_cdata.bge_rx_jumbo_map); 1386 /* FALLTHROUGH */ 1387 case 3: 1388 bus_dmamap_destroy(sc->bge_dmatag, 1389 sc->bge_cdata.bge_rx_jumbo_map); 1390 /* FALLTHROUGH */ 1391 case 2: 1392 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1393 /* FALLTHROUGH */ 1394 case 1: 1395 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1396 break; 1397 default: 1398 break; 1399 } 1400 } 1401 1402 return error; 1403 } 1404 1405 /* 1406 * Allocate a jumbo buffer. 1407 */ 1408 static void * 1409 bge_jalloc(struct bge_softc *sc) 1410 { 1411 struct bge_jpool_entry *entry; 1412 1413 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1414 1415 if (entry == NULL) { 1416 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1417 return NULL; 1418 } 1419 1420 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1421 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1422 return (sc->bge_cdata.bge_jslots[entry->slot]); 1423 } 1424 1425 /* 1426 * Release a jumbo buffer. 1427 */ 1428 static void 1429 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1430 { 1431 struct bge_jpool_entry *entry; 1432 struct bge_softc * const sc = arg; 1433 int i, s; 1434 1435 if (sc == NULL) 1436 panic("bge_jfree: can't find softc pointer!"); 1437 1438 /* calculate the slot this buffer belongs to */ 1439 1440 i = ((char *)buf 1441 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1442 1443 if ((i < 0) || (i >= BGE_JSLOTS)) 1444 panic("bge_jfree: asked to free buffer that we don't manage!"); 1445 1446 s = splvm(); 1447 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1448 if (entry == NULL) 1449 panic("bge_jfree: buffer not in use!"); 1450 entry->slot = i; 1451 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1452 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1453 1454 if (__predict_true(m != NULL)) 1455 pool_cache_put(mb_cache, m); 1456 splx(s); 1457 } 1458 1459 1460 /* 1461 * Initialize a standard receive ring descriptor. 1462 */ 1463 static int 1464 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1465 bus_dmamap_t dmamap) 1466 { 1467 struct mbuf *m_new = NULL; 1468 struct bge_rx_bd *r; 1469 int error; 1470 1471 if (dmamap == NULL) 1472 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1473 1474 if (dmamap == NULL) { 1475 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1476 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1477 if (error != 0) 1478 return error; 1479 } 1480 1481 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1482 1483 if (m == NULL) { 1484 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1485 if (m_new == NULL) 1486 return ENOBUFS; 1487 1488 MCLGET(m_new, M_DONTWAIT); 1489 if (!(m_new->m_flags & M_EXT)) { 1490 m_freem(m_new); 1491 return ENOBUFS; 1492 } 1493 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1494 1495 } else { 1496 m_new = m; 1497 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1498 m_new->m_data = m_new->m_ext.ext_buf; 1499 } 1500 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1501 m_adj(m_new, ETHER_ALIGN); 1502 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1503 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1504 m_freem(m_new); 1505 return ENOBUFS; 1506 } 1507 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1508 BUS_DMASYNC_PREREAD); 1509 1510 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1511 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1512 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1513 r->bge_flags = BGE_RXBDFLAG_END; 1514 r->bge_len = m_new->m_len; 1515 r->bge_idx = i; 1516 1517 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1518 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1519 i * sizeof (struct bge_rx_bd), 1520 sizeof (struct bge_rx_bd), 1521 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1522 1523 return 0; 1524 } 1525 1526 /* 1527 * Initialize a jumbo receive ring descriptor. This allocates 1528 * a jumbo buffer from the pool managed internally by the driver. 1529 */ 1530 static int 1531 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1532 { 1533 struct mbuf *m_new = NULL; 1534 struct bge_rx_bd *r; 1535 void *buf = NULL; 1536 1537 if (m == NULL) { 1538 1539 /* Allocate the mbuf. */ 1540 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1541 if (m_new == NULL) 1542 return ENOBUFS; 1543 1544 /* Allocate the jumbo buffer */ 1545 buf = bge_jalloc(sc); 1546 if (buf == NULL) { 1547 m_freem(m_new); 1548 aprint_error_dev(sc->bge_dev, 1549 "jumbo allocation failed -- packet dropped!\n"); 1550 return ENOBUFS; 1551 } 1552 1553 /* Attach the buffer to the mbuf. */ 1554 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1555 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1556 bge_jfree, sc); 1557 m_new->m_flags |= M_EXT_RW; 1558 } else { 1559 m_new = m; 1560 buf = m_new->m_data = m_new->m_ext.ext_buf; 1561 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1562 } 1563 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1564 m_adj(m_new, ETHER_ALIGN); 1565 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1566 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1567 BGE_JLEN, BUS_DMASYNC_PREREAD); 1568 /* Set up the descriptor. */ 1569 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1570 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1571 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1572 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1573 r->bge_len = m_new->m_len; 1574 r->bge_idx = i; 1575 1576 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1577 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1578 i * sizeof (struct bge_rx_bd), 1579 sizeof (struct bge_rx_bd), 1580 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1581 1582 return 0; 1583 } 1584 1585 /* 1586 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1587 * that's 1MB or memory, which is a lot. For now, we fill only the first 1588 * 256 ring entries and hope that our CPU is fast enough to keep up with 1589 * the NIC. 1590 */ 1591 static int 1592 bge_init_rx_ring_std(struct bge_softc *sc) 1593 { 1594 int i; 1595 1596 if (sc->bge_flags & BGEF_RXRING_VALID) 1597 return 0; 1598 1599 for (i = 0; i < BGE_SSLOTS; i++) { 1600 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1601 return ENOBUFS; 1602 } 1603 1604 sc->bge_std = i - 1; 1605 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1606 1607 sc->bge_flags |= BGEF_RXRING_VALID; 1608 1609 return 0; 1610 } 1611 1612 static void 1613 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1614 { 1615 int i; 1616 1617 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1618 return; 1619 1620 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1621 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1622 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1623 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1624 if (disable) { 1625 bus_dmamap_destroy(sc->bge_dmatag, 1626 sc->bge_cdata.bge_rx_std_map[i]); 1627 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1628 } 1629 } 1630 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1631 sizeof(struct bge_rx_bd)); 1632 } 1633 1634 sc->bge_flags &= ~BGEF_RXRING_VALID; 1635 } 1636 1637 static int 1638 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1639 { 1640 int i; 1641 volatile struct bge_rcb *rcb; 1642 1643 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1644 return 0; 1645 1646 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1647 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1648 return ENOBUFS; 1649 } 1650 1651 sc->bge_jumbo = i - 1; 1652 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1653 1654 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1655 rcb->bge_maxlen_flags = 0; 1656 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1657 1658 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1659 1660 return 0; 1661 } 1662 1663 static void 1664 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1665 { 1666 int i; 1667 1668 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1669 return; 1670 1671 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1672 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1673 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1674 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1675 } 1676 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1677 sizeof(struct bge_rx_bd)); 1678 } 1679 1680 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1681 } 1682 1683 static void 1684 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1685 { 1686 int i; 1687 struct txdmamap_pool_entry *dma; 1688 1689 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1690 return; 1691 1692 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1693 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1694 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1695 sc->bge_cdata.bge_tx_chain[i] = NULL; 1696 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1697 link); 1698 sc->txdma[i] = 0; 1699 } 1700 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1701 sizeof(struct bge_tx_bd)); 1702 } 1703 1704 if (disable) { 1705 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1706 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1707 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1708 if (sc->bge_dma64) { 1709 bus_dmamap_destroy(sc->bge_dmatag32, 1710 dma->dmamap32); 1711 } 1712 free(dma, M_DEVBUF); 1713 } 1714 SLIST_INIT(&sc->txdma_list); 1715 } 1716 1717 sc->bge_flags &= ~BGEF_TXRING_VALID; 1718 } 1719 1720 static int 1721 bge_init_tx_ring(struct bge_softc *sc) 1722 { 1723 struct ifnet * const ifp = &sc->ethercom.ec_if; 1724 int i; 1725 bus_dmamap_t dmamap, dmamap32; 1726 bus_size_t maxsegsz; 1727 struct txdmamap_pool_entry *dma; 1728 1729 if (sc->bge_flags & BGEF_TXRING_VALID) 1730 return 0; 1731 1732 sc->bge_txcnt = 0; 1733 sc->bge_tx_saved_considx = 0; 1734 1735 /* Initialize transmit producer index for host-memory send ring. */ 1736 sc->bge_tx_prodidx = 0; 1737 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1738 /* 5700 b2 errata */ 1739 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1740 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1741 1742 /* NIC-memory send ring not used; initialize to zero. */ 1743 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1744 /* 5700 b2 errata */ 1745 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1746 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1747 1748 /* Limit DMA segment size for some chips */ 1749 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1750 (ifp->if_mtu <= ETHERMTU)) 1751 maxsegsz = 2048; 1752 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1753 maxsegsz = 4096; 1754 else 1755 maxsegsz = ETHER_MAX_LEN_JUMBO; 1756 1757 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1758 goto alloc_done; 1759 1760 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1761 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1762 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1763 &dmamap)) 1764 return ENOBUFS; 1765 if (dmamap == NULL) 1766 panic("dmamap NULL in bge_init_tx_ring"); 1767 if (sc->bge_dma64) { 1768 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1769 BGE_NTXSEG, maxsegsz, 0, 1770 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1771 &dmamap32)) { 1772 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1773 return ENOBUFS; 1774 } 1775 if (dmamap32 == NULL) 1776 panic("dmamap32 NULL in bge_init_tx_ring"); 1777 } else 1778 dmamap32 = dmamap; 1779 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1780 if (dma == NULL) { 1781 aprint_error_dev(sc->bge_dev, 1782 "can't alloc txdmamap_pool_entry\n"); 1783 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1784 if (sc->bge_dma64) 1785 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1786 return ENOMEM; 1787 } 1788 dma->dmamap = dmamap; 1789 dma->dmamap32 = dmamap32; 1790 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1791 } 1792 alloc_done: 1793 sc->bge_flags |= BGEF_TXRING_VALID; 1794 1795 return 0; 1796 } 1797 1798 static void 1799 bge_setmulti(struct bge_softc *sc) 1800 { 1801 struct ethercom * const ec = &sc->ethercom; 1802 struct ifnet * const ifp = &ec->ec_if; 1803 struct ether_multi *enm; 1804 struct ether_multistep step; 1805 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1806 uint32_t h; 1807 int i; 1808 1809 if (ifp->if_flags & IFF_PROMISC) 1810 goto allmulti; 1811 1812 /* Now program new ones. */ 1813 ETHER_LOCK(ec); 1814 ETHER_FIRST_MULTI(step, ec, enm); 1815 while (enm != NULL) { 1816 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1817 /* 1818 * We must listen to a range of multicast addresses. 1819 * For now, just accept all multicasts, rather than 1820 * trying to set only those filter bits needed to match 1821 * the range. (At this time, the only use of address 1822 * ranges is for IP multicast routing, for which the 1823 * range is big enough to require all bits set.) 1824 */ 1825 ETHER_UNLOCK(ec); 1826 goto allmulti; 1827 } 1828 1829 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1830 1831 /* Just want the 7 least-significant bits. */ 1832 h &= 0x7f; 1833 1834 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1835 ETHER_NEXT_MULTI(step, enm); 1836 } 1837 ETHER_UNLOCK(ec); 1838 1839 ifp->if_flags &= ~IFF_ALLMULTI; 1840 goto setit; 1841 1842 allmulti: 1843 ifp->if_flags |= IFF_ALLMULTI; 1844 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1845 1846 setit: 1847 for (i = 0; i < 4; i++) 1848 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1849 } 1850 1851 static void 1852 bge_sig_pre_reset(struct bge_softc *sc, int type) 1853 { 1854 1855 /* 1856 * Some chips don't like this so only do this if ASF is enabled 1857 */ 1858 if (sc->bge_asf_mode) 1859 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1860 1861 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1862 switch (type) { 1863 case BGE_RESET_START: 1864 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1865 BGE_FW_DRV_STATE_START); 1866 break; 1867 case BGE_RESET_SHUTDOWN: 1868 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1869 BGE_FW_DRV_STATE_UNLOAD); 1870 break; 1871 case BGE_RESET_SUSPEND: 1872 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1873 BGE_FW_DRV_STATE_SUSPEND); 1874 break; 1875 } 1876 } 1877 1878 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1879 bge_ape_driver_state_change(sc, type); 1880 } 1881 1882 static void 1883 bge_sig_post_reset(struct bge_softc *sc, int type) 1884 { 1885 1886 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1887 switch (type) { 1888 case BGE_RESET_START: 1889 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1890 BGE_FW_DRV_STATE_START_DONE); 1891 /* START DONE */ 1892 break; 1893 case BGE_RESET_SHUTDOWN: 1894 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1895 BGE_FW_DRV_STATE_UNLOAD_DONE); 1896 break; 1897 } 1898 } 1899 1900 if (type == BGE_RESET_SHUTDOWN) 1901 bge_ape_driver_state_change(sc, type); 1902 } 1903 1904 static void 1905 bge_sig_legacy(struct bge_softc *sc, int type) 1906 { 1907 1908 if (sc->bge_asf_mode) { 1909 switch (type) { 1910 case BGE_RESET_START: 1911 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1912 BGE_FW_DRV_STATE_START); 1913 break; 1914 case BGE_RESET_SHUTDOWN: 1915 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1916 BGE_FW_DRV_STATE_UNLOAD); 1917 break; 1918 } 1919 } 1920 } 1921 1922 static void 1923 bge_wait_for_event_ack(struct bge_softc *sc) 1924 { 1925 int i; 1926 1927 /* wait up to 2500usec */ 1928 for (i = 0; i < 250; i++) { 1929 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1930 BGE_RX_CPU_DRV_EVENT)) 1931 break; 1932 DELAY(10); 1933 } 1934 } 1935 1936 static void 1937 bge_stop_fw(struct bge_softc *sc) 1938 { 1939 1940 if (sc->bge_asf_mode) { 1941 bge_wait_for_event_ack(sc); 1942 1943 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1944 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1945 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1946 1947 bge_wait_for_event_ack(sc); 1948 } 1949 } 1950 1951 static int 1952 bge_poll_fw(struct bge_softc *sc) 1953 { 1954 uint32_t val; 1955 int i; 1956 1957 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1958 for (i = 0; i < BGE_TIMEOUT; i++) { 1959 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1960 if (val & BGE_VCPU_STATUS_INIT_DONE) 1961 break; 1962 DELAY(100); 1963 } 1964 if (i >= BGE_TIMEOUT) { 1965 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1966 return -1; 1967 } 1968 } else { 1969 /* 1970 * Poll the value location we just wrote until 1971 * we see the 1's complement of the magic number. 1972 * This indicates that the firmware initialization 1973 * is complete. 1974 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1975 */ 1976 for (i = 0; i < BGE_TIMEOUT; i++) { 1977 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1978 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1979 break; 1980 DELAY(10); 1981 } 1982 1983 if ((i >= BGE_TIMEOUT) 1984 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1985 aprint_error_dev(sc->bge_dev, 1986 "firmware handshake timed out, val = %x\n", val); 1987 return -1; 1988 } 1989 } 1990 1991 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1992 /* tg3 says we have to wait extra time */ 1993 delay(10 * 1000); 1994 } 1995 1996 return 0; 1997 } 1998 1999 int 2000 bge_phy_addr(struct bge_softc *sc) 2001 { 2002 struct pci_attach_args *pa = &(sc->bge_pa); 2003 int phy_addr = 1; 2004 2005 /* 2006 * PHY address mapping for various devices. 2007 * 2008 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2009 * ---------+-------+-------+-------+-------+ 2010 * BCM57XX | 1 | X | X | X | 2011 * BCM5704 | 1 | X | 1 | X | 2012 * BCM5717 | 1 | 8 | 2 | 9 | 2013 * BCM5719 | 1 | 8 | 2 | 9 | 2014 * BCM5720 | 1 | 8 | 2 | 9 | 2015 * 2016 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2017 * ---------+-------+-------+-------+-------+ 2018 * BCM57XX | X | X | X | X | 2019 * BCM5704 | X | X | X | X | 2020 * BCM5717 | X | X | X | X | 2021 * BCM5719 | 3 | 10 | 4 | 11 | 2022 * BCM5720 | X | X | X | X | 2023 * 2024 * Other addresses may respond but they are not 2025 * IEEE compliant PHYs and should be ignored. 2026 */ 2027 switch (BGE_ASICREV(sc->bge_chipid)) { 2028 case BGE_ASICREV_BCM5717: 2029 case BGE_ASICREV_BCM5719: 2030 case BGE_ASICREV_BCM5720: 2031 phy_addr = pa->pa_function; 2032 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2033 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2034 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2035 } else { 2036 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2037 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2038 } 2039 } 2040 2041 return phy_addr; 2042 } 2043 2044 /* 2045 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2046 * self-test results. 2047 */ 2048 static int 2049 bge_chipinit(struct bge_softc *sc) 2050 { 2051 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2052 int i; 2053 2054 /* Set endianness before we access any non-PCI registers. */ 2055 misc_ctl = BGE_INIT; 2056 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2057 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2058 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2059 misc_ctl); 2060 2061 /* 2062 * Clear the MAC statistics block in the NIC's 2063 * internal memory. 2064 */ 2065 for (i = BGE_STATS_BLOCK; 2066 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2067 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2068 2069 for (i = BGE_STATUS_BLOCK; 2070 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2071 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2072 2073 /* 5717 workaround from tg3 */ 2074 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2075 /* Save */ 2076 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2077 2078 /* Temporary modify MODE_CTL to control TLP */ 2079 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2080 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2081 2082 /* Control TLP */ 2083 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2084 BGE_TLP_PHYCTL1); 2085 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2086 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2087 2088 /* Restore */ 2089 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2090 } 2091 2092 if (BGE_IS_57765_FAMILY(sc)) { 2093 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2094 /* Save */ 2095 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2096 2097 /* Temporary modify MODE_CTL to control TLP */ 2098 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2099 CSR_WRITE_4(sc, BGE_MODE_CTL, 2100 reg | BGE_MODECTL_PCIE_TLPADDR1); 2101 2102 /* Control TLP */ 2103 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2104 BGE_TLP_PHYCTL5); 2105 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2106 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2107 2108 /* Restore */ 2109 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2110 } 2111 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2112 /* 2113 * For the 57766 and non Ax versions of 57765, bootcode 2114 * needs to setup the PCIE Fast Training Sequence (FTS) 2115 * value to prevent transmit hangs. 2116 */ 2117 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2118 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2119 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2120 2121 /* Save */ 2122 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2123 2124 /* Temporary modify MODE_CTL to control TLP */ 2125 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2126 CSR_WRITE_4(sc, BGE_MODE_CTL, 2127 reg | BGE_MODECTL_PCIE_TLPADDR0); 2128 2129 /* Control TLP */ 2130 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2131 BGE_TLP_FTSMAX); 2132 reg &= ~BGE_TLP_FTSMAX_MSK; 2133 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2134 reg | BGE_TLP_FTSMAX_VAL); 2135 2136 /* Restore */ 2137 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2138 } 2139 2140 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2141 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2142 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2143 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2144 } 2145 2146 /* Set up the PCI DMA control register. */ 2147 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2148 if (sc->bge_flags & BGEF_PCIE) { 2149 /* Read watermark not used, 128 bytes for write. */ 2150 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2151 device_xname(sc->bge_dev))); 2152 if (sc->bge_mps >= 256) 2153 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2154 else 2155 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2156 } else if (sc->bge_flags & BGEF_PCIX) { 2157 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2158 device_xname(sc->bge_dev))); 2159 /* PCI-X bus */ 2160 if (BGE_IS_5714_FAMILY(sc)) { 2161 /* 256 bytes for read and write. */ 2162 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2163 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2164 2165 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2166 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2167 else 2168 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2169 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2170 /* 2171 * In the BCM5703, the DMA read watermark should 2172 * be set to less than or equal to the maximum 2173 * memory read byte count of the PCI-X command 2174 * register. 2175 */ 2176 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2177 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2178 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2179 /* 1536 bytes for read, 384 bytes for write. */ 2180 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2181 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2182 } else { 2183 /* 384 bytes for read and write. */ 2184 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2185 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2186 (0x0F); 2187 } 2188 2189 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2190 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2191 uint32_t tmp; 2192 2193 /* Set ONEDMA_ATONCE for hardware workaround. */ 2194 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2195 if (tmp == 6 || tmp == 7) 2196 dma_rw_ctl |= 2197 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2198 2199 /* Set PCI-X DMA write workaround. */ 2200 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2201 } 2202 } else { 2203 /* Conventional PCI bus: 256 bytes for read and write. */ 2204 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2205 device_xname(sc->bge_dev))); 2206 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2207 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2208 2209 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2210 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2211 dma_rw_ctl |= 0x0F; 2212 } 2213 2214 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2215 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2216 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2217 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2218 2219 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2220 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2221 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2222 2223 if (BGE_IS_57765_PLUS(sc)) { 2224 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2225 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2226 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2227 2228 /* 2229 * Enable HW workaround for controllers that misinterpret 2230 * a status tag update and leave interrupts permanently 2231 * disabled. 2232 */ 2233 if (!BGE_IS_57765_FAMILY(sc) && 2234 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2235 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2236 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2237 } 2238 2239 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2240 dma_rw_ctl); 2241 2242 /* 2243 * Set up general mode register. 2244 */ 2245 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2246 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2247 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2248 /* Retain Host-2-BMC settings written by APE firmware. */ 2249 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2250 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2251 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2252 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2253 } 2254 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2255 BGE_MODECTL_TX_NO_PHDR_CSUM; 2256 2257 /* 2258 * BCM5701 B5 have a bug causing data corruption when using 2259 * 64-bit DMA reads, which can be terminated early and then 2260 * completed later as 32-bit accesses, in combination with 2261 * certain bridges. 2262 */ 2263 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2264 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2265 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2266 2267 /* 2268 * Tell the firmware the driver is running 2269 */ 2270 if (sc->bge_asf_mode & ASF_STACKUP) 2271 mode_ctl |= BGE_MODECTL_STACKUP; 2272 2273 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2274 2275 /* 2276 * Disable memory write invalidate. Apparently it is not supported 2277 * properly by these devices. 2278 */ 2279 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2280 PCI_COMMAND_INVALIDATE_ENABLE); 2281 2282 #ifdef __brokenalpha__ 2283 /* 2284 * Must insure that we do not cross an 8K (bytes) boundary 2285 * for DMA reads. Our highest limit is 1K bytes. This is a 2286 * restriction on some ALPHA platforms with early revision 2287 * 21174 PCI chipsets, such as the AlphaPC 164lx 2288 */ 2289 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2290 #endif 2291 2292 /* Set the timer prescaler (always 66MHz) */ 2293 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2294 2295 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2296 DELAY(40); /* XXX */ 2297 2298 /* Put PHY into ready state */ 2299 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2300 DELAY(40); 2301 } 2302 2303 return 0; 2304 } 2305 2306 static int 2307 bge_blockinit(struct bge_softc *sc) 2308 { 2309 volatile struct bge_rcb *rcb; 2310 bus_size_t rcb_addr; 2311 struct ifnet * const ifp = &sc->ethercom.ec_if; 2312 bge_hostaddr taddr; 2313 uint32_t dmactl, rdmareg, mimode, val; 2314 int i, limit; 2315 2316 /* 2317 * Initialize the memory window pointer register so that 2318 * we can access the first 32K of internal NIC RAM. This will 2319 * allow us to set up the TX send ring RCBs and the RX return 2320 * ring RCBs, plus other things which live in NIC memory. 2321 */ 2322 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2323 2324 if (!BGE_IS_5705_PLUS(sc)) { 2325 /* 57XX step 33 */ 2326 /* Configure mbuf memory pool */ 2327 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2328 2329 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2330 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2331 else 2332 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2333 2334 /* 57XX step 34 */ 2335 /* Configure DMA resource pool */ 2336 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2337 BGE_DMA_DESCRIPTORS); 2338 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2339 } 2340 2341 /* 5718 step 11, 57XX step 35 */ 2342 /* 2343 * Configure mbuf pool watermarks. New broadcom docs strongly 2344 * recommend these. 2345 */ 2346 if (BGE_IS_5717_PLUS(sc)) { 2347 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2348 if (ifp->if_mtu > ETHERMTU) { 2349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2351 } else { 2352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2354 } 2355 } else if (BGE_IS_5705_PLUS(sc)) { 2356 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2357 2358 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2359 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2360 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2361 } else { 2362 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2363 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2364 } 2365 } else { 2366 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2367 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2368 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2369 } 2370 2371 /* 57XX step 36 */ 2372 /* Configure DMA resource watermarks */ 2373 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2374 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2375 2376 /* 5718 step 13, 57XX step 38 */ 2377 /* Enable buffer manager */ 2378 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2379 /* 2380 * Change the arbitration algorithm of TXMBUF read request to 2381 * round-robin instead of priority based for BCM5719. When 2382 * TXFIFO is almost empty, RDMA will hold its request until 2383 * TXFIFO is not almost empty. 2384 */ 2385 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2386 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2387 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2388 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2389 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2390 val |= BGE_BMANMODE_LOMBUF_ATTN; 2391 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2392 2393 /* 57XX step 39 */ 2394 /* Poll for buffer manager start indication */ 2395 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2396 DELAY(10); 2397 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2398 break; 2399 } 2400 2401 if (i == BGE_TIMEOUT * 2) { 2402 aprint_error_dev(sc->bge_dev, 2403 "buffer manager failed to start\n"); 2404 return ENXIO; 2405 } 2406 2407 /* 57XX step 40 */ 2408 /* Enable flow-through queues */ 2409 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2410 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2411 2412 /* Wait until queue initialization is complete */ 2413 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2414 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2415 break; 2416 DELAY(10); 2417 } 2418 2419 if (i == BGE_TIMEOUT * 2) { 2420 aprint_error_dev(sc->bge_dev, 2421 "flow-through queue init failed\n"); 2422 return ENXIO; 2423 } 2424 2425 /* 2426 * Summary of rings supported by the controller: 2427 * 2428 * Standard Receive Producer Ring 2429 * - This ring is used to feed receive buffers for "standard" 2430 * sized frames (typically 1536 bytes) to the controller. 2431 * 2432 * Jumbo Receive Producer Ring 2433 * - This ring is used to feed receive buffers for jumbo sized 2434 * frames (i.e. anything bigger than the "standard" frames) 2435 * to the controller. 2436 * 2437 * Mini Receive Producer Ring 2438 * - This ring is used to feed receive buffers for "mini" 2439 * sized frames to the controller. 2440 * - This feature required external memory for the controller 2441 * but was never used in a production system. Should always 2442 * be disabled. 2443 * 2444 * Receive Return Ring 2445 * - After the controller has placed an incoming frame into a 2446 * receive buffer that buffer is moved into a receive return 2447 * ring. The driver is then responsible to passing the 2448 * buffer up to the stack. Many versions of the controller 2449 * support multiple RR rings. 2450 * 2451 * Send Ring 2452 * - This ring is used for outgoing frames. Many versions of 2453 * the controller support multiple send rings. 2454 */ 2455 2456 /* 5718 step 15, 57XX step 41 */ 2457 /* Initialize the standard RX ring control block */ 2458 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2459 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2460 /* 5718 step 16 */ 2461 if (BGE_IS_57765_PLUS(sc)) { 2462 /* 2463 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2464 * Bits 15-2 : Maximum RX frame size 2465 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2466 * Bit 0 : Reserved 2467 */ 2468 rcb->bge_maxlen_flags = 2469 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2470 } else if (BGE_IS_5705_PLUS(sc)) { 2471 /* 2472 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2473 * Bits 15-2 : Reserved (should be 0) 2474 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2475 * Bit 0 : Reserved 2476 */ 2477 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2478 } else { 2479 /* 2480 * Ring size is always XXX entries 2481 * Bits 31-16: Maximum RX frame size 2482 * Bits 15-2 : Reserved (should be 0) 2483 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2484 * Bit 0 : Reserved 2485 */ 2486 rcb->bge_maxlen_flags = 2487 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2488 } 2489 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2492 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2493 else 2494 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2495 /* Write the standard receive producer ring control block. */ 2496 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2497 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2498 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2499 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2500 2501 /* Reset the standard receive producer ring producer index. */ 2502 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2503 2504 /* 57XX step 42 */ 2505 /* 2506 * Initialize the jumbo RX ring control block 2507 * We set the 'ring disabled' bit in the flags 2508 * field until we're actually ready to start 2509 * using this ring (i.e. once we set the MTU 2510 * high enough to require it). 2511 */ 2512 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2513 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2514 BGE_HOSTADDR(rcb->bge_hostaddr, 2515 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2516 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2517 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2518 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2519 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2520 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2521 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2522 else 2523 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2524 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2525 rcb->bge_hostaddr.bge_addr_hi); 2526 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2527 rcb->bge_hostaddr.bge_addr_lo); 2528 /* Program the jumbo receive producer ring RCB parameters. */ 2529 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2530 rcb->bge_maxlen_flags); 2531 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2532 /* Reset the jumbo receive producer ring producer index. */ 2533 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2534 } 2535 2536 /* 57XX step 43 */ 2537 /* Disable the mini receive producer ring RCB. */ 2538 if (BGE_IS_5700_FAMILY(sc)) { 2539 /* Set up dummy disabled mini ring RCB */ 2540 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2541 rcb->bge_maxlen_flags = 2542 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2543 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2544 rcb->bge_maxlen_flags); 2545 /* Reset the mini receive producer ring producer index. */ 2546 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2547 2548 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2549 offsetof(struct bge_ring_data, bge_info), 2550 sizeof (struct bge_gib), 2551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2552 } 2553 2554 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2555 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2556 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2557 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2558 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2559 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2560 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2561 } 2562 /* 5718 step 14, 57XX step 44 */ 2563 /* 2564 * The BD ring replenish thresholds control how often the 2565 * hardware fetches new BD's from the producer rings in host 2566 * memory. Setting the value too low on a busy system can 2567 * starve the hardware and recue the throughpout. 2568 * 2569 * Set the BD ring replenish thresholds. The recommended 2570 * values are 1/8th the number of descriptors allocated to 2571 * each ring, but since we try to avoid filling the entire 2572 * ring we set these to the minimal value of 8. This needs to 2573 * be done on several of the supported chip revisions anyway, 2574 * to work around HW bugs. 2575 */ 2576 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2577 if (BGE_IS_JUMBO_CAPABLE(sc)) 2578 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2579 2580 /* 5718 step 18 */ 2581 if (BGE_IS_5717_PLUS(sc)) { 2582 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2583 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2584 } 2585 2586 /* 57XX step 45 */ 2587 /* 2588 * Disable all send rings by setting the 'ring disabled' bit 2589 * in the flags field of all the TX send ring control blocks, 2590 * located in NIC memory. 2591 */ 2592 if (BGE_IS_5700_FAMILY(sc)) { 2593 /* 5700 to 5704 had 16 send rings. */ 2594 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2595 } else if (BGE_IS_5717_PLUS(sc)) { 2596 limit = BGE_TX_RINGS_5717_MAX; 2597 } else if (BGE_IS_57765_FAMILY(sc) || 2598 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2599 limit = BGE_TX_RINGS_57765_MAX; 2600 } else 2601 limit = 1; 2602 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2603 for (i = 0; i < limit; i++) { 2604 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2605 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2606 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2607 rcb_addr += sizeof(struct bge_rcb); 2608 } 2609 2610 /* 57XX step 46 and 47 */ 2611 /* Configure send ring RCB 0 (we use only the first ring) */ 2612 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2613 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2614 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2615 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2616 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2617 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2618 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2619 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2620 else 2621 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2622 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2623 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2624 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2625 2626 /* 57XX step 48 */ 2627 /* 2628 * Disable all receive return rings by setting the 2629 * 'ring diabled' bit in the flags field of all the receive 2630 * return ring control blocks, located in NIC memory. 2631 */ 2632 if (BGE_IS_5717_PLUS(sc)) { 2633 /* Should be 17, use 16 until we get an SRAM map. */ 2634 limit = 16; 2635 } else if (BGE_IS_5700_FAMILY(sc)) 2636 limit = BGE_RX_RINGS_MAX; 2637 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2638 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2639 BGE_IS_57765_FAMILY(sc)) 2640 limit = 4; 2641 else 2642 limit = 1; 2643 /* Disable all receive return rings */ 2644 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2645 for (i = 0; i < limit; i++) { 2646 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2647 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2648 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2649 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2650 BGE_RCB_FLAG_RING_DISABLED)); 2651 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2652 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2653 (i * (sizeof(uint64_t))), 0); 2654 rcb_addr += sizeof(struct bge_rcb); 2655 } 2656 2657 /* 57XX step 49 */ 2658 /* 2659 * Set up receive return ring 0. Note that the NIC address 2660 * for RX return rings is 0x0. The return rings live entirely 2661 * within the host, so the nicaddr field in the RCB isn't used. 2662 */ 2663 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2664 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2665 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2666 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2667 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2668 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2669 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2670 2671 /* 5718 step 24, 57XX step 53 */ 2672 /* Set random backoff seed for TX */ 2673 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2674 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2675 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2676 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2677 BGE_TX_BACKOFF_SEED_MASK); 2678 2679 /* 5718 step 26, 57XX step 55 */ 2680 /* Set inter-packet gap */ 2681 val = 0x2620; 2682 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2683 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2684 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2685 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2686 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2687 2688 /* 5718 step 27, 57XX step 56 */ 2689 /* 2690 * Specify which ring to use for packets that don't match 2691 * any RX rules. 2692 */ 2693 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2694 2695 /* 5718 step 28, 57XX step 57 */ 2696 /* 2697 * Configure number of RX lists. One interrupt distribution 2698 * list, sixteen active lists, one bad frames class. 2699 */ 2700 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2701 2702 /* 5718 step 29, 57XX step 58 */ 2703 /* Inialize RX list placement stats mask. */ 2704 if (BGE_IS_575X_PLUS(sc)) { 2705 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2706 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2707 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2708 } else 2709 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2710 2711 /* 5718 step 30, 57XX step 59 */ 2712 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2713 2714 /* 5718 step 33, 57XX step 62 */ 2715 /* Disable host coalescing until we get it set up */ 2716 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2717 2718 /* 5718 step 34, 57XX step 63 */ 2719 /* Poll to make sure it's shut down. */ 2720 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2721 DELAY(10); 2722 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2723 break; 2724 } 2725 2726 if (i == BGE_TIMEOUT * 2) { 2727 aprint_error_dev(sc->bge_dev, 2728 "host coalescing engine failed to idle\n"); 2729 return ENXIO; 2730 } 2731 2732 /* 5718 step 35, 36, 37 */ 2733 /* Set up host coalescing defaults */ 2734 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2735 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2736 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2737 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2738 if (!(BGE_IS_5705_PLUS(sc))) { 2739 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2740 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2741 } 2742 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2743 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2744 2745 /* Set up address of statistics block */ 2746 if (BGE_IS_5700_FAMILY(sc)) { 2747 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2748 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2749 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2750 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2751 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2752 } 2753 2754 /* 5718 step 38 */ 2755 /* Set up address of status block */ 2756 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2757 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2758 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2759 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2760 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2761 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2762 2763 /* Set up status block size. */ 2764 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2765 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2766 val = BGE_STATBLKSZ_FULL; 2767 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2768 } else { 2769 val = BGE_STATBLKSZ_32BYTE; 2770 bzero(&sc->bge_rdata->bge_status_block, 32); 2771 } 2772 2773 /* 5718 step 39, 57XX step 73 */ 2774 /* Turn on host coalescing state machine */ 2775 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2776 2777 /* 5718 step 40, 57XX step 74 */ 2778 /* Turn on RX BD completion state machine and enable attentions */ 2779 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2780 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2781 2782 /* 5718 step 41, 57XX step 75 */ 2783 /* Turn on RX list placement state machine */ 2784 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2785 2786 /* 57XX step 76 */ 2787 /* Turn on RX list selector state machine. */ 2788 if (!(BGE_IS_5705_PLUS(sc))) 2789 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2790 2791 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2792 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2793 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2794 BGE_MACMODE_FRMHDR_DMA_ENB; 2795 2796 if (sc->bge_flags & BGEF_FIBER_TBI) 2797 val |= BGE_PORTMODE_TBI; 2798 else if (sc->bge_flags & BGEF_FIBER_MII) 2799 val |= BGE_PORTMODE_GMII; 2800 else 2801 val |= BGE_PORTMODE_MII; 2802 2803 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2804 /* Allow APE to send/receive frames. */ 2805 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2806 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2807 2808 /* Turn on DMA, clear stats */ 2809 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2810 /* 5718 step 44 */ 2811 DELAY(40); 2812 2813 /* 5718 step 45, 57XX step 79 */ 2814 /* Set misc. local control, enable interrupts on attentions */ 2815 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2816 if (BGE_IS_5717_PLUS(sc)) { 2817 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2818 /* 5718 step 46 */ 2819 DELAY(100); 2820 } 2821 2822 /* 57XX step 81 */ 2823 /* Turn on DMA completion state machine */ 2824 if (!(BGE_IS_5705_PLUS(sc))) 2825 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2826 2827 /* 5718 step 47, 57XX step 82 */ 2828 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2829 2830 /* 5718 step 48 */ 2831 /* Enable host coalescing bug fix. */ 2832 if (BGE_IS_5755_PLUS(sc)) 2833 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2834 2835 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2836 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2837 2838 /* Turn on write DMA state machine */ 2839 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2840 /* 5718 step 49 */ 2841 DELAY(40); 2842 2843 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2844 2845 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2846 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2847 2848 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2849 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2850 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2851 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2852 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2853 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2854 2855 if (sc->bge_flags & BGEF_PCIE) 2856 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2857 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2858 if (ifp->if_mtu <= ETHERMTU) 2859 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2860 } 2861 if (sc->bge_flags & BGEF_TSO) { 2862 val |= BGE_RDMAMODE_TSO4_ENABLE; 2863 if (BGE_IS_5717_PLUS(sc)) 2864 val |= BGE_RDMAMODE_TSO6_ENABLE; 2865 } 2866 2867 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2868 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2869 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2870 BGE_RDMAMODE_H2BNC_VLAN_DET; 2871 /* 2872 * Allow multiple outstanding read requests from 2873 * non-LSO read DMA engine. 2874 */ 2875 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2876 } 2877 2878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2879 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2880 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2881 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2882 BGE_IS_57765_PLUS(sc)) { 2883 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2884 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2885 else 2886 rdmareg = BGE_RDMA_RSRVCTRL; 2887 dmactl = CSR_READ_4(sc, rdmareg); 2888 /* 2889 * Adjust tx margin to prevent TX data corruption and 2890 * fix internal FIFO overflow. 2891 */ 2892 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2893 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2894 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2895 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2896 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2897 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2898 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2899 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2900 } 2901 /* 2902 * Enable fix for read DMA FIFO overruns. 2903 * The fix is to limit the number of RX BDs 2904 * the hardware would fetch at a time. 2905 */ 2906 CSR_WRITE_4(sc, rdmareg, dmactl | 2907 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2908 } 2909 2910 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2911 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2912 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2913 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2914 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2915 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2916 /* 2917 * Allow 4KB burst length reads for non-LSO frames. 2918 * Enable 512B burst length reads for buffer descriptors. 2919 */ 2920 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2921 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2922 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2923 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2924 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2925 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2926 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2927 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2928 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2929 } 2930 /* Turn on read DMA state machine */ 2931 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2932 /* 5718 step 52 */ 2933 delay(40); 2934 2935 if (sc->bge_flags & BGEF_RDMA_BUG) { 2936 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2937 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2938 if ((val & 0xFFFF) > BGE_FRAMELEN) 2939 break; 2940 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2941 break; 2942 } 2943 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2944 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2945 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2946 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2947 else 2948 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2949 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2950 } 2951 } 2952 2953 /* 5718 step 56, 57XX step 84 */ 2954 /* Turn on RX data completion state machine */ 2955 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2956 2957 /* Turn on RX data and RX BD initiator state machine */ 2958 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2959 2960 /* 57XX step 85 */ 2961 /* Turn on Mbuf cluster free state machine */ 2962 if (!BGE_IS_5705_PLUS(sc)) 2963 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2964 2965 /* 5718 step 57, 57XX step 86 */ 2966 /* Turn on send data completion state machine */ 2967 val = BGE_SDCMODE_ENABLE; 2968 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2969 val |= BGE_SDCMODE_CDELAY; 2970 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2971 2972 /* 5718 step 58 */ 2973 /* Turn on send BD completion state machine */ 2974 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2975 2976 /* 57XX step 88 */ 2977 /* Turn on RX BD initiator state machine */ 2978 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2979 2980 /* 5718 step 60, 57XX step 90 */ 2981 /* Turn on send data initiator state machine */ 2982 if (sc->bge_flags & BGEF_TSO) { 2983 /* XXX: magic value from Linux driver */ 2984 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2985 BGE_SDIMODE_HW_LSO_PRE_DMA); 2986 } else 2987 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2988 2989 /* 5718 step 61, 57XX step 91 */ 2990 /* Turn on send BD initiator state machine */ 2991 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2992 2993 /* 5718 step 62, 57XX step 92 */ 2994 /* Turn on send BD selector state machine */ 2995 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2996 2997 /* 5718 step 31, 57XX step 60 */ 2998 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2999 /* 5718 step 32, 57XX step 61 */ 3000 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3001 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3002 3003 /* ack/clear link change events */ 3004 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3005 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3006 BGE_MACSTAT_LINK_CHANGED); 3007 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3008 3009 /* 3010 * Enable attention when the link has changed state for 3011 * devices that use auto polling. 3012 */ 3013 if (sc->bge_flags & BGEF_FIBER_TBI) { 3014 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3015 } else { 3016 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3017 mimode = BGE_MIMODE_500KHZ_CONST; 3018 else 3019 mimode = BGE_MIMODE_BASE; 3020 /* 5718 step 68. 5718 step 69 (optionally). */ 3021 if (BGE_IS_5700_FAMILY(sc) || 3022 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3023 mimode |= BGE_MIMODE_AUTOPOLL; 3024 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3025 } 3026 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3027 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3028 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3029 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3030 BGE_EVTENB_MI_INTERRUPT); 3031 } 3032 3033 /* 3034 * Clear any pending link state attention. 3035 * Otherwise some link state change events may be lost until attention 3036 * is cleared by bge_intr() -> bge_link_upd() sequence. 3037 * It's not necessary on newer BCM chips - perhaps enabling link 3038 * state change attentions implies clearing pending attention. 3039 */ 3040 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3041 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3042 BGE_MACSTAT_LINK_CHANGED); 3043 3044 /* Enable link state change attentions. */ 3045 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3046 3047 return 0; 3048 } 3049 3050 static const struct bge_revision * 3051 bge_lookup_rev(uint32_t chipid) 3052 { 3053 const struct bge_revision *br; 3054 3055 for (br = bge_revisions; br->br_name != NULL; br++) { 3056 if (br->br_chipid == chipid) 3057 return br; 3058 } 3059 3060 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3061 if (br->br_chipid == BGE_ASICREV(chipid)) 3062 return br; 3063 } 3064 3065 return NULL; 3066 } 3067 3068 static const struct bge_product * 3069 bge_lookup(const struct pci_attach_args *pa) 3070 { 3071 const struct bge_product *bp; 3072 3073 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3074 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3075 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3076 return bp; 3077 } 3078 3079 return NULL; 3080 } 3081 3082 static uint32_t 3083 bge_chipid(const struct pci_attach_args *pa) 3084 { 3085 uint32_t id; 3086 3087 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3088 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3089 3090 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3091 switch (PCI_PRODUCT(pa->pa_id)) { 3092 case PCI_PRODUCT_BROADCOM_BCM5717: 3093 case PCI_PRODUCT_BROADCOM_BCM5718: 3094 case PCI_PRODUCT_BROADCOM_BCM5719: 3095 case PCI_PRODUCT_BROADCOM_BCM5720: 3096 case PCI_PRODUCT_BROADCOM_BCM5725: 3097 case PCI_PRODUCT_BROADCOM_BCM5727: 3098 case PCI_PRODUCT_BROADCOM_BCM5762: 3099 case PCI_PRODUCT_BROADCOM_BCM57764: 3100 case PCI_PRODUCT_BROADCOM_BCM57767: 3101 case PCI_PRODUCT_BROADCOM_BCM57787: 3102 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3103 BGE_PCI_GEN2_PRODID_ASICREV); 3104 break; 3105 case PCI_PRODUCT_BROADCOM_BCM57761: 3106 case PCI_PRODUCT_BROADCOM_BCM57762: 3107 case PCI_PRODUCT_BROADCOM_BCM57765: 3108 case PCI_PRODUCT_BROADCOM_BCM57766: 3109 case PCI_PRODUCT_BROADCOM_BCM57781: 3110 case PCI_PRODUCT_BROADCOM_BCM57782: 3111 case PCI_PRODUCT_BROADCOM_BCM57785: 3112 case PCI_PRODUCT_BROADCOM_BCM57786: 3113 case PCI_PRODUCT_BROADCOM_BCM57791: 3114 case PCI_PRODUCT_BROADCOM_BCM57795: 3115 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3116 BGE_PCI_GEN15_PRODID_ASICREV); 3117 break; 3118 default: 3119 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3120 BGE_PCI_PRODID_ASICREV); 3121 break; 3122 } 3123 } 3124 3125 return id; 3126 } 3127 3128 /* 3129 * Return true if MSI can be used with this device. 3130 */ 3131 static int 3132 bge_can_use_msi(struct bge_softc *sc) 3133 { 3134 int can_use_msi = 0; 3135 3136 switch (BGE_ASICREV(sc->bge_chipid)) { 3137 case BGE_ASICREV_BCM5714_A0: 3138 case BGE_ASICREV_BCM5714: 3139 /* 3140 * Apparently, MSI doesn't work when these chips are 3141 * configured in single-port mode. 3142 */ 3143 break; 3144 case BGE_ASICREV_BCM5750: 3145 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3146 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3147 can_use_msi = 1; 3148 break; 3149 default: 3150 if (BGE_IS_575X_PLUS(sc)) 3151 can_use_msi = 1; 3152 } 3153 return (can_use_msi); 3154 } 3155 3156 /* 3157 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3158 * against our list and return its name if we find a match. Note 3159 * that since the Broadcom controller contains VPD support, we 3160 * can get the device name string from the controller itself instead 3161 * of the compiled-in string. This is a little slow, but it guarantees 3162 * we'll always announce the right product name. 3163 */ 3164 static int 3165 bge_probe(device_t parent, cfdata_t match, void *aux) 3166 { 3167 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3168 3169 if (bge_lookup(pa) != NULL) 3170 return 1; 3171 3172 return 0; 3173 } 3174 3175 static void 3176 bge_attach(device_t parent, device_t self, void *aux) 3177 { 3178 struct bge_softc * const sc = device_private(self); 3179 struct pci_attach_args * const pa = aux; 3180 prop_dictionary_t dict; 3181 const struct bge_product *bp; 3182 const struct bge_revision *br; 3183 pci_chipset_tag_t pc; 3184 const char *intrstr = NULL; 3185 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3186 uint32_t command; 3187 struct ifnet *ifp; 3188 struct mii_data * const mii = &sc->bge_mii; 3189 uint32_t misccfg, mimode, macmode; 3190 void * kva; 3191 u_char eaddr[ETHER_ADDR_LEN]; 3192 pcireg_t memtype, subid, reg; 3193 bus_addr_t memaddr; 3194 uint32_t pm_ctl; 3195 bool no_seeprom; 3196 int capmask, trys; 3197 int mii_flags; 3198 int map_flags; 3199 char intrbuf[PCI_INTRSTR_LEN]; 3200 3201 bp = bge_lookup(pa); 3202 KASSERT(bp != NULL); 3203 3204 sc->sc_pc = pa->pa_pc; 3205 sc->sc_pcitag = pa->pa_tag; 3206 sc->bge_dev = self; 3207 3208 sc->bge_pa = *pa; 3209 pc = sc->sc_pc; 3210 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3211 3212 aprint_naive(": Ethernet controller\n"); 3213 aprint_normal(": %s Ethernet\n", bp->bp_name); 3214 3215 /* 3216 * Map control/status registers. 3217 */ 3218 DPRINTFN(5, ("Map control/status regs\n")); 3219 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3220 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3221 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3222 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3223 3224 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3225 aprint_error_dev(sc->bge_dev, 3226 "failed to enable memory mapping!\n"); 3227 return; 3228 } 3229 3230 DPRINTFN(5, ("pci_mem_find\n")); 3231 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3232 switch (memtype) { 3233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3234 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3235 #if 0 3236 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3237 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3238 &memaddr, &sc->bge_bsize) == 0) 3239 break; 3240 #else 3241 /* 3242 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3243 * system get NMI on boot (PR#48451). This problem might not be 3244 * the driver's bug but our PCI common part's bug. Until we 3245 * find a real reason, we ignore the prefetchable bit. 3246 */ 3247 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3248 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3249 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3250 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3251 map_flags, &sc->bge_bhandle) == 0) { 3252 sc->bge_btag = pa->pa_memt; 3253 break; 3254 } 3255 } 3256 #endif 3257 /* FALLTHROUGH */ 3258 default: 3259 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3260 return; 3261 } 3262 3263 /* Save various chip information. */ 3264 sc->bge_chipid = bge_chipid(pa); 3265 sc->bge_phy_addr = bge_phy_addr(sc); 3266 3267 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3268 &sc->bge_pciecap, NULL) != 0) { 3269 /* PCIe */ 3270 sc->bge_flags |= BGEF_PCIE; 3271 /* Extract supported maximum payload size. */ 3272 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3273 sc->bge_pciecap + PCIE_DCAP); 3274 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3275 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3276 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3277 sc->bge_expmrq = 2048; 3278 else 3279 sc->bge_expmrq = 4096; 3280 bge_set_max_readrq(sc); 3281 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3282 /* PCIe without PCIe cap */ 3283 sc->bge_flags |= BGEF_PCIE; 3284 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3285 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3286 /* PCI-X */ 3287 sc->bge_flags |= BGEF_PCIX; 3288 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3289 &sc->bge_pcixcap, NULL) == 0) 3290 aprint_error_dev(sc->bge_dev, 3291 "unable to find PCIX capability\n"); 3292 } 3293 3294 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3295 /* 3296 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3297 * can clobber the chip's PCI config-space power control 3298 * registers, leaving the card in D3 powersave state. We do 3299 * not have memory-mapped registers in this state, so force 3300 * device into D0 state before starting initialization. 3301 */ 3302 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3303 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3304 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3305 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3306 DELAY(1000); /* 27 usec is allegedly sufficient */ 3307 } 3308 3309 /* Save chipset family. */ 3310 switch (BGE_ASICREV(sc->bge_chipid)) { 3311 case BGE_ASICREV_BCM5717: 3312 case BGE_ASICREV_BCM5719: 3313 case BGE_ASICREV_BCM5720: 3314 sc->bge_flags |= BGEF_5717_PLUS; 3315 /* FALLTHROUGH */ 3316 case BGE_ASICREV_BCM5762: 3317 case BGE_ASICREV_BCM57765: 3318 case BGE_ASICREV_BCM57766: 3319 if (!BGE_IS_5717_PLUS(sc)) 3320 sc->bge_flags |= BGEF_57765_FAMILY; 3321 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3322 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3323 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3324 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3325 /* 3326 * Enable work around for DMA engine miscalculation 3327 * of TXMBUF available space. 3328 */ 3329 sc->bge_flags |= BGEF_RDMA_BUG; 3330 3331 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3332 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3333 /* Jumbo frame on BCM5719 A0 does not work. */ 3334 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3335 } 3336 } 3337 break; 3338 case BGE_ASICREV_BCM5755: 3339 case BGE_ASICREV_BCM5761: 3340 case BGE_ASICREV_BCM5784: 3341 case BGE_ASICREV_BCM5785: 3342 case BGE_ASICREV_BCM5787: 3343 case BGE_ASICREV_BCM57780: 3344 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3345 break; 3346 case BGE_ASICREV_BCM5700: 3347 case BGE_ASICREV_BCM5701: 3348 case BGE_ASICREV_BCM5703: 3349 case BGE_ASICREV_BCM5704: 3350 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3351 break; 3352 case BGE_ASICREV_BCM5714_A0: 3353 case BGE_ASICREV_BCM5780: 3354 case BGE_ASICREV_BCM5714: 3355 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3356 /* FALLTHROUGH */ 3357 case BGE_ASICREV_BCM5750: 3358 case BGE_ASICREV_BCM5752: 3359 case BGE_ASICREV_BCM5906: 3360 sc->bge_flags |= BGEF_575X_PLUS; 3361 /* FALLTHROUGH */ 3362 case BGE_ASICREV_BCM5705: 3363 sc->bge_flags |= BGEF_5705_PLUS; 3364 break; 3365 } 3366 3367 /* Identify chips with APE processor. */ 3368 switch (BGE_ASICREV(sc->bge_chipid)) { 3369 case BGE_ASICREV_BCM5717: 3370 case BGE_ASICREV_BCM5719: 3371 case BGE_ASICREV_BCM5720: 3372 case BGE_ASICREV_BCM5761: 3373 case BGE_ASICREV_BCM5762: 3374 sc->bge_flags |= BGEF_APE; 3375 break; 3376 } 3377 3378 /* 3379 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3380 * not actually a MAC controller bug but an issue with the embedded 3381 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3382 */ 3383 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3384 sc->bge_flags |= BGEF_40BIT_BUG; 3385 3386 /* Chips with APE need BAR2 access for APE registers/memory. */ 3387 if ((sc->bge_flags & BGEF_APE) != 0) { 3388 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3389 #if 0 3390 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3391 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3392 &sc->bge_apesize)) { 3393 aprint_error_dev(sc->bge_dev, 3394 "couldn't map BAR2 memory\n"); 3395 return; 3396 } 3397 #else 3398 /* 3399 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3400 * system get NMI on boot (PR#48451). This problem might not be 3401 * the driver's bug but our PCI common part's bug. Until we 3402 * find a real reason, we ignore the prefetchable bit. 3403 */ 3404 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3405 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3406 aprint_error_dev(sc->bge_dev, 3407 "couldn't map BAR2 memory\n"); 3408 return; 3409 } 3410 3411 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3412 if (bus_space_map(pa->pa_memt, memaddr, 3413 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3414 aprint_error_dev(sc->bge_dev, 3415 "couldn't map BAR2 memory\n"); 3416 return; 3417 } 3418 sc->bge_apetag = pa->pa_memt; 3419 #endif 3420 3421 /* Enable APE register/memory access by host driver. */ 3422 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3423 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3424 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3425 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3426 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3427 3428 bge_ape_lock_init(sc); 3429 bge_ape_read_fw_ver(sc); 3430 } 3431 3432 /* Identify the chips that use an CPMU. */ 3433 if (BGE_IS_5717_PLUS(sc) || 3434 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3435 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3436 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3437 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3438 sc->bge_flags |= BGEF_CPMU_PRESENT; 3439 3440 /* 3441 * When using the BCM5701 in PCI-X mode, data corruption has 3442 * been observed in the first few bytes of some received packets. 3443 * Aligning the packet buffer in memory eliminates the corruption. 3444 * Unfortunately, this misaligns the packet payloads. On platforms 3445 * which do not support unaligned accesses, we will realign the 3446 * payloads by copying the received packets. 3447 */ 3448 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3449 sc->bge_flags & BGEF_PCIX) 3450 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3451 3452 if (BGE_IS_5700_FAMILY(sc)) 3453 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3454 3455 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3456 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3457 3458 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3459 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3460 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3461 sc->bge_flags |= BGEF_IS_5788; 3462 3463 /* 3464 * Some controllers seem to require a special firmware to use 3465 * TSO. But the firmware is not available to FreeBSD and Linux 3466 * claims that the TSO performed by the firmware is slower than 3467 * hardware based TSO. Moreover the firmware based TSO has one 3468 * known bug which can't handle TSO if ethernet header + IP/TCP 3469 * header is greater than 80 bytes. The workaround for the TSO 3470 * bug exist but it seems it's too expensive than not using 3471 * TSO at all. Some hardwares also have the TSO bug so limit 3472 * the TSO to the controllers that are not affected TSO issues 3473 * (e.g. 5755 or higher). 3474 */ 3475 if (BGE_IS_5755_PLUS(sc)) { 3476 /* 3477 * BCM5754 and BCM5787 shares the same ASIC id so 3478 * explicit device id check is required. 3479 */ 3480 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3481 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3482 sc->bge_flags |= BGEF_TSO; 3483 /* TSO on BCM5719 A0 does not work. */ 3484 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3485 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3486 sc->bge_flags &= ~BGEF_TSO; 3487 } 3488 3489 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3490 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3491 (misccfg == 0x4000 || misccfg == 0x8000)) || 3492 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3493 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3494 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3495 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3496 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3497 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3498 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3499 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3500 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3501 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3502 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3503 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3504 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3505 /* These chips are 10/100 only. */ 3506 capmask &= ~BMSR_EXTSTAT; 3507 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3508 } 3509 3510 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3511 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3512 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3513 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3514 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3515 3516 /* Set various PHY bug flags. */ 3517 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3518 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3519 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3520 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3521 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3522 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3523 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3524 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3525 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3526 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3527 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3528 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3529 if (BGE_IS_5705_PLUS(sc) && 3530 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3531 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3532 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3533 !BGE_IS_57765_PLUS(sc)) { 3534 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3535 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3536 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3537 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3538 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3539 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3540 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3541 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3542 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3543 } else 3544 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3545 } 3546 3547 /* 3548 * SEEPROM check. 3549 * First check if firmware knows we do not have SEEPROM. 3550 */ 3551 if (prop_dictionary_get_bool(device_properties(self), 3552 "without-seeprom", &no_seeprom) && no_seeprom) 3553 sc->bge_flags |= BGEF_NO_EEPROM; 3554 3555 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3556 sc->bge_flags |= BGEF_NO_EEPROM; 3557 3558 /* Now check the 'ROM failed' bit on the RX CPU */ 3559 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3560 sc->bge_flags |= BGEF_NO_EEPROM; 3561 3562 sc->bge_asf_mode = 0; 3563 /* No ASF if APE present. */ 3564 if ((sc->bge_flags & BGEF_APE) == 0) { 3565 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3566 BGE_SRAM_DATA_SIG_MAGIC)) { 3567 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3568 BGE_HWCFG_ASF) { 3569 sc->bge_asf_mode |= ASF_ENABLE; 3570 sc->bge_asf_mode |= ASF_STACKUP; 3571 if (BGE_IS_575X_PLUS(sc)) 3572 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3573 } 3574 } 3575 } 3576 3577 int counts[PCI_INTR_TYPE_SIZE] = { 3578 [PCI_INTR_TYPE_INTX] = 1, 3579 [PCI_INTR_TYPE_MSI] = 1, 3580 [PCI_INTR_TYPE_MSIX] = 1, 3581 }; 3582 int max_type = PCI_INTR_TYPE_MSIX; 3583 3584 if (!bge_can_use_msi(sc)) { 3585 /* MSI broken, allow only INTx */ 3586 max_type = PCI_INTR_TYPE_INTX; 3587 } 3588 3589 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3590 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3591 return; 3592 } 3593 3594 DPRINTFN(5, ("pci_intr_string\n")); 3595 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3596 sizeof(intrbuf)); 3597 DPRINTFN(5, ("pci_intr_establish\n")); 3598 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3599 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3600 if (sc->bge_intrhand == NULL) { 3601 pci_intr_release(pc, sc->bge_pihp, 1); 3602 sc->bge_pihp = NULL; 3603 3604 aprint_error_dev(self, "couldn't establish interrupt"); 3605 if (intrstr != NULL) 3606 aprint_error(" at %s", intrstr); 3607 aprint_error("\n"); 3608 return; 3609 } 3610 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3611 3612 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3613 case PCI_INTR_TYPE_MSIX: 3614 case PCI_INTR_TYPE_MSI: 3615 KASSERT(bge_can_use_msi(sc)); 3616 sc->bge_flags |= BGEF_MSI; 3617 break; 3618 default: 3619 /* nothing to do */ 3620 break; 3621 } 3622 3623 /* 3624 * All controllers except BCM5700 supports tagged status but 3625 * we use tagged status only for MSI case on BCM5717. Otherwise 3626 * MSI on BCM5717 does not work. 3627 */ 3628 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3629 sc->bge_flags |= BGEF_TAGGED_STATUS; 3630 3631 /* 3632 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3633 * lock in bge_reset(). 3634 */ 3635 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3636 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3637 delay(1000); 3638 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3639 3640 bge_stop_fw(sc); 3641 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3642 if (bge_reset(sc)) 3643 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3644 3645 /* 3646 * Read the hardware config word in the first 32k of NIC internal 3647 * memory, or fall back to the config word in the EEPROM. 3648 * Note: on some BCM5700 cards, this value appears to be unset. 3649 */ 3650 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3651 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3652 BGE_SRAM_DATA_SIG_MAGIC) { 3653 uint32_t tmp; 3654 3655 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3656 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3657 BGE_SRAM_DATA_VER_SHIFT; 3658 if ((0 < tmp) && (tmp < 0x100)) 3659 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3660 if (sc->bge_flags & BGEF_PCIE) 3661 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3662 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3663 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3664 if (BGE_IS_5717_PLUS(sc)) 3665 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3666 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3667 bge_read_eeprom(sc, (void *)&hwcfg, 3668 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3669 hwcfg = be32toh(hwcfg); 3670 } 3671 aprint_normal_dev(sc->bge_dev, 3672 "HW config %08x, %08x, %08x, %08x %08x\n", 3673 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3674 3675 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3676 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3677 3678 if (bge_chipinit(sc)) { 3679 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3680 bge_release_resources(sc); 3681 return; 3682 } 3683 3684 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3685 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3686 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3687 DELAY(100); 3688 } 3689 3690 /* Set MI_MODE */ 3691 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3692 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3693 mimode |= BGE_MIMODE_500KHZ_CONST; 3694 else 3695 mimode |= BGE_MIMODE_BASE; 3696 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3697 DELAY(80); 3698 3699 /* 3700 * Get station address from the EEPROM. 3701 */ 3702 if (bge_get_eaddr(sc, eaddr)) { 3703 aprint_error_dev(sc->bge_dev, 3704 "failed to read station address\n"); 3705 bge_release_resources(sc); 3706 return; 3707 } 3708 3709 br = bge_lookup_rev(sc->bge_chipid); 3710 3711 if (br == NULL) { 3712 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3713 sc->bge_chipid); 3714 } else { 3715 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3716 br->br_name, sc->bge_chipid); 3717 } 3718 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3719 3720 /* Allocate the general information block and ring buffers. */ 3721 if (pci_dma64_available(pa)) { 3722 sc->bge_dmatag = pa->pa_dmat64; 3723 sc->bge_dmatag32 = pa->pa_dmat; 3724 sc->bge_dma64 = true; 3725 } else { 3726 sc->bge_dmatag = pa->pa_dmat; 3727 sc->bge_dmatag32 = pa->pa_dmat; 3728 sc->bge_dma64 = false; 3729 } 3730 3731 /* 40bit DMA workaround */ 3732 if (sizeof(bus_addr_t) > 4) { 3733 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3734 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3735 3736 if (bus_dmatag_subregion(olddmatag, 0, 3737 (bus_addr_t)__MASK(40), 3738 &(sc->bge_dmatag), BUS_DMA_NOWAIT) != 0) { 3739 aprint_error_dev(self, 3740 "WARNING: failed to restrict dma range," 3741 " falling back to parent bus dma range\n"); 3742 sc->bge_dmatag = olddmatag; 3743 } 3744 } 3745 } 3746 SLIST_INIT(&sc->txdma_list); 3747 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3748 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3749 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3750 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3751 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3752 return; 3753 } 3754 DPRINTFN(5, ("bus_dmamem_map\n")); 3755 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3756 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3757 BUS_DMA_NOWAIT)) { 3758 aprint_error_dev(sc->bge_dev, 3759 "can't map DMA buffers (%zu bytes)\n", 3760 sizeof(struct bge_ring_data)); 3761 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3762 sc->bge_ring_rseg); 3763 return; 3764 } 3765 DPRINTFN(5, ("bus_dmamem_create\n")); 3766 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3767 sizeof(struct bge_ring_data), 0, 3768 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3769 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3770 bus_dmamem_unmap(sc->bge_dmatag, kva, 3771 sizeof(struct bge_ring_data)); 3772 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3773 sc->bge_ring_rseg); 3774 return; 3775 } 3776 DPRINTFN(5, ("bus_dmamem_load\n")); 3777 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3778 sizeof(struct bge_ring_data), NULL, 3779 BUS_DMA_NOWAIT)) { 3780 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3781 bus_dmamem_unmap(sc->bge_dmatag, kva, 3782 sizeof(struct bge_ring_data)); 3783 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3784 sc->bge_ring_rseg); 3785 return; 3786 } 3787 3788 DPRINTFN(5, ("bzero\n")); 3789 sc->bge_rdata = (struct bge_ring_data *)kva; 3790 3791 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3792 3793 /* Try to allocate memory for jumbo buffers. */ 3794 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3795 if (bge_alloc_jumbo_mem(sc)) { 3796 aprint_error_dev(sc->bge_dev, 3797 "jumbo buffer allocation failed\n"); 3798 } else 3799 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3800 } 3801 3802 /* Set default tuneable values. */ 3803 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3804 sc->bge_rx_coal_ticks = 150; 3805 sc->bge_rx_max_coal_bds = 64; 3806 sc->bge_tx_coal_ticks = 300; 3807 sc->bge_tx_max_coal_bds = 400; 3808 if (BGE_IS_5705_PLUS(sc)) { 3809 sc->bge_tx_coal_ticks = (12 * 5); 3810 sc->bge_tx_max_coal_bds = (12 * 5); 3811 aprint_verbose_dev(sc->bge_dev, 3812 "setting short Tx thresholds\n"); 3813 } 3814 3815 if (BGE_IS_5717_PLUS(sc)) 3816 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3817 else if (BGE_IS_5705_PLUS(sc)) 3818 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3819 else 3820 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3821 3822 /* Set up ifnet structure */ 3823 ifp = &sc->ethercom.ec_if; 3824 ifp->if_softc = sc; 3825 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3826 ifp->if_ioctl = bge_ioctl; 3827 ifp->if_stop = bge_stop; 3828 ifp->if_start = bge_start; 3829 ifp->if_init = bge_init; 3830 ifp->if_watchdog = bge_watchdog; 3831 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3832 IFQ_SET_READY(&ifp->if_snd); 3833 DPRINTFN(5, ("strcpy if_xname\n")); 3834 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3835 3836 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3837 sc->ethercom.ec_if.if_capabilities |= 3838 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3839 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3840 sc->ethercom.ec_if.if_capabilities |= 3841 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3842 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3843 #endif 3844 sc->ethercom.ec_capabilities |= 3845 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3846 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3847 3848 if (sc->bge_flags & BGEF_TSO) 3849 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3850 3851 /* 3852 * Do MII setup. 3853 */ 3854 DPRINTFN(5, ("mii setup\n")); 3855 mii->mii_ifp = ifp; 3856 mii->mii_readreg = bge_miibus_readreg; 3857 mii->mii_writereg = bge_miibus_writereg; 3858 mii->mii_statchg = bge_miibus_statchg; 3859 3860 /* 3861 * Figure out what sort of media we have by checking the hardware 3862 * config word. Note: on some BCM5700 cards, this value appears to be 3863 * unset. If that's the case, we have to rely on identifying the NIC 3864 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3865 * The SysKonnect SK-9D41 is a 1000baseSX card. 3866 */ 3867 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3868 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3869 if (BGE_IS_5705_PLUS(sc)) { 3870 sc->bge_flags |= BGEF_FIBER_MII; 3871 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3872 } else 3873 sc->bge_flags |= BGEF_FIBER_TBI; 3874 } 3875 3876 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3877 if (BGE_IS_JUMBO_CAPABLE(sc)) 3878 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3879 3880 /* set phyflags and chipid before mii_attach() */ 3881 dict = device_properties(self); 3882 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3883 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3884 3885 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3886 macmode &= ~BGE_MACMODE_PORTMODE; 3887 /* Initialize ifmedia structures. */ 3888 if (sc->bge_flags & BGEF_FIBER_TBI) { 3889 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3890 macmode | BGE_PORTMODE_TBI); 3891 DELAY(40); 3892 3893 sc->ethercom.ec_ifmedia = &sc->bge_ifmedia; 3894 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3895 bge_ifmedia_sts); 3896 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3897 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3898 0, NULL); 3899 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3900 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3901 /* Pretend the user requested this setting */ 3902 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3903 } else { 3904 uint16_t phyreg; 3905 int rv; 3906 /* 3907 * Do transceiver setup and tell the firmware the 3908 * driver is down so we can try to get access the 3909 * probe if ASF is running. Retry a couple of times 3910 * if we get a conflict with the ASF firmware accessing 3911 * the PHY. 3912 */ 3913 if (sc->bge_flags & BGEF_FIBER_MII) 3914 macmode |= BGE_PORTMODE_GMII; 3915 else 3916 macmode |= BGE_PORTMODE_MII; 3917 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3918 DELAY(40); 3919 3920 /* 3921 * Do transceiver setup and tell the firmware the 3922 * driver is down so we can try to get access the 3923 * probe if ASF is running. Retry a couple of times 3924 * if we get a conflict with the ASF firmware accessing 3925 * the PHY. 3926 */ 3927 trys = 0; 3928 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3929 sc->ethercom.ec_mii = mii; 3930 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3931 bge_ifmedia_sts); 3932 mii_flags = MIIF_DOPAUSE; 3933 if (sc->bge_flags & BGEF_FIBER_MII) 3934 mii_flags |= MIIF_HAVEFIBER; 3935 again: 3936 bge_asf_driver_up(sc); 3937 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 3938 MII_BMCR, &phyreg); 3939 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 3940 int i; 3941 3942 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 3943 MII_BMCR, BMCR_RESET); 3944 /* Wait up to 500ms for it to complete. */ 3945 for (i = 0; i < 500; i++) { 3946 bge_miibus_readreg(sc->bge_dev, 3947 sc->bge_phy_addr, MII_BMCR, &phyreg); 3948 if ((phyreg & BMCR_RESET) == 0) 3949 break; 3950 DELAY(1000); 3951 } 3952 } 3953 3954 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 3955 MII_OFFSET_ANY, mii_flags); 3956 3957 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 3958 goto again; 3959 3960 if (LIST_EMPTY(&mii->mii_phys)) { 3961 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3962 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 3963 0, NULL); 3964 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 3965 } else 3966 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 3967 3968 /* 3969 * Now tell the firmware we are going up after probing the PHY 3970 */ 3971 if (sc->bge_asf_mode & ASF_STACKUP) 3972 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3973 } 3974 3975 /* 3976 * Call MI attach routine. 3977 */ 3978 DPRINTFN(5, ("if_attach\n")); 3979 if_attach(ifp); 3980 if_deferred_start_init(ifp, NULL); 3981 DPRINTFN(5, ("ether_ifattach\n")); 3982 ether_ifattach(ifp, eaddr); 3983 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3984 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3985 RND_TYPE_NET, RND_FLAG_DEFAULT); 3986 #ifdef BGE_EVENT_COUNTERS 3987 /* 3988 * Attach event counters. 3989 */ 3990 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3991 NULL, device_xname(sc->bge_dev), "intr"); 3992 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3993 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3994 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3995 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3996 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3997 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3998 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3999 NULL, device_xname(sc->bge_dev), "tx_xon"); 4000 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4001 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4002 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4003 NULL, device_xname(sc->bge_dev), "rx_xon"); 4004 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4005 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4006 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4007 NULL, device_xname(sc->bge_dev), "xoffentered"); 4008 #endif /* BGE_EVENT_COUNTERS */ 4009 DPRINTFN(5, ("callout_init\n")); 4010 callout_init(&sc->bge_timeout, 0); 4011 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4012 4013 if (pmf_device_register(self, NULL, NULL)) 4014 pmf_class_network_register(self, ifp); 4015 else 4016 aprint_error_dev(self, "couldn't establish power handler\n"); 4017 4018 bge_sysctl_init(sc); 4019 4020 #ifdef BGE_DEBUG 4021 bge_debug_info(sc); 4022 #endif 4023 } 4024 4025 /* 4026 * Stop all chip I/O so that the kernel's probe routines don't 4027 * get confused by errant DMAs when rebooting. 4028 */ 4029 static int 4030 bge_detach(device_t self, int flags __unused) 4031 { 4032 struct bge_softc * const sc = device_private(self); 4033 struct ifnet * const ifp = &sc->ethercom.ec_if; 4034 int s; 4035 4036 s = splnet(); 4037 /* Stop the interface. Callouts are stopped in it. */ 4038 bge_stop(ifp, 1); 4039 splx(s); 4040 4041 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4042 4043 ether_ifdetach(ifp); 4044 if_detach(ifp); 4045 4046 /* Delete all remaining media. */ 4047 ifmedia_fini(&sc->bge_mii.mii_media); 4048 4049 bge_release_resources(sc); 4050 4051 return 0; 4052 } 4053 4054 static void 4055 bge_release_resources(struct bge_softc *sc) 4056 { 4057 4058 /* Detach sysctl */ 4059 if (sc->bge_log != NULL) 4060 sysctl_teardown(&sc->bge_log); 4061 4062 #ifdef BGE_EVENT_COUNTERS 4063 /* Detach event counters. */ 4064 evcnt_detach(&sc->bge_ev_intr); 4065 evcnt_detach(&sc->bge_ev_intr_spurious); 4066 evcnt_detach(&sc->bge_ev_intr_spurious2); 4067 evcnt_detach(&sc->bge_ev_tx_xoff); 4068 evcnt_detach(&sc->bge_ev_tx_xon); 4069 evcnt_detach(&sc->bge_ev_rx_xoff); 4070 evcnt_detach(&sc->bge_ev_rx_xon); 4071 evcnt_detach(&sc->bge_ev_rx_macctl); 4072 evcnt_detach(&sc->bge_ev_xoffentered); 4073 #endif /* BGE_EVENT_COUNTERS */ 4074 4075 /* Disestablish the interrupt handler */ 4076 if (sc->bge_intrhand != NULL) { 4077 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4078 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4079 sc->bge_intrhand = NULL; 4080 } 4081 4082 if (sc->bge_dmatag != NULL) { 4083 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4084 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4085 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4086 sizeof(struct bge_ring_data)); 4087 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4088 sc->bge_ring_rseg); 4089 } 4090 4091 /* Unmap the device registers */ 4092 if (sc->bge_bsize != 0) { 4093 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4094 sc->bge_bsize = 0; 4095 } 4096 4097 /* Unmap the APE registers */ 4098 if (sc->bge_apesize != 0) { 4099 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4100 sc->bge_apesize); 4101 sc->bge_apesize = 0; 4102 } 4103 } 4104 4105 static int 4106 bge_reset(struct bge_softc *sc) 4107 { 4108 uint32_t cachesize, command; 4109 uint32_t reset, mac_mode, mac_mode_mask; 4110 pcireg_t devctl, reg; 4111 int i, val; 4112 void (*write_op)(struct bge_softc *, int, int); 4113 4114 /* Make mask for BGE_MAC_MODE register. */ 4115 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4116 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4117 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4118 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4119 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4120 4121 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4122 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4123 if (sc->bge_flags & BGEF_PCIE) 4124 write_op = bge_writemem_direct; 4125 else 4126 write_op = bge_writemem_ind; 4127 } else 4128 write_op = bge_writereg_ind; 4129 4130 /* 57XX step 4 */ 4131 /* Acquire the NVM lock */ 4132 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4133 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4134 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4135 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4136 for (i = 0; i < 8000; i++) { 4137 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4138 BGE_NVRAMSWARB_GNT1) 4139 break; 4140 DELAY(20); 4141 } 4142 if (i == 8000) { 4143 printf("%s: NVRAM lock timedout!\n", 4144 device_xname(sc->bge_dev)); 4145 } 4146 } 4147 4148 /* Take APE lock when performing reset. */ 4149 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4150 4151 /* 57XX step 3 */ 4152 /* Save some important PCI state. */ 4153 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4154 /* 5718 reset step 3 */ 4155 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4156 4157 /* 5718 reset step 5, 57XX step 5b-5d */ 4158 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4159 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4160 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4161 4162 /* XXX ???: Disable fastboot on controllers that support it. */ 4163 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4164 BGE_IS_5755_PLUS(sc)) 4165 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4166 4167 /* 5718 reset step 2, 57XX step 6 */ 4168 /* 4169 * Write the magic number to SRAM at offset 0xB50. 4170 * When firmware finishes its initialization it will 4171 * write ~BGE_MAGIC_NUMBER to the same location. 4172 */ 4173 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4174 4175 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4176 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4177 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4178 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4179 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4180 } 4181 4182 /* 5718 reset step 6, 57XX step 7 */ 4183 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4184 /* 4185 * XXX: from FreeBSD/Linux; no documentation 4186 */ 4187 if (sc->bge_flags & BGEF_PCIE) { 4188 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4189 !BGE_IS_57765_PLUS(sc) && 4190 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4191 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4192 /* PCI Express 1.0 system */ 4193 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4194 BGE_PHY_PCIE_SCRAM_MODE); 4195 } 4196 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4197 /* 4198 * Prevent PCI Express link training 4199 * during global reset. 4200 */ 4201 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4202 reset |= (1 << 29); 4203 } 4204 } 4205 4206 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4207 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4208 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4209 i | BGE_VCPU_STATUS_DRV_RESET); 4210 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4211 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4212 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4213 } 4214 4215 /* 4216 * Set GPHY Power Down Override to leave GPHY 4217 * powered up in D0 uninitialized. 4218 */ 4219 if (BGE_IS_5705_PLUS(sc) && 4220 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4221 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4222 4223 /* Issue global reset */ 4224 write_op(sc, BGE_MISC_CFG, reset); 4225 4226 /* 5718 reset step 7, 57XX step 8 */ 4227 if (sc->bge_flags & BGEF_PCIE) 4228 delay(100*1000); /* too big */ 4229 else 4230 delay(1000); 4231 4232 if (sc->bge_flags & BGEF_PCIE) { 4233 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4234 DELAY(500000); 4235 /* XXX: Magic Numbers */ 4236 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4237 BGE_PCI_UNKNOWN0); 4238 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4239 BGE_PCI_UNKNOWN0, 4240 reg | (1 << 15)); 4241 } 4242 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4243 sc->bge_pciecap + PCIE_DCSR); 4244 /* Clear enable no snoop and disable relaxed ordering. */ 4245 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4246 PCIE_DCSR_ENA_NO_SNOOP); 4247 4248 /* Set PCIE max payload size to 128 for older PCIe devices */ 4249 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4250 devctl &= ~(0x00e0); 4251 /* Clear device status register. Write 1b to clear */ 4252 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4253 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4254 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4255 sc->bge_pciecap + PCIE_DCSR, devctl); 4256 bge_set_max_readrq(sc); 4257 } 4258 4259 /* From Linux: dummy read to flush PCI posted writes */ 4260 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4261 4262 /* 4263 * Reset some of the PCI state that got zapped by reset 4264 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4265 * set, too. 4266 */ 4267 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4268 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4269 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4270 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4271 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4272 (sc->bge_flags & BGEF_PCIX) != 0) 4273 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4274 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4275 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4276 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4277 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4278 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4279 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4280 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4281 4282 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4283 if (sc->bge_flags & BGEF_PCIX) { 4284 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4285 + PCIX_CMD); 4286 /* Set max memory read byte count to 2K */ 4287 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4288 reg &= ~PCIX_CMD_BYTECNT_MASK; 4289 reg |= PCIX_CMD_BCNT_2048; 4290 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4291 /* 4292 * For 5704, set max outstanding split transaction 4293 * field to 0 (0 means it supports 1 request) 4294 */ 4295 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4296 | PCIX_CMD_BYTECNT_MASK); 4297 reg |= PCIX_CMD_BCNT_2048; 4298 } 4299 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4300 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4301 } 4302 4303 /* 5718 reset step 10, 57XX step 12 */ 4304 /* Enable memory arbiter. */ 4305 if (BGE_IS_5714_FAMILY(sc)) { 4306 val = CSR_READ_4(sc, BGE_MARB_MODE); 4307 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4308 } else 4309 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4310 4311 /* XXX 5721, 5751 and 5752 */ 4312 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4313 /* Step 19: */ 4314 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4315 /* Step 20: */ 4316 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4317 } 4318 4319 /* 5718 reset step 12, 57XX step 15 and 16 */ 4320 /* Fix up byte swapping */ 4321 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4322 4323 /* 5718 reset step 13, 57XX step 17 */ 4324 /* Poll until the firmware initialization is complete */ 4325 bge_poll_fw(sc); 4326 4327 /* 57XX step 21 */ 4328 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4329 pcireg_t msidata; 4330 4331 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4332 BGE_PCI_MSI_DATA); 4333 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4334 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4335 msidata); 4336 } 4337 4338 /* 57XX step 18 */ 4339 /* Write mac mode. */ 4340 val = CSR_READ_4(sc, BGE_MAC_MODE); 4341 /* Restore mac_mode_mask's bits using mac_mode */ 4342 val = (val & ~mac_mode_mask) | mac_mode; 4343 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4344 DELAY(40); 4345 4346 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4347 4348 /* 4349 * The 5704 in TBI mode apparently needs some special 4350 * adjustment to insure the SERDES drive level is set 4351 * to 1.2V. 4352 */ 4353 if (sc->bge_flags & BGEF_FIBER_TBI && 4354 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4355 uint32_t serdescfg; 4356 4357 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4358 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4359 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4360 } 4361 4362 if (sc->bge_flags & BGEF_PCIE && 4363 !BGE_IS_57765_PLUS(sc) && 4364 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4365 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4366 uint32_t v; 4367 4368 /* Enable PCI Express bug fix */ 4369 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4370 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4371 v | BGE_TLP_DATA_FIFO_PROTECT); 4372 } 4373 4374 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4375 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4376 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4377 4378 return 0; 4379 } 4380 4381 /* 4382 * Frame reception handling. This is called if there's a frame 4383 * on the receive return list. 4384 * 4385 * Note: we have to be able to handle two possibilities here: 4386 * 1) the frame is from the jumbo receive ring 4387 * 2) the frame is from the standard receive ring 4388 */ 4389 4390 static void 4391 bge_rxeof(struct bge_softc *sc) 4392 { 4393 struct ifnet *ifp; 4394 uint16_t rx_prod, rx_cons; 4395 int stdcnt = 0, jumbocnt = 0; 4396 bus_dmamap_t dmamap; 4397 bus_addr_t offset, toff; 4398 bus_size_t tlen; 4399 int tosync; 4400 4401 rx_cons = sc->bge_rx_saved_considx; 4402 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4403 4404 /* Nothing to do */ 4405 if (rx_cons == rx_prod) 4406 return; 4407 4408 ifp = &sc->ethercom.ec_if; 4409 4410 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4411 offsetof(struct bge_ring_data, bge_status_block), 4412 sizeof (struct bge_status_block), 4413 BUS_DMASYNC_POSTREAD); 4414 4415 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4416 tosync = rx_prod - rx_cons; 4417 4418 if (tosync != 0) 4419 rnd_add_uint32(&sc->rnd_source, tosync); 4420 4421 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4422 4423 if (tosync < 0) { 4424 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4425 sizeof (struct bge_rx_bd); 4426 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4427 toff, tlen, BUS_DMASYNC_POSTREAD); 4428 tosync = -tosync; 4429 } 4430 4431 if (tosync != 0) { 4432 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4433 offset, tosync * sizeof (struct bge_rx_bd), 4434 BUS_DMASYNC_POSTREAD); 4435 } 4436 4437 while (rx_cons != rx_prod) { 4438 struct bge_rx_bd *cur_rx; 4439 uint32_t rxidx; 4440 struct mbuf *m = NULL; 4441 4442 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4443 4444 rxidx = cur_rx->bge_idx; 4445 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4446 4447 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4448 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4449 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4450 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4451 jumbocnt++; 4452 bus_dmamap_sync(sc->bge_dmatag, 4453 sc->bge_cdata.bge_rx_jumbo_map, 4454 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4455 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4456 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4457 if_statinc(ifp, if_ierrors); 4458 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4459 continue; 4460 } 4461 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4462 NULL)== ENOBUFS) { 4463 if_statinc(ifp, if_ierrors); 4464 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4465 continue; 4466 } 4467 } else { 4468 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4469 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4470 4471 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4472 stdcnt++; 4473 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4474 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4475 if (dmamap == NULL) { 4476 if_statinc(ifp, if_ierrors); 4477 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4478 continue; 4479 } 4480 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4481 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4482 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4483 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4484 if_statinc(ifp, if_ierrors); 4485 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4486 continue; 4487 } 4488 if (bge_newbuf_std(sc, sc->bge_std, 4489 NULL, dmamap) == ENOBUFS) { 4490 if_statinc(ifp, if_ierrors); 4491 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4492 continue; 4493 } 4494 } 4495 4496 #ifndef __NO_STRICT_ALIGNMENT 4497 /* 4498 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4499 * the Rx buffer has the layer-2 header unaligned. 4500 * If our CPU requires alignment, re-align by copying. 4501 */ 4502 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4503 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4504 cur_rx->bge_len); 4505 m->m_data += ETHER_ALIGN; 4506 } 4507 #endif 4508 4509 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4510 m_set_rcvif(m, ifp); 4511 4512 bge_rxcsum(sc, cur_rx, m); 4513 4514 /* 4515 * If we received a packet with a vlan tag, pass it 4516 * to vlan_input() instead of ether_input(). 4517 */ 4518 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4519 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4520 4521 if_percpuq_enqueue(ifp->if_percpuq, m); 4522 } 4523 4524 sc->bge_rx_saved_considx = rx_cons; 4525 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4526 if (stdcnt) 4527 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4528 if (jumbocnt) 4529 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4530 } 4531 4532 static void 4533 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4534 { 4535 4536 if (BGE_IS_57765_PLUS(sc)) { 4537 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4538 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4539 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4540 if ((cur_rx->bge_error_flag & 4541 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4542 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4543 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4544 m->m_pkthdr.csum_data = 4545 cur_rx->bge_tcp_udp_csum; 4546 m->m_pkthdr.csum_flags |= 4547 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4548 } 4549 } 4550 } else { 4551 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4552 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4553 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4554 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4555 /* 4556 * Rx transport checksum-offload may also 4557 * have bugs with packets which, when transmitted, 4558 * were `runts' requiring padding. 4559 */ 4560 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4561 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4562 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4563 m->m_pkthdr.csum_data = 4564 cur_rx->bge_tcp_udp_csum; 4565 m->m_pkthdr.csum_flags |= 4566 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4567 } 4568 } 4569 } 4570 4571 static void 4572 bge_txeof(struct bge_softc *sc) 4573 { 4574 struct bge_tx_bd *cur_tx = NULL; 4575 struct ifnet *ifp; 4576 struct txdmamap_pool_entry *dma; 4577 bus_addr_t offset, toff; 4578 bus_size_t tlen; 4579 int tosync; 4580 struct mbuf *m; 4581 4582 ifp = &sc->ethercom.ec_if; 4583 4584 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4585 offsetof(struct bge_ring_data, bge_status_block), 4586 sizeof (struct bge_status_block), 4587 BUS_DMASYNC_POSTREAD); 4588 4589 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4590 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4591 sc->bge_tx_saved_considx; 4592 4593 if (tosync != 0) 4594 rnd_add_uint32(&sc->rnd_source, tosync); 4595 4596 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4597 4598 if (tosync < 0) { 4599 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4600 sizeof (struct bge_tx_bd); 4601 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4602 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4603 tosync = -tosync; 4604 } 4605 4606 if (tosync != 0) { 4607 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4608 offset, tosync * sizeof (struct bge_tx_bd), 4609 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4610 } 4611 4612 /* 4613 * Go through our tx ring and free mbufs for those 4614 * frames that have been sent. 4615 */ 4616 while (sc->bge_tx_saved_considx != 4617 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4618 uint32_t idx = 0; 4619 4620 idx = sc->bge_tx_saved_considx; 4621 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4622 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4623 if_statinc(ifp, if_opackets); 4624 m = sc->bge_cdata.bge_tx_chain[idx]; 4625 if (m != NULL) { 4626 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4627 dma = sc->txdma[idx]; 4628 if (dma->is_dma32) { 4629 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4630 0, dma->dmamap32->dm_mapsize, 4631 BUS_DMASYNC_POSTWRITE); 4632 bus_dmamap_unload( 4633 sc->bge_dmatag32, dma->dmamap32); 4634 } else { 4635 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4636 0, dma->dmamap->dm_mapsize, 4637 BUS_DMASYNC_POSTWRITE); 4638 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4639 } 4640 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4641 sc->txdma[idx] = NULL; 4642 4643 m_freem(m); 4644 } 4645 sc->bge_txcnt--; 4646 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4647 ifp->if_timer = 0; 4648 } 4649 4650 if (cur_tx != NULL) 4651 ifp->if_flags &= ~IFF_OACTIVE; 4652 } 4653 4654 static int 4655 bge_intr(void *xsc) 4656 { 4657 struct bge_softc * const sc = xsc; 4658 struct ifnet * const ifp = &sc->ethercom.ec_if; 4659 uint32_t pcistate, statusword, statustag; 4660 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4661 4662 4663 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4664 if (BGE_IS_5717_PLUS(sc)) 4665 intrmask = 0; 4666 4667 /* It is possible for the interrupt to arrive before 4668 * the status block is updated prior to the interrupt. 4669 * Reading the PCI State register will confirm whether the 4670 * interrupt is ours and will flush the status block. 4671 */ 4672 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4673 4674 /* read status word from status block */ 4675 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4676 offsetof(struct bge_ring_data, bge_status_block), 4677 sizeof (struct bge_status_block), 4678 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4679 statusword = sc->bge_rdata->bge_status_block.bge_status; 4680 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4681 4682 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4683 if (sc->bge_lasttag == statustag && 4684 (~pcistate & intrmask)) { 4685 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4686 return (0); 4687 } 4688 sc->bge_lasttag = statustag; 4689 } else { 4690 if (!(statusword & BGE_STATFLAG_UPDATED) && 4691 !(~pcistate & intrmask)) { 4692 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4693 return (0); 4694 } 4695 statustag = 0; 4696 } 4697 /* Ack interrupt and stop others from occurring. */ 4698 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4699 BGE_EVCNT_INCR(sc->bge_ev_intr); 4700 4701 /* clear status word */ 4702 sc->bge_rdata->bge_status_block.bge_status = 0; 4703 4704 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4705 offsetof(struct bge_ring_data, bge_status_block), 4706 sizeof (struct bge_status_block), 4707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4708 4709 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4710 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4711 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4712 bge_link_upd(sc); 4713 4714 if (ifp->if_flags & IFF_RUNNING) { 4715 /* Check RX return ring producer/consumer */ 4716 bge_rxeof(sc); 4717 4718 /* Check TX ring producer/consumer */ 4719 bge_txeof(sc); 4720 } 4721 4722 if (sc->bge_pending_rxintr_change) { 4723 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4724 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4725 4726 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4727 DELAY(10); 4728 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4729 4730 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4731 DELAY(10); 4732 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4733 4734 sc->bge_pending_rxintr_change = 0; 4735 } 4736 bge_handle_events(sc); 4737 4738 /* Re-enable interrupts. */ 4739 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4740 4741 if (ifp->if_flags & IFF_RUNNING) 4742 if_schedule_deferred_start(ifp); 4743 4744 return 1; 4745 } 4746 4747 static void 4748 bge_asf_driver_up(struct bge_softc *sc) 4749 { 4750 if (sc->bge_asf_mode & ASF_STACKUP) { 4751 /* Send ASF heartbeat aprox. every 2s */ 4752 if (sc->bge_asf_count) 4753 sc->bge_asf_count --; 4754 else { 4755 sc->bge_asf_count = 2; 4756 4757 bge_wait_for_event_ack(sc); 4758 4759 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4760 BGE_FW_CMD_DRV_ALIVE3); 4761 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4762 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4763 BGE_FW_HB_TIMEOUT_SEC); 4764 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4765 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4766 BGE_RX_CPU_DRV_EVENT); 4767 } 4768 } 4769 } 4770 4771 static void 4772 bge_tick(void *xsc) 4773 { 4774 struct bge_softc * const sc = xsc; 4775 struct mii_data * const mii = &sc->bge_mii; 4776 int s; 4777 4778 s = splnet(); 4779 4780 if (BGE_IS_5705_PLUS(sc)) 4781 bge_stats_update_regs(sc); 4782 else 4783 bge_stats_update(sc); 4784 4785 if (sc->bge_flags & BGEF_FIBER_TBI) { 4786 /* 4787 * Since in TBI mode auto-polling can't be used we should poll 4788 * link status manually. Here we register pending link event 4789 * and trigger interrupt. 4790 */ 4791 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4792 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4793 } else { 4794 /* 4795 * Do not touch PHY if we have link up. This could break 4796 * IPMI/ASF mode or produce extra input errors. 4797 * (extra input errors was reported for bcm5701 & bcm5704). 4798 */ 4799 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4800 mii_tick(mii); 4801 } 4802 4803 bge_asf_driver_up(sc); 4804 4805 if (!sc->bge_detaching) 4806 callout_schedule(&sc->bge_timeout, hz); 4807 4808 splx(s); 4809 } 4810 4811 static void 4812 bge_stats_update_regs(struct bge_softc *sc) 4813 { 4814 struct ifnet *const ifp = &sc->ethercom.ec_if; 4815 4816 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4817 4818 if_statadd_ref(nsr, if_collisions, 4819 CSR_READ_4(sc, BGE_MAC_STATS + 4820 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4821 4822 /* 4823 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4824 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4825 * (silicon bug). There's no reliable workaround so just 4826 * ignore the counter 4827 */ 4828 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4829 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4830 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4831 if_statadd_ref(nsr, if_ierrors, 4832 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4833 } 4834 if_statadd_ref(nsr, if_ierrors, 4835 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4836 if_statadd_ref(nsr, if_ierrors, 4837 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4838 4839 IF_STAT_PUTREF(ifp); 4840 4841 if (sc->bge_flags & BGEF_RDMA_BUG) { 4842 uint32_t val, ucast, mcast, bcast; 4843 4844 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4845 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4846 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4847 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4848 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4849 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4850 4851 /* 4852 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4853 * frames, it's safe to disable workaround for DMA engine's 4854 * miscalculation of TXMBUF space. 4855 */ 4856 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4857 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4858 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4859 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4860 else 4861 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4862 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4863 sc->bge_flags &= ~BGEF_RDMA_BUG; 4864 } 4865 } 4866 } 4867 4868 static void 4869 bge_stats_update(struct bge_softc *sc) 4870 { 4871 struct ifnet * const ifp = &sc->ethercom.ec_if; 4872 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4873 4874 #define READ_STAT(sc, stats, stat) \ 4875 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4876 4877 uint64_t collisions = 4878 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4879 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4880 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4881 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4882 4883 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4884 sc->bge_if_collisions = collisions; 4885 4886 4887 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4888 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4889 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4890 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4891 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4892 READ_STAT(sc, stats, 4893 xoffPauseFramesReceived.bge_addr_lo)); 4894 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4895 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4896 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4897 READ_STAT(sc, stats, 4898 macControlFramesReceived.bge_addr_lo)); 4899 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4900 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4901 4902 #undef READ_STAT 4903 4904 #ifdef notdef 4905 ifp->if_collisions += 4906 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4907 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4908 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4909 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4910 ifp->if_collisions; 4911 #endif 4912 } 4913 4914 /* 4915 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4916 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4917 * but when such padded frames employ the bge IP/TCP checksum offload, 4918 * the hardware checksum assist gives incorrect results (possibly 4919 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4920 * If we pad such runts with zeros, the onboard checksum comes out correct. 4921 */ 4922 static inline int 4923 bge_cksum_pad(struct mbuf *pkt) 4924 { 4925 struct mbuf *last = NULL; 4926 int padlen; 4927 4928 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4929 4930 /* if there's only the packet-header and we can pad there, use it. */ 4931 if (pkt->m_pkthdr.len == pkt->m_len && 4932 M_TRAILINGSPACE(pkt) >= padlen) { 4933 last = pkt; 4934 } else { 4935 /* 4936 * Walk packet chain to find last mbuf. We will either 4937 * pad there, or append a new mbuf and pad it 4938 * (thus perhaps avoiding the bcm5700 dma-min bug). 4939 */ 4940 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4941 continue; /* do nothing */ 4942 } 4943 4944 /* `last' now points to last in chain. */ 4945 if (M_TRAILINGSPACE(last) < padlen) { 4946 /* Allocate new empty mbuf, pad it. Compact later. */ 4947 struct mbuf *n; 4948 MGET(n, M_DONTWAIT, MT_DATA); 4949 if (n == NULL) 4950 return ENOBUFS; 4951 n->m_len = 0; 4952 last->m_next = n; 4953 last = n; 4954 } 4955 } 4956 4957 KDASSERT(!M_READONLY(last)); 4958 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4959 4960 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4961 memset(mtod(last, char *) + last->m_len, 0, padlen); 4962 last->m_len += padlen; 4963 pkt->m_pkthdr.len += padlen; 4964 return 0; 4965 } 4966 4967 /* 4968 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4969 */ 4970 static inline int 4971 bge_compact_dma_runt(struct mbuf *pkt) 4972 { 4973 struct mbuf *m, *prev; 4974 int totlen; 4975 4976 prev = NULL; 4977 totlen = 0; 4978 4979 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 4980 int mlen = m->m_len; 4981 int shortfall = 8 - mlen ; 4982 4983 totlen += mlen; 4984 if (mlen == 0) 4985 continue; 4986 if (mlen >= 8) 4987 continue; 4988 4989 /* If we get here, mbuf data is too small for DMA engine. 4990 * Try to fix by shuffling data to prev or next in chain. 4991 * If that fails, do a compacting deep-copy of the whole chain. 4992 */ 4993 4994 /* Internal frag. If fits in prev, copy it there. */ 4995 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4996 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4997 prev->m_len += mlen; 4998 m->m_len = 0; 4999 /* XXX stitch chain */ 5000 prev->m_next = m_free(m); 5001 m = prev; 5002 continue; 5003 } else if (m->m_next != NULL && 5004 M_TRAILINGSPACE(m) >= shortfall && 5005 m->m_next->m_len >= (8 + shortfall)) { 5006 /* m is writable and have enough data in next, pull up. */ 5007 5008 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5009 shortfall); 5010 m->m_len += shortfall; 5011 m->m_next->m_len -= shortfall; 5012 m->m_next->m_data += shortfall; 5013 } else if (m->m_next == NULL || 1) { 5014 /* Got a runt at the very end of the packet. 5015 * borrow data from the tail of the preceding mbuf and 5016 * update its length in-place. (The original data is 5017 * still valid, so we can do this even if prev is not 5018 * writable.) 5019 */ 5020 5021 /* 5022 * If we'd make prev a runt, just move all of its data. 5023 */ 5024 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5025 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5026 5027 if ((prev->m_len - shortfall) < 8) 5028 shortfall = prev->m_len; 5029 5030 #ifdef notyet /* just do the safe slow thing for now */ 5031 if (!M_READONLY(m)) { 5032 if (M_LEADINGSPACE(m) < shorfall) { 5033 void *m_dat; 5034 m_dat = M_BUFADDR(m); 5035 memmove(m_dat, mtod(m, void*), 5036 m->m_len); 5037 m->m_data = m_dat; 5038 } 5039 } else 5040 #endif /* just do the safe slow thing */ 5041 { 5042 struct mbuf * n = NULL; 5043 int newprevlen = prev->m_len - shortfall; 5044 5045 MGET(n, M_NOWAIT, MT_DATA); 5046 if (n == NULL) 5047 return ENOBUFS; 5048 KASSERT(m->m_len + shortfall < MLEN 5049 /*, 5050 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5051 5052 /* first copy the data we're stealing from prev */ 5053 memcpy(n->m_data, prev->m_data + newprevlen, 5054 shortfall); 5055 5056 /* update prev->m_len accordingly */ 5057 prev->m_len -= shortfall; 5058 5059 /* copy data from runt m */ 5060 memcpy(n->m_data + shortfall, m->m_data, 5061 m->m_len); 5062 5063 /* n holds what we stole from prev, plus m */ 5064 n->m_len = shortfall + m->m_len; 5065 5066 /* stitch n into chain and free m */ 5067 n->m_next = m->m_next; 5068 prev->m_next = n; 5069 /* KASSERT(m->m_next == NULL); */ 5070 m->m_next = NULL; 5071 m_free(m); 5072 m = n; /* for continuing loop */ 5073 } 5074 } 5075 } 5076 return 0; 5077 } 5078 5079 /* 5080 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5081 * pointers to descriptors. 5082 */ 5083 static int 5084 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5085 { 5086 struct ifnet * const ifp = &sc->ethercom.ec_if; 5087 struct bge_tx_bd *f, *prev_f; 5088 uint32_t frag, cur; 5089 uint16_t csum_flags = 0; 5090 uint16_t txbd_tso_flags = 0; 5091 struct txdmamap_pool_entry *dma; 5092 bus_dmamap_t dmamap; 5093 bus_dma_tag_t dmatag; 5094 int i = 0; 5095 int use_tso, maxsegsize, error; 5096 bool have_vtag; 5097 uint16_t vtag; 5098 bool remap; 5099 5100 if (m_head->m_pkthdr.csum_flags) { 5101 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5102 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5103 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5104 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5105 } 5106 5107 /* 5108 * If we were asked to do an outboard checksum, and the NIC 5109 * has the bug where it sometimes adds in the Ethernet padding, 5110 * explicitly pad with zeros so the cksum will be correct either way. 5111 * (For now, do this for all chip versions, until newer 5112 * are confirmed to not require the workaround.) 5113 */ 5114 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5115 #ifdef notyet 5116 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5117 #endif 5118 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5119 goto check_dma_bug; 5120 5121 if (bge_cksum_pad(m_head) != 0) 5122 return ENOBUFS; 5123 5124 check_dma_bug: 5125 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5126 goto doit; 5127 5128 /* 5129 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5130 * less than eight bytes. If we encounter a teeny mbuf 5131 * at the end of a chain, we can pad. Otherwise, copy. 5132 */ 5133 if (bge_compact_dma_runt(m_head) != 0) 5134 return ENOBUFS; 5135 5136 doit: 5137 dma = SLIST_FIRST(&sc->txdma_list); 5138 if (dma == NULL) { 5139 ifp->if_flags |= IFF_OACTIVE; 5140 return ENOBUFS; 5141 } 5142 dmamap = dma->dmamap; 5143 dmatag = sc->bge_dmatag; 5144 dma->is_dma32 = false; 5145 5146 /* 5147 * Set up any necessary TSO state before we start packing... 5148 */ 5149 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5150 if (!use_tso) { 5151 maxsegsize = 0; 5152 } else { /* TSO setup */ 5153 unsigned mss; 5154 struct ether_header *eh; 5155 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5156 unsigned bge_hlen; 5157 struct mbuf * m0 = m_head; 5158 struct ip *ip; 5159 struct tcphdr *th; 5160 int iphl, hlen; 5161 5162 /* 5163 * XXX It would be nice if the mbuf pkthdr had offset 5164 * fields for the protocol headers. 5165 */ 5166 5167 eh = mtod(m0, struct ether_header *); 5168 switch (htons(eh->ether_type)) { 5169 case ETHERTYPE_IP: 5170 offset = ETHER_HDR_LEN; 5171 break; 5172 5173 case ETHERTYPE_VLAN: 5174 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5175 break; 5176 5177 default: 5178 /* 5179 * Don't support this protocol or encapsulation. 5180 */ 5181 return ENOBUFS; 5182 } 5183 5184 /* 5185 * TCP/IP headers are in the first mbuf; we can do 5186 * this the easy way. 5187 */ 5188 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5189 hlen = iphl + offset; 5190 if (__predict_false(m0->m_len < 5191 (hlen + sizeof(struct tcphdr)))) { 5192 5193 aprint_error_dev(sc->bge_dev, 5194 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5195 "not handled yet\n", 5196 m0->m_len, hlen+ sizeof(struct tcphdr)); 5197 #ifdef NOTYET 5198 /* 5199 * XXX jonathan (at) NetBSD.org: untested. 5200 * how to force this branch to be taken? 5201 */ 5202 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5203 5204 m_copydata(m0, offset, sizeof(ip), &ip); 5205 m_copydata(m0, hlen, sizeof(th), &th); 5206 5207 ip.ip_len = 0; 5208 5209 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5210 sizeof(ip.ip_len), &ip.ip_len); 5211 5212 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5213 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5214 5215 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5216 sizeof(th.th_sum), &th.th_sum); 5217 5218 hlen += th.th_off << 2; 5219 iptcp_opt_words = hlen; 5220 #else 5221 /* 5222 * if_wm "hard" case not yet supported, can we not 5223 * mandate it out of existence? 5224 */ 5225 (void) ip; (void)th; (void) ip_tcp_hlen; 5226 5227 return ENOBUFS; 5228 #endif 5229 } else { 5230 ip = (struct ip *) (mtod(m0, char *) + offset); 5231 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5232 ip_tcp_hlen = iphl + (th->th_off << 2); 5233 5234 /* Total IP/TCP options, in 32-bit words */ 5235 iptcp_opt_words = (ip_tcp_hlen 5236 - sizeof(struct tcphdr) 5237 - sizeof(struct ip)) >> 2; 5238 } 5239 if (BGE_IS_575X_PLUS(sc)) { 5240 th->th_sum = 0; 5241 csum_flags = 0; 5242 } else { 5243 /* 5244 * XXX jonathan (at) NetBSD.org: 5705 untested. 5245 * Requires TSO firmware patch for 5701/5703/5704. 5246 */ 5247 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5248 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5249 } 5250 5251 mss = m_head->m_pkthdr.segsz; 5252 txbd_tso_flags |= 5253 BGE_TXBDFLAG_CPU_PRE_DMA | 5254 BGE_TXBDFLAG_CPU_POST_DMA; 5255 5256 /* 5257 * Our NIC TSO-assist assumes TSO has standard, optionless 5258 * IPv4 and TCP headers, which total 40 bytes. By default, 5259 * the NIC copies 40 bytes of IP/TCP header from the 5260 * supplied header into the IP/TCP header portion of 5261 * each post-TSO-segment. If the supplied packet has IP or 5262 * TCP options, we need to tell the NIC to copy those extra 5263 * bytes into each post-TSO header, in addition to the normal 5264 * 40-byte IP/TCP header (and to leave space accordingly). 5265 * Unfortunately, the driver encoding of option length 5266 * varies across different ASIC families. 5267 */ 5268 tcp_seg_flags = 0; 5269 bge_hlen = ip_tcp_hlen >> 2; 5270 if (BGE_IS_5717_PLUS(sc)) { 5271 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5272 txbd_tso_flags |= 5273 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5274 } else if (BGE_IS_5705_PLUS(sc)) { 5275 tcp_seg_flags = bge_hlen << 11; 5276 } else { 5277 /* XXX iptcp_opt_words or bge_hlen ? */ 5278 txbd_tso_flags |= iptcp_opt_words << 12; 5279 } 5280 maxsegsize = mss | tcp_seg_flags; 5281 ip->ip_len = htons(mss + ip_tcp_hlen); 5282 ip->ip_sum = 0; 5283 5284 } /* TSO setup */ 5285 5286 have_vtag = vlan_has_tag(m_head); 5287 if (have_vtag) 5288 vtag = vlan_get_tag(m_head); 5289 5290 /* 5291 * Start packing the mbufs in this chain into 5292 * the fragment pointers. Stop when we run out 5293 * of fragments or hit the end of the mbuf chain. 5294 */ 5295 remap = true; 5296 load_again: 5297 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5298 if (__predict_false(error)) { 5299 if (error == EFBIG && remap) { 5300 struct mbuf *m; 5301 remap = false; 5302 m = m_defrag(m_head, M_NOWAIT); 5303 if (m != NULL) { 5304 KASSERT(m == m_head); 5305 goto load_again; 5306 } 5307 } 5308 return error; 5309 } 5310 /* 5311 * Sanity check: avoid coming within 16 descriptors 5312 * of the end of the ring. 5313 */ 5314 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5315 BGE_TSO_PRINTF(("%s: " 5316 " dmamap_load_mbuf too close to ring wrap\n", 5317 device_xname(sc->bge_dev))); 5318 goto fail_unload; 5319 } 5320 5321 /* Iterate over dmap-map fragments. */ 5322 f = prev_f = NULL; 5323 cur = frag = *txidx; 5324 5325 for (i = 0; i < dmamap->dm_nsegs; i++) { 5326 f = &sc->bge_rdata->bge_tx_ring[frag]; 5327 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5328 break; 5329 5330 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5331 f->bge_len = dmamap->dm_segs[i].ds_len; 5332 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5333 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5334 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5335 (prev_f != NULL && 5336 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5337 ) { 5338 /* 5339 * watchdog timeout issue was observed with TSO, 5340 * limiting DMA address space to 32bits seems to 5341 * address the issue. 5342 */ 5343 bus_dmamap_unload(dmatag, dmamap); 5344 dmatag = sc->bge_dmatag32; 5345 dmamap = dma->dmamap32; 5346 dma->is_dma32 = true; 5347 remap = true; 5348 goto load_again; 5349 } 5350 5351 /* 5352 * For 5751 and follow-ons, for TSO we must turn 5353 * off checksum-assist flag in the tx-descr, and 5354 * supply the ASIC-revision-specific encoding 5355 * of TSO flags and segsize. 5356 */ 5357 if (use_tso) { 5358 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5359 f->bge_rsvd = maxsegsize; 5360 f->bge_flags = csum_flags | txbd_tso_flags; 5361 } else { 5362 f->bge_rsvd = 0; 5363 f->bge_flags = 5364 (csum_flags | txbd_tso_flags) & 0x0fff; 5365 } 5366 } else { 5367 f->bge_rsvd = 0; 5368 f->bge_flags = csum_flags; 5369 } 5370 5371 if (have_vtag) { 5372 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5373 f->bge_vlan_tag = vtag; 5374 } else { 5375 f->bge_vlan_tag = 0; 5376 } 5377 prev_f = f; 5378 cur = frag; 5379 BGE_INC(frag, BGE_TX_RING_CNT); 5380 } 5381 5382 if (i < dmamap->dm_nsegs) { 5383 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5384 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5385 goto fail_unload; 5386 } 5387 5388 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5389 BUS_DMASYNC_PREWRITE); 5390 5391 if (frag == sc->bge_tx_saved_considx) { 5392 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5393 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5394 5395 goto fail_unload; 5396 } 5397 5398 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5399 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5400 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5401 sc->txdma[cur] = dma; 5402 sc->bge_txcnt += dmamap->dm_nsegs; 5403 5404 *txidx = frag; 5405 5406 return 0; 5407 5408 fail_unload: 5409 bus_dmamap_unload(dmatag, dmamap); 5410 ifp->if_flags |= IFF_OACTIVE; 5411 5412 return ENOBUFS; 5413 } 5414 5415 /* 5416 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5417 * to the mbuf data regions directly in the transmit descriptors. 5418 */ 5419 static void 5420 bge_start(struct ifnet *ifp) 5421 { 5422 struct bge_softc * const sc = ifp->if_softc; 5423 struct mbuf *m_head = NULL; 5424 struct mbuf *m; 5425 uint32_t prodidx; 5426 int pkts = 0; 5427 int error; 5428 5429 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5430 return; 5431 5432 prodidx = sc->bge_tx_prodidx; 5433 5434 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5435 IFQ_POLL(&ifp->if_snd, m_head); 5436 if (m_head == NULL) 5437 break; 5438 5439 #if 0 5440 /* 5441 * XXX 5442 * safety overkill. If this is a fragmented packet chain 5443 * with delayed TCP/UDP checksums, then only encapsulate 5444 * it if we have enough descriptors to handle the entire 5445 * chain at once. 5446 * (paranoia -- may not actually be needed) 5447 */ 5448 if (m_head->m_flags & M_FIRSTFRAG && 5449 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5450 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5451 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5452 ifp->if_flags |= IFF_OACTIVE; 5453 break; 5454 } 5455 } 5456 #endif 5457 5458 /* 5459 * Pack the data into the transmit ring. If we 5460 * don't have room, set the OACTIVE flag and wait 5461 * for the NIC to drain the ring. 5462 */ 5463 error = bge_encap(sc, m_head, &prodidx); 5464 if (__predict_false(error)) { 5465 if (ifp->if_flags & IFF_OACTIVE) { 5466 /* just wait for the transmit ring to drain */ 5467 break; 5468 } 5469 IFQ_DEQUEUE(&ifp->if_snd, m); 5470 KASSERT(m == m_head); 5471 m_freem(m_head); 5472 continue; 5473 } 5474 5475 /* now we are committed to transmit the packet */ 5476 IFQ_DEQUEUE(&ifp->if_snd, m); 5477 KASSERT(m == m_head); 5478 pkts++; 5479 5480 /* 5481 * If there's a BPF listener, bounce a copy of this frame 5482 * to him. 5483 */ 5484 bpf_mtap(ifp, m_head, BPF_D_OUT); 5485 } 5486 if (pkts == 0) 5487 return; 5488 5489 /* Transmit */ 5490 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5491 /* 5700 b2 errata */ 5492 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5493 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5494 5495 sc->bge_tx_prodidx = prodidx; 5496 5497 /* 5498 * Set a timeout in case the chip goes out to lunch. 5499 */ 5500 ifp->if_timer = 5; 5501 } 5502 5503 static int 5504 bge_init(struct ifnet *ifp) 5505 { 5506 struct bge_softc * const sc = ifp->if_softc; 5507 const uint16_t *m; 5508 uint32_t mode, reg; 5509 int s, error = 0; 5510 5511 s = splnet(); 5512 5513 ifp = &sc->ethercom.ec_if; 5514 5515 /* Cancel pending I/O and flush buffers. */ 5516 bge_stop(ifp, 0); 5517 5518 bge_stop_fw(sc); 5519 bge_sig_pre_reset(sc, BGE_RESET_START); 5520 bge_reset(sc); 5521 bge_sig_legacy(sc, BGE_RESET_START); 5522 5523 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5524 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5525 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5526 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5527 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5528 5529 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5530 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5531 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5532 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5533 5534 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5535 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5536 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5537 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5538 5539 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5540 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5541 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5542 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5543 } 5544 5545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5546 pcireg_t aercap; 5547 5548 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5549 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5550 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5551 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5552 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5553 5554 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5555 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5556 | BGE_PCIE_EIDLE_DELAY_13CLK; 5557 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5558 5559 /* Clear correctable error */ 5560 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5561 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5562 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5563 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5564 5565 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5566 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5567 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5568 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5569 } 5570 5571 bge_sig_post_reset(sc, BGE_RESET_START); 5572 5573 bge_chipinit(sc); 5574 5575 /* 5576 * Init the various state machines, ring 5577 * control blocks and firmware. 5578 */ 5579 error = bge_blockinit(sc); 5580 if (error != 0) { 5581 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5582 error); 5583 splx(s); 5584 return error; 5585 } 5586 5587 ifp = &sc->ethercom.ec_if; 5588 5589 /* 5718 step 25, 57XX step 54 */ 5590 /* Specify MTU. */ 5591 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5592 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5593 5594 /* 5718 step 23 */ 5595 /* Load our MAC address. */ 5596 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5597 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5598 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5599 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5600 5601 /* Enable or disable promiscuous mode as needed. */ 5602 if (ifp->if_flags & IFF_PROMISC) 5603 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5604 else 5605 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5606 5607 /* Program multicast filter. */ 5608 bge_setmulti(sc); 5609 5610 /* Init RX ring. */ 5611 bge_init_rx_ring_std(sc); 5612 5613 /* 5614 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5615 * memory to insure that the chip has in fact read the first 5616 * entry of the ring. 5617 */ 5618 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5619 uint32_t v, i; 5620 for (i = 0; i < 10; i++) { 5621 DELAY(20); 5622 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5623 if (v == (MCLBYTES - ETHER_ALIGN)) 5624 break; 5625 } 5626 if (i == 10) 5627 aprint_error_dev(sc->bge_dev, 5628 "5705 A0 chip failed to load RX ring\n"); 5629 } 5630 5631 /* Init jumbo RX ring. */ 5632 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5633 bge_init_rx_ring_jumbo(sc); 5634 5635 /* Init our RX return ring index */ 5636 sc->bge_rx_saved_considx = 0; 5637 5638 /* Init TX ring. */ 5639 bge_init_tx_ring(sc); 5640 5641 /* 5718 step 63, 57XX step 94 */ 5642 /* Enable TX MAC state machine lockup fix. */ 5643 mode = CSR_READ_4(sc, BGE_TX_MODE); 5644 if (BGE_IS_5755_PLUS(sc) || 5645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5646 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5647 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5648 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5649 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5650 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5651 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5652 } 5653 5654 /* Turn on transmitter */ 5655 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5656 /* 5718 step 64 */ 5657 DELAY(100); 5658 5659 /* 5718 step 65, 57XX step 95 */ 5660 /* Turn on receiver */ 5661 mode = CSR_READ_4(sc, BGE_RX_MODE); 5662 if (BGE_IS_5755_PLUS(sc)) 5663 mode |= BGE_RXMODE_IPV6_ENABLE; 5664 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5665 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5666 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5667 /* 5718 step 66 */ 5668 DELAY(10); 5669 5670 /* 5718 step 12, 57XX step 37 */ 5671 /* 5672 * XXX Doucments of 5718 series and 577xx say the recommended value 5673 * is 1, but tg3 set 1 only on 57765 series. 5674 */ 5675 if (BGE_IS_57765_PLUS(sc)) 5676 reg = 1; 5677 else 5678 reg = 2; 5679 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5680 5681 /* Tell firmware we're alive. */ 5682 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5683 5684 /* Enable host interrupts. */ 5685 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5686 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5687 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5688 5689 if ((error = bge_ifmedia_upd(ifp)) != 0) 5690 goto out; 5691 5692 ifp->if_flags |= IFF_RUNNING; 5693 ifp->if_flags &= ~IFF_OACTIVE; 5694 5695 callout_schedule(&sc->bge_timeout, hz); 5696 5697 out: 5698 sc->bge_if_flags = ifp->if_flags; 5699 splx(s); 5700 5701 return error; 5702 } 5703 5704 /* 5705 * Set media options. 5706 */ 5707 static int 5708 bge_ifmedia_upd(struct ifnet *ifp) 5709 { 5710 struct bge_softc * const sc = ifp->if_softc; 5711 struct mii_data * const mii = &sc->bge_mii; 5712 struct ifmedia * const ifm = &sc->bge_ifmedia; 5713 int rc; 5714 5715 /* If this is a 1000baseX NIC, enable the TBI port. */ 5716 if (sc->bge_flags & BGEF_FIBER_TBI) { 5717 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5718 return EINVAL; 5719 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5720 case IFM_AUTO: 5721 /* 5722 * The BCM5704 ASIC appears to have a special 5723 * mechanism for programming the autoneg 5724 * advertisement registers in TBI mode. 5725 */ 5726 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5727 uint32_t sgdig; 5728 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5729 if (sgdig & BGE_SGDIGSTS_DONE) { 5730 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5731 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5732 sgdig |= BGE_SGDIGCFG_AUTO | 5733 BGE_SGDIGCFG_PAUSE_CAP | 5734 BGE_SGDIGCFG_ASYM_PAUSE; 5735 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5736 sgdig | BGE_SGDIGCFG_SEND); 5737 DELAY(5); 5738 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5739 sgdig); 5740 } 5741 } 5742 break; 5743 case IFM_1000_SX: 5744 if ((ifm->ifm_media & IFM_FDX) != 0) { 5745 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5746 BGE_MACMODE_HALF_DUPLEX); 5747 } else { 5748 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5749 BGE_MACMODE_HALF_DUPLEX); 5750 } 5751 DELAY(40); 5752 break; 5753 default: 5754 return EINVAL; 5755 } 5756 /* XXX 802.3x flow control for 1000BASE-SX */ 5757 return 0; 5758 } 5759 5760 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5761 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5762 uint32_t reg; 5763 5764 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5765 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5766 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5767 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5768 } 5769 } 5770 5771 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5772 if ((rc = mii_mediachg(mii)) == ENXIO) 5773 return 0; 5774 5775 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5776 uint32_t reg; 5777 5778 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5779 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5780 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5781 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5782 delay(40); 5783 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5784 } 5785 } 5786 5787 /* 5788 * Force an interrupt so that we will call bge_link_upd 5789 * if needed and clear any pending link state attention. 5790 * Without this we are not getting any further interrupts 5791 * for link state changes and thus will not UP the link and 5792 * not be able to send in bge_start. The only way to get 5793 * things working was to receive a packet and get a RX intr. 5794 */ 5795 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5796 sc->bge_flags & BGEF_IS_5788) 5797 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5798 else 5799 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5800 5801 return rc; 5802 } 5803 5804 /* 5805 * Report current media status. 5806 */ 5807 static void 5808 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5809 { 5810 struct bge_softc * const sc = ifp->if_softc; 5811 struct mii_data * const mii = &sc->bge_mii; 5812 5813 if (sc->bge_flags & BGEF_FIBER_TBI) { 5814 ifmr->ifm_status = IFM_AVALID; 5815 ifmr->ifm_active = IFM_ETHER; 5816 if (CSR_READ_4(sc, BGE_MAC_STS) & 5817 BGE_MACSTAT_TBI_PCS_SYNCHED) 5818 ifmr->ifm_status |= IFM_ACTIVE; 5819 ifmr->ifm_active |= IFM_1000_SX; 5820 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5821 ifmr->ifm_active |= IFM_HDX; 5822 else 5823 ifmr->ifm_active |= IFM_FDX; 5824 return; 5825 } 5826 5827 mii_pollstat(mii); 5828 ifmr->ifm_status = mii->mii_media_status; 5829 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5830 sc->bge_flowflags; 5831 } 5832 5833 static int 5834 bge_ifflags_cb(struct ethercom *ec) 5835 { 5836 struct ifnet * const ifp = &ec->ec_if; 5837 struct bge_softc * const sc = ifp->if_softc; 5838 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5839 5840 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 5841 return ENETRESET; 5842 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5843 return 0; 5844 5845 if ((ifp->if_flags & IFF_PROMISC) == 0) 5846 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5847 else 5848 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5849 5850 bge_setmulti(sc); 5851 5852 sc->bge_if_flags = ifp->if_flags; 5853 return 0; 5854 } 5855 5856 static int 5857 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5858 { 5859 struct bge_softc * const sc = ifp->if_softc; 5860 struct ifreq * const ifr = (struct ifreq *) data; 5861 int s, error = 0; 5862 struct mii_data *mii; 5863 5864 s = splnet(); 5865 5866 switch (command) { 5867 case SIOCSIFMEDIA: 5868 /* XXX Flow control is not supported for 1000BASE-SX */ 5869 if (sc->bge_flags & BGEF_FIBER_TBI) { 5870 ifr->ifr_media &= ~IFM_ETH_FMASK; 5871 sc->bge_flowflags = 0; 5872 } 5873 5874 /* Flow control requires full-duplex mode. */ 5875 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5876 (ifr->ifr_media & IFM_FDX) == 0) { 5877 ifr->ifr_media &= ~IFM_ETH_FMASK; 5878 } 5879 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5880 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5881 /* We can do both TXPAUSE and RXPAUSE. */ 5882 ifr->ifr_media |= 5883 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5884 } 5885 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5886 } 5887 5888 if (sc->bge_flags & BGEF_FIBER_TBI) { 5889 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5890 command); 5891 } else { 5892 mii = &sc->bge_mii; 5893 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5894 command); 5895 } 5896 break; 5897 default: 5898 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5899 break; 5900 5901 error = 0; 5902 5903 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5904 ; 5905 else if (ifp->if_flags & IFF_RUNNING) 5906 bge_setmulti(sc); 5907 break; 5908 } 5909 5910 splx(s); 5911 5912 return error; 5913 } 5914 5915 static void 5916 bge_watchdog(struct ifnet *ifp) 5917 { 5918 struct bge_softc * const sc = ifp->if_softc; 5919 uint32_t status; 5920 5921 /* If pause frames are active then don't reset the hardware. */ 5922 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5923 status = CSR_READ_4(sc, BGE_RX_STS); 5924 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5925 /* 5926 * If link partner has us in XOFF state then wait for 5927 * the condition to clear. 5928 */ 5929 CSR_WRITE_4(sc, BGE_RX_STS, status); 5930 ifp->if_timer = 5; 5931 return; 5932 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5933 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5934 /* 5935 * If link partner has us in XOFF state then wait for 5936 * the condition to clear. 5937 */ 5938 CSR_WRITE_4(sc, BGE_RX_STS, status); 5939 ifp->if_timer = 5; 5940 return; 5941 } 5942 /* 5943 * Any other condition is unexpected and the controller 5944 * should be reset. 5945 */ 5946 } 5947 5948 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5949 5950 ifp->if_flags &= ~IFF_RUNNING; 5951 bge_init(ifp); 5952 5953 if_statinc(ifp, if_oerrors); 5954 } 5955 5956 static void 5957 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5958 { 5959 int i; 5960 5961 BGE_CLRBIT_FLUSH(sc, reg, bit); 5962 5963 for (i = 0; i < 1000; i++) { 5964 delay(100); 5965 if ((CSR_READ_4(sc, reg) & bit) == 0) 5966 return; 5967 } 5968 5969 /* 5970 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5971 * on some environment (and once after boot?) 5972 */ 5973 if (reg != BGE_SRS_MODE) 5974 aprint_error_dev(sc->bge_dev, 5975 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5976 (u_long)reg, bit); 5977 } 5978 5979 /* 5980 * Stop the adapter and free any mbufs allocated to the 5981 * RX and TX lists. 5982 */ 5983 static void 5984 bge_stop(struct ifnet *ifp, int disable) 5985 { 5986 struct bge_softc * const sc = ifp->if_softc; 5987 5988 if (disable) { 5989 sc->bge_detaching = 1; 5990 callout_halt(&sc->bge_timeout, NULL); 5991 } else 5992 callout_stop(&sc->bge_timeout); 5993 5994 /* Disable host interrupts. */ 5995 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5996 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5997 5998 /* 5999 * Tell firmware we're shutting down. 6000 */ 6001 bge_stop_fw(sc); 6002 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6003 6004 /* 6005 * Disable all of the receiver blocks. 6006 */ 6007 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6008 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6009 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6010 if (BGE_IS_5700_FAMILY(sc)) 6011 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6012 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6013 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6014 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6015 6016 /* 6017 * Disable all of the transmit blocks. 6018 */ 6019 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6020 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6021 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6022 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6023 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6024 if (BGE_IS_5700_FAMILY(sc)) 6025 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6026 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6027 6028 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6029 delay(40); 6030 6031 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6032 6033 /* 6034 * Shut down all of the memory managers and related 6035 * state machines. 6036 */ 6037 /* 5718 step 5a,5b */ 6038 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6039 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6040 if (BGE_IS_5700_FAMILY(sc)) 6041 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6042 6043 /* 5718 step 5c,5d */ 6044 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6045 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6046 6047 if (BGE_IS_5700_FAMILY(sc)) { 6048 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6049 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6050 } 6051 6052 bge_reset(sc); 6053 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6054 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6055 6056 /* 6057 * Keep the ASF firmware running if up. 6058 */ 6059 if (sc->bge_asf_mode & ASF_STACKUP) 6060 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6061 else 6062 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6063 6064 /* Free the RX lists. */ 6065 bge_free_rx_ring_std(sc, disable); 6066 6067 /* Free jumbo RX list. */ 6068 if (BGE_IS_JUMBO_CAPABLE(sc)) 6069 bge_free_rx_ring_jumbo(sc); 6070 6071 /* Free TX buffers. */ 6072 bge_free_tx_ring(sc, disable); 6073 6074 /* 6075 * Isolate/power down the PHY. 6076 */ 6077 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6078 mii_down(&sc->bge_mii); 6079 6080 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6081 6082 /* Clear MAC's link state (PHY may still have link UP). */ 6083 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6084 6085 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6086 } 6087 6088 static void 6089 bge_link_upd(struct bge_softc *sc) 6090 { 6091 struct ifnet * const ifp = &sc->ethercom.ec_if; 6092 struct mii_data * const mii = &sc->bge_mii; 6093 uint32_t status; 6094 uint16_t phyval; 6095 int link; 6096 6097 /* Clear 'pending link event' flag */ 6098 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6099 6100 /* 6101 * Process link state changes. 6102 * Grrr. The link status word in the status block does 6103 * not work correctly on the BCM5700 rev AX and BX chips, 6104 * according to all available information. Hence, we have 6105 * to enable MII interrupts in order to properly obtain 6106 * async link changes. Unfortunately, this also means that 6107 * we have to read the MAC status register to detect link 6108 * changes, thereby adding an additional register access to 6109 * the interrupt handler. 6110 */ 6111 6112 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6113 status = CSR_READ_4(sc, BGE_MAC_STS); 6114 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6115 mii_pollstat(mii); 6116 6117 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6118 mii->mii_media_status & IFM_ACTIVE && 6119 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6120 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6121 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6122 (!(mii->mii_media_status & IFM_ACTIVE) || 6123 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6124 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6125 6126 /* Clear the interrupt */ 6127 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6128 BGE_EVTENB_MI_INTERRUPT); 6129 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6130 BRGPHY_MII_ISR, &phyval); 6131 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6132 BRGPHY_MII_IMR, BRGPHY_INTRS); 6133 } 6134 return; 6135 } 6136 6137 if (sc->bge_flags & BGEF_FIBER_TBI) { 6138 status = CSR_READ_4(sc, BGE_MAC_STS); 6139 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6140 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6141 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6142 if (BGE_ASICREV(sc->bge_chipid) 6143 == BGE_ASICREV_BCM5704) { 6144 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6145 BGE_MACMODE_TBI_SEND_CFGS); 6146 DELAY(40); 6147 } 6148 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6149 if_link_state_change(ifp, LINK_STATE_UP); 6150 } 6151 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6152 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6153 if_link_state_change(ifp, LINK_STATE_DOWN); 6154 } 6155 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6156 /* 6157 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6158 * bit in status word always set. Workaround this bug by 6159 * reading PHY link status directly. 6160 */ 6161 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6162 BGE_STS_LINK : 0; 6163 6164 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6165 mii_pollstat(mii); 6166 6167 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6168 mii->mii_media_status & IFM_ACTIVE && 6169 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6170 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6171 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6172 (!(mii->mii_media_status & IFM_ACTIVE) || 6173 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6174 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6175 } 6176 } else { 6177 /* 6178 * For controllers that call mii_tick, we have to poll 6179 * link status. 6180 */ 6181 mii_pollstat(mii); 6182 } 6183 6184 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6185 uint32_t reg, scale; 6186 6187 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6188 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6189 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6190 scale = 65; 6191 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6192 scale = 6; 6193 else 6194 scale = 12; 6195 6196 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6197 ~BGE_MISCCFG_TIMER_PRESCALER; 6198 reg |= scale << 1; 6199 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6200 } 6201 /* Clear the attention */ 6202 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6203 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6204 BGE_MACSTAT_LINK_CHANGED); 6205 } 6206 6207 static int 6208 bge_sysctl_verify(SYSCTLFN_ARGS) 6209 { 6210 int error, t; 6211 struct sysctlnode node; 6212 6213 node = *rnode; 6214 t = *(int*)rnode->sysctl_data; 6215 node.sysctl_data = &t; 6216 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6217 if (error || newp == NULL) 6218 return error; 6219 6220 #if 0 6221 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6222 node.sysctl_num, rnode->sysctl_num)); 6223 #endif 6224 6225 if (node.sysctl_num == bge_rxthresh_nodenum) { 6226 if (t < 0 || t >= NBGE_RX_THRESH) 6227 return EINVAL; 6228 bge_update_all_threshes(t); 6229 } else 6230 return EINVAL; 6231 6232 *(int*)rnode->sysctl_data = t; 6233 6234 return 0; 6235 } 6236 6237 /* 6238 * Set up sysctl(3) MIB, hw.bge.*. 6239 */ 6240 static void 6241 bge_sysctl_init(struct bge_softc *sc) 6242 { 6243 int rc, bge_root_num; 6244 const struct sysctlnode *node; 6245 6246 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6247 0, CTLTYPE_NODE, "bge", 6248 SYSCTL_DESCR("BGE interface controls"), 6249 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6250 goto out; 6251 } 6252 6253 bge_root_num = node->sysctl_num; 6254 6255 /* BGE Rx interrupt mitigation level */ 6256 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6257 CTLFLAG_READWRITE, 6258 CTLTYPE_INT, "rx_lvl", 6259 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6260 bge_sysctl_verify, 0, 6261 &bge_rx_thresh_lvl, 6262 0, CTL_HW, bge_root_num, CTL_CREATE, 6263 CTL_EOL)) != 0) { 6264 goto out; 6265 } 6266 6267 bge_rxthresh_nodenum = node->sysctl_num; 6268 6269 return; 6270 6271 out: 6272 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6273 } 6274 6275 #ifdef BGE_DEBUG 6276 void 6277 bge_debug_info(struct bge_softc *sc) 6278 { 6279 6280 printf("Hardware Flags:\n"); 6281 if (BGE_IS_57765_PLUS(sc)) 6282 printf(" - 57765 Plus\n"); 6283 if (BGE_IS_5717_PLUS(sc)) 6284 printf(" - 5717 Plus\n"); 6285 if (BGE_IS_5755_PLUS(sc)) 6286 printf(" - 5755 Plus\n"); 6287 if (BGE_IS_575X_PLUS(sc)) 6288 printf(" - 575X Plus\n"); 6289 if (BGE_IS_5705_PLUS(sc)) 6290 printf(" - 5705 Plus\n"); 6291 if (BGE_IS_5714_FAMILY(sc)) 6292 printf(" - 5714 Family\n"); 6293 if (BGE_IS_5700_FAMILY(sc)) 6294 printf(" - 5700 Family\n"); 6295 if (sc->bge_flags & BGEF_IS_5788) 6296 printf(" - 5788\n"); 6297 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6298 printf(" - Supports Jumbo Frames\n"); 6299 if (sc->bge_flags & BGEF_NO_EEPROM) 6300 printf(" - No EEPROM\n"); 6301 if (sc->bge_flags & BGEF_PCIX) 6302 printf(" - PCI-X Bus\n"); 6303 if (sc->bge_flags & BGEF_PCIE) 6304 printf(" - PCI Express Bus\n"); 6305 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6306 printf(" - RX Alignment Bug\n"); 6307 if (sc->bge_flags & BGEF_APE) 6308 printf(" - APE\n"); 6309 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6310 printf(" - CPMU\n"); 6311 if (sc->bge_flags & BGEF_TSO) 6312 printf(" - TSO\n"); 6313 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6314 printf(" - TAGGED_STATUS\n"); 6315 6316 /* PHY related */ 6317 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6318 printf(" - No 3 LEDs\n"); 6319 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6320 printf(" - CRC bug\n"); 6321 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6322 printf(" - ADC bug\n"); 6323 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6324 printf(" - 5704 A0 bug\n"); 6325 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6326 printf(" - jitter bug\n"); 6327 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6328 printf(" - BER bug\n"); 6329 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6330 printf(" - adjust trim\n"); 6331 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6332 printf(" - no wirespeed\n"); 6333 6334 /* ASF related */ 6335 if (sc->bge_asf_mode & ASF_ENABLE) 6336 printf(" - ASF enable\n"); 6337 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6338 printf(" - ASF new handshake\n"); 6339 if (sc->bge_asf_mode & ASF_STACKUP) 6340 printf(" - ASF stackup\n"); 6341 } 6342 #endif /* BGE_DEBUG */ 6343 6344 static int 6345 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6346 { 6347 prop_dictionary_t dict; 6348 prop_data_t ea; 6349 6350 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6351 return 1; 6352 6353 dict = device_properties(sc->bge_dev); 6354 ea = prop_dictionary_get(dict, "mac-address"); 6355 if (ea != NULL) { 6356 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6357 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6358 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6359 return 0; 6360 } 6361 6362 return 1; 6363 } 6364 6365 static int 6366 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6367 { 6368 uint32_t mac_addr; 6369 6370 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6371 if ((mac_addr >> 16) == 0x484b) { 6372 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6373 ether_addr[1] = (uint8_t)mac_addr; 6374 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6375 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6376 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6377 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6378 ether_addr[5] = (uint8_t)mac_addr; 6379 return 0; 6380 } 6381 return 1; 6382 } 6383 6384 static int 6385 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6386 { 6387 int mac_offset = BGE_EE_MAC_OFFSET; 6388 6389 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6390 mac_offset = BGE_EE_MAC_OFFSET_5906; 6391 6392 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6393 ETHER_ADDR_LEN)); 6394 } 6395 6396 static int 6397 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6398 { 6399 6400 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6401 return 1; 6402 6403 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6404 ETHER_ADDR_LEN)); 6405 } 6406 6407 static int 6408 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6409 { 6410 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6411 /* NOTE: Order is critical */ 6412 bge_get_eaddr_fw, 6413 bge_get_eaddr_mem, 6414 bge_get_eaddr_nvram, 6415 bge_get_eaddr_eeprom, 6416 NULL 6417 }; 6418 const bge_eaddr_fcn_t *func; 6419 6420 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6421 if ((*func)(sc, eaddr) == 0) 6422 break; 6423 } 6424 return (*func == NULL ? ENXIO : 0); 6425 } 6426
Indexes created Thu Sep 25 02:09:54 GMT 2025