if_bge.c revision 1.357
1 /* $NetBSD: if_bge.c,v 1.357 2022/06/30 19:06:35 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.357 2022/06/30 19:06:35 skrll Exp $"); 83 84 #include <sys/param.h> 85 86 #include <sys/callout.h> 87 #include <sys/device.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/kernel.h> 91 #include <sys/rndsource.h> 92 #include <sys/socket.h> 93 #include <sys/sockio.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 #include <net/bpf.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 #include <dev/mii/miidevs.h> 123 #include <dev/mii/brgphyreg.h> 124 125 #include <dev/pci/if_bgereg.h> 126 #include <dev/pci/if_bgevar.h> 127 128 #include <prop/proplib.h> 129 130 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 131 132 133 /* 134 * Tunable thresholds for rx-side bge interrupt mitigation. 135 */ 136 137 /* 138 * The pairs of values below were obtained from empirical measurement 139 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 140 * interrupt for every N packets received, where N is, approximately, 141 * the second value (rx_max_bds) in each pair. The values are chosen 142 * such that moving from one pair to the succeeding pair was observed 143 * to roughly halve interrupt rate under sustained input packet load. 144 * The values were empirically chosen to avoid overflowing internal 145 * limits on the bcm5700: increasing rx_ticks much beyond 600 146 * results in internal wrapping and higher interrupt rates. 147 * The limit of 46 frames was chosen to match NFS workloads. 148 * 149 * These values also work well on bcm5701, bcm5704C, and (less 150 * tested) bcm5703. On other chipsets, (including the Altima chip 151 * family), the larger values may overflow internal chip limits, 152 * leading to increasing interrupt rates rather than lower interrupt 153 * rates. 154 * 155 * Applications using heavy interrupt mitigation (interrupting every 156 * 32 or 46 frames) in both directions may need to increase the TCP 157 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 158 * full link bandwidth, due to ACKs and window updates lingering 159 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 160 */ 161 static const struct bge_load_rx_thresh { 162 int rx_ticks; 163 int rx_max_bds; } 164 bge_rx_threshes[] = { 165 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 166 { 32, 2 }, 167 { 50, 4 }, 168 { 100, 8 }, 169 { 192, 16 }, 170 { 416, 32 }, 171 { 598, 46 } 172 }; 173 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 174 175 /* XXX patchable; should be sysctl'able */ 176 static int bge_auto_thresh = 1; 177 static int bge_rx_thresh_lvl; 178 179 static int bge_rxthresh_nodenum; 180 181 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 182 183 static uint32_t bge_chipid(const struct pci_attach_args *); 184 static int bge_can_use_msi(struct bge_softc *); 185 static int bge_probe(device_t, cfdata_t, void *); 186 static void bge_attach(device_t, device_t, void *); 187 static int bge_detach(device_t, int); 188 static void bge_release_resources(struct bge_softc *); 189 190 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 191 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 195 196 static void bge_txeof(struct bge_softc *); 197 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *m, bool); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_phy_addr(struct bge_softc *); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writembx_flush(struct bge_softc *, int, int); 247 static void bge_writemem_direct(struct bge_softc *, int, int); 248 static void bge_writereg_ind(struct bge_softc *, int, int); 249 static void bge_set_max_readrq(struct bge_softc *); 250 251 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 252 static int bge_miibus_writereg(device_t, int, int, uint16_t); 253 static void bge_miibus_statchg(struct ifnet *); 254 255 #define BGE_RESET_SHUTDOWN 0 256 #define BGE_RESET_START 1 257 #define BGE_RESET_SUSPEND 2 258 static void bge_sig_post_reset(struct bge_softc *, int); 259 static void bge_sig_legacy(struct bge_softc *, int); 260 static void bge_sig_pre_reset(struct bge_softc *, int); 261 static void bge_wait_for_event_ack(struct bge_softc *); 262 static void bge_stop_fw(struct bge_softc *); 263 static int bge_reset(struct bge_softc *); 264 static void bge_link_upd(struct bge_softc *); 265 static void bge_sysctl_init(struct bge_softc *); 266 static int bge_sysctl_verify(SYSCTLFN_PROTO); 267 268 static void bge_ape_lock_init(struct bge_softc *); 269 static void bge_ape_read_fw_ver(struct bge_softc *); 270 static int bge_ape_lock(struct bge_softc *, int); 271 static void bge_ape_unlock(struct bge_softc *, int); 272 static void bge_ape_send_event(struct bge_softc *, uint32_t); 273 static void bge_ape_driver_state_change(struct bge_softc *, int); 274 275 #ifdef BGE_DEBUG 276 #define DPRINTF(x) if (bgedebug) printf x 277 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 278 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 279 int bgedebug = 0; 280 int bge_tso_debug = 0; 281 void bge_debug_info(struct bge_softc *); 282 #else 283 #define DPRINTF(x) 284 #define DPRINTFN(n, x) 285 #define BGE_TSO_PRINTF(x) 286 #endif 287 288 #ifdef BGE_EVENT_COUNTERS 289 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 290 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 291 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 292 #else 293 #define BGE_EVCNT_INCR(ev) /* nothing */ 294 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 295 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 296 #endif 297 298 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 299 /* 300 * The BCM5700 documentation seems to indicate that the hardware still has the 301 * Alteon vendor ID burned into it, though it should always be overridden by 302 * the value in the EEPROM. We'll check for it anyway. 303 */ 304 static const struct bge_product { 305 pci_vendor_id_t bp_vendor; 306 pci_product_id_t bp_product; 307 const char *bp_name; 308 } bge_products[] = { 309 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 310 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 311 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 312 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 313 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 314 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 315 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 319 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 320 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 323 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 349 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 354 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 359 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 363 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 364 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 367 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 368 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 370 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 371 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 372 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 373 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 375 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 376 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 377 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 379 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 380 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 381 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 382 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 383 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 384 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 399 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 400 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 401 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 402 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 403 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 404 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 405 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 406 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 407 { 0, 0, NULL }, 408 }; 409 410 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 411 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 412 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 413 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 414 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 415 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 416 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 417 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 418 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 419 420 static const struct bge_revision { 421 uint32_t br_chipid; 422 const char *br_name; 423 } bge_revisions[] = { 424 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 425 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 426 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 427 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 428 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 429 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 430 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 431 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 432 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 433 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 434 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 435 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 436 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 437 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 438 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 439 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 440 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 441 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 442 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 443 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 444 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 445 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 446 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 447 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 448 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 449 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 450 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 451 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 452 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 453 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 454 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 455 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 456 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 457 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 458 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 459 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 460 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 461 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 462 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 463 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 464 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 465 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 466 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 467 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 468 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 469 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 470 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 471 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 472 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 473 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 474 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 475 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 476 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 477 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 478 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 479 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 480 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 481 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 482 /* 5754 and 5787 share the same ASIC ID */ 483 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 484 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 485 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 486 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 487 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 488 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 489 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 490 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 491 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 492 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 493 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 494 495 { 0, NULL } 496 }; 497 498 /* 499 * Some defaults for major revisions, so that newer steppings 500 * that we don't know about have a shot at working. 501 */ 502 static const struct bge_revision bge_majorrevs[] = { 503 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 504 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 505 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 506 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 507 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 508 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 509 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 510 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 511 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 512 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 513 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 514 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 515 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 516 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 517 /* 5754 and 5787 share the same ASIC ID */ 518 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 519 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 520 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 521 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 522 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 523 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 524 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 525 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 526 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 527 528 { 0, NULL } 529 }; 530 531 static int bge_allow_asf = 1; 532 533 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 534 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 535 536 static uint32_t 537 bge_readmem_ind(struct bge_softc *sc, int off) 538 { 539 pcireg_t val; 540 541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 542 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 543 return 0; 544 545 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 546 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 547 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 548 return val; 549 } 550 551 static void 552 bge_writemem_ind(struct bge_softc *sc, int off, int val) 553 { 554 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 556 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 557 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 558 } 559 560 /* 561 * PCI Express only 562 */ 563 static void 564 bge_set_max_readrq(struct bge_softc *sc) 565 { 566 pcireg_t val; 567 568 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 569 + PCIE_DCSR); 570 val &= ~PCIE_DCSR_MAX_READ_REQ; 571 switch (sc->bge_expmrq) { 572 case 2048: 573 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 574 break; 575 case 4096: 576 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 577 break; 578 default: 579 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 580 break; 581 } 582 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 583 + PCIE_DCSR, val); 584 } 585 586 #ifdef notdef 587 static uint32_t 588 bge_readreg_ind(struct bge_softc *sc, int off) 589 { 590 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 591 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 592 } 593 #endif 594 595 static void 596 bge_writereg_ind(struct bge_softc *sc, int off, int val) 597 { 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 599 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 600 } 601 602 static void 603 bge_writemem_direct(struct bge_softc *sc, int off, int val) 604 { 605 CSR_WRITE_4(sc, off, val); 606 } 607 608 static void 609 bge_writembx(struct bge_softc *sc, int off, int val) 610 { 611 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 612 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 613 614 CSR_WRITE_4(sc, off, val); 615 } 616 617 static void 618 bge_writembx_flush(struct bge_softc *sc, int off, int val) 619 { 620 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 621 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 622 623 CSR_WRITE_4_FLUSH(sc, off, val); 624 } 625 626 /* 627 * Clear all stale locks and select the lock for this driver instance. 628 */ 629 void 630 bge_ape_lock_init(struct bge_softc *sc) 631 { 632 struct pci_attach_args *pa = &(sc->bge_pa); 633 uint32_t bit, regbase; 634 int i; 635 636 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 637 regbase = BGE_APE_LOCK_GRANT; 638 else 639 regbase = BGE_APE_PER_LOCK_GRANT; 640 641 /* Clear any stale locks. */ 642 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 643 switch (i) { 644 case BGE_APE_LOCK_PHY0: 645 case BGE_APE_LOCK_PHY1: 646 case BGE_APE_LOCK_PHY2: 647 case BGE_APE_LOCK_PHY3: 648 bit = BGE_APE_LOCK_GRANT_DRIVER0; 649 break; 650 default: 651 if (pa->pa_function == 0) 652 bit = BGE_APE_LOCK_GRANT_DRIVER0; 653 else 654 bit = (1 << pa->pa_function); 655 } 656 APE_WRITE_4(sc, regbase + 4 * i, bit); 657 } 658 659 /* Select the PHY lock based on the device's function number. */ 660 switch (pa->pa_function) { 661 case 0: 662 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 663 break; 664 case 1: 665 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 666 break; 667 case 2: 668 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 669 break; 670 case 3: 671 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 672 break; 673 default: 674 printf("%s: PHY lock not supported on function\n", 675 device_xname(sc->bge_dev)); 676 break; 677 } 678 } 679 680 /* 681 * Check for APE firmware, set flags, and print version info. 682 */ 683 void 684 bge_ape_read_fw_ver(struct bge_softc *sc) 685 { 686 const char *fwtype; 687 uint32_t apedata, features; 688 689 /* Check for a valid APE signature in shared memory. */ 690 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 691 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 692 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 693 return; 694 } 695 696 /* Check if APE firmware is running. */ 697 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 698 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 699 printf("%s: APE signature found but FW status not ready! " 700 "0x%08x\n", device_xname(sc->bge_dev), apedata); 701 return; 702 } 703 704 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 705 706 /* Fetch the APE firwmare type and version. */ 707 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 708 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 709 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 710 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 711 fwtype = "NCSI"; 712 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 713 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 714 fwtype = "DASH"; 715 } else 716 fwtype = "UNKN"; 717 718 /* Print the APE firmware version. */ 719 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 720 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 721 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 722 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 723 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 724 } 725 726 int 727 bge_ape_lock(struct bge_softc *sc, int locknum) 728 { 729 struct pci_attach_args *pa = &(sc->bge_pa); 730 uint32_t bit, gnt, req, status; 731 int i, off; 732 733 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 734 return (0); 735 736 /* Lock request/grant registers have different bases. */ 737 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 738 req = BGE_APE_LOCK_REQ; 739 gnt = BGE_APE_LOCK_GRANT; 740 } else { 741 req = BGE_APE_PER_LOCK_REQ; 742 gnt = BGE_APE_PER_LOCK_GRANT; 743 } 744 745 off = 4 * locknum; 746 747 switch (locknum) { 748 case BGE_APE_LOCK_GPIO: 749 /* Lock required when using GPIO. */ 750 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 751 return (0); 752 if (pa->pa_function == 0) 753 bit = BGE_APE_LOCK_REQ_DRIVER0; 754 else 755 bit = (1 << pa->pa_function); 756 break; 757 case BGE_APE_LOCK_GRC: 758 /* Lock required to reset the device. */ 759 if (pa->pa_function == 0) 760 bit = BGE_APE_LOCK_REQ_DRIVER0; 761 else 762 bit = (1 << pa->pa_function); 763 break; 764 case BGE_APE_LOCK_MEM: 765 /* Lock required when accessing certain APE memory. */ 766 if (pa->pa_function == 0) 767 bit = BGE_APE_LOCK_REQ_DRIVER0; 768 else 769 bit = (1 << pa->pa_function); 770 break; 771 case BGE_APE_LOCK_PHY0: 772 case BGE_APE_LOCK_PHY1: 773 case BGE_APE_LOCK_PHY2: 774 case BGE_APE_LOCK_PHY3: 775 /* Lock required when accessing PHYs. */ 776 bit = BGE_APE_LOCK_REQ_DRIVER0; 777 break; 778 default: 779 return (EINVAL); 780 } 781 782 /* Request a lock. */ 783 APE_WRITE_4_FLUSH(sc, req + off, bit); 784 785 /* Wait up to 1 second to acquire lock. */ 786 for (i = 0; i < 20000; i++) { 787 status = APE_READ_4(sc, gnt + off); 788 if (status == bit) 789 break; 790 DELAY(50); 791 } 792 793 /* Handle any errors. */ 794 if (status != bit) { 795 printf("%s: APE lock %d request failed! " 796 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 797 device_xname(sc->bge_dev), 798 locknum, req + off, bit & 0xFFFF, gnt + off, 799 status & 0xFFFF); 800 /* Revoke the lock request. */ 801 APE_WRITE_4(sc, gnt + off, bit); 802 return (EBUSY); 803 } 804 805 return (0); 806 } 807 808 void 809 bge_ape_unlock(struct bge_softc *sc, int locknum) 810 { 811 struct pci_attach_args *pa = &(sc->bge_pa); 812 uint32_t bit, gnt; 813 int off; 814 815 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 816 return; 817 818 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 819 gnt = BGE_APE_LOCK_GRANT; 820 else 821 gnt = BGE_APE_PER_LOCK_GRANT; 822 823 off = 4 * locknum; 824 825 switch (locknum) { 826 case BGE_APE_LOCK_GPIO: 827 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 828 return; 829 if (pa->pa_function == 0) 830 bit = BGE_APE_LOCK_GRANT_DRIVER0; 831 else 832 bit = (1 << pa->pa_function); 833 break; 834 case BGE_APE_LOCK_GRC: 835 if (pa->pa_function == 0) 836 bit = BGE_APE_LOCK_GRANT_DRIVER0; 837 else 838 bit = (1 << pa->pa_function); 839 break; 840 case BGE_APE_LOCK_MEM: 841 if (pa->pa_function == 0) 842 bit = BGE_APE_LOCK_GRANT_DRIVER0; 843 else 844 bit = (1 << pa->pa_function); 845 break; 846 case BGE_APE_LOCK_PHY0: 847 case BGE_APE_LOCK_PHY1: 848 case BGE_APE_LOCK_PHY2: 849 case BGE_APE_LOCK_PHY3: 850 bit = BGE_APE_LOCK_GRANT_DRIVER0; 851 break; 852 default: 853 return; 854 } 855 856 /* Write and flush for consecutive bge_ape_lock() */ 857 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 858 } 859 860 /* 861 * Send an event to the APE firmware. 862 */ 863 void 864 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 865 { 866 uint32_t apedata; 867 int i; 868 869 /* NCSI does not support APE events. */ 870 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 871 return; 872 873 /* Wait up to 1ms for APE to service previous event. */ 874 for (i = 10; i > 0; i--) { 875 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 876 break; 877 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 878 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 879 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 880 BGE_APE_EVENT_STATUS_EVENT_PENDING); 881 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 882 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 883 break; 884 } 885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 886 DELAY(100); 887 } 888 if (i == 0) { 889 printf("%s: APE event 0x%08x send timed out\n", 890 device_xname(sc->bge_dev), event); 891 } 892 } 893 894 void 895 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 896 { 897 uint32_t apedata, event; 898 899 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 900 return; 901 902 switch (kind) { 903 case BGE_RESET_START: 904 /* If this is the first load, clear the load counter. */ 905 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 906 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 907 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 908 else { 909 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 910 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 911 } 912 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 913 BGE_APE_HOST_SEG_SIG_MAGIC); 914 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 915 BGE_APE_HOST_SEG_LEN_MAGIC); 916 917 /* Add some version info if bge(4) supports it. */ 918 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 919 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 920 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 921 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 922 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 923 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 924 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 925 BGE_APE_HOST_DRVR_STATE_START); 926 event = BGE_APE_EVENT_STATUS_STATE_START; 927 break; 928 case BGE_RESET_SHUTDOWN: 929 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 930 BGE_APE_HOST_DRVR_STATE_UNLOAD); 931 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 932 break; 933 case BGE_RESET_SUSPEND: 934 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 935 break; 936 default: 937 return; 938 } 939 940 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 941 BGE_APE_EVENT_STATUS_STATE_CHNGE); 942 } 943 944 static uint8_t 945 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 946 { 947 uint32_t access, byte = 0; 948 int i; 949 950 /* Lock. */ 951 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 952 for (i = 0; i < 8000; i++) { 953 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 954 break; 955 DELAY(20); 956 } 957 if (i == 8000) 958 return 1; 959 960 /* Enable access. */ 961 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 962 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 963 964 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 965 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 966 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 967 DELAY(10); 968 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 969 DELAY(10); 970 break; 971 } 972 } 973 974 if (i == BGE_TIMEOUT * 10) { 975 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 976 return 1; 977 } 978 979 /* Get result. */ 980 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 981 982 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 983 984 /* Disable access. */ 985 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 986 987 /* Unlock. */ 988 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 989 990 return 0; 991 } 992 993 /* 994 * Read a sequence of bytes from NVRAM. 995 */ 996 static int 997 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 998 { 999 int error = 0, i; 1000 uint8_t byte = 0; 1001 1002 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1003 return 1; 1004 1005 for (i = 0; i < cnt; i++) { 1006 error = bge_nvram_getbyte(sc, off + i, &byte); 1007 if (error) 1008 break; 1009 *(dest + i) = byte; 1010 } 1011 1012 return (error ? 1 : 0); 1013 } 1014 1015 /* 1016 * Read a byte of data stored in the EEPROM at address 'addr.' The 1017 * BCM570x supports both the traditional bitbang interface and an 1018 * auto access interface for reading the EEPROM. We use the auto 1019 * access method. 1020 */ 1021 static uint8_t 1022 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1023 { 1024 int i; 1025 uint32_t byte = 0; 1026 1027 /* 1028 * Enable use of auto EEPROM access so we can avoid 1029 * having to use the bitbang method. 1030 */ 1031 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1032 1033 /* Reset the EEPROM, load the clock period. */ 1034 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1035 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1036 DELAY(20); 1037 1038 /* Issue the read EEPROM command. */ 1039 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1040 1041 /* Wait for completion */ 1042 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1043 DELAY(10); 1044 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1045 break; 1046 } 1047 1048 if (i == BGE_TIMEOUT * 10) { 1049 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1050 return 1; 1051 } 1052 1053 /* Get result. */ 1054 byte = CSR_READ_4(sc, BGE_EE_DATA); 1055 1056 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1057 1058 return 0; 1059 } 1060 1061 /* 1062 * Read a sequence of bytes from the EEPROM. 1063 */ 1064 static int 1065 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1066 { 1067 int error = 0, i; 1068 uint8_t byte = 0; 1069 char *dest = destv; 1070 1071 for (i = 0; i < cnt; i++) { 1072 error = bge_eeprom_getbyte(sc, off + i, &byte); 1073 if (error) 1074 break; 1075 *(dest + i) = byte; 1076 } 1077 1078 return (error ? 1 : 0); 1079 } 1080 1081 static int 1082 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1083 { 1084 struct bge_softc * const sc = device_private(dev); 1085 uint32_t data; 1086 uint32_t autopoll; 1087 int rv = 0; 1088 int i; 1089 1090 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1091 return -1; 1092 1093 /* Reading with autopolling on may trigger PCI errors */ 1094 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1095 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1096 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1097 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1098 DELAY(80); 1099 } 1100 1101 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1102 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1103 1104 for (i = 0; i < BGE_TIMEOUT; i++) { 1105 delay(10); 1106 data = CSR_READ_4(sc, BGE_MI_COMM); 1107 if (!(data & BGE_MICOMM_BUSY)) { 1108 DELAY(5); 1109 data = CSR_READ_4(sc, BGE_MI_COMM); 1110 break; 1111 } 1112 } 1113 1114 if (i == BGE_TIMEOUT) { 1115 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1116 rv = ETIMEDOUT; 1117 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1118 /* XXX This error occurs on some devices while attaching. */ 1119 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1120 rv = EIO; 1121 } else 1122 *val = data & BGE_MICOMM_DATA; 1123 1124 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1125 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1126 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1127 DELAY(80); 1128 } 1129 1130 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1131 1132 return rv; 1133 } 1134 1135 static int 1136 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1137 { 1138 struct bge_softc * const sc = device_private(dev); 1139 uint32_t data, autopoll; 1140 int rv = 0; 1141 int i; 1142 1143 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1144 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1145 return 0; 1146 1147 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1148 return -1; 1149 1150 /* Reading with autopolling on may trigger PCI errors */ 1151 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1152 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1153 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1154 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1155 DELAY(80); 1156 } 1157 1158 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1159 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1160 1161 for (i = 0; i < BGE_TIMEOUT; i++) { 1162 delay(10); 1163 data = CSR_READ_4(sc, BGE_MI_COMM); 1164 if (!(data & BGE_MICOMM_BUSY)) { 1165 delay(5); 1166 data = CSR_READ_4(sc, BGE_MI_COMM); 1167 break; 1168 } 1169 } 1170 1171 if (i == BGE_TIMEOUT) { 1172 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1173 rv = ETIMEDOUT; 1174 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1175 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1176 rv = EIO; 1177 } 1178 1179 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1180 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1181 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1182 delay(80); 1183 } 1184 1185 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1186 1187 if (i == BGE_TIMEOUT) { 1188 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1189 return ETIMEDOUT; 1190 } 1191 1192 return rv; 1193 } 1194 1195 static void 1196 bge_miibus_statchg(struct ifnet *ifp) 1197 { 1198 struct bge_softc * const sc = ifp->if_softc; 1199 struct mii_data *mii = &sc->bge_mii; 1200 uint32_t mac_mode, rx_mode, tx_mode; 1201 1202 /* 1203 * Get flow control negotiation result. 1204 */ 1205 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1206 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1207 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1208 1209 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1210 mii->mii_media_status & IFM_ACTIVE && 1211 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1212 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1213 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1214 (!(mii->mii_media_status & IFM_ACTIVE) || 1215 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1216 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1217 1218 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1219 return; 1220 1221 /* Set the port mode (MII/GMII) to match the link speed. */ 1222 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1223 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1224 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1225 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1226 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1227 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1228 mac_mode |= BGE_PORTMODE_GMII; 1229 else 1230 mac_mode |= BGE_PORTMODE_MII; 1231 1232 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1233 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1234 if ((mii->mii_media_active & IFM_FDX) != 0) { 1235 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1236 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1237 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1238 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1239 } else 1240 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1241 1242 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1243 DELAY(40); 1244 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1245 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1246 } 1247 1248 /* 1249 * Update rx threshold levels to values in a particular slot 1250 * of the interrupt-mitigation table bge_rx_threshes. 1251 */ 1252 static void 1253 bge_set_thresh(struct ifnet *ifp, int lvl) 1254 { 1255 struct bge_softc * const sc = ifp->if_softc; 1256 int s; 1257 1258 /* 1259 * For now, just save the new Rx-intr thresholds and record 1260 * that a threshold update is pending. Updating the hardware 1261 * registers here (even at splhigh()) is observed to 1262 * occasionally cause glitches where Rx-interrupts are not 1263 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1264 */ 1265 s = splnet(); 1266 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1267 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1268 sc->bge_pending_rxintr_change = 1; 1269 splx(s); 1270 } 1271 1272 1273 /* 1274 * Update Rx thresholds of all bge devices 1275 */ 1276 static void 1277 bge_update_all_threshes(int lvl) 1278 { 1279 struct ifnet *ifp; 1280 const char * const namebuf = "bge"; 1281 int namelen; 1282 int s; 1283 1284 if (lvl < 0) 1285 lvl = 0; 1286 else if (lvl >= NBGE_RX_THRESH) 1287 lvl = NBGE_RX_THRESH - 1; 1288 1289 namelen = strlen(namebuf); 1290 /* 1291 * Now search all the interfaces for this name/number 1292 */ 1293 s = pserialize_read_enter(); 1294 IFNET_READER_FOREACH(ifp) { 1295 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1296 continue; 1297 /* We got a match: update if doing auto-threshold-tuning */ 1298 if (bge_auto_thresh) 1299 bge_set_thresh(ifp, lvl); 1300 } 1301 pserialize_read_exit(s); 1302 } 1303 1304 /* 1305 * Handle events that have triggered interrupts. 1306 */ 1307 static void 1308 bge_handle_events(struct bge_softc *sc) 1309 { 1310 1311 return; 1312 } 1313 1314 /* 1315 * Memory management for jumbo frames. 1316 */ 1317 1318 static int 1319 bge_alloc_jumbo_mem(struct bge_softc *sc) 1320 { 1321 char *ptr, *kva; 1322 bus_dma_segment_t seg; 1323 int i, rseg, state, error; 1324 struct bge_jpool_entry *entry; 1325 1326 state = error = 0; 1327 1328 /* Grab a big chunk o' storage. */ 1329 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1330 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1331 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1332 return ENOBUFS; 1333 } 1334 1335 state = 1; 1336 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1337 BUS_DMA_NOWAIT)) { 1338 aprint_error_dev(sc->bge_dev, 1339 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1340 error = ENOBUFS; 1341 goto out; 1342 } 1343 1344 state = 2; 1345 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1346 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1347 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1348 error = ENOBUFS; 1349 goto out; 1350 } 1351 1352 state = 3; 1353 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1354 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1355 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1356 error = ENOBUFS; 1357 goto out; 1358 } 1359 1360 state = 4; 1361 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1362 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1363 1364 SLIST_INIT(&sc->bge_jfree_listhead); 1365 SLIST_INIT(&sc->bge_jinuse_listhead); 1366 1367 /* 1368 * Now divide it up into 9K pieces and save the addresses 1369 * in an array. 1370 */ 1371 ptr = sc->bge_cdata.bge_jumbo_buf; 1372 for (i = 0; i < BGE_JSLOTS; i++) { 1373 sc->bge_cdata.bge_jslots[i] = ptr; 1374 ptr += BGE_JLEN; 1375 entry = malloc(sizeof(struct bge_jpool_entry), 1376 M_DEVBUF, M_WAITOK); 1377 entry->slot = i; 1378 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1379 entry, jpool_entries); 1380 } 1381 out: 1382 if (error != 0) { 1383 switch (state) { 1384 case 4: 1385 bus_dmamap_unload(sc->bge_dmatag, 1386 sc->bge_cdata.bge_rx_jumbo_map); 1387 /* FALLTHROUGH */ 1388 case 3: 1389 bus_dmamap_destroy(sc->bge_dmatag, 1390 sc->bge_cdata.bge_rx_jumbo_map); 1391 /* FALLTHROUGH */ 1392 case 2: 1393 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1394 /* FALLTHROUGH */ 1395 case 1: 1396 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1397 break; 1398 default: 1399 break; 1400 } 1401 } 1402 1403 return error; 1404 } 1405 1406 /* 1407 * Allocate a jumbo buffer. 1408 */ 1409 static void * 1410 bge_jalloc(struct bge_softc *sc) 1411 { 1412 struct bge_jpool_entry *entry; 1413 1414 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1415 1416 if (entry == NULL) { 1417 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1418 return NULL; 1419 } 1420 1421 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1422 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1423 return (sc->bge_cdata.bge_jslots[entry->slot]); 1424 } 1425 1426 /* 1427 * Release a jumbo buffer. 1428 */ 1429 static void 1430 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1431 { 1432 struct bge_jpool_entry *entry; 1433 struct bge_softc * const sc = arg; 1434 int i, s; 1435 1436 if (sc == NULL) 1437 panic("bge_jfree: can't find softc pointer!"); 1438 1439 /* calculate the slot this buffer belongs to */ 1440 1441 i = ((char *)buf 1442 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1443 1444 if ((i < 0) || (i >= BGE_JSLOTS)) 1445 panic("bge_jfree: asked to free buffer that we don't manage!"); 1446 1447 s = splvm(); 1448 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1449 if (entry == NULL) 1450 panic("bge_jfree: buffer not in use!"); 1451 entry->slot = i; 1452 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1453 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1454 1455 if (__predict_true(m != NULL)) 1456 pool_cache_put(mb_cache, m); 1457 splx(s); 1458 } 1459 1460 1461 /* 1462 * Initialize a standard receive ring descriptor. 1463 */ 1464 static int 1465 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1466 bus_dmamap_t dmamap) 1467 { 1468 struct mbuf *m_new = NULL; 1469 struct bge_rx_bd *r; 1470 int error; 1471 1472 if (dmamap == NULL) 1473 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1474 1475 if (dmamap == NULL) { 1476 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1477 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1478 if (error != 0) 1479 return error; 1480 } 1481 1482 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1483 1484 if (m == NULL) { 1485 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1486 if (m_new == NULL) 1487 return ENOBUFS; 1488 1489 MCLGET(m_new, M_DONTWAIT); 1490 if (!(m_new->m_flags & M_EXT)) { 1491 m_freem(m_new); 1492 return ENOBUFS; 1493 } 1494 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1495 1496 } else { 1497 m_new = m; 1498 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1499 m_new->m_data = m_new->m_ext.ext_buf; 1500 } 1501 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1502 m_adj(m_new, ETHER_ALIGN); 1503 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1504 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1505 m_freem(m_new); 1506 return ENOBUFS; 1507 } 1508 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1509 BUS_DMASYNC_PREREAD); 1510 1511 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1512 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1513 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1514 r->bge_flags = BGE_RXBDFLAG_END; 1515 r->bge_len = m_new->m_len; 1516 r->bge_idx = i; 1517 1518 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1519 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1520 i * sizeof (struct bge_rx_bd), 1521 sizeof (struct bge_rx_bd), 1522 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1523 1524 return 0; 1525 } 1526 1527 /* 1528 * Initialize a jumbo receive ring descriptor. This allocates 1529 * a jumbo buffer from the pool managed internally by the driver. 1530 */ 1531 static int 1532 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1533 { 1534 struct mbuf *m_new = NULL; 1535 struct bge_rx_bd *r; 1536 void *buf = NULL; 1537 1538 if (m == NULL) { 1539 1540 /* Allocate the mbuf. */ 1541 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1542 if (m_new == NULL) 1543 return ENOBUFS; 1544 1545 /* Allocate the jumbo buffer */ 1546 buf = bge_jalloc(sc); 1547 if (buf == NULL) { 1548 m_freem(m_new); 1549 aprint_error_dev(sc->bge_dev, 1550 "jumbo allocation failed -- packet dropped!\n"); 1551 return ENOBUFS; 1552 } 1553 1554 /* Attach the buffer to the mbuf. */ 1555 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1556 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1557 bge_jfree, sc); 1558 m_new->m_flags |= M_EXT_RW; 1559 } else { 1560 m_new = m; 1561 buf = m_new->m_data = m_new->m_ext.ext_buf; 1562 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1563 } 1564 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1565 m_adj(m_new, ETHER_ALIGN); 1566 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1567 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1568 BGE_JLEN, BUS_DMASYNC_PREREAD); 1569 /* Set up the descriptor. */ 1570 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1571 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1572 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1573 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1574 r->bge_len = m_new->m_len; 1575 r->bge_idx = i; 1576 1577 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1578 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1579 i * sizeof (struct bge_rx_bd), 1580 sizeof (struct bge_rx_bd), 1581 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1582 1583 return 0; 1584 } 1585 1586 /* 1587 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1588 * that's 1MB or memory, which is a lot. For now, we fill only the first 1589 * 256 ring entries and hope that our CPU is fast enough to keep up with 1590 * the NIC. 1591 */ 1592 static int 1593 bge_init_rx_ring_std(struct bge_softc *sc) 1594 { 1595 int i; 1596 1597 if (sc->bge_flags & BGEF_RXRING_VALID) 1598 return 0; 1599 1600 for (i = 0; i < BGE_SSLOTS; i++) { 1601 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1602 return ENOBUFS; 1603 } 1604 1605 sc->bge_std = i - 1; 1606 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1607 1608 sc->bge_flags |= BGEF_RXRING_VALID; 1609 1610 return 0; 1611 } 1612 1613 static void 1614 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1615 { 1616 int i; 1617 1618 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1619 return; 1620 1621 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1622 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1623 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1624 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1625 if (disable) { 1626 bus_dmamap_destroy(sc->bge_dmatag, 1627 sc->bge_cdata.bge_rx_std_map[i]); 1628 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1629 } 1630 } 1631 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1632 sizeof(struct bge_rx_bd)); 1633 } 1634 1635 sc->bge_flags &= ~BGEF_RXRING_VALID; 1636 } 1637 1638 static int 1639 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1640 { 1641 int i; 1642 volatile struct bge_rcb *rcb; 1643 1644 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1645 return 0; 1646 1647 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1648 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1649 return ENOBUFS; 1650 } 1651 1652 sc->bge_jumbo = i - 1; 1653 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1654 1655 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1656 rcb->bge_maxlen_flags = 0; 1657 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1658 1659 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1660 1661 return 0; 1662 } 1663 1664 static void 1665 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1666 { 1667 int i; 1668 1669 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1670 return; 1671 1672 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1673 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1674 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1675 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1676 } 1677 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1678 sizeof(struct bge_rx_bd)); 1679 } 1680 1681 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1682 } 1683 1684 static void 1685 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1686 { 1687 int i; 1688 struct txdmamap_pool_entry *dma; 1689 1690 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1691 return; 1692 1693 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1694 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1695 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1696 sc->bge_cdata.bge_tx_chain[i] = NULL; 1697 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1698 link); 1699 sc->txdma[i] = 0; 1700 } 1701 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1702 sizeof(struct bge_tx_bd)); 1703 } 1704 1705 if (disable) { 1706 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1707 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1708 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1709 if (sc->bge_dma64) { 1710 bus_dmamap_destroy(sc->bge_dmatag32, 1711 dma->dmamap32); 1712 } 1713 free(dma, M_DEVBUF); 1714 } 1715 SLIST_INIT(&sc->txdma_list); 1716 } 1717 1718 sc->bge_flags &= ~BGEF_TXRING_VALID; 1719 } 1720 1721 static int 1722 bge_init_tx_ring(struct bge_softc *sc) 1723 { 1724 struct ifnet * const ifp = &sc->ethercom.ec_if; 1725 int i; 1726 bus_dmamap_t dmamap, dmamap32; 1727 bus_size_t maxsegsz; 1728 struct txdmamap_pool_entry *dma; 1729 1730 if (sc->bge_flags & BGEF_TXRING_VALID) 1731 return 0; 1732 1733 sc->bge_txcnt = 0; 1734 sc->bge_tx_saved_considx = 0; 1735 1736 /* Initialize transmit producer index for host-memory send ring. */ 1737 sc->bge_tx_prodidx = 0; 1738 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1739 /* 5700 b2 errata */ 1740 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1741 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1742 1743 /* NIC-memory send ring not used; initialize to zero. */ 1744 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1745 /* 5700 b2 errata */ 1746 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1747 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1748 1749 /* Limit DMA segment size for some chips */ 1750 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1751 (ifp->if_mtu <= ETHERMTU)) 1752 maxsegsz = 2048; 1753 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1754 maxsegsz = 4096; 1755 else 1756 maxsegsz = ETHER_MAX_LEN_JUMBO; 1757 1758 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1759 goto alloc_done; 1760 1761 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1762 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1763 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1764 &dmamap)) 1765 return ENOBUFS; 1766 if (dmamap == NULL) 1767 panic("dmamap NULL in bge_init_tx_ring"); 1768 if (sc->bge_dma64) { 1769 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1770 BGE_NTXSEG, maxsegsz, 0, 1771 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1772 &dmamap32)) { 1773 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1774 return ENOBUFS; 1775 } 1776 if (dmamap32 == NULL) 1777 panic("dmamap32 NULL in bge_init_tx_ring"); 1778 } else 1779 dmamap32 = dmamap; 1780 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1781 if (dma == NULL) { 1782 aprint_error_dev(sc->bge_dev, 1783 "can't alloc txdmamap_pool_entry\n"); 1784 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1785 if (sc->bge_dma64) 1786 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1787 return ENOMEM; 1788 } 1789 dma->dmamap = dmamap; 1790 dma->dmamap32 = dmamap32; 1791 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1792 } 1793 alloc_done: 1794 sc->bge_flags |= BGEF_TXRING_VALID; 1795 1796 return 0; 1797 } 1798 1799 static void 1800 bge_setmulti(struct bge_softc *sc) 1801 { 1802 struct ethercom * const ec = &sc->ethercom; 1803 struct ifnet * const ifp = &ec->ec_if; 1804 struct ether_multi *enm; 1805 struct ether_multistep step; 1806 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1807 uint32_t h; 1808 int i; 1809 1810 if (ifp->if_flags & IFF_PROMISC) 1811 goto allmulti; 1812 1813 /* Now program new ones. */ 1814 ETHER_LOCK(ec); 1815 ETHER_FIRST_MULTI(step, ec, enm); 1816 while (enm != NULL) { 1817 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1818 /* 1819 * We must listen to a range of multicast addresses. 1820 * For now, just accept all multicasts, rather than 1821 * trying to set only those filter bits needed to match 1822 * the range. (At this time, the only use of address 1823 * ranges is for IP multicast routing, for which the 1824 * range is big enough to require all bits set.) 1825 */ 1826 ETHER_UNLOCK(ec); 1827 goto allmulti; 1828 } 1829 1830 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1831 1832 /* Just want the 7 least-significant bits. */ 1833 h &= 0x7f; 1834 1835 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1836 ETHER_NEXT_MULTI(step, enm); 1837 } 1838 ETHER_UNLOCK(ec); 1839 1840 ifp->if_flags &= ~IFF_ALLMULTI; 1841 goto setit; 1842 1843 allmulti: 1844 ifp->if_flags |= IFF_ALLMULTI; 1845 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1846 1847 setit: 1848 for (i = 0; i < 4; i++) 1849 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1850 } 1851 1852 static void 1853 bge_sig_pre_reset(struct bge_softc *sc, int type) 1854 { 1855 1856 /* 1857 * Some chips don't like this so only do this if ASF is enabled 1858 */ 1859 if (sc->bge_asf_mode) 1860 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1861 1862 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1863 switch (type) { 1864 case BGE_RESET_START: 1865 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1866 BGE_FW_DRV_STATE_START); 1867 break; 1868 case BGE_RESET_SHUTDOWN: 1869 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1870 BGE_FW_DRV_STATE_UNLOAD); 1871 break; 1872 case BGE_RESET_SUSPEND: 1873 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1874 BGE_FW_DRV_STATE_SUSPEND); 1875 break; 1876 } 1877 } 1878 1879 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1880 bge_ape_driver_state_change(sc, type); 1881 } 1882 1883 static void 1884 bge_sig_post_reset(struct bge_softc *sc, int type) 1885 { 1886 1887 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1888 switch (type) { 1889 case BGE_RESET_START: 1890 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1891 BGE_FW_DRV_STATE_START_DONE); 1892 /* START DONE */ 1893 break; 1894 case BGE_RESET_SHUTDOWN: 1895 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1896 BGE_FW_DRV_STATE_UNLOAD_DONE); 1897 break; 1898 } 1899 } 1900 1901 if (type == BGE_RESET_SHUTDOWN) 1902 bge_ape_driver_state_change(sc, type); 1903 } 1904 1905 static void 1906 bge_sig_legacy(struct bge_softc *sc, int type) 1907 { 1908 1909 if (sc->bge_asf_mode) { 1910 switch (type) { 1911 case BGE_RESET_START: 1912 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1913 BGE_FW_DRV_STATE_START); 1914 break; 1915 case BGE_RESET_SHUTDOWN: 1916 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1917 BGE_FW_DRV_STATE_UNLOAD); 1918 break; 1919 } 1920 } 1921 } 1922 1923 static void 1924 bge_wait_for_event_ack(struct bge_softc *sc) 1925 { 1926 int i; 1927 1928 /* wait up to 2500usec */ 1929 for (i = 0; i < 250; i++) { 1930 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1931 BGE_RX_CPU_DRV_EVENT)) 1932 break; 1933 DELAY(10); 1934 } 1935 } 1936 1937 static void 1938 bge_stop_fw(struct bge_softc *sc) 1939 { 1940 1941 if (sc->bge_asf_mode) { 1942 bge_wait_for_event_ack(sc); 1943 1944 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1945 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1946 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1947 1948 bge_wait_for_event_ack(sc); 1949 } 1950 } 1951 1952 static int 1953 bge_poll_fw(struct bge_softc *sc) 1954 { 1955 uint32_t val; 1956 int i; 1957 1958 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1959 for (i = 0; i < BGE_TIMEOUT; i++) { 1960 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1961 if (val & BGE_VCPU_STATUS_INIT_DONE) 1962 break; 1963 DELAY(100); 1964 } 1965 if (i >= BGE_TIMEOUT) { 1966 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1967 return -1; 1968 } 1969 } else { 1970 /* 1971 * Poll the value location we just wrote until 1972 * we see the 1's complement of the magic number. 1973 * This indicates that the firmware initialization 1974 * is complete. 1975 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1976 */ 1977 for (i = 0; i < BGE_TIMEOUT; i++) { 1978 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1979 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1980 break; 1981 DELAY(10); 1982 } 1983 1984 if ((i >= BGE_TIMEOUT) 1985 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1986 aprint_error_dev(sc->bge_dev, 1987 "firmware handshake timed out, val = %x\n", val); 1988 return -1; 1989 } 1990 } 1991 1992 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1993 /* tg3 says we have to wait extra time */ 1994 delay(10 * 1000); 1995 } 1996 1997 return 0; 1998 } 1999 2000 int 2001 bge_phy_addr(struct bge_softc *sc) 2002 { 2003 struct pci_attach_args *pa = &(sc->bge_pa); 2004 int phy_addr = 1; 2005 2006 /* 2007 * PHY address mapping for various devices. 2008 * 2009 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2010 * ---------+-------+-------+-------+-------+ 2011 * BCM57XX | 1 | X | X | X | 2012 * BCM5704 | 1 | X | 1 | X | 2013 * BCM5717 | 1 | 8 | 2 | 9 | 2014 * BCM5719 | 1 | 8 | 2 | 9 | 2015 * BCM5720 | 1 | 8 | 2 | 9 | 2016 * 2017 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2018 * ---------+-------+-------+-------+-------+ 2019 * BCM57XX | X | X | X | X | 2020 * BCM5704 | X | X | X | X | 2021 * BCM5717 | X | X | X | X | 2022 * BCM5719 | 3 | 10 | 4 | 11 | 2023 * BCM5720 | X | X | X | X | 2024 * 2025 * Other addresses may respond but they are not 2026 * IEEE compliant PHYs and should be ignored. 2027 */ 2028 switch (BGE_ASICREV(sc->bge_chipid)) { 2029 case BGE_ASICREV_BCM5717: 2030 case BGE_ASICREV_BCM5719: 2031 case BGE_ASICREV_BCM5720: 2032 phy_addr = pa->pa_function; 2033 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2034 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2035 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2036 } else { 2037 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2038 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2039 } 2040 } 2041 2042 return phy_addr; 2043 } 2044 2045 /* 2046 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2047 * self-test results. 2048 */ 2049 static int 2050 bge_chipinit(struct bge_softc *sc) 2051 { 2052 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2053 int i; 2054 2055 /* Set endianness before we access any non-PCI registers. */ 2056 misc_ctl = BGE_INIT; 2057 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2058 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2059 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2060 misc_ctl); 2061 2062 /* 2063 * Clear the MAC statistics block in the NIC's 2064 * internal memory. 2065 */ 2066 for (i = BGE_STATS_BLOCK; 2067 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2068 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2069 2070 for (i = BGE_STATUS_BLOCK; 2071 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2072 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2073 2074 /* 5717 workaround from tg3 */ 2075 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2076 /* Save */ 2077 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2078 2079 /* Temporary modify MODE_CTL to control TLP */ 2080 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2081 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2082 2083 /* Control TLP */ 2084 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2085 BGE_TLP_PHYCTL1); 2086 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2087 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2088 2089 /* Restore */ 2090 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2091 } 2092 2093 if (BGE_IS_57765_FAMILY(sc)) { 2094 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2095 /* Save */ 2096 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2097 2098 /* Temporary modify MODE_CTL to control TLP */ 2099 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2100 CSR_WRITE_4(sc, BGE_MODE_CTL, 2101 reg | BGE_MODECTL_PCIE_TLPADDR1); 2102 2103 /* Control TLP */ 2104 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2105 BGE_TLP_PHYCTL5); 2106 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2107 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2108 2109 /* Restore */ 2110 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2111 } 2112 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2113 /* 2114 * For the 57766 and non Ax versions of 57765, bootcode 2115 * needs to setup the PCIE Fast Training Sequence (FTS) 2116 * value to prevent transmit hangs. 2117 */ 2118 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2119 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2120 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2121 2122 /* Save */ 2123 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2124 2125 /* Temporary modify MODE_CTL to control TLP */ 2126 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2127 CSR_WRITE_4(sc, BGE_MODE_CTL, 2128 reg | BGE_MODECTL_PCIE_TLPADDR0); 2129 2130 /* Control TLP */ 2131 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2132 BGE_TLP_FTSMAX); 2133 reg &= ~BGE_TLP_FTSMAX_MSK; 2134 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2135 reg | BGE_TLP_FTSMAX_VAL); 2136 2137 /* Restore */ 2138 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2139 } 2140 2141 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2142 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2143 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2144 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2145 } 2146 2147 /* Set up the PCI DMA control register. */ 2148 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2149 if (sc->bge_flags & BGEF_PCIE) { 2150 /* Read watermark not used, 128 bytes for write. */ 2151 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2152 device_xname(sc->bge_dev))); 2153 if (sc->bge_mps >= 256) 2154 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2155 else 2156 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2157 } else if (sc->bge_flags & BGEF_PCIX) { 2158 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2159 device_xname(sc->bge_dev))); 2160 /* PCI-X bus */ 2161 if (BGE_IS_5714_FAMILY(sc)) { 2162 /* 256 bytes for read and write. */ 2163 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2164 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2165 2166 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2167 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2168 else 2169 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2170 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2171 /* 2172 * In the BCM5703, the DMA read watermark should 2173 * be set to less than or equal to the maximum 2174 * memory read byte count of the PCI-X command 2175 * register. 2176 */ 2177 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2178 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2179 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2180 /* 1536 bytes for read, 384 bytes for write. */ 2181 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2182 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2183 } else { 2184 /* 384 bytes for read and write. */ 2185 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2186 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2187 (0x0F); 2188 } 2189 2190 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2191 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2192 uint32_t tmp; 2193 2194 /* Set ONEDMA_ATONCE for hardware workaround. */ 2195 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2196 if (tmp == 6 || tmp == 7) 2197 dma_rw_ctl |= 2198 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2199 2200 /* Set PCI-X DMA write workaround. */ 2201 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2202 } 2203 } else { 2204 /* Conventional PCI bus: 256 bytes for read and write. */ 2205 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2206 device_xname(sc->bge_dev))); 2207 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2208 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2209 2210 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2211 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2212 dma_rw_ctl |= 0x0F; 2213 } 2214 2215 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2216 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2217 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2218 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2219 2220 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2221 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2222 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2223 2224 if (BGE_IS_57765_PLUS(sc)) { 2225 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2226 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2227 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2228 2229 /* 2230 * Enable HW workaround for controllers that misinterpret 2231 * a status tag update and leave interrupts permanently 2232 * disabled. 2233 */ 2234 if (!BGE_IS_57765_FAMILY(sc) && 2235 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2236 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2237 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2238 } 2239 2240 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2241 dma_rw_ctl); 2242 2243 /* 2244 * Set up general mode register. 2245 */ 2246 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2247 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2248 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2249 /* Retain Host-2-BMC settings written by APE firmware. */ 2250 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2251 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2252 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2253 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2254 } 2255 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2256 BGE_MODECTL_TX_NO_PHDR_CSUM; 2257 2258 /* 2259 * BCM5701 B5 have a bug causing data corruption when using 2260 * 64-bit DMA reads, which can be terminated early and then 2261 * completed later as 32-bit accesses, in combination with 2262 * certain bridges. 2263 */ 2264 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2265 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2266 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2267 2268 /* 2269 * Tell the firmware the driver is running 2270 */ 2271 if (sc->bge_asf_mode & ASF_STACKUP) 2272 mode_ctl |= BGE_MODECTL_STACKUP; 2273 2274 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2275 2276 /* 2277 * Disable memory write invalidate. Apparently it is not supported 2278 * properly by these devices. 2279 */ 2280 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2281 PCI_COMMAND_INVALIDATE_ENABLE); 2282 2283 #ifdef __brokenalpha__ 2284 /* 2285 * Must insure that we do not cross an 8K (bytes) boundary 2286 * for DMA reads. Our highest limit is 1K bytes. This is a 2287 * restriction on some ALPHA platforms with early revision 2288 * 21174 PCI chipsets, such as the AlphaPC 164lx 2289 */ 2290 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2291 #endif 2292 2293 /* Set the timer prescaler (always 66MHz) */ 2294 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2295 2296 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2297 DELAY(40); /* XXX */ 2298 2299 /* Put PHY into ready state */ 2300 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2301 DELAY(40); 2302 } 2303 2304 return 0; 2305 } 2306 2307 static int 2308 bge_blockinit(struct bge_softc *sc) 2309 { 2310 volatile struct bge_rcb *rcb; 2311 bus_size_t rcb_addr; 2312 struct ifnet * const ifp = &sc->ethercom.ec_if; 2313 bge_hostaddr taddr; 2314 uint32_t dmactl, rdmareg, mimode, val; 2315 int i, limit; 2316 2317 /* 2318 * Initialize the memory window pointer register so that 2319 * we can access the first 32K of internal NIC RAM. This will 2320 * allow us to set up the TX send ring RCBs and the RX return 2321 * ring RCBs, plus other things which live in NIC memory. 2322 */ 2323 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2324 2325 if (!BGE_IS_5705_PLUS(sc)) { 2326 /* 57XX step 33 */ 2327 /* Configure mbuf memory pool */ 2328 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2329 2330 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2331 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2332 else 2333 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2334 2335 /* 57XX step 34 */ 2336 /* Configure DMA resource pool */ 2337 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2338 BGE_DMA_DESCRIPTORS); 2339 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2340 } 2341 2342 /* 5718 step 11, 57XX step 35 */ 2343 /* 2344 * Configure mbuf pool watermarks. New broadcom docs strongly 2345 * recommend these. 2346 */ 2347 if (BGE_IS_5717_PLUS(sc)) { 2348 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2349 if (ifp->if_mtu > ETHERMTU) { 2350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2351 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2352 } else { 2353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2354 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2355 } 2356 } else if (BGE_IS_5705_PLUS(sc)) { 2357 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2358 2359 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2360 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2362 } else { 2363 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2364 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2365 } 2366 } else { 2367 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2368 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2369 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2370 } 2371 2372 /* 57XX step 36 */ 2373 /* Configure DMA resource watermarks */ 2374 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2375 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2376 2377 /* 5718 step 13, 57XX step 38 */ 2378 /* Enable buffer manager */ 2379 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2380 /* 2381 * Change the arbitration algorithm of TXMBUF read request to 2382 * round-robin instead of priority based for BCM5719. When 2383 * TXFIFO is almost empty, RDMA will hold its request until 2384 * TXFIFO is not almost empty. 2385 */ 2386 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2387 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2388 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2389 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2390 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2391 val |= BGE_BMANMODE_LOMBUF_ATTN; 2392 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2393 2394 /* 57XX step 39 */ 2395 /* Poll for buffer manager start indication */ 2396 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2397 DELAY(10); 2398 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2399 break; 2400 } 2401 2402 if (i == BGE_TIMEOUT * 2) { 2403 aprint_error_dev(sc->bge_dev, 2404 "buffer manager failed to start\n"); 2405 return ENXIO; 2406 } 2407 2408 /* 57XX step 40 */ 2409 /* Enable flow-through queues */ 2410 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2411 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2412 2413 /* Wait until queue initialization is complete */ 2414 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2415 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2416 break; 2417 DELAY(10); 2418 } 2419 2420 if (i == BGE_TIMEOUT * 2) { 2421 aprint_error_dev(sc->bge_dev, 2422 "flow-through queue init failed\n"); 2423 return ENXIO; 2424 } 2425 2426 /* 2427 * Summary of rings supported by the controller: 2428 * 2429 * Standard Receive Producer Ring 2430 * - This ring is used to feed receive buffers for "standard" 2431 * sized frames (typically 1536 bytes) to the controller. 2432 * 2433 * Jumbo Receive Producer Ring 2434 * - This ring is used to feed receive buffers for jumbo sized 2435 * frames (i.e. anything bigger than the "standard" frames) 2436 * to the controller. 2437 * 2438 * Mini Receive Producer Ring 2439 * - This ring is used to feed receive buffers for "mini" 2440 * sized frames to the controller. 2441 * - This feature required external memory for the controller 2442 * but was never used in a production system. Should always 2443 * be disabled. 2444 * 2445 * Receive Return Ring 2446 * - After the controller has placed an incoming frame into a 2447 * receive buffer that buffer is moved into a receive return 2448 * ring. The driver is then responsible to passing the 2449 * buffer up to the stack. Many versions of the controller 2450 * support multiple RR rings. 2451 * 2452 * Send Ring 2453 * - This ring is used for outgoing frames. Many versions of 2454 * the controller support multiple send rings. 2455 */ 2456 2457 /* 5718 step 15, 57XX step 41 */ 2458 /* Initialize the standard RX ring control block */ 2459 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2460 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2461 /* 5718 step 16 */ 2462 if (BGE_IS_57765_PLUS(sc)) { 2463 /* 2464 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2465 * Bits 15-2 : Maximum RX frame size 2466 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2467 * Bit 0 : Reserved 2468 */ 2469 rcb->bge_maxlen_flags = 2470 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2471 } else if (BGE_IS_5705_PLUS(sc)) { 2472 /* 2473 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2474 * Bits 15-2 : Reserved (should be 0) 2475 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2476 * Bit 0 : Reserved 2477 */ 2478 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2479 } else { 2480 /* 2481 * Ring size is always XXX entries 2482 * Bits 31-16: Maximum RX frame size 2483 * Bits 15-2 : Reserved (should be 0) 2484 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2485 * Bit 0 : Reserved 2486 */ 2487 rcb->bge_maxlen_flags = 2488 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2489 } 2490 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2493 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2494 else 2495 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2496 /* Write the standard receive producer ring control block. */ 2497 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2498 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2499 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2500 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2501 2502 /* Reset the standard receive producer ring producer index. */ 2503 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2504 2505 /* 57XX step 42 */ 2506 /* 2507 * Initialize the jumbo RX ring control block 2508 * We set the 'ring disabled' bit in the flags 2509 * field until we're actually ready to start 2510 * using this ring (i.e. once we set the MTU 2511 * high enough to require it). 2512 */ 2513 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2514 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2515 BGE_HOSTADDR(rcb->bge_hostaddr, 2516 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2517 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2518 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2519 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2520 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2521 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2522 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2523 else 2524 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2525 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2526 rcb->bge_hostaddr.bge_addr_hi); 2527 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2528 rcb->bge_hostaddr.bge_addr_lo); 2529 /* Program the jumbo receive producer ring RCB parameters. */ 2530 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2531 rcb->bge_maxlen_flags); 2532 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2533 /* Reset the jumbo receive producer ring producer index. */ 2534 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2535 } 2536 2537 /* 57XX step 43 */ 2538 /* Disable the mini receive producer ring RCB. */ 2539 if (BGE_IS_5700_FAMILY(sc)) { 2540 /* Set up dummy disabled mini ring RCB */ 2541 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2542 rcb->bge_maxlen_flags = 2543 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2544 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2545 rcb->bge_maxlen_flags); 2546 /* Reset the mini receive producer ring producer index. */ 2547 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2548 2549 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2550 offsetof(struct bge_ring_data, bge_info), 2551 sizeof (struct bge_gib), 2552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2553 } 2554 2555 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2556 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2557 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2558 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2559 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2560 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2561 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2562 } 2563 /* 5718 step 14, 57XX step 44 */ 2564 /* 2565 * The BD ring replenish thresholds control how often the 2566 * hardware fetches new BD's from the producer rings in host 2567 * memory. Setting the value too low on a busy system can 2568 * starve the hardware and recue the throughpout. 2569 * 2570 * Set the BD ring replenish thresholds. The recommended 2571 * values are 1/8th the number of descriptors allocated to 2572 * each ring, but since we try to avoid filling the entire 2573 * ring we set these to the minimal value of 8. This needs to 2574 * be done on several of the supported chip revisions anyway, 2575 * to work around HW bugs. 2576 */ 2577 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2578 if (BGE_IS_JUMBO_CAPABLE(sc)) 2579 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2580 2581 /* 5718 step 18 */ 2582 if (BGE_IS_5717_PLUS(sc)) { 2583 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2584 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2585 } 2586 2587 /* 57XX step 45 */ 2588 /* 2589 * Disable all send rings by setting the 'ring disabled' bit 2590 * in the flags field of all the TX send ring control blocks, 2591 * located in NIC memory. 2592 */ 2593 if (BGE_IS_5700_FAMILY(sc)) { 2594 /* 5700 to 5704 had 16 send rings. */ 2595 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2596 } else if (BGE_IS_5717_PLUS(sc)) { 2597 limit = BGE_TX_RINGS_5717_MAX; 2598 } else if (BGE_IS_57765_FAMILY(sc) || 2599 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2600 limit = BGE_TX_RINGS_57765_MAX; 2601 } else 2602 limit = 1; 2603 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2604 for (i = 0; i < limit; i++) { 2605 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2606 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2607 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2608 rcb_addr += sizeof(struct bge_rcb); 2609 } 2610 2611 /* 57XX step 46 and 47 */ 2612 /* Configure send ring RCB 0 (we use only the first ring) */ 2613 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2614 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2615 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2616 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2617 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2618 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2619 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2620 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2621 else 2622 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2623 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2624 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2625 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2626 2627 /* 57XX step 48 */ 2628 /* 2629 * Disable all receive return rings by setting the 2630 * 'ring diabled' bit in the flags field of all the receive 2631 * return ring control blocks, located in NIC memory. 2632 */ 2633 if (BGE_IS_5717_PLUS(sc)) { 2634 /* Should be 17, use 16 until we get an SRAM map. */ 2635 limit = 16; 2636 } else if (BGE_IS_5700_FAMILY(sc)) 2637 limit = BGE_RX_RINGS_MAX; 2638 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2639 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2640 BGE_IS_57765_FAMILY(sc)) 2641 limit = 4; 2642 else 2643 limit = 1; 2644 /* Disable all receive return rings */ 2645 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2646 for (i = 0; i < limit; i++) { 2647 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2648 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2649 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2650 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2651 BGE_RCB_FLAG_RING_DISABLED)); 2652 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2653 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2654 (i * (sizeof(uint64_t))), 0); 2655 rcb_addr += sizeof(struct bge_rcb); 2656 } 2657 2658 /* 57XX step 49 */ 2659 /* 2660 * Set up receive return ring 0. Note that the NIC address 2661 * for RX return rings is 0x0. The return rings live entirely 2662 * within the host, so the nicaddr field in the RCB isn't used. 2663 */ 2664 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2665 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2666 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2667 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2668 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2669 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2670 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2671 2672 /* 5718 step 24, 57XX step 53 */ 2673 /* Set random backoff seed for TX */ 2674 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2675 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2676 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2677 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2678 BGE_TX_BACKOFF_SEED_MASK); 2679 2680 /* 5718 step 26, 57XX step 55 */ 2681 /* Set inter-packet gap */ 2682 val = 0x2620; 2683 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2684 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2685 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2686 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2687 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2688 2689 /* 5718 step 27, 57XX step 56 */ 2690 /* 2691 * Specify which ring to use for packets that don't match 2692 * any RX rules. 2693 */ 2694 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2695 2696 /* 5718 step 28, 57XX step 57 */ 2697 /* 2698 * Configure number of RX lists. One interrupt distribution 2699 * list, sixteen active lists, one bad frames class. 2700 */ 2701 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2702 2703 /* 5718 step 29, 57XX step 58 */ 2704 /* Inialize RX list placement stats mask. */ 2705 if (BGE_IS_575X_PLUS(sc)) { 2706 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2707 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2708 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2709 } else 2710 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2711 2712 /* 5718 step 30, 57XX step 59 */ 2713 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2714 2715 /* 5718 step 33, 57XX step 62 */ 2716 /* Disable host coalescing until we get it set up */ 2717 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2718 2719 /* 5718 step 34, 57XX step 63 */ 2720 /* Poll to make sure it's shut down. */ 2721 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2722 DELAY(10); 2723 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2724 break; 2725 } 2726 2727 if (i == BGE_TIMEOUT * 2) { 2728 aprint_error_dev(sc->bge_dev, 2729 "host coalescing engine failed to idle\n"); 2730 return ENXIO; 2731 } 2732 2733 /* 5718 step 35, 36, 37 */ 2734 /* Set up host coalescing defaults */ 2735 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2736 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2737 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2738 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2739 if (!(BGE_IS_5705_PLUS(sc))) { 2740 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2741 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2742 } 2743 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2744 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2745 2746 /* Set up address of statistics block */ 2747 if (BGE_IS_5700_FAMILY(sc)) { 2748 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2749 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2750 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2751 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2752 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2753 } 2754 2755 /* 5718 step 38 */ 2756 /* Set up address of status block */ 2757 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2758 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2759 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2760 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2761 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2762 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2763 2764 /* Set up status block size. */ 2765 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2766 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2767 val = BGE_STATBLKSZ_FULL; 2768 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2769 } else { 2770 val = BGE_STATBLKSZ_32BYTE; 2771 bzero(&sc->bge_rdata->bge_status_block, 32); 2772 } 2773 2774 /* 5718 step 39, 57XX step 73 */ 2775 /* Turn on host coalescing state machine */ 2776 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2777 2778 /* 5718 step 40, 57XX step 74 */ 2779 /* Turn on RX BD completion state machine and enable attentions */ 2780 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2781 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2782 2783 /* 5718 step 41, 57XX step 75 */ 2784 /* Turn on RX list placement state machine */ 2785 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2786 2787 /* 57XX step 76 */ 2788 /* Turn on RX list selector state machine. */ 2789 if (!(BGE_IS_5705_PLUS(sc))) 2790 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2791 2792 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2793 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2794 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2795 BGE_MACMODE_FRMHDR_DMA_ENB; 2796 2797 if (sc->bge_flags & BGEF_FIBER_TBI) 2798 val |= BGE_PORTMODE_TBI; 2799 else if (sc->bge_flags & BGEF_FIBER_MII) 2800 val |= BGE_PORTMODE_GMII; 2801 else 2802 val |= BGE_PORTMODE_MII; 2803 2804 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2805 /* Allow APE to send/receive frames. */ 2806 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2807 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2808 2809 /* Turn on DMA, clear stats */ 2810 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2811 /* 5718 step 44 */ 2812 DELAY(40); 2813 2814 /* 5718 step 45, 57XX step 79 */ 2815 /* Set misc. local control, enable interrupts on attentions */ 2816 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2817 if (BGE_IS_5717_PLUS(sc)) { 2818 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2819 /* 5718 step 46 */ 2820 DELAY(100); 2821 } 2822 2823 /* 57XX step 81 */ 2824 /* Turn on DMA completion state machine */ 2825 if (!(BGE_IS_5705_PLUS(sc))) 2826 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2827 2828 /* 5718 step 47, 57XX step 82 */ 2829 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2830 2831 /* 5718 step 48 */ 2832 /* Enable host coalescing bug fix. */ 2833 if (BGE_IS_5755_PLUS(sc)) 2834 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2835 2836 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2837 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2838 2839 /* Turn on write DMA state machine */ 2840 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2841 /* 5718 step 49 */ 2842 DELAY(40); 2843 2844 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2845 2846 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2847 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2848 2849 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2850 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2851 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2852 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2853 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2854 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2855 2856 if (sc->bge_flags & BGEF_PCIE) 2857 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2858 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2859 if (ifp->if_mtu <= ETHERMTU) 2860 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2861 } 2862 if (sc->bge_flags & BGEF_TSO) { 2863 val |= BGE_RDMAMODE_TSO4_ENABLE; 2864 if (BGE_IS_5717_PLUS(sc)) 2865 val |= BGE_RDMAMODE_TSO6_ENABLE; 2866 } 2867 2868 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2869 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2870 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2871 BGE_RDMAMODE_H2BNC_VLAN_DET; 2872 /* 2873 * Allow multiple outstanding read requests from 2874 * non-LSO read DMA engine. 2875 */ 2876 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2877 } 2878 2879 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2880 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2881 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2882 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2883 BGE_IS_57765_PLUS(sc)) { 2884 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2885 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2886 else 2887 rdmareg = BGE_RDMA_RSRVCTRL; 2888 dmactl = CSR_READ_4(sc, rdmareg); 2889 /* 2890 * Adjust tx margin to prevent TX data corruption and 2891 * fix internal FIFO overflow. 2892 */ 2893 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2894 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2895 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2896 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2897 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2898 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2899 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2900 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2901 } 2902 /* 2903 * Enable fix for read DMA FIFO overruns. 2904 * The fix is to limit the number of RX BDs 2905 * the hardware would fetch at a time. 2906 */ 2907 CSR_WRITE_4(sc, rdmareg, dmactl | 2908 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2909 } 2910 2911 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2912 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2913 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2914 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2915 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2916 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2917 /* 2918 * Allow 4KB burst length reads for non-LSO frames. 2919 * Enable 512B burst length reads for buffer descriptors. 2920 */ 2921 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2922 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2923 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2924 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2925 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2926 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2927 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2928 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2929 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2930 } 2931 /* Turn on read DMA state machine */ 2932 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2933 /* 5718 step 52 */ 2934 delay(40); 2935 2936 if (sc->bge_flags & BGEF_RDMA_BUG) { 2937 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2938 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2939 if ((val & 0xFFFF) > BGE_FRAMELEN) 2940 break; 2941 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2942 break; 2943 } 2944 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2945 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2946 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2947 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2948 else 2949 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2950 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2951 } 2952 } 2953 2954 /* 5718 step 56, 57XX step 84 */ 2955 /* Turn on RX data completion state machine */ 2956 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2957 2958 /* Turn on RX data and RX BD initiator state machine */ 2959 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2960 2961 /* 57XX step 85 */ 2962 /* Turn on Mbuf cluster free state machine */ 2963 if (!BGE_IS_5705_PLUS(sc)) 2964 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2965 2966 /* 5718 step 57, 57XX step 86 */ 2967 /* Turn on send data completion state machine */ 2968 val = BGE_SDCMODE_ENABLE; 2969 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2970 val |= BGE_SDCMODE_CDELAY; 2971 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2972 2973 /* 5718 step 58 */ 2974 /* Turn on send BD completion state machine */ 2975 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2976 2977 /* 57XX step 88 */ 2978 /* Turn on RX BD initiator state machine */ 2979 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2980 2981 /* 5718 step 60, 57XX step 90 */ 2982 /* Turn on send data initiator state machine */ 2983 if (sc->bge_flags & BGEF_TSO) { 2984 /* XXX: magic value from Linux driver */ 2985 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2986 BGE_SDIMODE_HW_LSO_PRE_DMA); 2987 } else 2988 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2989 2990 /* 5718 step 61, 57XX step 91 */ 2991 /* Turn on send BD initiator state machine */ 2992 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2993 2994 /* 5718 step 62, 57XX step 92 */ 2995 /* Turn on send BD selector state machine */ 2996 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2997 2998 /* 5718 step 31, 57XX step 60 */ 2999 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3000 /* 5718 step 32, 57XX step 61 */ 3001 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3002 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3003 3004 /* ack/clear link change events */ 3005 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3006 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3007 BGE_MACSTAT_LINK_CHANGED); 3008 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3009 3010 /* 3011 * Enable attention when the link has changed state for 3012 * devices that use auto polling. 3013 */ 3014 if (sc->bge_flags & BGEF_FIBER_TBI) { 3015 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3016 } else { 3017 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3018 mimode = BGE_MIMODE_500KHZ_CONST; 3019 else 3020 mimode = BGE_MIMODE_BASE; 3021 /* 5718 step 68. 5718 step 69 (optionally). */ 3022 if (BGE_IS_5700_FAMILY(sc) || 3023 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3024 mimode |= BGE_MIMODE_AUTOPOLL; 3025 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3026 } 3027 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3028 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3029 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3030 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3031 BGE_EVTENB_MI_INTERRUPT); 3032 } 3033 3034 /* 3035 * Clear any pending link state attention. 3036 * Otherwise some link state change events may be lost until attention 3037 * is cleared by bge_intr() -> bge_link_upd() sequence. 3038 * It's not necessary on newer BCM chips - perhaps enabling link 3039 * state change attentions implies clearing pending attention. 3040 */ 3041 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3042 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3043 BGE_MACSTAT_LINK_CHANGED); 3044 3045 /* Enable link state change attentions. */ 3046 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3047 3048 return 0; 3049 } 3050 3051 static const struct bge_revision * 3052 bge_lookup_rev(uint32_t chipid) 3053 { 3054 const struct bge_revision *br; 3055 3056 for (br = bge_revisions; br->br_name != NULL; br++) { 3057 if (br->br_chipid == chipid) 3058 return br; 3059 } 3060 3061 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3062 if (br->br_chipid == BGE_ASICREV(chipid)) 3063 return br; 3064 } 3065 3066 return NULL; 3067 } 3068 3069 static const struct bge_product * 3070 bge_lookup(const struct pci_attach_args *pa) 3071 { 3072 const struct bge_product *bp; 3073 3074 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3075 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3076 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3077 return bp; 3078 } 3079 3080 return NULL; 3081 } 3082 3083 static uint32_t 3084 bge_chipid(const struct pci_attach_args *pa) 3085 { 3086 uint32_t id; 3087 3088 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3089 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3090 3091 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3092 switch (PCI_PRODUCT(pa->pa_id)) { 3093 case PCI_PRODUCT_BROADCOM_BCM5717: 3094 case PCI_PRODUCT_BROADCOM_BCM5718: 3095 case PCI_PRODUCT_BROADCOM_BCM5719: 3096 case PCI_PRODUCT_BROADCOM_BCM5720: 3097 case PCI_PRODUCT_BROADCOM_BCM5725: 3098 case PCI_PRODUCT_BROADCOM_BCM5727: 3099 case PCI_PRODUCT_BROADCOM_BCM5762: 3100 case PCI_PRODUCT_BROADCOM_BCM57764: 3101 case PCI_PRODUCT_BROADCOM_BCM57767: 3102 case PCI_PRODUCT_BROADCOM_BCM57787: 3103 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3104 BGE_PCI_GEN2_PRODID_ASICREV); 3105 break; 3106 case PCI_PRODUCT_BROADCOM_BCM57761: 3107 case PCI_PRODUCT_BROADCOM_BCM57762: 3108 case PCI_PRODUCT_BROADCOM_BCM57765: 3109 case PCI_PRODUCT_BROADCOM_BCM57766: 3110 case PCI_PRODUCT_BROADCOM_BCM57781: 3111 case PCI_PRODUCT_BROADCOM_BCM57782: 3112 case PCI_PRODUCT_BROADCOM_BCM57785: 3113 case PCI_PRODUCT_BROADCOM_BCM57786: 3114 case PCI_PRODUCT_BROADCOM_BCM57791: 3115 case PCI_PRODUCT_BROADCOM_BCM57795: 3116 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3117 BGE_PCI_GEN15_PRODID_ASICREV); 3118 break; 3119 default: 3120 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3121 BGE_PCI_PRODID_ASICREV); 3122 break; 3123 } 3124 } 3125 3126 return id; 3127 } 3128 3129 /* 3130 * Return true if MSI can be used with this device. 3131 */ 3132 static int 3133 bge_can_use_msi(struct bge_softc *sc) 3134 { 3135 int can_use_msi = 0; 3136 3137 switch (BGE_ASICREV(sc->bge_chipid)) { 3138 case BGE_ASICREV_BCM5714_A0: 3139 case BGE_ASICREV_BCM5714: 3140 /* 3141 * Apparently, MSI doesn't work when these chips are 3142 * configured in single-port mode. 3143 */ 3144 break; 3145 case BGE_ASICREV_BCM5750: 3146 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3147 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3148 can_use_msi = 1; 3149 break; 3150 default: 3151 if (BGE_IS_575X_PLUS(sc)) 3152 can_use_msi = 1; 3153 } 3154 return (can_use_msi); 3155 } 3156 3157 /* 3158 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3159 * against our list and return its name if we find a match. Note 3160 * that since the Broadcom controller contains VPD support, we 3161 * can get the device name string from the controller itself instead 3162 * of the compiled-in string. This is a little slow, but it guarantees 3163 * we'll always announce the right product name. 3164 */ 3165 static int 3166 bge_probe(device_t parent, cfdata_t match, void *aux) 3167 { 3168 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3169 3170 if (bge_lookup(pa) != NULL) 3171 return 1; 3172 3173 return 0; 3174 } 3175 3176 static void 3177 bge_attach(device_t parent, device_t self, void *aux) 3178 { 3179 struct bge_softc * const sc = device_private(self); 3180 struct pci_attach_args * const pa = aux; 3181 prop_dictionary_t dict; 3182 const struct bge_product *bp; 3183 const struct bge_revision *br; 3184 pci_chipset_tag_t pc; 3185 const char *intrstr = NULL; 3186 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3187 uint32_t command; 3188 struct ifnet *ifp; 3189 struct mii_data * const mii = &sc->bge_mii; 3190 uint32_t misccfg, mimode, macmode; 3191 void * kva; 3192 u_char eaddr[ETHER_ADDR_LEN]; 3193 pcireg_t memtype, subid, reg; 3194 bus_addr_t memaddr; 3195 uint32_t pm_ctl; 3196 bool no_seeprom; 3197 int capmask, trys; 3198 int mii_flags; 3199 int map_flags; 3200 char intrbuf[PCI_INTRSTR_LEN]; 3201 3202 bp = bge_lookup(pa); 3203 KASSERT(bp != NULL); 3204 3205 sc->sc_pc = pa->pa_pc; 3206 sc->sc_pcitag = pa->pa_tag; 3207 sc->bge_dev = self; 3208 3209 sc->bge_pa = *pa; 3210 pc = sc->sc_pc; 3211 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3212 3213 aprint_naive(": Ethernet controller\n"); 3214 aprint_normal(": %s Ethernet\n", bp->bp_name); 3215 3216 /* 3217 * Map control/status registers. 3218 */ 3219 DPRINTFN(5, ("Map control/status regs\n")); 3220 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3221 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3222 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3223 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3224 3225 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3226 aprint_error_dev(sc->bge_dev, 3227 "failed to enable memory mapping!\n"); 3228 return; 3229 } 3230 3231 DPRINTFN(5, ("pci_mem_find\n")); 3232 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3233 switch (memtype) { 3234 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3235 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3236 #if 0 3237 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3238 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3239 &memaddr, &sc->bge_bsize) == 0) 3240 break; 3241 #else 3242 /* 3243 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3244 * system get NMI on boot (PR#48451). This problem might not be 3245 * the driver's bug but our PCI common part's bug. Until we 3246 * find a real reason, we ignore the prefetchable bit. 3247 */ 3248 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3249 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3250 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3251 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3252 map_flags, &sc->bge_bhandle) == 0) { 3253 sc->bge_btag = pa->pa_memt; 3254 break; 3255 } 3256 } 3257 #endif 3258 /* FALLTHROUGH */ 3259 default: 3260 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3261 return; 3262 } 3263 3264 /* Save various chip information. */ 3265 sc->bge_chipid = bge_chipid(pa); 3266 sc->bge_phy_addr = bge_phy_addr(sc); 3267 3268 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3269 &sc->bge_pciecap, NULL) != 0) { 3270 /* PCIe */ 3271 sc->bge_flags |= BGEF_PCIE; 3272 /* Extract supported maximum payload size. */ 3273 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3274 sc->bge_pciecap + PCIE_DCAP); 3275 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3276 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3277 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3278 sc->bge_expmrq = 2048; 3279 else 3280 sc->bge_expmrq = 4096; 3281 bge_set_max_readrq(sc); 3282 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3283 /* PCIe without PCIe cap */ 3284 sc->bge_flags |= BGEF_PCIE; 3285 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3286 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3287 /* PCI-X */ 3288 sc->bge_flags |= BGEF_PCIX; 3289 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3290 &sc->bge_pcixcap, NULL) == 0) 3291 aprint_error_dev(sc->bge_dev, 3292 "unable to find PCIX capability\n"); 3293 } 3294 3295 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3296 /* 3297 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3298 * can clobber the chip's PCI config-space power control 3299 * registers, leaving the card in D3 powersave state. We do 3300 * not have memory-mapped registers in this state, so force 3301 * device into D0 state before starting initialization. 3302 */ 3303 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3304 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3305 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3306 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3307 DELAY(1000); /* 27 usec is allegedly sufficient */ 3308 } 3309 3310 /* Save chipset family. */ 3311 switch (BGE_ASICREV(sc->bge_chipid)) { 3312 case BGE_ASICREV_BCM5717: 3313 case BGE_ASICREV_BCM5719: 3314 case BGE_ASICREV_BCM5720: 3315 sc->bge_flags |= BGEF_5717_PLUS; 3316 /* FALLTHROUGH */ 3317 case BGE_ASICREV_BCM5762: 3318 case BGE_ASICREV_BCM57765: 3319 case BGE_ASICREV_BCM57766: 3320 if (!BGE_IS_5717_PLUS(sc)) 3321 sc->bge_flags |= BGEF_57765_FAMILY; 3322 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3323 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3324 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3325 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3326 /* 3327 * Enable work around for DMA engine miscalculation 3328 * of TXMBUF available space. 3329 */ 3330 sc->bge_flags |= BGEF_RDMA_BUG; 3331 3332 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3333 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3334 /* Jumbo frame on BCM5719 A0 does not work. */ 3335 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3336 } 3337 } 3338 break; 3339 case BGE_ASICREV_BCM5755: 3340 case BGE_ASICREV_BCM5761: 3341 case BGE_ASICREV_BCM5784: 3342 case BGE_ASICREV_BCM5785: 3343 case BGE_ASICREV_BCM5787: 3344 case BGE_ASICREV_BCM57780: 3345 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3346 break; 3347 case BGE_ASICREV_BCM5700: 3348 case BGE_ASICREV_BCM5701: 3349 case BGE_ASICREV_BCM5703: 3350 case BGE_ASICREV_BCM5704: 3351 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3352 break; 3353 case BGE_ASICREV_BCM5714_A0: 3354 case BGE_ASICREV_BCM5780: 3355 case BGE_ASICREV_BCM5714: 3356 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3357 /* FALLTHROUGH */ 3358 case BGE_ASICREV_BCM5750: 3359 case BGE_ASICREV_BCM5752: 3360 case BGE_ASICREV_BCM5906: 3361 sc->bge_flags |= BGEF_575X_PLUS; 3362 /* FALLTHROUGH */ 3363 case BGE_ASICREV_BCM5705: 3364 sc->bge_flags |= BGEF_5705_PLUS; 3365 break; 3366 } 3367 3368 /* Identify chips with APE processor. */ 3369 switch (BGE_ASICREV(sc->bge_chipid)) { 3370 case BGE_ASICREV_BCM5717: 3371 case BGE_ASICREV_BCM5719: 3372 case BGE_ASICREV_BCM5720: 3373 case BGE_ASICREV_BCM5761: 3374 case BGE_ASICREV_BCM5762: 3375 sc->bge_flags |= BGEF_APE; 3376 break; 3377 } 3378 3379 /* 3380 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3381 * not actually a MAC controller bug but an issue with the embedded 3382 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3383 */ 3384 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3385 sc->bge_flags |= BGEF_40BIT_BUG; 3386 3387 /* Chips with APE need BAR2 access for APE registers/memory. */ 3388 if ((sc->bge_flags & BGEF_APE) != 0) { 3389 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3390 #if 0 3391 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3392 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3393 &sc->bge_apesize)) { 3394 aprint_error_dev(sc->bge_dev, 3395 "couldn't map BAR2 memory\n"); 3396 return; 3397 } 3398 #else 3399 /* 3400 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3401 * system get NMI on boot (PR#48451). This problem might not be 3402 * the driver's bug but our PCI common part's bug. Until we 3403 * find a real reason, we ignore the prefetchable bit. 3404 */ 3405 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3406 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3407 aprint_error_dev(sc->bge_dev, 3408 "couldn't map BAR2 memory\n"); 3409 return; 3410 } 3411 3412 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3413 if (bus_space_map(pa->pa_memt, memaddr, 3414 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3415 aprint_error_dev(sc->bge_dev, 3416 "couldn't map BAR2 memory\n"); 3417 return; 3418 } 3419 sc->bge_apetag = pa->pa_memt; 3420 #endif 3421 3422 /* Enable APE register/memory access by host driver. */ 3423 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3424 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3425 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3426 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3427 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3428 3429 bge_ape_lock_init(sc); 3430 bge_ape_read_fw_ver(sc); 3431 } 3432 3433 /* Identify the chips that use an CPMU. */ 3434 if (BGE_IS_5717_PLUS(sc) || 3435 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3436 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3437 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3438 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3439 sc->bge_flags |= BGEF_CPMU_PRESENT; 3440 3441 /* 3442 * When using the BCM5701 in PCI-X mode, data corruption has 3443 * been observed in the first few bytes of some received packets. 3444 * Aligning the packet buffer in memory eliminates the corruption. 3445 * Unfortunately, this misaligns the packet payloads. On platforms 3446 * which do not support unaligned accesses, we will realign the 3447 * payloads by copying the received packets. 3448 */ 3449 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3450 sc->bge_flags & BGEF_PCIX) 3451 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3452 3453 if (BGE_IS_5700_FAMILY(sc)) 3454 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3455 3456 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3457 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3458 3459 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3460 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3461 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3462 sc->bge_flags |= BGEF_IS_5788; 3463 3464 /* 3465 * Some controllers seem to require a special firmware to use 3466 * TSO. But the firmware is not available to FreeBSD and Linux 3467 * claims that the TSO performed by the firmware is slower than 3468 * hardware based TSO. Moreover the firmware based TSO has one 3469 * known bug which can't handle TSO if ethernet header + IP/TCP 3470 * header is greater than 80 bytes. The workaround for the TSO 3471 * bug exist but it seems it's too expensive than not using 3472 * TSO at all. Some hardwares also have the TSO bug so limit 3473 * the TSO to the controllers that are not affected TSO issues 3474 * (e.g. 5755 or higher). 3475 */ 3476 if (BGE_IS_5755_PLUS(sc)) { 3477 /* 3478 * BCM5754 and BCM5787 shares the same ASIC id so 3479 * explicit device id check is required. 3480 */ 3481 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3482 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3483 sc->bge_flags |= BGEF_TSO; 3484 /* TSO on BCM5719 A0 does not work. */ 3485 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3486 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3487 sc->bge_flags &= ~BGEF_TSO; 3488 } 3489 3490 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3491 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3492 (misccfg == 0x4000 || misccfg == 0x8000)) || 3493 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3494 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3495 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3496 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3497 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3498 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3499 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3500 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3501 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3502 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3503 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3504 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3505 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3506 /* These chips are 10/100 only. */ 3507 capmask &= ~BMSR_EXTSTAT; 3508 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3509 } 3510 3511 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3512 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3513 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3514 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3515 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3516 3517 /* Set various PHY bug flags. */ 3518 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3519 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3520 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3521 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3522 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3523 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3524 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3525 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3526 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3527 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3528 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3529 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3530 if (BGE_IS_5705_PLUS(sc) && 3531 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3532 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3533 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3534 !BGE_IS_57765_PLUS(sc)) { 3535 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3536 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3537 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3538 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3539 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3540 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3541 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3542 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3543 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3544 } else 3545 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3546 } 3547 3548 /* 3549 * SEEPROM check. 3550 * First check if firmware knows we do not have SEEPROM. 3551 */ 3552 if (prop_dictionary_get_bool(device_properties(self), 3553 "without-seeprom", &no_seeprom) && no_seeprom) 3554 sc->bge_flags |= BGEF_NO_EEPROM; 3555 3556 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3557 sc->bge_flags |= BGEF_NO_EEPROM; 3558 3559 /* Now check the 'ROM failed' bit on the RX CPU */ 3560 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3561 sc->bge_flags |= BGEF_NO_EEPROM; 3562 3563 sc->bge_asf_mode = 0; 3564 /* No ASF if APE present. */ 3565 if ((sc->bge_flags & BGEF_APE) == 0) { 3566 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3567 BGE_SRAM_DATA_SIG_MAGIC)) { 3568 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3569 BGE_HWCFG_ASF) { 3570 sc->bge_asf_mode |= ASF_ENABLE; 3571 sc->bge_asf_mode |= ASF_STACKUP; 3572 if (BGE_IS_575X_PLUS(sc)) 3573 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3574 } 3575 } 3576 } 3577 3578 int counts[PCI_INTR_TYPE_SIZE] = { 3579 [PCI_INTR_TYPE_INTX] = 1, 3580 [PCI_INTR_TYPE_MSI] = 1, 3581 [PCI_INTR_TYPE_MSIX] = 1, 3582 }; 3583 int max_type = PCI_INTR_TYPE_MSIX; 3584 3585 if (!bge_can_use_msi(sc)) { 3586 /* MSI broken, allow only INTx */ 3587 max_type = PCI_INTR_TYPE_INTX; 3588 } 3589 3590 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3591 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3592 return; 3593 } 3594 3595 DPRINTFN(5, ("pci_intr_string\n")); 3596 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3597 sizeof(intrbuf)); 3598 DPRINTFN(5, ("pci_intr_establish\n")); 3599 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3600 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3601 if (sc->bge_intrhand == NULL) { 3602 pci_intr_release(pc, sc->bge_pihp, 1); 3603 sc->bge_pihp = NULL; 3604 3605 aprint_error_dev(self, "couldn't establish interrupt"); 3606 if (intrstr != NULL) 3607 aprint_error(" at %s", intrstr); 3608 aprint_error("\n"); 3609 return; 3610 } 3611 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3612 3613 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3614 case PCI_INTR_TYPE_MSIX: 3615 case PCI_INTR_TYPE_MSI: 3616 KASSERT(bge_can_use_msi(sc)); 3617 sc->bge_flags |= BGEF_MSI; 3618 break; 3619 default: 3620 /* nothing to do */ 3621 break; 3622 } 3623 3624 /* 3625 * All controllers except BCM5700 supports tagged status but 3626 * we use tagged status only for MSI case on BCM5717. Otherwise 3627 * MSI on BCM5717 does not work. 3628 */ 3629 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3630 sc->bge_flags |= BGEF_TAGGED_STATUS; 3631 3632 /* 3633 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3634 * lock in bge_reset(). 3635 */ 3636 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3637 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3638 delay(1000); 3639 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3640 3641 bge_stop_fw(sc); 3642 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3643 if (bge_reset(sc)) 3644 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3645 3646 /* 3647 * Read the hardware config word in the first 32k of NIC internal 3648 * memory, or fall back to the config word in the EEPROM. 3649 * Note: on some BCM5700 cards, this value appears to be unset. 3650 */ 3651 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3652 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3653 BGE_SRAM_DATA_SIG_MAGIC) { 3654 uint32_t tmp; 3655 3656 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3657 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3658 BGE_SRAM_DATA_VER_SHIFT; 3659 if ((0 < tmp) && (tmp < 0x100)) 3660 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3661 if (sc->bge_flags & BGEF_PCIE) 3662 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3663 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3664 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3665 if (BGE_IS_5717_PLUS(sc)) 3666 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3667 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3668 bge_read_eeprom(sc, (void *)&hwcfg, 3669 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3670 hwcfg = be32toh(hwcfg); 3671 } 3672 aprint_normal_dev(sc->bge_dev, 3673 "HW config %08x, %08x, %08x, %08x %08x\n", 3674 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3675 3676 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3677 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3678 3679 if (bge_chipinit(sc)) { 3680 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3681 bge_release_resources(sc); 3682 return; 3683 } 3684 3685 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3686 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3687 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3688 DELAY(100); 3689 } 3690 3691 /* Set MI_MODE */ 3692 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3693 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3694 mimode |= BGE_MIMODE_500KHZ_CONST; 3695 else 3696 mimode |= BGE_MIMODE_BASE; 3697 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3698 DELAY(80); 3699 3700 /* 3701 * Get station address from the EEPROM. 3702 */ 3703 if (bge_get_eaddr(sc, eaddr)) { 3704 aprint_error_dev(sc->bge_dev, 3705 "failed to read station address\n"); 3706 bge_release_resources(sc); 3707 return; 3708 } 3709 3710 br = bge_lookup_rev(sc->bge_chipid); 3711 3712 if (br == NULL) { 3713 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3714 sc->bge_chipid); 3715 } else { 3716 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3717 br->br_name, sc->bge_chipid); 3718 } 3719 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3720 3721 /* Allocate the general information block and ring buffers. */ 3722 if (pci_dma64_available(pa)) { 3723 sc->bge_dmatag = pa->pa_dmat64; 3724 sc->bge_dmatag32 = pa->pa_dmat; 3725 sc->bge_dma64 = true; 3726 } else { 3727 sc->bge_dmatag = pa->pa_dmat; 3728 sc->bge_dmatag32 = pa->pa_dmat; 3729 sc->bge_dma64 = false; 3730 } 3731 3732 /* 40bit DMA workaround */ 3733 if (sizeof(bus_addr_t) > 4) { 3734 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3735 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3736 3737 if (bus_dmatag_subregion(olddmatag, 0, 3738 (bus_addr_t)__MASK(40), 3739 &(sc->bge_dmatag), BUS_DMA_NOWAIT) != 0) { 3740 aprint_error_dev(self, 3741 "WARNING: failed to restrict dma range," 3742 " falling back to parent bus dma range\n"); 3743 sc->bge_dmatag = olddmatag; 3744 } 3745 } 3746 } 3747 SLIST_INIT(&sc->txdma_list); 3748 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3749 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3750 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3751 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3752 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3753 return; 3754 } 3755 DPRINTFN(5, ("bus_dmamem_map\n")); 3756 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3757 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3758 BUS_DMA_NOWAIT)) { 3759 aprint_error_dev(sc->bge_dev, 3760 "can't map DMA buffers (%zu bytes)\n", 3761 sizeof(struct bge_ring_data)); 3762 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3763 sc->bge_ring_rseg); 3764 return; 3765 } 3766 DPRINTFN(5, ("bus_dmamem_create\n")); 3767 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3768 sizeof(struct bge_ring_data), 0, 3769 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3770 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3771 bus_dmamem_unmap(sc->bge_dmatag, kva, 3772 sizeof(struct bge_ring_data)); 3773 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3774 sc->bge_ring_rseg); 3775 return; 3776 } 3777 DPRINTFN(5, ("bus_dmamem_load\n")); 3778 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3779 sizeof(struct bge_ring_data), NULL, 3780 BUS_DMA_NOWAIT)) { 3781 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3782 bus_dmamem_unmap(sc->bge_dmatag, kva, 3783 sizeof(struct bge_ring_data)); 3784 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3785 sc->bge_ring_rseg); 3786 return; 3787 } 3788 3789 DPRINTFN(5, ("bzero\n")); 3790 sc->bge_rdata = (struct bge_ring_data *)kva; 3791 3792 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3793 3794 /* Try to allocate memory for jumbo buffers. */ 3795 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3796 if (bge_alloc_jumbo_mem(sc)) { 3797 aprint_error_dev(sc->bge_dev, 3798 "jumbo buffer allocation failed\n"); 3799 } else 3800 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3801 } 3802 3803 /* Set default tuneable values. */ 3804 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3805 sc->bge_rx_coal_ticks = 150; 3806 sc->bge_rx_max_coal_bds = 64; 3807 sc->bge_tx_coal_ticks = 300; 3808 sc->bge_tx_max_coal_bds = 400; 3809 if (BGE_IS_5705_PLUS(sc)) { 3810 sc->bge_tx_coal_ticks = (12 * 5); 3811 sc->bge_tx_max_coal_bds = (12 * 5); 3812 aprint_verbose_dev(sc->bge_dev, 3813 "setting short Tx thresholds\n"); 3814 } 3815 3816 if (BGE_IS_5717_PLUS(sc)) 3817 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3818 else if (BGE_IS_5705_PLUS(sc)) 3819 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3820 else 3821 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3822 3823 /* Set up ifnet structure */ 3824 ifp = &sc->ethercom.ec_if; 3825 ifp->if_softc = sc; 3826 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3827 ifp->if_ioctl = bge_ioctl; 3828 ifp->if_stop = bge_stop; 3829 ifp->if_start = bge_start; 3830 ifp->if_init = bge_init; 3831 ifp->if_watchdog = bge_watchdog; 3832 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3833 IFQ_SET_READY(&ifp->if_snd); 3834 DPRINTFN(5, ("strcpy if_xname\n")); 3835 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3836 3837 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3838 sc->ethercom.ec_if.if_capabilities |= 3839 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3840 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3841 sc->ethercom.ec_if.if_capabilities |= 3842 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3843 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3844 #endif 3845 sc->ethercom.ec_capabilities |= 3846 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3847 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3848 3849 if (sc->bge_flags & BGEF_TSO) 3850 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3851 3852 /* 3853 * Do MII setup. 3854 */ 3855 DPRINTFN(5, ("mii setup\n")); 3856 mii->mii_ifp = ifp; 3857 mii->mii_readreg = bge_miibus_readreg; 3858 mii->mii_writereg = bge_miibus_writereg; 3859 mii->mii_statchg = bge_miibus_statchg; 3860 3861 /* 3862 * Figure out what sort of media we have by checking the hardware 3863 * config word. Note: on some BCM5700 cards, this value appears to be 3864 * unset. If that's the case, we have to rely on identifying the NIC 3865 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3866 * The SysKonnect SK-9D41 is a 1000baseSX card. 3867 */ 3868 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3869 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3870 if (BGE_IS_5705_PLUS(sc)) { 3871 sc->bge_flags |= BGEF_FIBER_MII; 3872 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3873 } else 3874 sc->bge_flags |= BGEF_FIBER_TBI; 3875 } 3876 3877 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3878 if (BGE_IS_JUMBO_CAPABLE(sc)) 3879 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3880 3881 /* set phyflags and chipid before mii_attach() */ 3882 dict = device_properties(self); 3883 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3884 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3885 3886 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3887 macmode &= ~BGE_MACMODE_PORTMODE; 3888 /* Initialize ifmedia structures. */ 3889 if (sc->bge_flags & BGEF_FIBER_TBI) { 3890 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3891 macmode | BGE_PORTMODE_TBI); 3892 DELAY(40); 3893 3894 sc->ethercom.ec_ifmedia = &sc->bge_ifmedia; 3895 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3896 bge_ifmedia_sts); 3897 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3898 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3899 0, NULL); 3900 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3901 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3902 /* Pretend the user requested this setting */ 3903 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3904 } else { 3905 uint16_t phyreg; 3906 int rv; 3907 /* 3908 * Do transceiver setup and tell the firmware the 3909 * driver is down so we can try to get access the 3910 * probe if ASF is running. Retry a couple of times 3911 * if we get a conflict with the ASF firmware accessing 3912 * the PHY. 3913 */ 3914 if (sc->bge_flags & BGEF_FIBER_MII) 3915 macmode |= BGE_PORTMODE_GMII; 3916 else 3917 macmode |= BGE_PORTMODE_MII; 3918 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3919 DELAY(40); 3920 3921 /* 3922 * Do transceiver setup and tell the firmware the 3923 * driver is down so we can try to get access the 3924 * probe if ASF is running. Retry a couple of times 3925 * if we get a conflict with the ASF firmware accessing 3926 * the PHY. 3927 */ 3928 trys = 0; 3929 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3930 sc->ethercom.ec_mii = mii; 3931 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3932 bge_ifmedia_sts); 3933 mii_flags = MIIF_DOPAUSE; 3934 if (sc->bge_flags & BGEF_FIBER_MII) 3935 mii_flags |= MIIF_HAVEFIBER; 3936 again: 3937 bge_asf_driver_up(sc); 3938 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 3939 MII_BMCR, &phyreg); 3940 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 3941 int i; 3942 3943 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 3944 MII_BMCR, BMCR_RESET); 3945 /* Wait up to 500ms for it to complete. */ 3946 for (i = 0; i < 500; i++) { 3947 bge_miibus_readreg(sc->bge_dev, 3948 sc->bge_phy_addr, MII_BMCR, &phyreg); 3949 if ((phyreg & BMCR_RESET) == 0) 3950 break; 3951 DELAY(1000); 3952 } 3953 } 3954 3955 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 3956 MII_OFFSET_ANY, mii_flags); 3957 3958 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 3959 goto again; 3960 3961 if (LIST_EMPTY(&mii->mii_phys)) { 3962 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3963 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 3964 0, NULL); 3965 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 3966 } else 3967 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 3968 3969 /* 3970 * Now tell the firmware we are going up after probing the PHY 3971 */ 3972 if (sc->bge_asf_mode & ASF_STACKUP) 3973 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3974 } 3975 3976 /* 3977 * Call MI attach routine. 3978 */ 3979 DPRINTFN(5, ("if_attach\n")); 3980 if_attach(ifp); 3981 if_deferred_start_init(ifp, NULL); 3982 DPRINTFN(5, ("ether_ifattach\n")); 3983 ether_ifattach(ifp, eaddr); 3984 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3985 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3986 RND_TYPE_NET, RND_FLAG_DEFAULT); 3987 #ifdef BGE_EVENT_COUNTERS 3988 /* 3989 * Attach event counters. 3990 */ 3991 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3992 NULL, device_xname(sc->bge_dev), "intr"); 3993 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3994 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3995 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3996 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3997 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3998 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3999 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4000 NULL, device_xname(sc->bge_dev), "tx_xon"); 4001 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4002 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4003 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4004 NULL, device_xname(sc->bge_dev), "rx_xon"); 4005 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4006 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4007 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4008 NULL, device_xname(sc->bge_dev), "xoffentered"); 4009 #endif /* BGE_EVENT_COUNTERS */ 4010 DPRINTFN(5, ("callout_init\n")); 4011 callout_init(&sc->bge_timeout, 0); 4012 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4013 4014 if (pmf_device_register(self, NULL, NULL)) 4015 pmf_class_network_register(self, ifp); 4016 else 4017 aprint_error_dev(self, "couldn't establish power handler\n"); 4018 4019 bge_sysctl_init(sc); 4020 4021 #ifdef BGE_DEBUG 4022 bge_debug_info(sc); 4023 #endif 4024 } 4025 4026 /* 4027 * Stop all chip I/O so that the kernel's probe routines don't 4028 * get confused by errant DMAs when rebooting. 4029 */ 4030 static int 4031 bge_detach(device_t self, int flags __unused) 4032 { 4033 struct bge_softc * const sc = device_private(self); 4034 struct ifnet * const ifp = &sc->ethercom.ec_if; 4035 int s; 4036 4037 s = splnet(); 4038 /* Stop the interface. Callouts are stopped in it. */ 4039 bge_stop(ifp, 1); 4040 splx(s); 4041 4042 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4043 4044 ether_ifdetach(ifp); 4045 if_detach(ifp); 4046 4047 /* Delete all remaining media. */ 4048 ifmedia_fini(&sc->bge_mii.mii_media); 4049 4050 bge_release_resources(sc); 4051 4052 return 0; 4053 } 4054 4055 static void 4056 bge_release_resources(struct bge_softc *sc) 4057 { 4058 4059 /* Detach sysctl */ 4060 if (sc->bge_log != NULL) 4061 sysctl_teardown(&sc->bge_log); 4062 4063 #ifdef BGE_EVENT_COUNTERS 4064 /* Detach event counters. */ 4065 evcnt_detach(&sc->bge_ev_intr); 4066 evcnt_detach(&sc->bge_ev_intr_spurious); 4067 evcnt_detach(&sc->bge_ev_intr_spurious2); 4068 evcnt_detach(&sc->bge_ev_tx_xoff); 4069 evcnt_detach(&sc->bge_ev_tx_xon); 4070 evcnt_detach(&sc->bge_ev_rx_xoff); 4071 evcnt_detach(&sc->bge_ev_rx_xon); 4072 evcnt_detach(&sc->bge_ev_rx_macctl); 4073 evcnt_detach(&sc->bge_ev_xoffentered); 4074 #endif /* BGE_EVENT_COUNTERS */ 4075 4076 /* Disestablish the interrupt handler */ 4077 if (sc->bge_intrhand != NULL) { 4078 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4079 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4080 sc->bge_intrhand = NULL; 4081 } 4082 4083 if (sc->bge_dmatag != NULL) { 4084 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4085 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4086 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4087 sizeof(struct bge_ring_data)); 4088 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4089 sc->bge_ring_rseg); 4090 } 4091 4092 /* Unmap the device registers */ 4093 if (sc->bge_bsize != 0) { 4094 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4095 sc->bge_bsize = 0; 4096 } 4097 4098 /* Unmap the APE registers */ 4099 if (sc->bge_apesize != 0) { 4100 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4101 sc->bge_apesize); 4102 sc->bge_apesize = 0; 4103 } 4104 } 4105 4106 static int 4107 bge_reset(struct bge_softc *sc) 4108 { 4109 uint32_t cachesize, command; 4110 uint32_t reset, mac_mode, mac_mode_mask; 4111 pcireg_t devctl, reg; 4112 int i, val; 4113 void (*write_op)(struct bge_softc *, int, int); 4114 4115 /* Make mask for BGE_MAC_MODE register. */ 4116 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4117 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4118 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4119 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4120 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4121 4122 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4123 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4124 if (sc->bge_flags & BGEF_PCIE) 4125 write_op = bge_writemem_direct; 4126 else 4127 write_op = bge_writemem_ind; 4128 } else 4129 write_op = bge_writereg_ind; 4130 4131 /* 57XX step 4 */ 4132 /* Acquire the NVM lock */ 4133 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4134 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4135 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4136 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4137 for (i = 0; i < 8000; i++) { 4138 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4139 BGE_NVRAMSWARB_GNT1) 4140 break; 4141 DELAY(20); 4142 } 4143 if (i == 8000) { 4144 printf("%s: NVRAM lock timedout!\n", 4145 device_xname(sc->bge_dev)); 4146 } 4147 } 4148 4149 /* Take APE lock when performing reset. */ 4150 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4151 4152 /* 57XX step 3 */ 4153 /* Save some important PCI state. */ 4154 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4155 /* 5718 reset step 3 */ 4156 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4157 4158 /* 5718 reset step 5, 57XX step 5b-5d */ 4159 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4160 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4161 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4162 4163 /* XXX ???: Disable fastboot on controllers that support it. */ 4164 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4165 BGE_IS_5755_PLUS(sc)) 4166 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4167 4168 /* 5718 reset step 2, 57XX step 6 */ 4169 /* 4170 * Write the magic number to SRAM at offset 0xB50. 4171 * When firmware finishes its initialization it will 4172 * write ~BGE_MAGIC_NUMBER to the same location. 4173 */ 4174 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4175 4176 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4177 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4178 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4179 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4180 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4181 } 4182 4183 /* 5718 reset step 6, 57XX step 7 */ 4184 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4185 /* 4186 * XXX: from FreeBSD/Linux; no documentation 4187 */ 4188 if (sc->bge_flags & BGEF_PCIE) { 4189 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4190 !BGE_IS_57765_PLUS(sc) && 4191 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4192 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4193 /* PCI Express 1.0 system */ 4194 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4195 BGE_PHY_PCIE_SCRAM_MODE); 4196 } 4197 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4198 /* 4199 * Prevent PCI Express link training 4200 * during global reset. 4201 */ 4202 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4203 reset |= (1 << 29); 4204 } 4205 } 4206 4207 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4208 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4209 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4210 i | BGE_VCPU_STATUS_DRV_RESET); 4211 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4212 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4213 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4214 } 4215 4216 /* 4217 * Set GPHY Power Down Override to leave GPHY 4218 * powered up in D0 uninitialized. 4219 */ 4220 if (BGE_IS_5705_PLUS(sc) && 4221 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4222 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4223 4224 /* Issue global reset */ 4225 write_op(sc, BGE_MISC_CFG, reset); 4226 4227 /* 5718 reset step 7, 57XX step 8 */ 4228 if (sc->bge_flags & BGEF_PCIE) 4229 delay(100*1000); /* too big */ 4230 else 4231 delay(1000); 4232 4233 if (sc->bge_flags & BGEF_PCIE) { 4234 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4235 DELAY(500000); 4236 /* XXX: Magic Numbers */ 4237 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4238 BGE_PCI_UNKNOWN0); 4239 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4240 BGE_PCI_UNKNOWN0, 4241 reg | (1 << 15)); 4242 } 4243 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4244 sc->bge_pciecap + PCIE_DCSR); 4245 /* Clear enable no snoop and disable relaxed ordering. */ 4246 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4247 PCIE_DCSR_ENA_NO_SNOOP); 4248 4249 /* Set PCIE max payload size to 128 for older PCIe devices */ 4250 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4251 devctl &= ~(0x00e0); 4252 /* Clear device status register. Write 1b to clear */ 4253 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4254 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4255 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4256 sc->bge_pciecap + PCIE_DCSR, devctl); 4257 bge_set_max_readrq(sc); 4258 } 4259 4260 /* From Linux: dummy read to flush PCI posted writes */ 4261 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4262 4263 /* 4264 * Reset some of the PCI state that got zapped by reset 4265 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4266 * set, too. 4267 */ 4268 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4269 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4270 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4271 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4272 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4273 (sc->bge_flags & BGEF_PCIX) != 0) 4274 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4275 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4276 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4277 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4278 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4279 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4280 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4281 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4282 4283 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4284 if (sc->bge_flags & BGEF_PCIX) { 4285 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4286 + PCIX_CMD); 4287 /* Set max memory read byte count to 2K */ 4288 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4289 reg &= ~PCIX_CMD_BYTECNT_MASK; 4290 reg |= PCIX_CMD_BCNT_2048; 4291 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4292 /* 4293 * For 5704, set max outstanding split transaction 4294 * field to 0 (0 means it supports 1 request) 4295 */ 4296 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4297 | PCIX_CMD_BYTECNT_MASK); 4298 reg |= PCIX_CMD_BCNT_2048; 4299 } 4300 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4301 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4302 } 4303 4304 /* 5718 reset step 10, 57XX step 12 */ 4305 /* Enable memory arbiter. */ 4306 if (BGE_IS_5714_FAMILY(sc)) { 4307 val = CSR_READ_4(sc, BGE_MARB_MODE); 4308 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4309 } else 4310 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4311 4312 /* XXX 5721, 5751 and 5752 */ 4313 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4314 /* Step 19: */ 4315 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4316 /* Step 20: */ 4317 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4318 } 4319 4320 /* 5718 reset step 12, 57XX step 15 and 16 */ 4321 /* Fix up byte swapping */ 4322 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4323 4324 /* 5718 reset step 13, 57XX step 17 */ 4325 /* Poll until the firmware initialization is complete */ 4326 bge_poll_fw(sc); 4327 4328 /* 57XX step 21 */ 4329 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4330 pcireg_t msidata; 4331 4332 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4333 BGE_PCI_MSI_DATA); 4334 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4335 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4336 msidata); 4337 } 4338 4339 /* 57XX step 18 */ 4340 /* Write mac mode. */ 4341 val = CSR_READ_4(sc, BGE_MAC_MODE); 4342 /* Restore mac_mode_mask's bits using mac_mode */ 4343 val = (val & ~mac_mode_mask) | mac_mode; 4344 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4345 DELAY(40); 4346 4347 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4348 4349 /* 4350 * The 5704 in TBI mode apparently needs some special 4351 * adjustment to insure the SERDES drive level is set 4352 * to 1.2V. 4353 */ 4354 if (sc->bge_flags & BGEF_FIBER_TBI && 4355 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4356 uint32_t serdescfg; 4357 4358 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4359 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4360 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4361 } 4362 4363 if (sc->bge_flags & BGEF_PCIE && 4364 !BGE_IS_57765_PLUS(sc) && 4365 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4366 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4367 uint32_t v; 4368 4369 /* Enable PCI Express bug fix */ 4370 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4371 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4372 v | BGE_TLP_DATA_FIFO_PROTECT); 4373 } 4374 4375 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4376 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4377 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4378 4379 return 0; 4380 } 4381 4382 /* 4383 * Frame reception handling. This is called if there's a frame 4384 * on the receive return list. 4385 * 4386 * Note: we have to be able to handle two possibilities here: 4387 * 1) the frame is from the jumbo receive ring 4388 * 2) the frame is from the standard receive ring 4389 */ 4390 4391 static void 4392 bge_rxeof(struct bge_softc *sc) 4393 { 4394 struct ifnet *ifp; 4395 uint16_t rx_prod, rx_cons; 4396 int stdcnt = 0, jumbocnt = 0; 4397 bus_dmamap_t dmamap; 4398 bus_addr_t offset, toff; 4399 bus_size_t tlen; 4400 int tosync; 4401 4402 rx_cons = sc->bge_rx_saved_considx; 4403 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4404 4405 /* Nothing to do */ 4406 if (rx_cons == rx_prod) 4407 return; 4408 4409 ifp = &sc->ethercom.ec_if; 4410 4411 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4412 offsetof(struct bge_ring_data, bge_status_block), 4413 sizeof (struct bge_status_block), 4414 BUS_DMASYNC_POSTREAD); 4415 4416 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4417 tosync = rx_prod - rx_cons; 4418 4419 if (tosync != 0) 4420 rnd_add_uint32(&sc->rnd_source, tosync); 4421 4422 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4423 4424 if (tosync < 0) { 4425 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4426 sizeof (struct bge_rx_bd); 4427 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4428 toff, tlen, BUS_DMASYNC_POSTREAD); 4429 tosync = -tosync; 4430 } 4431 4432 if (tosync != 0) { 4433 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4434 offset, tosync * sizeof (struct bge_rx_bd), 4435 BUS_DMASYNC_POSTREAD); 4436 } 4437 4438 while (rx_cons != rx_prod) { 4439 struct bge_rx_bd *cur_rx; 4440 uint32_t rxidx; 4441 struct mbuf *m = NULL; 4442 4443 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4444 4445 rxidx = cur_rx->bge_idx; 4446 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4447 4448 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4449 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4450 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4451 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4452 jumbocnt++; 4453 bus_dmamap_sync(sc->bge_dmatag, 4454 sc->bge_cdata.bge_rx_jumbo_map, 4455 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4456 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4457 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4458 if_statinc(ifp, if_ierrors); 4459 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4460 continue; 4461 } 4462 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4463 NULL)== ENOBUFS) { 4464 if_statinc(ifp, if_ierrors); 4465 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4466 continue; 4467 } 4468 } else { 4469 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4470 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4471 4472 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4473 stdcnt++; 4474 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4475 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4476 if (dmamap == NULL) { 4477 if_statinc(ifp, if_ierrors); 4478 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4479 continue; 4480 } 4481 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4482 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4483 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4484 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4485 if_statinc(ifp, if_ierrors); 4486 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4487 continue; 4488 } 4489 if (bge_newbuf_std(sc, sc->bge_std, 4490 NULL, dmamap) == ENOBUFS) { 4491 if_statinc(ifp, if_ierrors); 4492 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4493 continue; 4494 } 4495 } 4496 4497 #ifndef __NO_STRICT_ALIGNMENT 4498 /* 4499 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4500 * the Rx buffer has the layer-2 header unaligned. 4501 * If our CPU requires alignment, re-align by copying. 4502 */ 4503 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4504 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4505 cur_rx->bge_len); 4506 m->m_data += ETHER_ALIGN; 4507 } 4508 #endif 4509 4510 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4511 m_set_rcvif(m, ifp); 4512 4513 bge_rxcsum(sc, cur_rx, m); 4514 4515 /* 4516 * If we received a packet with a vlan tag, pass it 4517 * to vlan_input() instead of ether_input(). 4518 */ 4519 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4520 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4521 4522 if_percpuq_enqueue(ifp->if_percpuq, m); 4523 } 4524 4525 sc->bge_rx_saved_considx = rx_cons; 4526 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4527 if (stdcnt) 4528 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4529 if (jumbocnt) 4530 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4531 } 4532 4533 static void 4534 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4535 { 4536 4537 if (BGE_IS_57765_PLUS(sc)) { 4538 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4539 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4540 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4541 if ((cur_rx->bge_error_flag & 4542 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4543 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4544 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4545 m->m_pkthdr.csum_data = 4546 cur_rx->bge_tcp_udp_csum; 4547 m->m_pkthdr.csum_flags |= 4548 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4549 } 4550 } 4551 } else { 4552 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4553 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4554 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4555 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4556 /* 4557 * Rx transport checksum-offload may also 4558 * have bugs with packets which, when transmitted, 4559 * were `runts' requiring padding. 4560 */ 4561 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4562 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4563 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4564 m->m_pkthdr.csum_data = 4565 cur_rx->bge_tcp_udp_csum; 4566 m->m_pkthdr.csum_flags |= 4567 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4568 } 4569 } 4570 } 4571 4572 static void 4573 bge_txeof(struct bge_softc *sc) 4574 { 4575 struct bge_tx_bd *cur_tx = NULL; 4576 struct ifnet *ifp; 4577 struct txdmamap_pool_entry *dma; 4578 bus_addr_t offset, toff; 4579 bus_size_t tlen; 4580 int tosync; 4581 struct mbuf *m; 4582 4583 ifp = &sc->ethercom.ec_if; 4584 4585 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4586 offsetof(struct bge_ring_data, bge_status_block), 4587 sizeof (struct bge_status_block), 4588 BUS_DMASYNC_POSTREAD); 4589 4590 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4591 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4592 sc->bge_tx_saved_considx; 4593 4594 if (tosync != 0) 4595 rnd_add_uint32(&sc->rnd_source, tosync); 4596 4597 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4598 4599 if (tosync < 0) { 4600 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4601 sizeof (struct bge_tx_bd); 4602 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4603 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4604 tosync = -tosync; 4605 } 4606 4607 if (tosync != 0) { 4608 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4609 offset, tosync * sizeof (struct bge_tx_bd), 4610 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4611 } 4612 4613 /* 4614 * Go through our tx ring and free mbufs for those 4615 * frames that have been sent. 4616 */ 4617 while (sc->bge_tx_saved_considx != 4618 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4619 uint32_t idx = 0; 4620 4621 idx = sc->bge_tx_saved_considx; 4622 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4623 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4624 if_statinc(ifp, if_opackets); 4625 m = sc->bge_cdata.bge_tx_chain[idx]; 4626 if (m != NULL) { 4627 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4628 dma = sc->txdma[idx]; 4629 if (dma->is_dma32) { 4630 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4631 0, dma->dmamap32->dm_mapsize, 4632 BUS_DMASYNC_POSTWRITE); 4633 bus_dmamap_unload( 4634 sc->bge_dmatag32, dma->dmamap32); 4635 } else { 4636 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4637 0, dma->dmamap->dm_mapsize, 4638 BUS_DMASYNC_POSTWRITE); 4639 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4640 } 4641 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4642 sc->txdma[idx] = NULL; 4643 4644 m_freem(m); 4645 } 4646 sc->bge_txcnt--; 4647 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4648 ifp->if_timer = 0; 4649 } 4650 4651 if (cur_tx != NULL) 4652 ifp->if_flags &= ~IFF_OACTIVE; 4653 } 4654 4655 static int 4656 bge_intr(void *xsc) 4657 { 4658 struct bge_softc * const sc = xsc; 4659 struct ifnet * const ifp = &sc->ethercom.ec_if; 4660 uint32_t pcistate, statusword, statustag; 4661 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4662 4663 4664 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4665 if (BGE_IS_5717_PLUS(sc)) 4666 intrmask = 0; 4667 4668 /* 4669 * It is possible for the interrupt to arrive before 4670 * the status block is updated prior to the interrupt. 4671 * Reading the PCI State register will confirm whether the 4672 * interrupt is ours and will flush the status block. 4673 */ 4674 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4675 4676 /* read status word from status block */ 4677 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4678 offsetof(struct bge_ring_data, bge_status_block), 4679 sizeof (struct bge_status_block), 4680 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4681 statusword = sc->bge_rdata->bge_status_block.bge_status; 4682 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4683 4684 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4685 if (sc->bge_lasttag == statustag && 4686 (~pcistate & intrmask)) { 4687 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4688 return (0); 4689 } 4690 sc->bge_lasttag = statustag; 4691 } else { 4692 if (!(statusword & BGE_STATFLAG_UPDATED) && 4693 !(~pcistate & intrmask)) { 4694 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4695 return (0); 4696 } 4697 statustag = 0; 4698 } 4699 /* Ack interrupt and stop others from occurring. */ 4700 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4701 BGE_EVCNT_INCR(sc->bge_ev_intr); 4702 4703 /* clear status word */ 4704 sc->bge_rdata->bge_status_block.bge_status = 0; 4705 4706 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4707 offsetof(struct bge_ring_data, bge_status_block), 4708 sizeof (struct bge_status_block), 4709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4710 4711 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4712 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4713 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4714 bge_link_upd(sc); 4715 4716 if (ifp->if_flags & IFF_RUNNING) { 4717 /* Check RX return ring producer/consumer */ 4718 bge_rxeof(sc); 4719 4720 /* Check TX ring producer/consumer */ 4721 bge_txeof(sc); 4722 } 4723 4724 if (sc->bge_pending_rxintr_change) { 4725 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4726 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4727 4728 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4729 DELAY(10); 4730 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4731 4732 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4733 DELAY(10); 4734 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4735 4736 sc->bge_pending_rxintr_change = 0; 4737 } 4738 bge_handle_events(sc); 4739 4740 /* Re-enable interrupts. */ 4741 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4742 4743 if (ifp->if_flags & IFF_RUNNING) 4744 if_schedule_deferred_start(ifp); 4745 4746 return 1; 4747 } 4748 4749 static void 4750 bge_asf_driver_up(struct bge_softc *sc) 4751 { 4752 if (sc->bge_asf_mode & ASF_STACKUP) { 4753 /* Send ASF heartbeat aprox. every 2s */ 4754 if (sc->bge_asf_count) 4755 sc->bge_asf_count --; 4756 else { 4757 sc->bge_asf_count = 2; 4758 4759 bge_wait_for_event_ack(sc); 4760 4761 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4762 BGE_FW_CMD_DRV_ALIVE3); 4763 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4764 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4765 BGE_FW_HB_TIMEOUT_SEC); 4766 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4767 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4768 BGE_RX_CPU_DRV_EVENT); 4769 } 4770 } 4771 } 4772 4773 static void 4774 bge_tick(void *xsc) 4775 { 4776 struct bge_softc * const sc = xsc; 4777 struct mii_data * const mii = &sc->bge_mii; 4778 int s; 4779 4780 s = splnet(); 4781 4782 if (BGE_IS_5705_PLUS(sc)) 4783 bge_stats_update_regs(sc); 4784 else 4785 bge_stats_update(sc); 4786 4787 if (sc->bge_flags & BGEF_FIBER_TBI) { 4788 /* 4789 * Since in TBI mode auto-polling can't be used we should poll 4790 * link status manually. Here we register pending link event 4791 * and trigger interrupt. 4792 */ 4793 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4794 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4795 } else { 4796 /* 4797 * Do not touch PHY if we have link up. This could break 4798 * IPMI/ASF mode or produce extra input errors. 4799 * (extra input errors was reported for bcm5701 & bcm5704). 4800 */ 4801 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4802 mii_tick(mii); 4803 } 4804 4805 bge_asf_driver_up(sc); 4806 4807 if (!sc->bge_detaching) 4808 callout_schedule(&sc->bge_timeout, hz); 4809 4810 splx(s); 4811 } 4812 4813 static void 4814 bge_stats_update_regs(struct bge_softc *sc) 4815 { 4816 struct ifnet *const ifp = &sc->ethercom.ec_if; 4817 4818 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4819 4820 if_statadd_ref(nsr, if_collisions, 4821 CSR_READ_4(sc, BGE_MAC_STATS + 4822 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4823 4824 /* 4825 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4826 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4827 * (silicon bug). There's no reliable workaround so just 4828 * ignore the counter 4829 */ 4830 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4831 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4832 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4833 if_statadd_ref(nsr, if_ierrors, 4834 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4835 } 4836 if_statadd_ref(nsr, if_ierrors, 4837 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4838 if_statadd_ref(nsr, if_ierrors, 4839 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4840 4841 IF_STAT_PUTREF(ifp); 4842 4843 if (sc->bge_flags & BGEF_RDMA_BUG) { 4844 uint32_t val, ucast, mcast, bcast; 4845 4846 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4847 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4848 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4849 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4850 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4851 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4852 4853 /* 4854 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4855 * frames, it's safe to disable workaround for DMA engine's 4856 * miscalculation of TXMBUF space. 4857 */ 4858 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4859 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4860 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4861 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4862 else 4863 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4864 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4865 sc->bge_flags &= ~BGEF_RDMA_BUG; 4866 } 4867 } 4868 } 4869 4870 static void 4871 bge_stats_update(struct bge_softc *sc) 4872 { 4873 struct ifnet * const ifp = &sc->ethercom.ec_if; 4874 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4875 4876 #define READ_STAT(sc, stats, stat) \ 4877 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4878 4879 uint64_t collisions = 4880 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4881 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4882 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4883 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4884 4885 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4886 sc->bge_if_collisions = collisions; 4887 4888 4889 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4890 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4891 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4892 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4893 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4894 READ_STAT(sc, stats, 4895 xoffPauseFramesReceived.bge_addr_lo)); 4896 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4897 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4898 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4899 READ_STAT(sc, stats, 4900 macControlFramesReceived.bge_addr_lo)); 4901 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4902 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4903 4904 #undef READ_STAT 4905 4906 #ifdef notdef 4907 ifp->if_collisions += 4908 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4909 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4910 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4911 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4912 ifp->if_collisions; 4913 #endif 4914 } 4915 4916 /* 4917 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4918 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4919 * but when such padded frames employ the bge IP/TCP checksum offload, 4920 * the hardware checksum assist gives incorrect results (possibly 4921 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4922 * If we pad such runts with zeros, the onboard checksum comes out correct. 4923 */ 4924 static inline int 4925 bge_cksum_pad(struct mbuf *pkt) 4926 { 4927 struct mbuf *last = NULL; 4928 int padlen; 4929 4930 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4931 4932 /* if there's only the packet-header and we can pad there, use it. */ 4933 if (pkt->m_pkthdr.len == pkt->m_len && 4934 M_TRAILINGSPACE(pkt) >= padlen) { 4935 last = pkt; 4936 } else { 4937 /* 4938 * Walk packet chain to find last mbuf. We will either 4939 * pad there, or append a new mbuf and pad it 4940 * (thus perhaps avoiding the bcm5700 dma-min bug). 4941 */ 4942 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4943 continue; /* do nothing */ 4944 } 4945 4946 /* `last' now points to last in chain. */ 4947 if (M_TRAILINGSPACE(last) < padlen) { 4948 /* Allocate new empty mbuf, pad it. Compact later. */ 4949 struct mbuf *n; 4950 MGET(n, M_DONTWAIT, MT_DATA); 4951 if (n == NULL) 4952 return ENOBUFS; 4953 n->m_len = 0; 4954 last->m_next = n; 4955 last = n; 4956 } 4957 } 4958 4959 KDASSERT(!M_READONLY(last)); 4960 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4961 4962 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4963 memset(mtod(last, char *) + last->m_len, 0, padlen); 4964 last->m_len += padlen; 4965 pkt->m_pkthdr.len += padlen; 4966 return 0; 4967 } 4968 4969 /* 4970 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4971 */ 4972 static inline int 4973 bge_compact_dma_runt(struct mbuf *pkt) 4974 { 4975 struct mbuf *m, *prev; 4976 int totlen; 4977 4978 prev = NULL; 4979 totlen = 0; 4980 4981 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 4982 int mlen = m->m_len; 4983 int shortfall = 8 - mlen ; 4984 4985 totlen += mlen; 4986 if (mlen == 0) 4987 continue; 4988 if (mlen >= 8) 4989 continue; 4990 4991 /* 4992 * If we get here, mbuf data is too small for DMA engine. 4993 * Try to fix by shuffling data to prev or next in chain. 4994 * If that fails, do a compacting deep-copy of the whole chain. 4995 */ 4996 4997 /* Internal frag. If fits in prev, copy it there. */ 4998 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4999 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5000 prev->m_len += mlen; 5001 m->m_len = 0; 5002 /* XXX stitch chain */ 5003 prev->m_next = m_free(m); 5004 m = prev; 5005 continue; 5006 } else if (m->m_next != NULL && 5007 M_TRAILINGSPACE(m) >= shortfall && 5008 m->m_next->m_len >= (8 + shortfall)) { 5009 /* m is writable and have enough data in next, pull up. */ 5010 5011 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5012 shortfall); 5013 m->m_len += shortfall; 5014 m->m_next->m_len -= shortfall; 5015 m->m_next->m_data += shortfall; 5016 } else if (m->m_next == NULL || 1) { 5017 /* 5018 * Got a runt at the very end of the packet. 5019 * borrow data from the tail of the preceding mbuf and 5020 * update its length in-place. (The original data is 5021 * still valid, so we can do this even if prev is not 5022 * writable.) 5023 */ 5024 5025 /* 5026 * If we'd make prev a runt, just move all of its data. 5027 */ 5028 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5029 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5030 5031 if ((prev->m_len - shortfall) < 8) 5032 shortfall = prev->m_len; 5033 5034 #ifdef notyet /* just do the safe slow thing for now */ 5035 if (!M_READONLY(m)) { 5036 if (M_LEADINGSPACE(m) < shorfall) { 5037 void *m_dat; 5038 m_dat = M_BUFADDR(m); 5039 memmove(m_dat, mtod(m, void*), 5040 m->m_len); 5041 m->m_data = m_dat; 5042 } 5043 } else 5044 #endif /* just do the safe slow thing */ 5045 { 5046 struct mbuf * n = NULL; 5047 int newprevlen = prev->m_len - shortfall; 5048 5049 MGET(n, M_NOWAIT, MT_DATA); 5050 if (n == NULL) 5051 return ENOBUFS; 5052 KASSERT(m->m_len + shortfall < MLEN 5053 /*, 5054 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5055 5056 /* first copy the data we're stealing from prev */ 5057 memcpy(n->m_data, prev->m_data + newprevlen, 5058 shortfall); 5059 5060 /* update prev->m_len accordingly */ 5061 prev->m_len -= shortfall; 5062 5063 /* copy data from runt m */ 5064 memcpy(n->m_data + shortfall, m->m_data, 5065 m->m_len); 5066 5067 /* n holds what we stole from prev, plus m */ 5068 n->m_len = shortfall + m->m_len; 5069 5070 /* stitch n into chain and free m */ 5071 n->m_next = m->m_next; 5072 prev->m_next = n; 5073 /* KASSERT(m->m_next == NULL); */ 5074 m->m_next = NULL; 5075 m_free(m); 5076 m = n; /* for continuing loop */ 5077 } 5078 } 5079 } 5080 return 0; 5081 } 5082 5083 /* 5084 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5085 * pointers to descriptors. 5086 */ 5087 static int 5088 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5089 { 5090 struct ifnet * const ifp = &sc->ethercom.ec_if; 5091 struct bge_tx_bd *f, *prev_f; 5092 uint32_t frag, cur; 5093 uint16_t csum_flags = 0; 5094 uint16_t txbd_tso_flags = 0; 5095 struct txdmamap_pool_entry *dma; 5096 bus_dmamap_t dmamap; 5097 bus_dma_tag_t dmatag; 5098 int i = 0; 5099 int use_tso, maxsegsize, error; 5100 bool have_vtag; 5101 uint16_t vtag; 5102 bool remap; 5103 5104 if (m_head->m_pkthdr.csum_flags) { 5105 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5106 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5107 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5108 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5109 } 5110 5111 /* 5112 * If we were asked to do an outboard checksum, and the NIC 5113 * has the bug where it sometimes adds in the Ethernet padding, 5114 * explicitly pad with zeros so the cksum will be correct either way. 5115 * (For now, do this for all chip versions, until newer 5116 * are confirmed to not require the workaround.) 5117 */ 5118 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5119 #ifdef notyet 5120 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5121 #endif 5122 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5123 goto check_dma_bug; 5124 5125 if (bge_cksum_pad(m_head) != 0) 5126 return ENOBUFS; 5127 5128 check_dma_bug: 5129 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5130 goto doit; 5131 5132 /* 5133 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5134 * less than eight bytes. If we encounter a teeny mbuf 5135 * at the end of a chain, we can pad. Otherwise, copy. 5136 */ 5137 if (bge_compact_dma_runt(m_head) != 0) 5138 return ENOBUFS; 5139 5140 doit: 5141 dma = SLIST_FIRST(&sc->txdma_list); 5142 if (dma == NULL) { 5143 ifp->if_flags |= IFF_OACTIVE; 5144 return ENOBUFS; 5145 } 5146 dmamap = dma->dmamap; 5147 dmatag = sc->bge_dmatag; 5148 dma->is_dma32 = false; 5149 5150 /* 5151 * Set up any necessary TSO state before we start packing... 5152 */ 5153 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5154 if (!use_tso) { 5155 maxsegsize = 0; 5156 } else { /* TSO setup */ 5157 unsigned mss; 5158 struct ether_header *eh; 5159 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5160 unsigned bge_hlen; 5161 struct mbuf * m0 = m_head; 5162 struct ip *ip; 5163 struct tcphdr *th; 5164 int iphl, hlen; 5165 5166 /* 5167 * XXX It would be nice if the mbuf pkthdr had offset 5168 * fields for the protocol headers. 5169 */ 5170 5171 eh = mtod(m0, struct ether_header *); 5172 switch (htons(eh->ether_type)) { 5173 case ETHERTYPE_IP: 5174 offset = ETHER_HDR_LEN; 5175 break; 5176 5177 case ETHERTYPE_VLAN: 5178 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5179 break; 5180 5181 default: 5182 /* 5183 * Don't support this protocol or encapsulation. 5184 */ 5185 return ENOBUFS; 5186 } 5187 5188 /* 5189 * TCP/IP headers are in the first mbuf; we can do 5190 * this the easy way. 5191 */ 5192 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5193 hlen = iphl + offset; 5194 if (__predict_false(m0->m_len < 5195 (hlen + sizeof(struct tcphdr)))) { 5196 5197 aprint_error_dev(sc->bge_dev, 5198 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5199 "not handled yet\n", 5200 m0->m_len, hlen+ sizeof(struct tcphdr)); 5201 #ifdef NOTYET 5202 /* 5203 * XXX jonathan (at) NetBSD.org: untested. 5204 * how to force this branch to be taken? 5205 */ 5206 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5207 5208 m_copydata(m0, offset, sizeof(ip), &ip); 5209 m_copydata(m0, hlen, sizeof(th), &th); 5210 5211 ip.ip_len = 0; 5212 5213 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5214 sizeof(ip.ip_len), &ip.ip_len); 5215 5216 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5217 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5218 5219 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5220 sizeof(th.th_sum), &th.th_sum); 5221 5222 hlen += th.th_off << 2; 5223 iptcp_opt_words = hlen; 5224 #else 5225 /* 5226 * if_wm "hard" case not yet supported, can we not 5227 * mandate it out of existence? 5228 */ 5229 (void) ip; (void)th; (void) ip_tcp_hlen; 5230 5231 return ENOBUFS; 5232 #endif 5233 } else { 5234 ip = (struct ip *) (mtod(m0, char *) + offset); 5235 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5236 ip_tcp_hlen = iphl + (th->th_off << 2); 5237 5238 /* Total IP/TCP options, in 32-bit words */ 5239 iptcp_opt_words = (ip_tcp_hlen 5240 - sizeof(struct tcphdr) 5241 - sizeof(struct ip)) >> 2; 5242 } 5243 if (BGE_IS_575X_PLUS(sc)) { 5244 th->th_sum = 0; 5245 csum_flags = 0; 5246 } else { 5247 /* 5248 * XXX jonathan (at) NetBSD.org: 5705 untested. 5249 * Requires TSO firmware patch for 5701/5703/5704. 5250 */ 5251 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5252 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5253 } 5254 5255 mss = m_head->m_pkthdr.segsz; 5256 txbd_tso_flags |= 5257 BGE_TXBDFLAG_CPU_PRE_DMA | 5258 BGE_TXBDFLAG_CPU_POST_DMA; 5259 5260 /* 5261 * Our NIC TSO-assist assumes TSO has standard, optionless 5262 * IPv4 and TCP headers, which total 40 bytes. By default, 5263 * the NIC copies 40 bytes of IP/TCP header from the 5264 * supplied header into the IP/TCP header portion of 5265 * each post-TSO-segment. If the supplied packet has IP or 5266 * TCP options, we need to tell the NIC to copy those extra 5267 * bytes into each post-TSO header, in addition to the normal 5268 * 40-byte IP/TCP header (and to leave space accordingly). 5269 * Unfortunately, the driver encoding of option length 5270 * varies across different ASIC families. 5271 */ 5272 tcp_seg_flags = 0; 5273 bge_hlen = ip_tcp_hlen >> 2; 5274 if (BGE_IS_5717_PLUS(sc)) { 5275 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5276 txbd_tso_flags |= 5277 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5278 } else if (BGE_IS_5705_PLUS(sc)) { 5279 tcp_seg_flags = bge_hlen << 11; 5280 } else { 5281 /* XXX iptcp_opt_words or bge_hlen ? */ 5282 txbd_tso_flags |= iptcp_opt_words << 12; 5283 } 5284 maxsegsize = mss | tcp_seg_flags; 5285 ip->ip_len = htons(mss + ip_tcp_hlen); 5286 ip->ip_sum = 0; 5287 5288 } /* TSO setup */ 5289 5290 have_vtag = vlan_has_tag(m_head); 5291 if (have_vtag) 5292 vtag = vlan_get_tag(m_head); 5293 5294 /* 5295 * Start packing the mbufs in this chain into 5296 * the fragment pointers. Stop when we run out 5297 * of fragments or hit the end of the mbuf chain. 5298 */ 5299 remap = true; 5300 load_again: 5301 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5302 if (__predict_false(error)) { 5303 if (error == EFBIG && remap) { 5304 struct mbuf *m; 5305 remap = false; 5306 m = m_defrag(m_head, M_NOWAIT); 5307 if (m != NULL) { 5308 KASSERT(m == m_head); 5309 goto load_again; 5310 } 5311 } 5312 return error; 5313 } 5314 /* 5315 * Sanity check: avoid coming within 16 descriptors 5316 * of the end of the ring. 5317 */ 5318 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5319 BGE_TSO_PRINTF(("%s: " 5320 " dmamap_load_mbuf too close to ring wrap\n", 5321 device_xname(sc->bge_dev))); 5322 goto fail_unload; 5323 } 5324 5325 /* Iterate over dmap-map fragments. */ 5326 f = prev_f = NULL; 5327 cur = frag = *txidx; 5328 5329 for (i = 0; i < dmamap->dm_nsegs; i++) { 5330 f = &sc->bge_rdata->bge_tx_ring[frag]; 5331 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5332 break; 5333 5334 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5335 f->bge_len = dmamap->dm_segs[i].ds_len; 5336 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5337 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5338 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5339 (prev_f != NULL && 5340 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5341 ) { 5342 /* 5343 * watchdog timeout issue was observed with TSO, 5344 * limiting DMA address space to 32bits seems to 5345 * address the issue. 5346 */ 5347 bus_dmamap_unload(dmatag, dmamap); 5348 dmatag = sc->bge_dmatag32; 5349 dmamap = dma->dmamap32; 5350 dma->is_dma32 = true; 5351 remap = true; 5352 goto load_again; 5353 } 5354 5355 /* 5356 * For 5751 and follow-ons, for TSO we must turn 5357 * off checksum-assist flag in the tx-descr, and 5358 * supply the ASIC-revision-specific encoding 5359 * of TSO flags and segsize. 5360 */ 5361 if (use_tso) { 5362 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5363 f->bge_rsvd = maxsegsize; 5364 f->bge_flags = csum_flags | txbd_tso_flags; 5365 } else { 5366 f->bge_rsvd = 0; 5367 f->bge_flags = 5368 (csum_flags | txbd_tso_flags) & 0x0fff; 5369 } 5370 } else { 5371 f->bge_rsvd = 0; 5372 f->bge_flags = csum_flags; 5373 } 5374 5375 if (have_vtag) { 5376 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5377 f->bge_vlan_tag = vtag; 5378 } else { 5379 f->bge_vlan_tag = 0; 5380 } 5381 prev_f = f; 5382 cur = frag; 5383 BGE_INC(frag, BGE_TX_RING_CNT); 5384 } 5385 5386 if (i < dmamap->dm_nsegs) { 5387 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5388 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5389 goto fail_unload; 5390 } 5391 5392 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5393 BUS_DMASYNC_PREWRITE); 5394 5395 if (frag == sc->bge_tx_saved_considx) { 5396 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5397 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5398 5399 goto fail_unload; 5400 } 5401 5402 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5403 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5404 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5405 sc->txdma[cur] = dma; 5406 sc->bge_txcnt += dmamap->dm_nsegs; 5407 5408 *txidx = frag; 5409 5410 return 0; 5411 5412 fail_unload: 5413 bus_dmamap_unload(dmatag, dmamap); 5414 ifp->if_flags |= IFF_OACTIVE; 5415 5416 return ENOBUFS; 5417 } 5418 5419 /* 5420 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5421 * to the mbuf data regions directly in the transmit descriptors. 5422 */ 5423 static void 5424 bge_start(struct ifnet *ifp) 5425 { 5426 struct bge_softc * const sc = ifp->if_softc; 5427 struct mbuf *m_head = NULL; 5428 struct mbuf *m; 5429 uint32_t prodidx; 5430 int pkts = 0; 5431 int error; 5432 5433 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5434 return; 5435 5436 prodidx = sc->bge_tx_prodidx; 5437 5438 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5439 IFQ_POLL(&ifp->if_snd, m_head); 5440 if (m_head == NULL) 5441 break; 5442 5443 #if 0 5444 /* 5445 * XXX 5446 * safety overkill. If this is a fragmented packet chain 5447 * with delayed TCP/UDP checksums, then only encapsulate 5448 * it if we have enough descriptors to handle the entire 5449 * chain at once. 5450 * (paranoia -- may not actually be needed) 5451 */ 5452 if (m_head->m_flags & M_FIRSTFRAG && 5453 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5454 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5455 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5456 ifp->if_flags |= IFF_OACTIVE; 5457 break; 5458 } 5459 } 5460 #endif 5461 5462 /* 5463 * Pack the data into the transmit ring. If we 5464 * don't have room, set the OACTIVE flag and wait 5465 * for the NIC to drain the ring. 5466 */ 5467 error = bge_encap(sc, m_head, &prodidx); 5468 if (__predict_false(error)) { 5469 if (ifp->if_flags & IFF_OACTIVE) { 5470 /* just wait for the transmit ring to drain */ 5471 break; 5472 } 5473 IFQ_DEQUEUE(&ifp->if_snd, m); 5474 KASSERT(m == m_head); 5475 m_freem(m_head); 5476 continue; 5477 } 5478 5479 /* now we are committed to transmit the packet */ 5480 IFQ_DEQUEUE(&ifp->if_snd, m); 5481 KASSERT(m == m_head); 5482 pkts++; 5483 5484 /* 5485 * If there's a BPF listener, bounce a copy of this frame 5486 * to him. 5487 */ 5488 bpf_mtap(ifp, m_head, BPF_D_OUT); 5489 } 5490 if (pkts == 0) 5491 return; 5492 5493 /* Transmit */ 5494 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5495 /* 5700 b2 errata */ 5496 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5497 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5498 5499 sc->bge_tx_prodidx = prodidx; 5500 5501 /* 5502 * Set a timeout in case the chip goes out to lunch. 5503 */ 5504 ifp->if_timer = 5; 5505 } 5506 5507 static int 5508 bge_init(struct ifnet *ifp) 5509 { 5510 struct bge_softc * const sc = ifp->if_softc; 5511 const uint16_t *m; 5512 uint32_t mode, reg; 5513 int s, error = 0; 5514 5515 s = splnet(); 5516 5517 ifp = &sc->ethercom.ec_if; 5518 5519 /* Cancel pending I/O and flush buffers. */ 5520 bge_stop(ifp, 0); 5521 5522 bge_stop_fw(sc); 5523 bge_sig_pre_reset(sc, BGE_RESET_START); 5524 bge_reset(sc); 5525 bge_sig_legacy(sc, BGE_RESET_START); 5526 5527 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5528 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5529 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5530 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5531 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5532 5533 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5534 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5535 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5536 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5537 5538 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5539 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5540 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5541 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5542 5543 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5544 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5545 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5546 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5547 } 5548 5549 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5550 pcireg_t aercap; 5551 5552 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5553 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5554 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5555 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5556 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5557 5558 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5559 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5560 | BGE_PCIE_EIDLE_DELAY_13CLK; 5561 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5562 5563 /* Clear correctable error */ 5564 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5565 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5566 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5567 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5568 5569 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5570 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5571 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5572 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5573 } 5574 5575 bge_sig_post_reset(sc, BGE_RESET_START); 5576 5577 bge_chipinit(sc); 5578 5579 /* 5580 * Init the various state machines, ring 5581 * control blocks and firmware. 5582 */ 5583 error = bge_blockinit(sc); 5584 if (error != 0) { 5585 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5586 error); 5587 splx(s); 5588 return error; 5589 } 5590 5591 /* 5718 step 25, 57XX step 54 */ 5592 /* Specify MTU. */ 5593 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5594 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5595 5596 /* 5718 step 23 */ 5597 /* Load our MAC address. */ 5598 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5599 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5600 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5601 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5602 5603 /* Enable or disable promiscuous mode as needed. */ 5604 if (ifp->if_flags & IFF_PROMISC) 5605 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5606 else 5607 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5608 5609 /* Program multicast filter. */ 5610 bge_setmulti(sc); 5611 5612 /* Init RX ring. */ 5613 bge_init_rx_ring_std(sc); 5614 5615 /* 5616 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5617 * memory to insure that the chip has in fact read the first 5618 * entry of the ring. 5619 */ 5620 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5621 uint32_t v, i; 5622 for (i = 0; i < 10; i++) { 5623 DELAY(20); 5624 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5625 if (v == (MCLBYTES - ETHER_ALIGN)) 5626 break; 5627 } 5628 if (i == 10) 5629 aprint_error_dev(sc->bge_dev, 5630 "5705 A0 chip failed to load RX ring\n"); 5631 } 5632 5633 /* Init jumbo RX ring. */ 5634 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5635 bge_init_rx_ring_jumbo(sc); 5636 5637 /* Init our RX return ring index */ 5638 sc->bge_rx_saved_considx = 0; 5639 5640 /* Init TX ring. */ 5641 bge_init_tx_ring(sc); 5642 5643 /* 5718 step 63, 57XX step 94 */ 5644 /* Enable TX MAC state machine lockup fix. */ 5645 mode = CSR_READ_4(sc, BGE_TX_MODE); 5646 if (BGE_IS_5755_PLUS(sc) || 5647 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5648 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5649 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5650 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5651 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5652 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5653 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5654 } 5655 5656 /* Turn on transmitter */ 5657 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5658 /* 5718 step 64 */ 5659 DELAY(100); 5660 5661 /* 5718 step 65, 57XX step 95 */ 5662 /* Turn on receiver */ 5663 mode = CSR_READ_4(sc, BGE_RX_MODE); 5664 if (BGE_IS_5755_PLUS(sc)) 5665 mode |= BGE_RXMODE_IPV6_ENABLE; 5666 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5667 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5668 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5669 /* 5718 step 66 */ 5670 DELAY(10); 5671 5672 /* 5718 step 12, 57XX step 37 */ 5673 /* 5674 * XXX Doucments of 5718 series and 577xx say the recommended value 5675 * is 1, but tg3 set 1 only on 57765 series. 5676 */ 5677 if (BGE_IS_57765_PLUS(sc)) 5678 reg = 1; 5679 else 5680 reg = 2; 5681 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5682 5683 /* Tell firmware we're alive. */ 5684 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5685 5686 /* Enable host interrupts. */ 5687 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5688 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5689 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5690 5691 if ((error = bge_ifmedia_upd(ifp)) != 0) 5692 goto out; 5693 5694 ifp->if_flags |= IFF_RUNNING; 5695 ifp->if_flags &= ~IFF_OACTIVE; 5696 5697 callout_schedule(&sc->bge_timeout, hz); 5698 5699 out: 5700 sc->bge_if_flags = ifp->if_flags; 5701 splx(s); 5702 5703 return error; 5704 } 5705 5706 /* 5707 * Set media options. 5708 */ 5709 static int 5710 bge_ifmedia_upd(struct ifnet *ifp) 5711 { 5712 struct bge_softc * const sc = ifp->if_softc; 5713 struct mii_data * const mii = &sc->bge_mii; 5714 struct ifmedia * const ifm = &sc->bge_ifmedia; 5715 int rc; 5716 5717 /* If this is a 1000baseX NIC, enable the TBI port. */ 5718 if (sc->bge_flags & BGEF_FIBER_TBI) { 5719 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5720 return EINVAL; 5721 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5722 case IFM_AUTO: 5723 /* 5724 * The BCM5704 ASIC appears to have a special 5725 * mechanism for programming the autoneg 5726 * advertisement registers in TBI mode. 5727 */ 5728 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5729 uint32_t sgdig; 5730 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5731 if (sgdig & BGE_SGDIGSTS_DONE) { 5732 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5733 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5734 sgdig |= BGE_SGDIGCFG_AUTO | 5735 BGE_SGDIGCFG_PAUSE_CAP | 5736 BGE_SGDIGCFG_ASYM_PAUSE; 5737 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5738 sgdig | BGE_SGDIGCFG_SEND); 5739 DELAY(5); 5740 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5741 sgdig); 5742 } 5743 } 5744 break; 5745 case IFM_1000_SX: 5746 if ((ifm->ifm_media & IFM_FDX) != 0) { 5747 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5748 BGE_MACMODE_HALF_DUPLEX); 5749 } else { 5750 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5751 BGE_MACMODE_HALF_DUPLEX); 5752 } 5753 DELAY(40); 5754 break; 5755 default: 5756 return EINVAL; 5757 } 5758 /* XXX 802.3x flow control for 1000BASE-SX */ 5759 return 0; 5760 } 5761 5762 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5763 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5764 uint32_t reg; 5765 5766 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5767 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5768 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5769 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5770 } 5771 } 5772 5773 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5774 if ((rc = mii_mediachg(mii)) == ENXIO) 5775 return 0; 5776 5777 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5778 uint32_t reg; 5779 5780 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5781 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5782 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5783 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5784 delay(40); 5785 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5786 } 5787 } 5788 5789 /* 5790 * Force an interrupt so that we will call bge_link_upd 5791 * if needed and clear any pending link state attention. 5792 * Without this we are not getting any further interrupts 5793 * for link state changes and thus will not UP the link and 5794 * not be able to send in bge_start. The only way to get 5795 * things working was to receive a packet and get a RX intr. 5796 */ 5797 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5798 sc->bge_flags & BGEF_IS_5788) 5799 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5800 else 5801 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5802 5803 return rc; 5804 } 5805 5806 /* 5807 * Report current media status. 5808 */ 5809 static void 5810 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5811 { 5812 struct bge_softc * const sc = ifp->if_softc; 5813 struct mii_data * const mii = &sc->bge_mii; 5814 5815 if (sc->bge_flags & BGEF_FIBER_TBI) { 5816 ifmr->ifm_status = IFM_AVALID; 5817 ifmr->ifm_active = IFM_ETHER; 5818 if (CSR_READ_4(sc, BGE_MAC_STS) & 5819 BGE_MACSTAT_TBI_PCS_SYNCHED) 5820 ifmr->ifm_status |= IFM_ACTIVE; 5821 ifmr->ifm_active |= IFM_1000_SX; 5822 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5823 ifmr->ifm_active |= IFM_HDX; 5824 else 5825 ifmr->ifm_active |= IFM_FDX; 5826 return; 5827 } 5828 5829 mii_pollstat(mii); 5830 ifmr->ifm_status = mii->mii_media_status; 5831 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5832 sc->bge_flowflags; 5833 } 5834 5835 static int 5836 bge_ifflags_cb(struct ethercom *ec) 5837 { 5838 struct ifnet * const ifp = &ec->ec_if; 5839 struct bge_softc * const sc = ifp->if_softc; 5840 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5841 5842 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 5843 return ENETRESET; 5844 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5845 return 0; 5846 5847 if ((ifp->if_flags & IFF_PROMISC) == 0) 5848 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5849 else 5850 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5851 5852 bge_setmulti(sc); 5853 5854 sc->bge_if_flags = ifp->if_flags; 5855 return 0; 5856 } 5857 5858 static int 5859 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5860 { 5861 struct bge_softc * const sc = ifp->if_softc; 5862 struct ifreq * const ifr = (struct ifreq *) data; 5863 int s, error = 0; 5864 struct mii_data *mii; 5865 5866 s = splnet(); 5867 5868 switch (command) { 5869 case SIOCSIFMEDIA: 5870 /* XXX Flow control is not supported for 1000BASE-SX */ 5871 if (sc->bge_flags & BGEF_FIBER_TBI) { 5872 ifr->ifr_media &= ~IFM_ETH_FMASK; 5873 sc->bge_flowflags = 0; 5874 } 5875 5876 /* Flow control requires full-duplex mode. */ 5877 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5878 (ifr->ifr_media & IFM_FDX) == 0) { 5879 ifr->ifr_media &= ~IFM_ETH_FMASK; 5880 } 5881 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5882 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5883 /* We can do both TXPAUSE and RXPAUSE. */ 5884 ifr->ifr_media |= 5885 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5886 } 5887 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5888 } 5889 5890 if (sc->bge_flags & BGEF_FIBER_TBI) { 5891 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5892 command); 5893 } else { 5894 mii = &sc->bge_mii; 5895 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5896 command); 5897 } 5898 break; 5899 default: 5900 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5901 break; 5902 5903 error = 0; 5904 5905 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5906 ; 5907 else if (ifp->if_flags & IFF_RUNNING) 5908 bge_setmulti(sc); 5909 break; 5910 } 5911 5912 splx(s); 5913 5914 return error; 5915 } 5916 5917 static void 5918 bge_watchdog(struct ifnet *ifp) 5919 { 5920 struct bge_softc * const sc = ifp->if_softc; 5921 uint32_t status; 5922 5923 /* If pause frames are active then don't reset the hardware. */ 5924 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5925 status = CSR_READ_4(sc, BGE_RX_STS); 5926 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5927 /* 5928 * If link partner has us in XOFF state then wait for 5929 * the condition to clear. 5930 */ 5931 CSR_WRITE_4(sc, BGE_RX_STS, status); 5932 ifp->if_timer = 5; 5933 return; 5934 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5935 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5936 /* 5937 * If link partner has us in XOFF state then wait for 5938 * the condition to clear. 5939 */ 5940 CSR_WRITE_4(sc, BGE_RX_STS, status); 5941 ifp->if_timer = 5; 5942 return; 5943 } 5944 /* 5945 * Any other condition is unexpected and the controller 5946 * should be reset. 5947 */ 5948 } 5949 5950 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5951 5952 ifp->if_flags &= ~IFF_RUNNING; 5953 bge_init(ifp); 5954 5955 if_statinc(ifp, if_oerrors); 5956 } 5957 5958 static void 5959 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5960 { 5961 int i; 5962 5963 BGE_CLRBIT_FLUSH(sc, reg, bit); 5964 5965 for (i = 0; i < 1000; i++) { 5966 delay(100); 5967 if ((CSR_READ_4(sc, reg) & bit) == 0) 5968 return; 5969 } 5970 5971 /* 5972 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5973 * on some environment (and once after boot?) 5974 */ 5975 if (reg != BGE_SRS_MODE) 5976 aprint_error_dev(sc->bge_dev, 5977 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5978 (u_long)reg, bit); 5979 } 5980 5981 /* 5982 * Stop the adapter and free any mbufs allocated to the 5983 * RX and TX lists. 5984 */ 5985 static void 5986 bge_stop(struct ifnet *ifp, int disable) 5987 { 5988 struct bge_softc * const sc = ifp->if_softc; 5989 5990 if (disable) { 5991 sc->bge_detaching = 1; 5992 callout_halt(&sc->bge_timeout, NULL); 5993 } else 5994 callout_stop(&sc->bge_timeout); 5995 5996 /* Disable host interrupts. */ 5997 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5998 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5999 6000 /* 6001 * Tell firmware we're shutting down. 6002 */ 6003 bge_stop_fw(sc); 6004 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6005 6006 /* 6007 * Disable all of the receiver blocks. 6008 */ 6009 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6010 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6011 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6012 if (BGE_IS_5700_FAMILY(sc)) 6013 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6014 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6015 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6016 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6017 6018 /* 6019 * Disable all of the transmit blocks. 6020 */ 6021 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6022 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6023 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6024 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6025 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6026 if (BGE_IS_5700_FAMILY(sc)) 6027 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6028 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6029 6030 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6031 delay(40); 6032 6033 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6034 6035 /* 6036 * Shut down all of the memory managers and related 6037 * state machines. 6038 */ 6039 /* 5718 step 5a,5b */ 6040 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6041 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6042 if (BGE_IS_5700_FAMILY(sc)) 6043 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6044 6045 /* 5718 step 5c,5d */ 6046 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6047 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6048 6049 if (BGE_IS_5700_FAMILY(sc)) { 6050 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6051 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6052 } 6053 6054 bge_reset(sc); 6055 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6056 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6057 6058 /* 6059 * Keep the ASF firmware running if up. 6060 */ 6061 if (sc->bge_asf_mode & ASF_STACKUP) 6062 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6063 else 6064 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6065 6066 /* Free the RX lists. */ 6067 bge_free_rx_ring_std(sc, disable); 6068 6069 /* Free jumbo RX list. */ 6070 if (BGE_IS_JUMBO_CAPABLE(sc)) 6071 bge_free_rx_ring_jumbo(sc); 6072 6073 /* Free TX buffers. */ 6074 bge_free_tx_ring(sc, disable); 6075 6076 /* 6077 * Isolate/power down the PHY. 6078 */ 6079 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6080 mii_down(&sc->bge_mii); 6081 6082 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6083 6084 /* Clear MAC's link state (PHY may still have link UP). */ 6085 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6086 6087 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6088 } 6089 6090 static void 6091 bge_link_upd(struct bge_softc *sc) 6092 { 6093 struct ifnet * const ifp = &sc->ethercom.ec_if; 6094 struct mii_data * const mii = &sc->bge_mii; 6095 uint32_t status; 6096 uint16_t phyval; 6097 int link; 6098 6099 /* Clear 'pending link event' flag */ 6100 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6101 6102 /* 6103 * Process link state changes. 6104 * Grrr. The link status word in the status block does 6105 * not work correctly on the BCM5700 rev AX and BX chips, 6106 * according to all available information. Hence, we have 6107 * to enable MII interrupts in order to properly obtain 6108 * async link changes. Unfortunately, this also means that 6109 * we have to read the MAC status register to detect link 6110 * changes, thereby adding an additional register access to 6111 * the interrupt handler. 6112 */ 6113 6114 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6115 status = CSR_READ_4(sc, BGE_MAC_STS); 6116 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6117 mii_pollstat(mii); 6118 6119 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6120 mii->mii_media_status & IFM_ACTIVE && 6121 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6122 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6123 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6124 (!(mii->mii_media_status & IFM_ACTIVE) || 6125 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6126 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6127 6128 /* Clear the interrupt */ 6129 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6130 BGE_EVTENB_MI_INTERRUPT); 6131 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6132 BRGPHY_MII_ISR, &phyval); 6133 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6134 BRGPHY_MII_IMR, BRGPHY_INTRS); 6135 } 6136 return; 6137 } 6138 6139 if (sc->bge_flags & BGEF_FIBER_TBI) { 6140 status = CSR_READ_4(sc, BGE_MAC_STS); 6141 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6142 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6143 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6144 if (BGE_ASICREV(sc->bge_chipid) 6145 == BGE_ASICREV_BCM5704) { 6146 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6147 BGE_MACMODE_TBI_SEND_CFGS); 6148 DELAY(40); 6149 } 6150 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6151 if_link_state_change(ifp, LINK_STATE_UP); 6152 } 6153 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6154 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6155 if_link_state_change(ifp, LINK_STATE_DOWN); 6156 } 6157 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6158 /* 6159 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6160 * bit in status word always set. Workaround this bug by 6161 * reading PHY link status directly. 6162 */ 6163 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6164 BGE_STS_LINK : 0; 6165 6166 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6167 mii_pollstat(mii); 6168 6169 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6170 mii->mii_media_status & IFM_ACTIVE && 6171 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6172 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6173 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6174 (!(mii->mii_media_status & IFM_ACTIVE) || 6175 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6176 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6177 } 6178 } else { 6179 /* 6180 * For controllers that call mii_tick, we have to poll 6181 * link status. 6182 */ 6183 mii_pollstat(mii); 6184 } 6185 6186 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6187 uint32_t reg, scale; 6188 6189 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6190 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6191 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6192 scale = 65; 6193 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6194 scale = 6; 6195 else 6196 scale = 12; 6197 6198 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6199 ~BGE_MISCCFG_TIMER_PRESCALER; 6200 reg |= scale << 1; 6201 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6202 } 6203 /* Clear the attention */ 6204 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6205 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6206 BGE_MACSTAT_LINK_CHANGED); 6207 } 6208 6209 static int 6210 bge_sysctl_verify(SYSCTLFN_ARGS) 6211 { 6212 int error, t; 6213 struct sysctlnode node; 6214 6215 node = *rnode; 6216 t = *(int*)rnode->sysctl_data; 6217 node.sysctl_data = &t; 6218 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6219 if (error || newp == NULL) 6220 return error; 6221 6222 #if 0 6223 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6224 node.sysctl_num, rnode->sysctl_num)); 6225 #endif 6226 6227 if (node.sysctl_num == bge_rxthresh_nodenum) { 6228 if (t < 0 || t >= NBGE_RX_THRESH) 6229 return EINVAL; 6230 bge_update_all_threshes(t); 6231 } else 6232 return EINVAL; 6233 6234 *(int*)rnode->sysctl_data = t; 6235 6236 return 0; 6237 } 6238 6239 /* 6240 * Set up sysctl(3) MIB, hw.bge.*. 6241 */ 6242 static void 6243 bge_sysctl_init(struct bge_softc *sc) 6244 { 6245 int rc, bge_root_num; 6246 const struct sysctlnode *node; 6247 6248 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6249 0, CTLTYPE_NODE, "bge", 6250 SYSCTL_DESCR("BGE interface controls"), 6251 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6252 goto out; 6253 } 6254 6255 bge_root_num = node->sysctl_num; 6256 6257 /* BGE Rx interrupt mitigation level */ 6258 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6259 CTLFLAG_READWRITE, 6260 CTLTYPE_INT, "rx_lvl", 6261 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6262 bge_sysctl_verify, 0, 6263 &bge_rx_thresh_lvl, 6264 0, CTL_HW, bge_root_num, CTL_CREATE, 6265 CTL_EOL)) != 0) { 6266 goto out; 6267 } 6268 6269 bge_rxthresh_nodenum = node->sysctl_num; 6270 6271 return; 6272 6273 out: 6274 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6275 } 6276 6277 #ifdef BGE_DEBUG 6278 void 6279 bge_debug_info(struct bge_softc *sc) 6280 { 6281 6282 printf("Hardware Flags:\n"); 6283 if (BGE_IS_57765_PLUS(sc)) 6284 printf(" - 57765 Plus\n"); 6285 if (BGE_IS_5717_PLUS(sc)) 6286 printf(" - 5717 Plus\n"); 6287 if (BGE_IS_5755_PLUS(sc)) 6288 printf(" - 5755 Plus\n"); 6289 if (BGE_IS_575X_PLUS(sc)) 6290 printf(" - 575X Plus\n"); 6291 if (BGE_IS_5705_PLUS(sc)) 6292 printf(" - 5705 Plus\n"); 6293 if (BGE_IS_5714_FAMILY(sc)) 6294 printf(" - 5714 Family\n"); 6295 if (BGE_IS_5700_FAMILY(sc)) 6296 printf(" - 5700 Family\n"); 6297 if (sc->bge_flags & BGEF_IS_5788) 6298 printf(" - 5788\n"); 6299 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6300 printf(" - Supports Jumbo Frames\n"); 6301 if (sc->bge_flags & BGEF_NO_EEPROM) 6302 printf(" - No EEPROM\n"); 6303 if (sc->bge_flags & BGEF_PCIX) 6304 printf(" - PCI-X Bus\n"); 6305 if (sc->bge_flags & BGEF_PCIE) 6306 printf(" - PCI Express Bus\n"); 6307 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6308 printf(" - RX Alignment Bug\n"); 6309 if (sc->bge_flags & BGEF_APE) 6310 printf(" - APE\n"); 6311 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6312 printf(" - CPMU\n"); 6313 if (sc->bge_flags & BGEF_TSO) 6314 printf(" - TSO\n"); 6315 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6316 printf(" - TAGGED_STATUS\n"); 6317 6318 /* PHY related */ 6319 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6320 printf(" - No 3 LEDs\n"); 6321 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6322 printf(" - CRC bug\n"); 6323 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6324 printf(" - ADC bug\n"); 6325 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6326 printf(" - 5704 A0 bug\n"); 6327 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6328 printf(" - jitter bug\n"); 6329 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6330 printf(" - BER bug\n"); 6331 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6332 printf(" - adjust trim\n"); 6333 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6334 printf(" - no wirespeed\n"); 6335 6336 /* ASF related */ 6337 if (sc->bge_asf_mode & ASF_ENABLE) 6338 printf(" - ASF enable\n"); 6339 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6340 printf(" - ASF new handshake\n"); 6341 if (sc->bge_asf_mode & ASF_STACKUP) 6342 printf(" - ASF stackup\n"); 6343 } 6344 #endif /* BGE_DEBUG */ 6345 6346 static int 6347 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6348 { 6349 prop_dictionary_t dict; 6350 prop_data_t ea; 6351 6352 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6353 return 1; 6354 6355 dict = device_properties(sc->bge_dev); 6356 ea = prop_dictionary_get(dict, "mac-address"); 6357 if (ea != NULL) { 6358 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6359 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6360 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6361 return 0; 6362 } 6363 6364 return 1; 6365 } 6366 6367 static int 6368 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6369 { 6370 uint32_t mac_addr; 6371 6372 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6373 if ((mac_addr >> 16) == 0x484b) { 6374 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6375 ether_addr[1] = (uint8_t)mac_addr; 6376 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6377 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6378 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6379 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6380 ether_addr[5] = (uint8_t)mac_addr; 6381 return 0; 6382 } 6383 return 1; 6384 } 6385 6386 static int 6387 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6388 { 6389 int mac_offset = BGE_EE_MAC_OFFSET; 6390 6391 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6392 mac_offset = BGE_EE_MAC_OFFSET_5906; 6393 6394 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6395 ETHER_ADDR_LEN)); 6396 } 6397 6398 static int 6399 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6400 { 6401 6402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6403 return 1; 6404 6405 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6406 ETHER_ADDR_LEN)); 6407 } 6408 6409 static int 6410 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6411 { 6412 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6413 /* NOTE: Order is critical */ 6414 bge_get_eaddr_fw, 6415 bge_get_eaddr_mem, 6416 bge_get_eaddr_nvram, 6417 bge_get_eaddr_eeprom, 6418 NULL 6419 }; 6420 const bge_eaddr_fcn_t *func; 6421 6422 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6423 if ((*func)(sc, eaddr) == 0) 6424 break; 6425 } 6426 return (*func == NULL ? ENXIO : 0); 6427 } 6428
Indexes created Tue Sep 23 07:09:52 GMT 2025