if_bge.c revision 1.360
1 /* $NetBSD: if_bge.c,v 1.360 2022/07/02 08:31:43 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.360 2022/07/02 08:31:43 skrll Exp $"); 83 84 #include <sys/param.h> 85 86 #include <sys/callout.h> 87 #include <sys/device.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/kernel.h> 91 #include <sys/rndsource.h> 92 #include <sys/socket.h> 93 #include <sys/sockio.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 #include <net/bpf.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 #include <dev/mii/miidevs.h> 123 #include <dev/mii/brgphyreg.h> 124 125 #include <dev/pci/if_bgereg.h> 126 #include <dev/pci/if_bgevar.h> 127 128 #include <prop/proplib.h> 129 130 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 131 132 133 /* 134 * Tunable thresholds for rx-side bge interrupt mitigation. 135 */ 136 137 /* 138 * The pairs of values below were obtained from empirical measurement 139 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 140 * interrupt for every N packets received, where N is, approximately, 141 * the second value (rx_max_bds) in each pair. The values are chosen 142 * such that moving from one pair to the succeeding pair was observed 143 * to roughly halve interrupt rate under sustained input packet load. 144 * The values were empirically chosen to avoid overflowing internal 145 * limits on the bcm5700: increasing rx_ticks much beyond 600 146 * results in internal wrapping and higher interrupt rates. 147 * The limit of 46 frames was chosen to match NFS workloads. 148 * 149 * These values also work well on bcm5701, bcm5704C, and (less 150 * tested) bcm5703. On other chipsets, (including the Altima chip 151 * family), the larger values may overflow internal chip limits, 152 * leading to increasing interrupt rates rather than lower interrupt 153 * rates. 154 * 155 * Applications using heavy interrupt mitigation (interrupting every 156 * 32 or 46 frames) in both directions may need to increase the TCP 157 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 158 * full link bandwidth, due to ACKs and window updates lingering 159 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 160 */ 161 static const struct bge_load_rx_thresh { 162 int rx_ticks; 163 int rx_max_bds; } 164 bge_rx_threshes[] = { 165 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 166 { 32, 2 }, 167 { 50, 4 }, 168 { 100, 8 }, 169 { 192, 16 }, 170 { 416, 32 }, 171 { 598, 46 } 172 }; 173 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 174 175 /* XXX patchable; should be sysctl'able */ 176 static int bge_auto_thresh = 1; 177 static int bge_rx_thresh_lvl; 178 179 static int bge_rxthresh_nodenum; 180 181 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 182 183 static uint32_t bge_chipid(const struct pci_attach_args *); 184 static int bge_can_use_msi(struct bge_softc *); 185 static int bge_probe(device_t, cfdata_t, void *); 186 static void bge_attach(device_t, device_t, void *); 187 static int bge_detach(device_t, int); 188 static void bge_release_resources(struct bge_softc *); 189 190 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 191 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 195 196 static void bge_txeof(struct bge_softc *); 197 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *m, bool); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_phy_addr(struct bge_softc *); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writembx_flush(struct bge_softc *, int, int); 247 static void bge_writemem_direct(struct bge_softc *, int, int); 248 static void bge_writereg_ind(struct bge_softc *, int, int); 249 static void bge_set_max_readrq(struct bge_softc *); 250 251 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 252 static int bge_miibus_writereg(device_t, int, int, uint16_t); 253 static void bge_miibus_statchg(struct ifnet *); 254 255 #define BGE_RESET_SHUTDOWN 0 256 #define BGE_RESET_START 1 257 #define BGE_RESET_SUSPEND 2 258 static void bge_sig_post_reset(struct bge_softc *, int); 259 static void bge_sig_legacy(struct bge_softc *, int); 260 static void bge_sig_pre_reset(struct bge_softc *, int); 261 static void bge_wait_for_event_ack(struct bge_softc *); 262 static void bge_stop_fw(struct bge_softc *); 263 static int bge_reset(struct bge_softc *); 264 static void bge_link_upd(struct bge_softc *); 265 static void bge_sysctl_init(struct bge_softc *); 266 static int bge_sysctl_verify(SYSCTLFN_PROTO); 267 268 static void bge_ape_lock_init(struct bge_softc *); 269 static void bge_ape_read_fw_ver(struct bge_softc *); 270 static int bge_ape_lock(struct bge_softc *, int); 271 static void bge_ape_unlock(struct bge_softc *, int); 272 static void bge_ape_send_event(struct bge_softc *, uint32_t); 273 static void bge_ape_driver_state_change(struct bge_softc *, int); 274 275 #ifdef BGE_DEBUG 276 #define DPRINTF(x) if (bgedebug) printf x 277 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 278 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 279 int bgedebug = 0; 280 int bge_tso_debug = 0; 281 void bge_debug_info(struct bge_softc *); 282 #else 283 #define DPRINTF(x) 284 #define DPRINTFN(n, x) 285 #define BGE_TSO_PRINTF(x) 286 #endif 287 288 #ifdef BGE_EVENT_COUNTERS 289 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 290 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 291 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 292 #else 293 #define BGE_EVCNT_INCR(ev) /* nothing */ 294 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 295 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 296 #endif 297 298 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 299 /* 300 * The BCM5700 documentation seems to indicate that the hardware still has the 301 * Alteon vendor ID burned into it, though it should always be overridden by 302 * the value in the EEPROM. We'll check for it anyway. 303 */ 304 static const struct bge_product { 305 pci_vendor_id_t bp_vendor; 306 pci_product_id_t bp_product; 307 const char *bp_name; 308 } bge_products[] = { 309 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 310 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 311 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 312 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 313 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 314 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 315 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 319 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 320 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 323 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 349 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 354 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 359 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 363 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 364 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 367 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 368 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 370 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 371 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 372 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 373 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 375 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 376 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 377 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 379 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 380 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 381 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 382 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 383 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 384 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 399 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 400 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 401 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 402 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 403 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 404 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 405 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 406 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 407 { 0, 0, NULL }, 408 }; 409 410 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 411 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 412 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 413 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 414 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 415 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 416 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 417 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 418 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 419 420 static const struct bge_revision { 421 uint32_t br_chipid; 422 const char *br_name; 423 } bge_revisions[] = { 424 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 425 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 426 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 427 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 428 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 429 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 430 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 431 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 432 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 433 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 434 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 435 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 436 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 437 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 438 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 439 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 440 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 441 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 442 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 443 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 444 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 445 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 446 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 447 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 448 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 449 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 450 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 451 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 452 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 453 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 454 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 455 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 456 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 457 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 458 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 459 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 460 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 461 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 462 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 463 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 464 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 465 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 466 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 467 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 468 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 469 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 470 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 471 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 472 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 473 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 474 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 475 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 476 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 477 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 478 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 479 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 480 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 481 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 482 /* 5754 and 5787 share the same ASIC ID */ 483 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 484 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 485 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 486 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 487 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 488 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 489 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 490 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 491 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 492 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 493 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 494 495 { 0, NULL } 496 }; 497 498 /* 499 * Some defaults for major revisions, so that newer steppings 500 * that we don't know about have a shot at working. 501 */ 502 static const struct bge_revision bge_majorrevs[] = { 503 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 504 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 505 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 506 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 507 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 508 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 509 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 510 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 511 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 512 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 513 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 514 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 515 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 516 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 517 /* 5754 and 5787 share the same ASIC ID */ 518 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 519 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 520 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 521 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 522 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 523 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 524 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 525 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 526 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 527 528 { 0, NULL } 529 }; 530 531 static int bge_allow_asf = 1; 532 533 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 534 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 535 536 static uint32_t 537 bge_readmem_ind(struct bge_softc *sc, int off) 538 { 539 pcireg_t val; 540 541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 542 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 543 return 0; 544 545 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 546 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 547 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 548 return val; 549 } 550 551 static void 552 bge_writemem_ind(struct bge_softc *sc, int off, int val) 553 { 554 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 556 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 557 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 558 } 559 560 /* 561 * PCI Express only 562 */ 563 static void 564 bge_set_max_readrq(struct bge_softc *sc) 565 { 566 pcireg_t val; 567 568 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 569 + PCIE_DCSR); 570 val &= ~PCIE_DCSR_MAX_READ_REQ; 571 switch (sc->bge_expmrq) { 572 case 2048: 573 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 574 break; 575 case 4096: 576 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 577 break; 578 default: 579 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 580 break; 581 } 582 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 583 + PCIE_DCSR, val); 584 } 585 586 #ifdef notdef 587 static uint32_t 588 bge_readreg_ind(struct bge_softc *sc, int off) 589 { 590 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 591 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 592 } 593 #endif 594 595 static void 596 bge_writereg_ind(struct bge_softc *sc, int off, int val) 597 { 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 599 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 600 } 601 602 static void 603 bge_writemem_direct(struct bge_softc *sc, int off, int val) 604 { 605 CSR_WRITE_4(sc, off, val); 606 } 607 608 static void 609 bge_writembx(struct bge_softc *sc, int off, int val) 610 { 611 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 612 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 613 614 CSR_WRITE_4(sc, off, val); 615 } 616 617 static void 618 bge_writembx_flush(struct bge_softc *sc, int off, int val) 619 { 620 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 621 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 622 623 CSR_WRITE_4_FLUSH(sc, off, val); 624 } 625 626 /* 627 * Clear all stale locks and select the lock for this driver instance. 628 */ 629 void 630 bge_ape_lock_init(struct bge_softc *sc) 631 { 632 struct pci_attach_args *pa = &(sc->bge_pa); 633 uint32_t bit, regbase; 634 int i; 635 636 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 637 regbase = BGE_APE_LOCK_GRANT; 638 else 639 regbase = BGE_APE_PER_LOCK_GRANT; 640 641 /* Clear any stale locks. */ 642 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 643 switch (i) { 644 case BGE_APE_LOCK_PHY0: 645 case BGE_APE_LOCK_PHY1: 646 case BGE_APE_LOCK_PHY2: 647 case BGE_APE_LOCK_PHY3: 648 bit = BGE_APE_LOCK_GRANT_DRIVER0; 649 break; 650 default: 651 if (pa->pa_function == 0) 652 bit = BGE_APE_LOCK_GRANT_DRIVER0; 653 else 654 bit = (1 << pa->pa_function); 655 } 656 APE_WRITE_4(sc, regbase + 4 * i, bit); 657 } 658 659 /* Select the PHY lock based on the device's function number. */ 660 switch (pa->pa_function) { 661 case 0: 662 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 663 break; 664 case 1: 665 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 666 break; 667 case 2: 668 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 669 break; 670 case 3: 671 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 672 break; 673 default: 674 printf("%s: PHY lock not supported on function\n", 675 device_xname(sc->bge_dev)); 676 break; 677 } 678 } 679 680 /* 681 * Check for APE firmware, set flags, and print version info. 682 */ 683 void 684 bge_ape_read_fw_ver(struct bge_softc *sc) 685 { 686 const char *fwtype; 687 uint32_t apedata, features; 688 689 /* Check for a valid APE signature in shared memory. */ 690 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 691 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 692 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 693 return; 694 } 695 696 /* Check if APE firmware is running. */ 697 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 698 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 699 printf("%s: APE signature found but FW status not ready! " 700 "0x%08x\n", device_xname(sc->bge_dev), apedata); 701 return; 702 } 703 704 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 705 706 /* Fetch the APE firwmare type and version. */ 707 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 708 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 709 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 710 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 711 fwtype = "NCSI"; 712 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 713 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 714 fwtype = "DASH"; 715 } else 716 fwtype = "UNKN"; 717 718 /* Print the APE firmware version. */ 719 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 720 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 721 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 722 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 723 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 724 } 725 726 int 727 bge_ape_lock(struct bge_softc *sc, int locknum) 728 { 729 struct pci_attach_args *pa = &(sc->bge_pa); 730 uint32_t bit, gnt, req, status; 731 int i, off; 732 733 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 734 return (0); 735 736 /* Lock request/grant registers have different bases. */ 737 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 738 req = BGE_APE_LOCK_REQ; 739 gnt = BGE_APE_LOCK_GRANT; 740 } else { 741 req = BGE_APE_PER_LOCK_REQ; 742 gnt = BGE_APE_PER_LOCK_GRANT; 743 } 744 745 off = 4 * locknum; 746 747 switch (locknum) { 748 case BGE_APE_LOCK_GPIO: 749 /* Lock required when using GPIO. */ 750 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 751 return (0); 752 if (pa->pa_function == 0) 753 bit = BGE_APE_LOCK_REQ_DRIVER0; 754 else 755 bit = (1 << pa->pa_function); 756 break; 757 case BGE_APE_LOCK_GRC: 758 /* Lock required to reset the device. */ 759 if (pa->pa_function == 0) 760 bit = BGE_APE_LOCK_REQ_DRIVER0; 761 else 762 bit = (1 << pa->pa_function); 763 break; 764 case BGE_APE_LOCK_MEM: 765 /* Lock required when accessing certain APE memory. */ 766 if (pa->pa_function == 0) 767 bit = BGE_APE_LOCK_REQ_DRIVER0; 768 else 769 bit = (1 << pa->pa_function); 770 break; 771 case BGE_APE_LOCK_PHY0: 772 case BGE_APE_LOCK_PHY1: 773 case BGE_APE_LOCK_PHY2: 774 case BGE_APE_LOCK_PHY3: 775 /* Lock required when accessing PHYs. */ 776 bit = BGE_APE_LOCK_REQ_DRIVER0; 777 break; 778 default: 779 return (EINVAL); 780 } 781 782 /* Request a lock. */ 783 APE_WRITE_4_FLUSH(sc, req + off, bit); 784 785 /* Wait up to 1 second to acquire lock. */ 786 for (i = 0; i < 20000; i++) { 787 status = APE_READ_4(sc, gnt + off); 788 if (status == bit) 789 break; 790 DELAY(50); 791 } 792 793 /* Handle any errors. */ 794 if (status != bit) { 795 printf("%s: APE lock %d request failed! " 796 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 797 device_xname(sc->bge_dev), 798 locknum, req + off, bit & 0xFFFF, gnt + off, 799 status & 0xFFFF); 800 /* Revoke the lock request. */ 801 APE_WRITE_4(sc, gnt + off, bit); 802 return (EBUSY); 803 } 804 805 return (0); 806 } 807 808 void 809 bge_ape_unlock(struct bge_softc *sc, int locknum) 810 { 811 struct pci_attach_args *pa = &(sc->bge_pa); 812 uint32_t bit, gnt; 813 int off; 814 815 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 816 return; 817 818 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 819 gnt = BGE_APE_LOCK_GRANT; 820 else 821 gnt = BGE_APE_PER_LOCK_GRANT; 822 823 off = 4 * locknum; 824 825 switch (locknum) { 826 case BGE_APE_LOCK_GPIO: 827 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 828 return; 829 if (pa->pa_function == 0) 830 bit = BGE_APE_LOCK_GRANT_DRIVER0; 831 else 832 bit = (1 << pa->pa_function); 833 break; 834 case BGE_APE_LOCK_GRC: 835 if (pa->pa_function == 0) 836 bit = BGE_APE_LOCK_GRANT_DRIVER0; 837 else 838 bit = (1 << pa->pa_function); 839 break; 840 case BGE_APE_LOCK_MEM: 841 if (pa->pa_function == 0) 842 bit = BGE_APE_LOCK_GRANT_DRIVER0; 843 else 844 bit = (1 << pa->pa_function); 845 break; 846 case BGE_APE_LOCK_PHY0: 847 case BGE_APE_LOCK_PHY1: 848 case BGE_APE_LOCK_PHY2: 849 case BGE_APE_LOCK_PHY3: 850 bit = BGE_APE_LOCK_GRANT_DRIVER0; 851 break; 852 default: 853 return; 854 } 855 856 /* Write and flush for consecutive bge_ape_lock() */ 857 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 858 } 859 860 /* 861 * Send an event to the APE firmware. 862 */ 863 void 864 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 865 { 866 uint32_t apedata; 867 int i; 868 869 /* NCSI does not support APE events. */ 870 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 871 return; 872 873 /* Wait up to 1ms for APE to service previous event. */ 874 for (i = 10; i > 0; i--) { 875 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 876 break; 877 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 878 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 879 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 880 BGE_APE_EVENT_STATUS_EVENT_PENDING); 881 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 882 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 883 break; 884 } 885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 886 DELAY(100); 887 } 888 if (i == 0) { 889 printf("%s: APE event 0x%08x send timed out\n", 890 device_xname(sc->bge_dev), event); 891 } 892 } 893 894 void 895 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 896 { 897 uint32_t apedata, event; 898 899 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 900 return; 901 902 switch (kind) { 903 case BGE_RESET_START: 904 /* If this is the first load, clear the load counter. */ 905 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 906 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 907 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 908 else { 909 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 910 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 911 } 912 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 913 BGE_APE_HOST_SEG_SIG_MAGIC); 914 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 915 BGE_APE_HOST_SEG_LEN_MAGIC); 916 917 /* Add some version info if bge(4) supports it. */ 918 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 919 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 920 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 921 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 922 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 923 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 924 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 925 BGE_APE_HOST_DRVR_STATE_START); 926 event = BGE_APE_EVENT_STATUS_STATE_START; 927 break; 928 case BGE_RESET_SHUTDOWN: 929 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 930 BGE_APE_HOST_DRVR_STATE_UNLOAD); 931 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 932 break; 933 case BGE_RESET_SUSPEND: 934 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 935 break; 936 default: 937 return; 938 } 939 940 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 941 BGE_APE_EVENT_STATUS_STATE_CHNGE); 942 } 943 944 static uint8_t 945 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 946 { 947 uint32_t access, byte = 0; 948 int i; 949 950 /* Lock. */ 951 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 952 for (i = 0; i < 8000; i++) { 953 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 954 break; 955 DELAY(20); 956 } 957 if (i == 8000) 958 return 1; 959 960 /* Enable access. */ 961 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 962 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 963 964 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 965 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 966 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 967 DELAY(10); 968 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 969 DELAY(10); 970 break; 971 } 972 } 973 974 if (i == BGE_TIMEOUT * 10) { 975 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 976 return 1; 977 } 978 979 /* Get result. */ 980 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 981 982 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 983 984 /* Disable access. */ 985 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 986 987 /* Unlock. */ 988 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 989 990 return 0; 991 } 992 993 /* 994 * Read a sequence of bytes from NVRAM. 995 */ 996 static int 997 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 998 { 999 int error = 0, i; 1000 uint8_t byte = 0; 1001 1002 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1003 return 1; 1004 1005 for (i = 0; i < cnt; i++) { 1006 error = bge_nvram_getbyte(sc, off + i, &byte); 1007 if (error) 1008 break; 1009 *(dest + i) = byte; 1010 } 1011 1012 return (error ? 1 : 0); 1013 } 1014 1015 /* 1016 * Read a byte of data stored in the EEPROM at address 'addr.' The 1017 * BCM570x supports both the traditional bitbang interface and an 1018 * auto access interface for reading the EEPROM. We use the auto 1019 * access method. 1020 */ 1021 static uint8_t 1022 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1023 { 1024 int i; 1025 uint32_t byte = 0; 1026 1027 /* 1028 * Enable use of auto EEPROM access so we can avoid 1029 * having to use the bitbang method. 1030 */ 1031 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1032 1033 /* Reset the EEPROM, load the clock period. */ 1034 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1035 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1036 DELAY(20); 1037 1038 /* Issue the read EEPROM command. */ 1039 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1040 1041 /* Wait for completion */ 1042 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1043 DELAY(10); 1044 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1045 break; 1046 } 1047 1048 if (i == BGE_TIMEOUT * 10) { 1049 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1050 return 1; 1051 } 1052 1053 /* Get result. */ 1054 byte = CSR_READ_4(sc, BGE_EE_DATA); 1055 1056 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1057 1058 return 0; 1059 } 1060 1061 /* 1062 * Read a sequence of bytes from the EEPROM. 1063 */ 1064 static int 1065 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1066 { 1067 int error = 0, i; 1068 uint8_t byte = 0; 1069 char *dest = destv; 1070 1071 for (i = 0; i < cnt; i++) { 1072 error = bge_eeprom_getbyte(sc, off + i, &byte); 1073 if (error) 1074 break; 1075 *(dest + i) = byte; 1076 } 1077 1078 return (error ? 1 : 0); 1079 } 1080 1081 static int 1082 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1083 { 1084 struct bge_softc * const sc = device_private(dev); 1085 uint32_t data; 1086 uint32_t autopoll; 1087 int rv = 0; 1088 int i; 1089 1090 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1091 return -1; 1092 1093 /* Reading with autopolling on may trigger PCI errors */ 1094 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1095 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1096 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1097 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1098 DELAY(80); 1099 } 1100 1101 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1102 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1103 1104 for (i = 0; i < BGE_TIMEOUT; i++) { 1105 delay(10); 1106 data = CSR_READ_4(sc, BGE_MI_COMM); 1107 if (!(data & BGE_MICOMM_BUSY)) { 1108 DELAY(5); 1109 data = CSR_READ_4(sc, BGE_MI_COMM); 1110 break; 1111 } 1112 } 1113 1114 if (i == BGE_TIMEOUT) { 1115 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1116 rv = ETIMEDOUT; 1117 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1118 /* XXX This error occurs on some devices while attaching. */ 1119 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1120 rv = EIO; 1121 } else 1122 *val = data & BGE_MICOMM_DATA; 1123 1124 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1125 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1126 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1127 DELAY(80); 1128 } 1129 1130 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1131 1132 return rv; 1133 } 1134 1135 static int 1136 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1137 { 1138 struct bge_softc * const sc = device_private(dev); 1139 uint32_t data, autopoll; 1140 int rv = 0; 1141 int i; 1142 1143 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1144 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1145 return 0; 1146 1147 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1148 return -1; 1149 1150 /* Reading with autopolling on may trigger PCI errors */ 1151 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1152 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1153 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1154 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1155 DELAY(80); 1156 } 1157 1158 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1159 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1160 1161 for (i = 0; i < BGE_TIMEOUT; i++) { 1162 delay(10); 1163 data = CSR_READ_4(sc, BGE_MI_COMM); 1164 if (!(data & BGE_MICOMM_BUSY)) { 1165 delay(5); 1166 data = CSR_READ_4(sc, BGE_MI_COMM); 1167 break; 1168 } 1169 } 1170 1171 if (i == BGE_TIMEOUT) { 1172 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1173 rv = ETIMEDOUT; 1174 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1175 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1176 rv = EIO; 1177 } 1178 1179 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1180 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1181 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1182 delay(80); 1183 } 1184 1185 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1186 1187 if (i == BGE_TIMEOUT) { 1188 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1189 return ETIMEDOUT; 1190 } 1191 1192 return rv; 1193 } 1194 1195 static void 1196 bge_miibus_statchg(struct ifnet *ifp) 1197 { 1198 struct bge_softc * const sc = ifp->if_softc; 1199 struct mii_data *mii = &sc->bge_mii; 1200 uint32_t mac_mode, rx_mode, tx_mode; 1201 1202 /* 1203 * Get flow control negotiation result. 1204 */ 1205 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1206 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1207 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1208 1209 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1210 mii->mii_media_status & IFM_ACTIVE && 1211 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1212 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1213 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1214 (!(mii->mii_media_status & IFM_ACTIVE) || 1215 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1216 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1217 1218 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1219 return; 1220 1221 /* Set the port mode (MII/GMII) to match the link speed. */ 1222 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1223 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1224 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1225 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1226 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1227 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1228 mac_mode |= BGE_PORTMODE_GMII; 1229 else 1230 mac_mode |= BGE_PORTMODE_MII; 1231 1232 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1233 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1234 if ((mii->mii_media_active & IFM_FDX) != 0) { 1235 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1236 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1237 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1238 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1239 } else 1240 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1241 1242 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1243 DELAY(40); 1244 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1245 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1246 } 1247 1248 /* 1249 * Update rx threshold levels to values in a particular slot 1250 * of the interrupt-mitigation table bge_rx_threshes. 1251 */ 1252 static void 1253 bge_set_thresh(struct ifnet *ifp, int lvl) 1254 { 1255 struct bge_softc * const sc = ifp->if_softc; 1256 int s; 1257 1258 /* 1259 * For now, just save the new Rx-intr thresholds and record 1260 * that a threshold update is pending. Updating the hardware 1261 * registers here (even at splhigh()) is observed to 1262 * occasionally cause glitches where Rx-interrupts are not 1263 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1264 */ 1265 s = splnet(); 1266 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1267 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1268 sc->bge_pending_rxintr_change = 1; 1269 splx(s); 1270 } 1271 1272 1273 /* 1274 * Update Rx thresholds of all bge devices 1275 */ 1276 static void 1277 bge_update_all_threshes(int lvl) 1278 { 1279 const char * const namebuf = "bge"; 1280 const size_t namelen = strlen(namebuf); 1281 struct ifnet *ifp; 1282 1283 if (lvl < 0) 1284 lvl = 0; 1285 else if (lvl >= NBGE_RX_THRESH) 1286 lvl = NBGE_RX_THRESH - 1; 1287 1288 /* 1289 * Now search all the interfaces for this name/number 1290 */ 1291 int s = pserialize_read_enter(); 1292 IFNET_READER_FOREACH(ifp) { 1293 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1294 continue; 1295 /* We got a match: update if doing auto-threshold-tuning */ 1296 if (bge_auto_thresh) 1297 bge_set_thresh(ifp, lvl); 1298 } 1299 pserialize_read_exit(s); 1300 } 1301 1302 /* 1303 * Handle events that have triggered interrupts. 1304 */ 1305 static void 1306 bge_handle_events(struct bge_softc *sc) 1307 { 1308 1309 return; 1310 } 1311 1312 /* 1313 * Memory management for jumbo frames. 1314 */ 1315 1316 static int 1317 bge_alloc_jumbo_mem(struct bge_softc *sc) 1318 { 1319 char *ptr, *kva; 1320 bus_dma_segment_t seg; 1321 int i, rseg, state, error; 1322 struct bge_jpool_entry *entry; 1323 1324 state = error = 0; 1325 1326 /* Grab a big chunk o' storage. */ 1327 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1328 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1329 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1330 return ENOBUFS; 1331 } 1332 1333 state = 1; 1334 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1335 BUS_DMA_NOWAIT)) { 1336 aprint_error_dev(sc->bge_dev, 1337 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1338 error = ENOBUFS; 1339 goto out; 1340 } 1341 1342 state = 2; 1343 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1344 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1345 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1346 error = ENOBUFS; 1347 goto out; 1348 } 1349 1350 state = 3; 1351 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1352 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1353 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1354 error = ENOBUFS; 1355 goto out; 1356 } 1357 1358 state = 4; 1359 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1360 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1361 1362 SLIST_INIT(&sc->bge_jfree_listhead); 1363 SLIST_INIT(&sc->bge_jinuse_listhead); 1364 1365 /* 1366 * Now divide it up into 9K pieces and save the addresses 1367 * in an array. 1368 */ 1369 ptr = sc->bge_cdata.bge_jumbo_buf; 1370 for (i = 0; i < BGE_JSLOTS; i++) { 1371 sc->bge_cdata.bge_jslots[i] = ptr; 1372 ptr += BGE_JLEN; 1373 entry = malloc(sizeof(struct bge_jpool_entry), 1374 M_DEVBUF, M_WAITOK); 1375 entry->slot = i; 1376 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1377 entry, jpool_entries); 1378 } 1379 out: 1380 if (error != 0) { 1381 switch (state) { 1382 case 4: 1383 bus_dmamap_unload(sc->bge_dmatag, 1384 sc->bge_cdata.bge_rx_jumbo_map); 1385 /* FALLTHROUGH */ 1386 case 3: 1387 bus_dmamap_destroy(sc->bge_dmatag, 1388 sc->bge_cdata.bge_rx_jumbo_map); 1389 /* FALLTHROUGH */ 1390 case 2: 1391 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1392 /* FALLTHROUGH */ 1393 case 1: 1394 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1395 break; 1396 default: 1397 break; 1398 } 1399 } 1400 1401 return error; 1402 } 1403 1404 /* 1405 * Allocate a jumbo buffer. 1406 */ 1407 static void * 1408 bge_jalloc(struct bge_softc *sc) 1409 { 1410 struct bge_jpool_entry *entry; 1411 1412 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1413 1414 if (entry == NULL) { 1415 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1416 return NULL; 1417 } 1418 1419 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1420 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1421 return (sc->bge_cdata.bge_jslots[entry->slot]); 1422 } 1423 1424 /* 1425 * Release a jumbo buffer. 1426 */ 1427 static void 1428 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1429 { 1430 struct bge_jpool_entry *entry; 1431 struct bge_softc * const sc = arg; 1432 int i, s; 1433 1434 if (sc == NULL) 1435 panic("bge_jfree: can't find softc pointer!"); 1436 1437 /* calculate the slot this buffer belongs to */ 1438 1439 i = ((char *)buf 1440 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1441 1442 if ((i < 0) || (i >= BGE_JSLOTS)) 1443 panic("bge_jfree: asked to free buffer that we don't manage!"); 1444 1445 s = splvm(); 1446 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1447 if (entry == NULL) 1448 panic("bge_jfree: buffer not in use!"); 1449 entry->slot = i; 1450 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1451 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1452 1453 if (__predict_true(m != NULL)) 1454 pool_cache_put(mb_cache, m); 1455 splx(s); 1456 } 1457 1458 1459 /* 1460 * Initialize a standard receive ring descriptor. 1461 */ 1462 static int 1463 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1464 bus_dmamap_t dmamap) 1465 { 1466 struct mbuf *m_new = NULL; 1467 struct bge_rx_bd *r; 1468 int error; 1469 1470 if (dmamap == NULL) 1471 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1472 1473 if (dmamap == NULL) { 1474 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1475 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1476 if (error != 0) 1477 return error; 1478 } 1479 1480 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1481 1482 if (m == NULL) { 1483 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1484 if (m_new == NULL) 1485 return ENOBUFS; 1486 1487 MCLGET(m_new, M_DONTWAIT); 1488 if (!(m_new->m_flags & M_EXT)) { 1489 m_freem(m_new); 1490 return ENOBUFS; 1491 } 1492 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1493 1494 } else { 1495 m_new = m; 1496 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1497 m_new->m_data = m_new->m_ext.ext_buf; 1498 } 1499 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1500 m_adj(m_new, ETHER_ALIGN); 1501 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1502 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1503 m_freem(m_new); 1504 return ENOBUFS; 1505 } 1506 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1507 BUS_DMASYNC_PREREAD); 1508 1509 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1510 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1511 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1512 r->bge_flags = BGE_RXBDFLAG_END; 1513 r->bge_len = m_new->m_len; 1514 r->bge_idx = i; 1515 1516 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1517 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1518 i * sizeof (struct bge_rx_bd), 1519 sizeof (struct bge_rx_bd), 1520 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1521 1522 return 0; 1523 } 1524 1525 /* 1526 * Initialize a jumbo receive ring descriptor. This allocates 1527 * a jumbo buffer from the pool managed internally by the driver. 1528 */ 1529 static int 1530 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1531 { 1532 struct mbuf *m_new = NULL; 1533 struct bge_rx_bd *r; 1534 void *buf = NULL; 1535 1536 if (m == NULL) { 1537 1538 /* Allocate the mbuf. */ 1539 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1540 if (m_new == NULL) 1541 return ENOBUFS; 1542 1543 /* Allocate the jumbo buffer */ 1544 buf = bge_jalloc(sc); 1545 if (buf == NULL) { 1546 m_freem(m_new); 1547 aprint_error_dev(sc->bge_dev, 1548 "jumbo allocation failed -- packet dropped!\n"); 1549 return ENOBUFS; 1550 } 1551 1552 /* Attach the buffer to the mbuf. */ 1553 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1554 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1555 bge_jfree, sc); 1556 m_new->m_flags |= M_EXT_RW; 1557 } else { 1558 m_new = m; 1559 buf = m_new->m_data = m_new->m_ext.ext_buf; 1560 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1561 } 1562 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1563 m_adj(m_new, ETHER_ALIGN); 1564 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1565 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1566 BGE_JLEN, BUS_DMASYNC_PREREAD); 1567 /* Set up the descriptor. */ 1568 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1569 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1570 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1571 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1572 r->bge_len = m_new->m_len; 1573 r->bge_idx = i; 1574 1575 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1576 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1577 i * sizeof (struct bge_rx_bd), 1578 sizeof (struct bge_rx_bd), 1579 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1580 1581 return 0; 1582 } 1583 1584 /* 1585 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1586 * that's 1MB or memory, which is a lot. For now, we fill only the first 1587 * 256 ring entries and hope that our CPU is fast enough to keep up with 1588 * the NIC. 1589 */ 1590 static int 1591 bge_init_rx_ring_std(struct bge_softc *sc) 1592 { 1593 int i; 1594 1595 if (sc->bge_flags & BGEF_RXRING_VALID) 1596 return 0; 1597 1598 for (i = 0; i < BGE_SSLOTS; i++) { 1599 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1600 return ENOBUFS; 1601 } 1602 1603 sc->bge_std = i - 1; 1604 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1605 1606 sc->bge_flags |= BGEF_RXRING_VALID; 1607 1608 return 0; 1609 } 1610 1611 static void 1612 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1613 { 1614 int i; 1615 1616 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1617 return; 1618 1619 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1620 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1621 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1622 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1623 if (disable) { 1624 bus_dmamap_destroy(sc->bge_dmatag, 1625 sc->bge_cdata.bge_rx_std_map[i]); 1626 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1627 } 1628 } 1629 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1630 sizeof(struct bge_rx_bd)); 1631 } 1632 1633 sc->bge_flags &= ~BGEF_RXRING_VALID; 1634 } 1635 1636 static int 1637 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1638 { 1639 int i; 1640 volatile struct bge_rcb *rcb; 1641 1642 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1643 return 0; 1644 1645 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1646 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1647 return ENOBUFS; 1648 } 1649 1650 sc->bge_jumbo = i - 1; 1651 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1652 1653 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1654 rcb->bge_maxlen_flags = 0; 1655 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1656 1657 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1658 1659 return 0; 1660 } 1661 1662 static void 1663 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1664 { 1665 int i; 1666 1667 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1668 return; 1669 1670 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1671 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1672 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1673 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1674 } 1675 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1676 sizeof(struct bge_rx_bd)); 1677 } 1678 1679 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1680 } 1681 1682 static void 1683 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1684 { 1685 int i; 1686 struct txdmamap_pool_entry *dma; 1687 1688 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1689 return; 1690 1691 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1692 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1693 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1694 sc->bge_cdata.bge_tx_chain[i] = NULL; 1695 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1696 link); 1697 sc->txdma[i] = 0; 1698 } 1699 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1700 sizeof(struct bge_tx_bd)); 1701 } 1702 1703 if (disable) { 1704 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1705 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1706 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1707 if (sc->bge_dma64) { 1708 bus_dmamap_destroy(sc->bge_dmatag32, 1709 dma->dmamap32); 1710 } 1711 free(dma, M_DEVBUF); 1712 } 1713 SLIST_INIT(&sc->txdma_list); 1714 } 1715 1716 sc->bge_flags &= ~BGEF_TXRING_VALID; 1717 } 1718 1719 static int 1720 bge_init_tx_ring(struct bge_softc *sc) 1721 { 1722 struct ifnet * const ifp = &sc->ethercom.ec_if; 1723 int i; 1724 bus_dmamap_t dmamap, dmamap32; 1725 bus_size_t maxsegsz; 1726 struct txdmamap_pool_entry *dma; 1727 1728 if (sc->bge_flags & BGEF_TXRING_VALID) 1729 return 0; 1730 1731 sc->bge_txcnt = 0; 1732 sc->bge_tx_saved_considx = 0; 1733 1734 /* Initialize transmit producer index for host-memory send ring. */ 1735 sc->bge_tx_prodidx = 0; 1736 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1737 /* 5700 b2 errata */ 1738 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1739 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1740 1741 /* NIC-memory send ring not used; initialize to zero. */ 1742 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1743 /* 5700 b2 errata */ 1744 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1745 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1746 1747 /* Limit DMA segment size for some chips */ 1748 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1749 (ifp->if_mtu <= ETHERMTU)) 1750 maxsegsz = 2048; 1751 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1752 maxsegsz = 4096; 1753 else 1754 maxsegsz = ETHER_MAX_LEN_JUMBO; 1755 1756 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1757 goto alloc_done; 1758 1759 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1760 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1761 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1762 &dmamap)) 1763 return ENOBUFS; 1764 if (dmamap == NULL) 1765 panic("dmamap NULL in bge_init_tx_ring"); 1766 if (sc->bge_dma64) { 1767 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1768 BGE_NTXSEG, maxsegsz, 0, 1769 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1770 &dmamap32)) { 1771 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1772 return ENOBUFS; 1773 } 1774 if (dmamap32 == NULL) 1775 panic("dmamap32 NULL in bge_init_tx_ring"); 1776 } else 1777 dmamap32 = dmamap; 1778 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1779 if (dma == NULL) { 1780 aprint_error_dev(sc->bge_dev, 1781 "can't alloc txdmamap_pool_entry\n"); 1782 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1783 if (sc->bge_dma64) 1784 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1785 return ENOMEM; 1786 } 1787 dma->dmamap = dmamap; 1788 dma->dmamap32 = dmamap32; 1789 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1790 } 1791 alloc_done: 1792 sc->bge_flags |= BGEF_TXRING_VALID; 1793 1794 return 0; 1795 } 1796 1797 static void 1798 bge_setmulti(struct bge_softc *sc) 1799 { 1800 struct ethercom * const ec = &sc->ethercom; 1801 struct ifnet * const ifp = &ec->ec_if; 1802 struct ether_multi *enm; 1803 struct ether_multistep step; 1804 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1805 uint32_t h; 1806 int i; 1807 1808 if (ifp->if_flags & IFF_PROMISC) 1809 goto allmulti; 1810 1811 /* Now program new ones. */ 1812 ETHER_LOCK(ec); 1813 ETHER_FIRST_MULTI(step, ec, enm); 1814 while (enm != NULL) { 1815 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1816 /* 1817 * We must listen to a range of multicast addresses. 1818 * For now, just accept all multicasts, rather than 1819 * trying to set only those filter bits needed to match 1820 * the range. (At this time, the only use of address 1821 * ranges is for IP multicast routing, for which the 1822 * range is big enough to require all bits set.) 1823 */ 1824 ETHER_UNLOCK(ec); 1825 goto allmulti; 1826 } 1827 1828 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1829 1830 /* Just want the 7 least-significant bits. */ 1831 h &= 0x7f; 1832 1833 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1834 ETHER_NEXT_MULTI(step, enm); 1835 } 1836 ETHER_UNLOCK(ec); 1837 1838 ifp->if_flags &= ~IFF_ALLMULTI; 1839 goto setit; 1840 1841 allmulti: 1842 ifp->if_flags |= IFF_ALLMULTI; 1843 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1844 1845 setit: 1846 for (i = 0; i < 4; i++) 1847 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1848 } 1849 1850 static void 1851 bge_sig_pre_reset(struct bge_softc *sc, int type) 1852 { 1853 1854 /* 1855 * Some chips don't like this so only do this if ASF is enabled 1856 */ 1857 if (sc->bge_asf_mode) 1858 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1859 1860 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1861 switch (type) { 1862 case BGE_RESET_START: 1863 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1864 BGE_FW_DRV_STATE_START); 1865 break; 1866 case BGE_RESET_SHUTDOWN: 1867 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1868 BGE_FW_DRV_STATE_UNLOAD); 1869 break; 1870 case BGE_RESET_SUSPEND: 1871 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1872 BGE_FW_DRV_STATE_SUSPEND); 1873 break; 1874 } 1875 } 1876 1877 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1878 bge_ape_driver_state_change(sc, type); 1879 } 1880 1881 static void 1882 bge_sig_post_reset(struct bge_softc *sc, int type) 1883 { 1884 1885 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1886 switch (type) { 1887 case BGE_RESET_START: 1888 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1889 BGE_FW_DRV_STATE_START_DONE); 1890 /* START DONE */ 1891 break; 1892 case BGE_RESET_SHUTDOWN: 1893 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1894 BGE_FW_DRV_STATE_UNLOAD_DONE); 1895 break; 1896 } 1897 } 1898 1899 if (type == BGE_RESET_SHUTDOWN) 1900 bge_ape_driver_state_change(sc, type); 1901 } 1902 1903 static void 1904 bge_sig_legacy(struct bge_softc *sc, int type) 1905 { 1906 1907 if (sc->bge_asf_mode) { 1908 switch (type) { 1909 case BGE_RESET_START: 1910 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1911 BGE_FW_DRV_STATE_START); 1912 break; 1913 case BGE_RESET_SHUTDOWN: 1914 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1915 BGE_FW_DRV_STATE_UNLOAD); 1916 break; 1917 } 1918 } 1919 } 1920 1921 static void 1922 bge_wait_for_event_ack(struct bge_softc *sc) 1923 { 1924 int i; 1925 1926 /* wait up to 2500usec */ 1927 for (i = 0; i < 250; i++) { 1928 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1929 BGE_RX_CPU_DRV_EVENT)) 1930 break; 1931 DELAY(10); 1932 } 1933 } 1934 1935 static void 1936 bge_stop_fw(struct bge_softc *sc) 1937 { 1938 1939 if (sc->bge_asf_mode) { 1940 bge_wait_for_event_ack(sc); 1941 1942 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1943 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1944 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1945 1946 bge_wait_for_event_ack(sc); 1947 } 1948 } 1949 1950 static int 1951 bge_poll_fw(struct bge_softc *sc) 1952 { 1953 uint32_t val; 1954 int i; 1955 1956 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1957 for (i = 0; i < BGE_TIMEOUT; i++) { 1958 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1959 if (val & BGE_VCPU_STATUS_INIT_DONE) 1960 break; 1961 DELAY(100); 1962 } 1963 if (i >= BGE_TIMEOUT) { 1964 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1965 return -1; 1966 } 1967 } else { 1968 /* 1969 * Poll the value location we just wrote until 1970 * we see the 1's complement of the magic number. 1971 * This indicates that the firmware initialization 1972 * is complete. 1973 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1974 */ 1975 for (i = 0; i < BGE_TIMEOUT; i++) { 1976 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1977 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1978 break; 1979 DELAY(10); 1980 } 1981 1982 if ((i >= BGE_TIMEOUT) 1983 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1984 aprint_error_dev(sc->bge_dev, 1985 "firmware handshake timed out, val = %x\n", val); 1986 return -1; 1987 } 1988 } 1989 1990 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1991 /* tg3 says we have to wait extra time */ 1992 delay(10 * 1000); 1993 } 1994 1995 return 0; 1996 } 1997 1998 int 1999 bge_phy_addr(struct bge_softc *sc) 2000 { 2001 struct pci_attach_args *pa = &(sc->bge_pa); 2002 int phy_addr = 1; 2003 2004 /* 2005 * PHY address mapping for various devices. 2006 * 2007 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2008 * ---------+-------+-------+-------+-------+ 2009 * BCM57XX | 1 | X | X | X | 2010 * BCM5704 | 1 | X | 1 | X | 2011 * BCM5717 | 1 | 8 | 2 | 9 | 2012 * BCM5719 | 1 | 8 | 2 | 9 | 2013 * BCM5720 | 1 | 8 | 2 | 9 | 2014 * 2015 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2016 * ---------+-------+-------+-------+-------+ 2017 * BCM57XX | X | X | X | X | 2018 * BCM5704 | X | X | X | X | 2019 * BCM5717 | X | X | X | X | 2020 * BCM5719 | 3 | 10 | 4 | 11 | 2021 * BCM5720 | X | X | X | X | 2022 * 2023 * Other addresses may respond but they are not 2024 * IEEE compliant PHYs and should be ignored. 2025 */ 2026 switch (BGE_ASICREV(sc->bge_chipid)) { 2027 case BGE_ASICREV_BCM5717: 2028 case BGE_ASICREV_BCM5719: 2029 case BGE_ASICREV_BCM5720: 2030 phy_addr = pa->pa_function; 2031 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2032 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2033 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2034 } else { 2035 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2036 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2037 } 2038 } 2039 2040 return phy_addr; 2041 } 2042 2043 /* 2044 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2045 * self-test results. 2046 */ 2047 static int 2048 bge_chipinit(struct bge_softc *sc) 2049 { 2050 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2051 int i; 2052 2053 /* Set endianness before we access any non-PCI registers. */ 2054 misc_ctl = BGE_INIT; 2055 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2056 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2057 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2058 misc_ctl); 2059 2060 /* 2061 * Clear the MAC statistics block in the NIC's 2062 * internal memory. 2063 */ 2064 for (i = BGE_STATS_BLOCK; 2065 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2066 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2067 2068 for (i = BGE_STATUS_BLOCK; 2069 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2070 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2071 2072 /* 5717 workaround from tg3 */ 2073 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2074 /* Save */ 2075 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2076 2077 /* Temporary modify MODE_CTL to control TLP */ 2078 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2079 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2080 2081 /* Control TLP */ 2082 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2083 BGE_TLP_PHYCTL1); 2084 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2085 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2086 2087 /* Restore */ 2088 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2089 } 2090 2091 if (BGE_IS_57765_FAMILY(sc)) { 2092 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2093 /* Save */ 2094 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2095 2096 /* Temporary modify MODE_CTL to control TLP */ 2097 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2098 CSR_WRITE_4(sc, BGE_MODE_CTL, 2099 reg | BGE_MODECTL_PCIE_TLPADDR1); 2100 2101 /* Control TLP */ 2102 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2103 BGE_TLP_PHYCTL5); 2104 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2105 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2106 2107 /* Restore */ 2108 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2109 } 2110 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2111 /* 2112 * For the 57766 and non Ax versions of 57765, bootcode 2113 * needs to setup the PCIE Fast Training Sequence (FTS) 2114 * value to prevent transmit hangs. 2115 */ 2116 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2117 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2118 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2119 2120 /* Save */ 2121 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2122 2123 /* Temporary modify MODE_CTL to control TLP */ 2124 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2125 CSR_WRITE_4(sc, BGE_MODE_CTL, 2126 reg | BGE_MODECTL_PCIE_TLPADDR0); 2127 2128 /* Control TLP */ 2129 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2130 BGE_TLP_FTSMAX); 2131 reg &= ~BGE_TLP_FTSMAX_MSK; 2132 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2133 reg | BGE_TLP_FTSMAX_VAL); 2134 2135 /* Restore */ 2136 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2137 } 2138 2139 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2140 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2141 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2142 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2143 } 2144 2145 /* Set up the PCI DMA control register. */ 2146 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2147 if (sc->bge_flags & BGEF_PCIE) { 2148 /* Read watermark not used, 128 bytes for write. */ 2149 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2150 device_xname(sc->bge_dev))); 2151 if (sc->bge_mps >= 256) 2152 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2153 else 2154 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2155 } else if (sc->bge_flags & BGEF_PCIX) { 2156 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2157 device_xname(sc->bge_dev))); 2158 /* PCI-X bus */ 2159 if (BGE_IS_5714_FAMILY(sc)) { 2160 /* 256 bytes for read and write. */ 2161 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2162 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2163 2164 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2165 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2166 else 2167 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2168 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2169 /* 2170 * In the BCM5703, the DMA read watermark should 2171 * be set to less than or equal to the maximum 2172 * memory read byte count of the PCI-X command 2173 * register. 2174 */ 2175 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2176 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2177 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2178 /* 1536 bytes for read, 384 bytes for write. */ 2179 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2180 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2181 } else { 2182 /* 384 bytes for read and write. */ 2183 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2184 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2185 (0x0F); 2186 } 2187 2188 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2189 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2190 uint32_t tmp; 2191 2192 /* Set ONEDMA_ATONCE for hardware workaround. */ 2193 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2194 if (tmp == 6 || tmp == 7) 2195 dma_rw_ctl |= 2196 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2197 2198 /* Set PCI-X DMA write workaround. */ 2199 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2200 } 2201 } else { 2202 /* Conventional PCI bus: 256 bytes for read and write. */ 2203 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2204 device_xname(sc->bge_dev))); 2205 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2206 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2207 2208 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2209 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2210 dma_rw_ctl |= 0x0F; 2211 } 2212 2213 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2214 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2215 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2216 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2217 2218 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2219 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2220 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2221 2222 if (BGE_IS_57765_PLUS(sc)) { 2223 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2224 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2225 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2226 2227 /* 2228 * Enable HW workaround for controllers that misinterpret 2229 * a status tag update and leave interrupts permanently 2230 * disabled. 2231 */ 2232 if (!BGE_IS_57765_FAMILY(sc) && 2233 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2234 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2235 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2236 } 2237 2238 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2239 dma_rw_ctl); 2240 2241 /* 2242 * Set up general mode register. 2243 */ 2244 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2245 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2246 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2247 /* Retain Host-2-BMC settings written by APE firmware. */ 2248 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2249 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2250 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2251 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2252 } 2253 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2254 BGE_MODECTL_TX_NO_PHDR_CSUM; 2255 2256 /* 2257 * BCM5701 B5 have a bug causing data corruption when using 2258 * 64-bit DMA reads, which can be terminated early and then 2259 * completed later as 32-bit accesses, in combination with 2260 * certain bridges. 2261 */ 2262 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2263 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2264 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2265 2266 /* 2267 * Tell the firmware the driver is running 2268 */ 2269 if (sc->bge_asf_mode & ASF_STACKUP) 2270 mode_ctl |= BGE_MODECTL_STACKUP; 2271 2272 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2273 2274 /* 2275 * Disable memory write invalidate. Apparently it is not supported 2276 * properly by these devices. 2277 */ 2278 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2279 PCI_COMMAND_INVALIDATE_ENABLE); 2280 2281 #ifdef __brokenalpha__ 2282 /* 2283 * Must insure that we do not cross an 8K (bytes) boundary 2284 * for DMA reads. Our highest limit is 1K bytes. This is a 2285 * restriction on some ALPHA platforms with early revision 2286 * 21174 PCI chipsets, such as the AlphaPC 164lx 2287 */ 2288 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2289 #endif 2290 2291 /* Set the timer prescaler (always 66MHz) */ 2292 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2293 2294 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2295 DELAY(40); /* XXX */ 2296 2297 /* Put PHY into ready state */ 2298 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2299 DELAY(40); 2300 } 2301 2302 return 0; 2303 } 2304 2305 static int 2306 bge_blockinit(struct bge_softc *sc) 2307 { 2308 volatile struct bge_rcb *rcb; 2309 bus_size_t rcb_addr; 2310 struct ifnet * const ifp = &sc->ethercom.ec_if; 2311 bge_hostaddr taddr; 2312 uint32_t dmactl, rdmareg, mimode, val; 2313 int i, limit; 2314 2315 /* 2316 * Initialize the memory window pointer register so that 2317 * we can access the first 32K of internal NIC RAM. This will 2318 * allow us to set up the TX send ring RCBs and the RX return 2319 * ring RCBs, plus other things which live in NIC memory. 2320 */ 2321 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2322 2323 if (!BGE_IS_5705_PLUS(sc)) { 2324 /* 57XX step 33 */ 2325 /* Configure mbuf memory pool */ 2326 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2327 2328 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2329 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2330 else 2331 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2332 2333 /* 57XX step 34 */ 2334 /* Configure DMA resource pool */ 2335 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2336 BGE_DMA_DESCRIPTORS); 2337 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2338 } 2339 2340 /* 5718 step 11, 57XX step 35 */ 2341 /* 2342 * Configure mbuf pool watermarks. New broadcom docs strongly 2343 * recommend these. 2344 */ 2345 if (BGE_IS_5717_PLUS(sc)) { 2346 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2347 if (ifp->if_mtu > ETHERMTU) { 2348 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2350 } else { 2351 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2353 } 2354 } else if (BGE_IS_5705_PLUS(sc)) { 2355 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2356 2357 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2358 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2359 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2360 } else { 2361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2362 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2363 } 2364 } else { 2365 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2366 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2367 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2368 } 2369 2370 /* 57XX step 36 */ 2371 /* Configure DMA resource watermarks */ 2372 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2373 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2374 2375 /* 5718 step 13, 57XX step 38 */ 2376 /* Enable buffer manager */ 2377 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2378 /* 2379 * Change the arbitration algorithm of TXMBUF read request to 2380 * round-robin instead of priority based for BCM5719. When 2381 * TXFIFO is almost empty, RDMA will hold its request until 2382 * TXFIFO is not almost empty. 2383 */ 2384 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2385 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2386 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2387 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2388 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2389 val |= BGE_BMANMODE_LOMBUF_ATTN; 2390 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2391 2392 /* 57XX step 39 */ 2393 /* Poll for buffer manager start indication */ 2394 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2395 DELAY(10); 2396 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2397 break; 2398 } 2399 2400 if (i == BGE_TIMEOUT * 2) { 2401 aprint_error_dev(sc->bge_dev, 2402 "buffer manager failed to start\n"); 2403 return ENXIO; 2404 } 2405 2406 /* 57XX step 40 */ 2407 /* Enable flow-through queues */ 2408 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2409 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2410 2411 /* Wait until queue initialization is complete */ 2412 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2413 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2414 break; 2415 DELAY(10); 2416 } 2417 2418 if (i == BGE_TIMEOUT * 2) { 2419 aprint_error_dev(sc->bge_dev, 2420 "flow-through queue init failed\n"); 2421 return ENXIO; 2422 } 2423 2424 /* 2425 * Summary of rings supported by the controller: 2426 * 2427 * Standard Receive Producer Ring 2428 * - This ring is used to feed receive buffers for "standard" 2429 * sized frames (typically 1536 bytes) to the controller. 2430 * 2431 * Jumbo Receive Producer Ring 2432 * - This ring is used to feed receive buffers for jumbo sized 2433 * frames (i.e. anything bigger than the "standard" frames) 2434 * to the controller. 2435 * 2436 * Mini Receive Producer Ring 2437 * - This ring is used to feed receive buffers for "mini" 2438 * sized frames to the controller. 2439 * - This feature required external memory for the controller 2440 * but was never used in a production system. Should always 2441 * be disabled. 2442 * 2443 * Receive Return Ring 2444 * - After the controller has placed an incoming frame into a 2445 * receive buffer that buffer is moved into a receive return 2446 * ring. The driver is then responsible to passing the 2447 * buffer up to the stack. Many versions of the controller 2448 * support multiple RR rings. 2449 * 2450 * Send Ring 2451 * - This ring is used for outgoing frames. Many versions of 2452 * the controller support multiple send rings. 2453 */ 2454 2455 /* 5718 step 15, 57XX step 41 */ 2456 /* Initialize the standard RX ring control block */ 2457 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2458 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2459 /* 5718 step 16 */ 2460 if (BGE_IS_57765_PLUS(sc)) { 2461 /* 2462 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2463 * Bits 15-2 : Maximum RX frame size 2464 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2465 * Bit 0 : Reserved 2466 */ 2467 rcb->bge_maxlen_flags = 2468 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2469 } else if (BGE_IS_5705_PLUS(sc)) { 2470 /* 2471 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2472 * Bits 15-2 : Reserved (should be 0) 2473 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2474 * Bit 0 : Reserved 2475 */ 2476 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2477 } else { 2478 /* 2479 * Ring size is always XXX entries 2480 * Bits 31-16: Maximum RX frame size 2481 * Bits 15-2 : Reserved (should be 0) 2482 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2483 * Bit 0 : Reserved 2484 */ 2485 rcb->bge_maxlen_flags = 2486 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2487 } 2488 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2489 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2491 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2492 else 2493 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2494 /* Write the standard receive producer ring control block. */ 2495 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2496 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2497 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2498 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2499 2500 /* Reset the standard receive producer ring producer index. */ 2501 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2502 2503 /* 57XX step 42 */ 2504 /* 2505 * Initialize the jumbo RX ring control block 2506 * We set the 'ring disabled' bit in the flags 2507 * field until we're actually ready to start 2508 * using this ring (i.e. once we set the MTU 2509 * high enough to require it). 2510 */ 2511 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2512 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2513 BGE_HOSTADDR(rcb->bge_hostaddr, 2514 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2515 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2516 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2517 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2518 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2519 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2520 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2521 else 2522 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2523 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2524 rcb->bge_hostaddr.bge_addr_hi); 2525 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2526 rcb->bge_hostaddr.bge_addr_lo); 2527 /* Program the jumbo receive producer ring RCB parameters. */ 2528 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2529 rcb->bge_maxlen_flags); 2530 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2531 /* Reset the jumbo receive producer ring producer index. */ 2532 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2533 } 2534 2535 /* 57XX step 43 */ 2536 /* Disable the mini receive producer ring RCB. */ 2537 if (BGE_IS_5700_FAMILY(sc)) { 2538 /* Set up dummy disabled mini ring RCB */ 2539 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2540 rcb->bge_maxlen_flags = 2541 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2542 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2543 rcb->bge_maxlen_flags); 2544 /* Reset the mini receive producer ring producer index. */ 2545 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2546 2547 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2548 offsetof(struct bge_ring_data, bge_info), 2549 sizeof (struct bge_gib), 2550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2551 } 2552 2553 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2554 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2555 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2556 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2557 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2558 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2559 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2560 } 2561 /* 5718 step 14, 57XX step 44 */ 2562 /* 2563 * The BD ring replenish thresholds control how often the 2564 * hardware fetches new BD's from the producer rings in host 2565 * memory. Setting the value too low on a busy system can 2566 * starve the hardware and recue the throughpout. 2567 * 2568 * Set the BD ring replenish thresholds. The recommended 2569 * values are 1/8th the number of descriptors allocated to 2570 * each ring, but since we try to avoid filling the entire 2571 * ring we set these to the minimal value of 8. This needs to 2572 * be done on several of the supported chip revisions anyway, 2573 * to work around HW bugs. 2574 */ 2575 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2576 if (BGE_IS_JUMBO_CAPABLE(sc)) 2577 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2578 2579 /* 5718 step 18 */ 2580 if (BGE_IS_5717_PLUS(sc)) { 2581 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2582 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2583 } 2584 2585 /* 57XX step 45 */ 2586 /* 2587 * Disable all send rings by setting the 'ring disabled' bit 2588 * in the flags field of all the TX send ring control blocks, 2589 * located in NIC memory. 2590 */ 2591 if (BGE_IS_5700_FAMILY(sc)) { 2592 /* 5700 to 5704 had 16 send rings. */ 2593 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2594 } else if (BGE_IS_5717_PLUS(sc)) { 2595 limit = BGE_TX_RINGS_5717_MAX; 2596 } else if (BGE_IS_57765_FAMILY(sc) || 2597 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2598 limit = BGE_TX_RINGS_57765_MAX; 2599 } else 2600 limit = 1; 2601 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2602 for (i = 0; i < limit; i++) { 2603 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2604 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2605 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2606 rcb_addr += sizeof(struct bge_rcb); 2607 } 2608 2609 /* 57XX step 46 and 47 */ 2610 /* Configure send ring RCB 0 (we use only the first ring) */ 2611 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2612 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2613 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2614 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2615 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2616 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2617 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2618 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2619 else 2620 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2621 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2622 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2623 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2624 2625 /* 57XX step 48 */ 2626 /* 2627 * Disable all receive return rings by setting the 2628 * 'ring diabled' bit in the flags field of all the receive 2629 * return ring control blocks, located in NIC memory. 2630 */ 2631 if (BGE_IS_5717_PLUS(sc)) { 2632 /* Should be 17, use 16 until we get an SRAM map. */ 2633 limit = 16; 2634 } else if (BGE_IS_5700_FAMILY(sc)) 2635 limit = BGE_RX_RINGS_MAX; 2636 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2637 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2638 BGE_IS_57765_FAMILY(sc)) 2639 limit = 4; 2640 else 2641 limit = 1; 2642 /* Disable all receive return rings */ 2643 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2644 for (i = 0; i < limit; i++) { 2645 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2646 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2647 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2648 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2649 BGE_RCB_FLAG_RING_DISABLED)); 2650 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2651 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2652 (i * (sizeof(uint64_t))), 0); 2653 rcb_addr += sizeof(struct bge_rcb); 2654 } 2655 2656 /* 57XX step 49 */ 2657 /* 2658 * Set up receive return ring 0. Note that the NIC address 2659 * for RX return rings is 0x0. The return rings live entirely 2660 * within the host, so the nicaddr field in the RCB isn't used. 2661 */ 2662 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2663 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2664 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2665 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2666 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2667 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2668 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2669 2670 /* 5718 step 24, 57XX step 53 */ 2671 /* Set random backoff seed for TX */ 2672 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2673 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2674 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2675 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2676 BGE_TX_BACKOFF_SEED_MASK); 2677 2678 /* 5718 step 26, 57XX step 55 */ 2679 /* Set inter-packet gap */ 2680 val = 0x2620; 2681 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2682 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2683 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2684 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2685 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2686 2687 /* 5718 step 27, 57XX step 56 */ 2688 /* 2689 * Specify which ring to use for packets that don't match 2690 * any RX rules. 2691 */ 2692 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2693 2694 /* 5718 step 28, 57XX step 57 */ 2695 /* 2696 * Configure number of RX lists. One interrupt distribution 2697 * list, sixteen active lists, one bad frames class. 2698 */ 2699 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2700 2701 /* 5718 step 29, 57XX step 58 */ 2702 /* Inialize RX list placement stats mask. */ 2703 if (BGE_IS_575X_PLUS(sc)) { 2704 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2705 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2706 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2707 } else 2708 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2709 2710 /* 5718 step 30, 57XX step 59 */ 2711 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2712 2713 /* 5718 step 33, 57XX step 62 */ 2714 /* Disable host coalescing until we get it set up */ 2715 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2716 2717 /* 5718 step 34, 57XX step 63 */ 2718 /* Poll to make sure it's shut down. */ 2719 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2720 DELAY(10); 2721 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2722 break; 2723 } 2724 2725 if (i == BGE_TIMEOUT * 2) { 2726 aprint_error_dev(sc->bge_dev, 2727 "host coalescing engine failed to idle\n"); 2728 return ENXIO; 2729 } 2730 2731 /* 5718 step 35, 36, 37 */ 2732 /* Set up host coalescing defaults */ 2733 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2734 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2735 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2736 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2737 if (!(BGE_IS_5705_PLUS(sc))) { 2738 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2739 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2740 } 2741 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2742 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2743 2744 /* Set up address of statistics block */ 2745 if (BGE_IS_5700_FAMILY(sc)) { 2746 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2747 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2748 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2749 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2750 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2751 } 2752 2753 /* 5718 step 38 */ 2754 /* Set up address of status block */ 2755 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2756 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2757 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2758 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2759 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2760 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2761 2762 /* Set up status block size. */ 2763 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2764 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2765 val = BGE_STATBLKSZ_FULL; 2766 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2767 } else { 2768 val = BGE_STATBLKSZ_32BYTE; 2769 bzero(&sc->bge_rdata->bge_status_block, 32); 2770 } 2771 2772 /* 5718 step 39, 57XX step 73 */ 2773 /* Turn on host coalescing state machine */ 2774 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2775 2776 /* 5718 step 40, 57XX step 74 */ 2777 /* Turn on RX BD completion state machine and enable attentions */ 2778 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2779 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2780 2781 /* 5718 step 41, 57XX step 75 */ 2782 /* Turn on RX list placement state machine */ 2783 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2784 2785 /* 57XX step 76 */ 2786 /* Turn on RX list selector state machine. */ 2787 if (!(BGE_IS_5705_PLUS(sc))) 2788 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2789 2790 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2791 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2792 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2793 BGE_MACMODE_FRMHDR_DMA_ENB; 2794 2795 if (sc->bge_flags & BGEF_FIBER_TBI) 2796 val |= BGE_PORTMODE_TBI; 2797 else if (sc->bge_flags & BGEF_FIBER_MII) 2798 val |= BGE_PORTMODE_GMII; 2799 else 2800 val |= BGE_PORTMODE_MII; 2801 2802 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2803 /* Allow APE to send/receive frames. */ 2804 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2805 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2806 2807 /* Turn on DMA, clear stats */ 2808 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2809 /* 5718 step 44 */ 2810 DELAY(40); 2811 2812 /* 5718 step 45, 57XX step 79 */ 2813 /* Set misc. local control, enable interrupts on attentions */ 2814 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2815 if (BGE_IS_5717_PLUS(sc)) { 2816 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2817 /* 5718 step 46 */ 2818 DELAY(100); 2819 } 2820 2821 /* 57XX step 81 */ 2822 /* Turn on DMA completion state machine */ 2823 if (!(BGE_IS_5705_PLUS(sc))) 2824 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2825 2826 /* 5718 step 47, 57XX step 82 */ 2827 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2828 2829 /* 5718 step 48 */ 2830 /* Enable host coalescing bug fix. */ 2831 if (BGE_IS_5755_PLUS(sc)) 2832 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2833 2834 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2835 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2836 2837 /* Turn on write DMA state machine */ 2838 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2839 /* 5718 step 49 */ 2840 DELAY(40); 2841 2842 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2843 2844 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2845 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2846 2847 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2848 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2849 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2850 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2851 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2852 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2853 2854 if (sc->bge_flags & BGEF_PCIE) 2855 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2856 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2857 if (ifp->if_mtu <= ETHERMTU) 2858 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2859 } 2860 if (sc->bge_flags & BGEF_TSO) { 2861 val |= BGE_RDMAMODE_TSO4_ENABLE; 2862 if (BGE_IS_5717_PLUS(sc)) 2863 val |= BGE_RDMAMODE_TSO6_ENABLE; 2864 } 2865 2866 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2867 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2868 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2869 BGE_RDMAMODE_H2BNC_VLAN_DET; 2870 /* 2871 * Allow multiple outstanding read requests from 2872 * non-LSO read DMA engine. 2873 */ 2874 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2875 } 2876 2877 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2878 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2879 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2880 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2881 BGE_IS_57765_PLUS(sc)) { 2882 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2883 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2884 else 2885 rdmareg = BGE_RDMA_RSRVCTRL; 2886 dmactl = CSR_READ_4(sc, rdmareg); 2887 /* 2888 * Adjust tx margin to prevent TX data corruption and 2889 * fix internal FIFO overflow. 2890 */ 2891 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2892 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2893 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2894 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2895 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2896 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2897 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2898 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2899 } 2900 /* 2901 * Enable fix for read DMA FIFO overruns. 2902 * The fix is to limit the number of RX BDs 2903 * the hardware would fetch at a time. 2904 */ 2905 CSR_WRITE_4(sc, rdmareg, dmactl | 2906 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2907 } 2908 2909 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2910 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2911 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2912 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2913 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2914 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2915 /* 2916 * Allow 4KB burst length reads for non-LSO frames. 2917 * Enable 512B burst length reads for buffer descriptors. 2918 */ 2919 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2920 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2921 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2922 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2923 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2924 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2925 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2926 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2927 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2928 } 2929 /* Turn on read DMA state machine */ 2930 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2931 /* 5718 step 52 */ 2932 delay(40); 2933 2934 if (sc->bge_flags & BGEF_RDMA_BUG) { 2935 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2936 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2937 if ((val & 0xFFFF) > BGE_FRAMELEN) 2938 break; 2939 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2940 break; 2941 } 2942 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2943 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2944 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2945 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2946 else 2947 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2948 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2949 } 2950 } 2951 2952 /* 5718 step 56, 57XX step 84 */ 2953 /* Turn on RX data completion state machine */ 2954 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2955 2956 /* Turn on RX data and RX BD initiator state machine */ 2957 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2958 2959 /* 57XX step 85 */ 2960 /* Turn on Mbuf cluster free state machine */ 2961 if (!BGE_IS_5705_PLUS(sc)) 2962 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2963 2964 /* 5718 step 57, 57XX step 86 */ 2965 /* Turn on send data completion state machine */ 2966 val = BGE_SDCMODE_ENABLE; 2967 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2968 val |= BGE_SDCMODE_CDELAY; 2969 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2970 2971 /* 5718 step 58 */ 2972 /* Turn on send BD completion state machine */ 2973 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2974 2975 /* 57XX step 88 */ 2976 /* Turn on RX BD initiator state machine */ 2977 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2978 2979 /* 5718 step 60, 57XX step 90 */ 2980 /* Turn on send data initiator state machine */ 2981 if (sc->bge_flags & BGEF_TSO) { 2982 /* XXX: magic value from Linux driver */ 2983 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2984 BGE_SDIMODE_HW_LSO_PRE_DMA); 2985 } else 2986 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2987 2988 /* 5718 step 61, 57XX step 91 */ 2989 /* Turn on send BD initiator state machine */ 2990 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2991 2992 /* 5718 step 62, 57XX step 92 */ 2993 /* Turn on send BD selector state machine */ 2994 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2995 2996 /* 5718 step 31, 57XX step 60 */ 2997 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2998 /* 5718 step 32, 57XX step 61 */ 2999 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3000 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3001 3002 /* ack/clear link change events */ 3003 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3004 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3005 BGE_MACSTAT_LINK_CHANGED); 3006 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3007 3008 /* 3009 * Enable attention when the link has changed state for 3010 * devices that use auto polling. 3011 */ 3012 if (sc->bge_flags & BGEF_FIBER_TBI) { 3013 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3014 } else { 3015 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3016 mimode = BGE_MIMODE_500KHZ_CONST; 3017 else 3018 mimode = BGE_MIMODE_BASE; 3019 /* 5718 step 68. 5718 step 69 (optionally). */ 3020 if (BGE_IS_5700_FAMILY(sc) || 3021 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3022 mimode |= BGE_MIMODE_AUTOPOLL; 3023 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3024 } 3025 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3026 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3027 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3028 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3029 BGE_EVTENB_MI_INTERRUPT); 3030 } 3031 3032 /* 3033 * Clear any pending link state attention. 3034 * Otherwise some link state change events may be lost until attention 3035 * is cleared by bge_intr() -> bge_link_upd() sequence. 3036 * It's not necessary on newer BCM chips - perhaps enabling link 3037 * state change attentions implies clearing pending attention. 3038 */ 3039 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3040 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3041 BGE_MACSTAT_LINK_CHANGED); 3042 3043 /* Enable link state change attentions. */ 3044 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3045 3046 return 0; 3047 } 3048 3049 static const struct bge_revision * 3050 bge_lookup_rev(uint32_t chipid) 3051 { 3052 const struct bge_revision *br; 3053 3054 for (br = bge_revisions; br->br_name != NULL; br++) { 3055 if (br->br_chipid == chipid) 3056 return br; 3057 } 3058 3059 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3060 if (br->br_chipid == BGE_ASICREV(chipid)) 3061 return br; 3062 } 3063 3064 return NULL; 3065 } 3066 3067 static const struct bge_product * 3068 bge_lookup(const struct pci_attach_args *pa) 3069 { 3070 const struct bge_product *bp; 3071 3072 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3073 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3074 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3075 return bp; 3076 } 3077 3078 return NULL; 3079 } 3080 3081 static uint32_t 3082 bge_chipid(const struct pci_attach_args *pa) 3083 { 3084 uint32_t id; 3085 3086 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3087 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3088 3089 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3090 switch (PCI_PRODUCT(pa->pa_id)) { 3091 case PCI_PRODUCT_BROADCOM_BCM5717: 3092 case PCI_PRODUCT_BROADCOM_BCM5718: 3093 case PCI_PRODUCT_BROADCOM_BCM5719: 3094 case PCI_PRODUCT_BROADCOM_BCM5720: 3095 case PCI_PRODUCT_BROADCOM_BCM5725: 3096 case PCI_PRODUCT_BROADCOM_BCM5727: 3097 case PCI_PRODUCT_BROADCOM_BCM5762: 3098 case PCI_PRODUCT_BROADCOM_BCM57764: 3099 case PCI_PRODUCT_BROADCOM_BCM57767: 3100 case PCI_PRODUCT_BROADCOM_BCM57787: 3101 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3102 BGE_PCI_GEN2_PRODID_ASICREV); 3103 break; 3104 case PCI_PRODUCT_BROADCOM_BCM57761: 3105 case PCI_PRODUCT_BROADCOM_BCM57762: 3106 case PCI_PRODUCT_BROADCOM_BCM57765: 3107 case PCI_PRODUCT_BROADCOM_BCM57766: 3108 case PCI_PRODUCT_BROADCOM_BCM57781: 3109 case PCI_PRODUCT_BROADCOM_BCM57782: 3110 case PCI_PRODUCT_BROADCOM_BCM57785: 3111 case PCI_PRODUCT_BROADCOM_BCM57786: 3112 case PCI_PRODUCT_BROADCOM_BCM57791: 3113 case PCI_PRODUCT_BROADCOM_BCM57795: 3114 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3115 BGE_PCI_GEN15_PRODID_ASICREV); 3116 break; 3117 default: 3118 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3119 BGE_PCI_PRODID_ASICREV); 3120 break; 3121 } 3122 } 3123 3124 return id; 3125 } 3126 3127 /* 3128 * Return true if MSI can be used with this device. 3129 */ 3130 static int 3131 bge_can_use_msi(struct bge_softc *sc) 3132 { 3133 int can_use_msi = 0; 3134 3135 switch (BGE_ASICREV(sc->bge_chipid)) { 3136 case BGE_ASICREV_BCM5714_A0: 3137 case BGE_ASICREV_BCM5714: 3138 /* 3139 * Apparently, MSI doesn't work when these chips are 3140 * configured in single-port mode. 3141 */ 3142 break; 3143 case BGE_ASICREV_BCM5750: 3144 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3145 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3146 can_use_msi = 1; 3147 break; 3148 default: 3149 if (BGE_IS_575X_PLUS(sc)) 3150 can_use_msi = 1; 3151 } 3152 return (can_use_msi); 3153 } 3154 3155 /* 3156 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3157 * against our list and return its name if we find a match. Note 3158 * that since the Broadcom controller contains VPD support, we 3159 * can get the device name string from the controller itself instead 3160 * of the compiled-in string. This is a little slow, but it guarantees 3161 * we'll always announce the right product name. 3162 */ 3163 static int 3164 bge_probe(device_t parent, cfdata_t match, void *aux) 3165 { 3166 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3167 3168 if (bge_lookup(pa) != NULL) 3169 return 1; 3170 3171 return 0; 3172 } 3173 3174 static void 3175 bge_attach(device_t parent, device_t self, void *aux) 3176 { 3177 struct bge_softc * const sc = device_private(self); 3178 struct pci_attach_args * const pa = aux; 3179 prop_dictionary_t dict; 3180 const struct bge_product *bp; 3181 const struct bge_revision *br; 3182 pci_chipset_tag_t pc; 3183 const char *intrstr = NULL; 3184 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3185 uint32_t command; 3186 struct ifnet *ifp; 3187 struct mii_data * const mii = &sc->bge_mii; 3188 uint32_t misccfg, mimode, macmode; 3189 void * kva; 3190 u_char eaddr[ETHER_ADDR_LEN]; 3191 pcireg_t memtype, subid, reg; 3192 bus_addr_t memaddr; 3193 uint32_t pm_ctl; 3194 bool no_seeprom; 3195 int capmask, trys; 3196 int mii_flags; 3197 int map_flags; 3198 char intrbuf[PCI_INTRSTR_LEN]; 3199 3200 bp = bge_lookup(pa); 3201 KASSERT(bp != NULL); 3202 3203 sc->sc_pc = pa->pa_pc; 3204 sc->sc_pcitag = pa->pa_tag; 3205 sc->bge_dev = self; 3206 3207 sc->bge_pa = *pa; 3208 pc = sc->sc_pc; 3209 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3210 3211 aprint_naive(": Ethernet controller\n"); 3212 aprint_normal(": %s Ethernet\n", bp->bp_name); 3213 3214 /* 3215 * Map control/status registers. 3216 */ 3217 DPRINTFN(5, ("Map control/status regs\n")); 3218 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3219 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3220 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3221 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3222 3223 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3224 aprint_error_dev(sc->bge_dev, 3225 "failed to enable memory mapping!\n"); 3226 return; 3227 } 3228 3229 DPRINTFN(5, ("pci_mem_find\n")); 3230 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3231 switch (memtype) { 3232 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3233 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3234 #if 0 3235 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3236 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3237 &memaddr, &sc->bge_bsize) == 0) 3238 break; 3239 #else 3240 /* 3241 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3242 * system get NMI on boot (PR#48451). This problem might not be 3243 * the driver's bug but our PCI common part's bug. Until we 3244 * find a real reason, we ignore the prefetchable bit. 3245 */ 3246 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3247 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3248 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3249 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3250 map_flags, &sc->bge_bhandle) == 0) { 3251 sc->bge_btag = pa->pa_memt; 3252 break; 3253 } 3254 } 3255 #endif 3256 /* FALLTHROUGH */ 3257 default: 3258 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3259 return; 3260 } 3261 3262 /* Save various chip information. */ 3263 sc->bge_chipid = bge_chipid(pa); 3264 sc->bge_phy_addr = bge_phy_addr(sc); 3265 3266 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3267 &sc->bge_pciecap, NULL) != 0) { 3268 /* PCIe */ 3269 sc->bge_flags |= BGEF_PCIE; 3270 /* Extract supported maximum payload size. */ 3271 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3272 sc->bge_pciecap + PCIE_DCAP); 3273 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3274 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3275 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3276 sc->bge_expmrq = 2048; 3277 else 3278 sc->bge_expmrq = 4096; 3279 bge_set_max_readrq(sc); 3280 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3281 /* PCIe without PCIe cap */ 3282 sc->bge_flags |= BGEF_PCIE; 3283 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3284 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3285 /* PCI-X */ 3286 sc->bge_flags |= BGEF_PCIX; 3287 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3288 &sc->bge_pcixcap, NULL) == 0) 3289 aprint_error_dev(sc->bge_dev, 3290 "unable to find PCIX capability\n"); 3291 } 3292 3293 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3294 /* 3295 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3296 * can clobber the chip's PCI config-space power control 3297 * registers, leaving the card in D3 powersave state. We do 3298 * not have memory-mapped registers in this state, so force 3299 * device into D0 state before starting initialization. 3300 */ 3301 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3302 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3303 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3304 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3305 DELAY(1000); /* 27 usec is allegedly sufficient */ 3306 } 3307 3308 /* Save chipset family. */ 3309 switch (BGE_ASICREV(sc->bge_chipid)) { 3310 case BGE_ASICREV_BCM5717: 3311 case BGE_ASICREV_BCM5719: 3312 case BGE_ASICREV_BCM5720: 3313 sc->bge_flags |= BGEF_5717_PLUS; 3314 /* FALLTHROUGH */ 3315 case BGE_ASICREV_BCM5762: 3316 case BGE_ASICREV_BCM57765: 3317 case BGE_ASICREV_BCM57766: 3318 if (!BGE_IS_5717_PLUS(sc)) 3319 sc->bge_flags |= BGEF_57765_FAMILY; 3320 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3321 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3322 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3323 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3324 /* 3325 * Enable work around for DMA engine miscalculation 3326 * of TXMBUF available space. 3327 */ 3328 sc->bge_flags |= BGEF_RDMA_BUG; 3329 3330 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3331 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3332 /* Jumbo frame on BCM5719 A0 does not work. */ 3333 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3334 } 3335 } 3336 break; 3337 case BGE_ASICREV_BCM5755: 3338 case BGE_ASICREV_BCM5761: 3339 case BGE_ASICREV_BCM5784: 3340 case BGE_ASICREV_BCM5785: 3341 case BGE_ASICREV_BCM5787: 3342 case BGE_ASICREV_BCM57780: 3343 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3344 break; 3345 case BGE_ASICREV_BCM5700: 3346 case BGE_ASICREV_BCM5701: 3347 case BGE_ASICREV_BCM5703: 3348 case BGE_ASICREV_BCM5704: 3349 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3350 break; 3351 case BGE_ASICREV_BCM5714_A0: 3352 case BGE_ASICREV_BCM5780: 3353 case BGE_ASICREV_BCM5714: 3354 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3355 /* FALLTHROUGH */ 3356 case BGE_ASICREV_BCM5750: 3357 case BGE_ASICREV_BCM5752: 3358 case BGE_ASICREV_BCM5906: 3359 sc->bge_flags |= BGEF_575X_PLUS; 3360 /* FALLTHROUGH */ 3361 case BGE_ASICREV_BCM5705: 3362 sc->bge_flags |= BGEF_5705_PLUS; 3363 break; 3364 } 3365 3366 /* Identify chips with APE processor. */ 3367 switch (BGE_ASICREV(sc->bge_chipid)) { 3368 case BGE_ASICREV_BCM5717: 3369 case BGE_ASICREV_BCM5719: 3370 case BGE_ASICREV_BCM5720: 3371 case BGE_ASICREV_BCM5761: 3372 case BGE_ASICREV_BCM5762: 3373 sc->bge_flags |= BGEF_APE; 3374 break; 3375 } 3376 3377 /* 3378 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3379 * not actually a MAC controller bug but an issue with the embedded 3380 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3381 */ 3382 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3383 sc->bge_flags |= BGEF_40BIT_BUG; 3384 3385 /* Chips with APE need BAR2 access for APE registers/memory. */ 3386 if ((sc->bge_flags & BGEF_APE) != 0) { 3387 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3388 #if 0 3389 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3390 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3391 &sc->bge_apesize)) { 3392 aprint_error_dev(sc->bge_dev, 3393 "couldn't map BAR2 memory\n"); 3394 return; 3395 } 3396 #else 3397 /* 3398 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3399 * system get NMI on boot (PR#48451). This problem might not be 3400 * the driver's bug but our PCI common part's bug. Until we 3401 * find a real reason, we ignore the prefetchable bit. 3402 */ 3403 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3404 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3405 aprint_error_dev(sc->bge_dev, 3406 "couldn't map BAR2 memory\n"); 3407 return; 3408 } 3409 3410 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3411 if (bus_space_map(pa->pa_memt, memaddr, 3412 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3413 aprint_error_dev(sc->bge_dev, 3414 "couldn't map BAR2 memory\n"); 3415 return; 3416 } 3417 sc->bge_apetag = pa->pa_memt; 3418 #endif 3419 3420 /* Enable APE register/memory access by host driver. */ 3421 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3422 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3423 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3424 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3425 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3426 3427 bge_ape_lock_init(sc); 3428 bge_ape_read_fw_ver(sc); 3429 } 3430 3431 /* Identify the chips that use an CPMU. */ 3432 if (BGE_IS_5717_PLUS(sc) || 3433 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3434 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3435 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3436 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3437 sc->bge_flags |= BGEF_CPMU_PRESENT; 3438 3439 /* 3440 * When using the BCM5701 in PCI-X mode, data corruption has 3441 * been observed in the first few bytes of some received packets. 3442 * Aligning the packet buffer in memory eliminates the corruption. 3443 * Unfortunately, this misaligns the packet payloads. On platforms 3444 * which do not support unaligned accesses, we will realign the 3445 * payloads by copying the received packets. 3446 */ 3447 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3448 sc->bge_flags & BGEF_PCIX) 3449 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3450 3451 if (BGE_IS_5700_FAMILY(sc)) 3452 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3453 3454 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3455 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3456 3457 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3458 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3459 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3460 sc->bge_flags |= BGEF_IS_5788; 3461 3462 /* 3463 * Some controllers seem to require a special firmware to use 3464 * TSO. But the firmware is not available to FreeBSD and Linux 3465 * claims that the TSO performed by the firmware is slower than 3466 * hardware based TSO. Moreover the firmware based TSO has one 3467 * known bug which can't handle TSO if ethernet header + IP/TCP 3468 * header is greater than 80 bytes. The workaround for the TSO 3469 * bug exist but it seems it's too expensive than not using 3470 * TSO at all. Some hardwares also have the TSO bug so limit 3471 * the TSO to the controllers that are not affected TSO issues 3472 * (e.g. 5755 or higher). 3473 */ 3474 if (BGE_IS_5755_PLUS(sc)) { 3475 /* 3476 * BCM5754 and BCM5787 shares the same ASIC id so 3477 * explicit device id check is required. 3478 */ 3479 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3480 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3481 sc->bge_flags |= BGEF_TSO; 3482 /* TSO on BCM5719 A0 does not work. */ 3483 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3484 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3485 sc->bge_flags &= ~BGEF_TSO; 3486 } 3487 3488 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3489 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3490 (misccfg == 0x4000 || misccfg == 0x8000)) || 3491 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3492 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3493 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3494 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3495 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3496 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3497 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3498 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3499 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3500 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3501 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3502 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3503 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3504 /* These chips are 10/100 only. */ 3505 capmask &= ~BMSR_EXTSTAT; 3506 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3507 } 3508 3509 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3510 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3511 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3512 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3513 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3514 3515 /* Set various PHY bug flags. */ 3516 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3517 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3518 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3519 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3520 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3521 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3522 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3523 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3524 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3525 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3526 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3527 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3528 if (BGE_IS_5705_PLUS(sc) && 3529 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3530 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3531 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3532 !BGE_IS_57765_PLUS(sc)) { 3533 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3534 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3535 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3536 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3537 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3538 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3539 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3540 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3541 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3542 } else 3543 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3544 } 3545 3546 /* 3547 * SEEPROM check. 3548 * First check if firmware knows we do not have SEEPROM. 3549 */ 3550 if (prop_dictionary_get_bool(device_properties(self), 3551 "without-seeprom", &no_seeprom) && no_seeprom) 3552 sc->bge_flags |= BGEF_NO_EEPROM; 3553 3554 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3555 sc->bge_flags |= BGEF_NO_EEPROM; 3556 3557 /* Now check the 'ROM failed' bit on the RX CPU */ 3558 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3559 sc->bge_flags |= BGEF_NO_EEPROM; 3560 3561 sc->bge_asf_mode = 0; 3562 /* No ASF if APE present. */ 3563 if ((sc->bge_flags & BGEF_APE) == 0) { 3564 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3565 BGE_SRAM_DATA_SIG_MAGIC)) { 3566 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3567 BGE_HWCFG_ASF) { 3568 sc->bge_asf_mode |= ASF_ENABLE; 3569 sc->bge_asf_mode |= ASF_STACKUP; 3570 if (BGE_IS_575X_PLUS(sc)) 3571 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3572 } 3573 } 3574 } 3575 3576 int counts[PCI_INTR_TYPE_SIZE] = { 3577 [PCI_INTR_TYPE_INTX] = 1, 3578 [PCI_INTR_TYPE_MSI] = 1, 3579 [PCI_INTR_TYPE_MSIX] = 1, 3580 }; 3581 int max_type = PCI_INTR_TYPE_MSIX; 3582 3583 if (!bge_can_use_msi(sc)) { 3584 /* MSI broken, allow only INTx */ 3585 max_type = PCI_INTR_TYPE_INTX; 3586 } 3587 3588 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3589 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3590 return; 3591 } 3592 3593 DPRINTFN(5, ("pci_intr_string\n")); 3594 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3595 sizeof(intrbuf)); 3596 DPRINTFN(5, ("pci_intr_establish\n")); 3597 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3598 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3599 if (sc->bge_intrhand == NULL) { 3600 pci_intr_release(pc, sc->bge_pihp, 1); 3601 sc->bge_pihp = NULL; 3602 3603 aprint_error_dev(self, "couldn't establish interrupt"); 3604 if (intrstr != NULL) 3605 aprint_error(" at %s", intrstr); 3606 aprint_error("\n"); 3607 return; 3608 } 3609 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3610 3611 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3612 case PCI_INTR_TYPE_MSIX: 3613 case PCI_INTR_TYPE_MSI: 3614 KASSERT(bge_can_use_msi(sc)); 3615 sc->bge_flags |= BGEF_MSI; 3616 break; 3617 default: 3618 /* nothing to do */ 3619 break; 3620 } 3621 3622 /* 3623 * All controllers except BCM5700 supports tagged status but 3624 * we use tagged status only for MSI case on BCM5717. Otherwise 3625 * MSI on BCM5717 does not work. 3626 */ 3627 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3628 sc->bge_flags |= BGEF_TAGGED_STATUS; 3629 3630 /* 3631 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3632 * lock in bge_reset(). 3633 */ 3634 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3635 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3636 delay(1000); 3637 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3638 3639 bge_stop_fw(sc); 3640 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3641 if (bge_reset(sc)) 3642 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3643 3644 /* 3645 * Read the hardware config word in the first 32k of NIC internal 3646 * memory, or fall back to the config word in the EEPROM. 3647 * Note: on some BCM5700 cards, this value appears to be unset. 3648 */ 3649 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3650 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3651 BGE_SRAM_DATA_SIG_MAGIC) { 3652 uint32_t tmp; 3653 3654 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3655 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3656 BGE_SRAM_DATA_VER_SHIFT; 3657 if ((0 < tmp) && (tmp < 0x100)) 3658 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3659 if (sc->bge_flags & BGEF_PCIE) 3660 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3661 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3662 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3663 if (BGE_IS_5717_PLUS(sc)) 3664 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3665 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3666 bge_read_eeprom(sc, (void *)&hwcfg, 3667 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3668 hwcfg = be32toh(hwcfg); 3669 } 3670 aprint_normal_dev(sc->bge_dev, 3671 "HW config %08x, %08x, %08x, %08x %08x\n", 3672 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3673 3674 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3675 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3676 3677 if (bge_chipinit(sc)) { 3678 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3679 bge_release_resources(sc); 3680 return; 3681 } 3682 3683 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3684 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3685 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3686 DELAY(100); 3687 } 3688 3689 /* Set MI_MODE */ 3690 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3691 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3692 mimode |= BGE_MIMODE_500KHZ_CONST; 3693 else 3694 mimode |= BGE_MIMODE_BASE; 3695 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3696 DELAY(80); 3697 3698 /* 3699 * Get station address from the EEPROM. 3700 */ 3701 if (bge_get_eaddr(sc, eaddr)) { 3702 aprint_error_dev(sc->bge_dev, 3703 "failed to read station address\n"); 3704 bge_release_resources(sc); 3705 return; 3706 } 3707 3708 br = bge_lookup_rev(sc->bge_chipid); 3709 3710 if (br == NULL) { 3711 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3712 sc->bge_chipid); 3713 } else { 3714 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3715 br->br_name, sc->bge_chipid); 3716 } 3717 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3718 3719 /* Allocate the general information block and ring buffers. */ 3720 if (pci_dma64_available(pa)) { 3721 sc->bge_dmatag = pa->pa_dmat64; 3722 sc->bge_dmatag32 = pa->pa_dmat; 3723 sc->bge_dma64 = true; 3724 } else { 3725 sc->bge_dmatag = pa->pa_dmat; 3726 sc->bge_dmatag32 = pa->pa_dmat; 3727 sc->bge_dma64 = false; 3728 } 3729 3730 /* 40bit DMA workaround */ 3731 if (sizeof(bus_addr_t) > 4) { 3732 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3733 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3734 3735 if (bus_dmatag_subregion(olddmatag, 0, 3736 (bus_addr_t)__MASK(40), 3737 &(sc->bge_dmatag), BUS_DMA_NOWAIT) != 0) { 3738 aprint_error_dev(self, 3739 "WARNING: failed to restrict dma range," 3740 " falling back to parent bus dma range\n"); 3741 sc->bge_dmatag = olddmatag; 3742 } 3743 } 3744 } 3745 SLIST_INIT(&sc->txdma_list); 3746 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3747 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3748 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3749 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3750 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3751 return; 3752 } 3753 DPRINTFN(5, ("bus_dmamem_map\n")); 3754 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3755 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3756 BUS_DMA_NOWAIT)) { 3757 aprint_error_dev(sc->bge_dev, 3758 "can't map DMA buffers (%zu bytes)\n", 3759 sizeof(struct bge_ring_data)); 3760 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3761 sc->bge_ring_rseg); 3762 return; 3763 } 3764 DPRINTFN(5, ("bus_dmamem_create\n")); 3765 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3766 sizeof(struct bge_ring_data), 0, 3767 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3768 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3769 bus_dmamem_unmap(sc->bge_dmatag, kva, 3770 sizeof(struct bge_ring_data)); 3771 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3772 sc->bge_ring_rseg); 3773 return; 3774 } 3775 DPRINTFN(5, ("bus_dmamem_load\n")); 3776 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3777 sizeof(struct bge_ring_data), NULL, 3778 BUS_DMA_NOWAIT)) { 3779 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3780 bus_dmamem_unmap(sc->bge_dmatag, kva, 3781 sizeof(struct bge_ring_data)); 3782 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3783 sc->bge_ring_rseg); 3784 return; 3785 } 3786 3787 DPRINTFN(5, ("bzero\n")); 3788 sc->bge_rdata = (struct bge_ring_data *)kva; 3789 3790 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3791 3792 /* Try to allocate memory for jumbo buffers. */ 3793 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3794 if (bge_alloc_jumbo_mem(sc)) { 3795 aprint_error_dev(sc->bge_dev, 3796 "jumbo buffer allocation failed\n"); 3797 } else 3798 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3799 } 3800 3801 /* Set default tuneable values. */ 3802 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3803 sc->bge_rx_coal_ticks = 150; 3804 sc->bge_rx_max_coal_bds = 64; 3805 sc->bge_tx_coal_ticks = 300; 3806 sc->bge_tx_max_coal_bds = 400; 3807 if (BGE_IS_5705_PLUS(sc)) { 3808 sc->bge_tx_coal_ticks = (12 * 5); 3809 sc->bge_tx_max_coal_bds = (12 * 5); 3810 aprint_verbose_dev(sc->bge_dev, 3811 "setting short Tx thresholds\n"); 3812 } 3813 3814 if (BGE_IS_5717_PLUS(sc)) 3815 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3816 else if (BGE_IS_5705_PLUS(sc)) 3817 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3818 else 3819 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3820 3821 /* Set up ifnet structure */ 3822 ifp = &sc->ethercom.ec_if; 3823 ifp->if_softc = sc; 3824 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3825 ifp->if_ioctl = bge_ioctl; 3826 ifp->if_stop = bge_stop; 3827 ifp->if_start = bge_start; 3828 ifp->if_init = bge_init; 3829 ifp->if_watchdog = bge_watchdog; 3830 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3831 IFQ_SET_READY(&ifp->if_snd); 3832 DPRINTFN(5, ("strcpy if_xname\n")); 3833 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3834 3835 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3836 sc->ethercom.ec_if.if_capabilities |= 3837 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3838 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3839 sc->ethercom.ec_if.if_capabilities |= 3840 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3841 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3842 #endif 3843 sc->ethercom.ec_capabilities |= 3844 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3845 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3846 3847 if (sc->bge_flags & BGEF_TSO) 3848 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3849 3850 /* 3851 * Do MII setup. 3852 */ 3853 DPRINTFN(5, ("mii setup\n")); 3854 mii->mii_ifp = ifp; 3855 mii->mii_readreg = bge_miibus_readreg; 3856 mii->mii_writereg = bge_miibus_writereg; 3857 mii->mii_statchg = bge_miibus_statchg; 3858 3859 /* 3860 * Figure out what sort of media we have by checking the hardware 3861 * config word. Note: on some BCM5700 cards, this value appears to be 3862 * unset. If that's the case, we have to rely on identifying the NIC 3863 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3864 * The SysKonnect SK-9D41 is a 1000baseSX card. 3865 */ 3866 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3867 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3868 if (BGE_IS_5705_PLUS(sc)) { 3869 sc->bge_flags |= BGEF_FIBER_MII; 3870 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3871 } else 3872 sc->bge_flags |= BGEF_FIBER_TBI; 3873 } 3874 3875 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3876 if (BGE_IS_JUMBO_CAPABLE(sc)) 3877 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3878 3879 /* set phyflags and chipid before mii_attach() */ 3880 dict = device_properties(self); 3881 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3882 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3883 3884 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3885 macmode &= ~BGE_MACMODE_PORTMODE; 3886 /* Initialize ifmedia structures. */ 3887 if (sc->bge_flags & BGEF_FIBER_TBI) { 3888 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3889 macmode | BGE_PORTMODE_TBI); 3890 DELAY(40); 3891 3892 sc->ethercom.ec_ifmedia = &sc->bge_ifmedia; 3893 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3894 bge_ifmedia_sts); 3895 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3896 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3897 0, NULL); 3898 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3899 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3900 /* Pretend the user requested this setting */ 3901 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3902 } else { 3903 uint16_t phyreg; 3904 int rv; 3905 /* 3906 * Do transceiver setup and tell the firmware the 3907 * driver is down so we can try to get access the 3908 * probe if ASF is running. Retry a couple of times 3909 * if we get a conflict with the ASF firmware accessing 3910 * the PHY. 3911 */ 3912 if (sc->bge_flags & BGEF_FIBER_MII) 3913 macmode |= BGE_PORTMODE_GMII; 3914 else 3915 macmode |= BGE_PORTMODE_MII; 3916 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3917 DELAY(40); 3918 3919 /* 3920 * Do transceiver setup and tell the firmware the 3921 * driver is down so we can try to get access the 3922 * probe if ASF is running. Retry a couple of times 3923 * if we get a conflict with the ASF firmware accessing 3924 * the PHY. 3925 */ 3926 trys = 0; 3927 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3928 sc->ethercom.ec_mii = mii; 3929 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3930 bge_ifmedia_sts); 3931 mii_flags = MIIF_DOPAUSE; 3932 if (sc->bge_flags & BGEF_FIBER_MII) 3933 mii_flags |= MIIF_HAVEFIBER; 3934 again: 3935 bge_asf_driver_up(sc); 3936 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 3937 MII_BMCR, &phyreg); 3938 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 3939 int i; 3940 3941 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 3942 MII_BMCR, BMCR_RESET); 3943 /* Wait up to 500ms for it to complete. */ 3944 for (i = 0; i < 500; i++) { 3945 bge_miibus_readreg(sc->bge_dev, 3946 sc->bge_phy_addr, MII_BMCR, &phyreg); 3947 if ((phyreg & BMCR_RESET) == 0) 3948 break; 3949 DELAY(1000); 3950 } 3951 } 3952 3953 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 3954 MII_OFFSET_ANY, mii_flags); 3955 3956 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 3957 goto again; 3958 3959 if (LIST_EMPTY(&mii->mii_phys)) { 3960 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3961 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 3962 0, NULL); 3963 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 3964 } else 3965 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 3966 3967 /* 3968 * Now tell the firmware we are going up after probing the PHY 3969 */ 3970 if (sc->bge_asf_mode & ASF_STACKUP) 3971 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3972 } 3973 3974 /* 3975 * Call MI attach routine. 3976 */ 3977 DPRINTFN(5, ("if_attach\n")); 3978 if_attach(ifp); 3979 if_deferred_start_init(ifp, NULL); 3980 DPRINTFN(5, ("ether_ifattach\n")); 3981 ether_ifattach(ifp, eaddr); 3982 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3983 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3984 RND_TYPE_NET, RND_FLAG_DEFAULT); 3985 #ifdef BGE_EVENT_COUNTERS 3986 /* 3987 * Attach event counters. 3988 */ 3989 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3990 NULL, device_xname(sc->bge_dev), "intr"); 3991 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3992 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3993 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3994 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3995 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3996 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3997 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3998 NULL, device_xname(sc->bge_dev), "tx_xon"); 3999 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4000 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4001 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4002 NULL, device_xname(sc->bge_dev), "rx_xon"); 4003 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4004 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4005 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4006 NULL, device_xname(sc->bge_dev), "xoffentered"); 4007 #endif /* BGE_EVENT_COUNTERS */ 4008 DPRINTFN(5, ("callout_init\n")); 4009 callout_init(&sc->bge_timeout, 0); 4010 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4011 4012 if (pmf_device_register(self, NULL, NULL)) 4013 pmf_class_network_register(self, ifp); 4014 else 4015 aprint_error_dev(self, "couldn't establish power handler\n"); 4016 4017 bge_sysctl_init(sc); 4018 4019 #ifdef BGE_DEBUG 4020 bge_debug_info(sc); 4021 #endif 4022 } 4023 4024 /* 4025 * Stop all chip I/O so that the kernel's probe routines don't 4026 * get confused by errant DMAs when rebooting. 4027 */ 4028 static int 4029 bge_detach(device_t self, int flags __unused) 4030 { 4031 struct bge_softc * const sc = device_private(self); 4032 struct ifnet * const ifp = &sc->ethercom.ec_if; 4033 int s; 4034 4035 s = splnet(); 4036 /* Stop the interface. Callouts are stopped in it. */ 4037 bge_stop(ifp, 1); 4038 splx(s); 4039 4040 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4041 4042 ether_ifdetach(ifp); 4043 if_detach(ifp); 4044 4045 /* Delete all remaining media. */ 4046 ifmedia_fini(&sc->bge_mii.mii_media); 4047 4048 bge_release_resources(sc); 4049 4050 return 0; 4051 } 4052 4053 static void 4054 bge_release_resources(struct bge_softc *sc) 4055 { 4056 4057 /* Detach sysctl */ 4058 if (sc->bge_log != NULL) 4059 sysctl_teardown(&sc->bge_log); 4060 4061 #ifdef BGE_EVENT_COUNTERS 4062 /* Detach event counters. */ 4063 evcnt_detach(&sc->bge_ev_intr); 4064 evcnt_detach(&sc->bge_ev_intr_spurious); 4065 evcnt_detach(&sc->bge_ev_intr_spurious2); 4066 evcnt_detach(&sc->bge_ev_tx_xoff); 4067 evcnt_detach(&sc->bge_ev_tx_xon); 4068 evcnt_detach(&sc->bge_ev_rx_xoff); 4069 evcnt_detach(&sc->bge_ev_rx_xon); 4070 evcnt_detach(&sc->bge_ev_rx_macctl); 4071 evcnt_detach(&sc->bge_ev_xoffentered); 4072 #endif /* BGE_EVENT_COUNTERS */ 4073 4074 /* Disestablish the interrupt handler */ 4075 if (sc->bge_intrhand != NULL) { 4076 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4077 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4078 sc->bge_intrhand = NULL; 4079 } 4080 4081 if (sc->bge_dmatag != NULL) { 4082 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4083 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4084 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4085 sizeof(struct bge_ring_data)); 4086 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4087 sc->bge_ring_rseg); 4088 } 4089 4090 /* Unmap the device registers */ 4091 if (sc->bge_bsize != 0) { 4092 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4093 sc->bge_bsize = 0; 4094 } 4095 4096 /* Unmap the APE registers */ 4097 if (sc->bge_apesize != 0) { 4098 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4099 sc->bge_apesize); 4100 sc->bge_apesize = 0; 4101 } 4102 } 4103 4104 static int 4105 bge_reset(struct bge_softc *sc) 4106 { 4107 uint32_t cachesize, command; 4108 uint32_t reset, mac_mode, mac_mode_mask; 4109 pcireg_t devctl, reg; 4110 int i, val; 4111 void (*write_op)(struct bge_softc *, int, int); 4112 4113 /* Make mask for BGE_MAC_MODE register. */ 4114 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4115 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4116 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4117 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4118 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4119 4120 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4121 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4122 if (sc->bge_flags & BGEF_PCIE) 4123 write_op = bge_writemem_direct; 4124 else 4125 write_op = bge_writemem_ind; 4126 } else 4127 write_op = bge_writereg_ind; 4128 4129 /* 57XX step 4 */ 4130 /* Acquire the NVM lock */ 4131 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4132 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4133 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4134 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4135 for (i = 0; i < 8000; i++) { 4136 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4137 BGE_NVRAMSWARB_GNT1) 4138 break; 4139 DELAY(20); 4140 } 4141 if (i == 8000) { 4142 printf("%s: NVRAM lock timedout!\n", 4143 device_xname(sc->bge_dev)); 4144 } 4145 } 4146 4147 /* Take APE lock when performing reset. */ 4148 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4149 4150 /* 57XX step 3 */ 4151 /* Save some important PCI state. */ 4152 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4153 /* 5718 reset step 3 */ 4154 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4155 4156 /* 5718 reset step 5, 57XX step 5b-5d */ 4157 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4158 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4159 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4160 4161 /* XXX ???: Disable fastboot on controllers that support it. */ 4162 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4163 BGE_IS_5755_PLUS(sc)) 4164 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4165 4166 /* 5718 reset step 2, 57XX step 6 */ 4167 /* 4168 * Write the magic number to SRAM at offset 0xB50. 4169 * When firmware finishes its initialization it will 4170 * write ~BGE_MAGIC_NUMBER to the same location. 4171 */ 4172 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4173 4174 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4175 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4176 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4177 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4178 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4179 } 4180 4181 /* 5718 reset step 6, 57XX step 7 */ 4182 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4183 /* 4184 * XXX: from FreeBSD/Linux; no documentation 4185 */ 4186 if (sc->bge_flags & BGEF_PCIE) { 4187 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4188 !BGE_IS_57765_PLUS(sc) && 4189 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4190 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4191 /* PCI Express 1.0 system */ 4192 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4193 BGE_PHY_PCIE_SCRAM_MODE); 4194 } 4195 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4196 /* 4197 * Prevent PCI Express link training 4198 * during global reset. 4199 */ 4200 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4201 reset |= (1 << 29); 4202 } 4203 } 4204 4205 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4206 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4207 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4208 i | BGE_VCPU_STATUS_DRV_RESET); 4209 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4210 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4211 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4212 } 4213 4214 /* 4215 * Set GPHY Power Down Override to leave GPHY 4216 * powered up in D0 uninitialized. 4217 */ 4218 if (BGE_IS_5705_PLUS(sc) && 4219 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4220 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4221 4222 /* Issue global reset */ 4223 write_op(sc, BGE_MISC_CFG, reset); 4224 4225 /* 5718 reset step 7, 57XX step 8 */ 4226 if (sc->bge_flags & BGEF_PCIE) 4227 delay(100*1000); /* too big */ 4228 else 4229 delay(1000); 4230 4231 if (sc->bge_flags & BGEF_PCIE) { 4232 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4233 DELAY(500000); 4234 /* XXX: Magic Numbers */ 4235 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4236 BGE_PCI_UNKNOWN0); 4237 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4238 BGE_PCI_UNKNOWN0, 4239 reg | (1 << 15)); 4240 } 4241 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4242 sc->bge_pciecap + PCIE_DCSR); 4243 /* Clear enable no snoop and disable relaxed ordering. */ 4244 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4245 PCIE_DCSR_ENA_NO_SNOOP); 4246 4247 /* Set PCIE max payload size to 128 for older PCIe devices */ 4248 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4249 devctl &= ~(0x00e0); 4250 /* Clear device status register. Write 1b to clear */ 4251 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4252 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4253 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4254 sc->bge_pciecap + PCIE_DCSR, devctl); 4255 bge_set_max_readrq(sc); 4256 } 4257 4258 /* From Linux: dummy read to flush PCI posted writes */ 4259 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4260 4261 /* 4262 * Reset some of the PCI state that got zapped by reset 4263 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4264 * set, too. 4265 */ 4266 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4267 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4268 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4269 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4270 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4271 (sc->bge_flags & BGEF_PCIX) != 0) 4272 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4273 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4274 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4275 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4276 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4277 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4278 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4279 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4280 4281 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4282 if (sc->bge_flags & BGEF_PCIX) { 4283 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4284 + PCIX_CMD); 4285 /* Set max memory read byte count to 2K */ 4286 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4287 reg &= ~PCIX_CMD_BYTECNT_MASK; 4288 reg |= PCIX_CMD_BCNT_2048; 4289 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4290 /* 4291 * For 5704, set max outstanding split transaction 4292 * field to 0 (0 means it supports 1 request) 4293 */ 4294 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4295 | PCIX_CMD_BYTECNT_MASK); 4296 reg |= PCIX_CMD_BCNT_2048; 4297 } 4298 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4299 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4300 } 4301 4302 /* 5718 reset step 10, 57XX step 12 */ 4303 /* Enable memory arbiter. */ 4304 if (BGE_IS_5714_FAMILY(sc)) { 4305 val = CSR_READ_4(sc, BGE_MARB_MODE); 4306 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4307 } else 4308 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4309 4310 /* XXX 5721, 5751 and 5752 */ 4311 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4312 /* Step 19: */ 4313 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4314 /* Step 20: */ 4315 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4316 } 4317 4318 /* 5718 reset step 12, 57XX step 15 and 16 */ 4319 /* Fix up byte swapping */ 4320 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4321 4322 /* 5718 reset step 13, 57XX step 17 */ 4323 /* Poll until the firmware initialization is complete */ 4324 bge_poll_fw(sc); 4325 4326 /* 57XX step 21 */ 4327 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4328 pcireg_t msidata; 4329 4330 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4331 BGE_PCI_MSI_DATA); 4332 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4333 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4334 msidata); 4335 } 4336 4337 /* 57XX step 18 */ 4338 /* Write mac mode. */ 4339 val = CSR_READ_4(sc, BGE_MAC_MODE); 4340 /* Restore mac_mode_mask's bits using mac_mode */ 4341 val = (val & ~mac_mode_mask) | mac_mode; 4342 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4343 DELAY(40); 4344 4345 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4346 4347 /* 4348 * The 5704 in TBI mode apparently needs some special 4349 * adjustment to insure the SERDES drive level is set 4350 * to 1.2V. 4351 */ 4352 if (sc->bge_flags & BGEF_FIBER_TBI && 4353 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4354 uint32_t serdescfg; 4355 4356 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4357 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4358 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4359 } 4360 4361 if (sc->bge_flags & BGEF_PCIE && 4362 !BGE_IS_57765_PLUS(sc) && 4363 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4364 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4365 uint32_t v; 4366 4367 /* Enable PCI Express bug fix */ 4368 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4369 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4370 v | BGE_TLP_DATA_FIFO_PROTECT); 4371 } 4372 4373 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4374 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4375 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4376 4377 return 0; 4378 } 4379 4380 /* 4381 * Frame reception handling. This is called if there's a frame 4382 * on the receive return list. 4383 * 4384 * Note: we have to be able to handle two possibilities here: 4385 * 1) the frame is from the jumbo receive ring 4386 * 2) the frame is from the standard receive ring 4387 */ 4388 4389 static void 4390 bge_rxeof(struct bge_softc *sc) 4391 { 4392 struct ifnet * const ifp = &sc->ethercom.ec_if; 4393 uint16_t rx_prod, rx_cons; 4394 int stdcnt = 0, jumbocnt = 0; 4395 bus_dmamap_t dmamap; 4396 bus_addr_t offset, toff; 4397 bus_size_t tlen; 4398 int tosync; 4399 4400 rx_cons = sc->bge_rx_saved_considx; 4401 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4402 4403 /* Nothing to do */ 4404 if (rx_cons == rx_prod) 4405 return; 4406 4407 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4408 offsetof(struct bge_ring_data, bge_status_block), 4409 sizeof (struct bge_status_block), 4410 BUS_DMASYNC_POSTREAD); 4411 4412 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4413 tosync = rx_prod - rx_cons; 4414 4415 if (tosync != 0) 4416 rnd_add_uint32(&sc->rnd_source, tosync); 4417 4418 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 4419 4420 if (tosync < 0) { 4421 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4422 sizeof (struct bge_rx_bd); 4423 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4424 toff, tlen, BUS_DMASYNC_POSTREAD); 4425 tosync = -tosync; 4426 } 4427 4428 if (tosync != 0) { 4429 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4430 offset, tosync * sizeof (struct bge_rx_bd), 4431 BUS_DMASYNC_POSTREAD); 4432 } 4433 4434 while (rx_cons != rx_prod) { 4435 struct bge_rx_bd *cur_rx; 4436 uint32_t rxidx; 4437 struct mbuf *m = NULL; 4438 4439 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4440 4441 rxidx = cur_rx->bge_idx; 4442 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4443 4444 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4445 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4446 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4447 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4448 jumbocnt++; 4449 bus_dmamap_sync(sc->bge_dmatag, 4450 sc->bge_cdata.bge_rx_jumbo_map, 4451 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4452 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4453 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4454 if_statinc(ifp, if_ierrors); 4455 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4456 continue; 4457 } 4458 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4459 NULL)== ENOBUFS) { 4460 if_statinc(ifp, if_ierrors); 4461 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4462 continue; 4463 } 4464 } else { 4465 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4466 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4467 4468 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4469 stdcnt++; 4470 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4471 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4472 if (dmamap == NULL) { 4473 if_statinc(ifp, if_ierrors); 4474 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4475 continue; 4476 } 4477 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4478 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4479 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4480 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4481 if_statinc(ifp, if_ierrors); 4482 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4483 continue; 4484 } 4485 if (bge_newbuf_std(sc, sc->bge_std, 4486 NULL, dmamap) == ENOBUFS) { 4487 if_statinc(ifp, if_ierrors); 4488 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4489 continue; 4490 } 4491 } 4492 4493 #ifndef __NO_STRICT_ALIGNMENT 4494 /* 4495 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4496 * the Rx buffer has the layer-2 header unaligned. 4497 * If our CPU requires alignment, re-align by copying. 4498 */ 4499 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4500 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4501 cur_rx->bge_len); 4502 m->m_data += ETHER_ALIGN; 4503 } 4504 #endif 4505 4506 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4507 m_set_rcvif(m, ifp); 4508 4509 bge_rxcsum(sc, cur_rx, m); 4510 4511 /* 4512 * If we received a packet with a vlan tag, pass it 4513 * to vlan_input() instead of ether_input(). 4514 */ 4515 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4516 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4517 4518 if_percpuq_enqueue(ifp->if_percpuq, m); 4519 } 4520 4521 sc->bge_rx_saved_considx = rx_cons; 4522 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4523 if (stdcnt) 4524 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4525 if (jumbocnt) 4526 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4527 } 4528 4529 static void 4530 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4531 { 4532 4533 if (BGE_IS_57765_PLUS(sc)) { 4534 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4535 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4536 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4537 if ((cur_rx->bge_error_flag & 4538 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4539 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4540 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4541 m->m_pkthdr.csum_data = 4542 cur_rx->bge_tcp_udp_csum; 4543 m->m_pkthdr.csum_flags |= 4544 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4545 } 4546 } 4547 } else { 4548 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4549 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4550 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4551 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4552 /* 4553 * Rx transport checksum-offload may also 4554 * have bugs with packets which, when transmitted, 4555 * were `runts' requiring padding. 4556 */ 4557 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4558 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4559 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4560 m->m_pkthdr.csum_data = 4561 cur_rx->bge_tcp_udp_csum; 4562 m->m_pkthdr.csum_flags |= 4563 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4564 } 4565 } 4566 } 4567 4568 static void 4569 bge_txeof(struct bge_softc *sc) 4570 { 4571 struct ifnet * const ifp = &sc->ethercom.ec_if; 4572 struct bge_tx_bd *cur_tx = NULL; 4573 struct txdmamap_pool_entry *dma; 4574 bus_addr_t offset, toff; 4575 bus_size_t tlen; 4576 int tosync; 4577 struct mbuf *m; 4578 4579 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4580 offsetof(struct bge_ring_data, bge_status_block), 4581 sizeof (struct bge_status_block), 4582 BUS_DMASYNC_POSTREAD); 4583 4584 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4585 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4586 sc->bge_tx_saved_considx; 4587 4588 if (tosync != 0) 4589 rnd_add_uint32(&sc->rnd_source, tosync); 4590 4591 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 4592 4593 if (tosync < 0) { 4594 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4595 sizeof (struct bge_tx_bd); 4596 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4597 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4598 tosync = -tosync; 4599 } 4600 4601 if (tosync != 0) { 4602 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4603 offset, tosync * sizeof (struct bge_tx_bd), 4604 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4605 } 4606 4607 /* 4608 * Go through our tx ring and free mbufs for those 4609 * frames that have been sent. 4610 */ 4611 while (sc->bge_tx_saved_considx != 4612 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4613 uint32_t idx = sc->bge_tx_saved_considx; 4614 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4615 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4616 if_statinc(ifp, if_opackets); 4617 m = sc->bge_cdata.bge_tx_chain[idx]; 4618 if (m != NULL) { 4619 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4620 dma = sc->txdma[idx]; 4621 if (dma->is_dma32) { 4622 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4623 0, dma->dmamap32->dm_mapsize, 4624 BUS_DMASYNC_POSTWRITE); 4625 bus_dmamap_unload( 4626 sc->bge_dmatag32, dma->dmamap32); 4627 } else { 4628 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4629 0, dma->dmamap->dm_mapsize, 4630 BUS_DMASYNC_POSTWRITE); 4631 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4632 } 4633 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4634 sc->txdma[idx] = NULL; 4635 4636 m_freem(m); 4637 } 4638 sc->bge_txcnt--; 4639 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4640 ifp->if_timer = 0; 4641 } 4642 4643 if (cur_tx != NULL) 4644 ifp->if_flags &= ~IFF_OACTIVE; 4645 } 4646 4647 static int 4648 bge_intr(void *xsc) 4649 { 4650 struct bge_softc * const sc = xsc; 4651 struct ifnet * const ifp = &sc->ethercom.ec_if; 4652 uint32_t pcistate, statusword, statustag; 4653 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4654 4655 4656 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4657 if (BGE_IS_5717_PLUS(sc)) 4658 intrmask = 0; 4659 4660 /* 4661 * It is possible for the interrupt to arrive before 4662 * the status block is updated prior to the interrupt. 4663 * Reading the PCI State register will confirm whether the 4664 * interrupt is ours and will flush the status block. 4665 */ 4666 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4667 4668 /* read status word from status block */ 4669 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4670 offsetof(struct bge_ring_data, bge_status_block), 4671 sizeof (struct bge_status_block), 4672 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4673 statusword = sc->bge_rdata->bge_status_block.bge_status; 4674 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4675 4676 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4677 if (sc->bge_lasttag == statustag && 4678 (~pcistate & intrmask)) { 4679 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4680 return (0); 4681 } 4682 sc->bge_lasttag = statustag; 4683 } else { 4684 if (!(statusword & BGE_STATFLAG_UPDATED) && 4685 !(~pcistate & intrmask)) { 4686 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4687 return (0); 4688 } 4689 statustag = 0; 4690 } 4691 /* Ack interrupt and stop others from occurring. */ 4692 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4693 BGE_EVCNT_INCR(sc->bge_ev_intr); 4694 4695 /* clear status word */ 4696 sc->bge_rdata->bge_status_block.bge_status = 0; 4697 4698 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4699 offsetof(struct bge_ring_data, bge_status_block), 4700 sizeof (struct bge_status_block), 4701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4702 4703 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4704 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4705 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4706 bge_link_upd(sc); 4707 4708 if (ifp->if_flags & IFF_RUNNING) { 4709 /* Check RX return ring producer/consumer */ 4710 bge_rxeof(sc); 4711 4712 /* Check TX ring producer/consumer */ 4713 bge_txeof(sc); 4714 } 4715 4716 if (sc->bge_pending_rxintr_change) { 4717 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4718 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4719 4720 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4721 DELAY(10); 4722 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4723 4724 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4725 DELAY(10); 4726 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4727 4728 sc->bge_pending_rxintr_change = 0; 4729 } 4730 bge_handle_events(sc); 4731 4732 /* Re-enable interrupts. */ 4733 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4734 4735 if (ifp->if_flags & IFF_RUNNING) 4736 if_schedule_deferred_start(ifp); 4737 4738 return 1; 4739 } 4740 4741 static void 4742 bge_asf_driver_up(struct bge_softc *sc) 4743 { 4744 if (sc->bge_asf_mode & ASF_STACKUP) { 4745 /* Send ASF heartbeat aprox. every 2s */ 4746 if (sc->bge_asf_count) 4747 sc->bge_asf_count --; 4748 else { 4749 sc->bge_asf_count = 2; 4750 4751 bge_wait_for_event_ack(sc); 4752 4753 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4754 BGE_FW_CMD_DRV_ALIVE3); 4755 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4756 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4757 BGE_FW_HB_TIMEOUT_SEC); 4758 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4759 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4760 BGE_RX_CPU_DRV_EVENT); 4761 } 4762 } 4763 } 4764 4765 static void 4766 bge_tick(void *xsc) 4767 { 4768 struct bge_softc * const sc = xsc; 4769 struct mii_data * const mii = &sc->bge_mii; 4770 int s; 4771 4772 s = splnet(); 4773 4774 if (BGE_IS_5705_PLUS(sc)) 4775 bge_stats_update_regs(sc); 4776 else 4777 bge_stats_update(sc); 4778 4779 if (sc->bge_flags & BGEF_FIBER_TBI) { 4780 /* 4781 * Since in TBI mode auto-polling can't be used we should poll 4782 * link status manually. Here we register pending link event 4783 * and trigger interrupt. 4784 */ 4785 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4786 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4787 } else { 4788 /* 4789 * Do not touch PHY if we have link up. This could break 4790 * IPMI/ASF mode or produce extra input errors. 4791 * (extra input errors was reported for bcm5701 & bcm5704). 4792 */ 4793 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4794 mii_tick(mii); 4795 } 4796 4797 bge_asf_driver_up(sc); 4798 4799 if (!sc->bge_detaching) 4800 callout_schedule(&sc->bge_timeout, hz); 4801 4802 splx(s); 4803 } 4804 4805 static void 4806 bge_stats_update_regs(struct bge_softc *sc) 4807 { 4808 struct ifnet *const ifp = &sc->ethercom.ec_if; 4809 4810 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4811 4812 if_statadd_ref(nsr, if_collisions, 4813 CSR_READ_4(sc, BGE_MAC_STATS + 4814 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4815 4816 /* 4817 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4818 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4819 * (silicon bug). There's no reliable workaround so just 4820 * ignore the counter 4821 */ 4822 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4823 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4824 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4825 if_statadd_ref(nsr, if_ierrors, 4826 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4827 } 4828 if_statadd_ref(nsr, if_ierrors, 4829 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4830 if_statadd_ref(nsr, if_ierrors, 4831 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4832 4833 IF_STAT_PUTREF(ifp); 4834 4835 if (sc->bge_flags & BGEF_RDMA_BUG) { 4836 uint32_t val, ucast, mcast, bcast; 4837 4838 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4839 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4840 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4841 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4842 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4843 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4844 4845 /* 4846 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4847 * frames, it's safe to disable workaround for DMA engine's 4848 * miscalculation of TXMBUF space. 4849 */ 4850 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4851 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4852 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4853 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4854 else 4855 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4856 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4857 sc->bge_flags &= ~BGEF_RDMA_BUG; 4858 } 4859 } 4860 } 4861 4862 static void 4863 bge_stats_update(struct bge_softc *sc) 4864 { 4865 struct ifnet * const ifp = &sc->ethercom.ec_if; 4866 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4867 4868 #define READ_STAT(sc, stats, stat) \ 4869 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4870 4871 uint64_t collisions = 4872 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4873 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4874 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4875 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4876 4877 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4878 sc->bge_if_collisions = collisions; 4879 4880 4881 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4882 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4883 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4884 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4885 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4886 READ_STAT(sc, stats, 4887 xoffPauseFramesReceived.bge_addr_lo)); 4888 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4889 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4890 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4891 READ_STAT(sc, stats, 4892 macControlFramesReceived.bge_addr_lo)); 4893 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4894 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4895 4896 #undef READ_STAT 4897 4898 #ifdef notdef 4899 ifp->if_collisions += 4900 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4901 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4902 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4903 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4904 ifp->if_collisions; 4905 #endif 4906 } 4907 4908 /* 4909 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4910 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4911 * but when such padded frames employ the bge IP/TCP checksum offload, 4912 * the hardware checksum assist gives incorrect results (possibly 4913 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4914 * If we pad such runts with zeros, the onboard checksum comes out correct. 4915 */ 4916 static inline int 4917 bge_cksum_pad(struct mbuf *pkt) 4918 { 4919 struct mbuf *last = NULL; 4920 int padlen; 4921 4922 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4923 4924 /* if there's only the packet-header and we can pad there, use it. */ 4925 if (pkt->m_pkthdr.len == pkt->m_len && 4926 M_TRAILINGSPACE(pkt) >= padlen) { 4927 last = pkt; 4928 } else { 4929 /* 4930 * Walk packet chain to find last mbuf. We will either 4931 * pad there, or append a new mbuf and pad it 4932 * (thus perhaps avoiding the bcm5700 dma-min bug). 4933 */ 4934 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4935 continue; /* do nothing */ 4936 } 4937 4938 /* `last' now points to last in chain. */ 4939 if (M_TRAILINGSPACE(last) < padlen) { 4940 /* Allocate new empty mbuf, pad it. Compact later. */ 4941 struct mbuf *n; 4942 MGET(n, M_DONTWAIT, MT_DATA); 4943 if (n == NULL) 4944 return ENOBUFS; 4945 n->m_len = 0; 4946 last->m_next = n; 4947 last = n; 4948 } 4949 } 4950 4951 KDASSERT(!M_READONLY(last)); 4952 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4953 4954 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4955 memset(mtod(last, char *) + last->m_len, 0, padlen); 4956 last->m_len += padlen; 4957 pkt->m_pkthdr.len += padlen; 4958 return 0; 4959 } 4960 4961 /* 4962 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4963 */ 4964 static inline int 4965 bge_compact_dma_runt(struct mbuf *pkt) 4966 { 4967 struct mbuf *m, *prev; 4968 int totlen; 4969 4970 prev = NULL; 4971 totlen = 0; 4972 4973 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 4974 int mlen = m->m_len; 4975 int shortfall = 8 - mlen ; 4976 4977 totlen += mlen; 4978 if (mlen == 0) 4979 continue; 4980 if (mlen >= 8) 4981 continue; 4982 4983 /* 4984 * If we get here, mbuf data is too small for DMA engine. 4985 * Try to fix by shuffling data to prev or next in chain. 4986 * If that fails, do a compacting deep-copy of the whole chain. 4987 */ 4988 4989 /* Internal frag. If fits in prev, copy it there. */ 4990 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4991 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4992 prev->m_len += mlen; 4993 m->m_len = 0; 4994 /* XXX stitch chain */ 4995 prev->m_next = m_free(m); 4996 m = prev; 4997 continue; 4998 } else if (m->m_next != NULL && 4999 M_TRAILINGSPACE(m) >= shortfall && 5000 m->m_next->m_len >= (8 + shortfall)) { 5001 /* m is writable and have enough data in next, pull up. */ 5002 5003 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5004 shortfall); 5005 m->m_len += shortfall; 5006 m->m_next->m_len -= shortfall; 5007 m->m_next->m_data += shortfall; 5008 } else if (m->m_next == NULL || 1) { 5009 /* 5010 * Got a runt at the very end of the packet. 5011 * borrow data from the tail of the preceding mbuf and 5012 * update its length in-place. (The original data is 5013 * still valid, so we can do this even if prev is not 5014 * writable.) 5015 */ 5016 5017 /* 5018 * If we'd make prev a runt, just move all of its data. 5019 */ 5020 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5021 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5022 5023 if ((prev->m_len - shortfall) < 8) 5024 shortfall = prev->m_len; 5025 5026 #ifdef notyet /* just do the safe slow thing for now */ 5027 if (!M_READONLY(m)) { 5028 if (M_LEADINGSPACE(m) < shorfall) { 5029 void *m_dat; 5030 m_dat = M_BUFADDR(m); 5031 memmove(m_dat, mtod(m, void*), 5032 m->m_len); 5033 m->m_data = m_dat; 5034 } 5035 } else 5036 #endif /* just do the safe slow thing */ 5037 { 5038 struct mbuf * n = NULL; 5039 int newprevlen = prev->m_len - shortfall; 5040 5041 MGET(n, M_NOWAIT, MT_DATA); 5042 if (n == NULL) 5043 return ENOBUFS; 5044 KASSERT(m->m_len + shortfall < MLEN 5045 /*, 5046 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5047 5048 /* first copy the data we're stealing from prev */ 5049 memcpy(n->m_data, prev->m_data + newprevlen, 5050 shortfall); 5051 5052 /* update prev->m_len accordingly */ 5053 prev->m_len -= shortfall; 5054 5055 /* copy data from runt m */ 5056 memcpy(n->m_data + shortfall, m->m_data, 5057 m->m_len); 5058 5059 /* n holds what we stole from prev, plus m */ 5060 n->m_len = shortfall + m->m_len; 5061 5062 /* stitch n into chain and free m */ 5063 n->m_next = m->m_next; 5064 prev->m_next = n; 5065 /* KASSERT(m->m_next == NULL); */ 5066 m->m_next = NULL; 5067 m_free(m); 5068 m = n; /* for continuing loop */ 5069 } 5070 } 5071 } 5072 return 0; 5073 } 5074 5075 /* 5076 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5077 * pointers to descriptors. 5078 */ 5079 static int 5080 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5081 { 5082 struct ifnet * const ifp = &sc->ethercom.ec_if; 5083 struct bge_tx_bd *f, *prev_f; 5084 uint32_t frag, cur; 5085 uint16_t csum_flags = 0; 5086 uint16_t txbd_tso_flags = 0; 5087 struct txdmamap_pool_entry *dma; 5088 bus_dmamap_t dmamap; 5089 bus_dma_tag_t dmatag; 5090 int i = 0; 5091 int use_tso, maxsegsize, error; 5092 bool have_vtag; 5093 uint16_t vtag; 5094 bool remap; 5095 5096 if (m_head->m_pkthdr.csum_flags) { 5097 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5098 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5099 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5100 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5101 } 5102 5103 /* 5104 * If we were asked to do an outboard checksum, and the NIC 5105 * has the bug where it sometimes adds in the Ethernet padding, 5106 * explicitly pad with zeros so the cksum will be correct either way. 5107 * (For now, do this for all chip versions, until newer 5108 * are confirmed to not require the workaround.) 5109 */ 5110 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5111 #ifdef notyet 5112 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5113 #endif 5114 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5115 goto check_dma_bug; 5116 5117 if (bge_cksum_pad(m_head) != 0) 5118 return ENOBUFS; 5119 5120 check_dma_bug: 5121 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5122 goto doit; 5123 5124 /* 5125 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5126 * less than eight bytes. If we encounter a teeny mbuf 5127 * at the end of a chain, we can pad. Otherwise, copy. 5128 */ 5129 if (bge_compact_dma_runt(m_head) != 0) 5130 return ENOBUFS; 5131 5132 doit: 5133 dma = SLIST_FIRST(&sc->txdma_list); 5134 if (dma == NULL) { 5135 ifp->if_flags |= IFF_OACTIVE; 5136 return ENOBUFS; 5137 } 5138 dmamap = dma->dmamap; 5139 dmatag = sc->bge_dmatag; 5140 dma->is_dma32 = false; 5141 5142 /* 5143 * Set up any necessary TSO state before we start packing... 5144 */ 5145 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5146 if (!use_tso) { 5147 maxsegsize = 0; 5148 } else { /* TSO setup */ 5149 unsigned mss; 5150 struct ether_header *eh; 5151 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5152 unsigned bge_hlen; 5153 struct mbuf * m0 = m_head; 5154 struct ip *ip; 5155 struct tcphdr *th; 5156 int iphl, hlen; 5157 5158 /* 5159 * XXX It would be nice if the mbuf pkthdr had offset 5160 * fields for the protocol headers. 5161 */ 5162 5163 eh = mtod(m0, struct ether_header *); 5164 switch (htons(eh->ether_type)) { 5165 case ETHERTYPE_IP: 5166 offset = ETHER_HDR_LEN; 5167 break; 5168 5169 case ETHERTYPE_VLAN: 5170 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5171 break; 5172 5173 default: 5174 /* 5175 * Don't support this protocol or encapsulation. 5176 */ 5177 return ENOBUFS; 5178 } 5179 5180 /* 5181 * TCP/IP headers are in the first mbuf; we can do 5182 * this the easy way. 5183 */ 5184 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5185 hlen = iphl + offset; 5186 if (__predict_false(m0->m_len < 5187 (hlen + sizeof(struct tcphdr)))) { 5188 5189 aprint_error_dev(sc->bge_dev, 5190 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5191 "not handled yet\n", 5192 m0->m_len, hlen+ sizeof(struct tcphdr)); 5193 #ifdef NOTYET 5194 /* 5195 * XXX jonathan (at) NetBSD.org: untested. 5196 * how to force this branch to be taken? 5197 */ 5198 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5199 5200 m_copydata(m0, offset, sizeof(ip), &ip); 5201 m_copydata(m0, hlen, sizeof(th), &th); 5202 5203 ip.ip_len = 0; 5204 5205 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5206 sizeof(ip.ip_len), &ip.ip_len); 5207 5208 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5209 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5210 5211 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5212 sizeof(th.th_sum), &th.th_sum); 5213 5214 hlen += th.th_off << 2; 5215 iptcp_opt_words = hlen; 5216 #else 5217 /* 5218 * if_wm "hard" case not yet supported, can we not 5219 * mandate it out of existence? 5220 */ 5221 (void) ip; (void)th; (void) ip_tcp_hlen; 5222 5223 return ENOBUFS; 5224 #endif 5225 } else { 5226 ip = (struct ip *) (mtod(m0, char *) + offset); 5227 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5228 ip_tcp_hlen = iphl + (th->th_off << 2); 5229 5230 /* Total IP/TCP options, in 32-bit words */ 5231 iptcp_opt_words = (ip_tcp_hlen 5232 - sizeof(struct tcphdr) 5233 - sizeof(struct ip)) >> 2; 5234 } 5235 if (BGE_IS_575X_PLUS(sc)) { 5236 th->th_sum = 0; 5237 csum_flags = 0; 5238 } else { 5239 /* 5240 * XXX jonathan (at) NetBSD.org: 5705 untested. 5241 * Requires TSO firmware patch for 5701/5703/5704. 5242 */ 5243 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5244 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5245 } 5246 5247 mss = m_head->m_pkthdr.segsz; 5248 txbd_tso_flags |= 5249 BGE_TXBDFLAG_CPU_PRE_DMA | 5250 BGE_TXBDFLAG_CPU_POST_DMA; 5251 5252 /* 5253 * Our NIC TSO-assist assumes TSO has standard, optionless 5254 * IPv4 and TCP headers, which total 40 bytes. By default, 5255 * the NIC copies 40 bytes of IP/TCP header from the 5256 * supplied header into the IP/TCP header portion of 5257 * each post-TSO-segment. If the supplied packet has IP or 5258 * TCP options, we need to tell the NIC to copy those extra 5259 * bytes into each post-TSO header, in addition to the normal 5260 * 40-byte IP/TCP header (and to leave space accordingly). 5261 * Unfortunately, the driver encoding of option length 5262 * varies across different ASIC families. 5263 */ 5264 tcp_seg_flags = 0; 5265 bge_hlen = ip_tcp_hlen >> 2; 5266 if (BGE_IS_5717_PLUS(sc)) { 5267 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5268 txbd_tso_flags |= 5269 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5270 } else if (BGE_IS_5705_PLUS(sc)) { 5271 tcp_seg_flags = bge_hlen << 11; 5272 } else { 5273 /* XXX iptcp_opt_words or bge_hlen ? */ 5274 txbd_tso_flags |= iptcp_opt_words << 12; 5275 } 5276 maxsegsize = mss | tcp_seg_flags; 5277 ip->ip_len = htons(mss + ip_tcp_hlen); 5278 ip->ip_sum = 0; 5279 5280 } /* TSO setup */ 5281 5282 have_vtag = vlan_has_tag(m_head); 5283 if (have_vtag) 5284 vtag = vlan_get_tag(m_head); 5285 5286 /* 5287 * Start packing the mbufs in this chain into 5288 * the fragment pointers. Stop when we run out 5289 * of fragments or hit the end of the mbuf chain. 5290 */ 5291 remap = true; 5292 load_again: 5293 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5294 if (__predict_false(error)) { 5295 if (error == EFBIG && remap) { 5296 struct mbuf *m; 5297 remap = false; 5298 m = m_defrag(m_head, M_NOWAIT); 5299 if (m != NULL) { 5300 KASSERT(m == m_head); 5301 goto load_again; 5302 } 5303 } 5304 return error; 5305 } 5306 /* 5307 * Sanity check: avoid coming within 16 descriptors 5308 * of the end of the ring. 5309 */ 5310 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5311 BGE_TSO_PRINTF(("%s: " 5312 " dmamap_load_mbuf too close to ring wrap\n", 5313 device_xname(sc->bge_dev))); 5314 goto fail_unload; 5315 } 5316 5317 /* Iterate over dmap-map fragments. */ 5318 f = prev_f = NULL; 5319 cur = frag = *txidx; 5320 5321 for (i = 0; i < dmamap->dm_nsegs; i++) { 5322 f = &sc->bge_rdata->bge_tx_ring[frag]; 5323 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5324 break; 5325 5326 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5327 f->bge_len = dmamap->dm_segs[i].ds_len; 5328 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5329 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5330 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5331 (prev_f != NULL && 5332 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5333 ) { 5334 /* 5335 * watchdog timeout issue was observed with TSO, 5336 * limiting DMA address space to 32bits seems to 5337 * address the issue. 5338 */ 5339 bus_dmamap_unload(dmatag, dmamap); 5340 dmatag = sc->bge_dmatag32; 5341 dmamap = dma->dmamap32; 5342 dma->is_dma32 = true; 5343 remap = true; 5344 goto load_again; 5345 } 5346 5347 /* 5348 * For 5751 and follow-ons, for TSO we must turn 5349 * off checksum-assist flag in the tx-descr, and 5350 * supply the ASIC-revision-specific encoding 5351 * of TSO flags and segsize. 5352 */ 5353 if (use_tso) { 5354 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5355 f->bge_rsvd = maxsegsize; 5356 f->bge_flags = csum_flags | txbd_tso_flags; 5357 } else { 5358 f->bge_rsvd = 0; 5359 f->bge_flags = 5360 (csum_flags | txbd_tso_flags) & 0x0fff; 5361 } 5362 } else { 5363 f->bge_rsvd = 0; 5364 f->bge_flags = csum_flags; 5365 } 5366 5367 if (have_vtag) { 5368 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5369 f->bge_vlan_tag = vtag; 5370 } else { 5371 f->bge_vlan_tag = 0; 5372 } 5373 prev_f = f; 5374 cur = frag; 5375 BGE_INC(frag, BGE_TX_RING_CNT); 5376 } 5377 5378 if (i < dmamap->dm_nsegs) { 5379 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5380 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5381 goto fail_unload; 5382 } 5383 5384 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5385 BUS_DMASYNC_PREWRITE); 5386 5387 if (frag == sc->bge_tx_saved_considx) { 5388 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5389 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5390 5391 goto fail_unload; 5392 } 5393 5394 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5395 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5396 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5397 sc->txdma[cur] = dma; 5398 sc->bge_txcnt += dmamap->dm_nsegs; 5399 5400 *txidx = frag; 5401 5402 return 0; 5403 5404 fail_unload: 5405 bus_dmamap_unload(dmatag, dmamap); 5406 ifp->if_flags |= IFF_OACTIVE; 5407 5408 return ENOBUFS; 5409 } 5410 5411 /* 5412 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5413 * to the mbuf data regions directly in the transmit descriptors. 5414 */ 5415 static void 5416 bge_start(struct ifnet *ifp) 5417 { 5418 struct bge_softc * const sc = ifp->if_softc; 5419 struct mbuf *m_head = NULL; 5420 struct mbuf *m; 5421 uint32_t prodidx; 5422 int pkts = 0; 5423 int error; 5424 5425 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5426 return; 5427 5428 prodidx = sc->bge_tx_prodidx; 5429 5430 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5431 IFQ_POLL(&ifp->if_snd, m_head); 5432 if (m_head == NULL) 5433 break; 5434 5435 #if 0 5436 /* 5437 * XXX 5438 * safety overkill. If this is a fragmented packet chain 5439 * with delayed TCP/UDP checksums, then only encapsulate 5440 * it if we have enough descriptors to handle the entire 5441 * chain at once. 5442 * (paranoia -- may not actually be needed) 5443 */ 5444 if (m_head->m_flags & M_FIRSTFRAG && 5445 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5446 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5447 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5448 ifp->if_flags |= IFF_OACTIVE; 5449 break; 5450 } 5451 } 5452 #endif 5453 5454 /* 5455 * Pack the data into the transmit ring. If we 5456 * don't have room, set the OACTIVE flag and wait 5457 * for the NIC to drain the ring. 5458 */ 5459 error = bge_encap(sc, m_head, &prodidx); 5460 if (__predict_false(error)) { 5461 if (ifp->if_flags & IFF_OACTIVE) { 5462 /* just wait for the transmit ring to drain */ 5463 break; 5464 } 5465 IFQ_DEQUEUE(&ifp->if_snd, m); 5466 KASSERT(m == m_head); 5467 m_freem(m_head); 5468 continue; 5469 } 5470 5471 /* now we are committed to transmit the packet */ 5472 IFQ_DEQUEUE(&ifp->if_snd, m); 5473 KASSERT(m == m_head); 5474 pkts++; 5475 5476 /* 5477 * If there's a BPF listener, bounce a copy of this frame 5478 * to him. 5479 */ 5480 bpf_mtap(ifp, m_head, BPF_D_OUT); 5481 } 5482 if (pkts == 0) 5483 return; 5484 5485 /* Transmit */ 5486 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5487 /* 5700 b2 errata */ 5488 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5489 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5490 5491 sc->bge_tx_prodidx = prodidx; 5492 5493 /* 5494 * Set a timeout in case the chip goes out to lunch. 5495 */ 5496 ifp->if_timer = 5; 5497 } 5498 5499 static int 5500 bge_init(struct ifnet *ifp) 5501 { 5502 struct bge_softc * const sc = ifp->if_softc; 5503 const uint16_t *m; 5504 uint32_t mode, reg; 5505 int s, error = 0; 5506 5507 s = splnet(); 5508 5509 KASSERT(ifp == &sc->ethercom.ec_if); 5510 5511 /* Cancel pending I/O and flush buffers. */ 5512 bge_stop(ifp, 0); 5513 5514 bge_stop_fw(sc); 5515 bge_sig_pre_reset(sc, BGE_RESET_START); 5516 bge_reset(sc); 5517 bge_sig_legacy(sc, BGE_RESET_START); 5518 5519 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5520 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5521 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5522 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5523 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5524 5525 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5526 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5527 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5528 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5529 5530 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5531 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5532 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5533 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5534 5535 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5536 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5537 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5538 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5539 } 5540 5541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5542 pcireg_t aercap; 5543 5544 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5545 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5546 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5547 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5548 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5549 5550 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5551 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5552 | BGE_PCIE_EIDLE_DELAY_13CLK; 5553 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5554 5555 /* Clear correctable error */ 5556 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5557 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5558 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5559 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5560 5561 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5562 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5563 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5564 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5565 } 5566 5567 bge_sig_post_reset(sc, BGE_RESET_START); 5568 5569 bge_chipinit(sc); 5570 5571 /* 5572 * Init the various state machines, ring 5573 * control blocks and firmware. 5574 */ 5575 error = bge_blockinit(sc); 5576 if (error != 0) { 5577 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5578 error); 5579 splx(s); 5580 return error; 5581 } 5582 5583 /* 5718 step 25, 57XX step 54 */ 5584 /* Specify MTU. */ 5585 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5586 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5587 5588 /* 5718 step 23 */ 5589 /* Load our MAC address. */ 5590 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5591 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5592 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5593 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5594 5595 /* Enable or disable promiscuous mode as needed. */ 5596 if (ifp->if_flags & IFF_PROMISC) 5597 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5598 else 5599 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5600 5601 /* Program multicast filter. */ 5602 bge_setmulti(sc); 5603 5604 /* Init RX ring. */ 5605 bge_init_rx_ring_std(sc); 5606 5607 /* 5608 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5609 * memory to insure that the chip has in fact read the first 5610 * entry of the ring. 5611 */ 5612 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5613 uint32_t v, i; 5614 for (i = 0; i < 10; i++) { 5615 DELAY(20); 5616 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5617 if (v == (MCLBYTES - ETHER_ALIGN)) 5618 break; 5619 } 5620 if (i == 10) 5621 aprint_error_dev(sc->bge_dev, 5622 "5705 A0 chip failed to load RX ring\n"); 5623 } 5624 5625 /* Init jumbo RX ring. */ 5626 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5627 bge_init_rx_ring_jumbo(sc); 5628 5629 /* Init our RX return ring index */ 5630 sc->bge_rx_saved_considx = 0; 5631 5632 /* Init TX ring. */ 5633 bge_init_tx_ring(sc); 5634 5635 /* 5718 step 63, 57XX step 94 */ 5636 /* Enable TX MAC state machine lockup fix. */ 5637 mode = CSR_READ_4(sc, BGE_TX_MODE); 5638 if (BGE_IS_5755_PLUS(sc) || 5639 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5640 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5641 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5642 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5643 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5644 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5645 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5646 } 5647 5648 /* Turn on transmitter */ 5649 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5650 /* 5718 step 64 */ 5651 DELAY(100); 5652 5653 /* 5718 step 65, 57XX step 95 */ 5654 /* Turn on receiver */ 5655 mode = CSR_READ_4(sc, BGE_RX_MODE); 5656 if (BGE_IS_5755_PLUS(sc)) 5657 mode |= BGE_RXMODE_IPV6_ENABLE; 5658 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5659 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5660 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5661 /* 5718 step 66 */ 5662 DELAY(10); 5663 5664 /* 5718 step 12, 57XX step 37 */ 5665 /* 5666 * XXX Doucments of 5718 series and 577xx say the recommended value 5667 * is 1, but tg3 set 1 only on 57765 series. 5668 */ 5669 if (BGE_IS_57765_PLUS(sc)) 5670 reg = 1; 5671 else 5672 reg = 2; 5673 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5674 5675 /* Tell firmware we're alive. */ 5676 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5677 5678 /* Enable host interrupts. */ 5679 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5680 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5681 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5682 5683 if ((error = bge_ifmedia_upd(ifp)) != 0) 5684 goto out; 5685 5686 ifp->if_flags |= IFF_RUNNING; 5687 ifp->if_flags &= ~IFF_OACTIVE; 5688 5689 callout_schedule(&sc->bge_timeout, hz); 5690 5691 out: 5692 sc->bge_if_flags = ifp->if_flags; 5693 splx(s); 5694 5695 return error; 5696 } 5697 5698 /* 5699 * Set media options. 5700 */ 5701 static int 5702 bge_ifmedia_upd(struct ifnet *ifp) 5703 { 5704 struct bge_softc * const sc = ifp->if_softc; 5705 struct mii_data * const mii = &sc->bge_mii; 5706 struct ifmedia * const ifm = &sc->bge_ifmedia; 5707 int rc; 5708 5709 /* If this is a 1000baseX NIC, enable the TBI port. */ 5710 if (sc->bge_flags & BGEF_FIBER_TBI) { 5711 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5712 return EINVAL; 5713 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5714 case IFM_AUTO: 5715 /* 5716 * The BCM5704 ASIC appears to have a special 5717 * mechanism for programming the autoneg 5718 * advertisement registers in TBI mode. 5719 */ 5720 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5721 uint32_t sgdig; 5722 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5723 if (sgdig & BGE_SGDIGSTS_DONE) { 5724 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5725 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5726 sgdig |= BGE_SGDIGCFG_AUTO | 5727 BGE_SGDIGCFG_PAUSE_CAP | 5728 BGE_SGDIGCFG_ASYM_PAUSE; 5729 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5730 sgdig | BGE_SGDIGCFG_SEND); 5731 DELAY(5); 5732 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5733 sgdig); 5734 } 5735 } 5736 break; 5737 case IFM_1000_SX: 5738 if ((ifm->ifm_media & IFM_FDX) != 0) { 5739 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5740 BGE_MACMODE_HALF_DUPLEX); 5741 } else { 5742 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5743 BGE_MACMODE_HALF_DUPLEX); 5744 } 5745 DELAY(40); 5746 break; 5747 default: 5748 return EINVAL; 5749 } 5750 /* XXX 802.3x flow control for 1000BASE-SX */ 5751 return 0; 5752 } 5753 5754 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5755 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5756 uint32_t reg; 5757 5758 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5759 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5760 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5761 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5762 } 5763 } 5764 5765 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5766 if ((rc = mii_mediachg(mii)) == ENXIO) 5767 return 0; 5768 5769 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5770 uint32_t reg; 5771 5772 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5773 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5774 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5775 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5776 delay(40); 5777 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5778 } 5779 } 5780 5781 /* 5782 * Force an interrupt so that we will call bge_link_upd 5783 * if needed and clear any pending link state attention. 5784 * Without this we are not getting any further interrupts 5785 * for link state changes and thus will not UP the link and 5786 * not be able to send in bge_start. The only way to get 5787 * things working was to receive a packet and get a RX intr. 5788 */ 5789 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5790 sc->bge_flags & BGEF_IS_5788) 5791 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5792 else 5793 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5794 5795 return rc; 5796 } 5797 5798 /* 5799 * Report current media status. 5800 */ 5801 static void 5802 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5803 { 5804 struct bge_softc * const sc = ifp->if_softc; 5805 struct mii_data * const mii = &sc->bge_mii; 5806 5807 if (sc->bge_flags & BGEF_FIBER_TBI) { 5808 ifmr->ifm_status = IFM_AVALID; 5809 ifmr->ifm_active = IFM_ETHER; 5810 if (CSR_READ_4(sc, BGE_MAC_STS) & 5811 BGE_MACSTAT_TBI_PCS_SYNCHED) 5812 ifmr->ifm_status |= IFM_ACTIVE; 5813 ifmr->ifm_active |= IFM_1000_SX; 5814 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5815 ifmr->ifm_active |= IFM_HDX; 5816 else 5817 ifmr->ifm_active |= IFM_FDX; 5818 return; 5819 } 5820 5821 mii_pollstat(mii); 5822 ifmr->ifm_status = mii->mii_media_status; 5823 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5824 sc->bge_flowflags; 5825 } 5826 5827 static int 5828 bge_ifflags_cb(struct ethercom *ec) 5829 { 5830 struct ifnet * const ifp = &ec->ec_if; 5831 struct bge_softc * const sc = ifp->if_softc; 5832 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5833 5834 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 5835 return ENETRESET; 5836 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5837 return 0; 5838 5839 if ((ifp->if_flags & IFF_PROMISC) == 0) 5840 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5841 else 5842 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5843 5844 bge_setmulti(sc); 5845 5846 sc->bge_if_flags = ifp->if_flags; 5847 return 0; 5848 } 5849 5850 static int 5851 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5852 { 5853 struct bge_softc * const sc = ifp->if_softc; 5854 struct ifreq * const ifr = (struct ifreq *) data; 5855 int s, error = 0; 5856 struct mii_data *mii; 5857 5858 s = splnet(); 5859 5860 switch (command) { 5861 case SIOCSIFMEDIA: 5862 /* XXX Flow control is not supported for 1000BASE-SX */ 5863 if (sc->bge_flags & BGEF_FIBER_TBI) { 5864 ifr->ifr_media &= ~IFM_ETH_FMASK; 5865 sc->bge_flowflags = 0; 5866 } 5867 5868 /* Flow control requires full-duplex mode. */ 5869 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5870 (ifr->ifr_media & IFM_FDX) == 0) { 5871 ifr->ifr_media &= ~IFM_ETH_FMASK; 5872 } 5873 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5874 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5875 /* We can do both TXPAUSE and RXPAUSE. */ 5876 ifr->ifr_media |= 5877 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5878 } 5879 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5880 } 5881 5882 if (sc->bge_flags & BGEF_FIBER_TBI) { 5883 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5884 command); 5885 } else { 5886 mii = &sc->bge_mii; 5887 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5888 command); 5889 } 5890 break; 5891 default: 5892 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5893 break; 5894 5895 error = 0; 5896 5897 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5898 ; 5899 else if (ifp->if_flags & IFF_RUNNING) 5900 bge_setmulti(sc); 5901 break; 5902 } 5903 5904 splx(s); 5905 5906 return error; 5907 } 5908 5909 static void 5910 bge_watchdog(struct ifnet *ifp) 5911 { 5912 struct bge_softc * const sc = ifp->if_softc; 5913 uint32_t status; 5914 5915 /* If pause frames are active then don't reset the hardware. */ 5916 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5917 status = CSR_READ_4(sc, BGE_RX_STS); 5918 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5919 /* 5920 * If link partner has us in XOFF state then wait for 5921 * the condition to clear. 5922 */ 5923 CSR_WRITE_4(sc, BGE_RX_STS, status); 5924 ifp->if_timer = 5; 5925 return; 5926 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5927 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5928 /* 5929 * If link partner has us in XOFF state then wait for 5930 * the condition to clear. 5931 */ 5932 CSR_WRITE_4(sc, BGE_RX_STS, status); 5933 ifp->if_timer = 5; 5934 return; 5935 } 5936 /* 5937 * Any other condition is unexpected and the controller 5938 * should be reset. 5939 */ 5940 } 5941 5942 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5943 5944 ifp->if_flags &= ~IFF_RUNNING; 5945 bge_init(ifp); 5946 5947 if_statinc(ifp, if_oerrors); 5948 } 5949 5950 static void 5951 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5952 { 5953 int i; 5954 5955 BGE_CLRBIT_FLUSH(sc, reg, bit); 5956 5957 for (i = 0; i < 1000; i++) { 5958 delay(100); 5959 if ((CSR_READ_4(sc, reg) & bit) == 0) 5960 return; 5961 } 5962 5963 /* 5964 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5965 * on some environment (and once after boot?) 5966 */ 5967 if (reg != BGE_SRS_MODE) 5968 aprint_error_dev(sc->bge_dev, 5969 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5970 (u_long)reg, bit); 5971 } 5972 5973 /* 5974 * Stop the adapter and free any mbufs allocated to the 5975 * RX and TX lists. 5976 */ 5977 static void 5978 bge_stop(struct ifnet *ifp, int disable) 5979 { 5980 struct bge_softc * const sc = ifp->if_softc; 5981 5982 if (disable) { 5983 sc->bge_detaching = 1; 5984 callout_halt(&sc->bge_timeout, NULL); 5985 } else 5986 callout_stop(&sc->bge_timeout); 5987 5988 /* Disable host interrupts. */ 5989 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5990 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5991 5992 /* 5993 * Tell firmware we're shutting down. 5994 */ 5995 bge_stop_fw(sc); 5996 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5997 5998 /* 5999 * Disable all of the receiver blocks. 6000 */ 6001 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6002 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6003 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6004 if (BGE_IS_5700_FAMILY(sc)) 6005 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6006 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6007 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6008 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6009 6010 /* 6011 * Disable all of the transmit blocks. 6012 */ 6013 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6014 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6015 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6016 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6017 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6018 if (BGE_IS_5700_FAMILY(sc)) 6019 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6020 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6021 6022 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6023 delay(40); 6024 6025 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6026 6027 /* 6028 * Shut down all of the memory managers and related 6029 * state machines. 6030 */ 6031 /* 5718 step 5a,5b */ 6032 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6033 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6034 if (BGE_IS_5700_FAMILY(sc)) 6035 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6036 6037 /* 5718 step 5c,5d */ 6038 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6039 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6040 6041 if (BGE_IS_5700_FAMILY(sc)) { 6042 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6043 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6044 } 6045 6046 bge_reset(sc); 6047 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6048 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6049 6050 /* 6051 * Keep the ASF firmware running if up. 6052 */ 6053 if (sc->bge_asf_mode & ASF_STACKUP) 6054 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6055 else 6056 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6057 6058 /* Free the RX lists. */ 6059 bge_free_rx_ring_std(sc, disable); 6060 6061 /* Free jumbo RX list. */ 6062 if (BGE_IS_JUMBO_CAPABLE(sc)) 6063 bge_free_rx_ring_jumbo(sc); 6064 6065 /* Free TX buffers. */ 6066 bge_free_tx_ring(sc, disable); 6067 6068 /* 6069 * Isolate/power down the PHY. 6070 */ 6071 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6072 mii_down(&sc->bge_mii); 6073 6074 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6075 6076 /* Clear MAC's link state (PHY may still have link UP). */ 6077 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6078 6079 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6080 } 6081 6082 static void 6083 bge_link_upd(struct bge_softc *sc) 6084 { 6085 struct ifnet * const ifp = &sc->ethercom.ec_if; 6086 struct mii_data * const mii = &sc->bge_mii; 6087 uint32_t status; 6088 uint16_t phyval; 6089 int link; 6090 6091 /* Clear 'pending link event' flag */ 6092 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6093 6094 /* 6095 * Process link state changes. 6096 * Grrr. The link status word in the status block does 6097 * not work correctly on the BCM5700 rev AX and BX chips, 6098 * according to all available information. Hence, we have 6099 * to enable MII interrupts in order to properly obtain 6100 * async link changes. Unfortunately, this also means that 6101 * we have to read the MAC status register to detect link 6102 * changes, thereby adding an additional register access to 6103 * the interrupt handler. 6104 */ 6105 6106 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6107 status = CSR_READ_4(sc, BGE_MAC_STS); 6108 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6109 mii_pollstat(mii); 6110 6111 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6112 mii->mii_media_status & IFM_ACTIVE && 6113 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6114 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6115 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6116 (!(mii->mii_media_status & IFM_ACTIVE) || 6117 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6118 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6119 6120 /* Clear the interrupt */ 6121 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6122 BGE_EVTENB_MI_INTERRUPT); 6123 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6124 BRGPHY_MII_ISR, &phyval); 6125 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6126 BRGPHY_MII_IMR, BRGPHY_INTRS); 6127 } 6128 return; 6129 } 6130 6131 if (sc->bge_flags & BGEF_FIBER_TBI) { 6132 status = CSR_READ_4(sc, BGE_MAC_STS); 6133 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6134 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6135 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6136 if (BGE_ASICREV(sc->bge_chipid) 6137 == BGE_ASICREV_BCM5704) { 6138 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6139 BGE_MACMODE_TBI_SEND_CFGS); 6140 DELAY(40); 6141 } 6142 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6143 if_link_state_change(ifp, LINK_STATE_UP); 6144 } 6145 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6146 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6147 if_link_state_change(ifp, LINK_STATE_DOWN); 6148 } 6149 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6150 /* 6151 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6152 * bit in status word always set. Workaround this bug by 6153 * reading PHY link status directly. 6154 */ 6155 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6156 BGE_STS_LINK : 0; 6157 6158 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6159 mii_pollstat(mii); 6160 6161 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6162 mii->mii_media_status & IFM_ACTIVE && 6163 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6164 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6165 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6166 (!(mii->mii_media_status & IFM_ACTIVE) || 6167 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6168 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6169 } 6170 } else { 6171 /* 6172 * For controllers that call mii_tick, we have to poll 6173 * link status. 6174 */ 6175 mii_pollstat(mii); 6176 } 6177 6178 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6179 uint32_t reg, scale; 6180 6181 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6182 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6183 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6184 scale = 65; 6185 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6186 scale = 6; 6187 else 6188 scale = 12; 6189 6190 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6191 ~BGE_MISCCFG_TIMER_PRESCALER; 6192 reg |= scale << 1; 6193 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6194 } 6195 /* Clear the attention */ 6196 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6197 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6198 BGE_MACSTAT_LINK_CHANGED); 6199 } 6200 6201 static int 6202 bge_sysctl_verify(SYSCTLFN_ARGS) 6203 { 6204 int error, t; 6205 struct sysctlnode node; 6206 6207 node = *rnode; 6208 t = *(int*)rnode->sysctl_data; 6209 node.sysctl_data = &t; 6210 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6211 if (error || newp == NULL) 6212 return error; 6213 6214 #if 0 6215 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6216 node.sysctl_num, rnode->sysctl_num)); 6217 #endif 6218 6219 if (node.sysctl_num == bge_rxthresh_nodenum) { 6220 if (t < 0 || t >= NBGE_RX_THRESH) 6221 return EINVAL; 6222 bge_update_all_threshes(t); 6223 } else 6224 return EINVAL; 6225 6226 *(int*)rnode->sysctl_data = t; 6227 6228 return 0; 6229 } 6230 6231 /* 6232 * Set up sysctl(3) MIB, hw.bge.*. 6233 */ 6234 static void 6235 bge_sysctl_init(struct bge_softc *sc) 6236 { 6237 int rc, bge_root_num; 6238 const struct sysctlnode *node; 6239 6240 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6241 0, CTLTYPE_NODE, "bge", 6242 SYSCTL_DESCR("BGE interface controls"), 6243 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6244 goto out; 6245 } 6246 6247 bge_root_num = node->sysctl_num; 6248 6249 /* BGE Rx interrupt mitigation level */ 6250 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6251 CTLFLAG_READWRITE, 6252 CTLTYPE_INT, "rx_lvl", 6253 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6254 bge_sysctl_verify, 0, 6255 &bge_rx_thresh_lvl, 6256 0, CTL_HW, bge_root_num, CTL_CREATE, 6257 CTL_EOL)) != 0) { 6258 goto out; 6259 } 6260 6261 bge_rxthresh_nodenum = node->sysctl_num; 6262 6263 return; 6264 6265 out: 6266 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6267 } 6268 6269 #ifdef BGE_DEBUG 6270 void 6271 bge_debug_info(struct bge_softc *sc) 6272 { 6273 6274 printf("Hardware Flags:\n"); 6275 if (BGE_IS_57765_PLUS(sc)) 6276 printf(" - 57765 Plus\n"); 6277 if (BGE_IS_5717_PLUS(sc)) 6278 printf(" - 5717 Plus\n"); 6279 if (BGE_IS_5755_PLUS(sc)) 6280 printf(" - 5755 Plus\n"); 6281 if (BGE_IS_575X_PLUS(sc)) 6282 printf(" - 575X Plus\n"); 6283 if (BGE_IS_5705_PLUS(sc)) 6284 printf(" - 5705 Plus\n"); 6285 if (BGE_IS_5714_FAMILY(sc)) 6286 printf(" - 5714 Family\n"); 6287 if (BGE_IS_5700_FAMILY(sc)) 6288 printf(" - 5700 Family\n"); 6289 if (sc->bge_flags & BGEF_IS_5788) 6290 printf(" - 5788\n"); 6291 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6292 printf(" - Supports Jumbo Frames\n"); 6293 if (sc->bge_flags & BGEF_NO_EEPROM) 6294 printf(" - No EEPROM\n"); 6295 if (sc->bge_flags & BGEF_PCIX) 6296 printf(" - PCI-X Bus\n"); 6297 if (sc->bge_flags & BGEF_PCIE) 6298 printf(" - PCI Express Bus\n"); 6299 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6300 printf(" - RX Alignment Bug\n"); 6301 if (sc->bge_flags & BGEF_APE) 6302 printf(" - APE\n"); 6303 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6304 printf(" - CPMU\n"); 6305 if (sc->bge_flags & BGEF_TSO) 6306 printf(" - TSO\n"); 6307 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6308 printf(" - TAGGED_STATUS\n"); 6309 6310 /* PHY related */ 6311 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6312 printf(" - No 3 LEDs\n"); 6313 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6314 printf(" - CRC bug\n"); 6315 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6316 printf(" - ADC bug\n"); 6317 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6318 printf(" - 5704 A0 bug\n"); 6319 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6320 printf(" - jitter bug\n"); 6321 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6322 printf(" - BER bug\n"); 6323 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6324 printf(" - adjust trim\n"); 6325 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6326 printf(" - no wirespeed\n"); 6327 6328 /* ASF related */ 6329 if (sc->bge_asf_mode & ASF_ENABLE) 6330 printf(" - ASF enable\n"); 6331 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6332 printf(" - ASF new handshake\n"); 6333 if (sc->bge_asf_mode & ASF_STACKUP) 6334 printf(" - ASF stackup\n"); 6335 } 6336 #endif /* BGE_DEBUG */ 6337 6338 static int 6339 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6340 { 6341 prop_dictionary_t dict; 6342 prop_data_t ea; 6343 6344 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6345 return 1; 6346 6347 dict = device_properties(sc->bge_dev); 6348 ea = prop_dictionary_get(dict, "mac-address"); 6349 if (ea != NULL) { 6350 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6351 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6352 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6353 return 0; 6354 } 6355 6356 return 1; 6357 } 6358 6359 static int 6360 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6361 { 6362 uint32_t mac_addr; 6363 6364 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6365 if ((mac_addr >> 16) == 0x484b) { 6366 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6367 ether_addr[1] = (uint8_t)mac_addr; 6368 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6369 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6370 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6371 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6372 ether_addr[5] = (uint8_t)mac_addr; 6373 return 0; 6374 } 6375 return 1; 6376 } 6377 6378 static int 6379 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6380 { 6381 int mac_offset = BGE_EE_MAC_OFFSET; 6382 6383 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6384 mac_offset = BGE_EE_MAC_OFFSET_5906; 6385 6386 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6387 ETHER_ADDR_LEN)); 6388 } 6389 6390 static int 6391 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6392 { 6393 6394 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6395 return 1; 6396 6397 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6398 ETHER_ADDR_LEN)); 6399 } 6400 6401 static int 6402 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6403 { 6404 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6405 /* NOTE: Order is critical */ 6406 bge_get_eaddr_fw, 6407 bge_get_eaddr_mem, 6408 bge_get_eaddr_nvram, 6409 bge_get_eaddr_eeprom, 6410 NULL 6411 }; 6412 const bge_eaddr_fcn_t *func; 6413 6414 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6415 if ((*func)(sc, eaddr) == 0) 6416 break; 6417 } 6418 return (*func == NULL ? ENXIO : 0); 6419 } 6420
Indexes created Fri Sep 26 08:10:20 GMT 2025