if_bge.c revision 1.367
1 /* $NetBSD: if_bge.c,v 1.367 2022/07/26 14:53:12 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.367 2022/07/26 14:53:12 skrll Exp $"); 83 84 #include <sys/param.h> 85 86 #include <sys/callout.h> 87 #include <sys/device.h> 88 #include <sys/kernel.h> 89 #include <sys/kmem.h> 90 #include <sys/mbuf.h> 91 #include <sys/rndsource.h> 92 #include <sys/socket.h> 93 #include <sys/sockio.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 #include <net/bpf.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 #include <dev/mii/miidevs.h> 123 #include <dev/mii/brgphyreg.h> 124 125 #include <dev/pci/if_bgereg.h> 126 #include <dev/pci/if_bgevar.h> 127 128 #include <prop/proplib.h> 129 130 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 131 132 133 /* 134 * Tunable thresholds for rx-side bge interrupt mitigation. 135 */ 136 137 /* 138 * The pairs of values below were obtained from empirical measurement 139 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 140 * interrupt for every N packets received, where N is, approximately, 141 * the second value (rx_max_bds) in each pair. The values are chosen 142 * such that moving from one pair to the succeeding pair was observed 143 * to roughly halve interrupt rate under sustained input packet load. 144 * The values were empirically chosen to avoid overflowing internal 145 * limits on the bcm5700: increasing rx_ticks much beyond 600 146 * results in internal wrapping and higher interrupt rates. 147 * The limit of 46 frames was chosen to match NFS workloads. 148 * 149 * These values also work well on bcm5701, bcm5704C, and (less 150 * tested) bcm5703. On other chipsets, (including the Altima chip 151 * family), the larger values may overflow internal chip limits, 152 * leading to increasing interrupt rates rather than lower interrupt 153 * rates. 154 * 155 * Applications using heavy interrupt mitigation (interrupting every 156 * 32 or 46 frames) in both directions may need to increase the TCP 157 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 158 * full link bandwidth, due to ACKs and window updates lingering 159 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 160 */ 161 static const struct bge_load_rx_thresh { 162 int rx_ticks; 163 int rx_max_bds; } 164 bge_rx_threshes[] = { 165 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 166 { 32, 2 }, 167 { 50, 4 }, 168 { 100, 8 }, 169 { 192, 16 }, 170 { 416, 32 }, 171 { 598, 46 } 172 }; 173 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 174 175 /* XXX patchable; should be sysctl'able */ 176 static int bge_auto_thresh = 1; 177 static int bge_rx_thresh_lvl; 178 179 static int bge_rxthresh_nodenum; 180 181 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 182 183 static uint32_t bge_chipid(const struct pci_attach_args *); 184 static int bge_can_use_msi(struct bge_softc *); 185 static int bge_probe(device_t, cfdata_t, void *); 186 static void bge_attach(device_t, device_t, void *); 187 static int bge_detach(device_t, int); 188 static void bge_release_resources(struct bge_softc *); 189 190 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 191 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 195 196 static void bge_txeof(struct bge_softc *); 197 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 198 static void bge_rxeof(struct bge_softc *); 199 200 static void bge_asf_driver_up (struct bge_softc *); 201 static void bge_tick(void *); 202 static void bge_stats_update(struct bge_softc *); 203 static void bge_stats_update_regs(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ifflags_cb(struct ethercom *); 209 static int bge_ioctl(struct ifnet *, u_long, void *); 210 static int bge_init(struct ifnet *); 211 static void bge_stop(struct ifnet *, int); 212 static void bge_watchdog(struct ifnet *); 213 static int bge_ifmedia_upd(struct ifnet *); 214 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 215 216 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 217 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 218 219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 221 static void bge_setmulti(struct bge_softc *); 222 223 static void bge_handle_events(struct bge_softc *); 224 static int bge_alloc_jumbo_mem(struct bge_softc *); 225 #if 0 /* XXX */ 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 #endif 228 static void *bge_jalloc(struct bge_softc *); 229 static void bge_jfree(struct mbuf *, void *, size_t, void *); 230 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 231 bus_dmamap_t); 232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 233 static int bge_init_rx_ring_std(struct bge_softc *); 234 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 235 static int bge_init_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_rx_ring_jumbo(struct bge_softc *); 237 static void bge_free_tx_ring(struct bge_softc *m, bool); 238 static int bge_init_tx_ring(struct bge_softc *); 239 240 static int bge_chipinit(struct bge_softc *); 241 static int bge_blockinit(struct bge_softc *); 242 static int bge_phy_addr(struct bge_softc *); 243 static uint32_t bge_readmem_ind(struct bge_softc *, int); 244 static void bge_writemem_ind(struct bge_softc *, int, int); 245 static void bge_writembx(struct bge_softc *, int, int); 246 static void bge_writembx_flush(struct bge_softc *, int, int); 247 static void bge_writemem_direct(struct bge_softc *, int, int); 248 static void bge_writereg_ind(struct bge_softc *, int, int); 249 static void bge_set_max_readrq(struct bge_softc *); 250 251 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 252 static int bge_miibus_writereg(device_t, int, int, uint16_t); 253 static void bge_miibus_statchg(struct ifnet *); 254 255 #define BGE_RESET_SHUTDOWN 0 256 #define BGE_RESET_START 1 257 #define BGE_RESET_SUSPEND 2 258 static void bge_sig_post_reset(struct bge_softc *, int); 259 static void bge_sig_legacy(struct bge_softc *, int); 260 static void bge_sig_pre_reset(struct bge_softc *, int); 261 static void bge_wait_for_event_ack(struct bge_softc *); 262 static void bge_stop_fw(struct bge_softc *); 263 static int bge_reset(struct bge_softc *); 264 static void bge_link_upd(struct bge_softc *); 265 static void bge_sysctl_init(struct bge_softc *); 266 static int bge_sysctl_verify(SYSCTLFN_PROTO); 267 268 static void bge_ape_lock_init(struct bge_softc *); 269 static void bge_ape_read_fw_ver(struct bge_softc *); 270 static int bge_ape_lock(struct bge_softc *, int); 271 static void bge_ape_unlock(struct bge_softc *, int); 272 static void bge_ape_send_event(struct bge_softc *, uint32_t); 273 static void bge_ape_driver_state_change(struct bge_softc *, int); 274 275 #ifdef BGE_DEBUG 276 #define DPRINTF(x) if (bgedebug) printf x 277 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 278 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 279 int bgedebug = 0; 280 int bge_tso_debug = 0; 281 void bge_debug_info(struct bge_softc *); 282 #else 283 #define DPRINTF(x) 284 #define DPRINTFN(n, x) 285 #define BGE_TSO_PRINTF(x) 286 #endif 287 288 #ifdef BGE_EVENT_COUNTERS 289 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 290 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 291 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 292 #else 293 #define BGE_EVCNT_INCR(ev) /* nothing */ 294 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 295 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 296 #endif 297 298 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 299 /* 300 * The BCM5700 documentation seems to indicate that the hardware still has the 301 * Alteon vendor ID burned into it, though it should always be overridden by 302 * the value in the EEPROM. We'll check for it anyway. 303 */ 304 static const struct bge_product { 305 pci_vendor_id_t bp_vendor; 306 pci_product_id_t bp_product; 307 const char *bp_name; 308 } bge_products[] = { 309 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 310 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 311 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 312 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 313 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 314 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 315 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 319 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 320 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 323 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 349 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 354 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 359 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 363 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 364 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 367 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 368 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 370 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 371 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 372 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 373 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 375 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 376 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 377 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 379 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 380 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 381 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 382 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 383 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 384 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 399 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 400 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 401 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 402 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 403 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 404 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 405 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 406 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 407 { 0, 0, NULL }, 408 }; 409 410 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 411 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 412 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 413 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 414 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 415 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 416 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 417 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 418 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 419 420 static const struct bge_revision { 421 uint32_t br_chipid; 422 const char *br_name; 423 } bge_revisions[] = { 424 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 425 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 426 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 427 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 428 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 429 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 430 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 431 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 432 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 433 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 434 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 435 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 436 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 437 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 438 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 439 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 440 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 441 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 442 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 443 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 444 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 445 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 446 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 447 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 448 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 449 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 450 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 451 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 452 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 453 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 454 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 455 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 456 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 457 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 458 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 459 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 460 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 461 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 462 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 463 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 464 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 465 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 466 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 467 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 468 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 469 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 470 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 471 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 472 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 473 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 474 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 475 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 476 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 477 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 478 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 479 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 480 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 481 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 482 /* 5754 and 5787 share the same ASIC ID */ 483 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 484 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 485 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 486 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 487 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 488 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 489 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 490 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 491 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 492 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 493 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 494 495 { 0, NULL } 496 }; 497 498 /* 499 * Some defaults for major revisions, so that newer steppings 500 * that we don't know about have a shot at working. 501 */ 502 static const struct bge_revision bge_majorrevs[] = { 503 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 504 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 505 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 506 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 507 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 508 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 509 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 510 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 511 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 512 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 513 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 514 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 515 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 516 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 517 /* 5754 and 5787 share the same ASIC ID */ 518 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 519 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 520 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 521 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 522 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 523 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 524 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 525 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 526 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 527 528 { 0, NULL } 529 }; 530 531 static int bge_allow_asf = 1; 532 533 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 534 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 535 536 static uint32_t 537 bge_readmem_ind(struct bge_softc *sc, int off) 538 { 539 pcireg_t val; 540 541 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 542 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 543 return 0; 544 545 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 546 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 547 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 548 return val; 549 } 550 551 static void 552 bge_writemem_ind(struct bge_softc *sc, int off, int val) 553 { 554 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 556 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 557 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 558 } 559 560 /* 561 * PCI Express only 562 */ 563 static void 564 bge_set_max_readrq(struct bge_softc *sc) 565 { 566 pcireg_t val; 567 568 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 569 + PCIE_DCSR); 570 val &= ~PCIE_DCSR_MAX_READ_REQ; 571 switch (sc->bge_expmrq) { 572 case 2048: 573 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 574 break; 575 case 4096: 576 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 577 break; 578 default: 579 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 580 break; 581 } 582 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 583 + PCIE_DCSR, val); 584 } 585 586 #ifdef notdef 587 static uint32_t 588 bge_readreg_ind(struct bge_softc *sc, int off) 589 { 590 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 591 return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA); 592 } 593 #endif 594 595 static void 596 bge_writereg_ind(struct bge_softc *sc, int off, int val) 597 { 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 599 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 600 } 601 602 static void 603 bge_writemem_direct(struct bge_softc *sc, int off, int val) 604 { 605 CSR_WRITE_4(sc, off, val); 606 } 607 608 static void 609 bge_writembx(struct bge_softc *sc, int off, int val) 610 { 611 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 612 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 613 614 CSR_WRITE_4(sc, off, val); 615 } 616 617 static void 618 bge_writembx_flush(struct bge_softc *sc, int off, int val) 619 { 620 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 621 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 622 623 CSR_WRITE_4_FLUSH(sc, off, val); 624 } 625 626 /* 627 * Clear all stale locks and select the lock for this driver instance. 628 */ 629 void 630 bge_ape_lock_init(struct bge_softc *sc) 631 { 632 struct pci_attach_args *pa = &(sc->bge_pa); 633 uint32_t bit, regbase; 634 int i; 635 636 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 637 regbase = BGE_APE_LOCK_GRANT; 638 else 639 regbase = BGE_APE_PER_LOCK_GRANT; 640 641 /* Clear any stale locks. */ 642 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 643 switch (i) { 644 case BGE_APE_LOCK_PHY0: 645 case BGE_APE_LOCK_PHY1: 646 case BGE_APE_LOCK_PHY2: 647 case BGE_APE_LOCK_PHY3: 648 bit = BGE_APE_LOCK_GRANT_DRIVER0; 649 break; 650 default: 651 if (pa->pa_function == 0) 652 bit = BGE_APE_LOCK_GRANT_DRIVER0; 653 else 654 bit = (1 << pa->pa_function); 655 } 656 APE_WRITE_4(sc, regbase + 4 * i, bit); 657 } 658 659 /* Select the PHY lock based on the device's function number. */ 660 switch (pa->pa_function) { 661 case 0: 662 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 663 break; 664 case 1: 665 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 666 break; 667 case 2: 668 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 669 break; 670 case 3: 671 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 672 break; 673 default: 674 printf("%s: PHY lock not supported on function\n", 675 device_xname(sc->bge_dev)); 676 break; 677 } 678 } 679 680 /* 681 * Check for APE firmware, set flags, and print version info. 682 */ 683 void 684 bge_ape_read_fw_ver(struct bge_softc *sc) 685 { 686 const char *fwtype; 687 uint32_t apedata, features; 688 689 /* Check for a valid APE signature in shared memory. */ 690 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 691 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 692 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 693 return; 694 } 695 696 /* Check if APE firmware is running. */ 697 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 698 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 699 printf("%s: APE signature found but FW status not ready! " 700 "0x%08x\n", device_xname(sc->bge_dev), apedata); 701 return; 702 } 703 704 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 705 706 /* Fetch the APE firwmare type and version. */ 707 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 708 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 709 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 710 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 711 fwtype = "NCSI"; 712 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 713 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 714 fwtype = "DASH"; 715 } else 716 fwtype = "UNKN"; 717 718 /* Print the APE firmware version. */ 719 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 720 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 721 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 722 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 723 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 724 } 725 726 int 727 bge_ape_lock(struct bge_softc *sc, int locknum) 728 { 729 struct pci_attach_args *pa = &(sc->bge_pa); 730 uint32_t bit, gnt, req, status; 731 int i, off; 732 733 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 734 return 0; 735 736 /* Lock request/grant registers have different bases. */ 737 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 738 req = BGE_APE_LOCK_REQ; 739 gnt = BGE_APE_LOCK_GRANT; 740 } else { 741 req = BGE_APE_PER_LOCK_REQ; 742 gnt = BGE_APE_PER_LOCK_GRANT; 743 } 744 745 off = 4 * locknum; 746 747 switch (locknum) { 748 case BGE_APE_LOCK_GPIO: 749 /* Lock required when using GPIO. */ 750 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 751 return 0; 752 if (pa->pa_function == 0) 753 bit = BGE_APE_LOCK_REQ_DRIVER0; 754 else 755 bit = (1 << pa->pa_function); 756 break; 757 case BGE_APE_LOCK_GRC: 758 /* Lock required to reset the device. */ 759 if (pa->pa_function == 0) 760 bit = BGE_APE_LOCK_REQ_DRIVER0; 761 else 762 bit = (1 << pa->pa_function); 763 break; 764 case BGE_APE_LOCK_MEM: 765 /* Lock required when accessing certain APE memory. */ 766 if (pa->pa_function == 0) 767 bit = BGE_APE_LOCK_REQ_DRIVER0; 768 else 769 bit = (1 << pa->pa_function); 770 break; 771 case BGE_APE_LOCK_PHY0: 772 case BGE_APE_LOCK_PHY1: 773 case BGE_APE_LOCK_PHY2: 774 case BGE_APE_LOCK_PHY3: 775 /* Lock required when accessing PHYs. */ 776 bit = BGE_APE_LOCK_REQ_DRIVER0; 777 break; 778 default: 779 return EINVAL; 780 } 781 782 /* Request a lock. */ 783 APE_WRITE_4_FLUSH(sc, req + off, bit); 784 785 /* Wait up to 1 second to acquire lock. */ 786 for (i = 0; i < 20000; i++) { 787 status = APE_READ_4(sc, gnt + off); 788 if (status == bit) 789 break; 790 DELAY(50); 791 } 792 793 /* Handle any errors. */ 794 if (status != bit) { 795 printf("%s: APE lock %d request failed! " 796 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 797 device_xname(sc->bge_dev), 798 locknum, req + off, bit & 0xFFFF, gnt + off, 799 status & 0xFFFF); 800 /* Revoke the lock request. */ 801 APE_WRITE_4(sc, gnt + off, bit); 802 return EBUSY; 803 } 804 805 return 0; 806 } 807 808 void 809 bge_ape_unlock(struct bge_softc *sc, int locknum) 810 { 811 struct pci_attach_args *pa = &(sc->bge_pa); 812 uint32_t bit, gnt; 813 int off; 814 815 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 816 return; 817 818 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 819 gnt = BGE_APE_LOCK_GRANT; 820 else 821 gnt = BGE_APE_PER_LOCK_GRANT; 822 823 off = 4 * locknum; 824 825 switch (locknum) { 826 case BGE_APE_LOCK_GPIO: 827 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 828 return; 829 if (pa->pa_function == 0) 830 bit = BGE_APE_LOCK_GRANT_DRIVER0; 831 else 832 bit = (1 << pa->pa_function); 833 break; 834 case BGE_APE_LOCK_GRC: 835 if (pa->pa_function == 0) 836 bit = BGE_APE_LOCK_GRANT_DRIVER0; 837 else 838 bit = (1 << pa->pa_function); 839 break; 840 case BGE_APE_LOCK_MEM: 841 if (pa->pa_function == 0) 842 bit = BGE_APE_LOCK_GRANT_DRIVER0; 843 else 844 bit = (1 << pa->pa_function); 845 break; 846 case BGE_APE_LOCK_PHY0: 847 case BGE_APE_LOCK_PHY1: 848 case BGE_APE_LOCK_PHY2: 849 case BGE_APE_LOCK_PHY3: 850 bit = BGE_APE_LOCK_GRANT_DRIVER0; 851 break; 852 default: 853 return; 854 } 855 856 /* Write and flush for consecutive bge_ape_lock() */ 857 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 858 } 859 860 /* 861 * Send an event to the APE firmware. 862 */ 863 void 864 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 865 { 866 uint32_t apedata; 867 int i; 868 869 /* NCSI does not support APE events. */ 870 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 871 return; 872 873 /* Wait up to 1ms for APE to service previous event. */ 874 for (i = 10; i > 0; i--) { 875 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 876 break; 877 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 878 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 879 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 880 BGE_APE_EVENT_STATUS_EVENT_PENDING); 881 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 882 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 883 break; 884 } 885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 886 DELAY(100); 887 } 888 if (i == 0) { 889 printf("%s: APE event 0x%08x send timed out\n", 890 device_xname(sc->bge_dev), event); 891 } 892 } 893 894 void 895 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 896 { 897 uint32_t apedata, event; 898 899 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 900 return; 901 902 switch (kind) { 903 case BGE_RESET_START: 904 /* If this is the first load, clear the load counter. */ 905 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 906 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 907 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 908 else { 909 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 910 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 911 } 912 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 913 BGE_APE_HOST_SEG_SIG_MAGIC); 914 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 915 BGE_APE_HOST_SEG_LEN_MAGIC); 916 917 /* Add some version info if bge(4) supports it. */ 918 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 919 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 920 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 921 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 922 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 923 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 924 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 925 BGE_APE_HOST_DRVR_STATE_START); 926 event = BGE_APE_EVENT_STATUS_STATE_START; 927 break; 928 case BGE_RESET_SHUTDOWN: 929 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 930 BGE_APE_HOST_DRVR_STATE_UNLOAD); 931 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 932 break; 933 case BGE_RESET_SUSPEND: 934 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 935 break; 936 default: 937 return; 938 } 939 940 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 941 BGE_APE_EVENT_STATUS_STATE_CHNGE); 942 } 943 944 static uint8_t 945 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 946 { 947 uint32_t access, byte = 0; 948 int i; 949 950 /* Lock. */ 951 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 952 for (i = 0; i < 8000; i++) { 953 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 954 break; 955 DELAY(20); 956 } 957 if (i == 8000) 958 return 1; 959 960 /* Enable access. */ 961 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 962 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 963 964 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 965 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 966 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 967 DELAY(10); 968 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 969 DELAY(10); 970 break; 971 } 972 } 973 974 if (i == BGE_TIMEOUT * 10) { 975 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 976 return 1; 977 } 978 979 /* Get result. */ 980 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 981 982 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 983 984 /* Disable access. */ 985 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 986 987 /* Unlock. */ 988 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 989 990 return 0; 991 } 992 993 /* 994 * Read a sequence of bytes from NVRAM. 995 */ 996 static int 997 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 998 { 999 int error = 0, i; 1000 uint8_t byte = 0; 1001 1002 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1003 return 1; 1004 1005 for (i = 0; i < cnt; i++) { 1006 error = bge_nvram_getbyte(sc, off + i, &byte); 1007 if (error) 1008 break; 1009 *(dest + i) = byte; 1010 } 1011 1012 return error ? 1 : 0; 1013 } 1014 1015 /* 1016 * Read a byte of data stored in the EEPROM at address 'addr.' The 1017 * BCM570x supports both the traditional bitbang interface and an 1018 * auto access interface for reading the EEPROM. We use the auto 1019 * access method. 1020 */ 1021 static uint8_t 1022 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1023 { 1024 int i; 1025 uint32_t byte = 0; 1026 1027 /* 1028 * Enable use of auto EEPROM access so we can avoid 1029 * having to use the bitbang method. 1030 */ 1031 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1032 1033 /* Reset the EEPROM, load the clock period. */ 1034 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1035 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1036 DELAY(20); 1037 1038 /* Issue the read EEPROM command. */ 1039 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1040 1041 /* Wait for completion */ 1042 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1043 DELAY(10); 1044 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1045 break; 1046 } 1047 1048 if (i == BGE_TIMEOUT * 10) { 1049 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1050 return 1; 1051 } 1052 1053 /* Get result. */ 1054 byte = CSR_READ_4(sc, BGE_EE_DATA); 1055 1056 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1057 1058 return 0; 1059 } 1060 1061 /* 1062 * Read a sequence of bytes from the EEPROM. 1063 */ 1064 static int 1065 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1066 { 1067 int error = 0, i; 1068 uint8_t byte = 0; 1069 char *dest = destv; 1070 1071 for (i = 0; i < cnt; i++) { 1072 error = bge_eeprom_getbyte(sc, off + i, &byte); 1073 if (error) 1074 break; 1075 *(dest + i) = byte; 1076 } 1077 1078 return error ? 1 : 0; 1079 } 1080 1081 static int 1082 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1083 { 1084 struct bge_softc * const sc = device_private(dev); 1085 uint32_t data; 1086 uint32_t autopoll; 1087 int rv = 0; 1088 int i; 1089 1090 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1091 return -1; 1092 1093 /* Reading with autopolling on may trigger PCI errors */ 1094 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1095 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1096 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1097 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1098 DELAY(80); 1099 } 1100 1101 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1102 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1103 1104 for (i = 0; i < BGE_TIMEOUT; i++) { 1105 delay(10); 1106 data = CSR_READ_4(sc, BGE_MI_COMM); 1107 if (!(data & BGE_MICOMM_BUSY)) { 1108 DELAY(5); 1109 data = CSR_READ_4(sc, BGE_MI_COMM); 1110 break; 1111 } 1112 } 1113 1114 if (i == BGE_TIMEOUT) { 1115 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1116 rv = ETIMEDOUT; 1117 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1118 /* XXX This error occurs on some devices while attaching. */ 1119 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1120 rv = EIO; 1121 } else 1122 *val = data & BGE_MICOMM_DATA; 1123 1124 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1125 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1126 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1127 DELAY(80); 1128 } 1129 1130 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1131 1132 return rv; 1133 } 1134 1135 static int 1136 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1137 { 1138 struct bge_softc * const sc = device_private(dev); 1139 uint32_t data, autopoll; 1140 int rv = 0; 1141 int i; 1142 1143 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1144 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1145 return 0; 1146 1147 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1148 return -1; 1149 1150 /* Reading with autopolling on may trigger PCI errors */ 1151 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1152 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1153 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1154 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1155 DELAY(80); 1156 } 1157 1158 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1159 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1160 1161 for (i = 0; i < BGE_TIMEOUT; i++) { 1162 delay(10); 1163 data = CSR_READ_4(sc, BGE_MI_COMM); 1164 if (!(data & BGE_MICOMM_BUSY)) { 1165 delay(5); 1166 data = CSR_READ_4(sc, BGE_MI_COMM); 1167 break; 1168 } 1169 } 1170 1171 if (i == BGE_TIMEOUT) { 1172 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1173 rv = ETIMEDOUT; 1174 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1175 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1176 rv = EIO; 1177 } 1178 1179 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1180 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1181 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1182 delay(80); 1183 } 1184 1185 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1186 1187 return rv; 1188 } 1189 1190 static void 1191 bge_miibus_statchg(struct ifnet *ifp) 1192 { 1193 struct bge_softc * const sc = ifp->if_softc; 1194 struct mii_data *mii = &sc->bge_mii; 1195 uint32_t mac_mode, rx_mode, tx_mode; 1196 1197 /* 1198 * Get flow control negotiation result. 1199 */ 1200 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1201 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1202 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1203 1204 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1205 mii->mii_media_status & IFM_ACTIVE && 1206 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1207 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1208 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1209 (!(mii->mii_media_status & IFM_ACTIVE) || 1210 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1211 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1212 1213 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1214 return; 1215 1216 /* Set the port mode (MII/GMII) to match the link speed. */ 1217 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1218 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1219 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1220 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1221 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1222 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1223 mac_mode |= BGE_PORTMODE_GMII; 1224 else 1225 mac_mode |= BGE_PORTMODE_MII; 1226 1227 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1228 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1229 if ((mii->mii_media_active & IFM_FDX) != 0) { 1230 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1231 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1232 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1233 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1234 } else 1235 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1236 1237 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1238 DELAY(40); 1239 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1240 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1241 } 1242 1243 /* 1244 * Update rx threshold levels to values in a particular slot 1245 * of the interrupt-mitigation table bge_rx_threshes. 1246 */ 1247 static void 1248 bge_set_thresh(struct ifnet *ifp, int lvl) 1249 { 1250 struct bge_softc * const sc = ifp->if_softc; 1251 int s; 1252 1253 /* 1254 * For now, just save the new Rx-intr thresholds and record 1255 * that a threshold update is pending. Updating the hardware 1256 * registers here (even at splhigh()) is observed to 1257 * occasionally cause glitches where Rx-interrupts are not 1258 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1259 */ 1260 s = splnet(); 1261 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1262 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1263 sc->bge_pending_rxintr_change = 1; 1264 splx(s); 1265 } 1266 1267 1268 /* 1269 * Update Rx thresholds of all bge devices 1270 */ 1271 static void 1272 bge_update_all_threshes(int lvl) 1273 { 1274 const char * const namebuf = "bge"; 1275 const size_t namelen = strlen(namebuf); 1276 struct ifnet *ifp; 1277 1278 if (lvl < 0) 1279 lvl = 0; 1280 else if (lvl >= NBGE_RX_THRESH) 1281 lvl = NBGE_RX_THRESH - 1; 1282 1283 /* 1284 * Now search all the interfaces for this name/number 1285 */ 1286 int s = pserialize_read_enter(); 1287 IFNET_READER_FOREACH(ifp) { 1288 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1289 continue; 1290 /* We got a match: update if doing auto-threshold-tuning */ 1291 if (bge_auto_thresh) 1292 bge_set_thresh(ifp, lvl); 1293 } 1294 pserialize_read_exit(s); 1295 } 1296 1297 /* 1298 * Handle events that have triggered interrupts. 1299 */ 1300 static void 1301 bge_handle_events(struct bge_softc *sc) 1302 { 1303 1304 return; 1305 } 1306 1307 /* 1308 * Memory management for jumbo frames. 1309 */ 1310 1311 static int 1312 bge_alloc_jumbo_mem(struct bge_softc *sc) 1313 { 1314 char *ptr, *kva; 1315 bus_dma_segment_t seg; 1316 int i, rseg, state, error; 1317 struct bge_jpool_entry *entry; 1318 1319 state = error = 0; 1320 1321 /* Grab a big chunk o' storage. */ 1322 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1323 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1324 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1325 return ENOBUFS; 1326 } 1327 1328 state = 1; 1329 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1330 BUS_DMA_NOWAIT)) { 1331 aprint_error_dev(sc->bge_dev, 1332 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1333 error = ENOBUFS; 1334 goto out; 1335 } 1336 1337 state = 2; 1338 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1339 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1340 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1341 error = ENOBUFS; 1342 goto out; 1343 } 1344 1345 state = 3; 1346 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1347 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1348 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1349 error = ENOBUFS; 1350 goto out; 1351 } 1352 1353 state = 4; 1354 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1355 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1356 1357 SLIST_INIT(&sc->bge_jfree_listhead); 1358 SLIST_INIT(&sc->bge_jinuse_listhead); 1359 1360 /* 1361 * Now divide it up into 9K pieces and save the addresses 1362 * in an array. 1363 */ 1364 ptr = sc->bge_cdata.bge_jumbo_buf; 1365 for (i = 0; i < BGE_JSLOTS; i++) { 1366 sc->bge_cdata.bge_jslots[i] = ptr; 1367 ptr += BGE_JLEN; 1368 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 1369 entry->slot = i; 1370 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1371 entry, jpool_entries); 1372 } 1373 out: 1374 if (error != 0) { 1375 switch (state) { 1376 case 4: 1377 bus_dmamap_unload(sc->bge_dmatag, 1378 sc->bge_cdata.bge_rx_jumbo_map); 1379 /* FALLTHROUGH */ 1380 case 3: 1381 bus_dmamap_destroy(sc->bge_dmatag, 1382 sc->bge_cdata.bge_rx_jumbo_map); 1383 /* FALLTHROUGH */ 1384 case 2: 1385 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1386 /* FALLTHROUGH */ 1387 case 1: 1388 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1389 break; 1390 default: 1391 break; 1392 } 1393 } 1394 1395 return error; 1396 } 1397 1398 /* 1399 * Allocate a jumbo buffer. 1400 */ 1401 static void * 1402 bge_jalloc(struct bge_softc *sc) 1403 { 1404 struct bge_jpool_entry *entry; 1405 1406 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1407 1408 if (entry == NULL) { 1409 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1410 return NULL; 1411 } 1412 1413 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1414 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1415 return sc->bge_cdata.bge_jslots[entry->slot]; 1416 } 1417 1418 /* 1419 * Release a jumbo buffer. 1420 */ 1421 static void 1422 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1423 { 1424 struct bge_jpool_entry *entry; 1425 struct bge_softc * const sc = arg; 1426 int i, s; 1427 1428 if (sc == NULL) 1429 panic("bge_jfree: can't find softc pointer!"); 1430 1431 /* calculate the slot this buffer belongs to */ 1432 1433 i = ((char *)buf 1434 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1435 1436 if ((i < 0) || (i >= BGE_JSLOTS)) 1437 panic("bge_jfree: asked to free buffer that we don't manage!"); 1438 1439 s = splvm(); 1440 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1441 if (entry == NULL) 1442 panic("bge_jfree: buffer not in use!"); 1443 entry->slot = i; 1444 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1445 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1446 1447 if (__predict_true(m != NULL)) 1448 pool_cache_put(mb_cache, m); 1449 splx(s); 1450 } 1451 1452 1453 /* 1454 * Initialize a standard receive ring descriptor. 1455 */ 1456 static int 1457 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1458 bus_dmamap_t dmamap) 1459 { 1460 struct mbuf *m_new = NULL; 1461 struct bge_rx_bd *r; 1462 int error; 1463 1464 if (dmamap == NULL) 1465 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1466 1467 if (dmamap == NULL) { 1468 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1469 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1470 if (error != 0) 1471 return error; 1472 } 1473 1474 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1475 1476 if (m == NULL) { 1477 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1478 if (m_new == NULL) 1479 return ENOBUFS; 1480 1481 MCLGET(m_new, M_DONTWAIT); 1482 if (!(m_new->m_flags & M_EXT)) { 1483 m_freem(m_new); 1484 return ENOBUFS; 1485 } 1486 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1487 1488 } else { 1489 m_new = m; 1490 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1491 m_new->m_data = m_new->m_ext.ext_buf; 1492 } 1493 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1494 m_adj(m_new, ETHER_ALIGN); 1495 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1496 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1497 m_freem(m_new); 1498 return ENOBUFS; 1499 } 1500 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1501 BUS_DMASYNC_PREREAD); 1502 1503 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1504 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1505 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1506 r->bge_flags = BGE_RXBDFLAG_END; 1507 r->bge_len = m_new->m_len; 1508 r->bge_idx = i; 1509 1510 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1511 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1512 i * sizeof(struct bge_rx_bd), 1513 sizeof(struct bge_rx_bd), 1514 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1515 1516 return 0; 1517 } 1518 1519 /* 1520 * Initialize a jumbo receive ring descriptor. This allocates 1521 * a jumbo buffer from the pool managed internally by the driver. 1522 */ 1523 static int 1524 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1525 { 1526 struct mbuf *m_new = NULL; 1527 struct bge_rx_bd *r; 1528 void *buf = NULL; 1529 1530 if (m == NULL) { 1531 1532 /* Allocate the mbuf. */ 1533 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1534 if (m_new == NULL) 1535 return ENOBUFS; 1536 1537 /* Allocate the jumbo buffer */ 1538 buf = bge_jalloc(sc); 1539 if (buf == NULL) { 1540 m_freem(m_new); 1541 aprint_error_dev(sc->bge_dev, 1542 "jumbo allocation failed -- packet dropped!\n"); 1543 return ENOBUFS; 1544 } 1545 1546 /* Attach the buffer to the mbuf. */ 1547 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1548 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1549 bge_jfree, sc); 1550 m_new->m_flags |= M_EXT_RW; 1551 } else { 1552 m_new = m; 1553 buf = m_new->m_data = m_new->m_ext.ext_buf; 1554 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1555 } 1556 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1557 m_adj(m_new, ETHER_ALIGN); 1558 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1559 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1560 BGE_JLEN, BUS_DMASYNC_PREREAD); 1561 /* Set up the descriptor. */ 1562 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1563 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1564 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1565 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1566 r->bge_len = m_new->m_len; 1567 r->bge_idx = i; 1568 1569 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1570 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1571 i * sizeof(struct bge_rx_bd), 1572 sizeof(struct bge_rx_bd), 1573 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1574 1575 return 0; 1576 } 1577 1578 /* 1579 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1580 * that's 1MB or memory, which is a lot. For now, we fill only the first 1581 * 256 ring entries and hope that our CPU is fast enough to keep up with 1582 * the NIC. 1583 */ 1584 static int 1585 bge_init_rx_ring_std(struct bge_softc *sc) 1586 { 1587 int i; 1588 1589 if (sc->bge_flags & BGEF_RXRING_VALID) 1590 return 0; 1591 1592 for (i = 0; i < BGE_SSLOTS; i++) { 1593 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1594 return ENOBUFS; 1595 } 1596 1597 sc->bge_std = i - 1; 1598 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1599 1600 sc->bge_flags |= BGEF_RXRING_VALID; 1601 1602 return 0; 1603 } 1604 1605 static void 1606 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1607 { 1608 int i; 1609 1610 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1611 return; 1612 1613 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1614 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1615 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1616 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1617 if (disable) { 1618 bus_dmamap_destroy(sc->bge_dmatag, 1619 sc->bge_cdata.bge_rx_std_map[i]); 1620 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1621 } 1622 } 1623 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1624 sizeof(struct bge_rx_bd)); 1625 } 1626 1627 sc->bge_flags &= ~BGEF_RXRING_VALID; 1628 } 1629 1630 static int 1631 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1632 { 1633 int i; 1634 volatile struct bge_rcb *rcb; 1635 1636 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1637 return 0; 1638 1639 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1640 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1641 return ENOBUFS; 1642 } 1643 1644 sc->bge_jumbo = i - 1; 1645 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1646 1647 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1648 rcb->bge_maxlen_flags = 0; 1649 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1650 1651 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1652 1653 return 0; 1654 } 1655 1656 static void 1657 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1658 { 1659 int i; 1660 1661 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1662 return; 1663 1664 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1665 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1666 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1667 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1668 } 1669 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1670 sizeof(struct bge_rx_bd)); 1671 } 1672 1673 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1674 } 1675 1676 static void 1677 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1678 { 1679 int i; 1680 struct txdmamap_pool_entry *dma; 1681 1682 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1683 return; 1684 1685 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1686 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1687 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1688 sc->bge_cdata.bge_tx_chain[i] = NULL; 1689 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1690 link); 1691 sc->txdma[i] = 0; 1692 } 1693 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1694 sizeof(struct bge_tx_bd)); 1695 } 1696 1697 if (disable) { 1698 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1699 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1700 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1701 if (sc->bge_dma64) { 1702 bus_dmamap_destroy(sc->bge_dmatag32, 1703 dma->dmamap32); 1704 } 1705 kmem_free(dma, sizeof(*dma)); 1706 } 1707 SLIST_INIT(&sc->txdma_list); 1708 } 1709 1710 sc->bge_flags &= ~BGEF_TXRING_VALID; 1711 } 1712 1713 static int 1714 bge_init_tx_ring(struct bge_softc *sc) 1715 { 1716 struct ifnet * const ifp = &sc->ethercom.ec_if; 1717 int i; 1718 bus_dmamap_t dmamap, dmamap32; 1719 bus_size_t maxsegsz; 1720 struct txdmamap_pool_entry *dma; 1721 1722 if (sc->bge_flags & BGEF_TXRING_VALID) 1723 return 0; 1724 1725 sc->bge_txcnt = 0; 1726 sc->bge_tx_saved_considx = 0; 1727 1728 /* Initialize transmit producer index for host-memory send ring. */ 1729 sc->bge_tx_prodidx = 0; 1730 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1731 /* 5700 b2 errata */ 1732 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1733 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1734 1735 /* NIC-memory send ring not used; initialize to zero. */ 1736 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1737 /* 5700 b2 errata */ 1738 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1739 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1740 1741 /* Limit DMA segment size for some chips */ 1742 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1743 (ifp->if_mtu <= ETHERMTU)) 1744 maxsegsz = 2048; 1745 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1746 maxsegsz = 4096; 1747 else 1748 maxsegsz = ETHER_MAX_LEN_JUMBO; 1749 1750 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1751 goto alloc_done; 1752 1753 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1754 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1755 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1756 &dmamap)) 1757 return ENOBUFS; 1758 if (dmamap == NULL) 1759 panic("dmamap NULL in bge_init_tx_ring"); 1760 if (sc->bge_dma64) { 1761 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1762 BGE_NTXSEG, maxsegsz, 0, 1763 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1764 &dmamap32)) { 1765 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1766 return ENOBUFS; 1767 } 1768 if (dmamap32 == NULL) 1769 panic("dmamap32 NULL in bge_init_tx_ring"); 1770 } else 1771 dmamap32 = dmamap; 1772 dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP); 1773 if (dma == NULL) { 1774 aprint_error_dev(sc->bge_dev, 1775 "can't alloc txdmamap_pool_entry\n"); 1776 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1777 if (sc->bge_dma64) 1778 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1779 return ENOMEM; 1780 } 1781 dma->dmamap = dmamap; 1782 dma->dmamap32 = dmamap32; 1783 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1784 } 1785 alloc_done: 1786 sc->bge_flags |= BGEF_TXRING_VALID; 1787 1788 return 0; 1789 } 1790 1791 static void 1792 bge_setmulti(struct bge_softc *sc) 1793 { 1794 struct ethercom * const ec = &sc->ethercom; 1795 struct ifnet * const ifp = &ec->ec_if; 1796 struct ether_multi *enm; 1797 struct ether_multistep step; 1798 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1799 uint32_t h; 1800 int i; 1801 1802 if (ifp->if_flags & IFF_PROMISC) 1803 goto allmulti; 1804 1805 /* Now program new ones. */ 1806 ETHER_LOCK(ec); 1807 ETHER_FIRST_MULTI(step, ec, enm); 1808 while (enm != NULL) { 1809 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1810 /* 1811 * We must listen to a range of multicast addresses. 1812 * For now, just accept all multicasts, rather than 1813 * trying to set only those filter bits needed to match 1814 * the range. (At this time, the only use of address 1815 * ranges is for IP multicast routing, for which the 1816 * range is big enough to require all bits set.) 1817 */ 1818 ETHER_UNLOCK(ec); 1819 goto allmulti; 1820 } 1821 1822 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1823 1824 /* Just want the 7 least-significant bits. */ 1825 h &= 0x7f; 1826 1827 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1828 ETHER_NEXT_MULTI(step, enm); 1829 } 1830 ETHER_UNLOCK(ec); 1831 1832 ifp->if_flags &= ~IFF_ALLMULTI; 1833 goto setit; 1834 1835 allmulti: 1836 ifp->if_flags |= IFF_ALLMULTI; 1837 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1838 1839 setit: 1840 for (i = 0; i < 4; i++) 1841 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1842 } 1843 1844 static void 1845 bge_sig_pre_reset(struct bge_softc *sc, int type) 1846 { 1847 1848 /* 1849 * Some chips don't like this so only do this if ASF is enabled 1850 */ 1851 if (sc->bge_asf_mode) 1852 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1853 1854 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1855 switch (type) { 1856 case BGE_RESET_START: 1857 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1858 BGE_FW_DRV_STATE_START); 1859 break; 1860 case BGE_RESET_SHUTDOWN: 1861 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1862 BGE_FW_DRV_STATE_UNLOAD); 1863 break; 1864 case BGE_RESET_SUSPEND: 1865 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1866 BGE_FW_DRV_STATE_SUSPEND); 1867 break; 1868 } 1869 } 1870 1871 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1872 bge_ape_driver_state_change(sc, type); 1873 } 1874 1875 static void 1876 bge_sig_post_reset(struct bge_softc *sc, int type) 1877 { 1878 1879 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1880 switch (type) { 1881 case BGE_RESET_START: 1882 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1883 BGE_FW_DRV_STATE_START_DONE); 1884 /* START DONE */ 1885 break; 1886 case BGE_RESET_SHUTDOWN: 1887 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1888 BGE_FW_DRV_STATE_UNLOAD_DONE); 1889 break; 1890 } 1891 } 1892 1893 if (type == BGE_RESET_SHUTDOWN) 1894 bge_ape_driver_state_change(sc, type); 1895 } 1896 1897 static void 1898 bge_sig_legacy(struct bge_softc *sc, int type) 1899 { 1900 1901 if (sc->bge_asf_mode) { 1902 switch (type) { 1903 case BGE_RESET_START: 1904 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1905 BGE_FW_DRV_STATE_START); 1906 break; 1907 case BGE_RESET_SHUTDOWN: 1908 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1909 BGE_FW_DRV_STATE_UNLOAD); 1910 break; 1911 } 1912 } 1913 } 1914 1915 static void 1916 bge_wait_for_event_ack(struct bge_softc *sc) 1917 { 1918 int i; 1919 1920 /* wait up to 2500usec */ 1921 for (i = 0; i < 250; i++) { 1922 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1923 BGE_RX_CPU_DRV_EVENT)) 1924 break; 1925 DELAY(10); 1926 } 1927 } 1928 1929 static void 1930 bge_stop_fw(struct bge_softc *sc) 1931 { 1932 1933 if (sc->bge_asf_mode) { 1934 bge_wait_for_event_ack(sc); 1935 1936 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1937 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1938 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1939 1940 bge_wait_for_event_ack(sc); 1941 } 1942 } 1943 1944 static int 1945 bge_poll_fw(struct bge_softc *sc) 1946 { 1947 uint32_t val; 1948 int i; 1949 1950 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1951 for (i = 0; i < BGE_TIMEOUT; i++) { 1952 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1953 if (val & BGE_VCPU_STATUS_INIT_DONE) 1954 break; 1955 DELAY(100); 1956 } 1957 if (i >= BGE_TIMEOUT) { 1958 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1959 return -1; 1960 } 1961 } else { 1962 /* 1963 * Poll the value location we just wrote until 1964 * we see the 1's complement of the magic number. 1965 * This indicates that the firmware initialization 1966 * is complete. 1967 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1968 */ 1969 for (i = 0; i < BGE_TIMEOUT; i++) { 1970 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1971 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1972 break; 1973 DELAY(10); 1974 } 1975 1976 if ((i >= BGE_TIMEOUT) 1977 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1978 aprint_error_dev(sc->bge_dev, 1979 "firmware handshake timed out, val = %x\n", val); 1980 return -1; 1981 } 1982 } 1983 1984 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 1985 /* tg3 says we have to wait extra time */ 1986 delay(10 * 1000); 1987 } 1988 1989 return 0; 1990 } 1991 1992 int 1993 bge_phy_addr(struct bge_softc *sc) 1994 { 1995 struct pci_attach_args *pa = &(sc->bge_pa); 1996 int phy_addr = 1; 1997 1998 /* 1999 * PHY address mapping for various devices. 2000 * 2001 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2002 * ---------+-------+-------+-------+-------+ 2003 * BCM57XX | 1 | X | X | X | 2004 * BCM5704 | 1 | X | 1 | X | 2005 * BCM5717 | 1 | 8 | 2 | 9 | 2006 * BCM5719 | 1 | 8 | 2 | 9 | 2007 * BCM5720 | 1 | 8 | 2 | 9 | 2008 * 2009 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2010 * ---------+-------+-------+-------+-------+ 2011 * BCM57XX | X | X | X | X | 2012 * BCM5704 | X | X | X | X | 2013 * BCM5717 | X | X | X | X | 2014 * BCM5719 | 3 | 10 | 4 | 11 | 2015 * BCM5720 | X | X | X | X | 2016 * 2017 * Other addresses may respond but they are not 2018 * IEEE compliant PHYs and should be ignored. 2019 */ 2020 switch (BGE_ASICREV(sc->bge_chipid)) { 2021 case BGE_ASICREV_BCM5717: 2022 case BGE_ASICREV_BCM5719: 2023 case BGE_ASICREV_BCM5720: 2024 phy_addr = pa->pa_function; 2025 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2026 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2027 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2028 } else { 2029 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2030 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2031 } 2032 } 2033 2034 return phy_addr; 2035 } 2036 2037 /* 2038 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2039 * self-test results. 2040 */ 2041 static int 2042 bge_chipinit(struct bge_softc *sc) 2043 { 2044 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2045 int i; 2046 2047 /* Set endianness before we access any non-PCI registers. */ 2048 misc_ctl = BGE_INIT; 2049 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2050 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2051 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2052 misc_ctl); 2053 2054 /* 2055 * Clear the MAC statistics block in the NIC's 2056 * internal memory. 2057 */ 2058 for (i = BGE_STATS_BLOCK; 2059 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2060 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2061 2062 for (i = BGE_STATUS_BLOCK; 2063 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2064 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2065 2066 /* 5717 workaround from tg3 */ 2067 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2068 /* Save */ 2069 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2070 2071 /* Temporary modify MODE_CTL to control TLP */ 2072 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2073 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2074 2075 /* Control TLP */ 2076 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2077 BGE_TLP_PHYCTL1); 2078 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2079 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2080 2081 /* Restore */ 2082 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2083 } 2084 2085 if (BGE_IS_57765_FAMILY(sc)) { 2086 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2087 /* Save */ 2088 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2089 2090 /* Temporary modify MODE_CTL to control TLP */ 2091 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2092 CSR_WRITE_4(sc, BGE_MODE_CTL, 2093 reg | BGE_MODECTL_PCIE_TLPADDR1); 2094 2095 /* Control TLP */ 2096 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2097 BGE_TLP_PHYCTL5); 2098 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2099 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2100 2101 /* Restore */ 2102 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2103 } 2104 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2105 /* 2106 * For the 57766 and non Ax versions of 57765, bootcode 2107 * needs to setup the PCIE Fast Training Sequence (FTS) 2108 * value to prevent transmit hangs. 2109 */ 2110 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2111 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2112 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2113 2114 /* Save */ 2115 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2116 2117 /* Temporary modify MODE_CTL to control TLP */ 2118 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2119 CSR_WRITE_4(sc, BGE_MODE_CTL, 2120 reg | BGE_MODECTL_PCIE_TLPADDR0); 2121 2122 /* Control TLP */ 2123 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2124 BGE_TLP_FTSMAX); 2125 reg &= ~BGE_TLP_FTSMAX_MSK; 2126 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2127 reg | BGE_TLP_FTSMAX_VAL); 2128 2129 /* Restore */ 2130 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2131 } 2132 2133 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2134 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2135 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2136 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2137 } 2138 2139 /* Set up the PCI DMA control register. */ 2140 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2141 if (sc->bge_flags & BGEF_PCIE) { 2142 /* Read watermark not used, 128 bytes for write. */ 2143 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2144 device_xname(sc->bge_dev))); 2145 if (sc->bge_mps >= 256) 2146 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2147 else 2148 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2149 } else if (sc->bge_flags & BGEF_PCIX) { 2150 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2151 device_xname(sc->bge_dev))); 2152 /* PCI-X bus */ 2153 if (BGE_IS_5714_FAMILY(sc)) { 2154 /* 256 bytes for read and write. */ 2155 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2156 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2157 2158 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2159 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2160 else 2161 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2162 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2163 /* 2164 * In the BCM5703, the DMA read watermark should 2165 * be set to less than or equal to the maximum 2166 * memory read byte count of the PCI-X command 2167 * register. 2168 */ 2169 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2170 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2171 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2172 /* 1536 bytes for read, 384 bytes for write. */ 2173 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2174 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2175 } else { 2176 /* 384 bytes for read and write. */ 2177 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2178 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2179 (0x0F); 2180 } 2181 2182 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2183 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2184 uint32_t tmp; 2185 2186 /* Set ONEDMA_ATONCE for hardware workaround. */ 2187 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2188 if (tmp == 6 || tmp == 7) 2189 dma_rw_ctl |= 2190 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2191 2192 /* Set PCI-X DMA write workaround. */ 2193 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2194 } 2195 } else { 2196 /* Conventional PCI bus: 256 bytes for read and write. */ 2197 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2198 device_xname(sc->bge_dev))); 2199 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2200 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2201 2202 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2203 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2204 dma_rw_ctl |= 0x0F; 2205 } 2206 2207 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2208 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2209 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2210 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2211 2212 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2213 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2214 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2215 2216 if (BGE_IS_57765_PLUS(sc)) { 2217 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2218 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2219 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2220 2221 /* 2222 * Enable HW workaround for controllers that misinterpret 2223 * a status tag update and leave interrupts permanently 2224 * disabled. 2225 */ 2226 if (!BGE_IS_57765_FAMILY(sc) && 2227 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2228 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2229 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2230 } 2231 2232 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2233 dma_rw_ctl); 2234 2235 /* 2236 * Set up general mode register. 2237 */ 2238 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2239 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2240 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2241 /* Retain Host-2-BMC settings written by APE firmware. */ 2242 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2243 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2244 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2245 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2246 } 2247 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2248 BGE_MODECTL_TX_NO_PHDR_CSUM; 2249 2250 /* 2251 * BCM5701 B5 have a bug causing data corruption when using 2252 * 64-bit DMA reads, which can be terminated early and then 2253 * completed later as 32-bit accesses, in combination with 2254 * certain bridges. 2255 */ 2256 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2257 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2258 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2259 2260 /* 2261 * Tell the firmware the driver is running 2262 */ 2263 if (sc->bge_asf_mode & ASF_STACKUP) 2264 mode_ctl |= BGE_MODECTL_STACKUP; 2265 2266 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2267 2268 /* 2269 * Disable memory write invalidate. Apparently it is not supported 2270 * properly by these devices. 2271 */ 2272 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2273 PCI_COMMAND_INVALIDATE_ENABLE); 2274 2275 #ifdef __brokenalpha__ 2276 /* 2277 * Must insure that we do not cross an 8K (bytes) boundary 2278 * for DMA reads. Our highest limit is 1K bytes. This is a 2279 * restriction on some ALPHA platforms with early revision 2280 * 21174 PCI chipsets, such as the AlphaPC 164lx 2281 */ 2282 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2283 #endif 2284 2285 /* Set the timer prescaler (always 66MHz) */ 2286 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2287 2288 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2289 DELAY(40); /* XXX */ 2290 2291 /* Put PHY into ready state */ 2292 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2293 DELAY(40); 2294 } 2295 2296 return 0; 2297 } 2298 2299 static int 2300 bge_blockinit(struct bge_softc *sc) 2301 { 2302 volatile struct bge_rcb *rcb; 2303 bus_size_t rcb_addr; 2304 struct ifnet * const ifp = &sc->ethercom.ec_if; 2305 bge_hostaddr taddr; 2306 uint32_t dmactl, rdmareg, mimode, val; 2307 int i, limit; 2308 2309 /* 2310 * Initialize the memory window pointer register so that 2311 * we can access the first 32K of internal NIC RAM. This will 2312 * allow us to set up the TX send ring RCBs and the RX return 2313 * ring RCBs, plus other things which live in NIC memory. 2314 */ 2315 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2316 2317 if (!BGE_IS_5705_PLUS(sc)) { 2318 /* 57XX step 33 */ 2319 /* Configure mbuf memory pool */ 2320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2321 2322 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2323 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2324 else 2325 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2326 2327 /* 57XX step 34 */ 2328 /* Configure DMA resource pool */ 2329 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2330 BGE_DMA_DESCRIPTORS); 2331 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2332 } 2333 2334 /* 5718 step 11, 57XX step 35 */ 2335 /* 2336 * Configure mbuf pool watermarks. New broadcom docs strongly 2337 * recommend these. 2338 */ 2339 if (BGE_IS_5717_PLUS(sc)) { 2340 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2341 if (ifp->if_mtu > ETHERMTU) { 2342 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2344 } else { 2345 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2346 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2347 } 2348 } else if (BGE_IS_5705_PLUS(sc)) { 2349 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2350 2351 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2354 } else { 2355 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2356 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2357 } 2358 } else { 2359 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2360 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2362 } 2363 2364 /* 57XX step 36 */ 2365 /* Configure DMA resource watermarks */ 2366 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2367 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2368 2369 /* 5718 step 13, 57XX step 38 */ 2370 /* Enable buffer manager */ 2371 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2372 /* 2373 * Change the arbitration algorithm of TXMBUF read request to 2374 * round-robin instead of priority based for BCM5719. When 2375 * TXFIFO is almost empty, RDMA will hold its request until 2376 * TXFIFO is not almost empty. 2377 */ 2378 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2379 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2380 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2381 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2382 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2383 val |= BGE_BMANMODE_LOMBUF_ATTN; 2384 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2385 2386 /* 57XX step 39 */ 2387 /* Poll for buffer manager start indication */ 2388 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2389 DELAY(10); 2390 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2391 break; 2392 } 2393 2394 if (i == BGE_TIMEOUT * 2) { 2395 aprint_error_dev(sc->bge_dev, 2396 "buffer manager failed to start\n"); 2397 return ENXIO; 2398 } 2399 2400 /* 57XX step 40 */ 2401 /* Enable flow-through queues */ 2402 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2403 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2404 2405 /* Wait until queue initialization is complete */ 2406 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2407 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2408 break; 2409 DELAY(10); 2410 } 2411 2412 if (i == BGE_TIMEOUT * 2) { 2413 aprint_error_dev(sc->bge_dev, 2414 "flow-through queue init failed\n"); 2415 return ENXIO; 2416 } 2417 2418 /* 2419 * Summary of rings supported by the controller: 2420 * 2421 * Standard Receive Producer Ring 2422 * - This ring is used to feed receive buffers for "standard" 2423 * sized frames (typically 1536 bytes) to the controller. 2424 * 2425 * Jumbo Receive Producer Ring 2426 * - This ring is used to feed receive buffers for jumbo sized 2427 * frames (i.e. anything bigger than the "standard" frames) 2428 * to the controller. 2429 * 2430 * Mini Receive Producer Ring 2431 * - This ring is used to feed receive buffers for "mini" 2432 * sized frames to the controller. 2433 * - This feature required external memory for the controller 2434 * but was never used in a production system. Should always 2435 * be disabled. 2436 * 2437 * Receive Return Ring 2438 * - After the controller has placed an incoming frame into a 2439 * receive buffer that buffer is moved into a receive return 2440 * ring. The driver is then responsible to passing the 2441 * buffer up to the stack. Many versions of the controller 2442 * support multiple RR rings. 2443 * 2444 * Send Ring 2445 * - This ring is used for outgoing frames. Many versions of 2446 * the controller support multiple send rings. 2447 */ 2448 2449 /* 5718 step 15, 57XX step 41 */ 2450 /* Initialize the standard RX ring control block */ 2451 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2452 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2453 /* 5718 step 16 */ 2454 if (BGE_IS_57765_PLUS(sc)) { 2455 /* 2456 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2457 * Bits 15-2 : Maximum RX frame size 2458 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2459 * Bit 0 : Reserved 2460 */ 2461 rcb->bge_maxlen_flags = 2462 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2463 } else if (BGE_IS_5705_PLUS(sc)) { 2464 /* 2465 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2466 * Bits 15-2 : Reserved (should be 0) 2467 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2468 * Bit 0 : Reserved 2469 */ 2470 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2471 } else { 2472 /* 2473 * Ring size is always XXX entries 2474 * Bits 31-16: Maximum RX frame size 2475 * Bits 15-2 : Reserved (should be 0) 2476 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2477 * Bit 0 : Reserved 2478 */ 2479 rcb->bge_maxlen_flags = 2480 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2481 } 2482 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2483 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2485 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2486 else 2487 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2488 /* Write the standard receive producer ring control block. */ 2489 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2490 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2491 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2492 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2493 2494 /* Reset the standard receive producer ring producer index. */ 2495 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2496 2497 /* 57XX step 42 */ 2498 /* 2499 * Initialize the jumbo RX ring control block 2500 * We set the 'ring disabled' bit in the flags 2501 * field until we're actually ready to start 2502 * using this ring (i.e. once we set the MTU 2503 * high enough to require it). 2504 */ 2505 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2506 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2507 BGE_HOSTADDR(rcb->bge_hostaddr, 2508 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2509 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2510 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2511 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2512 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2513 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2514 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2515 else 2516 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2517 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2518 rcb->bge_hostaddr.bge_addr_hi); 2519 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2520 rcb->bge_hostaddr.bge_addr_lo); 2521 /* Program the jumbo receive producer ring RCB parameters. */ 2522 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2523 rcb->bge_maxlen_flags); 2524 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2525 /* Reset the jumbo receive producer ring producer index. */ 2526 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2527 } 2528 2529 /* 57XX step 43 */ 2530 /* Disable the mini receive producer ring RCB. */ 2531 if (BGE_IS_5700_FAMILY(sc)) { 2532 /* Set up dummy disabled mini ring RCB */ 2533 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2534 rcb->bge_maxlen_flags = 2535 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2536 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2537 rcb->bge_maxlen_flags); 2538 /* Reset the mini receive producer ring producer index. */ 2539 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2540 2541 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2542 offsetof(struct bge_ring_data, bge_info), 2543 sizeof(struct bge_gib), 2544 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2545 } 2546 2547 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2548 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2549 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2550 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2551 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2552 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2553 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2554 } 2555 /* 5718 step 14, 57XX step 44 */ 2556 /* 2557 * The BD ring replenish thresholds control how often the 2558 * hardware fetches new BD's from the producer rings in host 2559 * memory. Setting the value too low on a busy system can 2560 * starve the hardware and recue the throughpout. 2561 * 2562 * Set the BD ring replenish thresholds. The recommended 2563 * values are 1/8th the number of descriptors allocated to 2564 * each ring, but since we try to avoid filling the entire 2565 * ring we set these to the minimal value of 8. This needs to 2566 * be done on several of the supported chip revisions anyway, 2567 * to work around HW bugs. 2568 */ 2569 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2570 if (BGE_IS_JUMBO_CAPABLE(sc)) 2571 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2572 2573 /* 5718 step 18 */ 2574 if (BGE_IS_5717_PLUS(sc)) { 2575 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2576 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2577 } 2578 2579 /* 57XX step 45 */ 2580 /* 2581 * Disable all send rings by setting the 'ring disabled' bit 2582 * in the flags field of all the TX send ring control blocks, 2583 * located in NIC memory. 2584 */ 2585 if (BGE_IS_5700_FAMILY(sc)) { 2586 /* 5700 to 5704 had 16 send rings. */ 2587 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2588 } else if (BGE_IS_5717_PLUS(sc)) { 2589 limit = BGE_TX_RINGS_5717_MAX; 2590 } else if (BGE_IS_57765_FAMILY(sc) || 2591 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2592 limit = BGE_TX_RINGS_57765_MAX; 2593 } else 2594 limit = 1; 2595 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2596 for (i = 0; i < limit; i++) { 2597 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2598 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2599 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2600 rcb_addr += sizeof(struct bge_rcb); 2601 } 2602 2603 /* 57XX step 46 and 47 */ 2604 /* Configure send ring RCB 0 (we use only the first ring) */ 2605 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2606 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2607 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2608 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2609 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2610 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2611 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2612 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2613 else 2614 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2615 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2616 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2617 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2618 2619 /* 57XX step 48 */ 2620 /* 2621 * Disable all receive return rings by setting the 2622 * 'ring diabled' bit in the flags field of all the receive 2623 * return ring control blocks, located in NIC memory. 2624 */ 2625 if (BGE_IS_5717_PLUS(sc)) { 2626 /* Should be 17, use 16 until we get an SRAM map. */ 2627 limit = 16; 2628 } else if (BGE_IS_5700_FAMILY(sc)) 2629 limit = BGE_RX_RINGS_MAX; 2630 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2631 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2632 BGE_IS_57765_FAMILY(sc)) 2633 limit = 4; 2634 else 2635 limit = 1; 2636 /* Disable all receive return rings */ 2637 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2638 for (i = 0; i < limit; i++) { 2639 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2640 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2641 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2642 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2643 BGE_RCB_FLAG_RING_DISABLED)); 2644 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2645 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2646 (i * (sizeof(uint64_t))), 0); 2647 rcb_addr += sizeof(struct bge_rcb); 2648 } 2649 2650 /* 57XX step 49 */ 2651 /* 2652 * Set up receive return ring 0. Note that the NIC address 2653 * for RX return rings is 0x0. The return rings live entirely 2654 * within the host, so the nicaddr field in the RCB isn't used. 2655 */ 2656 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2657 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2658 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2659 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2660 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2661 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2662 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2663 2664 /* 5718 step 24, 57XX step 53 */ 2665 /* Set random backoff seed for TX */ 2666 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2667 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2668 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2669 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2670 BGE_TX_BACKOFF_SEED_MASK); 2671 2672 /* 5718 step 26, 57XX step 55 */ 2673 /* Set inter-packet gap */ 2674 val = 0x2620; 2675 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2676 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2677 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2678 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2679 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2680 2681 /* 5718 step 27, 57XX step 56 */ 2682 /* 2683 * Specify which ring to use for packets that don't match 2684 * any RX rules. 2685 */ 2686 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2687 2688 /* 5718 step 28, 57XX step 57 */ 2689 /* 2690 * Configure number of RX lists. One interrupt distribution 2691 * list, sixteen active lists, one bad frames class. 2692 */ 2693 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2694 2695 /* 5718 step 29, 57XX step 58 */ 2696 /* Inialize RX list placement stats mask. */ 2697 if (BGE_IS_575X_PLUS(sc)) { 2698 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2699 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2700 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2701 } else 2702 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2703 2704 /* 5718 step 30, 57XX step 59 */ 2705 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2706 2707 /* 5718 step 33, 57XX step 62 */ 2708 /* Disable host coalescing until we get it set up */ 2709 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2710 2711 /* 5718 step 34, 57XX step 63 */ 2712 /* Poll to make sure it's shut down. */ 2713 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2714 DELAY(10); 2715 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2716 break; 2717 } 2718 2719 if (i == BGE_TIMEOUT * 2) { 2720 aprint_error_dev(sc->bge_dev, 2721 "host coalescing engine failed to idle\n"); 2722 return ENXIO; 2723 } 2724 2725 /* 5718 step 35, 36, 37 */ 2726 /* Set up host coalescing defaults */ 2727 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2728 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2729 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2730 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2731 if (!(BGE_IS_5705_PLUS(sc))) { 2732 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2733 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2734 } 2735 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2736 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2737 2738 /* Set up address of statistics block */ 2739 if (BGE_IS_5700_FAMILY(sc)) { 2740 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2741 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2742 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2743 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2744 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2745 } 2746 2747 /* 5718 step 38 */ 2748 /* Set up address of status block */ 2749 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2750 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2751 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2752 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2753 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2754 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2755 2756 /* Set up status block size. */ 2757 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2758 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2759 val = BGE_STATBLKSZ_FULL; 2760 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2761 } else { 2762 val = BGE_STATBLKSZ_32BYTE; 2763 bzero(&sc->bge_rdata->bge_status_block, 32); 2764 } 2765 2766 /* 5718 step 39, 57XX step 73 */ 2767 /* Turn on host coalescing state machine */ 2768 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2769 2770 /* 5718 step 40, 57XX step 74 */ 2771 /* Turn on RX BD completion state machine and enable attentions */ 2772 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2773 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2774 2775 /* 5718 step 41, 57XX step 75 */ 2776 /* Turn on RX list placement state machine */ 2777 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2778 2779 /* 57XX step 76 */ 2780 /* Turn on RX list selector state machine. */ 2781 if (!(BGE_IS_5705_PLUS(sc))) 2782 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2783 2784 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2785 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2786 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2787 BGE_MACMODE_FRMHDR_DMA_ENB; 2788 2789 if (sc->bge_flags & BGEF_FIBER_TBI) 2790 val |= BGE_PORTMODE_TBI; 2791 else if (sc->bge_flags & BGEF_FIBER_MII) 2792 val |= BGE_PORTMODE_GMII; 2793 else 2794 val |= BGE_PORTMODE_MII; 2795 2796 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2797 /* Allow APE to send/receive frames. */ 2798 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2799 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2800 2801 /* Turn on DMA, clear stats */ 2802 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2803 /* 5718 step 44 */ 2804 DELAY(40); 2805 2806 /* 5718 step 45, 57XX step 79 */ 2807 /* Set misc. local control, enable interrupts on attentions */ 2808 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2809 if (BGE_IS_5717_PLUS(sc)) { 2810 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2811 /* 5718 step 46 */ 2812 DELAY(100); 2813 } 2814 2815 /* 57XX step 81 */ 2816 /* Turn on DMA completion state machine */ 2817 if (!(BGE_IS_5705_PLUS(sc))) 2818 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2819 2820 /* 5718 step 47, 57XX step 82 */ 2821 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2822 2823 /* 5718 step 48 */ 2824 /* Enable host coalescing bug fix. */ 2825 if (BGE_IS_5755_PLUS(sc)) 2826 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2827 2828 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2829 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2830 2831 /* Turn on write DMA state machine */ 2832 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2833 /* 5718 step 49 */ 2834 DELAY(40); 2835 2836 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2837 2838 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2839 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2840 2841 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2842 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2843 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2844 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2845 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2846 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2847 2848 if (sc->bge_flags & BGEF_PCIE) 2849 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2850 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2851 if (ifp->if_mtu <= ETHERMTU) 2852 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2853 } 2854 if (sc->bge_flags & BGEF_TSO) { 2855 val |= BGE_RDMAMODE_TSO4_ENABLE; 2856 if (BGE_IS_5717_PLUS(sc)) 2857 val |= BGE_RDMAMODE_TSO6_ENABLE; 2858 } 2859 2860 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2861 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2862 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2863 BGE_RDMAMODE_H2BNC_VLAN_DET; 2864 /* 2865 * Allow multiple outstanding read requests from 2866 * non-LSO read DMA engine. 2867 */ 2868 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2869 } 2870 2871 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2872 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2873 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2874 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2875 BGE_IS_57765_PLUS(sc)) { 2876 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2877 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2878 else 2879 rdmareg = BGE_RDMA_RSRVCTRL; 2880 dmactl = CSR_READ_4(sc, rdmareg); 2881 /* 2882 * Adjust tx margin to prevent TX data corruption and 2883 * fix internal FIFO overflow. 2884 */ 2885 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2886 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2887 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2888 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2889 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2890 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2891 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2892 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2893 } 2894 /* 2895 * Enable fix for read DMA FIFO overruns. 2896 * The fix is to limit the number of RX BDs 2897 * the hardware would fetch at a time. 2898 */ 2899 CSR_WRITE_4(sc, rdmareg, dmactl | 2900 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2901 } 2902 2903 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2904 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2905 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2906 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2907 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2908 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2909 /* 2910 * Allow 4KB burst length reads for non-LSO frames. 2911 * Enable 512B burst length reads for buffer descriptors. 2912 */ 2913 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2914 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2915 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2916 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2917 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2918 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2919 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2920 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2921 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2922 } 2923 /* Turn on read DMA state machine */ 2924 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2925 /* 5718 step 52 */ 2926 delay(40); 2927 2928 if (sc->bge_flags & BGEF_RDMA_BUG) { 2929 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2930 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2931 if ((val & 0xFFFF) > BGE_FRAMELEN) 2932 break; 2933 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2934 break; 2935 } 2936 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2937 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2938 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2939 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2940 else 2941 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2942 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2943 } 2944 } 2945 2946 /* 5718 step 56, 57XX step 84 */ 2947 /* Turn on RX data completion state machine */ 2948 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2949 2950 /* Turn on RX data and RX BD initiator state machine */ 2951 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2952 2953 /* 57XX step 85 */ 2954 /* Turn on Mbuf cluster free state machine */ 2955 if (!BGE_IS_5705_PLUS(sc)) 2956 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2957 2958 /* 5718 step 57, 57XX step 86 */ 2959 /* Turn on send data completion state machine */ 2960 val = BGE_SDCMODE_ENABLE; 2961 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2962 val |= BGE_SDCMODE_CDELAY; 2963 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2964 2965 /* 5718 step 58 */ 2966 /* Turn on send BD completion state machine */ 2967 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2968 2969 /* 57XX step 88 */ 2970 /* Turn on RX BD initiator state machine */ 2971 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2972 2973 /* 5718 step 60, 57XX step 90 */ 2974 /* Turn on send data initiator state machine */ 2975 if (sc->bge_flags & BGEF_TSO) { 2976 /* XXX: magic value from Linux driver */ 2977 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2978 BGE_SDIMODE_HW_LSO_PRE_DMA); 2979 } else 2980 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2981 2982 /* 5718 step 61, 57XX step 91 */ 2983 /* Turn on send BD initiator state machine */ 2984 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2985 2986 /* 5718 step 62, 57XX step 92 */ 2987 /* Turn on send BD selector state machine */ 2988 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2989 2990 /* 5718 step 31, 57XX step 60 */ 2991 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2992 /* 5718 step 32, 57XX step 61 */ 2993 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2994 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2995 2996 /* ack/clear link change events */ 2997 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2998 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2999 BGE_MACSTAT_LINK_CHANGED); 3000 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3001 3002 /* 3003 * Enable attention when the link has changed state for 3004 * devices that use auto polling. 3005 */ 3006 if (sc->bge_flags & BGEF_FIBER_TBI) { 3007 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3008 } else { 3009 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3010 mimode = BGE_MIMODE_500KHZ_CONST; 3011 else 3012 mimode = BGE_MIMODE_BASE; 3013 /* 5718 step 68. 5718 step 69 (optionally). */ 3014 if (BGE_IS_5700_FAMILY(sc) || 3015 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3016 mimode |= BGE_MIMODE_AUTOPOLL; 3017 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3018 } 3019 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3020 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3021 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3022 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3023 BGE_EVTENB_MI_INTERRUPT); 3024 } 3025 3026 /* 3027 * Clear any pending link state attention. 3028 * Otherwise some link state change events may be lost until attention 3029 * is cleared by bge_intr() -> bge_link_upd() sequence. 3030 * It's not necessary on newer BCM chips - perhaps enabling link 3031 * state change attentions implies clearing pending attention. 3032 */ 3033 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3034 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3035 BGE_MACSTAT_LINK_CHANGED); 3036 3037 /* Enable link state change attentions. */ 3038 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3039 3040 return 0; 3041 } 3042 3043 static const struct bge_revision * 3044 bge_lookup_rev(uint32_t chipid) 3045 { 3046 const struct bge_revision *br; 3047 3048 for (br = bge_revisions; br->br_name != NULL; br++) { 3049 if (br->br_chipid == chipid) 3050 return br; 3051 } 3052 3053 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3054 if (br->br_chipid == BGE_ASICREV(chipid)) 3055 return br; 3056 } 3057 3058 return NULL; 3059 } 3060 3061 static const struct bge_product * 3062 bge_lookup(const struct pci_attach_args *pa) 3063 { 3064 const struct bge_product *bp; 3065 3066 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3067 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3068 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3069 return bp; 3070 } 3071 3072 return NULL; 3073 } 3074 3075 static uint32_t 3076 bge_chipid(const struct pci_attach_args *pa) 3077 { 3078 uint32_t id; 3079 3080 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3081 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3082 3083 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3084 switch (PCI_PRODUCT(pa->pa_id)) { 3085 case PCI_PRODUCT_BROADCOM_BCM5717: 3086 case PCI_PRODUCT_BROADCOM_BCM5718: 3087 case PCI_PRODUCT_BROADCOM_BCM5719: 3088 case PCI_PRODUCT_BROADCOM_BCM5720: 3089 case PCI_PRODUCT_BROADCOM_BCM5725: 3090 case PCI_PRODUCT_BROADCOM_BCM5727: 3091 case PCI_PRODUCT_BROADCOM_BCM5762: 3092 case PCI_PRODUCT_BROADCOM_BCM57764: 3093 case PCI_PRODUCT_BROADCOM_BCM57767: 3094 case PCI_PRODUCT_BROADCOM_BCM57787: 3095 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3096 BGE_PCI_GEN2_PRODID_ASICREV); 3097 break; 3098 case PCI_PRODUCT_BROADCOM_BCM57761: 3099 case PCI_PRODUCT_BROADCOM_BCM57762: 3100 case PCI_PRODUCT_BROADCOM_BCM57765: 3101 case PCI_PRODUCT_BROADCOM_BCM57766: 3102 case PCI_PRODUCT_BROADCOM_BCM57781: 3103 case PCI_PRODUCT_BROADCOM_BCM57782: 3104 case PCI_PRODUCT_BROADCOM_BCM57785: 3105 case PCI_PRODUCT_BROADCOM_BCM57786: 3106 case PCI_PRODUCT_BROADCOM_BCM57791: 3107 case PCI_PRODUCT_BROADCOM_BCM57795: 3108 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3109 BGE_PCI_GEN15_PRODID_ASICREV); 3110 break; 3111 default: 3112 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3113 BGE_PCI_PRODID_ASICREV); 3114 break; 3115 } 3116 } 3117 3118 return id; 3119 } 3120 3121 /* 3122 * Return true if MSI can be used with this device. 3123 */ 3124 static int 3125 bge_can_use_msi(struct bge_softc *sc) 3126 { 3127 int can_use_msi = 0; 3128 3129 switch (BGE_ASICREV(sc->bge_chipid)) { 3130 case BGE_ASICREV_BCM5714_A0: 3131 case BGE_ASICREV_BCM5714: 3132 /* 3133 * Apparently, MSI doesn't work when these chips are 3134 * configured in single-port mode. 3135 */ 3136 break; 3137 case BGE_ASICREV_BCM5750: 3138 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3139 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3140 can_use_msi = 1; 3141 break; 3142 default: 3143 if (BGE_IS_575X_PLUS(sc)) 3144 can_use_msi = 1; 3145 } 3146 return can_use_msi; 3147 } 3148 3149 /* 3150 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3151 * against our list and return its name if we find a match. Note 3152 * that since the Broadcom controller contains VPD support, we 3153 * can get the device name string from the controller itself instead 3154 * of the compiled-in string. This is a little slow, but it guarantees 3155 * we'll always announce the right product name. 3156 */ 3157 static int 3158 bge_probe(device_t parent, cfdata_t match, void *aux) 3159 { 3160 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3161 3162 if (bge_lookup(pa) != NULL) 3163 return 1; 3164 3165 return 0; 3166 } 3167 3168 static void 3169 bge_attach(device_t parent, device_t self, void *aux) 3170 { 3171 struct bge_softc * const sc = device_private(self); 3172 struct pci_attach_args * const pa = aux; 3173 prop_dictionary_t dict; 3174 const struct bge_product *bp; 3175 const struct bge_revision *br; 3176 pci_chipset_tag_t pc; 3177 const char *intrstr = NULL; 3178 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3179 uint32_t command; 3180 struct ifnet *ifp; 3181 struct mii_data * const mii = &sc->bge_mii; 3182 uint32_t misccfg, mimode, macmode; 3183 void * kva; 3184 u_char eaddr[ETHER_ADDR_LEN]; 3185 pcireg_t memtype, subid, reg; 3186 bus_addr_t memaddr; 3187 uint32_t pm_ctl; 3188 bool no_seeprom; 3189 int capmask, trys; 3190 int mii_flags; 3191 int map_flags; 3192 char intrbuf[PCI_INTRSTR_LEN]; 3193 3194 bp = bge_lookup(pa); 3195 KASSERT(bp != NULL); 3196 3197 sc->sc_pc = pa->pa_pc; 3198 sc->sc_pcitag = pa->pa_tag; 3199 sc->bge_dev = self; 3200 3201 sc->bge_pa = *pa; 3202 pc = sc->sc_pc; 3203 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3204 3205 aprint_naive(": Ethernet controller\n"); 3206 aprint_normal(": %s Ethernet\n", bp->bp_name); 3207 3208 /* 3209 * Map control/status registers. 3210 */ 3211 DPRINTFN(5, ("Map control/status regs\n")); 3212 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3213 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3214 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3215 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3216 3217 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3218 aprint_error_dev(sc->bge_dev, 3219 "failed to enable memory mapping!\n"); 3220 return; 3221 } 3222 3223 DPRINTFN(5, ("pci_mem_find\n")); 3224 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3225 switch (memtype) { 3226 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3227 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3228 #if 0 3229 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3230 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3231 &memaddr, &sc->bge_bsize) == 0) 3232 break; 3233 #else 3234 /* 3235 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3236 * system get NMI on boot (PR#48451). This problem might not be 3237 * the driver's bug but our PCI common part's bug. Until we 3238 * find a real reason, we ignore the prefetchable bit. 3239 */ 3240 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3241 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3242 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3243 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3244 map_flags, &sc->bge_bhandle) == 0) { 3245 sc->bge_btag = pa->pa_memt; 3246 break; 3247 } 3248 } 3249 #endif 3250 /* FALLTHROUGH */ 3251 default: 3252 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3253 return; 3254 } 3255 3256 /* Save various chip information. */ 3257 sc->bge_chipid = bge_chipid(pa); 3258 sc->bge_phy_addr = bge_phy_addr(sc); 3259 3260 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3261 &sc->bge_pciecap, NULL) != 0) { 3262 /* PCIe */ 3263 sc->bge_flags |= BGEF_PCIE; 3264 /* Extract supported maximum payload size. */ 3265 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3266 sc->bge_pciecap + PCIE_DCAP); 3267 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3268 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3269 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3270 sc->bge_expmrq = 2048; 3271 else 3272 sc->bge_expmrq = 4096; 3273 bge_set_max_readrq(sc); 3274 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3275 /* PCIe without PCIe cap */ 3276 sc->bge_flags |= BGEF_PCIE; 3277 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3278 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3279 /* PCI-X */ 3280 sc->bge_flags |= BGEF_PCIX; 3281 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3282 &sc->bge_pcixcap, NULL) == 0) 3283 aprint_error_dev(sc->bge_dev, 3284 "unable to find PCIX capability\n"); 3285 } 3286 3287 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3288 /* 3289 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3290 * can clobber the chip's PCI config-space power control 3291 * registers, leaving the card in D3 powersave state. We do 3292 * not have memory-mapped registers in this state, so force 3293 * device into D0 state before starting initialization. 3294 */ 3295 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3296 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3297 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3298 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3299 DELAY(1000); /* 27 usec is allegedly sufficient */ 3300 } 3301 3302 /* Save chipset family. */ 3303 switch (BGE_ASICREV(sc->bge_chipid)) { 3304 case BGE_ASICREV_BCM5717: 3305 case BGE_ASICREV_BCM5719: 3306 case BGE_ASICREV_BCM5720: 3307 sc->bge_flags |= BGEF_5717_PLUS; 3308 /* FALLTHROUGH */ 3309 case BGE_ASICREV_BCM5762: 3310 case BGE_ASICREV_BCM57765: 3311 case BGE_ASICREV_BCM57766: 3312 if (!BGE_IS_5717_PLUS(sc)) 3313 sc->bge_flags |= BGEF_57765_FAMILY; 3314 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3315 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3316 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3317 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3318 /* 3319 * Enable work around for DMA engine miscalculation 3320 * of TXMBUF available space. 3321 */ 3322 sc->bge_flags |= BGEF_RDMA_BUG; 3323 3324 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3325 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3326 /* Jumbo frame on BCM5719 A0 does not work. */ 3327 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3328 } 3329 } 3330 break; 3331 case BGE_ASICREV_BCM5755: 3332 case BGE_ASICREV_BCM5761: 3333 case BGE_ASICREV_BCM5784: 3334 case BGE_ASICREV_BCM5785: 3335 case BGE_ASICREV_BCM5787: 3336 case BGE_ASICREV_BCM57780: 3337 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3338 break; 3339 case BGE_ASICREV_BCM5700: 3340 case BGE_ASICREV_BCM5701: 3341 case BGE_ASICREV_BCM5703: 3342 case BGE_ASICREV_BCM5704: 3343 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3344 break; 3345 case BGE_ASICREV_BCM5714_A0: 3346 case BGE_ASICREV_BCM5780: 3347 case BGE_ASICREV_BCM5714: 3348 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3349 /* FALLTHROUGH */ 3350 case BGE_ASICREV_BCM5750: 3351 case BGE_ASICREV_BCM5752: 3352 case BGE_ASICREV_BCM5906: 3353 sc->bge_flags |= BGEF_575X_PLUS; 3354 /* FALLTHROUGH */ 3355 case BGE_ASICREV_BCM5705: 3356 sc->bge_flags |= BGEF_5705_PLUS; 3357 break; 3358 } 3359 3360 /* Identify chips with APE processor. */ 3361 switch (BGE_ASICREV(sc->bge_chipid)) { 3362 case BGE_ASICREV_BCM5717: 3363 case BGE_ASICREV_BCM5719: 3364 case BGE_ASICREV_BCM5720: 3365 case BGE_ASICREV_BCM5761: 3366 case BGE_ASICREV_BCM5762: 3367 sc->bge_flags |= BGEF_APE; 3368 break; 3369 } 3370 3371 /* 3372 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3373 * not actually a MAC controller bug but an issue with the embedded 3374 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3375 */ 3376 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3377 sc->bge_flags |= BGEF_40BIT_BUG; 3378 3379 /* Chips with APE need BAR2 access for APE registers/memory. */ 3380 if ((sc->bge_flags & BGEF_APE) != 0) { 3381 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3382 #if 0 3383 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3384 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3385 &sc->bge_apesize)) { 3386 aprint_error_dev(sc->bge_dev, 3387 "couldn't map BAR2 memory\n"); 3388 return; 3389 } 3390 #else 3391 /* 3392 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3393 * system get NMI on boot (PR#48451). This problem might not be 3394 * the driver's bug but our PCI common part's bug. Until we 3395 * find a real reason, we ignore the prefetchable bit. 3396 */ 3397 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3398 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3399 aprint_error_dev(sc->bge_dev, 3400 "couldn't map BAR2 memory\n"); 3401 return; 3402 } 3403 3404 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3405 if (bus_space_map(pa->pa_memt, memaddr, 3406 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3407 aprint_error_dev(sc->bge_dev, 3408 "couldn't map BAR2 memory\n"); 3409 return; 3410 } 3411 sc->bge_apetag = pa->pa_memt; 3412 #endif 3413 3414 /* Enable APE register/memory access by host driver. */ 3415 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3416 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3417 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3418 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3419 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3420 3421 bge_ape_lock_init(sc); 3422 bge_ape_read_fw_ver(sc); 3423 } 3424 3425 /* Identify the chips that use an CPMU. */ 3426 if (BGE_IS_5717_PLUS(sc) || 3427 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3428 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3429 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3430 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3431 sc->bge_flags |= BGEF_CPMU_PRESENT; 3432 3433 /* 3434 * When using the BCM5701 in PCI-X mode, data corruption has 3435 * been observed in the first few bytes of some received packets. 3436 * Aligning the packet buffer in memory eliminates the corruption. 3437 * Unfortunately, this misaligns the packet payloads. On platforms 3438 * which do not support unaligned accesses, we will realign the 3439 * payloads by copying the received packets. 3440 */ 3441 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3442 sc->bge_flags & BGEF_PCIX) 3443 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3444 3445 if (BGE_IS_5700_FAMILY(sc)) 3446 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3447 3448 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3449 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3450 3451 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3452 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3453 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3454 sc->bge_flags |= BGEF_IS_5788; 3455 3456 /* 3457 * Some controllers seem to require a special firmware to use 3458 * TSO. But the firmware is not available to FreeBSD and Linux 3459 * claims that the TSO performed by the firmware is slower than 3460 * hardware based TSO. Moreover the firmware based TSO has one 3461 * known bug which can't handle TSO if ethernet header + IP/TCP 3462 * header is greater than 80 bytes. The workaround for the TSO 3463 * bug exist but it seems it's too expensive than not using 3464 * TSO at all. Some hardwares also have the TSO bug so limit 3465 * the TSO to the controllers that are not affected TSO issues 3466 * (e.g. 5755 or higher). 3467 */ 3468 if (BGE_IS_5755_PLUS(sc)) { 3469 /* 3470 * BCM5754 and BCM5787 shares the same ASIC id so 3471 * explicit device id check is required. 3472 */ 3473 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3474 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3475 sc->bge_flags |= BGEF_TSO; 3476 /* TSO on BCM5719 A0 does not work. */ 3477 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3478 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3479 sc->bge_flags &= ~BGEF_TSO; 3480 } 3481 3482 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3483 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3484 (misccfg == 0x4000 || misccfg == 0x8000)) || 3485 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3486 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3487 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3488 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3489 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3490 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3491 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3492 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3493 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3494 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3495 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3496 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3497 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3498 /* These chips are 10/100 only. */ 3499 capmask &= ~BMSR_EXTSTAT; 3500 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3501 } 3502 3503 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3504 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3505 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3506 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3507 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3508 3509 /* Set various PHY bug flags. */ 3510 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3511 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3512 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3513 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3514 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3515 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3516 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3517 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3518 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3519 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3520 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3521 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3522 if (BGE_IS_5705_PLUS(sc) && 3523 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3524 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3525 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3526 !BGE_IS_57765_PLUS(sc)) { 3527 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3528 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3529 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3530 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3531 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3532 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3533 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3534 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3535 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3536 } else 3537 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3538 } 3539 3540 /* 3541 * SEEPROM check. 3542 * First check if firmware knows we do not have SEEPROM. 3543 */ 3544 if (prop_dictionary_get_bool(device_properties(self), 3545 "without-seeprom", &no_seeprom) && no_seeprom) 3546 sc->bge_flags |= BGEF_NO_EEPROM; 3547 3548 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3549 sc->bge_flags |= BGEF_NO_EEPROM; 3550 3551 /* Now check the 'ROM failed' bit on the RX CPU */ 3552 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3553 sc->bge_flags |= BGEF_NO_EEPROM; 3554 3555 sc->bge_asf_mode = 0; 3556 /* No ASF if APE present. */ 3557 if ((sc->bge_flags & BGEF_APE) == 0) { 3558 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3559 BGE_SRAM_DATA_SIG_MAGIC)) { 3560 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3561 BGE_HWCFG_ASF) { 3562 sc->bge_asf_mode |= ASF_ENABLE; 3563 sc->bge_asf_mode |= ASF_STACKUP; 3564 if (BGE_IS_575X_PLUS(sc)) 3565 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3566 } 3567 } 3568 } 3569 3570 int counts[PCI_INTR_TYPE_SIZE] = { 3571 [PCI_INTR_TYPE_INTX] = 1, 3572 [PCI_INTR_TYPE_MSI] = 1, 3573 [PCI_INTR_TYPE_MSIX] = 1, 3574 }; 3575 int max_type = PCI_INTR_TYPE_MSIX; 3576 3577 if (!bge_can_use_msi(sc)) { 3578 /* MSI broken, allow only INTx */ 3579 max_type = PCI_INTR_TYPE_INTX; 3580 } 3581 3582 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3583 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3584 return; 3585 } 3586 3587 DPRINTFN(5, ("pci_intr_string\n")); 3588 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3589 sizeof(intrbuf)); 3590 DPRINTFN(5, ("pci_intr_establish\n")); 3591 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3592 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3593 if (sc->bge_intrhand == NULL) { 3594 pci_intr_release(pc, sc->bge_pihp, 1); 3595 sc->bge_pihp = NULL; 3596 3597 aprint_error_dev(self, "couldn't establish interrupt"); 3598 if (intrstr != NULL) 3599 aprint_error(" at %s", intrstr); 3600 aprint_error("\n"); 3601 return; 3602 } 3603 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3604 3605 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3606 case PCI_INTR_TYPE_MSIX: 3607 case PCI_INTR_TYPE_MSI: 3608 KASSERT(bge_can_use_msi(sc)); 3609 sc->bge_flags |= BGEF_MSI; 3610 break; 3611 default: 3612 /* nothing to do */ 3613 break; 3614 } 3615 3616 /* 3617 * All controllers except BCM5700 supports tagged status but 3618 * we use tagged status only for MSI case on BCM5717. Otherwise 3619 * MSI on BCM5717 does not work. 3620 */ 3621 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3622 sc->bge_flags |= BGEF_TAGGED_STATUS; 3623 3624 /* 3625 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3626 * lock in bge_reset(). 3627 */ 3628 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3629 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3630 delay(1000); 3631 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3632 3633 bge_stop_fw(sc); 3634 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3635 if (bge_reset(sc)) 3636 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3637 3638 /* 3639 * Read the hardware config word in the first 32k of NIC internal 3640 * memory, or fall back to the config word in the EEPROM. 3641 * Note: on some BCM5700 cards, this value appears to be unset. 3642 */ 3643 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3644 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3645 BGE_SRAM_DATA_SIG_MAGIC) { 3646 uint32_t tmp; 3647 3648 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3649 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3650 BGE_SRAM_DATA_VER_SHIFT; 3651 if ((0 < tmp) && (tmp < 0x100)) 3652 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3653 if (sc->bge_flags & BGEF_PCIE) 3654 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3655 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3656 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3657 if (BGE_IS_5717_PLUS(sc)) 3658 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3659 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3660 bge_read_eeprom(sc, (void *)&hwcfg, 3661 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3662 hwcfg = be32toh(hwcfg); 3663 } 3664 aprint_normal_dev(sc->bge_dev, 3665 "HW config %08x, %08x, %08x, %08x %08x\n", 3666 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3667 3668 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3669 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3670 3671 if (bge_chipinit(sc)) { 3672 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3673 bge_release_resources(sc); 3674 return; 3675 } 3676 3677 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3678 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3679 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3680 DELAY(100); 3681 } 3682 3683 /* Set MI_MODE */ 3684 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3685 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3686 mimode |= BGE_MIMODE_500KHZ_CONST; 3687 else 3688 mimode |= BGE_MIMODE_BASE; 3689 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3690 DELAY(80); 3691 3692 /* 3693 * Get station address from the EEPROM. 3694 */ 3695 if (bge_get_eaddr(sc, eaddr)) { 3696 aprint_error_dev(sc->bge_dev, 3697 "failed to read station address\n"); 3698 bge_release_resources(sc); 3699 return; 3700 } 3701 3702 br = bge_lookup_rev(sc->bge_chipid); 3703 3704 if (br == NULL) { 3705 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3706 sc->bge_chipid); 3707 } else { 3708 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3709 br->br_name, sc->bge_chipid); 3710 } 3711 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3712 3713 /* Allocate the general information block and ring buffers. */ 3714 if (pci_dma64_available(pa)) { 3715 sc->bge_dmatag = pa->pa_dmat64; 3716 sc->bge_dmatag32 = pa->pa_dmat; 3717 sc->bge_dma64 = true; 3718 } else { 3719 sc->bge_dmatag = pa->pa_dmat; 3720 sc->bge_dmatag32 = pa->pa_dmat; 3721 sc->bge_dma64 = false; 3722 } 3723 3724 /* 40bit DMA workaround */ 3725 if (sizeof(bus_addr_t) > 4) { 3726 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3727 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3728 3729 if (bus_dmatag_subregion(olddmatag, 0, 3730 (bus_addr_t)__MASK(40), 3731 &(sc->bge_dmatag), BUS_DMA_NOWAIT) != 0) { 3732 aprint_error_dev(self, 3733 "WARNING: failed to restrict dma range," 3734 " falling back to parent bus dma range\n"); 3735 sc->bge_dmatag = olddmatag; 3736 } 3737 } 3738 } 3739 SLIST_INIT(&sc->txdma_list); 3740 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3741 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3742 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3743 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3744 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3745 return; 3746 } 3747 DPRINTFN(5, ("bus_dmamem_map\n")); 3748 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3749 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3750 BUS_DMA_NOWAIT)) { 3751 aprint_error_dev(sc->bge_dev, 3752 "can't map DMA buffers (%zu bytes)\n", 3753 sizeof(struct bge_ring_data)); 3754 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3755 sc->bge_ring_rseg); 3756 return; 3757 } 3758 DPRINTFN(5, ("bus_dmamem_create\n")); 3759 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3760 sizeof(struct bge_ring_data), 0, 3761 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3762 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3763 bus_dmamem_unmap(sc->bge_dmatag, kva, 3764 sizeof(struct bge_ring_data)); 3765 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3766 sc->bge_ring_rseg); 3767 return; 3768 } 3769 DPRINTFN(5, ("bus_dmamem_load\n")); 3770 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3771 sizeof(struct bge_ring_data), NULL, 3772 BUS_DMA_NOWAIT)) { 3773 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3774 bus_dmamem_unmap(sc->bge_dmatag, kva, 3775 sizeof(struct bge_ring_data)); 3776 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3777 sc->bge_ring_rseg); 3778 return; 3779 } 3780 3781 DPRINTFN(5, ("bzero\n")); 3782 sc->bge_rdata = (struct bge_ring_data *)kva; 3783 3784 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3785 3786 /* Try to allocate memory for jumbo buffers. */ 3787 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3788 if (bge_alloc_jumbo_mem(sc)) { 3789 aprint_error_dev(sc->bge_dev, 3790 "jumbo buffer allocation failed\n"); 3791 } else 3792 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3793 } 3794 3795 /* Set default tuneable values. */ 3796 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3797 sc->bge_rx_coal_ticks = 150; 3798 sc->bge_rx_max_coal_bds = 64; 3799 sc->bge_tx_coal_ticks = 300; 3800 sc->bge_tx_max_coal_bds = 400; 3801 if (BGE_IS_5705_PLUS(sc)) { 3802 sc->bge_tx_coal_ticks = (12 * 5); 3803 sc->bge_tx_max_coal_bds = (12 * 5); 3804 aprint_verbose_dev(sc->bge_dev, 3805 "setting short Tx thresholds\n"); 3806 } 3807 3808 if (BGE_IS_5717_PLUS(sc)) 3809 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3810 else if (BGE_IS_5705_PLUS(sc)) 3811 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3812 else 3813 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3814 3815 /* Set up ifnet structure */ 3816 ifp = &sc->ethercom.ec_if; 3817 ifp->if_softc = sc; 3818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3819 ifp->if_ioctl = bge_ioctl; 3820 ifp->if_stop = bge_stop; 3821 ifp->if_start = bge_start; 3822 ifp->if_init = bge_init; 3823 ifp->if_watchdog = bge_watchdog; 3824 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3825 IFQ_SET_READY(&ifp->if_snd); 3826 DPRINTFN(5, ("strcpy if_xname\n")); 3827 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3828 3829 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3830 sc->ethercom.ec_if.if_capabilities |= 3831 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3832 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3833 sc->ethercom.ec_if.if_capabilities |= 3834 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3835 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3836 #endif 3837 sc->ethercom.ec_capabilities |= 3838 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3839 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3840 3841 if (sc->bge_flags & BGEF_TSO) 3842 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3843 3844 /* 3845 * Do MII setup. 3846 */ 3847 DPRINTFN(5, ("mii setup\n")); 3848 mii->mii_ifp = ifp; 3849 mii->mii_readreg = bge_miibus_readreg; 3850 mii->mii_writereg = bge_miibus_writereg; 3851 mii->mii_statchg = bge_miibus_statchg; 3852 3853 /* 3854 * Figure out what sort of media we have by checking the hardware 3855 * config word. Note: on some BCM5700 cards, this value appears to be 3856 * unset. If that's the case, we have to rely on identifying the NIC 3857 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3858 * The SysKonnect SK-9D41 is a 1000baseSX card. 3859 */ 3860 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3861 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3862 if (BGE_IS_5705_PLUS(sc)) { 3863 sc->bge_flags |= BGEF_FIBER_MII; 3864 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3865 } else 3866 sc->bge_flags |= BGEF_FIBER_TBI; 3867 } 3868 3869 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3870 if (BGE_IS_JUMBO_CAPABLE(sc)) 3871 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3872 3873 /* set phyflags and chipid before mii_attach() */ 3874 dict = device_properties(self); 3875 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3876 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3877 3878 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3879 macmode &= ~BGE_MACMODE_PORTMODE; 3880 /* Initialize ifmedia structures. */ 3881 if (sc->bge_flags & BGEF_FIBER_TBI) { 3882 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3883 macmode | BGE_PORTMODE_TBI); 3884 DELAY(40); 3885 3886 sc->ethercom.ec_ifmedia = &sc->bge_ifmedia; 3887 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3888 bge_ifmedia_sts); 3889 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3890 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3891 0, NULL); 3892 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3893 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3894 /* Pretend the user requested this setting */ 3895 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3896 } else { 3897 uint16_t phyreg; 3898 int rv; 3899 /* 3900 * Do transceiver setup and tell the firmware the 3901 * driver is down so we can try to get access the 3902 * probe if ASF is running. Retry a couple of times 3903 * if we get a conflict with the ASF firmware accessing 3904 * the PHY. 3905 */ 3906 if (sc->bge_flags & BGEF_FIBER_MII) 3907 macmode |= BGE_PORTMODE_GMII; 3908 else 3909 macmode |= BGE_PORTMODE_MII; 3910 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3911 DELAY(40); 3912 3913 /* 3914 * Do transceiver setup and tell the firmware the 3915 * driver is down so we can try to get access the 3916 * probe if ASF is running. Retry a couple of times 3917 * if we get a conflict with the ASF firmware accessing 3918 * the PHY. 3919 */ 3920 trys = 0; 3921 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3922 sc->ethercom.ec_mii = mii; 3923 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3924 bge_ifmedia_sts); 3925 mii_flags = MIIF_DOPAUSE; 3926 if (sc->bge_flags & BGEF_FIBER_MII) 3927 mii_flags |= MIIF_HAVEFIBER; 3928 again: 3929 bge_asf_driver_up(sc); 3930 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 3931 MII_BMCR, &phyreg); 3932 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 3933 int i; 3934 3935 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 3936 MII_BMCR, BMCR_RESET); 3937 /* Wait up to 500ms for it to complete. */ 3938 for (i = 0; i < 500; i++) { 3939 bge_miibus_readreg(sc->bge_dev, 3940 sc->bge_phy_addr, MII_BMCR, &phyreg); 3941 if ((phyreg & BMCR_RESET) == 0) 3942 break; 3943 DELAY(1000); 3944 } 3945 } 3946 3947 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 3948 MII_OFFSET_ANY, mii_flags); 3949 3950 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 3951 goto again; 3952 3953 if (LIST_EMPTY(&mii->mii_phys)) { 3954 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3955 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 3956 0, NULL); 3957 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 3958 } else 3959 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 3960 3961 /* 3962 * Now tell the firmware we are going up after probing the PHY 3963 */ 3964 if (sc->bge_asf_mode & ASF_STACKUP) 3965 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3966 } 3967 3968 /* 3969 * Call MI attach routine. 3970 */ 3971 DPRINTFN(5, ("if_attach\n")); 3972 if_attach(ifp); 3973 if_deferred_start_init(ifp, NULL); 3974 DPRINTFN(5, ("ether_ifattach\n")); 3975 ether_ifattach(ifp, eaddr); 3976 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3977 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3978 RND_TYPE_NET, RND_FLAG_DEFAULT); 3979 #ifdef BGE_EVENT_COUNTERS 3980 /* 3981 * Attach event counters. 3982 */ 3983 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3984 NULL, device_xname(sc->bge_dev), "intr"); 3985 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 3986 NULL, device_xname(sc->bge_dev), "intr_spurious"); 3987 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 3988 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 3989 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3990 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3991 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3992 NULL, device_xname(sc->bge_dev), "tx_xon"); 3993 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3994 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3995 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3996 NULL, device_xname(sc->bge_dev), "rx_xon"); 3997 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3998 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3999 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4000 NULL, device_xname(sc->bge_dev), "xoffentered"); 4001 #endif /* BGE_EVENT_COUNTERS */ 4002 DPRINTFN(5, ("callout_init\n")); 4003 callout_init(&sc->bge_timeout, 0); 4004 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4005 4006 if (pmf_device_register(self, NULL, NULL)) 4007 pmf_class_network_register(self, ifp); 4008 else 4009 aprint_error_dev(self, "couldn't establish power handler\n"); 4010 4011 bge_sysctl_init(sc); 4012 4013 #ifdef BGE_DEBUG 4014 bge_debug_info(sc); 4015 #endif 4016 } 4017 4018 /* 4019 * Stop all chip I/O so that the kernel's probe routines don't 4020 * get confused by errant DMAs when rebooting. 4021 */ 4022 static int 4023 bge_detach(device_t self, int flags __unused) 4024 { 4025 struct bge_softc * const sc = device_private(self); 4026 struct ifnet * const ifp = &sc->ethercom.ec_if; 4027 int s; 4028 4029 s = splnet(); 4030 /* Stop the interface. Callouts are stopped in it. */ 4031 bge_stop(ifp, 1); 4032 splx(s); 4033 4034 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4035 4036 ether_ifdetach(ifp); 4037 if_detach(ifp); 4038 4039 /* Delete all remaining media. */ 4040 ifmedia_fini(&sc->bge_mii.mii_media); 4041 4042 bge_release_resources(sc); 4043 4044 return 0; 4045 } 4046 4047 static void 4048 bge_release_resources(struct bge_softc *sc) 4049 { 4050 4051 /* Detach sysctl */ 4052 if (sc->bge_log != NULL) 4053 sysctl_teardown(&sc->bge_log); 4054 4055 #ifdef BGE_EVENT_COUNTERS 4056 /* Detach event counters. */ 4057 evcnt_detach(&sc->bge_ev_intr); 4058 evcnt_detach(&sc->bge_ev_intr_spurious); 4059 evcnt_detach(&sc->bge_ev_intr_spurious2); 4060 evcnt_detach(&sc->bge_ev_tx_xoff); 4061 evcnt_detach(&sc->bge_ev_tx_xon); 4062 evcnt_detach(&sc->bge_ev_rx_xoff); 4063 evcnt_detach(&sc->bge_ev_rx_xon); 4064 evcnt_detach(&sc->bge_ev_rx_macctl); 4065 evcnt_detach(&sc->bge_ev_xoffentered); 4066 #endif /* BGE_EVENT_COUNTERS */ 4067 4068 /* Disestablish the interrupt handler */ 4069 if (sc->bge_intrhand != NULL) { 4070 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4071 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4072 sc->bge_intrhand = NULL; 4073 } 4074 4075 if (sc->bge_dmatag != NULL) { 4076 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4077 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4078 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4079 sizeof(struct bge_ring_data)); 4080 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4081 sc->bge_ring_rseg); 4082 } 4083 4084 /* Unmap the device registers */ 4085 if (sc->bge_bsize != 0) { 4086 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4087 sc->bge_bsize = 0; 4088 } 4089 4090 /* Unmap the APE registers */ 4091 if (sc->bge_apesize != 0) { 4092 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4093 sc->bge_apesize); 4094 sc->bge_apesize = 0; 4095 } 4096 } 4097 4098 static int 4099 bge_reset(struct bge_softc *sc) 4100 { 4101 uint32_t cachesize, command; 4102 uint32_t reset, mac_mode, mac_mode_mask; 4103 pcireg_t devctl, reg; 4104 int i, val; 4105 void (*write_op)(struct bge_softc *, int, int); 4106 4107 /* Make mask for BGE_MAC_MODE register. */ 4108 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4109 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4110 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4111 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4112 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4113 4114 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4115 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4116 if (sc->bge_flags & BGEF_PCIE) 4117 write_op = bge_writemem_direct; 4118 else 4119 write_op = bge_writemem_ind; 4120 } else 4121 write_op = bge_writereg_ind; 4122 4123 /* 57XX step 4 */ 4124 /* Acquire the NVM lock */ 4125 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4126 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4127 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4128 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4129 for (i = 0; i < 8000; i++) { 4130 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4131 BGE_NVRAMSWARB_GNT1) 4132 break; 4133 DELAY(20); 4134 } 4135 if (i == 8000) { 4136 printf("%s: NVRAM lock timedout!\n", 4137 device_xname(sc->bge_dev)); 4138 } 4139 } 4140 4141 /* Take APE lock when performing reset. */ 4142 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4143 4144 /* 57XX step 3 */ 4145 /* Save some important PCI state. */ 4146 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4147 /* 5718 reset step 3 */ 4148 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4149 4150 /* 5718 reset step 5, 57XX step 5b-5d */ 4151 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4152 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4153 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4154 4155 /* XXX ???: Disable fastboot on controllers that support it. */ 4156 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4157 BGE_IS_5755_PLUS(sc)) 4158 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4159 4160 /* 5718 reset step 2, 57XX step 6 */ 4161 /* 4162 * Write the magic number to SRAM at offset 0xB50. 4163 * When firmware finishes its initialization it will 4164 * write ~BGE_MAGIC_NUMBER to the same location. 4165 */ 4166 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4167 4168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4169 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4170 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4171 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4172 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4173 } 4174 4175 /* 5718 reset step 6, 57XX step 7 */ 4176 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4177 /* 4178 * XXX: from FreeBSD/Linux; no documentation 4179 */ 4180 if (sc->bge_flags & BGEF_PCIE) { 4181 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4182 !BGE_IS_57765_PLUS(sc) && 4183 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4184 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4185 /* PCI Express 1.0 system */ 4186 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4187 BGE_PHY_PCIE_SCRAM_MODE); 4188 } 4189 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4190 /* 4191 * Prevent PCI Express link training 4192 * during global reset. 4193 */ 4194 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4195 reset |= (1 << 29); 4196 } 4197 } 4198 4199 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4200 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4201 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4202 i | BGE_VCPU_STATUS_DRV_RESET); 4203 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4204 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4205 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4206 } 4207 4208 /* 4209 * Set GPHY Power Down Override to leave GPHY 4210 * powered up in D0 uninitialized. 4211 */ 4212 if (BGE_IS_5705_PLUS(sc) && 4213 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4214 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4215 4216 /* Issue global reset */ 4217 write_op(sc, BGE_MISC_CFG, reset); 4218 4219 /* 5718 reset step 7, 57XX step 8 */ 4220 if (sc->bge_flags & BGEF_PCIE) 4221 delay(100*1000); /* too big */ 4222 else 4223 delay(1000); 4224 4225 if (sc->bge_flags & BGEF_PCIE) { 4226 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4227 DELAY(500000); 4228 /* XXX: Magic Numbers */ 4229 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4230 BGE_PCI_UNKNOWN0); 4231 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4232 BGE_PCI_UNKNOWN0, 4233 reg | (1 << 15)); 4234 } 4235 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4236 sc->bge_pciecap + PCIE_DCSR); 4237 /* Clear enable no snoop and disable relaxed ordering. */ 4238 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4239 PCIE_DCSR_ENA_NO_SNOOP); 4240 4241 /* Set PCIE max payload size to 128 for older PCIe devices */ 4242 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4243 devctl &= ~(0x00e0); 4244 /* Clear device status register. Write 1b to clear */ 4245 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4246 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4247 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4248 sc->bge_pciecap + PCIE_DCSR, devctl); 4249 bge_set_max_readrq(sc); 4250 } 4251 4252 /* From Linux: dummy read to flush PCI posted writes */ 4253 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4254 4255 /* 4256 * Reset some of the PCI state that got zapped by reset 4257 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4258 * set, too. 4259 */ 4260 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4261 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4262 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4263 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4264 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4265 (sc->bge_flags & BGEF_PCIX) != 0) 4266 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4267 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4268 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4269 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4270 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4271 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4272 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4273 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4274 4275 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4276 if (sc->bge_flags & BGEF_PCIX) { 4277 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4278 + PCIX_CMD); 4279 /* Set max memory read byte count to 2K */ 4280 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4281 reg &= ~PCIX_CMD_BYTECNT_MASK; 4282 reg |= PCIX_CMD_BCNT_2048; 4283 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4284 /* 4285 * For 5704, set max outstanding split transaction 4286 * field to 0 (0 means it supports 1 request) 4287 */ 4288 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4289 | PCIX_CMD_BYTECNT_MASK); 4290 reg |= PCIX_CMD_BCNT_2048; 4291 } 4292 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4293 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4294 } 4295 4296 /* 5718 reset step 10, 57XX step 12 */ 4297 /* Enable memory arbiter. */ 4298 if (BGE_IS_5714_FAMILY(sc)) { 4299 val = CSR_READ_4(sc, BGE_MARB_MODE); 4300 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4301 } else 4302 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4303 4304 /* XXX 5721, 5751 and 5752 */ 4305 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4306 /* Step 19: */ 4307 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4308 /* Step 20: */ 4309 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4310 } 4311 4312 /* 5718 reset step 12, 57XX step 15 and 16 */ 4313 /* Fix up byte swapping */ 4314 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4315 4316 /* 5718 reset step 13, 57XX step 17 */ 4317 /* Poll until the firmware initialization is complete */ 4318 bge_poll_fw(sc); 4319 4320 /* 57XX step 21 */ 4321 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4322 pcireg_t msidata; 4323 4324 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4325 BGE_PCI_MSI_DATA); 4326 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4327 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4328 msidata); 4329 } 4330 4331 /* 57XX step 18 */ 4332 /* Write mac mode. */ 4333 val = CSR_READ_4(sc, BGE_MAC_MODE); 4334 /* Restore mac_mode_mask's bits using mac_mode */ 4335 val = (val & ~mac_mode_mask) | mac_mode; 4336 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4337 DELAY(40); 4338 4339 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4340 4341 /* 4342 * The 5704 in TBI mode apparently needs some special 4343 * adjustment to insure the SERDES drive level is set 4344 * to 1.2V. 4345 */ 4346 if (sc->bge_flags & BGEF_FIBER_TBI && 4347 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4348 uint32_t serdescfg; 4349 4350 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4351 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4352 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4353 } 4354 4355 if (sc->bge_flags & BGEF_PCIE && 4356 !BGE_IS_57765_PLUS(sc) && 4357 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4358 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4359 uint32_t v; 4360 4361 /* Enable PCI Express bug fix */ 4362 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4363 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4364 v | BGE_TLP_DATA_FIFO_PROTECT); 4365 } 4366 4367 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4368 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4369 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4370 4371 return 0; 4372 } 4373 4374 /* 4375 * Frame reception handling. This is called if there's a frame 4376 * on the receive return list. 4377 * 4378 * Note: we have to be able to handle two possibilities here: 4379 * 1) the frame is from the jumbo receive ring 4380 * 2) the frame is from the standard receive ring 4381 */ 4382 4383 static void 4384 bge_rxeof(struct bge_softc *sc) 4385 { 4386 struct ifnet * const ifp = &sc->ethercom.ec_if; 4387 uint16_t rx_prod, rx_cons; 4388 int stdcnt = 0, jumbocnt = 0; 4389 bus_dmamap_t dmamap; 4390 bus_addr_t offset, toff; 4391 bus_size_t tlen; 4392 int tosync; 4393 4394 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4395 offsetof(struct bge_ring_data, bge_status_block), 4396 sizeof(struct bge_status_block), 4397 BUS_DMASYNC_POSTREAD); 4398 4399 rx_cons = sc->bge_rx_saved_considx; 4400 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4401 4402 /* Nothing to do */ 4403 if (rx_cons == rx_prod) 4404 return; 4405 4406 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4407 tosync = rx_prod - rx_cons; 4408 4409 if (tosync != 0) 4410 rnd_add_uint32(&sc->rnd_source, tosync); 4411 4412 toff = offset + (rx_cons * sizeof(struct bge_rx_bd)); 4413 4414 if (tosync < 0) { 4415 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4416 sizeof(struct bge_rx_bd); 4417 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4418 toff, tlen, BUS_DMASYNC_POSTREAD); 4419 tosync = -tosync; 4420 } 4421 4422 if (tosync != 0) { 4423 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4424 offset, tosync * sizeof(struct bge_rx_bd), 4425 BUS_DMASYNC_POSTREAD); 4426 } 4427 4428 while (rx_cons != rx_prod) { 4429 struct bge_rx_bd *cur_rx; 4430 uint32_t rxidx; 4431 struct mbuf *m = NULL; 4432 4433 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4434 4435 rxidx = cur_rx->bge_idx; 4436 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4437 4438 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4439 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4440 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4441 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4442 jumbocnt++; 4443 bus_dmamap_sync(sc->bge_dmatag, 4444 sc->bge_cdata.bge_rx_jumbo_map, 4445 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4446 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4447 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4448 if_statinc(ifp, if_ierrors); 4449 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4450 continue; 4451 } 4452 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4453 NULL) == ENOBUFS) { 4454 if_statinc(ifp, if_ierrors); 4455 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4456 continue; 4457 } 4458 } else { 4459 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4460 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4461 4462 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4463 stdcnt++; 4464 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4465 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4466 if (dmamap == NULL) { 4467 if_statinc(ifp, if_ierrors); 4468 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4469 continue; 4470 } 4471 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4472 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4473 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4474 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4475 if_statinc(ifp, if_ierrors); 4476 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4477 continue; 4478 } 4479 if (bge_newbuf_std(sc, sc->bge_std, 4480 NULL, dmamap) == ENOBUFS) { 4481 if_statinc(ifp, if_ierrors); 4482 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4483 continue; 4484 } 4485 } 4486 4487 #ifndef __NO_STRICT_ALIGNMENT 4488 /* 4489 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4490 * the Rx buffer has the layer-2 header unaligned. 4491 * If our CPU requires alignment, re-align by copying. 4492 */ 4493 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4494 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4495 cur_rx->bge_len); 4496 m->m_data += ETHER_ALIGN; 4497 } 4498 #endif 4499 4500 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4501 m_set_rcvif(m, ifp); 4502 4503 bge_rxcsum(sc, cur_rx, m); 4504 4505 /* 4506 * If we received a packet with a vlan tag, pass it 4507 * to vlan_input() instead of ether_input(). 4508 */ 4509 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4510 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4511 4512 if_percpuq_enqueue(ifp->if_percpuq, m); 4513 } 4514 4515 sc->bge_rx_saved_considx = rx_cons; 4516 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4517 if (stdcnt) 4518 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4519 if (jumbocnt) 4520 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4521 } 4522 4523 static void 4524 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4525 { 4526 4527 if (BGE_IS_57765_PLUS(sc)) { 4528 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4529 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4530 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4531 if ((cur_rx->bge_error_flag & 4532 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4533 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4534 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4535 m->m_pkthdr.csum_data = 4536 cur_rx->bge_tcp_udp_csum; 4537 m->m_pkthdr.csum_flags |= 4538 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4539 } 4540 } 4541 } else { 4542 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4543 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4544 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4545 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4546 /* 4547 * Rx transport checksum-offload may also 4548 * have bugs with packets which, when transmitted, 4549 * were `runts' requiring padding. 4550 */ 4551 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4552 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4553 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4554 m->m_pkthdr.csum_data = 4555 cur_rx->bge_tcp_udp_csum; 4556 m->m_pkthdr.csum_flags |= 4557 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4558 } 4559 } 4560 } 4561 4562 static void 4563 bge_txeof(struct bge_softc *sc) 4564 { 4565 struct ifnet * const ifp = &sc->ethercom.ec_if; 4566 struct bge_tx_bd *cur_tx = NULL; 4567 struct txdmamap_pool_entry *dma; 4568 bus_addr_t offset, toff; 4569 bus_size_t tlen; 4570 int tosync; 4571 struct mbuf *m; 4572 4573 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4574 offsetof(struct bge_ring_data, bge_status_block), 4575 sizeof(struct bge_status_block), 4576 BUS_DMASYNC_POSTREAD); 4577 4578 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4579 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4580 sc->bge_tx_saved_considx; 4581 4582 if (tosync != 0) 4583 rnd_add_uint32(&sc->rnd_source, tosync); 4584 4585 toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd)); 4586 4587 if (tosync < 0) { 4588 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4589 sizeof(struct bge_tx_bd); 4590 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4591 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4592 tosync = -tosync; 4593 } 4594 4595 if (tosync != 0) { 4596 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4597 offset, tosync * sizeof(struct bge_tx_bd), 4598 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4599 } 4600 4601 /* 4602 * Go through our tx ring and free mbufs for those 4603 * frames that have been sent. 4604 */ 4605 while (sc->bge_tx_saved_considx != 4606 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4607 uint32_t idx = sc->bge_tx_saved_considx; 4608 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4609 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4610 if_statinc(ifp, if_opackets); 4611 m = sc->bge_cdata.bge_tx_chain[idx]; 4612 if (m != NULL) { 4613 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4614 dma = sc->txdma[idx]; 4615 if (dma->is_dma32) { 4616 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4617 0, dma->dmamap32->dm_mapsize, 4618 BUS_DMASYNC_POSTWRITE); 4619 bus_dmamap_unload( 4620 sc->bge_dmatag32, dma->dmamap32); 4621 } else { 4622 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4623 0, dma->dmamap->dm_mapsize, 4624 BUS_DMASYNC_POSTWRITE); 4625 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4626 } 4627 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4628 sc->txdma[idx] = NULL; 4629 4630 m_freem(m); 4631 } 4632 sc->bge_txcnt--; 4633 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4634 ifp->if_timer = 0; 4635 } 4636 4637 if (cur_tx != NULL) 4638 ifp->if_flags &= ~IFF_OACTIVE; 4639 } 4640 4641 static int 4642 bge_intr(void *xsc) 4643 { 4644 struct bge_softc * const sc = xsc; 4645 struct ifnet * const ifp = &sc->ethercom.ec_if; 4646 uint32_t pcistate, statusword, statustag; 4647 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4648 4649 4650 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4651 if (BGE_IS_5717_PLUS(sc)) 4652 intrmask = 0; 4653 4654 /* 4655 * It is possible for the interrupt to arrive before 4656 * the status block is updated prior to the interrupt. 4657 * Reading the PCI State register will confirm whether the 4658 * interrupt is ours and will flush the status block. 4659 */ 4660 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4661 4662 /* read status word from status block */ 4663 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4664 offsetof(struct bge_ring_data, bge_status_block), 4665 sizeof(struct bge_status_block), 4666 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4667 statusword = sc->bge_rdata->bge_status_block.bge_status; 4668 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4669 4670 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4671 if (sc->bge_lasttag == statustag && 4672 (~pcistate & intrmask)) { 4673 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4674 return 0; 4675 } 4676 sc->bge_lasttag = statustag; 4677 } else { 4678 if (!(statusword & BGE_STATFLAG_UPDATED) && 4679 !(~pcistate & intrmask)) { 4680 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4681 return 0; 4682 } 4683 statustag = 0; 4684 } 4685 /* Ack interrupt and stop others from occurring. */ 4686 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4687 BGE_EVCNT_INCR(sc->bge_ev_intr); 4688 4689 /* clear status word */ 4690 sc->bge_rdata->bge_status_block.bge_status = 0; 4691 4692 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4693 offsetof(struct bge_ring_data, bge_status_block), 4694 sizeof(struct bge_status_block), 4695 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4696 4697 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4698 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4699 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4700 bge_link_upd(sc); 4701 4702 if (ifp->if_flags & IFF_RUNNING) { 4703 /* Check RX return ring producer/consumer */ 4704 bge_rxeof(sc); 4705 4706 /* Check TX ring producer/consumer */ 4707 bge_txeof(sc); 4708 } 4709 4710 if (sc->bge_pending_rxintr_change) { 4711 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4712 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4713 4714 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4715 DELAY(10); 4716 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4717 4718 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4719 DELAY(10); 4720 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4721 4722 sc->bge_pending_rxintr_change = 0; 4723 } 4724 bge_handle_events(sc); 4725 4726 /* Re-enable interrupts. */ 4727 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4728 4729 if (ifp->if_flags & IFF_RUNNING) 4730 if_schedule_deferred_start(ifp); 4731 4732 return 1; 4733 } 4734 4735 static void 4736 bge_asf_driver_up(struct bge_softc *sc) 4737 { 4738 if (sc->bge_asf_mode & ASF_STACKUP) { 4739 /* Send ASF heartbeat aprox. every 2s */ 4740 if (sc->bge_asf_count) 4741 sc->bge_asf_count --; 4742 else { 4743 sc->bge_asf_count = 2; 4744 4745 bge_wait_for_event_ack(sc); 4746 4747 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4748 BGE_FW_CMD_DRV_ALIVE3); 4749 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4750 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4751 BGE_FW_HB_TIMEOUT_SEC); 4752 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4753 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4754 BGE_RX_CPU_DRV_EVENT); 4755 } 4756 } 4757 } 4758 4759 static void 4760 bge_tick(void *xsc) 4761 { 4762 struct bge_softc * const sc = xsc; 4763 struct mii_data * const mii = &sc->bge_mii; 4764 int s; 4765 4766 s = splnet(); 4767 4768 if (BGE_IS_5705_PLUS(sc)) 4769 bge_stats_update_regs(sc); 4770 else 4771 bge_stats_update(sc); 4772 4773 if (sc->bge_flags & BGEF_FIBER_TBI) { 4774 /* 4775 * Since in TBI mode auto-polling can't be used we should poll 4776 * link status manually. Here we register pending link event 4777 * and trigger interrupt. 4778 */ 4779 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4780 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4781 } else { 4782 /* 4783 * Do not touch PHY if we have link up. This could break 4784 * IPMI/ASF mode or produce extra input errors. 4785 * (extra input errors was reported for bcm5701 & bcm5704). 4786 */ 4787 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4788 mii_tick(mii); 4789 } 4790 4791 bge_asf_driver_up(sc); 4792 4793 if (!sc->bge_detaching) 4794 callout_schedule(&sc->bge_timeout, hz); 4795 4796 splx(s); 4797 } 4798 4799 static void 4800 bge_stats_update_regs(struct bge_softc *sc) 4801 { 4802 struct ifnet *const ifp = &sc->ethercom.ec_if; 4803 4804 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4805 4806 if_statadd_ref(nsr, if_collisions, 4807 CSR_READ_4(sc, BGE_MAC_STATS + 4808 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4809 4810 /* 4811 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4812 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4813 * (silicon bug). There's no reliable workaround so just 4814 * ignore the counter 4815 */ 4816 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4817 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4818 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4819 if_statadd_ref(nsr, if_ierrors, 4820 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4821 } 4822 if_statadd_ref(nsr, if_ierrors, 4823 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4824 if_statadd_ref(nsr, if_ierrors, 4825 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4826 4827 IF_STAT_PUTREF(ifp); 4828 4829 if (sc->bge_flags & BGEF_RDMA_BUG) { 4830 uint32_t val, ucast, mcast, bcast; 4831 4832 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4833 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4834 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4835 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4836 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4837 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4838 4839 /* 4840 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4841 * frames, it's safe to disable workaround for DMA engine's 4842 * miscalculation of TXMBUF space. 4843 */ 4844 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4845 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4846 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4847 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4848 else 4849 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4850 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4851 sc->bge_flags &= ~BGEF_RDMA_BUG; 4852 } 4853 } 4854 } 4855 4856 static void 4857 bge_stats_update(struct bge_softc *sc) 4858 { 4859 struct ifnet * const ifp = &sc->ethercom.ec_if; 4860 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4861 4862 #define READ_STAT(sc, stats, stat) \ 4863 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4864 4865 uint64_t collisions = 4866 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4867 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4868 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4869 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4870 4871 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4872 sc->bge_if_collisions = collisions; 4873 4874 4875 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4876 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4877 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4878 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4879 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4880 READ_STAT(sc, stats, 4881 xoffPauseFramesReceived.bge_addr_lo)); 4882 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4883 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4884 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4885 READ_STAT(sc, stats, 4886 macControlFramesReceived.bge_addr_lo)); 4887 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4888 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4889 4890 #undef READ_STAT 4891 4892 #ifdef notdef 4893 ifp->if_collisions += 4894 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4895 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4896 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4897 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4898 ifp->if_collisions; 4899 #endif 4900 } 4901 4902 /* 4903 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4904 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4905 * but when such padded frames employ the bge IP/TCP checksum offload, 4906 * the hardware checksum assist gives incorrect results (possibly 4907 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4908 * If we pad such runts with zeros, the onboard checksum comes out correct. 4909 */ 4910 static inline int 4911 bge_cksum_pad(struct mbuf *pkt) 4912 { 4913 struct mbuf *last = NULL; 4914 int padlen; 4915 4916 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4917 4918 /* if there's only the packet-header and we can pad there, use it. */ 4919 if (pkt->m_pkthdr.len == pkt->m_len && 4920 M_TRAILINGSPACE(pkt) >= padlen) { 4921 last = pkt; 4922 } else { 4923 /* 4924 * Walk packet chain to find last mbuf. We will either 4925 * pad there, or append a new mbuf and pad it 4926 * (thus perhaps avoiding the bcm5700 dma-min bug). 4927 */ 4928 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4929 continue; /* do nothing */ 4930 } 4931 4932 /* `last' now points to last in chain. */ 4933 if (M_TRAILINGSPACE(last) < padlen) { 4934 /* Allocate new empty mbuf, pad it. Compact later. */ 4935 struct mbuf *n; 4936 MGET(n, M_DONTWAIT, MT_DATA); 4937 if (n == NULL) 4938 return ENOBUFS; 4939 n->m_len = 0; 4940 last->m_next = n; 4941 last = n; 4942 } 4943 } 4944 4945 KDASSERT(!M_READONLY(last)); 4946 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4947 4948 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4949 memset(mtod(last, char *) + last->m_len, 0, padlen); 4950 last->m_len += padlen; 4951 pkt->m_pkthdr.len += padlen; 4952 return 0; 4953 } 4954 4955 /* 4956 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4957 */ 4958 static inline int 4959 bge_compact_dma_runt(struct mbuf *pkt) 4960 { 4961 struct mbuf *m, *prev; 4962 int totlen; 4963 4964 prev = NULL; 4965 totlen = 0; 4966 4967 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 4968 int mlen = m->m_len; 4969 int shortfall = 8 - mlen ; 4970 4971 totlen += mlen; 4972 if (mlen == 0) 4973 continue; 4974 if (mlen >= 8) 4975 continue; 4976 4977 /* 4978 * If we get here, mbuf data is too small for DMA engine. 4979 * Try to fix by shuffling data to prev or next in chain. 4980 * If that fails, do a compacting deep-copy of the whole chain. 4981 */ 4982 4983 /* Internal frag. If fits in prev, copy it there. */ 4984 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 4985 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 4986 prev->m_len += mlen; 4987 m->m_len = 0; 4988 /* XXX stitch chain */ 4989 prev->m_next = m_free(m); 4990 m = prev; 4991 continue; 4992 } else if (m->m_next != NULL && 4993 M_TRAILINGSPACE(m) >= shortfall && 4994 m->m_next->m_len >= (8 + shortfall)) { 4995 /* m is writable and have enough data in next, pull up. */ 4996 4997 memcpy(m->m_data + m->m_len, m->m_next->m_data, 4998 shortfall); 4999 m->m_len += shortfall; 5000 m->m_next->m_len -= shortfall; 5001 m->m_next->m_data += shortfall; 5002 } else if (m->m_next == NULL || 1) { 5003 /* 5004 * Got a runt at the very end of the packet. 5005 * borrow data from the tail of the preceding mbuf and 5006 * update its length in-place. (The original data is 5007 * still valid, so we can do this even if prev is not 5008 * writable.) 5009 */ 5010 5011 /* 5012 * If we'd make prev a runt, just move all of its data. 5013 */ 5014 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5015 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5016 5017 if ((prev->m_len - shortfall) < 8) 5018 shortfall = prev->m_len; 5019 5020 #ifdef notyet /* just do the safe slow thing for now */ 5021 if (!M_READONLY(m)) { 5022 if (M_LEADINGSPACE(m) < shorfall) { 5023 void *m_dat; 5024 m_dat = M_BUFADDR(m); 5025 memmove(m_dat, mtod(m, void*), 5026 m->m_len); 5027 m->m_data = m_dat; 5028 } 5029 } else 5030 #endif /* just do the safe slow thing */ 5031 { 5032 struct mbuf * n = NULL; 5033 int newprevlen = prev->m_len - shortfall; 5034 5035 MGET(n, M_NOWAIT, MT_DATA); 5036 if (n == NULL) 5037 return ENOBUFS; 5038 KASSERT(m->m_len + shortfall < MLEN 5039 /*, 5040 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5041 5042 /* first copy the data we're stealing from prev */ 5043 memcpy(n->m_data, prev->m_data + newprevlen, 5044 shortfall); 5045 5046 /* update prev->m_len accordingly */ 5047 prev->m_len -= shortfall; 5048 5049 /* copy data from runt m */ 5050 memcpy(n->m_data + shortfall, m->m_data, 5051 m->m_len); 5052 5053 /* n holds what we stole from prev, plus m */ 5054 n->m_len = shortfall + m->m_len; 5055 5056 /* stitch n into chain and free m */ 5057 n->m_next = m->m_next; 5058 prev->m_next = n; 5059 /* KASSERT(m->m_next == NULL); */ 5060 m->m_next = NULL; 5061 m_free(m); 5062 m = n; /* for continuing loop */ 5063 } 5064 } 5065 } 5066 return 0; 5067 } 5068 5069 /* 5070 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5071 * pointers to descriptors. 5072 */ 5073 static int 5074 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5075 { 5076 struct ifnet * const ifp = &sc->ethercom.ec_if; 5077 struct bge_tx_bd *f, *prev_f; 5078 uint32_t frag, cur; 5079 uint16_t csum_flags = 0; 5080 uint16_t txbd_tso_flags = 0; 5081 struct txdmamap_pool_entry *dma; 5082 bus_dmamap_t dmamap; 5083 bus_dma_tag_t dmatag; 5084 int i = 0; 5085 int use_tso, maxsegsize, error; 5086 bool have_vtag; 5087 uint16_t vtag; 5088 bool remap; 5089 5090 if (m_head->m_pkthdr.csum_flags) { 5091 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5092 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5093 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5094 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5095 } 5096 5097 /* 5098 * If we were asked to do an outboard checksum, and the NIC 5099 * has the bug where it sometimes adds in the Ethernet padding, 5100 * explicitly pad with zeros so the cksum will be correct either way. 5101 * (For now, do this for all chip versions, until newer 5102 * are confirmed to not require the workaround.) 5103 */ 5104 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5105 #ifdef notyet 5106 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5107 #endif 5108 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5109 goto check_dma_bug; 5110 5111 if (bge_cksum_pad(m_head) != 0) 5112 return ENOBUFS; 5113 5114 check_dma_bug: 5115 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5116 goto doit; 5117 5118 /* 5119 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5120 * less than eight bytes. If we encounter a teeny mbuf 5121 * at the end of a chain, we can pad. Otherwise, copy. 5122 */ 5123 if (bge_compact_dma_runt(m_head) != 0) 5124 return ENOBUFS; 5125 5126 doit: 5127 dma = SLIST_FIRST(&sc->txdma_list); 5128 if (dma == NULL) { 5129 ifp->if_flags |= IFF_OACTIVE; 5130 return ENOBUFS; 5131 } 5132 dmamap = dma->dmamap; 5133 dmatag = sc->bge_dmatag; 5134 dma->is_dma32 = false; 5135 5136 /* 5137 * Set up any necessary TSO state before we start packing... 5138 */ 5139 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5140 if (!use_tso) { 5141 maxsegsize = 0; 5142 } else { /* TSO setup */ 5143 unsigned mss; 5144 struct ether_header *eh; 5145 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5146 unsigned bge_hlen; 5147 struct mbuf * m0 = m_head; 5148 struct ip *ip; 5149 struct tcphdr *th; 5150 int iphl, hlen; 5151 5152 /* 5153 * XXX It would be nice if the mbuf pkthdr had offset 5154 * fields for the protocol headers. 5155 */ 5156 5157 eh = mtod(m0, struct ether_header *); 5158 switch (htons(eh->ether_type)) { 5159 case ETHERTYPE_IP: 5160 offset = ETHER_HDR_LEN; 5161 break; 5162 5163 case ETHERTYPE_VLAN: 5164 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5165 break; 5166 5167 default: 5168 /* 5169 * Don't support this protocol or encapsulation. 5170 */ 5171 return ENOBUFS; 5172 } 5173 5174 /* 5175 * TCP/IP headers are in the first mbuf; we can do 5176 * this the easy way. 5177 */ 5178 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5179 hlen = iphl + offset; 5180 if (__predict_false(m0->m_len < 5181 (hlen + sizeof(struct tcphdr)))) { 5182 5183 aprint_error_dev(sc->bge_dev, 5184 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5185 "not handled yet\n", 5186 m0->m_len, hlen+ sizeof(struct tcphdr)); 5187 #ifdef NOTYET 5188 /* 5189 * XXX jonathan (at) NetBSD.org: untested. 5190 * how to force this branch to be taken? 5191 */ 5192 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5193 5194 m_copydata(m0, offset, sizeof(ip), &ip); 5195 m_copydata(m0, hlen, sizeof(th), &th); 5196 5197 ip.ip_len = 0; 5198 5199 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5200 sizeof(ip.ip_len), &ip.ip_len); 5201 5202 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5203 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5204 5205 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5206 sizeof(th.th_sum), &th.th_sum); 5207 5208 hlen += th.th_off << 2; 5209 iptcp_opt_words = hlen; 5210 #else 5211 /* 5212 * if_wm "hard" case not yet supported, can we not 5213 * mandate it out of existence? 5214 */ 5215 (void) ip; (void)th; (void) ip_tcp_hlen; 5216 5217 return ENOBUFS; 5218 #endif 5219 } else { 5220 ip = (struct ip *) (mtod(m0, char *) + offset); 5221 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5222 ip_tcp_hlen = iphl + (th->th_off << 2); 5223 5224 /* Total IP/TCP options, in 32-bit words */ 5225 iptcp_opt_words = (ip_tcp_hlen 5226 - sizeof(struct tcphdr) 5227 - sizeof(struct ip)) >> 2; 5228 } 5229 if (BGE_IS_575X_PLUS(sc)) { 5230 th->th_sum = 0; 5231 csum_flags = 0; 5232 } else { 5233 /* 5234 * XXX jonathan (at) NetBSD.org: 5705 untested. 5235 * Requires TSO firmware patch for 5701/5703/5704. 5236 */ 5237 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5238 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5239 } 5240 5241 mss = m_head->m_pkthdr.segsz; 5242 txbd_tso_flags |= 5243 BGE_TXBDFLAG_CPU_PRE_DMA | 5244 BGE_TXBDFLAG_CPU_POST_DMA; 5245 5246 /* 5247 * Our NIC TSO-assist assumes TSO has standard, optionless 5248 * IPv4 and TCP headers, which total 40 bytes. By default, 5249 * the NIC copies 40 bytes of IP/TCP header from the 5250 * supplied header into the IP/TCP header portion of 5251 * each post-TSO-segment. If the supplied packet has IP or 5252 * TCP options, we need to tell the NIC to copy those extra 5253 * bytes into each post-TSO header, in addition to the normal 5254 * 40-byte IP/TCP header (and to leave space accordingly). 5255 * Unfortunately, the driver encoding of option length 5256 * varies across different ASIC families. 5257 */ 5258 tcp_seg_flags = 0; 5259 bge_hlen = ip_tcp_hlen >> 2; 5260 if (BGE_IS_5717_PLUS(sc)) { 5261 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5262 txbd_tso_flags |= 5263 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5264 } else if (BGE_IS_5705_PLUS(sc)) { 5265 tcp_seg_flags = bge_hlen << 11; 5266 } else { 5267 /* XXX iptcp_opt_words or bge_hlen ? */ 5268 txbd_tso_flags |= iptcp_opt_words << 12; 5269 } 5270 maxsegsize = mss | tcp_seg_flags; 5271 ip->ip_len = htons(mss + ip_tcp_hlen); 5272 ip->ip_sum = 0; 5273 5274 } /* TSO setup */ 5275 5276 have_vtag = vlan_has_tag(m_head); 5277 if (have_vtag) 5278 vtag = vlan_get_tag(m_head); 5279 5280 /* 5281 * Start packing the mbufs in this chain into 5282 * the fragment pointers. Stop when we run out 5283 * of fragments or hit the end of the mbuf chain. 5284 */ 5285 remap = true; 5286 load_again: 5287 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5288 if (__predict_false(error)) { 5289 if (error == EFBIG && remap) { 5290 struct mbuf *m; 5291 remap = false; 5292 m = m_defrag(m_head, M_NOWAIT); 5293 if (m != NULL) { 5294 KASSERT(m == m_head); 5295 goto load_again; 5296 } 5297 } 5298 return error; 5299 } 5300 /* 5301 * Sanity check: avoid coming within 16 descriptors 5302 * of the end of the ring. 5303 */ 5304 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5305 BGE_TSO_PRINTF(("%s: " 5306 " dmamap_load_mbuf too close to ring wrap\n", 5307 device_xname(sc->bge_dev))); 5308 goto fail_unload; 5309 } 5310 5311 /* Iterate over dmap-map fragments. */ 5312 f = prev_f = NULL; 5313 cur = frag = *txidx; 5314 5315 for (i = 0; i < dmamap->dm_nsegs; i++) { 5316 f = &sc->bge_rdata->bge_tx_ring[frag]; 5317 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5318 break; 5319 5320 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5321 f->bge_len = dmamap->dm_segs[i].ds_len; 5322 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5323 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5324 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5325 (prev_f != NULL && 5326 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5327 ) { 5328 /* 5329 * watchdog timeout issue was observed with TSO, 5330 * limiting DMA address space to 32bits seems to 5331 * address the issue. 5332 */ 5333 bus_dmamap_unload(dmatag, dmamap); 5334 dmatag = sc->bge_dmatag32; 5335 dmamap = dma->dmamap32; 5336 dma->is_dma32 = true; 5337 remap = true; 5338 goto load_again; 5339 } 5340 5341 /* 5342 * For 5751 and follow-ons, for TSO we must turn 5343 * off checksum-assist flag in the tx-descr, and 5344 * supply the ASIC-revision-specific encoding 5345 * of TSO flags and segsize. 5346 */ 5347 if (use_tso) { 5348 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5349 f->bge_rsvd = maxsegsize; 5350 f->bge_flags = csum_flags | txbd_tso_flags; 5351 } else { 5352 f->bge_rsvd = 0; 5353 f->bge_flags = 5354 (csum_flags | txbd_tso_flags) & 0x0fff; 5355 } 5356 } else { 5357 f->bge_rsvd = 0; 5358 f->bge_flags = csum_flags; 5359 } 5360 5361 if (have_vtag) { 5362 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5363 f->bge_vlan_tag = vtag; 5364 } else { 5365 f->bge_vlan_tag = 0; 5366 } 5367 prev_f = f; 5368 cur = frag; 5369 BGE_INC(frag, BGE_TX_RING_CNT); 5370 } 5371 5372 if (i < dmamap->dm_nsegs) { 5373 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5374 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5375 goto fail_unload; 5376 } 5377 5378 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5379 BUS_DMASYNC_PREWRITE); 5380 5381 if (frag == sc->bge_tx_saved_considx) { 5382 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5383 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5384 5385 goto fail_unload; 5386 } 5387 5388 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5389 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5390 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5391 sc->txdma[cur] = dma; 5392 sc->bge_txcnt += dmamap->dm_nsegs; 5393 5394 *txidx = frag; 5395 5396 return 0; 5397 5398 fail_unload: 5399 bus_dmamap_unload(dmatag, dmamap); 5400 ifp->if_flags |= IFF_OACTIVE; 5401 5402 return ENOBUFS; 5403 } 5404 5405 /* 5406 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5407 * to the mbuf data regions directly in the transmit descriptors. 5408 */ 5409 static void 5410 bge_start(struct ifnet *ifp) 5411 { 5412 struct bge_softc * const sc = ifp->if_softc; 5413 struct mbuf *m_head = NULL; 5414 struct mbuf *m; 5415 uint32_t prodidx; 5416 int pkts = 0; 5417 int error; 5418 5419 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5420 return; 5421 5422 prodidx = sc->bge_tx_prodidx; 5423 5424 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5425 IFQ_POLL(&ifp->if_snd, m_head); 5426 if (m_head == NULL) 5427 break; 5428 5429 #if 0 5430 /* 5431 * XXX 5432 * safety overkill. If this is a fragmented packet chain 5433 * with delayed TCP/UDP checksums, then only encapsulate 5434 * it if we have enough descriptors to handle the entire 5435 * chain at once. 5436 * (paranoia -- may not actually be needed) 5437 */ 5438 if (m_head->m_flags & M_FIRSTFRAG && 5439 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5440 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5441 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5442 ifp->if_flags |= IFF_OACTIVE; 5443 break; 5444 } 5445 } 5446 #endif 5447 5448 /* 5449 * Pack the data into the transmit ring. If we 5450 * don't have room, set the OACTIVE flag and wait 5451 * for the NIC to drain the ring. 5452 */ 5453 error = bge_encap(sc, m_head, &prodidx); 5454 if (__predict_false(error)) { 5455 if (ifp->if_flags & IFF_OACTIVE) { 5456 /* just wait for the transmit ring to drain */ 5457 break; 5458 } 5459 IFQ_DEQUEUE(&ifp->if_snd, m); 5460 KASSERT(m == m_head); 5461 m_freem(m_head); 5462 continue; 5463 } 5464 5465 /* now we are committed to transmit the packet */ 5466 IFQ_DEQUEUE(&ifp->if_snd, m); 5467 KASSERT(m == m_head); 5468 pkts++; 5469 5470 /* 5471 * If there's a BPF listener, bounce a copy of this frame 5472 * to him. 5473 */ 5474 bpf_mtap(ifp, m_head, BPF_D_OUT); 5475 } 5476 if (pkts == 0) 5477 return; 5478 5479 /* Transmit */ 5480 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5481 /* 5700 b2 errata */ 5482 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5483 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5484 5485 sc->bge_tx_prodidx = prodidx; 5486 5487 /* 5488 * Set a timeout in case the chip goes out to lunch. 5489 */ 5490 ifp->if_timer = 5; 5491 } 5492 5493 static int 5494 bge_init(struct ifnet *ifp) 5495 { 5496 struct bge_softc * const sc = ifp->if_softc; 5497 const uint16_t *m; 5498 uint32_t mode, reg; 5499 int s, error = 0; 5500 5501 s = splnet(); 5502 5503 KASSERT(ifp == &sc->ethercom.ec_if); 5504 5505 /* Cancel pending I/O and flush buffers. */ 5506 bge_stop(ifp, 0); 5507 5508 bge_stop_fw(sc); 5509 bge_sig_pre_reset(sc, BGE_RESET_START); 5510 bge_reset(sc); 5511 bge_sig_legacy(sc, BGE_RESET_START); 5512 5513 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5514 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5515 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5516 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5517 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5518 5519 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5520 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5521 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5522 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5523 5524 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5525 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5526 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5527 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5528 5529 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5530 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5531 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5532 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5533 } 5534 5535 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5536 pcireg_t aercap; 5537 5538 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5539 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5540 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5541 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5542 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5543 5544 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5545 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5546 | BGE_PCIE_EIDLE_DELAY_13CLK; 5547 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5548 5549 /* Clear correctable error */ 5550 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5551 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5552 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5553 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5554 5555 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5556 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5557 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5558 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5559 } 5560 5561 bge_sig_post_reset(sc, BGE_RESET_START); 5562 5563 bge_chipinit(sc); 5564 5565 /* 5566 * Init the various state machines, ring 5567 * control blocks and firmware. 5568 */ 5569 error = bge_blockinit(sc); 5570 if (error != 0) { 5571 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5572 error); 5573 splx(s); 5574 return error; 5575 } 5576 5577 /* 5718 step 25, 57XX step 54 */ 5578 /* Specify MTU. */ 5579 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5580 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5581 5582 /* 5718 step 23 */ 5583 /* Load our MAC address. */ 5584 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5585 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5586 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5587 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5588 5589 /* Enable or disable promiscuous mode as needed. */ 5590 if (ifp->if_flags & IFF_PROMISC) 5591 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5592 else 5593 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5594 5595 /* Program multicast filter. */ 5596 bge_setmulti(sc); 5597 5598 /* Init RX ring. */ 5599 bge_init_rx_ring_std(sc); 5600 5601 /* 5602 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5603 * memory to insure that the chip has in fact read the first 5604 * entry of the ring. 5605 */ 5606 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5607 uint32_t v, i; 5608 for (i = 0; i < 10; i++) { 5609 DELAY(20); 5610 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5611 if (v == (MCLBYTES - ETHER_ALIGN)) 5612 break; 5613 } 5614 if (i == 10) 5615 aprint_error_dev(sc->bge_dev, 5616 "5705 A0 chip failed to load RX ring\n"); 5617 } 5618 5619 /* Init jumbo RX ring. */ 5620 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5621 bge_init_rx_ring_jumbo(sc); 5622 5623 /* Init our RX return ring index */ 5624 sc->bge_rx_saved_considx = 0; 5625 5626 /* Init TX ring. */ 5627 bge_init_tx_ring(sc); 5628 5629 /* 5718 step 63, 57XX step 94 */ 5630 /* Enable TX MAC state machine lockup fix. */ 5631 mode = CSR_READ_4(sc, BGE_TX_MODE); 5632 if (BGE_IS_5755_PLUS(sc) || 5633 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5634 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5635 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5636 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5637 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5638 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5639 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5640 } 5641 5642 /* Turn on transmitter */ 5643 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5644 /* 5718 step 64 */ 5645 DELAY(100); 5646 5647 /* 5718 step 65, 57XX step 95 */ 5648 /* Turn on receiver */ 5649 mode = CSR_READ_4(sc, BGE_RX_MODE); 5650 if (BGE_IS_5755_PLUS(sc)) 5651 mode |= BGE_RXMODE_IPV6_ENABLE; 5652 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5653 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5654 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5655 /* 5718 step 66 */ 5656 DELAY(10); 5657 5658 /* 5718 step 12, 57XX step 37 */ 5659 /* 5660 * XXX Doucments of 5718 series and 577xx say the recommended value 5661 * is 1, but tg3 set 1 only on 57765 series. 5662 */ 5663 if (BGE_IS_57765_PLUS(sc)) 5664 reg = 1; 5665 else 5666 reg = 2; 5667 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5668 5669 /* Tell firmware we're alive. */ 5670 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5671 5672 /* Enable host interrupts. */ 5673 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5674 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5675 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5676 5677 if ((error = bge_ifmedia_upd(ifp)) != 0) 5678 goto out; 5679 5680 ifp->if_flags |= IFF_RUNNING; 5681 ifp->if_flags &= ~IFF_OACTIVE; 5682 5683 callout_schedule(&sc->bge_timeout, hz); 5684 5685 out: 5686 sc->bge_if_flags = ifp->if_flags; 5687 splx(s); 5688 5689 return error; 5690 } 5691 5692 /* 5693 * Set media options. 5694 */ 5695 static int 5696 bge_ifmedia_upd(struct ifnet *ifp) 5697 { 5698 struct bge_softc * const sc = ifp->if_softc; 5699 struct mii_data * const mii = &sc->bge_mii; 5700 struct ifmedia * const ifm = &sc->bge_ifmedia; 5701 int rc; 5702 5703 /* If this is a 1000baseX NIC, enable the TBI port. */ 5704 if (sc->bge_flags & BGEF_FIBER_TBI) { 5705 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5706 return EINVAL; 5707 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5708 case IFM_AUTO: 5709 /* 5710 * The BCM5704 ASIC appears to have a special 5711 * mechanism for programming the autoneg 5712 * advertisement registers in TBI mode. 5713 */ 5714 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5715 uint32_t sgdig; 5716 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5717 if (sgdig & BGE_SGDIGSTS_DONE) { 5718 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5719 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5720 sgdig |= BGE_SGDIGCFG_AUTO | 5721 BGE_SGDIGCFG_PAUSE_CAP | 5722 BGE_SGDIGCFG_ASYM_PAUSE; 5723 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5724 sgdig | BGE_SGDIGCFG_SEND); 5725 DELAY(5); 5726 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5727 sgdig); 5728 } 5729 } 5730 break; 5731 case IFM_1000_SX: 5732 if ((ifm->ifm_media & IFM_FDX) != 0) { 5733 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5734 BGE_MACMODE_HALF_DUPLEX); 5735 } else { 5736 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5737 BGE_MACMODE_HALF_DUPLEX); 5738 } 5739 DELAY(40); 5740 break; 5741 default: 5742 return EINVAL; 5743 } 5744 /* XXX 802.3x flow control for 1000BASE-SX */ 5745 return 0; 5746 } 5747 5748 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5749 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5750 uint32_t reg; 5751 5752 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5753 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5754 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5755 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5756 } 5757 } 5758 5759 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5760 if ((rc = mii_mediachg(mii)) == ENXIO) 5761 return 0; 5762 5763 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5764 uint32_t reg; 5765 5766 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5767 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5768 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5769 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5770 delay(40); 5771 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5772 } 5773 } 5774 5775 /* 5776 * Force an interrupt so that we will call bge_link_upd 5777 * if needed and clear any pending link state attention. 5778 * Without this we are not getting any further interrupts 5779 * for link state changes and thus will not UP the link and 5780 * not be able to send in bge_start. The only way to get 5781 * things working was to receive a packet and get a RX intr. 5782 */ 5783 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5784 sc->bge_flags & BGEF_IS_5788) 5785 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5786 else 5787 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5788 5789 return rc; 5790 } 5791 5792 /* 5793 * Report current media status. 5794 */ 5795 static void 5796 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5797 { 5798 struct bge_softc * const sc = ifp->if_softc; 5799 struct mii_data * const mii = &sc->bge_mii; 5800 5801 if (sc->bge_flags & BGEF_FIBER_TBI) { 5802 ifmr->ifm_status = IFM_AVALID; 5803 ifmr->ifm_active = IFM_ETHER; 5804 if (CSR_READ_4(sc, BGE_MAC_STS) & 5805 BGE_MACSTAT_TBI_PCS_SYNCHED) 5806 ifmr->ifm_status |= IFM_ACTIVE; 5807 ifmr->ifm_active |= IFM_1000_SX; 5808 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5809 ifmr->ifm_active |= IFM_HDX; 5810 else 5811 ifmr->ifm_active |= IFM_FDX; 5812 return; 5813 } 5814 5815 mii_pollstat(mii); 5816 ifmr->ifm_status = mii->mii_media_status; 5817 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5818 sc->bge_flowflags; 5819 } 5820 5821 static int 5822 bge_ifflags_cb(struct ethercom *ec) 5823 { 5824 struct ifnet * const ifp = &ec->ec_if; 5825 struct bge_softc * const sc = ifp->if_softc; 5826 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5827 5828 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 5829 return ENETRESET; 5830 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5831 return 0; 5832 5833 if ((ifp->if_flags & IFF_PROMISC) == 0) 5834 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5835 else 5836 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5837 5838 bge_setmulti(sc); 5839 5840 sc->bge_if_flags = ifp->if_flags; 5841 return 0; 5842 } 5843 5844 static int 5845 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5846 { 5847 struct bge_softc * const sc = ifp->if_softc; 5848 struct ifreq * const ifr = (struct ifreq *) data; 5849 int s, error = 0; 5850 struct mii_data *mii; 5851 5852 s = splnet(); 5853 5854 switch (command) { 5855 case SIOCSIFMEDIA: 5856 /* XXX Flow control is not supported for 1000BASE-SX */ 5857 if (sc->bge_flags & BGEF_FIBER_TBI) { 5858 ifr->ifr_media &= ~IFM_ETH_FMASK; 5859 sc->bge_flowflags = 0; 5860 } 5861 5862 /* Flow control requires full-duplex mode. */ 5863 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5864 (ifr->ifr_media & IFM_FDX) == 0) { 5865 ifr->ifr_media &= ~IFM_ETH_FMASK; 5866 } 5867 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5868 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5869 /* We can do both TXPAUSE and RXPAUSE. */ 5870 ifr->ifr_media |= 5871 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5872 } 5873 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5874 } 5875 5876 if (sc->bge_flags & BGEF_FIBER_TBI) { 5877 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5878 command); 5879 } else { 5880 mii = &sc->bge_mii; 5881 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5882 command); 5883 } 5884 break; 5885 default: 5886 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5887 break; 5888 5889 error = 0; 5890 5891 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5892 ; 5893 else if (ifp->if_flags & IFF_RUNNING) 5894 bge_setmulti(sc); 5895 break; 5896 } 5897 5898 splx(s); 5899 5900 return error; 5901 } 5902 5903 static void 5904 bge_watchdog(struct ifnet *ifp) 5905 { 5906 struct bge_softc * const sc = ifp->if_softc; 5907 uint32_t status; 5908 5909 /* If pause frames are active then don't reset the hardware. */ 5910 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5911 status = CSR_READ_4(sc, BGE_RX_STS); 5912 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5913 /* 5914 * If link partner has us in XOFF state then wait for 5915 * the condition to clear. 5916 */ 5917 CSR_WRITE_4(sc, BGE_RX_STS, status); 5918 ifp->if_timer = 5; 5919 return; 5920 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5921 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5922 /* 5923 * If link partner has us in XOFF state then wait for 5924 * the condition to clear. 5925 */ 5926 CSR_WRITE_4(sc, BGE_RX_STS, status); 5927 ifp->if_timer = 5; 5928 return; 5929 } 5930 /* 5931 * Any other condition is unexpected and the controller 5932 * should be reset. 5933 */ 5934 } 5935 5936 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5937 5938 ifp->if_flags &= ~IFF_RUNNING; 5939 bge_init(ifp); 5940 5941 if_statinc(ifp, if_oerrors); 5942 } 5943 5944 static void 5945 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5946 { 5947 int i; 5948 5949 BGE_CLRBIT_FLUSH(sc, reg, bit); 5950 5951 for (i = 0; i < 1000; i++) { 5952 delay(100); 5953 if ((CSR_READ_4(sc, reg) & bit) == 0) 5954 return; 5955 } 5956 5957 /* 5958 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5959 * on some environment (and once after boot?) 5960 */ 5961 if (reg != BGE_SRS_MODE) 5962 aprint_error_dev(sc->bge_dev, 5963 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5964 (u_long)reg, bit); 5965 } 5966 5967 /* 5968 * Stop the adapter and free any mbufs allocated to the 5969 * RX and TX lists. 5970 */ 5971 static void 5972 bge_stop(struct ifnet *ifp, int disable) 5973 { 5974 struct bge_softc * const sc = ifp->if_softc; 5975 5976 if (disable) { 5977 sc->bge_detaching = 1; 5978 callout_halt(&sc->bge_timeout, NULL); 5979 } else 5980 callout_stop(&sc->bge_timeout); 5981 5982 /* Disable host interrupts. */ 5983 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5984 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 5985 5986 /* 5987 * Tell firmware we're shutting down. 5988 */ 5989 bge_stop_fw(sc); 5990 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5991 5992 /* 5993 * Disable all of the receiver blocks. 5994 */ 5995 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5996 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5997 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5998 if (BGE_IS_5700_FAMILY(sc)) 5999 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6000 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6001 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6002 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6003 6004 /* 6005 * Disable all of the transmit blocks. 6006 */ 6007 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6008 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6009 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6010 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6011 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6012 if (BGE_IS_5700_FAMILY(sc)) 6013 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6014 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6015 6016 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6017 delay(40); 6018 6019 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6020 6021 /* 6022 * Shut down all of the memory managers and related 6023 * state machines. 6024 */ 6025 /* 5718 step 5a,5b */ 6026 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6027 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6028 if (BGE_IS_5700_FAMILY(sc)) 6029 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6030 6031 /* 5718 step 5c,5d */ 6032 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6033 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6034 6035 if (BGE_IS_5700_FAMILY(sc)) { 6036 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6037 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6038 } 6039 6040 bge_reset(sc); 6041 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6042 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6043 6044 /* 6045 * Keep the ASF firmware running if up. 6046 */ 6047 if (sc->bge_asf_mode & ASF_STACKUP) 6048 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6049 else 6050 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6051 6052 /* Free the RX lists. */ 6053 bge_free_rx_ring_std(sc, disable); 6054 6055 /* Free jumbo RX list. */ 6056 if (BGE_IS_JUMBO_CAPABLE(sc)) 6057 bge_free_rx_ring_jumbo(sc); 6058 6059 /* Free TX buffers. */ 6060 bge_free_tx_ring(sc, disable); 6061 6062 /* 6063 * Isolate/power down the PHY. 6064 */ 6065 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6066 mii_down(&sc->bge_mii); 6067 6068 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6069 6070 /* Clear MAC's link state (PHY may still have link UP). */ 6071 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6072 6073 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6074 } 6075 6076 static void 6077 bge_link_upd(struct bge_softc *sc) 6078 { 6079 struct ifnet * const ifp = &sc->ethercom.ec_if; 6080 struct mii_data * const mii = &sc->bge_mii; 6081 uint32_t status; 6082 uint16_t phyval; 6083 int link; 6084 6085 /* Clear 'pending link event' flag */ 6086 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6087 6088 /* 6089 * Process link state changes. 6090 * Grrr. The link status word in the status block does 6091 * not work correctly on the BCM5700 rev AX and BX chips, 6092 * according to all available information. Hence, we have 6093 * to enable MII interrupts in order to properly obtain 6094 * async link changes. Unfortunately, this also means that 6095 * we have to read the MAC status register to detect link 6096 * changes, thereby adding an additional register access to 6097 * the interrupt handler. 6098 */ 6099 6100 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6101 status = CSR_READ_4(sc, BGE_MAC_STS); 6102 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6103 mii_pollstat(mii); 6104 6105 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6106 mii->mii_media_status & IFM_ACTIVE && 6107 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6108 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6109 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6110 (!(mii->mii_media_status & IFM_ACTIVE) || 6111 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6112 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6113 6114 /* Clear the interrupt */ 6115 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6116 BGE_EVTENB_MI_INTERRUPT); 6117 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6118 BRGPHY_MII_ISR, &phyval); 6119 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6120 BRGPHY_MII_IMR, BRGPHY_INTRS); 6121 } 6122 return; 6123 } 6124 6125 if (sc->bge_flags & BGEF_FIBER_TBI) { 6126 status = CSR_READ_4(sc, BGE_MAC_STS); 6127 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6128 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6129 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6130 if (BGE_ASICREV(sc->bge_chipid) 6131 == BGE_ASICREV_BCM5704) { 6132 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6133 BGE_MACMODE_TBI_SEND_CFGS); 6134 DELAY(40); 6135 } 6136 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6137 if_link_state_change(ifp, LINK_STATE_UP); 6138 } 6139 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6140 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6141 if_link_state_change(ifp, LINK_STATE_DOWN); 6142 } 6143 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6144 /* 6145 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6146 * bit in status word always set. Workaround this bug by 6147 * reading PHY link status directly. 6148 */ 6149 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6150 BGE_STS_LINK : 0; 6151 6152 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6153 mii_pollstat(mii); 6154 6155 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6156 mii->mii_media_status & IFM_ACTIVE && 6157 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6158 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6159 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6160 (!(mii->mii_media_status & IFM_ACTIVE) || 6161 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6162 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6163 } 6164 } else { 6165 /* 6166 * For controllers that call mii_tick, we have to poll 6167 * link status. 6168 */ 6169 mii_pollstat(mii); 6170 } 6171 6172 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6173 uint32_t reg, scale; 6174 6175 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6176 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6177 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6178 scale = 65; 6179 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6180 scale = 6; 6181 else 6182 scale = 12; 6183 6184 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6185 ~BGE_MISCCFG_TIMER_PRESCALER; 6186 reg |= scale << 1; 6187 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6188 } 6189 /* Clear the attention */ 6190 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6191 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6192 BGE_MACSTAT_LINK_CHANGED); 6193 } 6194 6195 static int 6196 bge_sysctl_verify(SYSCTLFN_ARGS) 6197 { 6198 int error, t; 6199 struct sysctlnode node; 6200 6201 node = *rnode; 6202 t = *(int*)rnode->sysctl_data; 6203 node.sysctl_data = &t; 6204 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6205 if (error || newp == NULL) 6206 return error; 6207 6208 #if 0 6209 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6210 node.sysctl_num, rnode->sysctl_num)); 6211 #endif 6212 6213 if (node.sysctl_num == bge_rxthresh_nodenum) { 6214 if (t < 0 || t >= NBGE_RX_THRESH) 6215 return EINVAL; 6216 bge_update_all_threshes(t); 6217 } else 6218 return EINVAL; 6219 6220 *(int*)rnode->sysctl_data = t; 6221 6222 return 0; 6223 } 6224 6225 /* 6226 * Set up sysctl(3) MIB, hw.bge.*. 6227 */ 6228 static void 6229 bge_sysctl_init(struct bge_softc *sc) 6230 { 6231 int rc, bge_root_num; 6232 const struct sysctlnode *node; 6233 6234 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6235 0, CTLTYPE_NODE, "bge", 6236 SYSCTL_DESCR("BGE interface controls"), 6237 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6238 goto out; 6239 } 6240 6241 bge_root_num = node->sysctl_num; 6242 6243 /* BGE Rx interrupt mitigation level */ 6244 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6245 CTLFLAG_READWRITE, 6246 CTLTYPE_INT, "rx_lvl", 6247 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6248 bge_sysctl_verify, 0, 6249 &bge_rx_thresh_lvl, 6250 0, CTL_HW, bge_root_num, CTL_CREATE, 6251 CTL_EOL)) != 0) { 6252 goto out; 6253 } 6254 6255 bge_rxthresh_nodenum = node->sysctl_num; 6256 6257 return; 6258 6259 out: 6260 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6261 } 6262 6263 #ifdef BGE_DEBUG 6264 void 6265 bge_debug_info(struct bge_softc *sc) 6266 { 6267 6268 printf("Hardware Flags:\n"); 6269 if (BGE_IS_57765_PLUS(sc)) 6270 printf(" - 57765 Plus\n"); 6271 if (BGE_IS_5717_PLUS(sc)) 6272 printf(" - 5717 Plus\n"); 6273 if (BGE_IS_5755_PLUS(sc)) 6274 printf(" - 5755 Plus\n"); 6275 if (BGE_IS_575X_PLUS(sc)) 6276 printf(" - 575X Plus\n"); 6277 if (BGE_IS_5705_PLUS(sc)) 6278 printf(" - 5705 Plus\n"); 6279 if (BGE_IS_5714_FAMILY(sc)) 6280 printf(" - 5714 Family\n"); 6281 if (BGE_IS_5700_FAMILY(sc)) 6282 printf(" - 5700 Family\n"); 6283 if (sc->bge_flags & BGEF_IS_5788) 6284 printf(" - 5788\n"); 6285 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6286 printf(" - Supports Jumbo Frames\n"); 6287 if (sc->bge_flags & BGEF_NO_EEPROM) 6288 printf(" - No EEPROM\n"); 6289 if (sc->bge_flags & BGEF_PCIX) 6290 printf(" - PCI-X Bus\n"); 6291 if (sc->bge_flags & BGEF_PCIE) 6292 printf(" - PCI Express Bus\n"); 6293 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6294 printf(" - RX Alignment Bug\n"); 6295 if (sc->bge_flags & BGEF_APE) 6296 printf(" - APE\n"); 6297 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6298 printf(" - CPMU\n"); 6299 if (sc->bge_flags & BGEF_TSO) 6300 printf(" - TSO\n"); 6301 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6302 printf(" - TAGGED_STATUS\n"); 6303 6304 /* PHY related */ 6305 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6306 printf(" - No 3 LEDs\n"); 6307 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6308 printf(" - CRC bug\n"); 6309 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6310 printf(" - ADC bug\n"); 6311 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6312 printf(" - 5704 A0 bug\n"); 6313 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6314 printf(" - jitter bug\n"); 6315 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6316 printf(" - BER bug\n"); 6317 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6318 printf(" - adjust trim\n"); 6319 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6320 printf(" - no wirespeed\n"); 6321 6322 /* ASF related */ 6323 if (sc->bge_asf_mode & ASF_ENABLE) 6324 printf(" - ASF enable\n"); 6325 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6326 printf(" - ASF new handshake\n"); 6327 if (sc->bge_asf_mode & ASF_STACKUP) 6328 printf(" - ASF stackup\n"); 6329 } 6330 #endif /* BGE_DEBUG */ 6331 6332 static int 6333 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6334 { 6335 prop_dictionary_t dict; 6336 prop_data_t ea; 6337 6338 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6339 return 1; 6340 6341 dict = device_properties(sc->bge_dev); 6342 ea = prop_dictionary_get(dict, "mac-address"); 6343 if (ea != NULL) { 6344 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6345 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6346 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6347 return 0; 6348 } 6349 6350 return 1; 6351 } 6352 6353 static int 6354 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6355 { 6356 uint32_t mac_addr; 6357 6358 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6359 if ((mac_addr >> 16) == 0x484b) { 6360 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6361 ether_addr[1] = (uint8_t)mac_addr; 6362 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6363 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6364 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6365 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6366 ether_addr[5] = (uint8_t)mac_addr; 6367 return 0; 6368 } 6369 return 1; 6370 } 6371 6372 static int 6373 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6374 { 6375 int mac_offset = BGE_EE_MAC_OFFSET; 6376 6377 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6378 mac_offset = BGE_EE_MAC_OFFSET_5906; 6379 6380 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6381 ETHER_ADDR_LEN)); 6382 } 6383 6384 static int 6385 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6386 { 6387 6388 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6389 return 1; 6390 6391 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6392 ETHER_ADDR_LEN)); 6393 } 6394 6395 static int 6396 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6397 { 6398 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6399 /* NOTE: Order is critical */ 6400 bge_get_eaddr_fw, 6401 bge_get_eaddr_mem, 6402 bge_get_eaddr_nvram, 6403 bge_get_eaddr_eeprom, 6404 NULL 6405 }; 6406 const bge_eaddr_fcn_t *func; 6407 6408 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6409 if ((*func)(sc, eaddr) == 0) 6410 break; 6411 } 6412 return *func == NULL ? ENXIO : 0; 6413 } 6414
Indexes created Mon Sep 22 10:09:38 GMT 2025