if_bge.c revision 1.373
1 /* $NetBSD: if_bge.c,v 1.373 2022/08/07 08:37:48 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.373 2022/08/07 08:37:48 skrll Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/callout.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> 90 #include <sys/kmem.h> 91 #include <sys/mbuf.h> 92 #include <sys/rndsource.h> 93 #include <sys/socket.h> 94 #include <sys/sockio.h> 95 #include <sys/sysctl.h> 96 #include <sys/systm.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 #include <net/bpf.h> 103 104 #ifdef INET 105 #include <netinet/in.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 /* Headers for TCP Segmentation Offload (TSO) */ 112 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 113 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 114 #include <netinet/ip.h> /* for struct ip */ 115 #include <netinet/tcp.h> /* for struct tcphdr */ 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 #include <dev/pci/pcidevs.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 #include <dev/mii/miidevs.h> 124 #include <dev/mii/brgphyreg.h> 125 126 #include <dev/pci/if_bgereg.h> 127 #include <dev/pci/if_bgevar.h> 128 129 #include <prop/proplib.h> 130 131 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 132 133 134 /* 135 * Tunable thresholds for rx-side bge interrupt mitigation. 136 */ 137 138 /* 139 * The pairs of values below were obtained from empirical measurement 140 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 141 * interrupt for every N packets received, where N is, approximately, 142 * the second value (rx_max_bds) in each pair. The values are chosen 143 * such that moving from one pair to the succeeding pair was observed 144 * to roughly halve interrupt rate under sustained input packet load. 145 * The values were empirically chosen to avoid overflowing internal 146 * limits on the bcm5700: increasing rx_ticks much beyond 600 147 * results in internal wrapping and higher interrupt rates. 148 * The limit of 46 frames was chosen to match NFS workloads. 149 * 150 * These values also work well on bcm5701, bcm5704C, and (less 151 * tested) bcm5703. On other chipsets, (including the Altima chip 152 * family), the larger values may overflow internal chip limits, 153 * leading to increasing interrupt rates rather than lower interrupt 154 * rates. 155 * 156 * Applications using heavy interrupt mitigation (interrupting every 157 * 32 or 46 frames) in both directions may need to increase the TCP 158 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 159 * full link bandwidth, due to ACKs and window updates lingering 160 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 161 */ 162 static const struct bge_load_rx_thresh { 163 int rx_ticks; 164 int rx_max_bds; } 165 bge_rx_threshes[] = { 166 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 167 { 32, 2 }, 168 { 50, 4 }, 169 { 100, 8 }, 170 { 192, 16 }, 171 { 416, 32 }, 172 { 598, 46 } 173 }; 174 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 175 176 /* XXX patchable; should be sysctl'able */ 177 static int bge_auto_thresh = 1; 178 static int bge_rx_thresh_lvl; 179 180 static int bge_rxthresh_nodenum; 181 182 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 183 184 static uint32_t bge_chipid(const struct pci_attach_args *); 185 static int bge_can_use_msi(struct bge_softc *); 186 static int bge_probe(device_t, cfdata_t, void *); 187 static void bge_attach(device_t, device_t, void *); 188 static int bge_detach(device_t, int); 189 static void bge_release_resources(struct bge_softc *); 190 191 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 192 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 193 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 196 197 static void bge_txeof(struct bge_softc *); 198 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 199 static void bge_rxeof(struct bge_softc *); 200 201 static void bge_asf_driver_up (struct bge_softc *); 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static void bge_stats_update_regs(struct bge_softc *); 205 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 206 207 static int bge_intr(void *); 208 static void bge_start(struct ifnet *); 209 static int bge_ifflags_cb(struct ethercom *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 219 220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 221 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 222 static void bge_setmulti(struct bge_softc *); 223 224 static void bge_handle_events(struct bge_softc *); 225 static int bge_alloc_jumbo_mem(struct bge_softc *); 226 static void bge_free_jumbo_mem(struct bge_softc *); 227 static void *bge_jalloc(struct bge_softc *); 228 static void bge_jfree(struct mbuf *, void *, size_t, void *); 229 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 230 bus_dmamap_t); 231 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 232 static int bge_init_rx_ring_std(struct bge_softc *); 233 static void bge_free_rx_ring_std(struct bge_softc *m, bool); 234 static int bge_init_rx_ring_jumbo(struct bge_softc *); 235 static void bge_free_rx_ring_jumbo(struct bge_softc *); 236 static void bge_free_tx_ring(struct bge_softc *m, bool); 237 static int bge_init_tx_ring(struct bge_softc *); 238 239 static int bge_chipinit(struct bge_softc *); 240 static int bge_blockinit(struct bge_softc *); 241 static int bge_phy_addr(struct bge_softc *); 242 static uint32_t bge_readmem_ind(struct bge_softc *, int); 243 static void bge_writemem_ind(struct bge_softc *, int, int); 244 static void bge_writembx(struct bge_softc *, int, int); 245 static void bge_writembx_flush(struct bge_softc *, int, int); 246 static void bge_writemem_direct(struct bge_softc *, int, int); 247 static void bge_writereg_ind(struct bge_softc *, int, int); 248 static void bge_set_max_readrq(struct bge_softc *); 249 250 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 251 static int bge_miibus_writereg(device_t, int, int, uint16_t); 252 static void bge_miibus_statchg(struct ifnet *); 253 254 #define BGE_RESET_SHUTDOWN 0 255 #define BGE_RESET_START 1 256 #define BGE_RESET_SUSPEND 2 257 static void bge_sig_post_reset(struct bge_softc *, int); 258 static void bge_sig_legacy(struct bge_softc *, int); 259 static void bge_sig_pre_reset(struct bge_softc *, int); 260 static void bge_wait_for_event_ack(struct bge_softc *); 261 static void bge_stop_fw(struct bge_softc *); 262 static int bge_reset(struct bge_softc *); 263 static void bge_link_upd(struct bge_softc *); 264 static void bge_sysctl_init(struct bge_softc *); 265 static int bge_sysctl_verify(SYSCTLFN_PROTO); 266 267 static void bge_ape_lock_init(struct bge_softc *); 268 static void bge_ape_read_fw_ver(struct bge_softc *); 269 static int bge_ape_lock(struct bge_softc *, int); 270 static void bge_ape_unlock(struct bge_softc *, int); 271 static void bge_ape_send_event(struct bge_softc *, uint32_t); 272 static void bge_ape_driver_state_change(struct bge_softc *, int); 273 274 #ifdef BGE_DEBUG 275 #define DPRINTF(x) if (bgedebug) printf x 276 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 277 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 278 int bgedebug = 0; 279 int bge_tso_debug = 0; 280 void bge_debug_info(struct bge_softc *); 281 #else 282 #define DPRINTF(x) 283 #define DPRINTFN(n, x) 284 #define BGE_TSO_PRINTF(x) 285 #endif 286 287 #ifdef BGE_EVENT_COUNTERS 288 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 289 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 290 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 291 #else 292 #define BGE_EVCNT_INCR(ev) /* nothing */ 293 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 294 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 295 #endif 296 297 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 298 /* 299 * The BCM5700 documentation seems to indicate that the hardware still has the 300 * Alteon vendor ID burned into it, though it should always be overridden by 301 * the value in the EEPROM. We'll check for it anyway. 302 */ 303 static const struct bge_product { 304 pci_vendor_id_t bp_vendor; 305 pci_product_id_t bp_product; 306 const char *bp_name; 307 } bge_products[] = { 308 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 309 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 310 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 311 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 312 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 313 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 314 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 315 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 319 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 320 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 322 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 323 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 326 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 330 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 331 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 332 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 333 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 334 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 335 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 336 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 348 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 349 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 350 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 351 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 353 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 354 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 355 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 356 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 357 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 358 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 362 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 363 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 364 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 367 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 368 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 369 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 370 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 371 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 372 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 373 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 375 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 376 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 377 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 378 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 379 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 380 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 381 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 382 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 383 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 399 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 400 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 401 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 402 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 403 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 404 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 405 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 406 { 0, 0, NULL }, 407 }; 408 409 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 410 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 411 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 412 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 413 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 414 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 415 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 416 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 417 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 418 419 static const struct bge_revision { 420 uint32_t br_chipid; 421 const char *br_name; 422 } bge_revisions[] = { 423 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 424 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 425 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 426 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 427 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 428 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 429 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 430 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 431 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 432 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 433 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 434 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 435 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 436 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 437 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 438 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 439 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 440 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 441 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 442 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 443 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 444 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 445 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 446 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 447 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 448 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 449 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 450 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 451 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 452 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 453 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 454 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 455 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 456 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 457 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 458 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 459 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 460 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 461 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 462 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 463 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 464 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 465 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 466 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 467 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 468 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 469 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 470 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 471 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 472 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 473 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 474 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 475 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 476 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 477 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 478 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 479 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 480 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 481 /* 5754 and 5787 share the same ASIC ID */ 482 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 483 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 484 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 485 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 486 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 487 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 488 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 489 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 490 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 491 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 492 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 493 494 { 0, NULL } 495 }; 496 497 /* 498 * Some defaults for major revisions, so that newer steppings 499 * that we don't know about have a shot at working. 500 */ 501 static const struct bge_revision bge_majorrevs[] = { 502 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 503 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 504 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 505 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 506 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 507 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 508 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 509 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 510 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 511 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 512 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 513 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 514 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 515 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 516 /* 5754 and 5787 share the same ASIC ID */ 517 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 518 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 519 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 520 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 521 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 522 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 523 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 524 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 525 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 526 527 { 0, NULL } 528 }; 529 530 static int bge_allow_asf = 1; 531 532 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 533 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 534 535 static uint32_t 536 bge_readmem_ind(struct bge_softc *sc, int off) 537 { 538 pcireg_t val; 539 540 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 541 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 542 return 0; 543 544 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 545 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 546 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 547 return val; 548 } 549 550 static void 551 bge_writemem_ind(struct bge_softc *sc, int off, int val) 552 { 553 554 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 556 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 557 } 558 559 /* 560 * PCI Express only 561 */ 562 static void 563 bge_set_max_readrq(struct bge_softc *sc) 564 { 565 pcireg_t val; 566 567 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 568 + PCIE_DCSR); 569 val &= ~PCIE_DCSR_MAX_READ_REQ; 570 switch (sc->bge_expmrq) { 571 case 2048: 572 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 573 break; 574 case 4096: 575 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 576 break; 577 default: 578 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 579 break; 580 } 581 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 582 + PCIE_DCSR, val); 583 } 584 585 #ifdef notdef 586 static uint32_t 587 bge_readreg_ind(struct bge_softc *sc, int off) 588 { 589 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 590 return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA); 591 } 592 #endif 593 594 static void 595 bge_writereg_ind(struct bge_softc *sc, int off, int val) 596 { 597 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 599 } 600 601 static void 602 bge_writemem_direct(struct bge_softc *sc, int off, int val) 603 { 604 CSR_WRITE_4(sc, off, val); 605 } 606 607 static void 608 bge_writembx(struct bge_softc *sc, int off, int val) 609 { 610 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 611 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 612 613 CSR_WRITE_4(sc, off, val); 614 } 615 616 static void 617 bge_writembx_flush(struct bge_softc *sc, int off, int val) 618 { 619 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 620 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 621 622 CSR_WRITE_4_FLUSH(sc, off, val); 623 } 624 625 /* 626 * Clear all stale locks and select the lock for this driver instance. 627 */ 628 void 629 bge_ape_lock_init(struct bge_softc *sc) 630 { 631 struct pci_attach_args *pa = &(sc->bge_pa); 632 uint32_t bit, regbase; 633 int i; 634 635 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 636 regbase = BGE_APE_LOCK_GRANT; 637 else 638 regbase = BGE_APE_PER_LOCK_GRANT; 639 640 /* Clear any stale locks. */ 641 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 642 switch (i) { 643 case BGE_APE_LOCK_PHY0: 644 case BGE_APE_LOCK_PHY1: 645 case BGE_APE_LOCK_PHY2: 646 case BGE_APE_LOCK_PHY3: 647 bit = BGE_APE_LOCK_GRANT_DRIVER0; 648 break; 649 default: 650 if (pa->pa_function == 0) 651 bit = BGE_APE_LOCK_GRANT_DRIVER0; 652 else 653 bit = (1 << pa->pa_function); 654 } 655 APE_WRITE_4(sc, regbase + 4 * i, bit); 656 } 657 658 /* Select the PHY lock based on the device's function number. */ 659 switch (pa->pa_function) { 660 case 0: 661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 662 break; 663 case 1: 664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 665 break; 666 case 2: 667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 668 break; 669 case 3: 670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 671 break; 672 default: 673 printf("%s: PHY lock not supported on function\n", 674 device_xname(sc->bge_dev)); 675 break; 676 } 677 } 678 679 /* 680 * Check for APE firmware, set flags, and print version info. 681 */ 682 void 683 bge_ape_read_fw_ver(struct bge_softc *sc) 684 { 685 const char *fwtype; 686 uint32_t apedata, features; 687 688 /* Check for a valid APE signature in shared memory. */ 689 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 690 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 691 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 692 return; 693 } 694 695 /* Check if APE firmware is running. */ 696 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 697 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 698 printf("%s: APE signature found but FW status not ready! " 699 "0x%08x\n", device_xname(sc->bge_dev), apedata); 700 return; 701 } 702 703 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 704 705 /* Fetch the APE firwmare type and version. */ 706 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 707 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 708 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 709 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 710 fwtype = "NCSI"; 711 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 712 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 713 fwtype = "DASH"; 714 } else 715 fwtype = "UNKN"; 716 717 /* Print the APE firmware version. */ 718 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 719 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 720 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 721 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 722 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 723 } 724 725 int 726 bge_ape_lock(struct bge_softc *sc, int locknum) 727 { 728 struct pci_attach_args *pa = &(sc->bge_pa); 729 uint32_t bit, gnt, req, status; 730 int i, off; 731 732 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 733 return 0; 734 735 /* Lock request/grant registers have different bases. */ 736 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 737 req = BGE_APE_LOCK_REQ; 738 gnt = BGE_APE_LOCK_GRANT; 739 } else { 740 req = BGE_APE_PER_LOCK_REQ; 741 gnt = BGE_APE_PER_LOCK_GRANT; 742 } 743 744 off = 4 * locknum; 745 746 switch (locknum) { 747 case BGE_APE_LOCK_GPIO: 748 /* Lock required when using GPIO. */ 749 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 750 return 0; 751 if (pa->pa_function == 0) 752 bit = BGE_APE_LOCK_REQ_DRIVER0; 753 else 754 bit = (1 << pa->pa_function); 755 break; 756 case BGE_APE_LOCK_GRC: 757 /* Lock required to reset the device. */ 758 if (pa->pa_function == 0) 759 bit = BGE_APE_LOCK_REQ_DRIVER0; 760 else 761 bit = (1 << pa->pa_function); 762 break; 763 case BGE_APE_LOCK_MEM: 764 /* Lock required when accessing certain APE memory. */ 765 if (pa->pa_function == 0) 766 bit = BGE_APE_LOCK_REQ_DRIVER0; 767 else 768 bit = (1 << pa->pa_function); 769 break; 770 case BGE_APE_LOCK_PHY0: 771 case BGE_APE_LOCK_PHY1: 772 case BGE_APE_LOCK_PHY2: 773 case BGE_APE_LOCK_PHY3: 774 /* Lock required when accessing PHYs. */ 775 bit = BGE_APE_LOCK_REQ_DRIVER0; 776 break; 777 default: 778 return EINVAL; 779 } 780 781 /* Request a lock. */ 782 APE_WRITE_4_FLUSH(sc, req + off, bit); 783 784 /* Wait up to 1 second to acquire lock. */ 785 for (i = 0; i < 20000; i++) { 786 status = APE_READ_4(sc, gnt + off); 787 if (status == bit) 788 break; 789 DELAY(50); 790 } 791 792 /* Handle any errors. */ 793 if (status != bit) { 794 printf("%s: APE lock %d request failed! " 795 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 796 device_xname(sc->bge_dev), 797 locknum, req + off, bit & 0xFFFF, gnt + off, 798 status & 0xFFFF); 799 /* Revoke the lock request. */ 800 APE_WRITE_4(sc, gnt + off, bit); 801 return EBUSY; 802 } 803 804 return 0; 805 } 806 807 void 808 bge_ape_unlock(struct bge_softc *sc, int locknum) 809 { 810 struct pci_attach_args *pa = &(sc->bge_pa); 811 uint32_t bit, gnt; 812 int off; 813 814 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 815 return; 816 817 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 818 gnt = BGE_APE_LOCK_GRANT; 819 else 820 gnt = BGE_APE_PER_LOCK_GRANT; 821 822 off = 4 * locknum; 823 824 switch (locknum) { 825 case BGE_APE_LOCK_GPIO: 826 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 827 return; 828 if (pa->pa_function == 0) 829 bit = BGE_APE_LOCK_GRANT_DRIVER0; 830 else 831 bit = (1 << pa->pa_function); 832 break; 833 case BGE_APE_LOCK_GRC: 834 if (pa->pa_function == 0) 835 bit = BGE_APE_LOCK_GRANT_DRIVER0; 836 else 837 bit = (1 << pa->pa_function); 838 break; 839 case BGE_APE_LOCK_MEM: 840 if (pa->pa_function == 0) 841 bit = BGE_APE_LOCK_GRANT_DRIVER0; 842 else 843 bit = (1 << pa->pa_function); 844 break; 845 case BGE_APE_LOCK_PHY0: 846 case BGE_APE_LOCK_PHY1: 847 case BGE_APE_LOCK_PHY2: 848 case BGE_APE_LOCK_PHY3: 849 bit = BGE_APE_LOCK_GRANT_DRIVER0; 850 break; 851 default: 852 return; 853 } 854 855 /* Write and flush for consecutive bge_ape_lock() */ 856 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 857 } 858 859 /* 860 * Send an event to the APE firmware. 861 */ 862 void 863 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 864 { 865 uint32_t apedata; 866 int i; 867 868 /* NCSI does not support APE events. */ 869 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 870 return; 871 872 /* Wait up to 1ms for APE to service previous event. */ 873 for (i = 10; i > 0; i--) { 874 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 875 break; 876 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 877 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 878 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 879 BGE_APE_EVENT_STATUS_EVENT_PENDING); 880 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 881 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 882 break; 883 } 884 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 885 DELAY(100); 886 } 887 if (i == 0) { 888 printf("%s: APE event 0x%08x send timed out\n", 889 device_xname(sc->bge_dev), event); 890 } 891 } 892 893 void 894 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 895 { 896 uint32_t apedata, event; 897 898 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 899 return; 900 901 switch (kind) { 902 case BGE_RESET_START: 903 /* If this is the first load, clear the load counter. */ 904 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 905 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 906 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 907 else { 908 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 909 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 910 } 911 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 912 BGE_APE_HOST_SEG_SIG_MAGIC); 913 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 914 BGE_APE_HOST_SEG_LEN_MAGIC); 915 916 /* Add some version info if bge(4) supports it. */ 917 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 918 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 919 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 920 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 921 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 922 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 923 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 924 BGE_APE_HOST_DRVR_STATE_START); 925 event = BGE_APE_EVENT_STATUS_STATE_START; 926 break; 927 case BGE_RESET_SHUTDOWN: 928 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 929 BGE_APE_HOST_DRVR_STATE_UNLOAD); 930 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 931 break; 932 case BGE_RESET_SUSPEND: 933 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 934 break; 935 default: 936 return; 937 } 938 939 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 940 BGE_APE_EVENT_STATUS_STATE_CHNGE); 941 } 942 943 static uint8_t 944 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 945 { 946 uint32_t access, byte = 0; 947 int i; 948 949 /* Lock. */ 950 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 951 for (i = 0; i < 8000; i++) { 952 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 953 break; 954 DELAY(20); 955 } 956 if (i == 8000) 957 return 1; 958 959 /* Enable access. */ 960 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 961 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 962 963 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 964 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 965 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 966 DELAY(10); 967 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 968 DELAY(10); 969 break; 970 } 971 } 972 973 if (i == BGE_TIMEOUT * 10) { 974 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 975 return 1; 976 } 977 978 /* Get result. */ 979 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 980 981 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 982 983 /* Disable access. */ 984 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 985 986 /* Unlock. */ 987 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 988 989 return 0; 990 } 991 992 /* 993 * Read a sequence of bytes from NVRAM. 994 */ 995 static int 996 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 997 { 998 int error = 0, i; 999 uint8_t byte = 0; 1000 1001 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1002 return 1; 1003 1004 for (i = 0; i < cnt; i++) { 1005 error = bge_nvram_getbyte(sc, off + i, &byte); 1006 if (error) 1007 break; 1008 *(dest + i) = byte; 1009 } 1010 1011 return error ? 1 : 0; 1012 } 1013 1014 /* 1015 * Read a byte of data stored in the EEPROM at address 'addr.' The 1016 * BCM570x supports both the traditional bitbang interface and an 1017 * auto access interface for reading the EEPROM. We use the auto 1018 * access method. 1019 */ 1020 static uint8_t 1021 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1022 { 1023 int i; 1024 uint32_t byte = 0; 1025 1026 /* 1027 * Enable use of auto EEPROM access so we can avoid 1028 * having to use the bitbang method. 1029 */ 1030 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1031 1032 /* Reset the EEPROM, load the clock period. */ 1033 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1034 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1035 DELAY(20); 1036 1037 /* Issue the read EEPROM command. */ 1038 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1039 1040 /* Wait for completion */ 1041 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1042 DELAY(10); 1043 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1044 break; 1045 } 1046 1047 if (i == BGE_TIMEOUT * 10) { 1048 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1049 return 1; 1050 } 1051 1052 /* Get result. */ 1053 byte = CSR_READ_4(sc, BGE_EE_DATA); 1054 1055 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1056 1057 return 0; 1058 } 1059 1060 /* 1061 * Read a sequence of bytes from the EEPROM. 1062 */ 1063 static int 1064 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1065 { 1066 int error = 0, i; 1067 uint8_t byte = 0; 1068 char *dest = destv; 1069 1070 for (i = 0; i < cnt; i++) { 1071 error = bge_eeprom_getbyte(sc, off + i, &byte); 1072 if (error) 1073 break; 1074 *(dest + i) = byte; 1075 } 1076 1077 return error ? 1 : 0; 1078 } 1079 1080 static int 1081 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1082 { 1083 struct bge_softc * const sc = device_private(dev); 1084 uint32_t data; 1085 uint32_t autopoll; 1086 int rv = 0; 1087 int i; 1088 1089 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1090 return -1; 1091 1092 /* Reading with autopolling on may trigger PCI errors */ 1093 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1094 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1095 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1096 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1097 DELAY(80); 1098 } 1099 1100 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1101 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1102 1103 for (i = 0; i < BGE_TIMEOUT; i++) { 1104 delay(10); 1105 data = CSR_READ_4(sc, BGE_MI_COMM); 1106 if (!(data & BGE_MICOMM_BUSY)) { 1107 DELAY(5); 1108 data = CSR_READ_4(sc, BGE_MI_COMM); 1109 break; 1110 } 1111 } 1112 1113 if (i == BGE_TIMEOUT) { 1114 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1115 rv = ETIMEDOUT; 1116 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1117 /* XXX This error occurs on some devices while attaching. */ 1118 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1119 rv = EIO; 1120 } else 1121 *val = data & BGE_MICOMM_DATA; 1122 1123 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1124 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1125 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1126 DELAY(80); 1127 } 1128 1129 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1130 1131 return rv; 1132 } 1133 1134 static int 1135 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1136 { 1137 struct bge_softc * const sc = device_private(dev); 1138 uint32_t data, autopoll; 1139 int rv = 0; 1140 int i; 1141 1142 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1143 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1144 return 0; 1145 1146 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1147 return -1; 1148 1149 /* Reading with autopolling on may trigger PCI errors */ 1150 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1151 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1152 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1153 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1154 DELAY(80); 1155 } 1156 1157 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1158 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1159 1160 for (i = 0; i < BGE_TIMEOUT; i++) { 1161 delay(10); 1162 data = CSR_READ_4(sc, BGE_MI_COMM); 1163 if (!(data & BGE_MICOMM_BUSY)) { 1164 delay(5); 1165 data = CSR_READ_4(sc, BGE_MI_COMM); 1166 break; 1167 } 1168 } 1169 1170 if (i == BGE_TIMEOUT) { 1171 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1172 rv = ETIMEDOUT; 1173 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1174 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1175 rv = EIO; 1176 } 1177 1178 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1179 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1180 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1181 delay(80); 1182 } 1183 1184 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1185 1186 return rv; 1187 } 1188 1189 static void 1190 bge_miibus_statchg(struct ifnet *ifp) 1191 { 1192 struct bge_softc * const sc = ifp->if_softc; 1193 struct mii_data *mii = &sc->bge_mii; 1194 uint32_t mac_mode, rx_mode, tx_mode; 1195 1196 /* 1197 * Get flow control negotiation result. 1198 */ 1199 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1200 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1201 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1202 1203 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1204 mii->mii_media_status & IFM_ACTIVE && 1205 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1206 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1207 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1208 (!(mii->mii_media_status & IFM_ACTIVE) || 1209 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1210 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1211 1212 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1213 return; 1214 1215 /* Set the port mode (MII/GMII) to match the link speed. */ 1216 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1217 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1218 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1219 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1220 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1221 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1222 mac_mode |= BGE_PORTMODE_GMII; 1223 else 1224 mac_mode |= BGE_PORTMODE_MII; 1225 1226 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1227 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1228 if ((mii->mii_media_active & IFM_FDX) != 0) { 1229 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1230 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1231 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1232 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1233 } else 1234 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1235 1236 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1237 DELAY(40); 1238 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1239 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1240 } 1241 1242 /* 1243 * Update rx threshold levels to values in a particular slot 1244 * of the interrupt-mitigation table bge_rx_threshes. 1245 */ 1246 static void 1247 bge_set_thresh(struct ifnet *ifp, int lvl) 1248 { 1249 struct bge_softc * const sc = ifp->if_softc; 1250 int s; 1251 1252 /* 1253 * For now, just save the new Rx-intr thresholds and record 1254 * that a threshold update is pending. Updating the hardware 1255 * registers here (even at splhigh()) is observed to 1256 * occasionally cause glitches where Rx-interrupts are not 1257 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1258 */ 1259 s = splnet(); 1260 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1261 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1262 sc->bge_pending_rxintr_change = 1; 1263 splx(s); 1264 } 1265 1266 1267 /* 1268 * Update Rx thresholds of all bge devices 1269 */ 1270 static void 1271 bge_update_all_threshes(int lvl) 1272 { 1273 const char * const namebuf = "bge"; 1274 const size_t namelen = strlen(namebuf); 1275 struct ifnet *ifp; 1276 1277 if (lvl < 0) 1278 lvl = 0; 1279 else if (lvl >= NBGE_RX_THRESH) 1280 lvl = NBGE_RX_THRESH - 1; 1281 1282 /* 1283 * Now search all the interfaces for this name/number 1284 */ 1285 int s = pserialize_read_enter(); 1286 IFNET_READER_FOREACH(ifp) { 1287 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1288 continue; 1289 /* We got a match: update if doing auto-threshold-tuning */ 1290 if (bge_auto_thresh) 1291 bge_set_thresh(ifp, lvl); 1292 } 1293 pserialize_read_exit(s); 1294 } 1295 1296 /* 1297 * Handle events that have triggered interrupts. 1298 */ 1299 static void 1300 bge_handle_events(struct bge_softc *sc) 1301 { 1302 1303 return; 1304 } 1305 1306 /* 1307 * Memory management for jumbo frames. 1308 */ 1309 1310 static int 1311 bge_alloc_jumbo_mem(struct bge_softc *sc) 1312 { 1313 char *ptr, *kva; 1314 int i, rseg, state, error; 1315 struct bge_jpool_entry *entry; 1316 1317 state = error = 0; 1318 1319 /* Grab a big chunk o' storage. */ 1320 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1321 &sc->bge_cdata.bge_rx_jumbo_seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1322 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1323 return ENOBUFS; 1324 } 1325 1326 state = 1; 1327 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1328 rseg, BGE_JMEM, (void **)&kva, 1329 BUS_DMA_NOWAIT)) { 1330 aprint_error_dev(sc->bge_dev, 1331 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1332 error = ENOBUFS; 1333 goto out; 1334 } 1335 1336 state = 2; 1337 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1338 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1339 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1340 error = ENOBUFS; 1341 goto out; 1342 } 1343 1344 state = 3; 1345 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1346 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1347 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1348 error = ENOBUFS; 1349 goto out; 1350 } 1351 1352 state = 4; 1353 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1354 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1355 1356 SLIST_INIT(&sc->bge_jfree_listhead); 1357 SLIST_INIT(&sc->bge_jinuse_listhead); 1358 1359 /* 1360 * Now divide it up into 9K pieces and save the addresses 1361 * in an array. 1362 */ 1363 ptr = sc->bge_cdata.bge_jumbo_buf; 1364 for (i = 0; i < BGE_JSLOTS; i++) { 1365 sc->bge_cdata.bge_jslots[i] = ptr; 1366 ptr += BGE_JLEN; 1367 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 1368 entry->slot = i; 1369 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1370 entry, jpool_entries); 1371 } 1372 out: 1373 if (error != 0) { 1374 switch (state) { 1375 case 4: 1376 bus_dmamap_unload(sc->bge_dmatag, 1377 sc->bge_cdata.bge_rx_jumbo_map); 1378 /* FALLTHROUGH */ 1379 case 3: 1380 bus_dmamap_destroy(sc->bge_dmatag, 1381 sc->bge_cdata.bge_rx_jumbo_map); 1382 /* FALLTHROUGH */ 1383 case 2: 1384 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1385 /* FALLTHROUGH */ 1386 case 1: 1387 bus_dmamem_free(sc->bge_dmatag, 1388 &sc->bge_cdata.bge_rx_jumbo_seg, rseg); 1389 break; 1390 default: 1391 break; 1392 } 1393 } 1394 1395 return error; 1396 } 1397 1398 static void 1399 bge_free_jumbo_mem(struct bge_softc *sc) 1400 { 1401 struct bge_jpool_entry *entry, *tmp; 1402 1403 KASSERT(SLIST_EMPTY(&sc->bge_jinuse_listhead)); 1404 1405 SLIST_FOREACH_SAFE(entry, &sc->bge_jfree_listhead, jpool_entries, tmp) { 1406 kmem_free(entry, sizeof(*entry)); 1407 } 1408 1409 bus_dmamap_unload(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1410 1411 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1412 1413 bus_dmamem_unmap(sc->bge_dmatag, sc->bge_cdata.bge_jumbo_buf, BGE_JMEM); 1414 1415 bus_dmamem_free(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1); 1416 } 1417 1418 /* 1419 * Allocate a jumbo buffer. 1420 */ 1421 static void * 1422 bge_jalloc(struct bge_softc *sc) 1423 { 1424 struct bge_jpool_entry *entry; 1425 1426 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1427 1428 if (entry == NULL) { 1429 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1430 return NULL; 1431 } 1432 1433 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1434 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1435 return sc->bge_cdata.bge_jslots[entry->slot]; 1436 } 1437 1438 /* 1439 * Release a jumbo buffer. 1440 */ 1441 static void 1442 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1443 { 1444 struct bge_jpool_entry *entry; 1445 struct bge_softc * const sc = arg; 1446 int s; 1447 1448 if (sc == NULL) 1449 panic("bge_jfree: can't find softc pointer!"); 1450 1451 /* calculate the slot this buffer belongs to */ 1452 int i = ((char *)buf - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1453 1454 if (i < 0 || i >= BGE_JSLOTS) 1455 panic("bge_jfree: asked to free buffer that we don't manage!"); 1456 1457 s = splvm(); 1458 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1459 if (entry == NULL) 1460 panic("bge_jfree: buffer not in use!"); 1461 entry->slot = i; 1462 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1463 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1464 1465 if (__predict_true(m != NULL)) 1466 pool_cache_put(mb_cache, m); 1467 splx(s); 1468 } 1469 1470 1471 /* 1472 * Initialize a standard receive ring descriptor. 1473 */ 1474 static int 1475 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1476 bus_dmamap_t dmamap) 1477 { 1478 struct mbuf *m_new = NULL; 1479 struct bge_rx_bd *r; 1480 int error; 1481 1482 if (dmamap == NULL) 1483 dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1484 1485 if (dmamap == NULL) { 1486 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1487 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1488 if (error != 0) 1489 return error; 1490 } 1491 1492 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1493 1494 if (m == NULL) { 1495 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1496 if (m_new == NULL) 1497 return ENOBUFS; 1498 1499 MCLGET(m_new, M_DONTWAIT); 1500 if (!(m_new->m_flags & M_EXT)) { 1501 m_freem(m_new); 1502 return ENOBUFS; 1503 } 1504 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1505 1506 } else { 1507 m_new = m; 1508 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1509 m_new->m_data = m_new->m_ext.ext_buf; 1510 } 1511 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1512 m_adj(m_new, ETHER_ALIGN); 1513 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1514 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1515 m_freem(m_new); 1516 return ENOBUFS; 1517 } 1518 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1519 BUS_DMASYNC_PREREAD); 1520 1521 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1522 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1523 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1524 r->bge_flags = BGE_RXBDFLAG_END; 1525 r->bge_len = m_new->m_len; 1526 r->bge_idx = i; 1527 1528 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1529 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1530 i * sizeof(struct bge_rx_bd), 1531 sizeof(struct bge_rx_bd), 1532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1533 1534 return 0; 1535 } 1536 1537 /* 1538 * Initialize a jumbo receive ring descriptor. This allocates 1539 * a jumbo buffer from the pool managed internally by the driver. 1540 */ 1541 static int 1542 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1543 { 1544 struct mbuf *m_new = NULL; 1545 struct bge_rx_bd *r; 1546 void *buf = NULL; 1547 1548 if (m == NULL) { 1549 1550 /* Allocate the mbuf. */ 1551 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1552 if (m_new == NULL) 1553 return ENOBUFS; 1554 1555 /* Allocate the jumbo buffer */ 1556 buf = bge_jalloc(sc); 1557 if (buf == NULL) { 1558 m_freem(m_new); 1559 aprint_error_dev(sc->bge_dev, 1560 "jumbo allocation failed -- packet dropped!\n"); 1561 return ENOBUFS; 1562 } 1563 1564 /* Attach the buffer to the mbuf. */ 1565 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1566 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1567 bge_jfree, sc); 1568 m_new->m_flags |= M_EXT_RW; 1569 } else { 1570 m_new = m; 1571 buf = m_new->m_data = m_new->m_ext.ext_buf; 1572 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1573 } 1574 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1575 m_adj(m_new, ETHER_ALIGN); 1576 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1577 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1578 BGE_JLEN, BUS_DMASYNC_PREREAD); 1579 /* Set up the descriptor. */ 1580 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1581 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1582 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1583 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1584 r->bge_len = m_new->m_len; 1585 r->bge_idx = i; 1586 1587 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1588 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1589 i * sizeof(struct bge_rx_bd), 1590 sizeof(struct bge_rx_bd), 1591 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1592 1593 return 0; 1594 } 1595 1596 /* 1597 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1598 * that's 1MB or memory, which is a lot. For now, we fill only the first 1599 * 256 ring entries and hope that our CPU is fast enough to keep up with 1600 * the NIC. 1601 */ 1602 static int 1603 bge_init_rx_ring_std(struct bge_softc *sc) 1604 { 1605 int i; 1606 1607 if (sc->bge_flags & BGEF_RXRING_VALID) 1608 return 0; 1609 1610 for (i = 0; i < BGE_SSLOTS; i++) { 1611 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1612 return ENOBUFS; 1613 } 1614 1615 sc->bge_std = i - 1; 1616 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1617 1618 sc->bge_flags |= BGEF_RXRING_VALID; 1619 1620 return 0; 1621 } 1622 1623 static void 1624 bge_free_rx_ring_std(struct bge_softc *sc, bool disable) 1625 { 1626 int i; 1627 1628 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1629 return; 1630 1631 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1632 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1633 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1634 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1635 if (disable) { 1636 bus_dmamap_destroy(sc->bge_dmatag, 1637 sc->bge_cdata.bge_rx_std_map[i]); 1638 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1639 } 1640 } 1641 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1642 sizeof(struct bge_rx_bd)); 1643 } 1644 1645 sc->bge_flags &= ~BGEF_RXRING_VALID; 1646 } 1647 1648 static int 1649 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1650 { 1651 int i; 1652 volatile struct bge_rcb *rcb; 1653 1654 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1655 return 0; 1656 1657 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1658 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1659 return ENOBUFS; 1660 } 1661 1662 sc->bge_jumbo = i - 1; 1663 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1664 1665 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1666 rcb->bge_maxlen_flags = 0; 1667 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1668 1669 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1670 1671 return 0; 1672 } 1673 1674 static void 1675 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1676 { 1677 int i; 1678 1679 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1680 return; 1681 1682 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1683 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1684 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1685 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1686 } 1687 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1688 sizeof(struct bge_rx_bd)); 1689 } 1690 1691 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1692 } 1693 1694 static void 1695 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1696 { 1697 int i; 1698 struct txdmamap_pool_entry *dma; 1699 1700 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1701 return; 1702 1703 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1704 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1705 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1706 sc->bge_cdata.bge_tx_chain[i] = NULL; 1707 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1708 link); 1709 sc->txdma[i] = 0; 1710 } 1711 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1712 sizeof(struct bge_tx_bd)); 1713 } 1714 1715 if (disable) { 1716 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1717 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1718 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1719 if (sc->bge_dma64) { 1720 bus_dmamap_destroy(sc->bge_dmatag32, 1721 dma->dmamap32); 1722 } 1723 kmem_free(dma, sizeof(*dma)); 1724 } 1725 SLIST_INIT(&sc->txdma_list); 1726 } 1727 1728 sc->bge_flags &= ~BGEF_TXRING_VALID; 1729 } 1730 1731 static int 1732 bge_init_tx_ring(struct bge_softc *sc) 1733 { 1734 struct ifnet * const ifp = &sc->ethercom.ec_if; 1735 int i; 1736 bus_dmamap_t dmamap, dmamap32; 1737 bus_size_t maxsegsz; 1738 struct txdmamap_pool_entry *dma; 1739 1740 if (sc->bge_flags & BGEF_TXRING_VALID) 1741 return 0; 1742 1743 sc->bge_txcnt = 0; 1744 sc->bge_tx_saved_considx = 0; 1745 1746 /* Initialize transmit producer index for host-memory send ring. */ 1747 sc->bge_tx_prodidx = 0; 1748 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1749 /* 5700 b2 errata */ 1750 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1751 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1752 1753 /* NIC-memory send ring not used; initialize to zero. */ 1754 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1755 /* 5700 b2 errata */ 1756 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1757 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1758 1759 /* Limit DMA segment size for some chips */ 1760 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1761 (ifp->if_mtu <= ETHERMTU)) 1762 maxsegsz = 2048; 1763 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1764 maxsegsz = 4096; 1765 else 1766 maxsegsz = ETHER_MAX_LEN_JUMBO; 1767 1768 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1769 goto alloc_done; 1770 1771 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1772 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1773 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1774 &dmamap)) 1775 return ENOBUFS; 1776 if (dmamap == NULL) 1777 panic("dmamap NULL in bge_init_tx_ring"); 1778 if (sc->bge_dma64) { 1779 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1780 BGE_NTXSEG, maxsegsz, 0, 1781 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1782 &dmamap32)) { 1783 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1784 return ENOBUFS; 1785 } 1786 if (dmamap32 == NULL) 1787 panic("dmamap32 NULL in bge_init_tx_ring"); 1788 } else 1789 dmamap32 = dmamap; 1790 dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP); 1791 if (dma == NULL) { 1792 aprint_error_dev(sc->bge_dev, 1793 "can't alloc txdmamap_pool_entry\n"); 1794 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1795 if (sc->bge_dma64) 1796 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1797 return ENOMEM; 1798 } 1799 dma->dmamap = dmamap; 1800 dma->dmamap32 = dmamap32; 1801 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1802 } 1803 alloc_done: 1804 sc->bge_flags |= BGEF_TXRING_VALID; 1805 1806 return 0; 1807 } 1808 1809 static void 1810 bge_setmulti(struct bge_softc *sc) 1811 { 1812 struct ethercom * const ec = &sc->ethercom; 1813 struct ifnet * const ifp = &ec->ec_if; 1814 struct ether_multi *enm; 1815 struct ether_multistep step; 1816 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1817 uint32_t h; 1818 int i; 1819 1820 if (ifp->if_flags & IFF_PROMISC) 1821 goto allmulti; 1822 1823 /* Now program new ones. */ 1824 ETHER_LOCK(ec); 1825 ETHER_FIRST_MULTI(step, ec, enm); 1826 while (enm != NULL) { 1827 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1828 /* 1829 * We must listen to a range of multicast addresses. 1830 * For now, just accept all multicasts, rather than 1831 * trying to set only those filter bits needed to match 1832 * the range. (At this time, the only use of address 1833 * ranges is for IP multicast routing, for which the 1834 * range is big enough to require all bits set.) 1835 */ 1836 ETHER_UNLOCK(ec); 1837 goto allmulti; 1838 } 1839 1840 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1841 1842 /* Just want the 7 least-significant bits. */ 1843 h &= 0x7f; 1844 1845 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1846 ETHER_NEXT_MULTI(step, enm); 1847 } 1848 ETHER_UNLOCK(ec); 1849 1850 ifp->if_flags &= ~IFF_ALLMULTI; 1851 goto setit; 1852 1853 allmulti: 1854 ifp->if_flags |= IFF_ALLMULTI; 1855 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1856 1857 setit: 1858 for (i = 0; i < 4; i++) 1859 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1860 } 1861 1862 static void 1863 bge_sig_pre_reset(struct bge_softc *sc, int type) 1864 { 1865 1866 /* 1867 * Some chips don't like this so only do this if ASF is enabled 1868 */ 1869 if (sc->bge_asf_mode) 1870 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1871 1872 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1873 switch (type) { 1874 case BGE_RESET_START: 1875 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1876 BGE_FW_DRV_STATE_START); 1877 break; 1878 case BGE_RESET_SHUTDOWN: 1879 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1880 BGE_FW_DRV_STATE_UNLOAD); 1881 break; 1882 case BGE_RESET_SUSPEND: 1883 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1884 BGE_FW_DRV_STATE_SUSPEND); 1885 break; 1886 } 1887 } 1888 1889 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1890 bge_ape_driver_state_change(sc, type); 1891 } 1892 1893 static void 1894 bge_sig_post_reset(struct bge_softc *sc, int type) 1895 { 1896 1897 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1898 switch (type) { 1899 case BGE_RESET_START: 1900 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1901 BGE_FW_DRV_STATE_START_DONE); 1902 /* START DONE */ 1903 break; 1904 case BGE_RESET_SHUTDOWN: 1905 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1906 BGE_FW_DRV_STATE_UNLOAD_DONE); 1907 break; 1908 } 1909 } 1910 1911 if (type == BGE_RESET_SHUTDOWN) 1912 bge_ape_driver_state_change(sc, type); 1913 } 1914 1915 static void 1916 bge_sig_legacy(struct bge_softc *sc, int type) 1917 { 1918 1919 if (sc->bge_asf_mode) { 1920 switch (type) { 1921 case BGE_RESET_START: 1922 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1923 BGE_FW_DRV_STATE_START); 1924 break; 1925 case BGE_RESET_SHUTDOWN: 1926 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1927 BGE_FW_DRV_STATE_UNLOAD); 1928 break; 1929 } 1930 } 1931 } 1932 1933 static void 1934 bge_wait_for_event_ack(struct bge_softc *sc) 1935 { 1936 int i; 1937 1938 /* wait up to 2500usec */ 1939 for (i = 0; i < 250; i++) { 1940 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1941 BGE_RX_CPU_DRV_EVENT)) 1942 break; 1943 DELAY(10); 1944 } 1945 } 1946 1947 static void 1948 bge_stop_fw(struct bge_softc *sc) 1949 { 1950 1951 if (sc->bge_asf_mode) { 1952 bge_wait_for_event_ack(sc); 1953 1954 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1955 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1956 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1957 1958 bge_wait_for_event_ack(sc); 1959 } 1960 } 1961 1962 static int 1963 bge_poll_fw(struct bge_softc *sc) 1964 { 1965 uint32_t val; 1966 int i; 1967 1968 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1969 for (i = 0; i < BGE_TIMEOUT; i++) { 1970 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1971 if (val & BGE_VCPU_STATUS_INIT_DONE) 1972 break; 1973 DELAY(100); 1974 } 1975 if (i >= BGE_TIMEOUT) { 1976 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1977 return -1; 1978 } 1979 } else { 1980 /* 1981 * Poll the value location we just wrote until 1982 * we see the 1's complement of the magic number. 1983 * This indicates that the firmware initialization 1984 * is complete. 1985 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1986 */ 1987 for (i = 0; i < BGE_TIMEOUT; i++) { 1988 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 1989 if (val == ~BGE_SRAM_FW_MB_MAGIC) 1990 break; 1991 DELAY(10); 1992 } 1993 1994 if ((i >= BGE_TIMEOUT) 1995 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 1996 aprint_error_dev(sc->bge_dev, 1997 "firmware handshake timed out, val = %x\n", val); 1998 return -1; 1999 } 2000 } 2001 2002 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2003 /* tg3 says we have to wait extra time */ 2004 delay(10 * 1000); 2005 } 2006 2007 return 0; 2008 } 2009 2010 int 2011 bge_phy_addr(struct bge_softc *sc) 2012 { 2013 struct pci_attach_args *pa = &(sc->bge_pa); 2014 int phy_addr = 1; 2015 2016 /* 2017 * PHY address mapping for various devices. 2018 * 2019 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2020 * ---------+-------+-------+-------+-------+ 2021 * BCM57XX | 1 | X | X | X | 2022 * BCM5704 | 1 | X | 1 | X | 2023 * BCM5717 | 1 | 8 | 2 | 9 | 2024 * BCM5719 | 1 | 8 | 2 | 9 | 2025 * BCM5720 | 1 | 8 | 2 | 9 | 2026 * 2027 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2028 * ---------+-------+-------+-------+-------+ 2029 * BCM57XX | X | X | X | X | 2030 * BCM5704 | X | X | X | X | 2031 * BCM5717 | X | X | X | X | 2032 * BCM5719 | 3 | 10 | 4 | 11 | 2033 * BCM5720 | X | X | X | X | 2034 * 2035 * Other addresses may respond but they are not 2036 * IEEE compliant PHYs and should be ignored. 2037 */ 2038 switch (BGE_ASICREV(sc->bge_chipid)) { 2039 case BGE_ASICREV_BCM5717: 2040 case BGE_ASICREV_BCM5719: 2041 case BGE_ASICREV_BCM5720: 2042 phy_addr = pa->pa_function; 2043 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2044 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2045 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2046 } else { 2047 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2048 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2049 } 2050 } 2051 2052 return phy_addr; 2053 } 2054 2055 /* 2056 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2057 * self-test results. 2058 */ 2059 static int 2060 bge_chipinit(struct bge_softc *sc) 2061 { 2062 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2063 int i; 2064 2065 /* Set endianness before we access any non-PCI registers. */ 2066 misc_ctl = BGE_INIT; 2067 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2068 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2069 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2070 misc_ctl); 2071 2072 /* 2073 * Clear the MAC statistics block in the NIC's 2074 * internal memory. 2075 */ 2076 for (i = BGE_STATS_BLOCK; 2077 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2078 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2079 2080 for (i = BGE_STATUS_BLOCK; 2081 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2082 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2083 2084 /* 5717 workaround from tg3 */ 2085 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2086 /* Save */ 2087 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2088 2089 /* Temporary modify MODE_CTL to control TLP */ 2090 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2091 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2092 2093 /* Control TLP */ 2094 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2095 BGE_TLP_PHYCTL1); 2096 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2097 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2098 2099 /* Restore */ 2100 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2101 } 2102 2103 if (BGE_IS_57765_FAMILY(sc)) { 2104 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2105 /* Save */ 2106 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2107 2108 /* Temporary modify MODE_CTL to control TLP */ 2109 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2110 CSR_WRITE_4(sc, BGE_MODE_CTL, 2111 reg | BGE_MODECTL_PCIE_TLPADDR1); 2112 2113 /* Control TLP */ 2114 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2115 BGE_TLP_PHYCTL5); 2116 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2117 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2118 2119 /* Restore */ 2120 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2121 } 2122 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2123 /* 2124 * For the 57766 and non Ax versions of 57765, bootcode 2125 * needs to setup the PCIE Fast Training Sequence (FTS) 2126 * value to prevent transmit hangs. 2127 */ 2128 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2129 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2130 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2131 2132 /* Save */ 2133 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2134 2135 /* Temporary modify MODE_CTL to control TLP */ 2136 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2137 CSR_WRITE_4(sc, BGE_MODE_CTL, 2138 reg | BGE_MODECTL_PCIE_TLPADDR0); 2139 2140 /* Control TLP */ 2141 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2142 BGE_TLP_FTSMAX); 2143 reg &= ~BGE_TLP_FTSMAX_MSK; 2144 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2145 reg | BGE_TLP_FTSMAX_VAL); 2146 2147 /* Restore */ 2148 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2149 } 2150 2151 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2152 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2153 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2154 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2155 } 2156 2157 /* Set up the PCI DMA control register. */ 2158 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2159 if (sc->bge_flags & BGEF_PCIE) { 2160 /* Read watermark not used, 128 bytes for write. */ 2161 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2162 device_xname(sc->bge_dev))); 2163 if (sc->bge_mps >= 256) 2164 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2165 else 2166 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2167 } else if (sc->bge_flags & BGEF_PCIX) { 2168 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2169 device_xname(sc->bge_dev))); 2170 /* PCI-X bus */ 2171 if (BGE_IS_5714_FAMILY(sc)) { 2172 /* 256 bytes for read and write. */ 2173 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2174 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2175 2176 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2177 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2178 else 2179 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2180 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2181 /* 2182 * In the BCM5703, the DMA read watermark should 2183 * be set to less than or equal to the maximum 2184 * memory read byte count of the PCI-X command 2185 * register. 2186 */ 2187 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2188 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2189 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2190 /* 1536 bytes for read, 384 bytes for write. */ 2191 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2192 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2193 } else { 2194 /* 384 bytes for read and write. */ 2195 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2196 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2197 (0x0F); 2198 } 2199 2200 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2201 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2202 uint32_t tmp; 2203 2204 /* Set ONEDMA_ATONCE for hardware workaround. */ 2205 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2206 if (tmp == 6 || tmp == 7) 2207 dma_rw_ctl |= 2208 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2209 2210 /* Set PCI-X DMA write workaround. */ 2211 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2212 } 2213 } else { 2214 /* Conventional PCI bus: 256 bytes for read and write. */ 2215 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2216 device_xname(sc->bge_dev))); 2217 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2218 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2219 2220 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2221 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2222 dma_rw_ctl |= 0x0F; 2223 } 2224 2225 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2226 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2227 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2228 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2229 2230 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2231 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2232 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2233 2234 if (BGE_IS_57765_PLUS(sc)) { 2235 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2236 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2237 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2238 2239 /* 2240 * Enable HW workaround for controllers that misinterpret 2241 * a status tag update and leave interrupts permanently 2242 * disabled. 2243 */ 2244 if (!BGE_IS_57765_FAMILY(sc) && 2245 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2246 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2247 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2248 } 2249 2250 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2251 dma_rw_ctl); 2252 2253 /* 2254 * Set up general mode register. 2255 */ 2256 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2257 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2258 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2259 /* Retain Host-2-BMC settings written by APE firmware. */ 2260 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2261 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2262 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2263 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2264 } 2265 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2266 BGE_MODECTL_TX_NO_PHDR_CSUM; 2267 2268 /* 2269 * BCM5701 B5 have a bug causing data corruption when using 2270 * 64-bit DMA reads, which can be terminated early and then 2271 * completed later as 32-bit accesses, in combination with 2272 * certain bridges. 2273 */ 2274 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2275 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2276 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2277 2278 /* 2279 * Tell the firmware the driver is running 2280 */ 2281 if (sc->bge_asf_mode & ASF_STACKUP) 2282 mode_ctl |= BGE_MODECTL_STACKUP; 2283 2284 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2285 2286 /* 2287 * Disable memory write invalidate. Apparently it is not supported 2288 * properly by these devices. 2289 */ 2290 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2291 PCI_COMMAND_INVALIDATE_ENABLE); 2292 2293 #ifdef __brokenalpha__ 2294 /* 2295 * Must insure that we do not cross an 8K (bytes) boundary 2296 * for DMA reads. Our highest limit is 1K bytes. This is a 2297 * restriction on some ALPHA platforms with early revision 2298 * 21174 PCI chipsets, such as the AlphaPC 164lx 2299 */ 2300 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2301 #endif 2302 2303 /* Set the timer prescaler (always 66MHz) */ 2304 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2305 2306 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2307 DELAY(40); /* XXX */ 2308 2309 /* Put PHY into ready state */ 2310 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2311 DELAY(40); 2312 } 2313 2314 return 0; 2315 } 2316 2317 static int 2318 bge_blockinit(struct bge_softc *sc) 2319 { 2320 volatile struct bge_rcb *rcb; 2321 bus_size_t rcb_addr; 2322 struct ifnet * const ifp = &sc->ethercom.ec_if; 2323 bge_hostaddr taddr; 2324 uint32_t dmactl, rdmareg, mimode, val; 2325 int i, limit; 2326 2327 /* 2328 * Initialize the memory window pointer register so that 2329 * we can access the first 32K of internal NIC RAM. This will 2330 * allow us to set up the TX send ring RCBs and the RX return 2331 * ring RCBs, plus other things which live in NIC memory. 2332 */ 2333 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2334 2335 if (!BGE_IS_5705_PLUS(sc)) { 2336 /* 57XX step 33 */ 2337 /* Configure mbuf memory pool */ 2338 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2339 2340 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2341 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2342 else 2343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2344 2345 /* 57XX step 34 */ 2346 /* Configure DMA resource pool */ 2347 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2348 BGE_DMA_DESCRIPTORS); 2349 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2350 } 2351 2352 /* 5718 step 11, 57XX step 35 */ 2353 /* 2354 * Configure mbuf pool watermarks. New broadcom docs strongly 2355 * recommend these. 2356 */ 2357 if (BGE_IS_5717_PLUS(sc)) { 2358 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2359 if (ifp->if_mtu > ETHERMTU) { 2360 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2362 } else { 2363 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2364 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2365 } 2366 } else if (BGE_IS_5705_PLUS(sc)) { 2367 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2368 2369 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2370 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2371 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2372 } else { 2373 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2374 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2375 } 2376 } else { 2377 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2378 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2379 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2380 } 2381 2382 /* 57XX step 36 */ 2383 /* Configure DMA resource watermarks */ 2384 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2385 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2386 2387 /* 5718 step 13, 57XX step 38 */ 2388 /* Enable buffer manager */ 2389 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2390 /* 2391 * Change the arbitration algorithm of TXMBUF read request to 2392 * round-robin instead of priority based for BCM5719. When 2393 * TXFIFO is almost empty, RDMA will hold its request until 2394 * TXFIFO is not almost empty. 2395 */ 2396 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2397 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2398 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2399 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2400 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2401 val |= BGE_BMANMODE_LOMBUF_ATTN; 2402 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2403 2404 /* 57XX step 39 */ 2405 /* Poll for buffer manager start indication */ 2406 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2407 DELAY(10); 2408 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2409 break; 2410 } 2411 2412 if (i == BGE_TIMEOUT * 2) { 2413 aprint_error_dev(sc->bge_dev, 2414 "buffer manager failed to start\n"); 2415 return ENXIO; 2416 } 2417 2418 /* 57XX step 40 */ 2419 /* Enable flow-through queues */ 2420 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2421 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2422 2423 /* Wait until queue initialization is complete */ 2424 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2425 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2426 break; 2427 DELAY(10); 2428 } 2429 2430 if (i == BGE_TIMEOUT * 2) { 2431 aprint_error_dev(sc->bge_dev, 2432 "flow-through queue init failed\n"); 2433 return ENXIO; 2434 } 2435 2436 /* 2437 * Summary of rings supported by the controller: 2438 * 2439 * Standard Receive Producer Ring 2440 * - This ring is used to feed receive buffers for "standard" 2441 * sized frames (typically 1536 bytes) to the controller. 2442 * 2443 * Jumbo Receive Producer Ring 2444 * - This ring is used to feed receive buffers for jumbo sized 2445 * frames (i.e. anything bigger than the "standard" frames) 2446 * to the controller. 2447 * 2448 * Mini Receive Producer Ring 2449 * - This ring is used to feed receive buffers for "mini" 2450 * sized frames to the controller. 2451 * - This feature required external memory for the controller 2452 * but was never used in a production system. Should always 2453 * be disabled. 2454 * 2455 * Receive Return Ring 2456 * - After the controller has placed an incoming frame into a 2457 * receive buffer that buffer is moved into a receive return 2458 * ring. The driver is then responsible to passing the 2459 * buffer up to the stack. Many versions of the controller 2460 * support multiple RR rings. 2461 * 2462 * Send Ring 2463 * - This ring is used for outgoing frames. Many versions of 2464 * the controller support multiple send rings. 2465 */ 2466 2467 /* 5718 step 15, 57XX step 41 */ 2468 /* Initialize the standard RX ring control block */ 2469 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2470 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2471 /* 5718 step 16 */ 2472 if (BGE_IS_57765_PLUS(sc)) { 2473 /* 2474 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2475 * Bits 15-2 : Maximum RX frame size 2476 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2477 * Bit 0 : Reserved 2478 */ 2479 rcb->bge_maxlen_flags = 2480 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2481 } else if (BGE_IS_5705_PLUS(sc)) { 2482 /* 2483 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2484 * Bits 15-2 : Reserved (should be 0) 2485 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2486 * Bit 0 : Reserved 2487 */ 2488 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2489 } else { 2490 /* 2491 * Ring size is always XXX entries 2492 * Bits 31-16: Maximum RX frame size 2493 * Bits 15-2 : Reserved (should be 0) 2494 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2495 * Bit 0 : Reserved 2496 */ 2497 rcb->bge_maxlen_flags = 2498 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2499 } 2500 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2501 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2502 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2503 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2504 else 2505 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2506 /* Write the standard receive producer ring control block. */ 2507 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2508 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2509 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2510 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2511 2512 /* Reset the standard receive producer ring producer index. */ 2513 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2514 2515 /* 57XX step 42 */ 2516 /* 2517 * Initialize the jumbo RX ring control block 2518 * We set the 'ring disabled' bit in the flags 2519 * field until we're actually ready to start 2520 * using this ring (i.e. once we set the MTU 2521 * high enough to require it). 2522 */ 2523 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2524 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2525 BGE_HOSTADDR(rcb->bge_hostaddr, 2526 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2527 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2528 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2529 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2530 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2531 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2532 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2533 else 2534 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2535 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2536 rcb->bge_hostaddr.bge_addr_hi); 2537 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2538 rcb->bge_hostaddr.bge_addr_lo); 2539 /* Program the jumbo receive producer ring RCB parameters. */ 2540 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2541 rcb->bge_maxlen_flags); 2542 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2543 /* Reset the jumbo receive producer ring producer index. */ 2544 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2545 } 2546 2547 /* 57XX step 43 */ 2548 /* Disable the mini receive producer ring RCB. */ 2549 if (BGE_IS_5700_FAMILY(sc)) { 2550 /* Set up dummy disabled mini ring RCB */ 2551 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2552 rcb->bge_maxlen_flags = 2553 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2554 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2555 rcb->bge_maxlen_flags); 2556 /* Reset the mini receive producer ring producer index. */ 2557 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2558 2559 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2560 offsetof(struct bge_ring_data, bge_info), 2561 sizeof(struct bge_gib), 2562 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2563 } 2564 2565 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2566 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2567 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2568 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2569 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2570 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2571 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2572 } 2573 /* 5718 step 14, 57XX step 44 */ 2574 /* 2575 * The BD ring replenish thresholds control how often the 2576 * hardware fetches new BD's from the producer rings in host 2577 * memory. Setting the value too low on a busy system can 2578 * starve the hardware and recue the throughpout. 2579 * 2580 * Set the BD ring replenish thresholds. The recommended 2581 * values are 1/8th the number of descriptors allocated to 2582 * each ring, but since we try to avoid filling the entire 2583 * ring we set these to the minimal value of 8. This needs to 2584 * be done on several of the supported chip revisions anyway, 2585 * to work around HW bugs. 2586 */ 2587 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2588 if (BGE_IS_JUMBO_CAPABLE(sc)) 2589 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2590 2591 /* 5718 step 18 */ 2592 if (BGE_IS_5717_PLUS(sc)) { 2593 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2594 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2595 } 2596 2597 /* 57XX step 45 */ 2598 /* 2599 * Disable all send rings by setting the 'ring disabled' bit 2600 * in the flags field of all the TX send ring control blocks, 2601 * located in NIC memory. 2602 */ 2603 if (BGE_IS_5700_FAMILY(sc)) { 2604 /* 5700 to 5704 had 16 send rings. */ 2605 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2606 } else if (BGE_IS_5717_PLUS(sc)) { 2607 limit = BGE_TX_RINGS_5717_MAX; 2608 } else if (BGE_IS_57765_FAMILY(sc) || 2609 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2610 limit = BGE_TX_RINGS_57765_MAX; 2611 } else 2612 limit = 1; 2613 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2614 for (i = 0; i < limit; i++) { 2615 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2616 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2617 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2618 rcb_addr += sizeof(struct bge_rcb); 2619 } 2620 2621 /* 57XX step 46 and 47 */ 2622 /* Configure send ring RCB 0 (we use only the first ring) */ 2623 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2624 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2625 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2626 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2627 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2628 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2629 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2630 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2631 else 2632 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2633 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2634 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2635 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2636 2637 /* 57XX step 48 */ 2638 /* 2639 * Disable all receive return rings by setting the 2640 * 'ring diabled' bit in the flags field of all the receive 2641 * return ring control blocks, located in NIC memory. 2642 */ 2643 if (BGE_IS_5717_PLUS(sc)) { 2644 /* Should be 17, use 16 until we get an SRAM map. */ 2645 limit = 16; 2646 } else if (BGE_IS_5700_FAMILY(sc)) 2647 limit = BGE_RX_RINGS_MAX; 2648 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2649 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2650 BGE_IS_57765_FAMILY(sc)) 2651 limit = 4; 2652 else 2653 limit = 1; 2654 /* Disable all receive return rings */ 2655 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2656 for (i = 0; i < limit; i++) { 2657 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2658 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2659 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2660 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2661 BGE_RCB_FLAG_RING_DISABLED)); 2662 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2663 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2664 (i * (sizeof(uint64_t))), 0); 2665 rcb_addr += sizeof(struct bge_rcb); 2666 } 2667 2668 /* 57XX step 49 */ 2669 /* 2670 * Set up receive return ring 0. Note that the NIC address 2671 * for RX return rings is 0x0. The return rings live entirely 2672 * within the host, so the nicaddr field in the RCB isn't used. 2673 */ 2674 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2675 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2676 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2677 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2678 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2679 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2680 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2681 2682 /* 5718 step 24, 57XX step 53 */ 2683 /* Set random backoff seed for TX */ 2684 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2685 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2686 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2687 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2688 BGE_TX_BACKOFF_SEED_MASK); 2689 2690 /* 5718 step 26, 57XX step 55 */ 2691 /* Set inter-packet gap */ 2692 val = 0x2620; 2693 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2694 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2695 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2696 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2697 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2698 2699 /* 5718 step 27, 57XX step 56 */ 2700 /* 2701 * Specify which ring to use for packets that don't match 2702 * any RX rules. 2703 */ 2704 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2705 2706 /* 5718 step 28, 57XX step 57 */ 2707 /* 2708 * Configure number of RX lists. One interrupt distribution 2709 * list, sixteen active lists, one bad frames class. 2710 */ 2711 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2712 2713 /* 5718 step 29, 57XX step 58 */ 2714 /* Inialize RX list placement stats mask. */ 2715 if (BGE_IS_575X_PLUS(sc)) { 2716 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2717 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2718 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2719 } else 2720 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2721 2722 /* 5718 step 30, 57XX step 59 */ 2723 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2724 2725 /* 5718 step 33, 57XX step 62 */ 2726 /* Disable host coalescing until we get it set up */ 2727 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2728 2729 /* 5718 step 34, 57XX step 63 */ 2730 /* Poll to make sure it's shut down. */ 2731 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2732 DELAY(10); 2733 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2734 break; 2735 } 2736 2737 if (i == BGE_TIMEOUT * 2) { 2738 aprint_error_dev(sc->bge_dev, 2739 "host coalescing engine failed to idle\n"); 2740 return ENXIO; 2741 } 2742 2743 /* 5718 step 35, 36, 37 */ 2744 /* Set up host coalescing defaults */ 2745 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2746 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2747 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2748 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2749 if (!(BGE_IS_5705_PLUS(sc))) { 2750 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2751 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2752 } 2753 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2754 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2755 2756 /* Set up address of statistics block */ 2757 if (BGE_IS_5700_FAMILY(sc)) { 2758 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2759 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2760 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2761 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2762 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2763 } 2764 2765 /* 5718 step 38 */ 2766 /* Set up address of status block */ 2767 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2768 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2769 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2770 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2771 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2772 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2773 2774 /* Set up status block size. */ 2775 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2776 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2777 val = BGE_STATBLKSZ_FULL; 2778 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2779 } else { 2780 val = BGE_STATBLKSZ_32BYTE; 2781 bzero(&sc->bge_rdata->bge_status_block, 32); 2782 } 2783 2784 /* 5718 step 39, 57XX step 73 */ 2785 /* Turn on host coalescing state machine */ 2786 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2787 2788 /* 5718 step 40, 57XX step 74 */ 2789 /* Turn on RX BD completion state machine and enable attentions */ 2790 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2791 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2792 2793 /* 5718 step 41, 57XX step 75 */ 2794 /* Turn on RX list placement state machine */ 2795 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2796 2797 /* 57XX step 76 */ 2798 /* Turn on RX list selector state machine. */ 2799 if (!(BGE_IS_5705_PLUS(sc))) 2800 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2801 2802 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2803 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2804 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2805 BGE_MACMODE_FRMHDR_DMA_ENB; 2806 2807 if (sc->bge_flags & BGEF_FIBER_TBI) 2808 val |= BGE_PORTMODE_TBI; 2809 else if (sc->bge_flags & BGEF_FIBER_MII) 2810 val |= BGE_PORTMODE_GMII; 2811 else 2812 val |= BGE_PORTMODE_MII; 2813 2814 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2815 /* Allow APE to send/receive frames. */ 2816 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2817 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2818 2819 /* Turn on DMA, clear stats */ 2820 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2821 /* 5718 step 44 */ 2822 DELAY(40); 2823 2824 /* 5718 step 45, 57XX step 79 */ 2825 /* Set misc. local control, enable interrupts on attentions */ 2826 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2827 if (BGE_IS_5717_PLUS(sc)) { 2828 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2829 /* 5718 step 46 */ 2830 DELAY(100); 2831 } 2832 2833 /* 57XX step 81 */ 2834 /* Turn on DMA completion state machine */ 2835 if (!(BGE_IS_5705_PLUS(sc))) 2836 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2837 2838 /* 5718 step 47, 57XX step 82 */ 2839 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2840 2841 /* 5718 step 48 */ 2842 /* Enable host coalescing bug fix. */ 2843 if (BGE_IS_5755_PLUS(sc)) 2844 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2845 2846 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2847 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2848 2849 /* Turn on write DMA state machine */ 2850 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2851 /* 5718 step 49 */ 2852 DELAY(40); 2853 2854 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2855 2856 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2857 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2858 2859 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2860 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2861 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2862 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2863 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2864 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2865 2866 if (sc->bge_flags & BGEF_PCIE) 2867 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2868 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2869 if (ifp->if_mtu <= ETHERMTU) 2870 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2871 } 2872 if (sc->bge_flags & BGEF_TSO) { 2873 val |= BGE_RDMAMODE_TSO4_ENABLE; 2874 if (BGE_IS_5717_PLUS(sc)) 2875 val |= BGE_RDMAMODE_TSO6_ENABLE; 2876 } 2877 2878 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2879 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2880 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2881 BGE_RDMAMODE_H2BNC_VLAN_DET; 2882 /* 2883 * Allow multiple outstanding read requests from 2884 * non-LSO read DMA engine. 2885 */ 2886 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2887 } 2888 2889 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2890 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2891 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2892 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2893 BGE_IS_57765_PLUS(sc)) { 2894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2895 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2896 else 2897 rdmareg = BGE_RDMA_RSRVCTRL; 2898 dmactl = CSR_READ_4(sc, rdmareg); 2899 /* 2900 * Adjust tx margin to prevent TX data corruption and 2901 * fix internal FIFO overflow. 2902 */ 2903 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2904 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2905 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2906 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2907 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2908 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2909 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2910 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2911 } 2912 /* 2913 * Enable fix for read DMA FIFO overruns. 2914 * The fix is to limit the number of RX BDs 2915 * the hardware would fetch at a time. 2916 */ 2917 CSR_WRITE_4(sc, rdmareg, dmactl | 2918 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2919 } 2920 2921 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2922 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2923 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2924 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2925 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2926 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2927 /* 2928 * Allow 4KB burst length reads for non-LSO frames. 2929 * Enable 512B burst length reads for buffer descriptors. 2930 */ 2931 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2932 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2933 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2934 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2935 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2936 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2937 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2938 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2939 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2940 } 2941 /* Turn on read DMA state machine */ 2942 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2943 /* 5718 step 52 */ 2944 delay(40); 2945 2946 if (sc->bge_flags & BGEF_RDMA_BUG) { 2947 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2948 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2949 if ((val & 0xFFFF) > BGE_FRAMELEN) 2950 break; 2951 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2952 break; 2953 } 2954 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2955 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2956 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2957 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2958 else 2959 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2960 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2961 } 2962 } 2963 2964 /* 5718 step 56, 57XX step 84 */ 2965 /* Turn on RX data completion state machine */ 2966 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2967 2968 /* Turn on RX data and RX BD initiator state machine */ 2969 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2970 2971 /* 57XX step 85 */ 2972 /* Turn on Mbuf cluster free state machine */ 2973 if (!BGE_IS_5705_PLUS(sc)) 2974 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2975 2976 /* 5718 step 57, 57XX step 86 */ 2977 /* Turn on send data completion state machine */ 2978 val = BGE_SDCMODE_ENABLE; 2979 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2980 val |= BGE_SDCMODE_CDELAY; 2981 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2982 2983 /* 5718 step 58 */ 2984 /* Turn on send BD completion state machine */ 2985 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2986 2987 /* 57XX step 88 */ 2988 /* Turn on RX BD initiator state machine */ 2989 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2990 2991 /* 5718 step 60, 57XX step 90 */ 2992 /* Turn on send data initiator state machine */ 2993 if (sc->bge_flags & BGEF_TSO) { 2994 /* XXX: magic value from Linux driver */ 2995 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2996 BGE_SDIMODE_HW_LSO_PRE_DMA); 2997 } else 2998 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2999 3000 /* 5718 step 61, 57XX step 91 */ 3001 /* Turn on send BD initiator state machine */ 3002 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3003 3004 /* 5718 step 62, 57XX step 92 */ 3005 /* Turn on send BD selector state machine */ 3006 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3007 3008 /* 5718 step 31, 57XX step 60 */ 3009 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3010 /* 5718 step 32, 57XX step 61 */ 3011 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3012 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3013 3014 /* ack/clear link change events */ 3015 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3016 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3017 BGE_MACSTAT_LINK_CHANGED); 3018 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3019 3020 /* 3021 * Enable attention when the link has changed state for 3022 * devices that use auto polling. 3023 */ 3024 if (sc->bge_flags & BGEF_FIBER_TBI) { 3025 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3026 } else { 3027 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3028 mimode = BGE_MIMODE_500KHZ_CONST; 3029 else 3030 mimode = BGE_MIMODE_BASE; 3031 /* 5718 step 68. 5718 step 69 (optionally). */ 3032 if (BGE_IS_5700_FAMILY(sc) || 3033 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3034 mimode |= BGE_MIMODE_AUTOPOLL; 3035 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3036 } 3037 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3038 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3039 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3040 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3041 BGE_EVTENB_MI_INTERRUPT); 3042 } 3043 3044 /* 3045 * Clear any pending link state attention. 3046 * Otherwise some link state change events may be lost until attention 3047 * is cleared by bge_intr() -> bge_link_upd() sequence. 3048 * It's not necessary on newer BCM chips - perhaps enabling link 3049 * state change attentions implies clearing pending attention. 3050 */ 3051 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3052 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3053 BGE_MACSTAT_LINK_CHANGED); 3054 3055 /* Enable link state change attentions. */ 3056 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3057 3058 return 0; 3059 } 3060 3061 static const struct bge_revision * 3062 bge_lookup_rev(uint32_t chipid) 3063 { 3064 const struct bge_revision *br; 3065 3066 for (br = bge_revisions; br->br_name != NULL; br++) { 3067 if (br->br_chipid == chipid) 3068 return br; 3069 } 3070 3071 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3072 if (br->br_chipid == BGE_ASICREV(chipid)) 3073 return br; 3074 } 3075 3076 return NULL; 3077 } 3078 3079 static const struct bge_product * 3080 bge_lookup(const struct pci_attach_args *pa) 3081 { 3082 const struct bge_product *bp; 3083 3084 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3085 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3086 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3087 return bp; 3088 } 3089 3090 return NULL; 3091 } 3092 3093 static uint32_t 3094 bge_chipid(const struct pci_attach_args *pa) 3095 { 3096 uint32_t id; 3097 3098 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3099 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3100 3101 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3102 switch (PCI_PRODUCT(pa->pa_id)) { 3103 case PCI_PRODUCT_BROADCOM_BCM5717: 3104 case PCI_PRODUCT_BROADCOM_BCM5718: 3105 case PCI_PRODUCT_BROADCOM_BCM5719: 3106 case PCI_PRODUCT_BROADCOM_BCM5720: 3107 case PCI_PRODUCT_BROADCOM_BCM5725: 3108 case PCI_PRODUCT_BROADCOM_BCM5727: 3109 case PCI_PRODUCT_BROADCOM_BCM5762: 3110 case PCI_PRODUCT_BROADCOM_BCM57764: 3111 case PCI_PRODUCT_BROADCOM_BCM57767: 3112 case PCI_PRODUCT_BROADCOM_BCM57787: 3113 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3114 BGE_PCI_GEN2_PRODID_ASICREV); 3115 break; 3116 case PCI_PRODUCT_BROADCOM_BCM57761: 3117 case PCI_PRODUCT_BROADCOM_BCM57762: 3118 case PCI_PRODUCT_BROADCOM_BCM57765: 3119 case PCI_PRODUCT_BROADCOM_BCM57766: 3120 case PCI_PRODUCT_BROADCOM_BCM57781: 3121 case PCI_PRODUCT_BROADCOM_BCM57782: 3122 case PCI_PRODUCT_BROADCOM_BCM57785: 3123 case PCI_PRODUCT_BROADCOM_BCM57786: 3124 case PCI_PRODUCT_BROADCOM_BCM57791: 3125 case PCI_PRODUCT_BROADCOM_BCM57795: 3126 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3127 BGE_PCI_GEN15_PRODID_ASICREV); 3128 break; 3129 default: 3130 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3131 BGE_PCI_PRODID_ASICREV); 3132 break; 3133 } 3134 } 3135 3136 return id; 3137 } 3138 3139 /* 3140 * Return true if MSI can be used with this device. 3141 */ 3142 static int 3143 bge_can_use_msi(struct bge_softc *sc) 3144 { 3145 int can_use_msi = 0; 3146 3147 switch (BGE_ASICREV(sc->bge_chipid)) { 3148 case BGE_ASICREV_BCM5714_A0: 3149 case BGE_ASICREV_BCM5714: 3150 /* 3151 * Apparently, MSI doesn't work when these chips are 3152 * configured in single-port mode. 3153 */ 3154 break; 3155 case BGE_ASICREV_BCM5750: 3156 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3157 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3158 can_use_msi = 1; 3159 break; 3160 default: 3161 if (BGE_IS_575X_PLUS(sc)) 3162 can_use_msi = 1; 3163 } 3164 return can_use_msi; 3165 } 3166 3167 /* 3168 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3169 * against our list and return its name if we find a match. Note 3170 * that since the Broadcom controller contains VPD support, we 3171 * can get the device name string from the controller itself instead 3172 * of the compiled-in string. This is a little slow, but it guarantees 3173 * we'll always announce the right product name. 3174 */ 3175 static int 3176 bge_probe(device_t parent, cfdata_t match, void *aux) 3177 { 3178 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3179 3180 if (bge_lookup(pa) != NULL) 3181 return 1; 3182 3183 return 0; 3184 } 3185 3186 static void 3187 bge_attach(device_t parent, device_t self, void *aux) 3188 { 3189 struct bge_softc * const sc = device_private(self); 3190 struct pci_attach_args * const pa = aux; 3191 prop_dictionary_t dict; 3192 const struct bge_product *bp; 3193 const struct bge_revision *br; 3194 pci_chipset_tag_t pc; 3195 const char *intrstr = NULL; 3196 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3197 uint32_t command; 3198 struct ifnet *ifp; 3199 struct mii_data * const mii = &sc->bge_mii; 3200 uint32_t misccfg, mimode, macmode; 3201 void * kva; 3202 u_char eaddr[ETHER_ADDR_LEN]; 3203 pcireg_t memtype, subid, reg; 3204 bus_addr_t memaddr; 3205 uint32_t pm_ctl; 3206 bool no_seeprom; 3207 int capmask, trys; 3208 int mii_flags; 3209 int map_flags; 3210 char intrbuf[PCI_INTRSTR_LEN]; 3211 3212 bp = bge_lookup(pa); 3213 KASSERT(bp != NULL); 3214 3215 sc->sc_pc = pa->pa_pc; 3216 sc->sc_pcitag = pa->pa_tag; 3217 sc->bge_dev = self; 3218 3219 sc->bge_pa = *pa; 3220 pc = sc->sc_pc; 3221 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3222 3223 aprint_naive(": Ethernet controller\n"); 3224 aprint_normal(": %s Ethernet\n", bp->bp_name); 3225 3226 /* 3227 * Map control/status registers. 3228 */ 3229 DPRINTFN(5, ("Map control/status regs\n")); 3230 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3231 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3232 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3233 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3234 3235 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3236 aprint_error_dev(sc->bge_dev, 3237 "failed to enable memory mapping!\n"); 3238 return; 3239 } 3240 3241 DPRINTFN(5, ("pci_mem_find\n")); 3242 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3243 switch (memtype) { 3244 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3245 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3246 #if 0 3247 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3248 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3249 &memaddr, &sc->bge_bsize) == 0) 3250 break; 3251 #else 3252 /* 3253 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3254 * system get NMI on boot (PR#48451). This problem might not be 3255 * the driver's bug but our PCI common part's bug. Until we 3256 * find a real reason, we ignore the prefetchable bit. 3257 */ 3258 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3259 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3260 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3261 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3262 map_flags, &sc->bge_bhandle) == 0) { 3263 sc->bge_btag = pa->pa_memt; 3264 break; 3265 } 3266 } 3267 #endif 3268 /* FALLTHROUGH */ 3269 default: 3270 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3271 return; 3272 } 3273 3274 /* Save various chip information. */ 3275 sc->bge_chipid = bge_chipid(pa); 3276 sc->bge_phy_addr = bge_phy_addr(sc); 3277 3278 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3279 &sc->bge_pciecap, NULL) != 0) { 3280 /* PCIe */ 3281 sc->bge_flags |= BGEF_PCIE; 3282 /* Extract supported maximum payload size. */ 3283 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3284 sc->bge_pciecap + PCIE_DCAP); 3285 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3286 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3287 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3288 sc->bge_expmrq = 2048; 3289 else 3290 sc->bge_expmrq = 4096; 3291 bge_set_max_readrq(sc); 3292 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3293 /* PCIe without PCIe cap */ 3294 sc->bge_flags |= BGEF_PCIE; 3295 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3296 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3297 /* PCI-X */ 3298 sc->bge_flags |= BGEF_PCIX; 3299 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3300 &sc->bge_pcixcap, NULL) == 0) 3301 aprint_error_dev(sc->bge_dev, 3302 "unable to find PCIX capability\n"); 3303 } 3304 3305 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3306 /* 3307 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3308 * can clobber the chip's PCI config-space power control 3309 * registers, leaving the card in D3 powersave state. We do 3310 * not have memory-mapped registers in this state, so force 3311 * device into D0 state before starting initialization. 3312 */ 3313 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3314 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3315 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3316 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3317 DELAY(1000); /* 27 usec is allegedly sufficient */ 3318 } 3319 3320 /* Save chipset family. */ 3321 switch (BGE_ASICREV(sc->bge_chipid)) { 3322 case BGE_ASICREV_BCM5717: 3323 case BGE_ASICREV_BCM5719: 3324 case BGE_ASICREV_BCM5720: 3325 sc->bge_flags |= BGEF_5717_PLUS; 3326 /* FALLTHROUGH */ 3327 case BGE_ASICREV_BCM5762: 3328 case BGE_ASICREV_BCM57765: 3329 case BGE_ASICREV_BCM57766: 3330 if (!BGE_IS_5717_PLUS(sc)) 3331 sc->bge_flags |= BGEF_57765_FAMILY; 3332 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3333 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3334 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3335 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3336 /* 3337 * Enable work around for DMA engine miscalculation 3338 * of TXMBUF available space. 3339 */ 3340 sc->bge_flags |= BGEF_RDMA_BUG; 3341 3342 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3343 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3344 /* Jumbo frame on BCM5719 A0 does not work. */ 3345 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3346 } 3347 } 3348 break; 3349 case BGE_ASICREV_BCM5755: 3350 case BGE_ASICREV_BCM5761: 3351 case BGE_ASICREV_BCM5784: 3352 case BGE_ASICREV_BCM5785: 3353 case BGE_ASICREV_BCM5787: 3354 case BGE_ASICREV_BCM57780: 3355 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3356 break; 3357 case BGE_ASICREV_BCM5700: 3358 case BGE_ASICREV_BCM5701: 3359 case BGE_ASICREV_BCM5703: 3360 case BGE_ASICREV_BCM5704: 3361 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3362 break; 3363 case BGE_ASICREV_BCM5714_A0: 3364 case BGE_ASICREV_BCM5780: 3365 case BGE_ASICREV_BCM5714: 3366 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3367 /* FALLTHROUGH */ 3368 case BGE_ASICREV_BCM5750: 3369 case BGE_ASICREV_BCM5752: 3370 case BGE_ASICREV_BCM5906: 3371 sc->bge_flags |= BGEF_575X_PLUS; 3372 /* FALLTHROUGH */ 3373 case BGE_ASICREV_BCM5705: 3374 sc->bge_flags |= BGEF_5705_PLUS; 3375 break; 3376 } 3377 3378 /* Identify chips with APE processor. */ 3379 switch (BGE_ASICREV(sc->bge_chipid)) { 3380 case BGE_ASICREV_BCM5717: 3381 case BGE_ASICREV_BCM5719: 3382 case BGE_ASICREV_BCM5720: 3383 case BGE_ASICREV_BCM5761: 3384 case BGE_ASICREV_BCM5762: 3385 sc->bge_flags |= BGEF_APE; 3386 break; 3387 } 3388 3389 /* 3390 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3391 * not actually a MAC controller bug but an issue with the embedded 3392 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3393 */ 3394 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3395 sc->bge_flags |= BGEF_40BIT_BUG; 3396 3397 /* Chips with APE need BAR2 access for APE registers/memory. */ 3398 if ((sc->bge_flags & BGEF_APE) != 0) { 3399 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3400 #if 0 3401 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3402 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3403 &sc->bge_apesize)) { 3404 aprint_error_dev(sc->bge_dev, 3405 "couldn't map BAR2 memory\n"); 3406 return; 3407 } 3408 #else 3409 /* 3410 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3411 * system get NMI on boot (PR#48451). This problem might not be 3412 * the driver's bug but our PCI common part's bug. Until we 3413 * find a real reason, we ignore the prefetchable bit. 3414 */ 3415 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3416 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3417 aprint_error_dev(sc->bge_dev, 3418 "couldn't map BAR2 memory\n"); 3419 return; 3420 } 3421 3422 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3423 if (bus_space_map(pa->pa_memt, memaddr, 3424 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3425 aprint_error_dev(sc->bge_dev, 3426 "couldn't map BAR2 memory\n"); 3427 return; 3428 } 3429 sc->bge_apetag = pa->pa_memt; 3430 #endif 3431 3432 /* Enable APE register/memory access by host driver. */ 3433 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3434 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3435 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3436 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3437 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3438 3439 bge_ape_lock_init(sc); 3440 bge_ape_read_fw_ver(sc); 3441 } 3442 3443 /* Identify the chips that use an CPMU. */ 3444 if (BGE_IS_5717_PLUS(sc) || 3445 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3446 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3447 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3448 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3449 sc->bge_flags |= BGEF_CPMU_PRESENT; 3450 3451 /* 3452 * When using the BCM5701 in PCI-X mode, data corruption has 3453 * been observed in the first few bytes of some received packets. 3454 * Aligning the packet buffer in memory eliminates the corruption. 3455 * Unfortunately, this misaligns the packet payloads. On platforms 3456 * which do not support unaligned accesses, we will realign the 3457 * payloads by copying the received packets. 3458 */ 3459 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3460 sc->bge_flags & BGEF_PCIX) 3461 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3462 3463 if (BGE_IS_5700_FAMILY(sc)) 3464 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3465 3466 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3467 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3468 3469 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3470 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3471 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3472 sc->bge_flags |= BGEF_IS_5788; 3473 3474 /* 3475 * Some controllers seem to require a special firmware to use 3476 * TSO. But the firmware is not available to FreeBSD and Linux 3477 * claims that the TSO performed by the firmware is slower than 3478 * hardware based TSO. Moreover the firmware based TSO has one 3479 * known bug which can't handle TSO if ethernet header + IP/TCP 3480 * header is greater than 80 bytes. The workaround for the TSO 3481 * bug exist but it seems it's too expensive than not using 3482 * TSO at all. Some hardwares also have the TSO bug so limit 3483 * the TSO to the controllers that are not affected TSO issues 3484 * (e.g. 5755 or higher). 3485 */ 3486 if (BGE_IS_5755_PLUS(sc)) { 3487 /* 3488 * BCM5754 and BCM5787 shares the same ASIC id so 3489 * explicit device id check is required. 3490 */ 3491 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3492 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3493 sc->bge_flags |= BGEF_TSO; 3494 /* TSO on BCM5719 A0 does not work. */ 3495 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3496 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3497 sc->bge_flags &= ~BGEF_TSO; 3498 } 3499 3500 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3501 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3502 (misccfg == 0x4000 || misccfg == 0x8000)) || 3503 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3504 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3505 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3506 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3507 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3508 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3509 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3510 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3511 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3512 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3513 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3514 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3515 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3516 /* These chips are 10/100 only. */ 3517 capmask &= ~BMSR_EXTSTAT; 3518 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3519 } 3520 3521 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3522 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3523 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3524 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3525 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3526 3527 /* Set various PHY bug flags. */ 3528 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3529 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3530 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3531 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3532 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3533 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3534 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3535 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3536 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3537 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3538 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3539 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3540 if (BGE_IS_5705_PLUS(sc) && 3541 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3542 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3543 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3544 !BGE_IS_57765_PLUS(sc)) { 3545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3546 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3547 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3548 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3549 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3550 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3551 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3552 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3553 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3554 } else 3555 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3556 } 3557 3558 /* 3559 * SEEPROM check. 3560 * First check if firmware knows we do not have SEEPROM. 3561 */ 3562 if (prop_dictionary_get_bool(device_properties(self), 3563 "without-seeprom", &no_seeprom) && no_seeprom) 3564 sc->bge_flags |= BGEF_NO_EEPROM; 3565 3566 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3567 sc->bge_flags |= BGEF_NO_EEPROM; 3568 3569 /* Now check the 'ROM failed' bit on the RX CPU */ 3570 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3571 sc->bge_flags |= BGEF_NO_EEPROM; 3572 3573 sc->bge_asf_mode = 0; 3574 /* No ASF if APE present. */ 3575 if ((sc->bge_flags & BGEF_APE) == 0) { 3576 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3577 BGE_SRAM_DATA_SIG_MAGIC)) { 3578 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3579 BGE_HWCFG_ASF) { 3580 sc->bge_asf_mode |= ASF_ENABLE; 3581 sc->bge_asf_mode |= ASF_STACKUP; 3582 if (BGE_IS_575X_PLUS(sc)) 3583 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3584 } 3585 } 3586 } 3587 3588 int counts[PCI_INTR_TYPE_SIZE] = { 3589 [PCI_INTR_TYPE_INTX] = 1, 3590 [PCI_INTR_TYPE_MSI] = 1, 3591 [PCI_INTR_TYPE_MSIX] = 1, 3592 }; 3593 int max_type = PCI_INTR_TYPE_MSIX; 3594 3595 if (!bge_can_use_msi(sc)) { 3596 /* MSI broken, allow only INTx */ 3597 max_type = PCI_INTR_TYPE_INTX; 3598 } 3599 3600 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3601 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3602 return; 3603 } 3604 3605 DPRINTFN(5, ("pci_intr_string\n")); 3606 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3607 sizeof(intrbuf)); 3608 DPRINTFN(5, ("pci_intr_establish\n")); 3609 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3610 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3611 if (sc->bge_intrhand == NULL) { 3612 pci_intr_release(pc, sc->bge_pihp, 1); 3613 sc->bge_pihp = NULL; 3614 3615 aprint_error_dev(self, "couldn't establish interrupt"); 3616 if (intrstr != NULL) 3617 aprint_error(" at %s", intrstr); 3618 aprint_error("\n"); 3619 return; 3620 } 3621 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3622 3623 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3624 case PCI_INTR_TYPE_MSIX: 3625 case PCI_INTR_TYPE_MSI: 3626 KASSERT(bge_can_use_msi(sc)); 3627 sc->bge_flags |= BGEF_MSI; 3628 break; 3629 default: 3630 /* nothing to do */ 3631 break; 3632 } 3633 3634 /* 3635 * All controllers except BCM5700 supports tagged status but 3636 * we use tagged status only for MSI case on BCM5717. Otherwise 3637 * MSI on BCM5717 does not work. 3638 */ 3639 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3640 sc->bge_flags |= BGEF_TAGGED_STATUS; 3641 3642 /* 3643 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3644 * lock in bge_reset(). 3645 */ 3646 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3647 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3648 delay(1000); 3649 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3650 3651 bge_stop_fw(sc); 3652 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3653 if (bge_reset(sc)) 3654 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3655 3656 /* 3657 * Read the hardware config word in the first 32k of NIC internal 3658 * memory, or fall back to the config word in the EEPROM. 3659 * Note: on some BCM5700 cards, this value appears to be unset. 3660 */ 3661 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3662 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3663 BGE_SRAM_DATA_SIG_MAGIC) { 3664 uint32_t tmp; 3665 3666 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3667 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3668 BGE_SRAM_DATA_VER_SHIFT; 3669 if ((0 < tmp) && (tmp < 0x100)) 3670 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3671 if (sc->bge_flags & BGEF_PCIE) 3672 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3673 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3674 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3675 if (BGE_IS_5717_PLUS(sc)) 3676 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3677 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3678 bge_read_eeprom(sc, (void *)&hwcfg, 3679 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3680 hwcfg = be32toh(hwcfg); 3681 } 3682 aprint_normal_dev(sc->bge_dev, 3683 "HW config %08x, %08x, %08x, %08x %08x\n", 3684 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3685 3686 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3687 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3688 3689 if (bge_chipinit(sc)) { 3690 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3691 bge_release_resources(sc); 3692 return; 3693 } 3694 3695 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3696 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3697 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3698 DELAY(100); 3699 } 3700 3701 /* Set MI_MODE */ 3702 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3703 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3704 mimode |= BGE_MIMODE_500KHZ_CONST; 3705 else 3706 mimode |= BGE_MIMODE_BASE; 3707 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3708 DELAY(80); 3709 3710 /* 3711 * Get station address from the EEPROM. 3712 */ 3713 if (bge_get_eaddr(sc, eaddr)) { 3714 aprint_error_dev(sc->bge_dev, 3715 "failed to read station address\n"); 3716 bge_release_resources(sc); 3717 return; 3718 } 3719 3720 br = bge_lookup_rev(sc->bge_chipid); 3721 3722 if (br == NULL) { 3723 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3724 sc->bge_chipid); 3725 } else { 3726 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3727 br->br_name, sc->bge_chipid); 3728 } 3729 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3730 3731 /* Allocate the general information block and ring buffers. */ 3732 if (pci_dma64_available(pa)) { 3733 sc->bge_dmatag = pa->pa_dmat64; 3734 sc->bge_dmatag32 = pa->pa_dmat; 3735 sc->bge_dma64 = true; 3736 } else { 3737 sc->bge_dmatag = pa->pa_dmat; 3738 sc->bge_dmatag32 = pa->pa_dmat; 3739 sc->bge_dma64 = false; 3740 } 3741 3742 /* 40bit DMA workaround */ 3743 if (sizeof(bus_addr_t) > 4) { 3744 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3745 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3746 3747 if (bus_dmatag_subregion(olddmatag, 0, 3748 (bus_addr_t)__MASK(40), 3749 &(sc->bge_dmatag), BUS_DMA_NOWAIT) != 0) { 3750 aprint_error_dev(self, 3751 "WARNING: failed to restrict dma range," 3752 " falling back to parent bus dma range\n"); 3753 sc->bge_dmatag = olddmatag; 3754 } 3755 } 3756 } 3757 SLIST_INIT(&sc->txdma_list); 3758 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3759 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3760 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3761 &sc->bge_ring_rseg, BUS_DMA_NOWAIT)) { 3762 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3763 return; 3764 } 3765 DPRINTFN(5, ("bus_dmamem_map\n")); 3766 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3767 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3768 BUS_DMA_NOWAIT)) { 3769 aprint_error_dev(sc->bge_dev, 3770 "can't map DMA buffers (%zu bytes)\n", 3771 sizeof(struct bge_ring_data)); 3772 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3773 sc->bge_ring_rseg); 3774 return; 3775 } 3776 DPRINTFN(5, ("bus_dmamem_create\n")); 3777 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3778 sizeof(struct bge_ring_data), 0, 3779 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 3780 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3781 bus_dmamem_unmap(sc->bge_dmatag, kva, 3782 sizeof(struct bge_ring_data)); 3783 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3784 sc->bge_ring_rseg); 3785 return; 3786 } 3787 DPRINTFN(5, ("bus_dmamem_load\n")); 3788 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3789 sizeof(struct bge_ring_data), NULL, 3790 BUS_DMA_NOWAIT)) { 3791 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3792 bus_dmamem_unmap(sc->bge_dmatag, kva, 3793 sizeof(struct bge_ring_data)); 3794 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3795 sc->bge_ring_rseg); 3796 return; 3797 } 3798 3799 DPRINTFN(5, ("bzero\n")); 3800 sc->bge_rdata = (struct bge_ring_data *)kva; 3801 3802 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3803 3804 /* Try to allocate memory for jumbo buffers. */ 3805 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3806 if (bge_alloc_jumbo_mem(sc)) { 3807 aprint_error_dev(sc->bge_dev, 3808 "jumbo buffer allocation failed\n"); 3809 } else 3810 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3811 } 3812 3813 /* Set default tuneable values. */ 3814 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3815 sc->bge_rx_coal_ticks = 150; 3816 sc->bge_rx_max_coal_bds = 64; 3817 sc->bge_tx_coal_ticks = 300; 3818 sc->bge_tx_max_coal_bds = 400; 3819 if (BGE_IS_5705_PLUS(sc)) { 3820 sc->bge_tx_coal_ticks = (12 * 5); 3821 sc->bge_tx_max_coal_bds = (12 * 5); 3822 aprint_verbose_dev(sc->bge_dev, 3823 "setting short Tx thresholds\n"); 3824 } 3825 3826 if (BGE_IS_5717_PLUS(sc)) 3827 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3828 else if (BGE_IS_5705_PLUS(sc)) 3829 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3830 else 3831 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3832 3833 /* Set up ifnet structure */ 3834 ifp = &sc->ethercom.ec_if; 3835 ifp->if_softc = sc; 3836 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3837 ifp->if_ioctl = bge_ioctl; 3838 ifp->if_stop = bge_stop; 3839 ifp->if_start = bge_start; 3840 ifp->if_init = bge_init; 3841 ifp->if_watchdog = bge_watchdog; 3842 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3843 IFQ_SET_READY(&ifp->if_snd); 3844 DPRINTFN(5, ("strcpy if_xname\n")); 3845 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3846 3847 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3848 sc->ethercom.ec_if.if_capabilities |= 3849 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3850 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3851 sc->ethercom.ec_if.if_capabilities |= 3852 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3853 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3854 #endif 3855 sc->ethercom.ec_capabilities |= 3856 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3857 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3858 3859 if (sc->bge_flags & BGEF_TSO) 3860 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3861 3862 /* 3863 * Do MII setup. 3864 */ 3865 DPRINTFN(5, ("mii setup\n")); 3866 mii->mii_ifp = ifp; 3867 mii->mii_readreg = bge_miibus_readreg; 3868 mii->mii_writereg = bge_miibus_writereg; 3869 mii->mii_statchg = bge_miibus_statchg; 3870 3871 /* 3872 * Figure out what sort of media we have by checking the hardware 3873 * config word. Note: on some BCM5700 cards, this value appears to be 3874 * unset. If that's the case, we have to rely on identifying the NIC 3875 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3876 * The SysKonnect SK-9D41 is a 1000baseSX card. 3877 */ 3878 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3879 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3880 if (BGE_IS_5705_PLUS(sc)) { 3881 sc->bge_flags |= BGEF_FIBER_MII; 3882 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3883 } else 3884 sc->bge_flags |= BGEF_FIBER_TBI; 3885 } 3886 3887 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3888 if (BGE_IS_JUMBO_CAPABLE(sc)) 3889 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3890 3891 /* set phyflags and chipid before mii_attach() */ 3892 dict = device_properties(self); 3893 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3894 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3895 3896 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3897 macmode &= ~BGE_MACMODE_PORTMODE; 3898 /* Initialize ifmedia structures. */ 3899 if (sc->bge_flags & BGEF_FIBER_TBI) { 3900 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3901 macmode | BGE_PORTMODE_TBI); 3902 DELAY(40); 3903 3904 sc->ethercom.ec_ifmedia = &sc->bge_ifmedia; 3905 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3906 bge_ifmedia_sts); 3907 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3908 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3909 0, NULL); 3910 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3911 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3912 /* Pretend the user requested this setting */ 3913 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3914 } else { 3915 uint16_t phyreg; 3916 int rv; 3917 /* 3918 * Do transceiver setup and tell the firmware the 3919 * driver is down so we can try to get access the 3920 * probe if ASF is running. Retry a couple of times 3921 * if we get a conflict with the ASF firmware accessing 3922 * the PHY. 3923 */ 3924 if (sc->bge_flags & BGEF_FIBER_MII) 3925 macmode |= BGE_PORTMODE_GMII; 3926 else 3927 macmode |= BGE_PORTMODE_MII; 3928 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3929 DELAY(40); 3930 3931 /* 3932 * Do transceiver setup and tell the firmware the 3933 * driver is down so we can try to get access the 3934 * probe if ASF is running. Retry a couple of times 3935 * if we get a conflict with the ASF firmware accessing 3936 * the PHY. 3937 */ 3938 trys = 0; 3939 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3940 sc->ethercom.ec_mii = mii; 3941 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3942 bge_ifmedia_sts); 3943 mii_flags = MIIF_DOPAUSE; 3944 if (sc->bge_flags & BGEF_FIBER_MII) 3945 mii_flags |= MIIF_HAVEFIBER; 3946 again: 3947 bge_asf_driver_up(sc); 3948 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 3949 MII_BMCR, &phyreg); 3950 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 3951 int i; 3952 3953 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 3954 MII_BMCR, BMCR_RESET); 3955 /* Wait up to 500ms for it to complete. */ 3956 for (i = 0; i < 500; i++) { 3957 bge_miibus_readreg(sc->bge_dev, 3958 sc->bge_phy_addr, MII_BMCR, &phyreg); 3959 if ((phyreg & BMCR_RESET) == 0) 3960 break; 3961 DELAY(1000); 3962 } 3963 } 3964 3965 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 3966 MII_OFFSET_ANY, mii_flags); 3967 3968 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 3969 goto again; 3970 3971 if (LIST_EMPTY(&mii->mii_phys)) { 3972 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3973 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 3974 0, NULL); 3975 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 3976 } else 3977 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 3978 3979 /* 3980 * Now tell the firmware we are going up after probing the PHY 3981 */ 3982 if (sc->bge_asf_mode & ASF_STACKUP) 3983 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3984 } 3985 3986 /* 3987 * Call MI attach routine. 3988 */ 3989 DPRINTFN(5, ("if_attach\n")); 3990 if_attach(ifp); 3991 if_deferred_start_init(ifp, NULL); 3992 DPRINTFN(5, ("ether_ifattach\n")); 3993 ether_ifattach(ifp, eaddr); 3994 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3995 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3996 RND_TYPE_NET, RND_FLAG_DEFAULT); 3997 #ifdef BGE_EVENT_COUNTERS 3998 /* 3999 * Attach event counters. 4000 */ 4001 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4002 NULL, device_xname(sc->bge_dev), "intr"); 4003 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4004 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4005 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4006 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4007 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4008 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4009 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4010 NULL, device_xname(sc->bge_dev), "tx_xon"); 4011 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4012 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4013 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4014 NULL, device_xname(sc->bge_dev), "rx_xon"); 4015 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4016 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4017 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4018 NULL, device_xname(sc->bge_dev), "xoffentered"); 4019 #endif /* BGE_EVENT_COUNTERS */ 4020 DPRINTFN(5, ("callout_init\n")); 4021 callout_init(&sc->bge_timeout, 0); 4022 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4023 4024 if (pmf_device_register(self, NULL, NULL)) 4025 pmf_class_network_register(self, ifp); 4026 else 4027 aprint_error_dev(self, "couldn't establish power handler\n"); 4028 4029 bge_sysctl_init(sc); 4030 4031 #ifdef BGE_DEBUG 4032 bge_debug_info(sc); 4033 #endif 4034 } 4035 4036 /* 4037 * Stop all chip I/O so that the kernel's probe routines don't 4038 * get confused by errant DMAs when rebooting. 4039 */ 4040 static int 4041 bge_detach(device_t self, int flags __unused) 4042 { 4043 struct bge_softc * const sc = device_private(self); 4044 struct ifnet * const ifp = &sc->ethercom.ec_if; 4045 int s; 4046 4047 s = splnet(); 4048 /* Stop the interface. Callouts are stopped in it. */ 4049 bge_stop(ifp, 1); 4050 splx(s); 4051 4052 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4053 4054 ether_ifdetach(ifp); 4055 if_detach(ifp); 4056 4057 /* Delete all remaining media. */ 4058 ifmedia_fini(&sc->bge_mii.mii_media); 4059 4060 bge_release_resources(sc); 4061 4062 return 0; 4063 } 4064 4065 static void 4066 bge_release_resources(struct bge_softc *sc) 4067 { 4068 4069 /* Detach sysctl */ 4070 if (sc->bge_log != NULL) 4071 sysctl_teardown(&sc->bge_log); 4072 4073 #ifdef BGE_EVENT_COUNTERS 4074 /* Detach event counters. */ 4075 evcnt_detach(&sc->bge_ev_intr); 4076 evcnt_detach(&sc->bge_ev_intr_spurious); 4077 evcnt_detach(&sc->bge_ev_intr_spurious2); 4078 evcnt_detach(&sc->bge_ev_tx_xoff); 4079 evcnt_detach(&sc->bge_ev_tx_xon); 4080 evcnt_detach(&sc->bge_ev_rx_xoff); 4081 evcnt_detach(&sc->bge_ev_rx_xon); 4082 evcnt_detach(&sc->bge_ev_rx_macctl); 4083 evcnt_detach(&sc->bge_ev_xoffentered); 4084 #endif /* BGE_EVENT_COUNTERS */ 4085 4086 /* Disestablish the interrupt handler */ 4087 if (sc->bge_intrhand != NULL) { 4088 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4089 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4090 sc->bge_intrhand = NULL; 4091 } 4092 4093 if (sc->bge_cdata.bge_jumbo_buf != NULL) 4094 bge_free_jumbo_mem(sc); 4095 4096 if (sc->bge_dmatag != NULL) { 4097 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4098 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4099 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4100 sizeof(struct bge_ring_data)); 4101 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4102 sc->bge_ring_rseg); 4103 } 4104 4105 /* Unmap the device registers */ 4106 if (sc->bge_bsize != 0) { 4107 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4108 sc->bge_bsize = 0; 4109 } 4110 4111 /* Unmap the APE registers */ 4112 if (sc->bge_apesize != 0) { 4113 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4114 sc->bge_apesize); 4115 sc->bge_apesize = 0; 4116 } 4117 } 4118 4119 static int 4120 bge_reset(struct bge_softc *sc) 4121 { 4122 uint32_t cachesize, command; 4123 uint32_t reset, mac_mode, mac_mode_mask; 4124 pcireg_t devctl, reg; 4125 int i, val; 4126 void (*write_op)(struct bge_softc *, int, int); 4127 4128 /* Make mask for BGE_MAC_MODE register. */ 4129 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4130 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4131 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4132 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4133 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4134 4135 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4136 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4137 if (sc->bge_flags & BGEF_PCIE) 4138 write_op = bge_writemem_direct; 4139 else 4140 write_op = bge_writemem_ind; 4141 } else 4142 write_op = bge_writereg_ind; 4143 4144 /* 57XX step 4 */ 4145 /* Acquire the NVM lock */ 4146 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4147 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4148 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4149 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4150 for (i = 0; i < 8000; i++) { 4151 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4152 BGE_NVRAMSWARB_GNT1) 4153 break; 4154 DELAY(20); 4155 } 4156 if (i == 8000) { 4157 printf("%s: NVRAM lock timedout!\n", 4158 device_xname(sc->bge_dev)); 4159 } 4160 } 4161 4162 /* Take APE lock when performing reset. */ 4163 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4164 4165 /* 57XX step 3 */ 4166 /* Save some important PCI state. */ 4167 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4168 /* 5718 reset step 3 */ 4169 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4170 4171 /* 5718 reset step 5, 57XX step 5b-5d */ 4172 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4173 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4174 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4175 4176 /* XXX ???: Disable fastboot on controllers that support it. */ 4177 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4178 BGE_IS_5755_PLUS(sc)) 4179 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4180 4181 /* 5718 reset step 2, 57XX step 6 */ 4182 /* 4183 * Write the magic number to SRAM at offset 0xB50. 4184 * When firmware finishes its initialization it will 4185 * write ~BGE_MAGIC_NUMBER to the same location. 4186 */ 4187 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4188 4189 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4190 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4191 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4192 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4193 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4194 } 4195 4196 /* 5718 reset step 6, 57XX step 7 */ 4197 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4198 /* 4199 * XXX: from FreeBSD/Linux; no documentation 4200 */ 4201 if (sc->bge_flags & BGEF_PCIE) { 4202 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4203 !BGE_IS_57765_PLUS(sc) && 4204 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4205 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4206 /* PCI Express 1.0 system */ 4207 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4208 BGE_PHY_PCIE_SCRAM_MODE); 4209 } 4210 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4211 /* 4212 * Prevent PCI Express link training 4213 * during global reset. 4214 */ 4215 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4216 reset |= (1 << 29); 4217 } 4218 } 4219 4220 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4221 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4222 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4223 i | BGE_VCPU_STATUS_DRV_RESET); 4224 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4225 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4226 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4227 } 4228 4229 /* 4230 * Set GPHY Power Down Override to leave GPHY 4231 * powered up in D0 uninitialized. 4232 */ 4233 if (BGE_IS_5705_PLUS(sc) && 4234 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4235 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4236 4237 /* Issue global reset */ 4238 write_op(sc, BGE_MISC_CFG, reset); 4239 4240 /* 5718 reset step 7, 57XX step 8 */ 4241 if (sc->bge_flags & BGEF_PCIE) 4242 delay(100*1000); /* too big */ 4243 else 4244 delay(1000); 4245 4246 if (sc->bge_flags & BGEF_PCIE) { 4247 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4248 DELAY(500000); 4249 /* XXX: Magic Numbers */ 4250 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4251 BGE_PCI_UNKNOWN0); 4252 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4253 BGE_PCI_UNKNOWN0, 4254 reg | (1 << 15)); 4255 } 4256 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4257 sc->bge_pciecap + PCIE_DCSR); 4258 /* Clear enable no snoop and disable relaxed ordering. */ 4259 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4260 PCIE_DCSR_ENA_NO_SNOOP); 4261 4262 /* Set PCIE max payload size to 128 for older PCIe devices */ 4263 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4264 devctl &= ~(0x00e0); 4265 /* Clear device status register. Write 1b to clear */ 4266 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4267 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4268 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4269 sc->bge_pciecap + PCIE_DCSR, devctl); 4270 bge_set_max_readrq(sc); 4271 } 4272 4273 /* From Linux: dummy read to flush PCI posted writes */ 4274 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4275 4276 /* 4277 * Reset some of the PCI state that got zapped by reset 4278 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4279 * set, too. 4280 */ 4281 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4282 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4283 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4284 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4285 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4286 (sc->bge_flags & BGEF_PCIX) != 0) 4287 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4288 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4289 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4290 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4291 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4292 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4293 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4294 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4295 4296 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4297 if (sc->bge_flags & BGEF_PCIX) { 4298 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4299 + PCIX_CMD); 4300 /* Set max memory read byte count to 2K */ 4301 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4302 reg &= ~PCIX_CMD_BYTECNT_MASK; 4303 reg |= PCIX_CMD_BCNT_2048; 4304 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4305 /* 4306 * For 5704, set max outstanding split transaction 4307 * field to 0 (0 means it supports 1 request) 4308 */ 4309 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4310 | PCIX_CMD_BYTECNT_MASK); 4311 reg |= PCIX_CMD_BCNT_2048; 4312 } 4313 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4314 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4315 } 4316 4317 /* 5718 reset step 10, 57XX step 12 */ 4318 /* Enable memory arbiter. */ 4319 if (BGE_IS_5714_FAMILY(sc)) { 4320 val = CSR_READ_4(sc, BGE_MARB_MODE); 4321 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4322 } else 4323 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4324 4325 /* XXX 5721, 5751 and 5752 */ 4326 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4327 /* Step 19: */ 4328 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4329 /* Step 20: */ 4330 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4331 } 4332 4333 /* 5718 reset step 12, 57XX step 15 and 16 */ 4334 /* Fix up byte swapping */ 4335 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4336 4337 /* 5718 reset step 13, 57XX step 17 */ 4338 /* Poll until the firmware initialization is complete */ 4339 bge_poll_fw(sc); 4340 4341 /* 57XX step 21 */ 4342 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4343 pcireg_t msidata; 4344 4345 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4346 BGE_PCI_MSI_DATA); 4347 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4348 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4349 msidata); 4350 } 4351 4352 /* 57XX step 18 */ 4353 /* Write mac mode. */ 4354 val = CSR_READ_4(sc, BGE_MAC_MODE); 4355 /* Restore mac_mode_mask's bits using mac_mode */ 4356 val = (val & ~mac_mode_mask) | mac_mode; 4357 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4358 DELAY(40); 4359 4360 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4361 4362 /* 4363 * The 5704 in TBI mode apparently needs some special 4364 * adjustment to insure the SERDES drive level is set 4365 * to 1.2V. 4366 */ 4367 if (sc->bge_flags & BGEF_FIBER_TBI && 4368 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4369 uint32_t serdescfg; 4370 4371 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4372 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4373 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4374 } 4375 4376 if (sc->bge_flags & BGEF_PCIE && 4377 !BGE_IS_57765_PLUS(sc) && 4378 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4379 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4380 uint32_t v; 4381 4382 /* Enable PCI Express bug fix */ 4383 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4384 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4385 v | BGE_TLP_DATA_FIFO_PROTECT); 4386 } 4387 4388 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4389 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4390 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4391 4392 return 0; 4393 } 4394 4395 /* 4396 * Frame reception handling. This is called if there's a frame 4397 * on the receive return list. 4398 * 4399 * Note: we have to be able to handle two possibilities here: 4400 * 1) the frame is from the jumbo receive ring 4401 * 2) the frame is from the standard receive ring 4402 */ 4403 4404 static void 4405 bge_rxeof(struct bge_softc *sc) 4406 { 4407 struct ifnet * const ifp = &sc->ethercom.ec_if; 4408 uint16_t rx_prod, rx_cons; 4409 int stdcnt = 0, jumbocnt = 0; 4410 bus_dmamap_t dmamap; 4411 bus_addr_t offset, toff; 4412 bus_size_t tlen; 4413 int tosync; 4414 4415 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4416 offsetof(struct bge_ring_data, bge_status_block), 4417 sizeof(struct bge_status_block), 4418 BUS_DMASYNC_POSTREAD); 4419 4420 rx_cons = sc->bge_rx_saved_considx; 4421 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4422 4423 /* Nothing to do */ 4424 if (rx_cons == rx_prod) 4425 return; 4426 4427 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4428 tosync = rx_prod - rx_cons; 4429 4430 if (tosync != 0) 4431 rnd_add_uint32(&sc->rnd_source, tosync); 4432 4433 toff = offset + (rx_cons * sizeof(struct bge_rx_bd)); 4434 4435 if (tosync < 0) { 4436 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4437 sizeof(struct bge_rx_bd); 4438 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4439 toff, tlen, BUS_DMASYNC_POSTREAD); 4440 tosync = -tosync; 4441 } 4442 4443 if (tosync != 0) { 4444 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4445 offset, tosync * sizeof(struct bge_rx_bd), 4446 BUS_DMASYNC_POSTREAD); 4447 } 4448 4449 while (rx_cons != rx_prod) { 4450 struct bge_rx_bd *cur_rx; 4451 uint32_t rxidx; 4452 struct mbuf *m = NULL; 4453 4454 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4455 4456 rxidx = cur_rx->bge_idx; 4457 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4458 4459 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4460 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4461 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4462 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4463 jumbocnt++; 4464 bus_dmamap_sync(sc->bge_dmatag, 4465 sc->bge_cdata.bge_rx_jumbo_map, 4466 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4467 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4468 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4469 if_statinc(ifp, if_ierrors); 4470 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4471 continue; 4472 } 4473 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4474 NULL) == ENOBUFS) { 4475 if_statinc(ifp, if_ierrors); 4476 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4477 continue; 4478 } 4479 } else { 4480 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4481 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4482 4483 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4484 stdcnt++; 4485 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4486 sc->bge_cdata.bge_rx_std_map[rxidx] = NULL; 4487 if (dmamap == NULL) { 4488 if_statinc(ifp, if_ierrors); 4489 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4490 continue; 4491 } 4492 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4493 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4494 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4495 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4496 if_statinc(ifp, if_ierrors); 4497 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4498 continue; 4499 } 4500 if (bge_newbuf_std(sc, sc->bge_std, 4501 NULL, dmamap) == ENOBUFS) { 4502 if_statinc(ifp, if_ierrors); 4503 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 4504 continue; 4505 } 4506 } 4507 4508 #ifndef __NO_STRICT_ALIGNMENT 4509 /* 4510 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4511 * the Rx buffer has the layer-2 header unaligned. 4512 * If our CPU requires alignment, re-align by copying. 4513 */ 4514 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4515 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4516 cur_rx->bge_len); 4517 m->m_data += ETHER_ALIGN; 4518 } 4519 #endif 4520 4521 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4522 m_set_rcvif(m, ifp); 4523 4524 bge_rxcsum(sc, cur_rx, m); 4525 4526 /* 4527 * If we received a packet with a vlan tag, pass it 4528 * to vlan_input() instead of ether_input(). 4529 */ 4530 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4531 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4532 4533 if_percpuq_enqueue(ifp->if_percpuq, m); 4534 } 4535 4536 sc->bge_rx_saved_considx = rx_cons; 4537 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4538 if (stdcnt) 4539 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 4540 if (jumbocnt) 4541 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4542 } 4543 4544 static void 4545 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4546 { 4547 4548 if (BGE_IS_57765_PLUS(sc)) { 4549 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4550 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4551 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4552 if ((cur_rx->bge_error_flag & 4553 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4554 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4555 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4556 m->m_pkthdr.csum_data = 4557 cur_rx->bge_tcp_udp_csum; 4558 m->m_pkthdr.csum_flags |= 4559 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4560 } 4561 } 4562 } else { 4563 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4564 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4565 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4566 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4567 /* 4568 * Rx transport checksum-offload may also 4569 * have bugs with packets which, when transmitted, 4570 * were `runts' requiring padding. 4571 */ 4572 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4573 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4574 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4575 m->m_pkthdr.csum_data = 4576 cur_rx->bge_tcp_udp_csum; 4577 m->m_pkthdr.csum_flags |= 4578 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4579 } 4580 } 4581 } 4582 4583 static void 4584 bge_txeof(struct bge_softc *sc) 4585 { 4586 struct ifnet * const ifp = &sc->ethercom.ec_if; 4587 struct bge_tx_bd *cur_tx = NULL; 4588 struct txdmamap_pool_entry *dma; 4589 bus_addr_t offset, toff; 4590 bus_size_t tlen; 4591 int tosync; 4592 struct mbuf *m; 4593 4594 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4595 offsetof(struct bge_ring_data, bge_status_block), 4596 sizeof(struct bge_status_block), 4597 BUS_DMASYNC_POSTREAD); 4598 4599 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4600 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 4601 sc->bge_tx_saved_considx; 4602 4603 if (tosync != 0) 4604 rnd_add_uint32(&sc->rnd_source, tosync); 4605 4606 toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd)); 4607 4608 if (tosync < 0) { 4609 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4610 sizeof(struct bge_tx_bd); 4611 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4612 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4613 tosync = -tosync; 4614 } 4615 4616 if (tosync != 0) { 4617 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4618 offset, tosync * sizeof(struct bge_tx_bd), 4619 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4620 } 4621 4622 /* 4623 * Go through our tx ring and free mbufs for those 4624 * frames that have been sent. 4625 */ 4626 while (sc->bge_tx_saved_considx != 4627 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 4628 uint32_t idx = sc->bge_tx_saved_considx; 4629 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4630 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4631 if_statinc(ifp, if_opackets); 4632 m = sc->bge_cdata.bge_tx_chain[idx]; 4633 if (m != NULL) { 4634 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4635 dma = sc->txdma[idx]; 4636 if (dma->is_dma32) { 4637 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4638 0, dma->dmamap32->dm_mapsize, 4639 BUS_DMASYNC_POSTWRITE); 4640 bus_dmamap_unload( 4641 sc->bge_dmatag32, dma->dmamap32); 4642 } else { 4643 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4644 0, dma->dmamap->dm_mapsize, 4645 BUS_DMASYNC_POSTWRITE); 4646 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4647 } 4648 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4649 sc->txdma[idx] = NULL; 4650 4651 m_freem(m); 4652 } 4653 sc->bge_txcnt--; 4654 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4655 ifp->if_timer = 0; 4656 } 4657 4658 if (cur_tx != NULL) 4659 ifp->if_flags &= ~IFF_OACTIVE; 4660 } 4661 4662 static int 4663 bge_intr(void *xsc) 4664 { 4665 struct bge_softc * const sc = xsc; 4666 struct ifnet * const ifp = &sc->ethercom.ec_if; 4667 uint32_t pcistate, statusword, statustag; 4668 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4669 4670 4671 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4672 if (BGE_IS_5717_PLUS(sc)) 4673 intrmask = 0; 4674 4675 /* 4676 * It is possible for the interrupt to arrive before 4677 * the status block is updated prior to the interrupt. 4678 * Reading the PCI State register will confirm whether the 4679 * interrupt is ours and will flush the status block. 4680 */ 4681 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4682 4683 /* read status word from status block */ 4684 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4685 offsetof(struct bge_ring_data, bge_status_block), 4686 sizeof(struct bge_status_block), 4687 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4688 statusword = sc->bge_rdata->bge_status_block.bge_status; 4689 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4690 4691 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4692 if (sc->bge_lasttag == statustag && 4693 (~pcistate & intrmask)) { 4694 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4695 return 0; 4696 } 4697 sc->bge_lasttag = statustag; 4698 } else { 4699 if (!(statusword & BGE_STATFLAG_UPDATED) && 4700 !(~pcistate & intrmask)) { 4701 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4702 return 0; 4703 } 4704 statustag = 0; 4705 } 4706 /* Ack interrupt and stop others from occurring. */ 4707 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4708 BGE_EVCNT_INCR(sc->bge_ev_intr); 4709 4710 /* clear status word */ 4711 sc->bge_rdata->bge_status_block.bge_status = 0; 4712 4713 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4714 offsetof(struct bge_ring_data, bge_status_block), 4715 sizeof(struct bge_status_block), 4716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4717 4718 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4719 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4720 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4721 bge_link_upd(sc); 4722 4723 if (ifp->if_flags & IFF_RUNNING) { 4724 /* Check RX return ring producer/consumer */ 4725 bge_rxeof(sc); 4726 4727 /* Check TX ring producer/consumer */ 4728 bge_txeof(sc); 4729 } 4730 4731 if (sc->bge_pending_rxintr_change) { 4732 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4733 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4734 4735 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4736 DELAY(10); 4737 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4738 4739 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4740 DELAY(10); 4741 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4742 4743 sc->bge_pending_rxintr_change = 0; 4744 } 4745 bge_handle_events(sc); 4746 4747 /* Re-enable interrupts. */ 4748 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4749 4750 if (ifp->if_flags & IFF_RUNNING) 4751 if_schedule_deferred_start(ifp); 4752 4753 return 1; 4754 } 4755 4756 static void 4757 bge_asf_driver_up(struct bge_softc *sc) 4758 { 4759 if (sc->bge_asf_mode & ASF_STACKUP) { 4760 /* Send ASF heartbeat aprox. every 2s */ 4761 if (sc->bge_asf_count) 4762 sc->bge_asf_count --; 4763 else { 4764 sc->bge_asf_count = 2; 4765 4766 bge_wait_for_event_ack(sc); 4767 4768 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4769 BGE_FW_CMD_DRV_ALIVE3); 4770 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4771 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4772 BGE_FW_HB_TIMEOUT_SEC); 4773 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4774 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4775 BGE_RX_CPU_DRV_EVENT); 4776 } 4777 } 4778 } 4779 4780 static void 4781 bge_tick(void *xsc) 4782 { 4783 struct bge_softc * const sc = xsc; 4784 struct mii_data * const mii = &sc->bge_mii; 4785 int s; 4786 4787 s = splnet(); 4788 4789 if (BGE_IS_5705_PLUS(sc)) 4790 bge_stats_update_regs(sc); 4791 else 4792 bge_stats_update(sc); 4793 4794 if (sc->bge_flags & BGEF_FIBER_TBI) { 4795 /* 4796 * Since in TBI mode auto-polling can't be used we should poll 4797 * link status manually. Here we register pending link event 4798 * and trigger interrupt. 4799 */ 4800 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4801 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4802 } else { 4803 /* 4804 * Do not touch PHY if we have link up. This could break 4805 * IPMI/ASF mode or produce extra input errors. 4806 * (extra input errors was reported for bcm5701 & bcm5704). 4807 */ 4808 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4809 mii_tick(mii); 4810 } 4811 4812 bge_asf_driver_up(sc); 4813 4814 if (!sc->bge_detaching) 4815 callout_schedule(&sc->bge_timeout, hz); 4816 4817 splx(s); 4818 } 4819 4820 static void 4821 bge_stats_update_regs(struct bge_softc *sc) 4822 { 4823 struct ifnet *const ifp = &sc->ethercom.ec_if; 4824 4825 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4826 4827 if_statadd_ref(nsr, if_collisions, 4828 CSR_READ_4(sc, BGE_MAC_STATS + 4829 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4830 4831 /* 4832 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4833 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4834 * (silicon bug). There's no reliable workaround so just 4835 * ignore the counter 4836 */ 4837 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4838 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4839 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4840 if_statadd_ref(nsr, if_ierrors, 4841 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4842 } 4843 if_statadd_ref(nsr, if_ierrors, 4844 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4845 if_statadd_ref(nsr, if_ierrors, 4846 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4847 4848 IF_STAT_PUTREF(ifp); 4849 4850 if (sc->bge_flags & BGEF_RDMA_BUG) { 4851 uint32_t val, ucast, mcast, bcast; 4852 4853 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4854 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4855 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4856 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4857 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4858 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4859 4860 /* 4861 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4862 * frames, it's safe to disable workaround for DMA engine's 4863 * miscalculation of TXMBUF space. 4864 */ 4865 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4866 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4867 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4868 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4869 else 4870 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4871 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4872 sc->bge_flags &= ~BGEF_RDMA_BUG; 4873 } 4874 } 4875 } 4876 4877 static void 4878 bge_stats_update(struct bge_softc *sc) 4879 { 4880 struct ifnet * const ifp = &sc->ethercom.ec_if; 4881 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4882 4883 #define READ_STAT(sc, stats, stat) \ 4884 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4885 4886 uint64_t collisions = 4887 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4888 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4889 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4890 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4891 4892 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4893 sc->bge_if_collisions = collisions; 4894 4895 4896 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4897 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4898 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4899 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4900 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4901 READ_STAT(sc, stats, 4902 xoffPauseFramesReceived.bge_addr_lo)); 4903 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4904 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4905 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4906 READ_STAT(sc, stats, 4907 macControlFramesReceived.bge_addr_lo)); 4908 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4909 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4910 4911 #undef READ_STAT 4912 4913 #ifdef notdef 4914 ifp->if_collisions += 4915 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 4916 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 4917 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 4918 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 4919 ifp->if_collisions; 4920 #endif 4921 } 4922 4923 /* 4924 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4925 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4926 * but when such padded frames employ the bge IP/TCP checksum offload, 4927 * the hardware checksum assist gives incorrect results (possibly 4928 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4929 * If we pad such runts with zeros, the onboard checksum comes out correct. 4930 */ 4931 static inline int 4932 bge_cksum_pad(struct mbuf *pkt) 4933 { 4934 struct mbuf *last = NULL; 4935 int padlen; 4936 4937 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4938 4939 /* if there's only the packet-header and we can pad there, use it. */ 4940 if (pkt->m_pkthdr.len == pkt->m_len && 4941 M_TRAILINGSPACE(pkt) >= padlen) { 4942 last = pkt; 4943 } else { 4944 /* 4945 * Walk packet chain to find last mbuf. We will either 4946 * pad there, or append a new mbuf and pad it 4947 * (thus perhaps avoiding the bcm5700 dma-min bug). 4948 */ 4949 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4950 continue; /* do nothing */ 4951 } 4952 4953 /* `last' now points to last in chain. */ 4954 if (M_TRAILINGSPACE(last) < padlen) { 4955 /* Allocate new empty mbuf, pad it. Compact later. */ 4956 struct mbuf *n; 4957 MGET(n, M_DONTWAIT, MT_DATA); 4958 if (n == NULL) 4959 return ENOBUFS; 4960 n->m_len = 0; 4961 last->m_next = n; 4962 last = n; 4963 } 4964 } 4965 4966 KDASSERT(!M_READONLY(last)); 4967 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4968 4969 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4970 memset(mtod(last, char *) + last->m_len, 0, padlen); 4971 last->m_len += padlen; 4972 pkt->m_pkthdr.len += padlen; 4973 return 0; 4974 } 4975 4976 /* 4977 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 4978 */ 4979 static inline int 4980 bge_compact_dma_runt(struct mbuf *pkt) 4981 { 4982 struct mbuf *m, *prev; 4983 int totlen; 4984 4985 prev = NULL; 4986 totlen = 0; 4987 4988 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 4989 int mlen = m->m_len; 4990 int shortfall = 8 - mlen ; 4991 4992 totlen += mlen; 4993 if (mlen == 0) 4994 continue; 4995 if (mlen >= 8) 4996 continue; 4997 4998 /* 4999 * If we get here, mbuf data is too small for DMA engine. 5000 * Try to fix by shuffling data to prev or next in chain. 5001 * If that fails, do a compacting deep-copy of the whole chain. 5002 */ 5003 5004 /* Internal frag. If fits in prev, copy it there. */ 5005 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5006 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5007 prev->m_len += mlen; 5008 m->m_len = 0; 5009 /* XXX stitch chain */ 5010 prev->m_next = m_free(m); 5011 m = prev; 5012 continue; 5013 } else if (m->m_next != NULL && 5014 M_TRAILINGSPACE(m) >= shortfall && 5015 m->m_next->m_len >= (8 + shortfall)) { 5016 /* m is writable and have enough data in next, pull up. */ 5017 5018 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5019 shortfall); 5020 m->m_len += shortfall; 5021 m->m_next->m_len -= shortfall; 5022 m->m_next->m_data += shortfall; 5023 } else if (m->m_next == NULL || 1) { 5024 /* 5025 * Got a runt at the very end of the packet. 5026 * borrow data from the tail of the preceding mbuf and 5027 * update its length in-place. (The original data is 5028 * still valid, so we can do this even if prev is not 5029 * writable.) 5030 */ 5031 5032 /* 5033 * If we'd make prev a runt, just move all of its data. 5034 */ 5035 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5036 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5037 5038 if ((prev->m_len - shortfall) < 8) 5039 shortfall = prev->m_len; 5040 5041 #ifdef notyet /* just do the safe slow thing for now */ 5042 if (!M_READONLY(m)) { 5043 if (M_LEADINGSPACE(m) < shorfall) { 5044 void *m_dat; 5045 m_dat = M_BUFADDR(m); 5046 memmove(m_dat, mtod(m, void*), 5047 m->m_len); 5048 m->m_data = m_dat; 5049 } 5050 } else 5051 #endif /* just do the safe slow thing */ 5052 { 5053 struct mbuf * n = NULL; 5054 int newprevlen = prev->m_len - shortfall; 5055 5056 MGET(n, M_NOWAIT, MT_DATA); 5057 if (n == NULL) 5058 return ENOBUFS; 5059 KASSERT(m->m_len + shortfall < MLEN 5060 /*, 5061 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5062 5063 /* first copy the data we're stealing from prev */ 5064 memcpy(n->m_data, prev->m_data + newprevlen, 5065 shortfall); 5066 5067 /* update prev->m_len accordingly */ 5068 prev->m_len -= shortfall; 5069 5070 /* copy data from runt m */ 5071 memcpy(n->m_data + shortfall, m->m_data, 5072 m->m_len); 5073 5074 /* n holds what we stole from prev, plus m */ 5075 n->m_len = shortfall + m->m_len; 5076 5077 /* stitch n into chain and free m */ 5078 n->m_next = m->m_next; 5079 prev->m_next = n; 5080 /* KASSERT(m->m_next == NULL); */ 5081 m->m_next = NULL; 5082 m_free(m); 5083 m = n; /* for continuing loop */ 5084 } 5085 } 5086 } 5087 return 0; 5088 } 5089 5090 /* 5091 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5092 * pointers to descriptors. 5093 */ 5094 static int 5095 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5096 { 5097 struct ifnet * const ifp = &sc->ethercom.ec_if; 5098 struct bge_tx_bd *f, *prev_f; 5099 uint32_t frag, cur; 5100 uint16_t csum_flags = 0; 5101 uint16_t txbd_tso_flags = 0; 5102 struct txdmamap_pool_entry *dma; 5103 bus_dmamap_t dmamap; 5104 bus_dma_tag_t dmatag; 5105 int i = 0; 5106 int use_tso, maxsegsize, error; 5107 bool have_vtag; 5108 uint16_t vtag; 5109 bool remap; 5110 5111 if (m_head->m_pkthdr.csum_flags) { 5112 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5113 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5114 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5115 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5116 } 5117 5118 /* 5119 * If we were asked to do an outboard checksum, and the NIC 5120 * has the bug where it sometimes adds in the Ethernet padding, 5121 * explicitly pad with zeros so the cksum will be correct either way. 5122 * (For now, do this for all chip versions, until newer 5123 * are confirmed to not require the workaround.) 5124 */ 5125 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5126 #ifdef notyet 5127 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5128 #endif 5129 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5130 goto check_dma_bug; 5131 5132 if (bge_cksum_pad(m_head) != 0) 5133 return ENOBUFS; 5134 5135 check_dma_bug: 5136 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5137 goto doit; 5138 5139 /* 5140 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5141 * less than eight bytes. If we encounter a teeny mbuf 5142 * at the end of a chain, we can pad. Otherwise, copy. 5143 */ 5144 if (bge_compact_dma_runt(m_head) != 0) 5145 return ENOBUFS; 5146 5147 doit: 5148 dma = SLIST_FIRST(&sc->txdma_list); 5149 if (dma == NULL) { 5150 ifp->if_flags |= IFF_OACTIVE; 5151 return ENOBUFS; 5152 } 5153 dmamap = dma->dmamap; 5154 dmatag = sc->bge_dmatag; 5155 dma->is_dma32 = false; 5156 5157 /* 5158 * Set up any necessary TSO state before we start packing... 5159 */ 5160 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5161 if (!use_tso) { 5162 maxsegsize = 0; 5163 } else { /* TSO setup */ 5164 unsigned mss; 5165 struct ether_header *eh; 5166 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5167 unsigned bge_hlen; 5168 struct mbuf * m0 = m_head; 5169 struct ip *ip; 5170 struct tcphdr *th; 5171 int iphl, hlen; 5172 5173 /* 5174 * XXX It would be nice if the mbuf pkthdr had offset 5175 * fields for the protocol headers. 5176 */ 5177 5178 eh = mtod(m0, struct ether_header *); 5179 switch (htons(eh->ether_type)) { 5180 case ETHERTYPE_IP: 5181 offset = ETHER_HDR_LEN; 5182 break; 5183 5184 case ETHERTYPE_VLAN: 5185 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5186 break; 5187 5188 default: 5189 /* 5190 * Don't support this protocol or encapsulation. 5191 */ 5192 return ENOBUFS; 5193 } 5194 5195 /* 5196 * TCP/IP headers are in the first mbuf; we can do 5197 * this the easy way. 5198 */ 5199 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5200 hlen = iphl + offset; 5201 if (__predict_false(m0->m_len < 5202 (hlen + sizeof(struct tcphdr)))) { 5203 5204 aprint_error_dev(sc->bge_dev, 5205 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5206 "not handled yet\n", 5207 m0->m_len, hlen+ sizeof(struct tcphdr)); 5208 #ifdef NOTYET 5209 /* 5210 * XXX jonathan (at) NetBSD.org: untested. 5211 * how to force this branch to be taken? 5212 */ 5213 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5214 5215 m_copydata(m0, offset, sizeof(ip), &ip); 5216 m_copydata(m0, hlen, sizeof(th), &th); 5217 5218 ip.ip_len = 0; 5219 5220 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5221 sizeof(ip.ip_len), &ip.ip_len); 5222 5223 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5224 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5225 5226 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5227 sizeof(th.th_sum), &th.th_sum); 5228 5229 hlen += th.th_off << 2; 5230 iptcp_opt_words = hlen; 5231 #else 5232 /* 5233 * if_wm "hard" case not yet supported, can we not 5234 * mandate it out of existence? 5235 */ 5236 (void) ip; (void)th; (void) ip_tcp_hlen; 5237 5238 return ENOBUFS; 5239 #endif 5240 } else { 5241 ip = (struct ip *) (mtod(m0, char *) + offset); 5242 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5243 ip_tcp_hlen = iphl + (th->th_off << 2); 5244 5245 /* Total IP/TCP options, in 32-bit words */ 5246 iptcp_opt_words = (ip_tcp_hlen 5247 - sizeof(struct tcphdr) 5248 - sizeof(struct ip)) >> 2; 5249 } 5250 if (BGE_IS_575X_PLUS(sc)) { 5251 th->th_sum = 0; 5252 csum_flags = 0; 5253 } else { 5254 /* 5255 * XXX jonathan (at) NetBSD.org: 5705 untested. 5256 * Requires TSO firmware patch for 5701/5703/5704. 5257 */ 5258 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5259 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5260 } 5261 5262 mss = m_head->m_pkthdr.segsz; 5263 txbd_tso_flags |= 5264 BGE_TXBDFLAG_CPU_PRE_DMA | 5265 BGE_TXBDFLAG_CPU_POST_DMA; 5266 5267 /* 5268 * Our NIC TSO-assist assumes TSO has standard, optionless 5269 * IPv4 and TCP headers, which total 40 bytes. By default, 5270 * the NIC copies 40 bytes of IP/TCP header from the 5271 * supplied header into the IP/TCP header portion of 5272 * each post-TSO-segment. If the supplied packet has IP or 5273 * TCP options, we need to tell the NIC to copy those extra 5274 * bytes into each post-TSO header, in addition to the normal 5275 * 40-byte IP/TCP header (and to leave space accordingly). 5276 * Unfortunately, the driver encoding of option length 5277 * varies across different ASIC families. 5278 */ 5279 tcp_seg_flags = 0; 5280 bge_hlen = ip_tcp_hlen >> 2; 5281 if (BGE_IS_5717_PLUS(sc)) { 5282 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5283 txbd_tso_flags |= 5284 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5285 } else if (BGE_IS_5705_PLUS(sc)) { 5286 tcp_seg_flags = bge_hlen << 11; 5287 } else { 5288 /* XXX iptcp_opt_words or bge_hlen ? */ 5289 txbd_tso_flags |= iptcp_opt_words << 12; 5290 } 5291 maxsegsize = mss | tcp_seg_flags; 5292 ip->ip_len = htons(mss + ip_tcp_hlen); 5293 ip->ip_sum = 0; 5294 5295 } /* TSO setup */ 5296 5297 have_vtag = vlan_has_tag(m_head); 5298 if (have_vtag) 5299 vtag = vlan_get_tag(m_head); 5300 5301 /* 5302 * Start packing the mbufs in this chain into 5303 * the fragment pointers. Stop when we run out 5304 * of fragments or hit the end of the mbuf chain. 5305 */ 5306 remap = true; 5307 load_again: 5308 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5309 if (__predict_false(error)) { 5310 if (error == EFBIG && remap) { 5311 struct mbuf *m; 5312 remap = false; 5313 m = m_defrag(m_head, M_NOWAIT); 5314 if (m != NULL) { 5315 KASSERT(m == m_head); 5316 goto load_again; 5317 } 5318 } 5319 return error; 5320 } 5321 /* 5322 * Sanity check: avoid coming within 16 descriptors 5323 * of the end of the ring. 5324 */ 5325 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5326 BGE_TSO_PRINTF(("%s: " 5327 " dmamap_load_mbuf too close to ring wrap\n", 5328 device_xname(sc->bge_dev))); 5329 goto fail_unload; 5330 } 5331 5332 /* Iterate over dmap-map fragments. */ 5333 f = prev_f = NULL; 5334 cur = frag = *txidx; 5335 5336 for (i = 0; i < dmamap->dm_nsegs; i++) { 5337 f = &sc->bge_rdata->bge_tx_ring[frag]; 5338 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5339 break; 5340 5341 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5342 f->bge_len = dmamap->dm_segs[i].ds_len; 5343 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5344 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5345 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5346 (prev_f != NULL && 5347 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5348 ) { 5349 /* 5350 * watchdog timeout issue was observed with TSO, 5351 * limiting DMA address space to 32bits seems to 5352 * address the issue. 5353 */ 5354 bus_dmamap_unload(dmatag, dmamap); 5355 dmatag = sc->bge_dmatag32; 5356 dmamap = dma->dmamap32; 5357 dma->is_dma32 = true; 5358 remap = true; 5359 goto load_again; 5360 } 5361 5362 /* 5363 * For 5751 and follow-ons, for TSO we must turn 5364 * off checksum-assist flag in the tx-descr, and 5365 * supply the ASIC-revision-specific encoding 5366 * of TSO flags and segsize. 5367 */ 5368 if (use_tso) { 5369 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5370 f->bge_rsvd = maxsegsize; 5371 f->bge_flags = csum_flags | txbd_tso_flags; 5372 } else { 5373 f->bge_rsvd = 0; 5374 f->bge_flags = 5375 (csum_flags | txbd_tso_flags) & 0x0fff; 5376 } 5377 } else { 5378 f->bge_rsvd = 0; 5379 f->bge_flags = csum_flags; 5380 } 5381 5382 if (have_vtag) { 5383 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5384 f->bge_vlan_tag = vtag; 5385 } else { 5386 f->bge_vlan_tag = 0; 5387 } 5388 prev_f = f; 5389 cur = frag; 5390 BGE_INC(frag, BGE_TX_RING_CNT); 5391 } 5392 5393 if (i < dmamap->dm_nsegs) { 5394 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5395 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5396 goto fail_unload; 5397 } 5398 5399 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5400 BUS_DMASYNC_PREWRITE); 5401 5402 if (frag == sc->bge_tx_saved_considx) { 5403 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5404 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5405 5406 goto fail_unload; 5407 } 5408 5409 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5410 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5411 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5412 sc->txdma[cur] = dma; 5413 sc->bge_txcnt += dmamap->dm_nsegs; 5414 5415 *txidx = frag; 5416 5417 return 0; 5418 5419 fail_unload: 5420 bus_dmamap_unload(dmatag, dmamap); 5421 ifp->if_flags |= IFF_OACTIVE; 5422 5423 return ENOBUFS; 5424 } 5425 5426 /* 5427 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5428 * to the mbuf data regions directly in the transmit descriptors. 5429 */ 5430 static void 5431 bge_start(struct ifnet *ifp) 5432 { 5433 struct bge_softc * const sc = ifp->if_softc; 5434 struct mbuf *m_head = NULL; 5435 struct mbuf *m; 5436 uint32_t prodidx; 5437 int pkts = 0; 5438 int error; 5439 5440 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 5441 return; 5442 5443 prodidx = sc->bge_tx_prodidx; 5444 5445 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5446 IFQ_POLL(&ifp->if_snd, m_head); 5447 if (m_head == NULL) 5448 break; 5449 5450 #if 0 5451 /* 5452 * XXX 5453 * safety overkill. If this is a fragmented packet chain 5454 * with delayed TCP/UDP checksums, then only encapsulate 5455 * it if we have enough descriptors to handle the entire 5456 * chain at once. 5457 * (paranoia -- may not actually be needed) 5458 */ 5459 if (m_head->m_flags & M_FIRSTFRAG && 5460 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5461 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5462 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5463 ifp->if_flags |= IFF_OACTIVE; 5464 break; 5465 } 5466 } 5467 #endif 5468 5469 /* 5470 * Pack the data into the transmit ring. If we 5471 * don't have room, set the OACTIVE flag and wait 5472 * for the NIC to drain the ring. 5473 */ 5474 error = bge_encap(sc, m_head, &prodidx); 5475 if (__predict_false(error)) { 5476 if (ifp->if_flags & IFF_OACTIVE) { 5477 /* just wait for the transmit ring to drain */ 5478 break; 5479 } 5480 IFQ_DEQUEUE(&ifp->if_snd, m); 5481 KASSERT(m == m_head); 5482 m_freem(m_head); 5483 continue; 5484 } 5485 5486 /* now we are committed to transmit the packet */ 5487 IFQ_DEQUEUE(&ifp->if_snd, m); 5488 KASSERT(m == m_head); 5489 pkts++; 5490 5491 /* 5492 * If there's a BPF listener, bounce a copy of this frame 5493 * to him. 5494 */ 5495 bpf_mtap(ifp, m_head, BPF_D_OUT); 5496 } 5497 if (pkts == 0) 5498 return; 5499 5500 /* Transmit */ 5501 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5502 /* 5700 b2 errata */ 5503 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5504 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5505 5506 sc->bge_tx_prodidx = prodidx; 5507 5508 /* 5509 * Set a timeout in case the chip goes out to lunch. 5510 */ 5511 ifp->if_timer = 5; 5512 } 5513 5514 static int 5515 bge_init(struct ifnet *ifp) 5516 { 5517 struct bge_softc * const sc = ifp->if_softc; 5518 const uint16_t *m; 5519 uint32_t mode, reg; 5520 int s, error = 0; 5521 5522 s = splnet(); 5523 5524 KASSERT(ifp == &sc->ethercom.ec_if); 5525 5526 /* Cancel pending I/O and flush buffers. */ 5527 bge_stop(ifp, 0); 5528 5529 bge_stop_fw(sc); 5530 bge_sig_pre_reset(sc, BGE_RESET_START); 5531 bge_reset(sc); 5532 bge_sig_legacy(sc, BGE_RESET_START); 5533 5534 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5535 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5536 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5537 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5538 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5539 5540 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5541 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5542 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5543 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5544 5545 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5546 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5547 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5548 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5549 5550 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5551 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5552 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5553 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5554 } 5555 5556 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5557 pcireg_t aercap; 5558 5559 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5560 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5561 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5562 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5563 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5564 5565 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5566 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5567 | BGE_PCIE_EIDLE_DELAY_13CLK; 5568 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5569 5570 /* Clear correctable error */ 5571 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5572 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5573 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5574 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5575 5576 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5577 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5578 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5579 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5580 } 5581 5582 bge_sig_post_reset(sc, BGE_RESET_START); 5583 5584 bge_chipinit(sc); 5585 5586 /* 5587 * Init the various state machines, ring 5588 * control blocks and firmware. 5589 */ 5590 error = bge_blockinit(sc); 5591 if (error != 0) { 5592 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5593 error); 5594 splx(s); 5595 return error; 5596 } 5597 5598 /* 5718 step 25, 57XX step 54 */ 5599 /* Specify MTU. */ 5600 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5601 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5602 5603 /* 5718 step 23 */ 5604 /* Load our MAC address. */ 5605 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5606 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5607 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5608 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5609 5610 /* Enable or disable promiscuous mode as needed. */ 5611 if (ifp->if_flags & IFF_PROMISC) 5612 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5613 else 5614 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5615 5616 /* Program multicast filter. */ 5617 bge_setmulti(sc); 5618 5619 /* Init RX ring. */ 5620 bge_init_rx_ring_std(sc); 5621 5622 /* 5623 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5624 * memory to insure that the chip has in fact read the first 5625 * entry of the ring. 5626 */ 5627 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5628 u_int i; 5629 for (i = 0; i < 10; i++) { 5630 DELAY(20); 5631 uint32_t v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5632 if (v == (MCLBYTES - ETHER_ALIGN)) 5633 break; 5634 } 5635 if (i == 10) 5636 aprint_error_dev(sc->bge_dev, 5637 "5705 A0 chip failed to load RX ring\n"); 5638 } 5639 5640 /* Init jumbo RX ring. */ 5641 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5642 bge_init_rx_ring_jumbo(sc); 5643 5644 /* Init our RX return ring index */ 5645 sc->bge_rx_saved_considx = 0; 5646 5647 /* Init TX ring. */ 5648 bge_init_tx_ring(sc); 5649 5650 /* 5718 step 63, 57XX step 94 */ 5651 /* Enable TX MAC state machine lockup fix. */ 5652 mode = CSR_READ_4(sc, BGE_TX_MODE); 5653 if (BGE_IS_5755_PLUS(sc) || 5654 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5655 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5656 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5657 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5658 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5659 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5660 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5661 } 5662 5663 /* Turn on transmitter */ 5664 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5665 /* 5718 step 64 */ 5666 DELAY(100); 5667 5668 /* 5718 step 65, 57XX step 95 */ 5669 /* Turn on receiver */ 5670 mode = CSR_READ_4(sc, BGE_RX_MODE); 5671 if (BGE_IS_5755_PLUS(sc)) 5672 mode |= BGE_RXMODE_IPV6_ENABLE; 5673 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5674 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5675 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5676 /* 5718 step 66 */ 5677 DELAY(10); 5678 5679 /* 5718 step 12, 57XX step 37 */ 5680 /* 5681 * XXX Doucments of 5718 series and 577xx say the recommended value 5682 * is 1, but tg3 set 1 only on 57765 series. 5683 */ 5684 if (BGE_IS_57765_PLUS(sc)) 5685 reg = 1; 5686 else 5687 reg = 2; 5688 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5689 5690 /* Tell firmware we're alive. */ 5691 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5692 5693 /* Enable host interrupts. */ 5694 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5695 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5696 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5697 5698 if ((error = bge_ifmedia_upd(ifp)) != 0) 5699 goto out; 5700 5701 ifp->if_flags |= IFF_RUNNING; 5702 ifp->if_flags &= ~IFF_OACTIVE; 5703 5704 callout_schedule(&sc->bge_timeout, hz); 5705 5706 out: 5707 sc->bge_if_flags = ifp->if_flags; 5708 splx(s); 5709 5710 return error; 5711 } 5712 5713 /* 5714 * Set media options. 5715 */ 5716 static int 5717 bge_ifmedia_upd(struct ifnet *ifp) 5718 { 5719 struct bge_softc * const sc = ifp->if_softc; 5720 struct mii_data * const mii = &sc->bge_mii; 5721 struct ifmedia * const ifm = &sc->bge_ifmedia; 5722 int rc; 5723 5724 /* If this is a 1000baseX NIC, enable the TBI port. */ 5725 if (sc->bge_flags & BGEF_FIBER_TBI) { 5726 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5727 return EINVAL; 5728 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5729 case IFM_AUTO: 5730 /* 5731 * The BCM5704 ASIC appears to have a special 5732 * mechanism for programming the autoneg 5733 * advertisement registers in TBI mode. 5734 */ 5735 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5736 uint32_t sgdig; 5737 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5738 if (sgdig & BGE_SGDIGSTS_DONE) { 5739 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5740 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5741 sgdig |= BGE_SGDIGCFG_AUTO | 5742 BGE_SGDIGCFG_PAUSE_CAP | 5743 BGE_SGDIGCFG_ASYM_PAUSE; 5744 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5745 sgdig | BGE_SGDIGCFG_SEND); 5746 DELAY(5); 5747 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5748 sgdig); 5749 } 5750 } 5751 break; 5752 case IFM_1000_SX: 5753 if ((ifm->ifm_media & IFM_FDX) != 0) { 5754 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5755 BGE_MACMODE_HALF_DUPLEX); 5756 } else { 5757 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5758 BGE_MACMODE_HALF_DUPLEX); 5759 } 5760 DELAY(40); 5761 break; 5762 default: 5763 return EINVAL; 5764 } 5765 /* XXX 802.3x flow control for 1000BASE-SX */ 5766 return 0; 5767 } 5768 5769 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5770 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5771 uint32_t reg; 5772 5773 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5774 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5775 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5776 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5777 } 5778 } 5779 5780 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5781 if ((rc = mii_mediachg(mii)) == ENXIO) 5782 return 0; 5783 5784 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5785 uint32_t reg; 5786 5787 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5788 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5789 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5790 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5791 delay(40); 5792 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5793 } 5794 } 5795 5796 /* 5797 * Force an interrupt so that we will call bge_link_upd 5798 * if needed and clear any pending link state attention. 5799 * Without this we are not getting any further interrupts 5800 * for link state changes and thus will not UP the link and 5801 * not be able to send in bge_start. The only way to get 5802 * things working was to receive a packet and get a RX intr. 5803 */ 5804 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5805 sc->bge_flags & BGEF_IS_5788) 5806 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5807 else 5808 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5809 5810 return rc; 5811 } 5812 5813 /* 5814 * Report current media status. 5815 */ 5816 static void 5817 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5818 { 5819 struct bge_softc * const sc = ifp->if_softc; 5820 struct mii_data * const mii = &sc->bge_mii; 5821 5822 if (sc->bge_flags & BGEF_FIBER_TBI) { 5823 ifmr->ifm_status = IFM_AVALID; 5824 ifmr->ifm_active = IFM_ETHER; 5825 if (CSR_READ_4(sc, BGE_MAC_STS) & 5826 BGE_MACSTAT_TBI_PCS_SYNCHED) 5827 ifmr->ifm_status |= IFM_ACTIVE; 5828 ifmr->ifm_active |= IFM_1000_SX; 5829 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5830 ifmr->ifm_active |= IFM_HDX; 5831 else 5832 ifmr->ifm_active |= IFM_FDX; 5833 return; 5834 } 5835 5836 mii_pollstat(mii); 5837 ifmr->ifm_status = mii->mii_media_status; 5838 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5839 sc->bge_flowflags; 5840 } 5841 5842 static int 5843 bge_ifflags_cb(struct ethercom *ec) 5844 { 5845 struct ifnet * const ifp = &ec->ec_if; 5846 struct bge_softc * const sc = ifp->if_softc; 5847 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5848 5849 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 5850 return ENETRESET; 5851 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 5852 return 0; 5853 5854 if ((ifp->if_flags & IFF_PROMISC) == 0) 5855 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5856 else 5857 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5858 5859 bge_setmulti(sc); 5860 5861 sc->bge_if_flags = ifp->if_flags; 5862 return 0; 5863 } 5864 5865 static int 5866 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5867 { 5868 struct bge_softc * const sc = ifp->if_softc; 5869 struct ifreq * const ifr = (struct ifreq *) data; 5870 int s, error = 0; 5871 struct mii_data *mii; 5872 5873 s = splnet(); 5874 5875 switch (command) { 5876 case SIOCSIFMEDIA: 5877 /* XXX Flow control is not supported for 1000BASE-SX */ 5878 if (sc->bge_flags & BGEF_FIBER_TBI) { 5879 ifr->ifr_media &= ~IFM_ETH_FMASK; 5880 sc->bge_flowflags = 0; 5881 } 5882 5883 /* Flow control requires full-duplex mode. */ 5884 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5885 (ifr->ifr_media & IFM_FDX) == 0) { 5886 ifr->ifr_media &= ~IFM_ETH_FMASK; 5887 } 5888 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5889 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5890 /* We can do both TXPAUSE and RXPAUSE. */ 5891 ifr->ifr_media |= 5892 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5893 } 5894 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5895 } 5896 5897 if (sc->bge_flags & BGEF_FIBER_TBI) { 5898 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5899 command); 5900 } else { 5901 mii = &sc->bge_mii; 5902 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5903 command); 5904 } 5905 break; 5906 default: 5907 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5908 break; 5909 5910 error = 0; 5911 5912 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 5913 ; 5914 else if (ifp->if_flags & IFF_RUNNING) 5915 bge_setmulti(sc); 5916 break; 5917 } 5918 5919 splx(s); 5920 5921 return error; 5922 } 5923 5924 static void 5925 bge_watchdog(struct ifnet *ifp) 5926 { 5927 struct bge_softc * const sc = ifp->if_softc; 5928 uint32_t status; 5929 5930 /* If pause frames are active then don't reset the hardware. */ 5931 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5932 status = CSR_READ_4(sc, BGE_RX_STS); 5933 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5934 /* 5935 * If link partner has us in XOFF state then wait for 5936 * the condition to clear. 5937 */ 5938 CSR_WRITE_4(sc, BGE_RX_STS, status); 5939 ifp->if_timer = 5; 5940 return; 5941 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5942 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5943 /* 5944 * If link partner has us in XOFF state then wait for 5945 * the condition to clear. 5946 */ 5947 CSR_WRITE_4(sc, BGE_RX_STS, status); 5948 ifp->if_timer = 5; 5949 return; 5950 } 5951 /* 5952 * Any other condition is unexpected and the controller 5953 * should be reset. 5954 */ 5955 } 5956 5957 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 5958 5959 ifp->if_flags &= ~IFF_RUNNING; 5960 bge_init(ifp); 5961 5962 if_statinc(ifp, if_oerrors); 5963 } 5964 5965 static void 5966 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 5967 { 5968 int i; 5969 5970 BGE_CLRBIT_FLUSH(sc, reg, bit); 5971 5972 for (i = 0; i < 1000; i++) { 5973 delay(100); 5974 if ((CSR_READ_4(sc, reg) & bit) == 0) 5975 return; 5976 } 5977 5978 /* 5979 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 5980 * on some environment (and once after boot?) 5981 */ 5982 if (reg != BGE_SRS_MODE) 5983 aprint_error_dev(sc->bge_dev, 5984 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 5985 (u_long)reg, bit); 5986 } 5987 5988 /* 5989 * Stop the adapter and free any mbufs allocated to the 5990 * RX and TX lists. 5991 */ 5992 static void 5993 bge_stop(struct ifnet *ifp, int disable) 5994 { 5995 struct bge_softc * const sc = ifp->if_softc; 5996 5997 if (disable) { 5998 sc->bge_detaching = 1; 5999 callout_halt(&sc->bge_timeout, NULL); 6000 } else 6001 callout_stop(&sc->bge_timeout); 6002 6003 /* Disable host interrupts. */ 6004 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6005 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6006 6007 /* 6008 * Tell firmware we're shutting down. 6009 */ 6010 bge_stop_fw(sc); 6011 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6012 6013 /* 6014 * Disable all of the receiver blocks. 6015 */ 6016 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6017 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6018 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6019 if (BGE_IS_5700_FAMILY(sc)) 6020 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6021 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6022 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6023 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6024 6025 /* 6026 * Disable all of the transmit blocks. 6027 */ 6028 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6029 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6030 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6031 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6032 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6033 if (BGE_IS_5700_FAMILY(sc)) 6034 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6035 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6036 6037 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6038 delay(40); 6039 6040 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6041 6042 /* 6043 * Shut down all of the memory managers and related 6044 * state machines. 6045 */ 6046 /* 5718 step 5a,5b */ 6047 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6048 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6049 if (BGE_IS_5700_FAMILY(sc)) 6050 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6051 6052 /* 5718 step 5c,5d */ 6053 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6054 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6055 6056 if (BGE_IS_5700_FAMILY(sc)) { 6057 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6058 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6059 } 6060 6061 bge_reset(sc); 6062 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6063 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6064 6065 /* 6066 * Keep the ASF firmware running if up. 6067 */ 6068 if (sc->bge_asf_mode & ASF_STACKUP) 6069 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6070 else 6071 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6072 6073 /* Free the RX lists. */ 6074 bge_free_rx_ring_std(sc, disable); 6075 6076 /* Free jumbo RX list. */ 6077 if (BGE_IS_JUMBO_CAPABLE(sc)) 6078 bge_free_rx_ring_jumbo(sc); 6079 6080 /* Free TX buffers. */ 6081 bge_free_tx_ring(sc, disable); 6082 6083 /* 6084 * Isolate/power down the PHY. 6085 */ 6086 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6087 mii_down(&sc->bge_mii); 6088 6089 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6090 6091 /* Clear MAC's link state (PHY may still have link UP). */ 6092 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6093 6094 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6095 } 6096 6097 static void 6098 bge_link_upd(struct bge_softc *sc) 6099 { 6100 struct ifnet * const ifp = &sc->ethercom.ec_if; 6101 struct mii_data * const mii = &sc->bge_mii; 6102 uint32_t status; 6103 uint16_t phyval; 6104 int link; 6105 6106 /* Clear 'pending link event' flag */ 6107 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6108 6109 /* 6110 * Process link state changes. 6111 * Grrr. The link status word in the status block does 6112 * not work correctly on the BCM5700 rev AX and BX chips, 6113 * according to all available information. Hence, we have 6114 * to enable MII interrupts in order to properly obtain 6115 * async link changes. Unfortunately, this also means that 6116 * we have to read the MAC status register to detect link 6117 * changes, thereby adding an additional register access to 6118 * the interrupt handler. 6119 */ 6120 6121 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6122 status = CSR_READ_4(sc, BGE_MAC_STS); 6123 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6124 mii_pollstat(mii); 6125 6126 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6127 mii->mii_media_status & IFM_ACTIVE && 6128 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6129 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6130 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6131 (!(mii->mii_media_status & IFM_ACTIVE) || 6132 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6133 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6134 6135 /* Clear the interrupt */ 6136 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6137 BGE_EVTENB_MI_INTERRUPT); 6138 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6139 BRGPHY_MII_ISR, &phyval); 6140 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6141 BRGPHY_MII_IMR, BRGPHY_INTRS); 6142 } 6143 return; 6144 } 6145 6146 if (sc->bge_flags & BGEF_FIBER_TBI) { 6147 status = CSR_READ_4(sc, BGE_MAC_STS); 6148 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6149 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6150 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6151 if (BGE_ASICREV(sc->bge_chipid) 6152 == BGE_ASICREV_BCM5704) { 6153 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6154 BGE_MACMODE_TBI_SEND_CFGS); 6155 DELAY(40); 6156 } 6157 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6158 if_link_state_change(ifp, LINK_STATE_UP); 6159 } 6160 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6161 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6162 if_link_state_change(ifp, LINK_STATE_DOWN); 6163 } 6164 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6165 /* 6166 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6167 * bit in status word always set. Workaround this bug by 6168 * reading PHY link status directly. 6169 */ 6170 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6171 BGE_STS_LINK : 0; 6172 6173 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6174 mii_pollstat(mii); 6175 6176 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6177 mii->mii_media_status & IFM_ACTIVE && 6178 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6179 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6180 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6181 (!(mii->mii_media_status & IFM_ACTIVE) || 6182 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6183 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6184 } 6185 } else { 6186 /* 6187 * For controllers that call mii_tick, we have to poll 6188 * link status. 6189 */ 6190 mii_pollstat(mii); 6191 } 6192 6193 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6194 uint32_t reg, scale; 6195 6196 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6197 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6198 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6199 scale = 65; 6200 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6201 scale = 6; 6202 else 6203 scale = 12; 6204 6205 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6206 ~BGE_MISCCFG_TIMER_PRESCALER; 6207 reg |= scale << 1; 6208 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6209 } 6210 /* Clear the attention */ 6211 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6212 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6213 BGE_MACSTAT_LINK_CHANGED); 6214 } 6215 6216 static int 6217 bge_sysctl_verify(SYSCTLFN_ARGS) 6218 { 6219 int error, t; 6220 struct sysctlnode node; 6221 6222 node = *rnode; 6223 t = *(int*)rnode->sysctl_data; 6224 node.sysctl_data = &t; 6225 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6226 if (error || newp == NULL) 6227 return error; 6228 6229 #if 0 6230 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6231 node.sysctl_num, rnode->sysctl_num)); 6232 #endif 6233 6234 if (node.sysctl_num == bge_rxthresh_nodenum) { 6235 if (t < 0 || t >= NBGE_RX_THRESH) 6236 return EINVAL; 6237 bge_update_all_threshes(t); 6238 } else 6239 return EINVAL; 6240 6241 *(int*)rnode->sysctl_data = t; 6242 6243 return 0; 6244 } 6245 6246 /* 6247 * Set up sysctl(3) MIB, hw.bge.*. 6248 */ 6249 static void 6250 bge_sysctl_init(struct bge_softc *sc) 6251 { 6252 int rc, bge_root_num; 6253 const struct sysctlnode *node; 6254 6255 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6256 0, CTLTYPE_NODE, "bge", 6257 SYSCTL_DESCR("BGE interface controls"), 6258 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6259 goto out; 6260 } 6261 6262 bge_root_num = node->sysctl_num; 6263 6264 /* BGE Rx interrupt mitigation level */ 6265 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6266 CTLFLAG_READWRITE, 6267 CTLTYPE_INT, "rx_lvl", 6268 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6269 bge_sysctl_verify, 0, 6270 &bge_rx_thresh_lvl, 6271 0, CTL_HW, bge_root_num, CTL_CREATE, 6272 CTL_EOL)) != 0) { 6273 goto out; 6274 } 6275 6276 bge_rxthresh_nodenum = node->sysctl_num; 6277 6278 return; 6279 6280 out: 6281 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6282 } 6283 6284 #ifdef BGE_DEBUG 6285 void 6286 bge_debug_info(struct bge_softc *sc) 6287 { 6288 6289 printf("Hardware Flags:\n"); 6290 if (BGE_IS_57765_PLUS(sc)) 6291 printf(" - 57765 Plus\n"); 6292 if (BGE_IS_5717_PLUS(sc)) 6293 printf(" - 5717 Plus\n"); 6294 if (BGE_IS_5755_PLUS(sc)) 6295 printf(" - 5755 Plus\n"); 6296 if (BGE_IS_575X_PLUS(sc)) 6297 printf(" - 575X Plus\n"); 6298 if (BGE_IS_5705_PLUS(sc)) 6299 printf(" - 5705 Plus\n"); 6300 if (BGE_IS_5714_FAMILY(sc)) 6301 printf(" - 5714 Family\n"); 6302 if (BGE_IS_5700_FAMILY(sc)) 6303 printf(" - 5700 Family\n"); 6304 if (sc->bge_flags & BGEF_IS_5788) 6305 printf(" - 5788\n"); 6306 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6307 printf(" - Supports Jumbo Frames\n"); 6308 if (sc->bge_flags & BGEF_NO_EEPROM) 6309 printf(" - No EEPROM\n"); 6310 if (sc->bge_flags & BGEF_PCIX) 6311 printf(" - PCI-X Bus\n"); 6312 if (sc->bge_flags & BGEF_PCIE) 6313 printf(" - PCI Express Bus\n"); 6314 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6315 printf(" - RX Alignment Bug\n"); 6316 if (sc->bge_flags & BGEF_APE) 6317 printf(" - APE\n"); 6318 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6319 printf(" - CPMU\n"); 6320 if (sc->bge_flags & BGEF_TSO) 6321 printf(" - TSO\n"); 6322 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6323 printf(" - TAGGED_STATUS\n"); 6324 6325 /* PHY related */ 6326 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6327 printf(" - No 3 LEDs\n"); 6328 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6329 printf(" - CRC bug\n"); 6330 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6331 printf(" - ADC bug\n"); 6332 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6333 printf(" - 5704 A0 bug\n"); 6334 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6335 printf(" - jitter bug\n"); 6336 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6337 printf(" - BER bug\n"); 6338 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6339 printf(" - adjust trim\n"); 6340 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6341 printf(" - no wirespeed\n"); 6342 6343 /* ASF related */ 6344 if (sc->bge_asf_mode & ASF_ENABLE) 6345 printf(" - ASF enable\n"); 6346 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6347 printf(" - ASF new handshake\n"); 6348 if (sc->bge_asf_mode & ASF_STACKUP) 6349 printf(" - ASF stackup\n"); 6350 } 6351 #endif /* BGE_DEBUG */ 6352 6353 static int 6354 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6355 { 6356 prop_dictionary_t dict; 6357 prop_data_t ea; 6358 6359 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6360 return 1; 6361 6362 dict = device_properties(sc->bge_dev); 6363 ea = prop_dictionary_get(dict, "mac-address"); 6364 if (ea != NULL) { 6365 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6366 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6367 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6368 return 0; 6369 } 6370 6371 return 1; 6372 } 6373 6374 static int 6375 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6376 { 6377 uint32_t mac_addr; 6378 6379 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6380 if ((mac_addr >> 16) == 0x484b) { 6381 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6382 ether_addr[1] = (uint8_t)mac_addr; 6383 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6384 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6385 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6386 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6387 ether_addr[5] = (uint8_t)mac_addr; 6388 return 0; 6389 } 6390 return 1; 6391 } 6392 6393 static int 6394 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6395 { 6396 int mac_offset = BGE_EE_MAC_OFFSET; 6397 6398 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6399 mac_offset = BGE_EE_MAC_OFFSET_5906; 6400 6401 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6402 ETHER_ADDR_LEN)); 6403 } 6404 6405 static int 6406 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6407 { 6408 6409 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6410 return 1; 6411 6412 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6413 ETHER_ADDR_LEN)); 6414 } 6415 6416 static int 6417 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6418 { 6419 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6420 /* NOTE: Order is critical */ 6421 bge_get_eaddr_fw, 6422 bge_get_eaddr_mem, 6423 bge_get_eaddr_nvram, 6424 bge_get_eaddr_eeprom, 6425 NULL 6426 }; 6427 const bge_eaddr_fcn_t *func; 6428 6429 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6430 if ((*func)(sc, eaddr) == 0) 6431 break; 6432 } 6433 return *func == NULL ? ENXIO : 0; 6434 } 6435
Indexes created Tue Sep 23 02:09:52 GMT 2025