if_bge.c revision 1.384
1 /* $NetBSD: if_bge.c,v 1.384 2022/08/27 06:32:53 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.384 2022/08/27 06:32:53 skrll Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/callout.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> 90 #include <sys/kmem.h> 91 #include <sys/mbuf.h> 92 #include <sys/rndsource.h> 93 #include <sys/socket.h> 94 #include <sys/sockio.h> 95 #include <sys/sysctl.h> 96 #include <sys/systm.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 #include <net/bpf.h> 103 104 /* Headers for TCP Segmentation Offload (TSO) */ 105 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 106 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 107 #include <netinet/ip.h> /* for struct ip */ 108 #include <netinet/tcp.h> /* for struct tcphdr */ 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 #include <dev/mii/miidevs.h> 117 #include <dev/mii/brgphyreg.h> 118 119 #include <dev/pci/if_bgereg.h> 120 #include <dev/pci/if_bgevar.h> 121 122 #include <prop/proplib.h> 123 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 127 /* 128 * Tunable thresholds for rx-side bge interrupt mitigation. 129 */ 130 131 /* 132 * The pairs of values below were obtained from empirical measurement 133 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 134 * interrupt for every N packets received, where N is, approximately, 135 * the second value (rx_max_bds) in each pair. The values are chosen 136 * such that moving from one pair to the succeeding pair was observed 137 * to roughly halve interrupt rate under sustained input packet load. 138 * The values were empirically chosen to avoid overflowing internal 139 * limits on the bcm5700: increasing rx_ticks much beyond 600 140 * results in internal wrapping and higher interrupt rates. 141 * The limit of 46 frames was chosen to match NFS workloads. 142 * 143 * These values also work well on bcm5701, bcm5704C, and (less 144 * tested) bcm5703. On other chipsets, (including the Altima chip 145 * family), the larger values may overflow internal chip limits, 146 * leading to increasing interrupt rates rather than lower interrupt 147 * rates. 148 * 149 * Applications using heavy interrupt mitigation (interrupting every 150 * 32 or 46 frames) in both directions may need to increase the TCP 151 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 152 * full link bandwidth, due to ACKs and window updates lingering 153 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 154 */ 155 static const struct bge_load_rx_thresh { 156 int rx_ticks; 157 int rx_max_bds; } 158 bge_rx_threshes[] = { 159 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 160 { 32, 2 }, 161 { 50, 4 }, 162 { 100, 8 }, 163 { 192, 16 }, 164 { 416, 32 }, 165 { 598, 46 } 166 }; 167 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 168 169 /* XXX patchable; should be sysctl'able */ 170 static int bge_auto_thresh = 1; 171 static int bge_rx_thresh_lvl; 172 173 static int bge_rxthresh_nodenum; 174 175 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 176 177 static uint32_t bge_chipid(const struct pci_attach_args *); 178 static int bge_can_use_msi(struct bge_softc *); 179 static int bge_probe(device_t, cfdata_t, void *); 180 static void bge_attach(device_t, device_t, void *); 181 static int bge_detach(device_t, int); 182 static void bge_release_resources(struct bge_softc *); 183 184 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 185 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 186 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 187 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 188 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 189 190 static void bge_txeof(struct bge_softc *); 191 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 192 static void bge_rxeof(struct bge_softc *); 193 194 static void bge_asf_driver_up (struct bge_softc *); 195 static void bge_tick(void *); 196 static void bge_stats_update(struct bge_softc *); 197 static void bge_stats_update_regs(struct bge_softc *); 198 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 199 200 static int bge_intr(void *); 201 static void bge_start(struct ifnet *); 202 static void bge_start_locked(struct ifnet *); 203 static int bge_ifflags_cb(struct ethercom *); 204 static int bge_ioctl(struct ifnet *, u_long, void *); 205 static int bge_init(struct ifnet *); 206 static int bge_init_locked(struct ifnet *); 207 static void bge_stop(struct ifnet *, int); 208 static void bge_stop_locked(struct ifnet *, int); 209 static bool bge_watchdog(struct ifnet *); 210 static int bge_ifmedia_upd(struct ifnet *); 211 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 212 static void bge_handle_reset_work(struct work *, void *); 213 214 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 215 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 216 217 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 219 static void bge_setmulti(struct bge_softc *); 220 221 static void bge_handle_events(struct bge_softc *); 222 static int bge_alloc_jumbo_mem(struct bge_softc *); 223 static void bge_free_jumbo_mem(struct bge_softc *); 224 static void *bge_jalloc(struct bge_softc *); 225 static void bge_jfree(struct mbuf *, void *, size_t, void *); 226 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 227 static int bge_init_rx_ring_jumbo(struct bge_softc *); 228 static void bge_free_rx_ring_jumbo(struct bge_softc *); 229 230 static int bge_newbuf_std(struct bge_softc *, int); 231 static int bge_init_rx_ring_std(struct bge_softc *); 232 static void bge_fill_rx_ring_std(struct bge_softc *); 233 static void bge_free_rx_ring_std(struct bge_softc *m); 234 235 static void bge_free_tx_ring(struct bge_softc *m, bool); 236 static int bge_init_tx_ring(struct bge_softc *); 237 238 static int bge_chipinit(struct bge_softc *); 239 static int bge_blockinit(struct bge_softc *); 240 static int bge_phy_addr(struct bge_softc *); 241 static uint32_t bge_readmem_ind(struct bge_softc *, int); 242 static void bge_writemem_ind(struct bge_softc *, int, int); 243 static void bge_writembx(struct bge_softc *, int, int); 244 static void bge_writembx_flush(struct bge_softc *, int, int); 245 static void bge_writemem_direct(struct bge_softc *, int, int); 246 static void bge_writereg_ind(struct bge_softc *, int, int); 247 static void bge_set_max_readrq(struct bge_softc *); 248 249 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 250 static int bge_miibus_writereg(device_t, int, int, uint16_t); 251 static void bge_miibus_statchg(struct ifnet *); 252 253 #define BGE_RESET_SHUTDOWN 0 254 #define BGE_RESET_START 1 255 #define BGE_RESET_SUSPEND 2 256 static void bge_sig_post_reset(struct bge_softc *, int); 257 static void bge_sig_legacy(struct bge_softc *, int); 258 static void bge_sig_pre_reset(struct bge_softc *, int); 259 static void bge_wait_for_event_ack(struct bge_softc *); 260 static void bge_stop_fw(struct bge_softc *); 261 static int bge_reset(struct bge_softc *); 262 static void bge_link_upd(struct bge_softc *); 263 static void bge_sysctl_init(struct bge_softc *); 264 static int bge_sysctl_verify(SYSCTLFN_PROTO); 265 266 static void bge_ape_lock_init(struct bge_softc *); 267 static void bge_ape_read_fw_ver(struct bge_softc *); 268 static int bge_ape_lock(struct bge_softc *, int); 269 static void bge_ape_unlock(struct bge_softc *, int); 270 static void bge_ape_send_event(struct bge_softc *, uint32_t); 271 static void bge_ape_driver_state_change(struct bge_softc *, int); 272 273 #ifdef BGE_DEBUG 274 #define DPRINTF(x) if (bgedebug) printf x 275 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 276 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 277 int bgedebug = 0; 278 int bge_tso_debug = 0; 279 void bge_debug_info(struct bge_softc *); 280 #else 281 #define DPRINTF(x) 282 #define DPRINTFN(n, x) 283 #define BGE_TSO_PRINTF(x) 284 #endif 285 286 #ifdef BGE_EVENT_COUNTERS 287 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 288 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 289 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 290 #else 291 #define BGE_EVCNT_INCR(ev) /* nothing */ 292 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 293 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 294 #endif 295 296 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 297 /* 298 * The BCM5700 documentation seems to indicate that the hardware still has the 299 * Alteon vendor ID burned into it, though it should always be overridden by 300 * the value in the EEPROM. We'll check for it anyway. 301 */ 302 static const struct bge_product { 303 pci_vendor_id_t bp_vendor; 304 pci_product_id_t bp_product; 305 const char *bp_name; 306 } bge_products[] = { 307 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 308 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 309 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 310 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 311 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 312 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 313 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 314 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 315 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 318 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 319 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 320 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 322 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 323 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 326 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 330 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 331 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 332 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 334 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 336 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 348 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 349 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 353 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 354 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 362 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 363 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 364 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 366 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 367 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 368 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 369 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 370 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 371 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 372 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 373 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 374 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 375 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 376 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 377 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 378 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 379 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 380 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 381 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 382 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 383 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 399 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 400 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 401 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 402 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 403 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 404 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 405 { 0, 0, NULL }, 406 }; 407 408 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 409 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 410 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 411 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 412 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 413 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 414 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 415 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 416 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 417 418 static const struct bge_revision { 419 uint32_t br_chipid; 420 const char *br_name; 421 } bge_revisions[] = { 422 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 423 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 424 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 425 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 426 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 427 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 428 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 429 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 430 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 431 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 432 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 433 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 434 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 435 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 436 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 437 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 438 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 439 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 440 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 441 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 442 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 443 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 444 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 445 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 446 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 447 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 448 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 449 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 450 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 451 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 452 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 453 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 454 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 455 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 456 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 457 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 458 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 459 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 460 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 461 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 462 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 463 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 464 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 465 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 466 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 467 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 468 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 469 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 470 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 471 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 472 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 473 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 474 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 475 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 476 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 477 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 478 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 479 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 480 /* 5754 and 5787 share the same ASIC ID */ 481 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 482 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 483 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 484 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 485 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 486 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 487 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 488 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 489 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 490 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 491 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 492 493 { 0, NULL } 494 }; 495 496 /* 497 * Some defaults for major revisions, so that newer steppings 498 * that we don't know about have a shot at working. 499 */ 500 static const struct bge_revision bge_majorrevs[] = { 501 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 502 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 503 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 504 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 505 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 506 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 507 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 508 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 509 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 510 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 511 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 512 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 513 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 514 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 515 /* 5754 and 5787 share the same ASIC ID */ 516 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 517 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 518 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 519 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 520 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 521 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 522 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 523 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 524 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 525 526 { 0, NULL } 527 }; 528 529 static int bge_allow_asf = 1; 530 531 #ifndef BGE_WATCHDOG_TIMEOUT 532 #define BGE_WATCHDOG_TIMEOUT 5 533 #endif 534 static int bge_watchdog_timeout = BGE_WATCHDOG_TIMEOUT; 535 536 537 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 538 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 539 540 static uint32_t 541 bge_readmem_ind(struct bge_softc *sc, int off) 542 { 543 pcireg_t val; 544 545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 546 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 547 return 0; 548 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 550 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 551 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 552 return val; 553 } 554 555 static void 556 bge_writemem_ind(struct bge_softc *sc, int off, int val) 557 { 558 559 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 560 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 561 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 562 } 563 564 /* 565 * PCI Express only 566 */ 567 static void 568 bge_set_max_readrq(struct bge_softc *sc) 569 { 570 pcireg_t val; 571 572 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 573 + PCIE_DCSR); 574 val &= ~PCIE_DCSR_MAX_READ_REQ; 575 switch (sc->bge_expmrq) { 576 case 2048: 577 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 578 break; 579 case 4096: 580 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 581 break; 582 default: 583 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 584 break; 585 } 586 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 587 + PCIE_DCSR, val); 588 } 589 590 #ifdef notdef 591 static uint32_t 592 bge_readreg_ind(struct bge_softc *sc, int off) 593 { 594 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 595 return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA); 596 } 597 #endif 598 599 static void 600 bge_writereg_ind(struct bge_softc *sc, int off, int val) 601 { 602 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 603 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 604 } 605 606 static void 607 bge_writemem_direct(struct bge_softc *sc, int off, int val) 608 { 609 CSR_WRITE_4(sc, off, val); 610 } 611 612 static void 613 bge_writembx(struct bge_softc *sc, int off, int val) 614 { 615 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 616 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 617 618 CSR_WRITE_4(sc, off, val); 619 } 620 621 static void 622 bge_writembx_flush(struct bge_softc *sc, int off, int val) 623 { 624 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 625 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 626 627 CSR_WRITE_4_FLUSH(sc, off, val); 628 } 629 630 /* 631 * Clear all stale locks and select the lock for this driver instance. 632 */ 633 void 634 bge_ape_lock_init(struct bge_softc *sc) 635 { 636 struct pci_attach_args *pa = &(sc->bge_pa); 637 uint32_t bit, regbase; 638 int i; 639 640 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 641 regbase = BGE_APE_LOCK_GRANT; 642 else 643 regbase = BGE_APE_PER_LOCK_GRANT; 644 645 /* Clear any stale locks. */ 646 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 647 switch (i) { 648 case BGE_APE_LOCK_PHY0: 649 case BGE_APE_LOCK_PHY1: 650 case BGE_APE_LOCK_PHY2: 651 case BGE_APE_LOCK_PHY3: 652 bit = BGE_APE_LOCK_GRANT_DRIVER0; 653 break; 654 default: 655 if (pa->pa_function == 0) 656 bit = BGE_APE_LOCK_GRANT_DRIVER0; 657 else 658 bit = (1 << pa->pa_function); 659 } 660 APE_WRITE_4(sc, regbase + 4 * i, bit); 661 } 662 663 /* Select the PHY lock based on the device's function number. */ 664 switch (pa->pa_function) { 665 case 0: 666 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 667 break; 668 case 1: 669 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 670 break; 671 case 2: 672 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 673 break; 674 case 3: 675 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 676 break; 677 default: 678 printf("%s: PHY lock not supported on function\n", 679 device_xname(sc->bge_dev)); 680 break; 681 } 682 } 683 684 /* 685 * Check for APE firmware, set flags, and print version info. 686 */ 687 void 688 bge_ape_read_fw_ver(struct bge_softc *sc) 689 { 690 const char *fwtype; 691 uint32_t apedata, features; 692 693 /* Check for a valid APE signature in shared memory. */ 694 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 695 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 696 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 697 return; 698 } 699 700 /* Check if APE firmware is running. */ 701 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 702 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 703 printf("%s: APE signature found but FW status not ready! " 704 "0x%08x\n", device_xname(sc->bge_dev), apedata); 705 return; 706 } 707 708 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 709 710 /* Fetch the APE firwmare type and version. */ 711 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 712 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 713 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 714 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 715 fwtype = "NCSI"; 716 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 717 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 718 fwtype = "DASH"; 719 } else 720 fwtype = "UNKN"; 721 722 /* Print the APE firmware version. */ 723 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 724 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 725 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 726 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 727 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 728 } 729 730 int 731 bge_ape_lock(struct bge_softc *sc, int locknum) 732 { 733 struct pci_attach_args *pa = &(sc->bge_pa); 734 uint32_t bit, gnt, req, status; 735 int i, off; 736 737 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 738 return 0; 739 740 /* Lock request/grant registers have different bases. */ 741 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 742 req = BGE_APE_LOCK_REQ; 743 gnt = BGE_APE_LOCK_GRANT; 744 } else { 745 req = BGE_APE_PER_LOCK_REQ; 746 gnt = BGE_APE_PER_LOCK_GRANT; 747 } 748 749 off = 4 * locknum; 750 751 switch (locknum) { 752 case BGE_APE_LOCK_GPIO: 753 /* Lock required when using GPIO. */ 754 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 755 return 0; 756 if (pa->pa_function == 0) 757 bit = BGE_APE_LOCK_REQ_DRIVER0; 758 else 759 bit = (1 << pa->pa_function); 760 break; 761 case BGE_APE_LOCK_GRC: 762 /* Lock required to reset the device. */ 763 if (pa->pa_function == 0) 764 bit = BGE_APE_LOCK_REQ_DRIVER0; 765 else 766 bit = (1 << pa->pa_function); 767 break; 768 case BGE_APE_LOCK_MEM: 769 /* Lock required when accessing certain APE memory. */ 770 if (pa->pa_function == 0) 771 bit = BGE_APE_LOCK_REQ_DRIVER0; 772 else 773 bit = (1 << pa->pa_function); 774 break; 775 case BGE_APE_LOCK_PHY0: 776 case BGE_APE_LOCK_PHY1: 777 case BGE_APE_LOCK_PHY2: 778 case BGE_APE_LOCK_PHY3: 779 /* Lock required when accessing PHYs. */ 780 bit = BGE_APE_LOCK_REQ_DRIVER0; 781 break; 782 default: 783 return EINVAL; 784 } 785 786 /* Request a lock. */ 787 APE_WRITE_4_FLUSH(sc, req + off, bit); 788 789 /* Wait up to 1 second to acquire lock. */ 790 for (i = 0; i < 20000; i++) { 791 status = APE_READ_4(sc, gnt + off); 792 if (status == bit) 793 break; 794 DELAY(50); 795 } 796 797 /* Handle any errors. */ 798 if (status != bit) { 799 printf("%s: APE lock %d request failed! " 800 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 801 device_xname(sc->bge_dev), 802 locknum, req + off, bit & 0xFFFF, gnt + off, 803 status & 0xFFFF); 804 /* Revoke the lock request. */ 805 APE_WRITE_4(sc, gnt + off, bit); 806 return EBUSY; 807 } 808 809 return 0; 810 } 811 812 void 813 bge_ape_unlock(struct bge_softc *sc, int locknum) 814 { 815 struct pci_attach_args *pa = &(sc->bge_pa); 816 uint32_t bit, gnt; 817 int off; 818 819 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 820 return; 821 822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 823 gnt = BGE_APE_LOCK_GRANT; 824 else 825 gnt = BGE_APE_PER_LOCK_GRANT; 826 827 off = 4 * locknum; 828 829 switch (locknum) { 830 case BGE_APE_LOCK_GPIO: 831 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 832 return; 833 if (pa->pa_function == 0) 834 bit = BGE_APE_LOCK_GRANT_DRIVER0; 835 else 836 bit = (1 << pa->pa_function); 837 break; 838 case BGE_APE_LOCK_GRC: 839 if (pa->pa_function == 0) 840 bit = BGE_APE_LOCK_GRANT_DRIVER0; 841 else 842 bit = (1 << pa->pa_function); 843 break; 844 case BGE_APE_LOCK_MEM: 845 if (pa->pa_function == 0) 846 bit = BGE_APE_LOCK_GRANT_DRIVER0; 847 else 848 bit = (1 << pa->pa_function); 849 break; 850 case BGE_APE_LOCK_PHY0: 851 case BGE_APE_LOCK_PHY1: 852 case BGE_APE_LOCK_PHY2: 853 case BGE_APE_LOCK_PHY3: 854 bit = BGE_APE_LOCK_GRANT_DRIVER0; 855 break; 856 default: 857 return; 858 } 859 860 /* Write and flush for consecutive bge_ape_lock() */ 861 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 862 } 863 864 /* 865 * Send an event to the APE firmware. 866 */ 867 void 868 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 869 { 870 uint32_t apedata; 871 int i; 872 873 /* NCSI does not support APE events. */ 874 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 875 return; 876 877 /* Wait up to 1ms for APE to service previous event. */ 878 for (i = 10; i > 0; i--) { 879 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 880 break; 881 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 882 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 883 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 884 BGE_APE_EVENT_STATUS_EVENT_PENDING); 885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 886 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 887 break; 888 } 889 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 890 DELAY(100); 891 } 892 if (i == 0) { 893 printf("%s: APE event 0x%08x send timed out\n", 894 device_xname(sc->bge_dev), event); 895 } 896 } 897 898 void 899 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 900 { 901 uint32_t apedata, event; 902 903 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 904 return; 905 906 switch (kind) { 907 case BGE_RESET_START: 908 /* If this is the first load, clear the load counter. */ 909 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 910 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 911 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 912 else { 913 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 914 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 915 } 916 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 917 BGE_APE_HOST_SEG_SIG_MAGIC); 918 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 919 BGE_APE_HOST_SEG_LEN_MAGIC); 920 921 /* Add some version info if bge(4) supports it. */ 922 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 923 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 924 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 925 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 926 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 927 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 928 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 929 BGE_APE_HOST_DRVR_STATE_START); 930 event = BGE_APE_EVENT_STATUS_STATE_START; 931 break; 932 case BGE_RESET_SHUTDOWN: 933 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 934 BGE_APE_HOST_DRVR_STATE_UNLOAD); 935 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 936 break; 937 case BGE_RESET_SUSPEND: 938 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 939 break; 940 default: 941 return; 942 } 943 944 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 945 BGE_APE_EVENT_STATUS_STATE_CHNGE); 946 } 947 948 static uint8_t 949 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 950 { 951 uint32_t access, byte = 0; 952 int i; 953 954 /* Lock. */ 955 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 956 for (i = 0; i < 8000; i++) { 957 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 958 break; 959 DELAY(20); 960 } 961 if (i == 8000) 962 return 1; 963 964 /* Enable access. */ 965 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 966 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 967 968 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 969 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 970 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 971 DELAY(10); 972 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 973 DELAY(10); 974 break; 975 } 976 } 977 978 if (i == BGE_TIMEOUT * 10) { 979 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 980 return 1; 981 } 982 983 /* Get result. */ 984 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 985 986 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 987 988 /* Disable access. */ 989 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 990 991 /* Unlock. */ 992 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 993 994 return 0; 995 } 996 997 /* 998 * Read a sequence of bytes from NVRAM. 999 */ 1000 static int 1001 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1002 { 1003 int error = 0, i; 1004 uint8_t byte = 0; 1005 1006 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1007 return 1; 1008 1009 for (i = 0; i < cnt; i++) { 1010 error = bge_nvram_getbyte(sc, off + i, &byte); 1011 if (error) 1012 break; 1013 *(dest + i) = byte; 1014 } 1015 1016 return error ? 1 : 0; 1017 } 1018 1019 /* 1020 * Read a byte of data stored in the EEPROM at address 'addr.' The 1021 * BCM570x supports both the traditional bitbang interface and an 1022 * auto access interface for reading the EEPROM. We use the auto 1023 * access method. 1024 */ 1025 static uint8_t 1026 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1027 { 1028 int i; 1029 uint32_t byte = 0; 1030 1031 /* 1032 * Enable use of auto EEPROM access so we can avoid 1033 * having to use the bitbang method. 1034 */ 1035 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1036 1037 /* Reset the EEPROM, load the clock period. */ 1038 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1039 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1040 DELAY(20); 1041 1042 /* Issue the read EEPROM command. */ 1043 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1044 1045 /* Wait for completion */ 1046 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1047 DELAY(10); 1048 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1049 break; 1050 } 1051 1052 if (i == BGE_TIMEOUT * 10) { 1053 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1054 return 1; 1055 } 1056 1057 /* Get result. */ 1058 byte = CSR_READ_4(sc, BGE_EE_DATA); 1059 1060 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1061 1062 return 0; 1063 } 1064 1065 /* 1066 * Read a sequence of bytes from the EEPROM. 1067 */ 1068 static int 1069 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1070 { 1071 int error = 0, i; 1072 uint8_t byte = 0; 1073 char *dest = destv; 1074 1075 for (i = 0; i < cnt; i++) { 1076 error = bge_eeprom_getbyte(sc, off + i, &byte); 1077 if (error) 1078 break; 1079 *(dest + i) = byte; 1080 } 1081 1082 return error ? 1 : 0; 1083 } 1084 1085 static int 1086 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1087 { 1088 struct bge_softc * const sc = device_private(dev); 1089 uint32_t data; 1090 uint32_t autopoll; 1091 int rv = 0; 1092 int i; 1093 1094 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1095 return -1; 1096 1097 /* Reading with autopolling on may trigger PCI errors */ 1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1099 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1100 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1101 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1102 DELAY(80); 1103 } 1104 1105 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1106 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1107 1108 for (i = 0; i < BGE_TIMEOUT; i++) { 1109 delay(10); 1110 data = CSR_READ_4(sc, BGE_MI_COMM); 1111 if (!(data & BGE_MICOMM_BUSY)) { 1112 DELAY(5); 1113 data = CSR_READ_4(sc, BGE_MI_COMM); 1114 break; 1115 } 1116 } 1117 1118 if (i == BGE_TIMEOUT) { 1119 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1120 rv = ETIMEDOUT; 1121 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1122 /* XXX This error occurs on some devices while attaching. */ 1123 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1124 rv = EIO; 1125 } else 1126 *val = data & BGE_MICOMM_DATA; 1127 1128 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1129 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1130 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1131 DELAY(80); 1132 } 1133 1134 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1135 1136 return rv; 1137 } 1138 1139 static int 1140 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1141 { 1142 struct bge_softc * const sc = device_private(dev); 1143 uint32_t data, autopoll; 1144 int rv = 0; 1145 int i; 1146 1147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1148 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1149 return 0; 1150 1151 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1152 return -1; 1153 1154 /* Reading with autopolling on may trigger PCI errors */ 1155 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1156 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1157 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1158 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1159 DELAY(80); 1160 } 1161 1162 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1163 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1164 1165 for (i = 0; i < BGE_TIMEOUT; i++) { 1166 delay(10); 1167 data = CSR_READ_4(sc, BGE_MI_COMM); 1168 if (!(data & BGE_MICOMM_BUSY)) { 1169 delay(5); 1170 data = CSR_READ_4(sc, BGE_MI_COMM); 1171 break; 1172 } 1173 } 1174 1175 if (i == BGE_TIMEOUT) { 1176 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1177 rv = ETIMEDOUT; 1178 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1179 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1180 rv = EIO; 1181 } 1182 1183 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1184 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1185 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1186 delay(80); 1187 } 1188 1189 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1190 1191 return rv; 1192 } 1193 1194 static void 1195 bge_miibus_statchg(struct ifnet *ifp) 1196 { 1197 struct bge_softc * const sc = ifp->if_softc; 1198 struct mii_data *mii = &sc->bge_mii; 1199 uint32_t mac_mode, rx_mode, tx_mode; 1200 1201 /* 1202 * Get flow control negotiation result. 1203 */ 1204 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1205 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1206 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1207 1208 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1209 mii->mii_media_status & IFM_ACTIVE && 1210 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1211 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1212 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1213 (!(mii->mii_media_status & IFM_ACTIVE) || 1214 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1215 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1216 1217 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1218 return; 1219 1220 /* Set the port mode (MII/GMII) to match the link speed. */ 1221 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1222 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1223 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1224 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1225 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1226 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1227 mac_mode |= BGE_PORTMODE_GMII; 1228 else 1229 mac_mode |= BGE_PORTMODE_MII; 1230 1231 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1232 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1233 if ((mii->mii_media_active & IFM_FDX) != 0) { 1234 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1235 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1236 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1237 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1238 } else 1239 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1240 1241 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1242 DELAY(40); 1243 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1244 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1245 } 1246 1247 /* 1248 * Update rx threshold levels to values in a particular slot 1249 * of the interrupt-mitigation table bge_rx_threshes. 1250 */ 1251 static void 1252 bge_set_thresh(struct ifnet *ifp, int lvl) 1253 { 1254 struct bge_softc * const sc = ifp->if_softc; 1255 1256 /* 1257 * For now, just save the new Rx-intr thresholds and record 1258 * that a threshold update is pending. Updating the hardware 1259 * registers here (even at splhigh()) is observed to 1260 * occasionally cause glitches where Rx-interrupts are not 1261 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1262 */ 1263 mutex_enter(sc->sc_core_lock); 1264 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1265 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1266 sc->bge_pending_rxintr_change = true; 1267 mutex_exit(sc->sc_core_lock); 1268 } 1269 1270 1271 /* 1272 * Update Rx thresholds of all bge devices 1273 */ 1274 static void 1275 bge_update_all_threshes(int lvl) 1276 { 1277 const char * const namebuf = "bge"; 1278 const size_t namelen = strlen(namebuf); 1279 struct ifnet *ifp; 1280 1281 if (lvl < 0) 1282 lvl = 0; 1283 else if (lvl >= NBGE_RX_THRESH) 1284 lvl = NBGE_RX_THRESH - 1; 1285 1286 /* 1287 * Now search all the interfaces for this name/number 1288 */ 1289 int s = pserialize_read_enter(); 1290 IFNET_READER_FOREACH(ifp) { 1291 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1292 continue; 1293 /* We got a match: update if doing auto-threshold-tuning */ 1294 if (bge_auto_thresh) 1295 bge_set_thresh(ifp, lvl); 1296 } 1297 pserialize_read_exit(s); 1298 } 1299 1300 /* 1301 * Handle events that have triggered interrupts. 1302 */ 1303 static void 1304 bge_handle_events(struct bge_softc *sc) 1305 { 1306 1307 return; 1308 } 1309 1310 /* 1311 * Memory management for jumbo frames. 1312 */ 1313 1314 static int 1315 bge_alloc_jumbo_mem(struct bge_softc *sc) 1316 { 1317 char *ptr, *kva; 1318 int i, rseg, state, error; 1319 struct bge_jpool_entry *entry; 1320 1321 state = error = 0; 1322 1323 /* Grab a big chunk o' storage. */ 1324 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1325 &sc->bge_cdata.bge_rx_jumbo_seg, 1, &rseg, BUS_DMA_WAITOK)) { 1326 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1327 return ENOBUFS; 1328 } 1329 1330 state = 1; 1331 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1332 rseg, BGE_JMEM, (void **)&kva, BUS_DMA_WAITOK)) { 1333 aprint_error_dev(sc->bge_dev, 1334 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1335 error = ENOBUFS; 1336 goto out; 1337 } 1338 1339 state = 2; 1340 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1341 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_jumbo_map)) { 1342 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1343 error = ENOBUFS; 1344 goto out; 1345 } 1346 1347 state = 3; 1348 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1349 kva, BGE_JMEM, NULL, BUS_DMA_WAITOK)) { 1350 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1351 error = ENOBUFS; 1352 goto out; 1353 } 1354 1355 state = 4; 1356 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1357 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1358 1359 SLIST_INIT(&sc->bge_jfree_listhead); 1360 SLIST_INIT(&sc->bge_jinuse_listhead); 1361 1362 /* 1363 * Now divide it up into 9K pieces and save the addresses 1364 * in an array. 1365 */ 1366 ptr = sc->bge_cdata.bge_jumbo_buf; 1367 for (i = 0; i < BGE_JSLOTS; i++) { 1368 sc->bge_cdata.bge_jslots[i] = ptr; 1369 ptr += BGE_JLEN; 1370 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 1371 entry->slot = i; 1372 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1373 entry, jpool_entries); 1374 } 1375 out: 1376 if (error != 0) { 1377 switch (state) { 1378 case 4: 1379 bus_dmamap_unload(sc->bge_dmatag, 1380 sc->bge_cdata.bge_rx_jumbo_map); 1381 /* FALLTHROUGH */ 1382 case 3: 1383 bus_dmamap_destroy(sc->bge_dmatag, 1384 sc->bge_cdata.bge_rx_jumbo_map); 1385 /* FALLTHROUGH */ 1386 case 2: 1387 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1388 /* FALLTHROUGH */ 1389 case 1: 1390 bus_dmamem_free(sc->bge_dmatag, 1391 &sc->bge_cdata.bge_rx_jumbo_seg, rseg); 1392 break; 1393 default: 1394 break; 1395 } 1396 } 1397 1398 return error; 1399 } 1400 1401 static void 1402 bge_free_jumbo_mem(struct bge_softc *sc) 1403 { 1404 struct bge_jpool_entry *entry, *tmp; 1405 1406 KASSERT(SLIST_EMPTY(&sc->bge_jinuse_listhead)); 1407 1408 SLIST_FOREACH_SAFE(entry, &sc->bge_jfree_listhead, jpool_entries, tmp) { 1409 kmem_free(entry, sizeof(*entry)); 1410 } 1411 1412 bus_dmamap_unload(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1413 1414 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1415 1416 bus_dmamem_unmap(sc->bge_dmatag, sc->bge_cdata.bge_jumbo_buf, BGE_JMEM); 1417 1418 bus_dmamem_free(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1); 1419 } 1420 1421 /* 1422 * Allocate a jumbo buffer. 1423 */ 1424 static void * 1425 bge_jalloc(struct bge_softc *sc) 1426 { 1427 struct bge_jpool_entry *entry; 1428 1429 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1430 1431 if (entry == NULL) { 1432 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1433 return NULL; 1434 } 1435 1436 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1437 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1438 return sc->bge_cdata.bge_jslots[entry->slot]; 1439 } 1440 1441 /* 1442 * Release a jumbo buffer. 1443 */ 1444 static void 1445 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1446 { 1447 struct bge_jpool_entry *entry; 1448 struct bge_softc * const sc = arg; 1449 1450 if (sc == NULL) 1451 panic("bge_jfree: can't find softc pointer!"); 1452 1453 /* calculate the slot this buffer belongs to */ 1454 int i = ((char *)buf - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1455 1456 if (i < 0 || i >= BGE_JSLOTS) 1457 panic("bge_jfree: asked to free buffer that we don't manage!"); 1458 1459 mutex_enter(sc->sc_core_lock); 1460 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1461 if (entry == NULL) 1462 panic("bge_jfree: buffer not in use!"); 1463 entry->slot = i; 1464 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1465 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1466 mutex_exit(sc->sc_core_lock); 1467 1468 if (__predict_true(m != NULL)) 1469 pool_cache_put(mb_cache, m); 1470 } 1471 1472 1473 /* 1474 * Initialize a standard receive ring descriptor. 1475 */ 1476 static int 1477 bge_newbuf_std(struct bge_softc *sc, int i) 1478 { 1479 const bus_dmamap_t dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1480 struct mbuf *m; 1481 1482 MGETHDR(m, M_DONTWAIT, MT_DATA); 1483 if (m == NULL) 1484 return ENOBUFS; 1485 1486 MCLGET(m, M_DONTWAIT); 1487 if (!(m->m_flags & M_EXT)) { 1488 m_freem(m); 1489 return ENOBUFS; 1490 } 1491 m->m_len = m->m_pkthdr.len = MCLBYTES; 1492 1493 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1494 m_adj(m, ETHER_ALIGN); 1495 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m, 1496 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1497 m_freem(m); 1498 return ENOBUFS; 1499 } 1500 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1501 BUS_DMASYNC_PREREAD); 1502 sc->bge_cdata.bge_rx_std_chain[i] = m; 1503 1504 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1505 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1506 i * sizeof(struct bge_rx_bd), 1507 sizeof(struct bge_rx_bd), 1508 BUS_DMASYNC_POSTWRITE); 1509 1510 struct bge_rx_bd * const r = &sc->bge_rdata->bge_rx_std_ring[i]; 1511 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1512 r->bge_flags = BGE_RXBDFLAG_END; 1513 r->bge_len = m->m_len; 1514 r->bge_idx = i; 1515 1516 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1517 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1518 i * sizeof(struct bge_rx_bd), 1519 sizeof(struct bge_rx_bd), 1520 BUS_DMASYNC_PREWRITE); 1521 1522 sc->bge_std_cnt++; 1523 1524 return 0; 1525 } 1526 1527 /* 1528 * Initialize a jumbo receive ring descriptor. This allocates 1529 * a jumbo buffer from the pool managed internally by the driver. 1530 */ 1531 static int 1532 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1533 { 1534 struct mbuf *m_new = NULL; 1535 struct bge_rx_bd *r; 1536 void *buf = NULL; 1537 1538 if (m == NULL) { 1539 1540 /* Allocate the mbuf. */ 1541 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1542 if (m_new == NULL) 1543 return ENOBUFS; 1544 1545 /* Allocate the jumbo buffer */ 1546 buf = bge_jalloc(sc); 1547 if (buf == NULL) { 1548 m_freem(m_new); 1549 aprint_error_dev(sc->bge_dev, 1550 "jumbo allocation failed -- packet dropped!\n"); 1551 return ENOBUFS; 1552 } 1553 1554 /* Attach the buffer to the mbuf. */ 1555 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1556 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1557 bge_jfree, sc); 1558 m_new->m_flags |= M_EXT_RW; 1559 } else { 1560 m_new = m; 1561 buf = m_new->m_data = m_new->m_ext.ext_buf; 1562 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1563 } 1564 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1565 m_adj(m_new, ETHER_ALIGN); 1566 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1567 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1568 BGE_JLEN, BUS_DMASYNC_PREREAD); 1569 1570 /* Set up the descriptor. */ 1571 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1572 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1573 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1574 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1575 r->bge_len = m_new->m_len; 1576 r->bge_idx = i; 1577 1578 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1579 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1580 i * sizeof(struct bge_rx_bd), 1581 sizeof(struct bge_rx_bd), 1582 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1583 1584 return 0; 1585 } 1586 1587 static int 1588 bge_init_rx_ring_std(struct bge_softc *sc) 1589 { 1590 bus_dmamap_t dmamap; 1591 int error = 0; 1592 u_int i; 1593 1594 if (sc->bge_flags & BGEF_RXRING_VALID) 1595 return 0; 1596 1597 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1598 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1599 MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dmamap); 1600 if (error) 1601 goto uncreate; 1602 1603 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1604 memset(&sc->bge_rdata->bge_rx_std_ring[i], 0, 1605 sizeof(struct bge_rx_bd)); 1606 } 1607 1608 sc->bge_std = i - 1; 1609 sc->bge_std_cnt = 0; 1610 bge_fill_rx_ring_std(sc); 1611 1612 sc->bge_flags |= BGEF_RXRING_VALID; 1613 1614 return 0; 1615 1616 uncreate: 1617 while (--i) { 1618 bus_dmamap_destroy(sc->bge_dmatag, 1619 sc->bge_cdata.bge_rx_std_map[i]); 1620 } 1621 return error; 1622 } 1623 1624 static void 1625 bge_fill_rx_ring_std(struct bge_softc *sc) 1626 { 1627 int i = sc->bge_std; 1628 bool post = false; 1629 1630 while (sc->bge_std_cnt < BGE_STD_RX_RING_CNT) { 1631 BGE_INC(i, BGE_STD_RX_RING_CNT); 1632 1633 if (bge_newbuf_std(sc, i) != 0) 1634 break; 1635 1636 sc->bge_std = i; 1637 post = true; 1638 } 1639 1640 if (post) 1641 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1642 } 1643 1644 1645 static void 1646 bge_free_rx_ring_std(struct bge_softc *sc) 1647 { 1648 1649 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1650 return; 1651 1652 for (u_int i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1653 const bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i]; 1654 struct mbuf * const m = sc->bge_cdata.bge_rx_std_chain[i]; 1655 if (m != NULL) { 1656 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 1657 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1658 bus_dmamap_unload(sc->bge_dmatag, dmap); 1659 m_freem(m); 1660 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1661 } 1662 bus_dmamap_destroy(sc->bge_dmatag, 1663 sc->bge_cdata.bge_rx_std_map[i]); 1664 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1665 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1666 sizeof(struct bge_rx_bd)); 1667 } 1668 1669 sc->bge_flags &= ~BGEF_RXRING_VALID; 1670 } 1671 1672 static int 1673 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1674 { 1675 int i; 1676 volatile struct bge_rcb *rcb; 1677 1678 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1679 return 0; 1680 1681 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1682 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1683 return ENOBUFS; 1684 } 1685 1686 sc->bge_jumbo = i - 1; 1687 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1688 1689 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1690 rcb->bge_maxlen_flags = 0; 1691 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1692 1693 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1694 1695 return 0; 1696 } 1697 1698 static void 1699 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1700 { 1701 int i; 1702 1703 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1704 return; 1705 1706 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1707 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1708 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1709 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1710 } 1711 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1712 sizeof(struct bge_rx_bd)); 1713 } 1714 1715 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1716 } 1717 1718 static void 1719 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1720 { 1721 int i; 1722 struct txdmamap_pool_entry *dma; 1723 1724 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1725 return; 1726 1727 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1728 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1729 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1730 sc->bge_cdata.bge_tx_chain[i] = NULL; 1731 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1732 link); 1733 sc->txdma[i] = 0; 1734 } 1735 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1736 sizeof(struct bge_tx_bd)); 1737 } 1738 1739 if (disable) { 1740 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1741 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1742 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1743 if (sc->bge_dma64) { 1744 bus_dmamap_destroy(sc->bge_dmatag32, 1745 dma->dmamap32); 1746 } 1747 kmem_free(dma, sizeof(*dma)); 1748 } 1749 SLIST_INIT(&sc->txdma_list); 1750 } 1751 1752 sc->bge_flags &= ~BGEF_TXRING_VALID; 1753 } 1754 1755 static int 1756 bge_init_tx_ring(struct bge_softc *sc) 1757 { 1758 struct ifnet * const ifp = &sc->ethercom.ec_if; 1759 int i; 1760 bus_dmamap_t dmamap, dmamap32; 1761 bus_size_t maxsegsz; 1762 struct txdmamap_pool_entry *dma; 1763 1764 if (sc->bge_flags & BGEF_TXRING_VALID) 1765 return 0; 1766 1767 sc->bge_txcnt = 0; 1768 sc->bge_tx_saved_considx = 0; 1769 1770 /* Initialize transmit producer index for host-memory send ring. */ 1771 sc->bge_tx_prodidx = 0; 1772 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1773 /* 5700 b2 errata */ 1774 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1775 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1776 1777 /* NIC-memory send ring not used; initialize to zero. */ 1778 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1779 /* 5700 b2 errata */ 1780 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1781 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1782 1783 /* Limit DMA segment size for some chips */ 1784 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1785 (ifp->if_mtu <= ETHERMTU)) 1786 maxsegsz = 2048; 1787 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1788 maxsegsz = 4096; 1789 else 1790 maxsegsz = ETHER_MAX_LEN_JUMBO; 1791 1792 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1793 goto alloc_done; 1794 1795 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1796 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1797 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1798 &dmamap)) 1799 return ENOBUFS; 1800 if (dmamap == NULL) 1801 panic("dmamap NULL in bge_init_tx_ring"); 1802 if (sc->bge_dma64) { 1803 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1804 BGE_NTXSEG, maxsegsz, 0, 1805 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1806 &dmamap32)) { 1807 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1808 return ENOBUFS; 1809 } 1810 if (dmamap32 == NULL) 1811 panic("dmamap32 NULL in bge_init_tx_ring"); 1812 } else 1813 dmamap32 = dmamap; 1814 dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP); 1815 if (dma == NULL) { 1816 aprint_error_dev(sc->bge_dev, 1817 "can't alloc txdmamap_pool_entry\n"); 1818 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1819 if (sc->bge_dma64) 1820 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1821 return ENOMEM; 1822 } 1823 dma->dmamap = dmamap; 1824 dma->dmamap32 = dmamap32; 1825 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1826 } 1827 alloc_done: 1828 sc->bge_flags |= BGEF_TXRING_VALID; 1829 1830 return 0; 1831 } 1832 1833 static void 1834 bge_setmulti(struct bge_softc *sc) 1835 { 1836 struct ethercom * const ec = &sc->ethercom; 1837 struct ether_multi *enm; 1838 struct ether_multistep step; 1839 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1840 uint32_t h; 1841 int i; 1842 1843 KASSERT(mutex_owned(sc->sc_core_lock)); 1844 if (sc->bge_if_flags & IFF_PROMISC) 1845 goto allmulti; 1846 1847 /* Now program new ones. */ 1848 ETHER_LOCK(ec); 1849 ETHER_FIRST_MULTI(step, ec, enm); 1850 while (enm != NULL) { 1851 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1852 /* 1853 * We must listen to a range of multicast addresses. 1854 * For now, just accept all multicasts, rather than 1855 * trying to set only those filter bits needed to match 1856 * the range. (At this time, the only use of address 1857 * ranges is for IP multicast routing, for which the 1858 * range is big enough to require all bits set.) 1859 */ 1860 ETHER_UNLOCK(ec); 1861 goto allmulti; 1862 } 1863 1864 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1865 1866 /* Just want the 7 least-significant bits. */ 1867 h &= 0x7f; 1868 1869 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1870 ETHER_NEXT_MULTI(step, enm); 1871 } 1872 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1873 ETHER_UNLOCK(ec); 1874 1875 goto setit; 1876 1877 allmulti: 1878 ETHER_LOCK(ec); 1879 ec->ec_flags |= ETHER_F_ALLMULTI; 1880 ETHER_UNLOCK(ec); 1881 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1882 1883 setit: 1884 for (i = 0; i < 4; i++) 1885 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1886 } 1887 1888 static void 1889 bge_sig_pre_reset(struct bge_softc *sc, int type) 1890 { 1891 1892 /* 1893 * Some chips don't like this so only do this if ASF is enabled 1894 */ 1895 if (sc->bge_asf_mode) 1896 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1897 1898 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1899 switch (type) { 1900 case BGE_RESET_START: 1901 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1902 BGE_FW_DRV_STATE_START); 1903 break; 1904 case BGE_RESET_SHUTDOWN: 1905 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1906 BGE_FW_DRV_STATE_UNLOAD); 1907 break; 1908 case BGE_RESET_SUSPEND: 1909 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1910 BGE_FW_DRV_STATE_SUSPEND); 1911 break; 1912 } 1913 } 1914 1915 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1916 bge_ape_driver_state_change(sc, type); 1917 } 1918 1919 static void 1920 bge_sig_post_reset(struct bge_softc *sc, int type) 1921 { 1922 1923 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1924 switch (type) { 1925 case BGE_RESET_START: 1926 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1927 BGE_FW_DRV_STATE_START_DONE); 1928 /* START DONE */ 1929 break; 1930 case BGE_RESET_SHUTDOWN: 1931 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1932 BGE_FW_DRV_STATE_UNLOAD_DONE); 1933 break; 1934 } 1935 } 1936 1937 if (type == BGE_RESET_SHUTDOWN) 1938 bge_ape_driver_state_change(sc, type); 1939 } 1940 1941 static void 1942 bge_sig_legacy(struct bge_softc *sc, int type) 1943 { 1944 1945 if (sc->bge_asf_mode) { 1946 switch (type) { 1947 case BGE_RESET_START: 1948 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1949 BGE_FW_DRV_STATE_START); 1950 break; 1951 case BGE_RESET_SHUTDOWN: 1952 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1953 BGE_FW_DRV_STATE_UNLOAD); 1954 break; 1955 } 1956 } 1957 } 1958 1959 static void 1960 bge_wait_for_event_ack(struct bge_softc *sc) 1961 { 1962 int i; 1963 1964 /* wait up to 2500usec */ 1965 for (i = 0; i < 250; i++) { 1966 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1967 BGE_RX_CPU_DRV_EVENT)) 1968 break; 1969 DELAY(10); 1970 } 1971 } 1972 1973 static void 1974 bge_stop_fw(struct bge_softc *sc) 1975 { 1976 1977 if (sc->bge_asf_mode) { 1978 bge_wait_for_event_ack(sc); 1979 1980 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1981 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1982 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1983 1984 bge_wait_for_event_ack(sc); 1985 } 1986 } 1987 1988 static int 1989 bge_poll_fw(struct bge_softc *sc) 1990 { 1991 uint32_t val; 1992 int i; 1993 1994 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1995 for (i = 0; i < BGE_TIMEOUT; i++) { 1996 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1997 if (val & BGE_VCPU_STATUS_INIT_DONE) 1998 break; 1999 DELAY(100); 2000 } 2001 if (i >= BGE_TIMEOUT) { 2002 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2003 return -1; 2004 } 2005 } else { 2006 /* 2007 * Poll the value location we just wrote until 2008 * we see the 1's complement of the magic number. 2009 * This indicates that the firmware initialization 2010 * is complete. 2011 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2012 */ 2013 for (i = 0; i < BGE_TIMEOUT; i++) { 2014 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2015 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2016 break; 2017 DELAY(10); 2018 } 2019 2020 if ((i >= BGE_TIMEOUT) 2021 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2022 aprint_error_dev(sc->bge_dev, 2023 "firmware handshake timed out, val = %x\n", val); 2024 return -1; 2025 } 2026 } 2027 2028 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2029 /* tg3 says we have to wait extra time */ 2030 delay(10 * 1000); 2031 } 2032 2033 return 0; 2034 } 2035 2036 int 2037 bge_phy_addr(struct bge_softc *sc) 2038 { 2039 struct pci_attach_args *pa = &(sc->bge_pa); 2040 int phy_addr = 1; 2041 2042 /* 2043 * PHY address mapping for various devices. 2044 * 2045 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2046 * ---------+-------+-------+-------+-------+ 2047 * BCM57XX | 1 | X | X | X | 2048 * BCM5704 | 1 | X | 1 | X | 2049 * BCM5717 | 1 | 8 | 2 | 9 | 2050 * BCM5719 | 1 | 8 | 2 | 9 | 2051 * BCM5720 | 1 | 8 | 2 | 9 | 2052 * 2053 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2054 * ---------+-------+-------+-------+-------+ 2055 * BCM57XX | X | X | X | X | 2056 * BCM5704 | X | X | X | X | 2057 * BCM5717 | X | X | X | X | 2058 * BCM5719 | 3 | 10 | 4 | 11 | 2059 * BCM5720 | X | X | X | X | 2060 * 2061 * Other addresses may respond but they are not 2062 * IEEE compliant PHYs and should be ignored. 2063 */ 2064 switch (BGE_ASICREV(sc->bge_chipid)) { 2065 case BGE_ASICREV_BCM5717: 2066 case BGE_ASICREV_BCM5719: 2067 case BGE_ASICREV_BCM5720: 2068 phy_addr = pa->pa_function; 2069 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2070 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2071 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2072 } else { 2073 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2074 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2075 } 2076 } 2077 2078 return phy_addr; 2079 } 2080 2081 /* 2082 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2083 * self-test results. 2084 */ 2085 static int 2086 bge_chipinit(struct bge_softc *sc) 2087 { 2088 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2089 int i; 2090 2091 /* Set endianness before we access any non-PCI registers. */ 2092 misc_ctl = BGE_INIT; 2093 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2094 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2095 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2096 misc_ctl); 2097 2098 /* 2099 * Clear the MAC statistics block in the NIC's 2100 * internal memory. 2101 */ 2102 for (i = BGE_STATS_BLOCK; 2103 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2104 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2105 2106 for (i = BGE_STATUS_BLOCK; 2107 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2108 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2109 2110 /* 5717 workaround from tg3 */ 2111 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2112 /* Save */ 2113 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2114 2115 /* Temporary modify MODE_CTL to control TLP */ 2116 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2117 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2118 2119 /* Control TLP */ 2120 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2121 BGE_TLP_PHYCTL1); 2122 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2123 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2124 2125 /* Restore */ 2126 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2127 } 2128 2129 if (BGE_IS_57765_FAMILY(sc)) { 2130 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2131 /* Save */ 2132 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2133 2134 /* Temporary modify MODE_CTL to control TLP */ 2135 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2136 CSR_WRITE_4(sc, BGE_MODE_CTL, 2137 reg | BGE_MODECTL_PCIE_TLPADDR1); 2138 2139 /* Control TLP */ 2140 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2141 BGE_TLP_PHYCTL5); 2142 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2143 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2144 2145 /* Restore */ 2146 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2147 } 2148 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2149 /* 2150 * For the 57766 and non Ax versions of 57765, bootcode 2151 * needs to setup the PCIE Fast Training Sequence (FTS) 2152 * value to prevent transmit hangs. 2153 */ 2154 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2155 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2156 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2157 2158 /* Save */ 2159 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2160 2161 /* Temporary modify MODE_CTL to control TLP */ 2162 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2163 CSR_WRITE_4(sc, BGE_MODE_CTL, 2164 reg | BGE_MODECTL_PCIE_TLPADDR0); 2165 2166 /* Control TLP */ 2167 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2168 BGE_TLP_FTSMAX); 2169 reg &= ~BGE_TLP_FTSMAX_MSK; 2170 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2171 reg | BGE_TLP_FTSMAX_VAL); 2172 2173 /* Restore */ 2174 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2175 } 2176 2177 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2178 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2179 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2180 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2181 } 2182 2183 /* Set up the PCI DMA control register. */ 2184 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2185 if (sc->bge_flags & BGEF_PCIE) { 2186 /* Read watermark not used, 128 bytes for write. */ 2187 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2188 device_xname(sc->bge_dev))); 2189 if (sc->bge_mps >= 256) 2190 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2191 else 2192 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2193 } else if (sc->bge_flags & BGEF_PCIX) { 2194 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2195 device_xname(sc->bge_dev))); 2196 /* PCI-X bus */ 2197 if (BGE_IS_5714_FAMILY(sc)) { 2198 /* 256 bytes for read and write. */ 2199 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2200 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2201 2202 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2203 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2204 else 2205 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2206 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2207 /* 2208 * In the BCM5703, the DMA read watermark should 2209 * be set to less than or equal to the maximum 2210 * memory read byte count of the PCI-X command 2211 * register. 2212 */ 2213 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2214 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2215 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2216 /* 1536 bytes for read, 384 bytes for write. */ 2217 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2218 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2219 } else { 2220 /* 384 bytes for read and write. */ 2221 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2222 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2223 (0x0F); 2224 } 2225 2226 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2227 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2228 uint32_t tmp; 2229 2230 /* Set ONEDMA_ATONCE for hardware workaround. */ 2231 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2232 if (tmp == 6 || tmp == 7) 2233 dma_rw_ctl |= 2234 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2235 2236 /* Set PCI-X DMA write workaround. */ 2237 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2238 } 2239 } else { 2240 /* Conventional PCI bus: 256 bytes for read and write. */ 2241 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2242 device_xname(sc->bge_dev))); 2243 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2244 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2245 2246 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2247 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2248 dma_rw_ctl |= 0x0F; 2249 } 2250 2251 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2252 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2253 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2254 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2255 2256 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2257 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2258 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2259 2260 if (BGE_IS_57765_PLUS(sc)) { 2261 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2262 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2263 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2264 2265 /* 2266 * Enable HW workaround for controllers that misinterpret 2267 * a status tag update and leave interrupts permanently 2268 * disabled. 2269 */ 2270 if (!BGE_IS_57765_FAMILY(sc) && 2271 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2272 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2273 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2274 } 2275 2276 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2277 dma_rw_ctl); 2278 2279 /* 2280 * Set up general mode register. 2281 */ 2282 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2283 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2284 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2285 /* Retain Host-2-BMC settings written by APE firmware. */ 2286 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2287 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2288 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2289 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2290 } 2291 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2292 BGE_MODECTL_TX_NO_PHDR_CSUM; 2293 2294 /* 2295 * BCM5701 B5 have a bug causing data corruption when using 2296 * 64-bit DMA reads, which can be terminated early and then 2297 * completed later as 32-bit accesses, in combination with 2298 * certain bridges. 2299 */ 2300 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2301 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2302 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2303 2304 /* 2305 * Tell the firmware the driver is running 2306 */ 2307 if (sc->bge_asf_mode & ASF_STACKUP) 2308 mode_ctl |= BGE_MODECTL_STACKUP; 2309 2310 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2311 2312 /* 2313 * Disable memory write invalidate. Apparently it is not supported 2314 * properly by these devices. 2315 */ 2316 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2317 PCI_COMMAND_INVALIDATE_ENABLE); 2318 2319 #ifdef __brokenalpha__ 2320 /* 2321 * Must insure that we do not cross an 8K (bytes) boundary 2322 * for DMA reads. Our highest limit is 1K bytes. This is a 2323 * restriction on some ALPHA platforms with early revision 2324 * 21174 PCI chipsets, such as the AlphaPC 164lx 2325 */ 2326 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2327 #endif 2328 2329 /* Set the timer prescaler (always 66MHz) */ 2330 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2331 2332 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2333 DELAY(40); /* XXX */ 2334 2335 /* Put PHY into ready state */ 2336 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2337 DELAY(40); 2338 } 2339 2340 return 0; 2341 } 2342 2343 static int 2344 bge_blockinit(struct bge_softc *sc) 2345 { 2346 volatile struct bge_rcb *rcb; 2347 bus_size_t rcb_addr; 2348 struct ifnet * const ifp = &sc->ethercom.ec_if; 2349 bge_hostaddr taddr; 2350 uint32_t dmactl, rdmareg, mimode, val; 2351 int i, limit; 2352 2353 /* 2354 * Initialize the memory window pointer register so that 2355 * we can access the first 32K of internal NIC RAM. This will 2356 * allow us to set up the TX send ring RCBs and the RX return 2357 * ring RCBs, plus other things which live in NIC memory. 2358 */ 2359 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2360 2361 if (!BGE_IS_5705_PLUS(sc)) { 2362 /* 57XX step 33 */ 2363 /* Configure mbuf memory pool */ 2364 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2365 2366 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2367 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2368 else 2369 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2370 2371 /* 57XX step 34 */ 2372 /* Configure DMA resource pool */ 2373 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2374 BGE_DMA_DESCRIPTORS); 2375 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2376 } 2377 2378 /* 5718 step 11, 57XX step 35 */ 2379 /* 2380 * Configure mbuf pool watermarks. New broadcom docs strongly 2381 * recommend these. 2382 */ 2383 if (BGE_IS_5717_PLUS(sc)) { 2384 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2385 if (ifp->if_mtu > ETHERMTU) { 2386 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2387 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2388 } else { 2389 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2390 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2391 } 2392 } else if (BGE_IS_5705_PLUS(sc)) { 2393 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2394 2395 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2396 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2397 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2398 } else { 2399 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2400 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2401 } 2402 } else { 2403 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2404 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2405 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2406 } 2407 2408 /* 57XX step 36 */ 2409 /* Configure DMA resource watermarks */ 2410 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2411 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2412 2413 /* 5718 step 13, 57XX step 38 */ 2414 /* Enable buffer manager */ 2415 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2416 /* 2417 * Change the arbitration algorithm of TXMBUF read request to 2418 * round-robin instead of priority based for BCM5719. When 2419 * TXFIFO is almost empty, RDMA will hold its request until 2420 * TXFIFO is not almost empty. 2421 */ 2422 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2423 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2424 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2425 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2426 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2427 val |= BGE_BMANMODE_LOMBUF_ATTN; 2428 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2429 2430 /* 57XX step 39 */ 2431 /* Poll for buffer manager start indication */ 2432 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2433 DELAY(10); 2434 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2435 break; 2436 } 2437 2438 if (i == BGE_TIMEOUT * 2) { 2439 aprint_error_dev(sc->bge_dev, 2440 "buffer manager failed to start\n"); 2441 return ENXIO; 2442 } 2443 2444 /* 57XX step 40 */ 2445 /* Enable flow-through queues */ 2446 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2447 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2448 2449 /* Wait until queue initialization is complete */ 2450 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2451 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2452 break; 2453 DELAY(10); 2454 } 2455 2456 if (i == BGE_TIMEOUT * 2) { 2457 aprint_error_dev(sc->bge_dev, 2458 "flow-through queue init failed\n"); 2459 return ENXIO; 2460 } 2461 2462 /* 2463 * Summary of rings supported by the controller: 2464 * 2465 * Standard Receive Producer Ring 2466 * - This ring is used to feed receive buffers for "standard" 2467 * sized frames (typically 1536 bytes) to the controller. 2468 * 2469 * Jumbo Receive Producer Ring 2470 * - This ring is used to feed receive buffers for jumbo sized 2471 * frames (i.e. anything bigger than the "standard" frames) 2472 * to the controller. 2473 * 2474 * Mini Receive Producer Ring 2475 * - This ring is used to feed receive buffers for "mini" 2476 * sized frames to the controller. 2477 * - This feature required external memory for the controller 2478 * but was never used in a production system. Should always 2479 * be disabled. 2480 * 2481 * Receive Return Ring 2482 * - After the controller has placed an incoming frame into a 2483 * receive buffer that buffer is moved into a receive return 2484 * ring. The driver is then responsible to passing the 2485 * buffer up to the stack. Many versions of the controller 2486 * support multiple RR rings. 2487 * 2488 * Send Ring 2489 * - This ring is used for outgoing frames. Many versions of 2490 * the controller support multiple send rings. 2491 */ 2492 2493 /* 5718 step 15, 57XX step 41 */ 2494 /* Initialize the standard RX ring control block */ 2495 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2496 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2497 /* 5718 step 16 */ 2498 if (BGE_IS_57765_PLUS(sc)) { 2499 /* 2500 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2501 * Bits 15-2 : Maximum RX frame size 2502 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2503 * Bit 0 : Reserved 2504 */ 2505 rcb->bge_maxlen_flags = 2506 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2507 } else if (BGE_IS_5705_PLUS(sc)) { 2508 /* 2509 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2510 * Bits 15-2 : Reserved (should be 0) 2511 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2512 * Bit 0 : Reserved 2513 */ 2514 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2515 } else { 2516 /* 2517 * Ring size is always XXX entries 2518 * Bits 31-16: Maximum RX frame size 2519 * Bits 15-2 : Reserved (should be 0) 2520 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2521 * Bit 0 : Reserved 2522 */ 2523 rcb->bge_maxlen_flags = 2524 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2525 } 2526 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2527 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2528 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2529 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2530 else 2531 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2532 /* Write the standard receive producer ring control block. */ 2533 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2534 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2535 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2537 2538 /* Reset the standard receive producer ring producer index. */ 2539 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2540 2541 /* 57XX step 42 */ 2542 /* 2543 * Initialize the jumbo RX ring control block 2544 * We set the 'ring disabled' bit in the flags 2545 * field until we're actually ready to start 2546 * using this ring (i.e. once we set the MTU 2547 * high enough to require it). 2548 */ 2549 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2550 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2551 BGE_HOSTADDR(rcb->bge_hostaddr, 2552 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2553 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2554 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2555 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2556 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2557 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2558 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2559 else 2560 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2561 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2562 rcb->bge_hostaddr.bge_addr_hi); 2563 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2564 rcb->bge_hostaddr.bge_addr_lo); 2565 /* Program the jumbo receive producer ring RCB parameters. */ 2566 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2567 rcb->bge_maxlen_flags); 2568 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2569 /* Reset the jumbo receive producer ring producer index. */ 2570 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2571 } 2572 2573 /* 57XX step 43 */ 2574 /* Disable the mini receive producer ring RCB. */ 2575 if (BGE_IS_5700_FAMILY(sc)) { 2576 /* Set up dummy disabled mini ring RCB */ 2577 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2578 rcb->bge_maxlen_flags = 2579 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2580 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2581 rcb->bge_maxlen_flags); 2582 /* Reset the mini receive producer ring producer index. */ 2583 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2584 2585 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2586 offsetof(struct bge_ring_data, bge_info), 2587 sizeof(struct bge_gib), 2588 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2589 } 2590 2591 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2592 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2593 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2594 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2595 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2596 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2597 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2598 } 2599 /* 5718 step 14, 57XX step 44 */ 2600 /* 2601 * The BD ring replenish thresholds control how often the 2602 * hardware fetches new BD's from the producer rings in host 2603 * memory. Setting the value too low on a busy system can 2604 * starve the hardware and recue the throughpout. 2605 * 2606 * Set the BD ring replenish thresholds. The recommended 2607 * values are 1/8th the number of descriptors allocated to 2608 * each ring, but since we try to avoid filling the entire 2609 * ring we set these to the minimal value of 8. This needs to 2610 * be done on several of the supported chip revisions anyway, 2611 * to work around HW bugs. 2612 */ 2613 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2614 if (BGE_IS_JUMBO_CAPABLE(sc)) 2615 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2616 2617 /* 5718 step 18 */ 2618 if (BGE_IS_5717_PLUS(sc)) { 2619 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2620 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2621 } 2622 2623 /* 57XX step 45 */ 2624 /* 2625 * Disable all send rings by setting the 'ring disabled' bit 2626 * in the flags field of all the TX send ring control blocks, 2627 * located in NIC memory. 2628 */ 2629 if (BGE_IS_5700_FAMILY(sc)) { 2630 /* 5700 to 5704 had 16 send rings. */ 2631 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2632 } else if (BGE_IS_5717_PLUS(sc)) { 2633 limit = BGE_TX_RINGS_5717_MAX; 2634 } else if (BGE_IS_57765_FAMILY(sc) || 2635 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2636 limit = BGE_TX_RINGS_57765_MAX; 2637 } else 2638 limit = 1; 2639 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2640 for (i = 0; i < limit; i++) { 2641 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2642 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2643 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2644 rcb_addr += sizeof(struct bge_rcb); 2645 } 2646 2647 /* 57XX step 46 and 47 */ 2648 /* Configure send ring RCB 0 (we use only the first ring) */ 2649 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2650 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2651 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2652 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2653 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2654 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2655 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2656 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2657 else 2658 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2659 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2660 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2661 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2662 2663 /* 57XX step 48 */ 2664 /* 2665 * Disable all receive return rings by setting the 2666 * 'ring diabled' bit in the flags field of all the receive 2667 * return ring control blocks, located in NIC memory. 2668 */ 2669 if (BGE_IS_5717_PLUS(sc)) { 2670 /* Should be 17, use 16 until we get an SRAM map. */ 2671 limit = 16; 2672 } else if (BGE_IS_5700_FAMILY(sc)) 2673 limit = BGE_RX_RINGS_MAX; 2674 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2675 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2676 BGE_IS_57765_FAMILY(sc)) 2677 limit = 4; 2678 else 2679 limit = 1; 2680 /* Disable all receive return rings */ 2681 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2682 for (i = 0; i < limit; i++) { 2683 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2684 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2685 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2686 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2687 BGE_RCB_FLAG_RING_DISABLED)); 2688 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2689 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2690 (i * (sizeof(uint64_t))), 0); 2691 rcb_addr += sizeof(struct bge_rcb); 2692 } 2693 2694 /* 57XX step 49 */ 2695 /* 2696 * Set up receive return ring 0. Note that the NIC address 2697 * for RX return rings is 0x0. The return rings live entirely 2698 * within the host, so the nicaddr field in the RCB isn't used. 2699 */ 2700 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2701 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2702 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2703 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2704 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2705 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2706 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2707 2708 /* 5718 step 24, 57XX step 53 */ 2709 /* Set random backoff seed for TX */ 2710 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2711 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2712 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2713 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2714 BGE_TX_BACKOFF_SEED_MASK); 2715 2716 /* 5718 step 26, 57XX step 55 */ 2717 /* Set inter-packet gap */ 2718 val = 0x2620; 2719 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2720 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2721 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2722 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2723 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2724 2725 /* 5718 step 27, 57XX step 56 */ 2726 /* 2727 * Specify which ring to use for packets that don't match 2728 * any RX rules. 2729 */ 2730 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2731 2732 /* 5718 step 28, 57XX step 57 */ 2733 /* 2734 * Configure number of RX lists. One interrupt distribution 2735 * list, sixteen active lists, one bad frames class. 2736 */ 2737 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2738 2739 /* 5718 step 29, 57XX step 58 */ 2740 /* Inialize RX list placement stats mask. */ 2741 if (BGE_IS_575X_PLUS(sc)) { 2742 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2743 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2744 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2745 } else 2746 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2747 2748 /* 5718 step 30, 57XX step 59 */ 2749 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2750 2751 /* 5718 step 33, 57XX step 62 */ 2752 /* Disable host coalescing until we get it set up */ 2753 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2754 2755 /* 5718 step 34, 57XX step 63 */ 2756 /* Poll to make sure it's shut down. */ 2757 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2758 DELAY(10); 2759 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2760 break; 2761 } 2762 2763 if (i == BGE_TIMEOUT * 2) { 2764 aprint_error_dev(sc->bge_dev, 2765 "host coalescing engine failed to idle\n"); 2766 return ENXIO; 2767 } 2768 2769 /* 5718 step 35, 36, 37 */ 2770 /* Set up host coalescing defaults */ 2771 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2772 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2773 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2774 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2775 if (!(BGE_IS_5705_PLUS(sc))) { 2776 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2777 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2778 } 2779 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2780 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2781 2782 /* Set up address of statistics block */ 2783 if (BGE_IS_5700_FAMILY(sc)) { 2784 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2785 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2786 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2787 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2788 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2789 } 2790 2791 /* 5718 step 38 */ 2792 /* Set up address of status block */ 2793 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2794 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2795 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2796 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2797 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2798 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2799 2800 /* Set up status block size. */ 2801 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2802 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2803 val = BGE_STATBLKSZ_FULL; 2804 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2805 } else { 2806 val = BGE_STATBLKSZ_32BYTE; 2807 bzero(&sc->bge_rdata->bge_status_block, 32); 2808 } 2809 2810 /* 5718 step 39, 57XX step 73 */ 2811 /* Turn on host coalescing state machine */ 2812 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2813 2814 /* 5718 step 40, 57XX step 74 */ 2815 /* Turn on RX BD completion state machine and enable attentions */ 2816 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2817 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2818 2819 /* 5718 step 41, 57XX step 75 */ 2820 /* Turn on RX list placement state machine */ 2821 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2822 2823 /* 57XX step 76 */ 2824 /* Turn on RX list selector state machine. */ 2825 if (!(BGE_IS_5705_PLUS(sc))) 2826 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2827 2828 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2829 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2830 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2831 BGE_MACMODE_FRMHDR_DMA_ENB; 2832 2833 if (sc->bge_flags & BGEF_FIBER_TBI) 2834 val |= BGE_PORTMODE_TBI; 2835 else if (sc->bge_flags & BGEF_FIBER_MII) 2836 val |= BGE_PORTMODE_GMII; 2837 else 2838 val |= BGE_PORTMODE_MII; 2839 2840 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2841 /* Allow APE to send/receive frames. */ 2842 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2843 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2844 2845 /* Turn on DMA, clear stats */ 2846 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2847 /* 5718 step 44 */ 2848 DELAY(40); 2849 2850 /* 5718 step 45, 57XX step 79 */ 2851 /* Set misc. local control, enable interrupts on attentions */ 2852 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2853 if (BGE_IS_5717_PLUS(sc)) { 2854 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2855 /* 5718 step 46 */ 2856 DELAY(100); 2857 } 2858 2859 /* 57XX step 81 */ 2860 /* Turn on DMA completion state machine */ 2861 if (!(BGE_IS_5705_PLUS(sc))) 2862 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2863 2864 /* 5718 step 47, 57XX step 82 */ 2865 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2866 2867 /* 5718 step 48 */ 2868 /* Enable host coalescing bug fix. */ 2869 if (BGE_IS_5755_PLUS(sc)) 2870 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2871 2872 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2873 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2874 2875 /* Turn on write DMA state machine */ 2876 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2877 /* 5718 step 49 */ 2878 DELAY(40); 2879 2880 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2881 2882 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2883 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2884 2885 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2886 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2887 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2888 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2889 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2890 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2891 2892 if (sc->bge_flags & BGEF_PCIE) 2893 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2894 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2895 if (ifp->if_mtu <= ETHERMTU) 2896 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2897 } 2898 if (sc->bge_flags & BGEF_TSO) { 2899 val |= BGE_RDMAMODE_TSO4_ENABLE; 2900 if (BGE_IS_5717_PLUS(sc)) 2901 val |= BGE_RDMAMODE_TSO6_ENABLE; 2902 } 2903 2904 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2905 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2906 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2907 BGE_RDMAMODE_H2BNC_VLAN_DET; 2908 /* 2909 * Allow multiple outstanding read requests from 2910 * non-LSO read DMA engine. 2911 */ 2912 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2913 } 2914 2915 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2916 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2917 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2918 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2919 BGE_IS_57765_PLUS(sc)) { 2920 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2921 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2922 else 2923 rdmareg = BGE_RDMA_RSRVCTRL; 2924 dmactl = CSR_READ_4(sc, rdmareg); 2925 /* 2926 * Adjust tx margin to prevent TX data corruption and 2927 * fix internal FIFO overflow. 2928 */ 2929 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2930 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2931 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2932 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2933 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2934 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2935 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2936 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2937 } 2938 /* 2939 * Enable fix for read DMA FIFO overruns. 2940 * The fix is to limit the number of RX BDs 2941 * the hardware would fetch at a time. 2942 */ 2943 CSR_WRITE_4(sc, rdmareg, dmactl | 2944 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2945 } 2946 2947 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2948 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2949 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2950 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2951 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2952 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2953 /* 2954 * Allow 4KB burst length reads for non-LSO frames. 2955 * Enable 512B burst length reads for buffer descriptors. 2956 */ 2957 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2958 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2959 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2960 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2961 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2962 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2963 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2964 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2965 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2966 } 2967 /* Turn on read DMA state machine */ 2968 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2969 /* 5718 step 52 */ 2970 delay(40); 2971 2972 if (sc->bge_flags & BGEF_RDMA_BUG) { 2973 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2974 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2975 if ((val & 0xFFFF) > BGE_FRAMELEN) 2976 break; 2977 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2978 break; 2979 } 2980 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2981 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2982 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2983 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2984 else 2985 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2986 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2987 } 2988 } 2989 2990 /* 5718 step 56, 57XX step 84 */ 2991 /* Turn on RX data completion state machine */ 2992 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2993 2994 /* Turn on RX data and RX BD initiator state machine */ 2995 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2996 2997 /* 57XX step 85 */ 2998 /* Turn on Mbuf cluster free state machine */ 2999 if (!BGE_IS_5705_PLUS(sc)) 3000 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3001 3002 /* 5718 step 57, 57XX step 86 */ 3003 /* Turn on send data completion state machine */ 3004 val = BGE_SDCMODE_ENABLE; 3005 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3006 val |= BGE_SDCMODE_CDELAY; 3007 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3008 3009 /* 5718 step 58 */ 3010 /* Turn on send BD completion state machine */ 3011 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3012 3013 /* 57XX step 88 */ 3014 /* Turn on RX BD initiator state machine */ 3015 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3016 3017 /* 5718 step 60, 57XX step 90 */ 3018 /* Turn on send data initiator state machine */ 3019 if (sc->bge_flags & BGEF_TSO) { 3020 /* XXX: magic value from Linux driver */ 3021 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3022 BGE_SDIMODE_HW_LSO_PRE_DMA); 3023 } else 3024 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3025 3026 /* 5718 step 61, 57XX step 91 */ 3027 /* Turn on send BD initiator state machine */ 3028 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3029 3030 /* 5718 step 62, 57XX step 92 */ 3031 /* Turn on send BD selector state machine */ 3032 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3033 3034 /* 5718 step 31, 57XX step 60 */ 3035 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3036 /* 5718 step 32, 57XX step 61 */ 3037 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3038 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3039 3040 /* ack/clear link change events */ 3041 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3042 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3043 BGE_MACSTAT_LINK_CHANGED); 3044 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3045 3046 /* 3047 * Enable attention when the link has changed state for 3048 * devices that use auto polling. 3049 */ 3050 if (sc->bge_flags & BGEF_FIBER_TBI) { 3051 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3052 } else { 3053 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3054 mimode = BGE_MIMODE_500KHZ_CONST; 3055 else 3056 mimode = BGE_MIMODE_BASE; 3057 /* 5718 step 68. 5718 step 69 (optionally). */ 3058 if (BGE_IS_5700_FAMILY(sc) || 3059 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3060 mimode |= BGE_MIMODE_AUTOPOLL; 3061 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3062 } 3063 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3064 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3065 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3066 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3067 BGE_EVTENB_MI_INTERRUPT); 3068 } 3069 3070 /* 3071 * Clear any pending link state attention. 3072 * Otherwise some link state change events may be lost until attention 3073 * is cleared by bge_intr() -> bge_link_upd() sequence. 3074 * It's not necessary on newer BCM chips - perhaps enabling link 3075 * state change attentions implies clearing pending attention. 3076 */ 3077 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3078 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3079 BGE_MACSTAT_LINK_CHANGED); 3080 3081 /* Enable link state change attentions. */ 3082 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3083 3084 return 0; 3085 } 3086 3087 static const struct bge_revision * 3088 bge_lookup_rev(uint32_t chipid) 3089 { 3090 const struct bge_revision *br; 3091 3092 for (br = bge_revisions; br->br_name != NULL; br++) { 3093 if (br->br_chipid == chipid) 3094 return br; 3095 } 3096 3097 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3098 if (br->br_chipid == BGE_ASICREV(chipid)) 3099 return br; 3100 } 3101 3102 return NULL; 3103 } 3104 3105 static const struct bge_product * 3106 bge_lookup(const struct pci_attach_args *pa) 3107 { 3108 const struct bge_product *bp; 3109 3110 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3111 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3112 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3113 return bp; 3114 } 3115 3116 return NULL; 3117 } 3118 3119 static uint32_t 3120 bge_chipid(const struct pci_attach_args *pa) 3121 { 3122 uint32_t id; 3123 3124 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3125 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3126 3127 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3128 switch (PCI_PRODUCT(pa->pa_id)) { 3129 case PCI_PRODUCT_BROADCOM_BCM5717: 3130 case PCI_PRODUCT_BROADCOM_BCM5718: 3131 case PCI_PRODUCT_BROADCOM_BCM5719: 3132 case PCI_PRODUCT_BROADCOM_BCM5720: 3133 case PCI_PRODUCT_BROADCOM_BCM5725: 3134 case PCI_PRODUCT_BROADCOM_BCM5727: 3135 case PCI_PRODUCT_BROADCOM_BCM5762: 3136 case PCI_PRODUCT_BROADCOM_BCM57764: 3137 case PCI_PRODUCT_BROADCOM_BCM57767: 3138 case PCI_PRODUCT_BROADCOM_BCM57787: 3139 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3140 BGE_PCI_GEN2_PRODID_ASICREV); 3141 break; 3142 case PCI_PRODUCT_BROADCOM_BCM57761: 3143 case PCI_PRODUCT_BROADCOM_BCM57762: 3144 case PCI_PRODUCT_BROADCOM_BCM57765: 3145 case PCI_PRODUCT_BROADCOM_BCM57766: 3146 case PCI_PRODUCT_BROADCOM_BCM57781: 3147 case PCI_PRODUCT_BROADCOM_BCM57782: 3148 case PCI_PRODUCT_BROADCOM_BCM57785: 3149 case PCI_PRODUCT_BROADCOM_BCM57786: 3150 case PCI_PRODUCT_BROADCOM_BCM57791: 3151 case PCI_PRODUCT_BROADCOM_BCM57795: 3152 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3153 BGE_PCI_GEN15_PRODID_ASICREV); 3154 break; 3155 default: 3156 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3157 BGE_PCI_PRODID_ASICREV); 3158 break; 3159 } 3160 } 3161 3162 return id; 3163 } 3164 3165 /* 3166 * Return true if MSI can be used with this device. 3167 */ 3168 static int 3169 bge_can_use_msi(struct bge_softc *sc) 3170 { 3171 int can_use_msi = 0; 3172 3173 switch (BGE_ASICREV(sc->bge_chipid)) { 3174 case BGE_ASICREV_BCM5714_A0: 3175 case BGE_ASICREV_BCM5714: 3176 /* 3177 * Apparently, MSI doesn't work when these chips are 3178 * configured in single-port mode. 3179 */ 3180 break; 3181 case BGE_ASICREV_BCM5750: 3182 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3183 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3184 can_use_msi = 1; 3185 break; 3186 default: 3187 if (BGE_IS_575X_PLUS(sc)) 3188 can_use_msi = 1; 3189 } 3190 return can_use_msi; 3191 } 3192 3193 /* 3194 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3195 * against our list and return its name if we find a match. Note 3196 * that since the Broadcom controller contains VPD support, we 3197 * can get the device name string from the controller itself instead 3198 * of the compiled-in string. This is a little slow, but it guarantees 3199 * we'll always announce the right product name. 3200 */ 3201 static int 3202 bge_probe(device_t parent, cfdata_t match, void *aux) 3203 { 3204 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3205 3206 if (bge_lookup(pa) != NULL) 3207 return 1; 3208 3209 return 0; 3210 } 3211 3212 static void 3213 bge_attach(device_t parent, device_t self, void *aux) 3214 { 3215 struct bge_softc * const sc = device_private(self); 3216 struct pci_attach_args * const pa = aux; 3217 prop_dictionary_t dict; 3218 const struct bge_product *bp; 3219 const struct bge_revision *br; 3220 pci_chipset_tag_t pc; 3221 const char *intrstr = NULL; 3222 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3223 uint32_t command; 3224 struct ifnet *ifp; 3225 struct mii_data * const mii = &sc->bge_mii; 3226 uint32_t misccfg, mimode, macmode; 3227 void * kva; 3228 u_char eaddr[ETHER_ADDR_LEN]; 3229 pcireg_t memtype, subid, reg; 3230 bus_addr_t memaddr; 3231 uint32_t pm_ctl; 3232 bool no_seeprom; 3233 int capmask, trys; 3234 int mii_flags; 3235 int map_flags; 3236 char intrbuf[PCI_INTRSTR_LEN]; 3237 3238 bp = bge_lookup(pa); 3239 KASSERT(bp != NULL); 3240 3241 sc->sc_pc = pa->pa_pc; 3242 sc->sc_pcitag = pa->pa_tag; 3243 sc->bge_dev = self; 3244 3245 sc->bge_pa = *pa; 3246 pc = sc->sc_pc; 3247 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3248 3249 aprint_naive(": Ethernet controller\n"); 3250 aprint_normal(": %s Ethernet\n", bp->bp_name); 3251 3252 /* 3253 * Map control/status registers. 3254 */ 3255 DPRINTFN(5, ("Map control/status regs\n")); 3256 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3257 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3258 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3259 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3260 3261 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3262 aprint_error_dev(sc->bge_dev, 3263 "failed to enable memory mapping!\n"); 3264 return; 3265 } 3266 3267 DPRINTFN(5, ("pci_mem_find\n")); 3268 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3269 switch (memtype) { 3270 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3271 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3272 #if 0 3273 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3274 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3275 &memaddr, &sc->bge_bsize) == 0) 3276 break; 3277 #else 3278 /* 3279 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3280 * system get NMI on boot (PR#48451). This problem might not be 3281 * the driver's bug but our PCI common part's bug. Until we 3282 * find a real reason, we ignore the prefetchable bit. 3283 */ 3284 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3285 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3286 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3287 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3288 map_flags, &sc->bge_bhandle) == 0) { 3289 sc->bge_btag = pa->pa_memt; 3290 break; 3291 } 3292 } 3293 #endif 3294 /* FALLTHROUGH */ 3295 default: 3296 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3297 return; 3298 } 3299 3300 /* Save various chip information. */ 3301 sc->bge_chipid = bge_chipid(pa); 3302 sc->bge_phy_addr = bge_phy_addr(sc); 3303 3304 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3305 &sc->bge_pciecap, NULL) != 0) { 3306 /* PCIe */ 3307 sc->bge_flags |= BGEF_PCIE; 3308 /* Extract supported maximum payload size. */ 3309 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3310 sc->bge_pciecap + PCIE_DCAP); 3311 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3312 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3313 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3314 sc->bge_expmrq = 2048; 3315 else 3316 sc->bge_expmrq = 4096; 3317 bge_set_max_readrq(sc); 3318 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3319 /* PCIe without PCIe cap */ 3320 sc->bge_flags |= BGEF_PCIE; 3321 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3322 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3323 /* PCI-X */ 3324 sc->bge_flags |= BGEF_PCIX; 3325 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3326 &sc->bge_pcixcap, NULL) == 0) 3327 aprint_error_dev(sc->bge_dev, 3328 "unable to find PCIX capability\n"); 3329 } 3330 3331 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3332 /* 3333 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3334 * can clobber the chip's PCI config-space power control 3335 * registers, leaving the card in D3 powersave state. We do 3336 * not have memory-mapped registers in this state, so force 3337 * device into D0 state before starting initialization. 3338 */ 3339 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3340 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3341 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3342 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3343 DELAY(1000); /* 27 usec is allegedly sufficient */ 3344 } 3345 3346 /* Save chipset family. */ 3347 switch (BGE_ASICREV(sc->bge_chipid)) { 3348 case BGE_ASICREV_BCM5717: 3349 case BGE_ASICREV_BCM5719: 3350 case BGE_ASICREV_BCM5720: 3351 sc->bge_flags |= BGEF_5717_PLUS; 3352 /* FALLTHROUGH */ 3353 case BGE_ASICREV_BCM5762: 3354 case BGE_ASICREV_BCM57765: 3355 case BGE_ASICREV_BCM57766: 3356 if (!BGE_IS_5717_PLUS(sc)) 3357 sc->bge_flags |= BGEF_57765_FAMILY; 3358 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3359 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3360 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3361 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3362 /* 3363 * Enable work around for DMA engine miscalculation 3364 * of TXMBUF available space. 3365 */ 3366 sc->bge_flags |= BGEF_RDMA_BUG; 3367 3368 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3369 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3370 /* Jumbo frame on BCM5719 A0 does not work. */ 3371 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3372 } 3373 } 3374 break; 3375 case BGE_ASICREV_BCM5755: 3376 case BGE_ASICREV_BCM5761: 3377 case BGE_ASICREV_BCM5784: 3378 case BGE_ASICREV_BCM5785: 3379 case BGE_ASICREV_BCM5787: 3380 case BGE_ASICREV_BCM57780: 3381 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3382 break; 3383 case BGE_ASICREV_BCM5700: 3384 case BGE_ASICREV_BCM5701: 3385 case BGE_ASICREV_BCM5703: 3386 case BGE_ASICREV_BCM5704: 3387 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3388 break; 3389 case BGE_ASICREV_BCM5714_A0: 3390 case BGE_ASICREV_BCM5780: 3391 case BGE_ASICREV_BCM5714: 3392 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3393 /* FALLTHROUGH */ 3394 case BGE_ASICREV_BCM5750: 3395 case BGE_ASICREV_BCM5752: 3396 case BGE_ASICREV_BCM5906: 3397 sc->bge_flags |= BGEF_575X_PLUS; 3398 /* FALLTHROUGH */ 3399 case BGE_ASICREV_BCM5705: 3400 sc->bge_flags |= BGEF_5705_PLUS; 3401 break; 3402 } 3403 3404 /* Identify chips with APE processor. */ 3405 switch (BGE_ASICREV(sc->bge_chipid)) { 3406 case BGE_ASICREV_BCM5717: 3407 case BGE_ASICREV_BCM5719: 3408 case BGE_ASICREV_BCM5720: 3409 case BGE_ASICREV_BCM5761: 3410 case BGE_ASICREV_BCM5762: 3411 sc->bge_flags |= BGEF_APE; 3412 break; 3413 } 3414 3415 /* 3416 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3417 * not actually a MAC controller bug but an issue with the embedded 3418 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3419 */ 3420 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3421 sc->bge_flags |= BGEF_40BIT_BUG; 3422 3423 /* Chips with APE need BAR2 access for APE registers/memory. */ 3424 if ((sc->bge_flags & BGEF_APE) != 0) { 3425 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3426 #if 0 3427 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3428 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3429 &sc->bge_apesize)) { 3430 aprint_error_dev(sc->bge_dev, 3431 "couldn't map BAR2 memory\n"); 3432 return; 3433 } 3434 #else 3435 /* 3436 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3437 * system get NMI on boot (PR#48451). This problem might not be 3438 * the driver's bug but our PCI common part's bug. Until we 3439 * find a real reason, we ignore the prefetchable bit. 3440 */ 3441 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3442 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3443 aprint_error_dev(sc->bge_dev, 3444 "couldn't map BAR2 memory\n"); 3445 return; 3446 } 3447 3448 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3449 if (bus_space_map(pa->pa_memt, memaddr, 3450 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3451 aprint_error_dev(sc->bge_dev, 3452 "couldn't map BAR2 memory\n"); 3453 return; 3454 } 3455 sc->bge_apetag = pa->pa_memt; 3456 #endif 3457 3458 /* Enable APE register/memory access by host driver. */ 3459 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3460 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3461 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3462 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3463 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3464 3465 bge_ape_lock_init(sc); 3466 bge_ape_read_fw_ver(sc); 3467 } 3468 3469 /* Identify the chips that use an CPMU. */ 3470 if (BGE_IS_5717_PLUS(sc) || 3471 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3472 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3473 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3474 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3475 sc->bge_flags |= BGEF_CPMU_PRESENT; 3476 3477 /* 3478 * When using the BCM5701 in PCI-X mode, data corruption has 3479 * been observed in the first few bytes of some received packets. 3480 * Aligning the packet buffer in memory eliminates the corruption. 3481 * Unfortunately, this misaligns the packet payloads. On platforms 3482 * which do not support unaligned accesses, we will realign the 3483 * payloads by copying the received packets. 3484 */ 3485 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3486 sc->bge_flags & BGEF_PCIX) 3487 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3488 3489 if (BGE_IS_5700_FAMILY(sc)) 3490 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3491 3492 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3493 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3494 3495 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3496 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3497 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3498 sc->bge_flags |= BGEF_IS_5788; 3499 3500 /* 3501 * Some controllers seem to require a special firmware to use 3502 * TSO. But the firmware is not available to FreeBSD and Linux 3503 * claims that the TSO performed by the firmware is slower than 3504 * hardware based TSO. Moreover the firmware based TSO has one 3505 * known bug which can't handle TSO if ethernet header + IP/TCP 3506 * header is greater than 80 bytes. The workaround for the TSO 3507 * bug exist but it seems it's too expensive than not using 3508 * TSO at all. Some hardwares also have the TSO bug so limit 3509 * the TSO to the controllers that are not affected TSO issues 3510 * (e.g. 5755 or higher). 3511 */ 3512 if (BGE_IS_5755_PLUS(sc)) { 3513 /* 3514 * BCM5754 and BCM5787 shares the same ASIC id so 3515 * explicit device id check is required. 3516 */ 3517 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3518 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3519 sc->bge_flags |= BGEF_TSO; 3520 /* TSO on BCM5719 A0 does not work. */ 3521 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3522 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3523 sc->bge_flags &= ~BGEF_TSO; 3524 } 3525 3526 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3527 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3528 (misccfg == 0x4000 || misccfg == 0x8000)) || 3529 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3530 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3531 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3532 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3533 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3534 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3535 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3536 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3537 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3538 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3539 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3540 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3541 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3542 /* These chips are 10/100 only. */ 3543 capmask &= ~BMSR_EXTSTAT; 3544 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3545 } 3546 3547 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3548 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3549 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3550 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3551 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3552 3553 /* Set various PHY bug flags. */ 3554 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3555 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3556 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3557 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3558 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3559 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3560 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3561 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3562 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3563 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3564 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3565 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3566 if (BGE_IS_5705_PLUS(sc) && 3567 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3568 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3569 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3570 !BGE_IS_57765_PLUS(sc)) { 3571 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3572 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3573 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3574 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3575 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3576 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3577 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3578 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3579 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3580 } else 3581 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3582 } 3583 3584 /* 3585 * SEEPROM check. 3586 * First check if firmware knows we do not have SEEPROM. 3587 */ 3588 if (prop_dictionary_get_bool(device_properties(self), 3589 "without-seeprom", &no_seeprom) && no_seeprom) 3590 sc->bge_flags |= BGEF_NO_EEPROM; 3591 3592 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3593 sc->bge_flags |= BGEF_NO_EEPROM; 3594 3595 /* Now check the 'ROM failed' bit on the RX CPU */ 3596 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3597 sc->bge_flags |= BGEF_NO_EEPROM; 3598 3599 sc->bge_asf_mode = 0; 3600 /* No ASF if APE present. */ 3601 if ((sc->bge_flags & BGEF_APE) == 0) { 3602 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3603 BGE_SRAM_DATA_SIG_MAGIC)) { 3604 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3605 BGE_HWCFG_ASF) { 3606 sc->bge_asf_mode |= ASF_ENABLE; 3607 sc->bge_asf_mode |= ASF_STACKUP; 3608 if (BGE_IS_575X_PLUS(sc)) 3609 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3610 } 3611 } 3612 } 3613 3614 int counts[PCI_INTR_TYPE_SIZE] = { 3615 [PCI_INTR_TYPE_INTX] = 1, 3616 [PCI_INTR_TYPE_MSI] = 1, 3617 [PCI_INTR_TYPE_MSIX] = 1, 3618 }; 3619 int max_type = PCI_INTR_TYPE_MSIX; 3620 3621 if (!bge_can_use_msi(sc)) { 3622 /* MSI broken, allow only INTx */ 3623 max_type = PCI_INTR_TYPE_INTX; 3624 } 3625 3626 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3627 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3628 return; 3629 } 3630 3631 DPRINTFN(5, ("pci_intr_string\n")); 3632 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3633 sizeof(intrbuf)); 3634 DPRINTFN(5, ("pci_intr_establish\n")); 3635 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3636 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3637 if (sc->bge_intrhand == NULL) { 3638 pci_intr_release(pc, sc->bge_pihp, 1); 3639 sc->bge_pihp = NULL; 3640 3641 aprint_error_dev(self, "couldn't establish interrupt"); 3642 if (intrstr != NULL) 3643 aprint_error(" at %s", intrstr); 3644 aprint_error("\n"); 3645 return; 3646 } 3647 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3648 3649 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3650 case PCI_INTR_TYPE_MSIX: 3651 case PCI_INTR_TYPE_MSI: 3652 KASSERT(bge_can_use_msi(sc)); 3653 sc->bge_flags |= BGEF_MSI; 3654 break; 3655 default: 3656 /* nothing to do */ 3657 break; 3658 } 3659 3660 char wqname[MAXCOMLEN]; 3661 snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->bge_dev)); 3662 int error = workqueue_create(&sc->sc_reset_wq, wqname, 3663 bge_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK, 3664 WQ_MPSAFE); 3665 if (error) { 3666 aprint_error_dev(sc->bge_dev, 3667 "unable to create reset workqueue\n"); 3668 return; 3669 } 3670 3671 3672 /* 3673 * All controllers except BCM5700 supports tagged status but 3674 * we use tagged status only for MSI case on BCM5717. Otherwise 3675 * MSI on BCM5717 does not work. 3676 */ 3677 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3678 sc->bge_flags |= BGEF_TAGGED_STATUS; 3679 3680 /* 3681 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3682 * lock in bge_reset(). 3683 */ 3684 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3685 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3686 delay(1000); 3687 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3688 3689 bge_stop_fw(sc); 3690 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3691 if (bge_reset(sc)) 3692 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3693 3694 /* 3695 * Read the hardware config word in the first 32k of NIC internal 3696 * memory, or fall back to the config word in the EEPROM. 3697 * Note: on some BCM5700 cards, this value appears to be unset. 3698 */ 3699 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3700 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3701 BGE_SRAM_DATA_SIG_MAGIC) { 3702 uint32_t tmp; 3703 3704 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3705 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3706 BGE_SRAM_DATA_VER_SHIFT; 3707 if ((0 < tmp) && (tmp < 0x100)) 3708 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3709 if (sc->bge_flags & BGEF_PCIE) 3710 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3711 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3712 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3713 if (BGE_IS_5717_PLUS(sc)) 3714 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3715 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3716 bge_read_eeprom(sc, (void *)&hwcfg, 3717 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3718 hwcfg = be32toh(hwcfg); 3719 } 3720 aprint_normal_dev(sc->bge_dev, 3721 "HW config %08x, %08x, %08x, %08x %08x\n", 3722 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3723 3724 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3725 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3726 3727 if (bge_chipinit(sc)) { 3728 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3729 bge_release_resources(sc); 3730 return; 3731 } 3732 3733 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3734 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3735 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3736 DELAY(100); 3737 } 3738 3739 /* Set MI_MODE */ 3740 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3741 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3742 mimode |= BGE_MIMODE_500KHZ_CONST; 3743 else 3744 mimode |= BGE_MIMODE_BASE; 3745 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3746 DELAY(80); 3747 3748 /* 3749 * Get station address from the EEPROM. 3750 */ 3751 if (bge_get_eaddr(sc, eaddr)) { 3752 aprint_error_dev(sc->bge_dev, 3753 "failed to read station address\n"); 3754 bge_release_resources(sc); 3755 return; 3756 } 3757 3758 br = bge_lookup_rev(sc->bge_chipid); 3759 3760 if (br == NULL) { 3761 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3762 sc->bge_chipid); 3763 } else { 3764 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3765 br->br_name, sc->bge_chipid); 3766 } 3767 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3768 3769 /* Allocate the general information block and ring buffers. */ 3770 if (pci_dma64_available(pa)) { 3771 sc->bge_dmatag = pa->pa_dmat64; 3772 sc->bge_dmatag32 = pa->pa_dmat; 3773 sc->bge_dma64 = true; 3774 } else { 3775 sc->bge_dmatag = pa->pa_dmat; 3776 sc->bge_dmatag32 = pa->pa_dmat; 3777 sc->bge_dma64 = false; 3778 } 3779 3780 /* 40bit DMA workaround */ 3781 if (sizeof(bus_addr_t) > 4) { 3782 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3783 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3784 3785 if (bus_dmatag_subregion(olddmatag, 0, 3786 (bus_addr_t)__MASK(40), 3787 &(sc->bge_dmatag), BUS_DMA_WAITOK) != 0) { 3788 aprint_error_dev(self, 3789 "WARNING: failed to restrict dma range," 3790 " falling back to parent bus dma range\n"); 3791 sc->bge_dmatag = olddmatag; 3792 } 3793 } 3794 } 3795 SLIST_INIT(&sc->txdma_list); 3796 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3797 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3798 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3799 &sc->bge_ring_rseg, BUS_DMA_WAITOK)) { 3800 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3801 return; 3802 } 3803 DPRINTFN(5, ("bus_dmamem_map\n")); 3804 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3805 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3806 BUS_DMA_WAITOK)) { 3807 aprint_error_dev(sc->bge_dev, 3808 "can't map DMA buffers (%zu bytes)\n", 3809 sizeof(struct bge_ring_data)); 3810 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3811 sc->bge_ring_rseg); 3812 return; 3813 } 3814 DPRINTFN(5, ("bus_dmamem_create\n")); 3815 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3816 sizeof(struct bge_ring_data), 0, 3817 BUS_DMA_WAITOK, &sc->bge_ring_map)) { 3818 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3819 bus_dmamem_unmap(sc->bge_dmatag, kva, 3820 sizeof(struct bge_ring_data)); 3821 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3822 sc->bge_ring_rseg); 3823 return; 3824 } 3825 DPRINTFN(5, ("bus_dmamem_load\n")); 3826 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3827 sizeof(struct bge_ring_data), NULL, 3828 BUS_DMA_WAITOK)) { 3829 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3830 bus_dmamem_unmap(sc->bge_dmatag, kva, 3831 sizeof(struct bge_ring_data)); 3832 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3833 sc->bge_ring_rseg); 3834 return; 3835 } 3836 3837 DPRINTFN(5, ("bzero\n")); 3838 sc->bge_rdata = (struct bge_ring_data *)kva; 3839 3840 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3841 3842 /* Try to allocate memory for jumbo buffers. */ 3843 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3844 if (bge_alloc_jumbo_mem(sc)) { 3845 aprint_error_dev(sc->bge_dev, 3846 "jumbo buffer allocation failed\n"); 3847 } else 3848 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3849 } 3850 3851 /* Set default tuneable values. */ 3852 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3853 sc->bge_rx_coal_ticks = 150; 3854 sc->bge_rx_max_coal_bds = 64; 3855 sc->bge_tx_coal_ticks = 300; 3856 sc->bge_tx_max_coal_bds = 400; 3857 if (BGE_IS_5705_PLUS(sc)) { 3858 sc->bge_tx_coal_ticks = (12 * 5); 3859 sc->bge_tx_max_coal_bds = (12 * 5); 3860 aprint_verbose_dev(sc->bge_dev, 3861 "setting short Tx thresholds\n"); 3862 } 3863 3864 if (BGE_IS_5717_PLUS(sc)) 3865 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3866 else if (BGE_IS_5705_PLUS(sc)) 3867 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3868 else 3869 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3870 3871 sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 3872 3873 /* Set up ifnet structure */ 3874 ifp = &sc->ethercom.ec_if; 3875 ifp->if_softc = sc; 3876 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3877 ifp->if_extflags = IFEF_MPSAFE; 3878 ifp->if_ioctl = bge_ioctl; 3879 ifp->if_stop = bge_stop; 3880 ifp->if_start = bge_start; 3881 ifp->if_init = bge_init; 3882 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3883 IFQ_SET_READY(&ifp->if_snd); 3884 DPRINTFN(5, ("strcpy if_xname\n")); 3885 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3886 3887 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3888 sc->ethercom.ec_if.if_capabilities |= 3889 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3890 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3891 sc->ethercom.ec_if.if_capabilities |= 3892 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3893 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3894 #endif 3895 sc->ethercom.ec_capabilities |= 3896 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3897 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3898 3899 if (sc->bge_flags & BGEF_TSO) 3900 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3901 3902 /* 3903 * Do MII setup. 3904 */ 3905 DPRINTFN(5, ("mii setup\n")); 3906 mii->mii_ifp = ifp; 3907 mii->mii_readreg = bge_miibus_readreg; 3908 mii->mii_writereg = bge_miibus_writereg; 3909 mii->mii_statchg = bge_miibus_statchg; 3910 3911 /* 3912 * Figure out what sort of media we have by checking the hardware 3913 * config word. Note: on some BCM5700 cards, this value appears to be 3914 * unset. If that's the case, we have to rely on identifying the NIC 3915 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3916 * The SysKonnect SK-9D41 is a 1000baseSX card. 3917 */ 3918 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3919 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3920 if (BGE_IS_5705_PLUS(sc)) { 3921 sc->bge_flags |= BGEF_FIBER_MII; 3922 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3923 } else 3924 sc->bge_flags |= BGEF_FIBER_TBI; 3925 } 3926 3927 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3928 if (BGE_IS_JUMBO_CAPABLE(sc)) 3929 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3930 3931 /* set phyflags and chipid before mii_attach() */ 3932 dict = device_properties(self); 3933 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3934 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3935 3936 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3937 macmode &= ~BGE_MACMODE_PORTMODE; 3938 /* Initialize ifmedia structures. */ 3939 if (sc->bge_flags & BGEF_FIBER_TBI) { 3940 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3941 macmode | BGE_PORTMODE_TBI); 3942 DELAY(40); 3943 3944 sc->ethercom.ec_ifmedia = &sc->bge_ifmedia; 3945 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3946 bge_ifmedia_sts); 3947 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 3948 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX |IFM_FDX, 3949 0, NULL); 3950 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3951 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3952 /* Pretend the user requested this setting */ 3953 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3954 } else { 3955 uint16_t phyreg; 3956 int rv; 3957 /* 3958 * Do transceiver setup and tell the firmware the 3959 * driver is down so we can try to get access the 3960 * probe if ASF is running. Retry a couple of times 3961 * if we get a conflict with the ASF firmware accessing 3962 * the PHY. 3963 */ 3964 if (sc->bge_flags & BGEF_FIBER_MII) 3965 macmode |= BGE_PORTMODE_GMII; 3966 else 3967 macmode |= BGE_PORTMODE_MII; 3968 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3969 DELAY(40); 3970 3971 /* 3972 * Do transceiver setup and tell the firmware the 3973 * driver is down so we can try to get access the 3974 * probe if ASF is running. Retry a couple of times 3975 * if we get a conflict with the ASF firmware accessing 3976 * the PHY. 3977 */ 3978 trys = 0; 3979 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3980 sc->ethercom.ec_mii = mii; 3981 ifmedia_init(&mii->mii_media, 0, bge_ifmedia_upd, 3982 bge_ifmedia_sts); 3983 mii_flags = MIIF_DOPAUSE; 3984 if (sc->bge_flags & BGEF_FIBER_MII) 3985 mii_flags |= MIIF_HAVEFIBER; 3986 again: 3987 bge_asf_driver_up(sc); 3988 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 3989 MII_BMCR, &phyreg); 3990 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 3991 int i; 3992 3993 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 3994 MII_BMCR, BMCR_RESET); 3995 /* Wait up to 500ms for it to complete. */ 3996 for (i = 0; i < 500; i++) { 3997 bge_miibus_readreg(sc->bge_dev, 3998 sc->bge_phy_addr, MII_BMCR, &phyreg); 3999 if ((phyreg & BMCR_RESET) == 0) 4000 break; 4001 DELAY(1000); 4002 } 4003 } 4004 4005 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 4006 MII_OFFSET_ANY, mii_flags); 4007 4008 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 4009 goto again; 4010 4011 if (LIST_EMPTY(&mii->mii_phys)) { 4012 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4013 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 4014 0, NULL); 4015 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 4016 } else 4017 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 4018 4019 /* 4020 * Now tell the firmware we are going up after probing the PHY 4021 */ 4022 if (sc->bge_asf_mode & ASF_STACKUP) 4023 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4024 } 4025 4026 /* 4027 * Call MI attach routine. 4028 */ 4029 DPRINTFN(5, ("if_initialize\n")); 4030 if_initialize(ifp); 4031 ifp->if_percpuq = if_percpuq_create(ifp); 4032 if_deferred_start_init(ifp, NULL); 4033 if_register(ifp); 4034 4035 DPRINTFN(5, ("ether_ifattach\n")); 4036 ether_ifattach(ifp, eaddr); 4037 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4038 4039 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4040 RND_TYPE_NET, RND_FLAG_DEFAULT); 4041 #ifdef BGE_EVENT_COUNTERS 4042 /* 4043 * Attach event counters. 4044 */ 4045 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4046 NULL, device_xname(sc->bge_dev), "intr"); 4047 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4048 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4049 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4050 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4051 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4052 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4053 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4054 NULL, device_xname(sc->bge_dev), "tx_xon"); 4055 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4056 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4057 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4058 NULL, device_xname(sc->bge_dev), "rx_xon"); 4059 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4060 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4061 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4062 NULL, device_xname(sc->bge_dev), "xoffentered"); 4063 #endif /* BGE_EVENT_COUNTERS */ 4064 DPRINTFN(5, ("callout_init\n")); 4065 callout_init(&sc->bge_timeout, CALLOUT_MPSAFE); 4066 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4067 4068 if (pmf_device_register(self, NULL, NULL)) 4069 pmf_class_network_register(self, ifp); 4070 else 4071 aprint_error_dev(self, "couldn't establish power handler\n"); 4072 4073 bge_sysctl_init(sc); 4074 4075 #ifdef BGE_DEBUG 4076 bge_debug_info(sc); 4077 #endif 4078 } 4079 4080 /* 4081 * Stop all chip I/O so that the kernel's probe routines don't 4082 * get confused by errant DMAs when rebooting. 4083 */ 4084 static int 4085 bge_detach(device_t self, int flags __unused) 4086 { 4087 struct bge_softc * const sc = device_private(self); 4088 struct ifnet * const ifp = &sc->ethercom.ec_if; 4089 4090 /* Stop the interface. Callouts are stopped in it. */ 4091 bge_stop(ifp, 1); 4092 4093 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4094 4095 ether_ifdetach(ifp); 4096 if_detach(ifp); 4097 4098 /* Delete all remaining media. */ 4099 ifmedia_fini(&sc->bge_mii.mii_media); 4100 4101 bge_release_resources(sc); 4102 4103 return 0; 4104 } 4105 4106 static void 4107 bge_release_resources(struct bge_softc *sc) 4108 { 4109 4110 /* Detach sysctl */ 4111 if (sc->bge_log != NULL) 4112 sysctl_teardown(&sc->bge_log); 4113 4114 #ifdef BGE_EVENT_COUNTERS 4115 /* Detach event counters. */ 4116 evcnt_detach(&sc->bge_ev_intr); 4117 evcnt_detach(&sc->bge_ev_intr_spurious); 4118 evcnt_detach(&sc->bge_ev_intr_spurious2); 4119 evcnt_detach(&sc->bge_ev_tx_xoff); 4120 evcnt_detach(&sc->bge_ev_tx_xon); 4121 evcnt_detach(&sc->bge_ev_rx_xoff); 4122 evcnt_detach(&sc->bge_ev_rx_xon); 4123 evcnt_detach(&sc->bge_ev_rx_macctl); 4124 evcnt_detach(&sc->bge_ev_xoffentered); 4125 #endif /* BGE_EVENT_COUNTERS */ 4126 4127 /* Disestablish the interrupt handler */ 4128 if (sc->bge_intrhand != NULL) { 4129 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4130 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4131 sc->bge_intrhand = NULL; 4132 } 4133 4134 if (sc->bge_cdata.bge_jumbo_buf != NULL) 4135 bge_free_jumbo_mem(sc); 4136 4137 if (sc->bge_dmatag != NULL) { 4138 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4139 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4140 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4141 sizeof(struct bge_ring_data)); 4142 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4143 sc->bge_ring_rseg); 4144 } 4145 4146 /* Unmap the device registers */ 4147 if (sc->bge_bsize != 0) { 4148 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4149 sc->bge_bsize = 0; 4150 } 4151 4152 /* Unmap the APE registers */ 4153 if (sc->bge_apesize != 0) { 4154 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4155 sc->bge_apesize); 4156 sc->bge_apesize = 0; 4157 } 4158 } 4159 4160 static int 4161 bge_reset(struct bge_softc *sc) 4162 { 4163 uint32_t cachesize, command; 4164 uint32_t reset, mac_mode, mac_mode_mask; 4165 pcireg_t devctl, reg; 4166 int i, val; 4167 void (*write_op)(struct bge_softc *, int, int); 4168 4169 /* Make mask for BGE_MAC_MODE register. */ 4170 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4171 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4172 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4173 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4174 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4175 4176 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4177 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4178 if (sc->bge_flags & BGEF_PCIE) 4179 write_op = bge_writemem_direct; 4180 else 4181 write_op = bge_writemem_ind; 4182 } else 4183 write_op = bge_writereg_ind; 4184 4185 /* 57XX step 4 */ 4186 /* Acquire the NVM lock */ 4187 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4188 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4189 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4190 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4191 for (i = 0; i < 8000; i++) { 4192 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4193 BGE_NVRAMSWARB_GNT1) 4194 break; 4195 DELAY(20); 4196 } 4197 if (i == 8000) { 4198 printf("%s: NVRAM lock timedout!\n", 4199 device_xname(sc->bge_dev)); 4200 } 4201 } 4202 4203 /* Take APE lock when performing reset. */ 4204 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4205 4206 /* 57XX step 3 */ 4207 /* Save some important PCI state. */ 4208 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4209 /* 5718 reset step 3 */ 4210 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4211 4212 /* 5718 reset step 5, 57XX step 5b-5d */ 4213 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4214 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4215 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4216 4217 /* XXX ???: Disable fastboot on controllers that support it. */ 4218 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4219 BGE_IS_5755_PLUS(sc)) 4220 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4221 4222 /* 5718 reset step 2, 57XX step 6 */ 4223 /* 4224 * Write the magic number to SRAM at offset 0xB50. 4225 * When firmware finishes its initialization it will 4226 * write ~BGE_MAGIC_NUMBER to the same location. 4227 */ 4228 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4229 4230 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4231 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4232 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4233 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4234 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4235 } 4236 4237 /* 5718 reset step 6, 57XX step 7 */ 4238 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4239 /* 4240 * XXX: from FreeBSD/Linux; no documentation 4241 */ 4242 if (sc->bge_flags & BGEF_PCIE) { 4243 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4244 !BGE_IS_57765_PLUS(sc) && 4245 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4246 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4247 /* PCI Express 1.0 system */ 4248 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4249 BGE_PHY_PCIE_SCRAM_MODE); 4250 } 4251 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4252 /* 4253 * Prevent PCI Express link training 4254 * during global reset. 4255 */ 4256 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4257 reset |= (1 << 29); 4258 } 4259 } 4260 4261 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4262 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4263 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4264 i | BGE_VCPU_STATUS_DRV_RESET); 4265 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4266 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4267 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4268 } 4269 4270 /* 4271 * Set GPHY Power Down Override to leave GPHY 4272 * powered up in D0 uninitialized. 4273 */ 4274 if (BGE_IS_5705_PLUS(sc) && 4275 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4276 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4277 4278 /* Issue global reset */ 4279 write_op(sc, BGE_MISC_CFG, reset); 4280 4281 /* 5718 reset step 7, 57XX step 8 */ 4282 if (sc->bge_flags & BGEF_PCIE) 4283 delay(100*1000); /* too big */ 4284 else 4285 delay(1000); 4286 4287 if (sc->bge_flags & BGEF_PCIE) { 4288 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4289 DELAY(500000); 4290 /* XXX: Magic Numbers */ 4291 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4292 BGE_PCI_UNKNOWN0); 4293 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4294 BGE_PCI_UNKNOWN0, 4295 reg | (1 << 15)); 4296 } 4297 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4298 sc->bge_pciecap + PCIE_DCSR); 4299 /* Clear enable no snoop and disable relaxed ordering. */ 4300 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4301 PCIE_DCSR_ENA_NO_SNOOP); 4302 4303 /* Set PCIE max payload size to 128 for older PCIe devices */ 4304 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4305 devctl &= ~(0x00e0); 4306 /* Clear device status register. Write 1b to clear */ 4307 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4308 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4309 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4310 sc->bge_pciecap + PCIE_DCSR, devctl); 4311 bge_set_max_readrq(sc); 4312 } 4313 4314 /* From Linux: dummy read to flush PCI posted writes */ 4315 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4316 4317 /* 4318 * Reset some of the PCI state that got zapped by reset 4319 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4320 * set, too. 4321 */ 4322 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4323 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4324 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4325 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4326 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4327 (sc->bge_flags & BGEF_PCIX) != 0) 4328 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4329 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4330 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4331 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4332 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4333 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4334 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4335 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4336 4337 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4338 if (sc->bge_flags & BGEF_PCIX) { 4339 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4340 + PCIX_CMD); 4341 /* Set max memory read byte count to 2K */ 4342 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4343 reg &= ~PCIX_CMD_BYTECNT_MASK; 4344 reg |= PCIX_CMD_BCNT_2048; 4345 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4346 /* 4347 * For 5704, set max outstanding split transaction 4348 * field to 0 (0 means it supports 1 request) 4349 */ 4350 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4351 | PCIX_CMD_BYTECNT_MASK); 4352 reg |= PCIX_CMD_BCNT_2048; 4353 } 4354 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4355 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4356 } 4357 4358 /* 5718 reset step 10, 57XX step 12 */ 4359 /* Enable memory arbiter. */ 4360 if (BGE_IS_5714_FAMILY(sc)) { 4361 val = CSR_READ_4(sc, BGE_MARB_MODE); 4362 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4363 } else 4364 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4365 4366 /* XXX 5721, 5751 and 5752 */ 4367 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4368 /* Step 19: */ 4369 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4370 /* Step 20: */ 4371 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4372 } 4373 4374 /* 5718 reset step 12, 57XX step 15 and 16 */ 4375 /* Fix up byte swapping */ 4376 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4377 4378 /* 5718 reset step 13, 57XX step 17 */ 4379 /* Poll until the firmware initialization is complete */ 4380 bge_poll_fw(sc); 4381 4382 /* 57XX step 21 */ 4383 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4384 pcireg_t msidata; 4385 4386 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4387 BGE_PCI_MSI_DATA); 4388 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4389 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4390 msidata); 4391 } 4392 4393 /* 57XX step 18 */ 4394 /* Write mac mode. */ 4395 val = CSR_READ_4(sc, BGE_MAC_MODE); 4396 /* Restore mac_mode_mask's bits using mac_mode */ 4397 val = (val & ~mac_mode_mask) | mac_mode; 4398 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4399 DELAY(40); 4400 4401 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4402 4403 /* 4404 * The 5704 in TBI mode apparently needs some special 4405 * adjustment to insure the SERDES drive level is set 4406 * to 1.2V. 4407 */ 4408 if (sc->bge_flags & BGEF_FIBER_TBI && 4409 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4410 uint32_t serdescfg; 4411 4412 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4413 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4414 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4415 } 4416 4417 if (sc->bge_flags & BGEF_PCIE && 4418 !BGE_IS_57765_PLUS(sc) && 4419 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4420 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4421 uint32_t v; 4422 4423 /* Enable PCI Express bug fix */ 4424 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4425 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4426 v | BGE_TLP_DATA_FIFO_PROTECT); 4427 } 4428 4429 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4430 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4431 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4432 4433 return 0; 4434 } 4435 4436 /* 4437 * Frame reception handling. This is called if there's a frame 4438 * on the receive return list. 4439 * 4440 * Note: we have to be able to handle two possibilities here: 4441 * 1) the frame is from the jumbo receive ring 4442 * 2) the frame is from the standard receive ring 4443 */ 4444 4445 static void 4446 bge_rxeof(struct bge_softc *sc) 4447 { 4448 struct ifnet * const ifp = &sc->ethercom.ec_if; 4449 uint16_t rx_prod, rx_cons; 4450 int stdcnt = 0, jumbocnt = 0; 4451 bus_dmamap_t dmamap; 4452 bus_addr_t offset, toff; 4453 bus_size_t tlen; 4454 int tosync; 4455 4456 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4457 offsetof(struct bge_ring_data, bge_status_block), 4458 sizeof(struct bge_status_block), 4459 BUS_DMASYNC_POSTREAD); 4460 4461 rx_cons = sc->bge_rx_saved_considx; 4462 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4463 4464 /* Nothing to do */ 4465 if (rx_cons == rx_prod) 4466 return; 4467 4468 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4469 tosync = rx_prod - rx_cons; 4470 4471 if (tosync != 0) 4472 rnd_add_uint32(&sc->rnd_source, tosync); 4473 4474 toff = offset + (rx_cons * sizeof(struct bge_rx_bd)); 4475 4476 if (tosync < 0) { 4477 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4478 sizeof(struct bge_rx_bd); 4479 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4480 toff, tlen, BUS_DMASYNC_POSTREAD); 4481 tosync = rx_prod; 4482 toff = offset; 4483 } 4484 4485 if (tosync != 0) { 4486 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4487 toff, tosync * sizeof(struct bge_rx_bd), 4488 BUS_DMASYNC_POSTREAD); 4489 } 4490 4491 while (rx_cons != rx_prod) { 4492 struct bge_rx_bd *cur_rx; 4493 uint32_t rxidx; 4494 struct mbuf *m = NULL; 4495 4496 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4497 4498 rxidx = cur_rx->bge_idx; 4499 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4500 4501 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4502 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4503 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4504 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4505 jumbocnt++; 4506 bus_dmamap_sync(sc->bge_dmatag, 4507 sc->bge_cdata.bge_rx_jumbo_map, 4508 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4509 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4510 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4511 if_statinc(ifp, if_ierrors); 4512 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4513 continue; 4514 } 4515 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4516 NULL) == ENOBUFS) { 4517 if_statinc(ifp, if_ierrors); 4518 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4519 continue; 4520 } 4521 } else { 4522 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4523 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4524 4525 stdcnt++; 4526 sc->bge_std_cnt--; 4527 4528 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4529 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4530 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4531 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4532 4533 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4534 m_free(m); 4535 if_statinc(ifp, if_ierrors); 4536 continue; 4537 } 4538 } 4539 4540 #ifndef __NO_STRICT_ALIGNMENT 4541 /* 4542 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4543 * the Rx buffer has the layer-2 header unaligned. 4544 * If our CPU requires alignment, re-align by copying. 4545 */ 4546 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4547 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4548 cur_rx->bge_len); 4549 m->m_data += ETHER_ALIGN; 4550 } 4551 #endif 4552 4553 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4554 m_set_rcvif(m, ifp); 4555 4556 bge_rxcsum(sc, cur_rx, m); 4557 4558 /* 4559 * If we received a packet with a vlan tag, pass it 4560 * to vlan_input() instead of ether_input(). 4561 */ 4562 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4563 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4564 4565 if_percpuq_enqueue(ifp->if_percpuq, m); 4566 } 4567 4568 sc->bge_rx_saved_considx = rx_cons; 4569 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4570 if (stdcnt) 4571 bge_fill_rx_ring_std(sc); 4572 if (jumbocnt) 4573 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4574 } 4575 4576 static void 4577 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4578 { 4579 4580 if (BGE_IS_57765_PLUS(sc)) { 4581 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4582 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4583 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4584 if ((cur_rx->bge_error_flag & 4585 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4586 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4587 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4588 m->m_pkthdr.csum_data = 4589 cur_rx->bge_tcp_udp_csum; 4590 m->m_pkthdr.csum_flags |= 4591 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4592 } 4593 } 4594 } else { 4595 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4596 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4597 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4598 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4599 /* 4600 * Rx transport checksum-offload may also 4601 * have bugs with packets which, when transmitted, 4602 * were `runts' requiring padding. 4603 */ 4604 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4605 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4606 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4607 m->m_pkthdr.csum_data = 4608 cur_rx->bge_tcp_udp_csum; 4609 m->m_pkthdr.csum_flags |= 4610 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4611 } 4612 } 4613 } 4614 4615 static void 4616 bge_txeof(struct bge_softc *sc) 4617 { 4618 struct ifnet * const ifp = &sc->ethercom.ec_if; 4619 struct bge_tx_bd *cur_tx = NULL; 4620 struct txdmamap_pool_entry *dma; 4621 bus_addr_t offset, toff; 4622 bus_size_t tlen; 4623 int tosync; 4624 struct mbuf *m; 4625 4626 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4627 offsetof(struct bge_ring_data, bge_status_block), 4628 sizeof(struct bge_status_block), 4629 BUS_DMASYNC_POSTREAD); 4630 4631 const uint16_t hw_cons_idx = 4632 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx; 4633 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4634 tosync = hw_cons_idx - sc->bge_tx_saved_considx; 4635 4636 if (tosync != 0) 4637 rnd_add_uint32(&sc->rnd_source, tosync); 4638 4639 toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd)); 4640 4641 if (tosync < 0) { 4642 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4643 sizeof(struct bge_tx_bd); 4644 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4645 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4646 tosync = hw_cons_idx; 4647 toff = offset; 4648 } 4649 4650 if (tosync != 0) { 4651 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4652 toff, tosync * sizeof(struct bge_tx_bd), 4653 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4654 } 4655 4656 /* 4657 * Go through our tx ring and free mbufs for those 4658 * frames that have been sent. 4659 */ 4660 while (sc->bge_tx_saved_considx != hw_cons_idx) { 4661 uint32_t idx = sc->bge_tx_saved_considx; 4662 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4663 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4664 if_statinc(ifp, if_opackets); 4665 m = sc->bge_cdata.bge_tx_chain[idx]; 4666 if (m != NULL) { 4667 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4668 dma = sc->txdma[idx]; 4669 if (dma->is_dma32) { 4670 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4671 0, dma->dmamap32->dm_mapsize, 4672 BUS_DMASYNC_POSTWRITE); 4673 bus_dmamap_unload( 4674 sc->bge_dmatag32, dma->dmamap32); 4675 } else { 4676 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4677 0, dma->dmamap->dm_mapsize, 4678 BUS_DMASYNC_POSTWRITE); 4679 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4680 } 4681 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4682 sc->txdma[idx] = NULL; 4683 4684 m_freem(m); 4685 } 4686 sc->bge_txcnt--; 4687 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4688 sc->bge_tx_sending = false; 4689 } 4690 } 4691 4692 static int 4693 bge_intr(void *xsc) 4694 { 4695 struct bge_softc * const sc = xsc; 4696 struct ifnet * const ifp = &sc->ethercom.ec_if; 4697 uint32_t pcistate, statusword, statustag; 4698 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4699 4700 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4701 if (BGE_IS_5717_PLUS(sc)) 4702 intrmask = 0; 4703 4704 mutex_enter(sc->sc_core_lock); 4705 4706 /* 4707 * It is possible for the interrupt to arrive before 4708 * the status block is updated prior to the interrupt. 4709 * Reading the PCI State register will confirm whether the 4710 * interrupt is ours and will flush the status block. 4711 */ 4712 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4713 4714 /* read status word from status block */ 4715 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4716 offsetof(struct bge_ring_data, bge_status_block), 4717 sizeof(struct bge_status_block), 4718 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4719 statusword = sc->bge_rdata->bge_status_block.bge_status; 4720 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4721 4722 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4723 if (sc->bge_lasttag == statustag && 4724 (~pcistate & intrmask)) { 4725 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4726 mutex_exit(sc->sc_core_lock); 4727 return 0; 4728 } 4729 sc->bge_lasttag = statustag; 4730 } else { 4731 if (!(statusword & BGE_STATFLAG_UPDATED) && 4732 !(~pcistate & intrmask)) { 4733 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4734 mutex_exit(sc->sc_core_lock); 4735 return 0; 4736 } 4737 statustag = 0; 4738 } 4739 /* Ack interrupt and stop others from occurring. */ 4740 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4741 BGE_EVCNT_INCR(sc->bge_ev_intr); 4742 4743 /* clear status word */ 4744 sc->bge_rdata->bge_status_block.bge_status = 0; 4745 4746 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4747 offsetof(struct bge_ring_data, bge_status_block), 4748 sizeof(struct bge_status_block), 4749 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4750 4751 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4752 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4753 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4754 bge_link_upd(sc); 4755 4756 if (sc->bge_if_flags & IFF_RUNNING) { 4757 /* Check RX return ring producer/consumer */ 4758 bge_rxeof(sc); 4759 4760 /* Check TX ring producer/consumer */ 4761 bge_txeof(sc); 4762 } 4763 4764 if (sc->bge_pending_rxintr_change) { 4765 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4766 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4767 4768 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4769 DELAY(10); 4770 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4771 4772 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4773 DELAY(10); 4774 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4775 4776 sc->bge_pending_rxintr_change = false; 4777 } 4778 bge_handle_events(sc); 4779 4780 /* Re-enable interrupts. */ 4781 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4782 4783 if (sc->bge_if_flags & IFF_RUNNING) 4784 if_schedule_deferred_start(ifp); 4785 4786 mutex_exit(sc->sc_core_lock); 4787 4788 return 1; 4789 } 4790 4791 static void 4792 bge_asf_driver_up(struct bge_softc *sc) 4793 { 4794 if (sc->bge_asf_mode & ASF_STACKUP) { 4795 /* Send ASF heartbeat approx. every 2s */ 4796 if (sc->bge_asf_count) 4797 sc->bge_asf_count --; 4798 else { 4799 sc->bge_asf_count = 2; 4800 4801 bge_wait_for_event_ack(sc); 4802 4803 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4804 BGE_FW_CMD_DRV_ALIVE3); 4805 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4806 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4807 BGE_FW_HB_TIMEOUT_SEC); 4808 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4809 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4810 BGE_RX_CPU_DRV_EVENT); 4811 } 4812 } 4813 } 4814 4815 static void 4816 bge_tick(void *xsc) 4817 { 4818 struct bge_softc * const sc = xsc; 4819 struct ifnet * const ifp = &sc->ethercom.ec_if; 4820 struct mii_data * const mii = &sc->bge_mii; 4821 4822 mutex_enter(sc->sc_core_lock); 4823 4824 if (BGE_IS_5705_PLUS(sc)) 4825 bge_stats_update_regs(sc); 4826 else 4827 bge_stats_update(sc); 4828 4829 if (sc->bge_flags & BGEF_FIBER_TBI) { 4830 /* 4831 * Since in TBI mode auto-polling can't be used we should poll 4832 * link status manually. Here we register pending link event 4833 * and trigger interrupt. 4834 */ 4835 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4836 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4837 } else { 4838 /* 4839 * Do not touch PHY if we have link up. This could break 4840 * IPMI/ASF mode or produce extra input errors. 4841 * (extra input errors was reported for bcm5701 & bcm5704). 4842 */ 4843 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 4844 mii_tick(mii); 4845 } 4846 4847 bge_asf_driver_up(sc); 4848 4849 const bool ok = bge_watchdog(ifp); 4850 4851 if (ok && !sc->bge_detaching) 4852 callout_schedule(&sc->bge_timeout, hz); 4853 4854 mutex_exit(sc->sc_core_lock); 4855 } 4856 4857 static void 4858 bge_stats_update_regs(struct bge_softc *sc) 4859 { 4860 struct ifnet * const ifp = &sc->ethercom.ec_if; 4861 4862 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4863 4864 if_statadd_ref(nsr, if_collisions, 4865 CSR_READ_4(sc, BGE_MAC_STATS + 4866 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4867 4868 /* 4869 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4870 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4871 * (silicon bug). There's no reliable workaround so just 4872 * ignore the counter 4873 */ 4874 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4875 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4876 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4877 if_statadd_ref(nsr, if_ierrors, 4878 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4879 } 4880 if_statadd_ref(nsr, if_ierrors, 4881 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4882 if_statadd_ref(nsr, if_ierrors, 4883 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4884 4885 IF_STAT_PUTREF(ifp); 4886 4887 if (sc->bge_flags & BGEF_RDMA_BUG) { 4888 uint32_t val, ucast, mcast, bcast; 4889 4890 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4891 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4892 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4893 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4894 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4895 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4896 4897 /* 4898 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4899 * frames, it's safe to disable workaround for DMA engine's 4900 * miscalculation of TXMBUF space. 4901 */ 4902 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4903 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4904 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4905 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4906 else 4907 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4908 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4909 sc->bge_flags &= ~BGEF_RDMA_BUG; 4910 } 4911 } 4912 } 4913 4914 static void 4915 bge_stats_update(struct bge_softc *sc) 4916 { 4917 struct ifnet * const ifp = &sc->ethercom.ec_if; 4918 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4919 4920 #define READ_STAT(sc, stats, stat) \ 4921 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4922 4923 uint64_t collisions = 4924 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4925 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4926 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4927 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4928 4929 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4930 sc->bge_if_collisions = collisions; 4931 4932 4933 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4934 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4935 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4936 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4937 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4938 READ_STAT(sc, stats, 4939 xoffPauseFramesReceived.bge_addr_lo)); 4940 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4941 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4942 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4943 READ_STAT(sc, stats, 4944 macControlFramesReceived.bge_addr_lo)); 4945 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4946 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4947 4948 #undef READ_STAT 4949 } 4950 4951 /* 4952 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4953 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4954 * but when such padded frames employ the bge IP/TCP checksum offload, 4955 * the hardware checksum assist gives incorrect results (possibly 4956 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4957 * If we pad such runts with zeros, the onboard checksum comes out correct. 4958 */ 4959 static inline int 4960 bge_cksum_pad(struct mbuf *pkt) 4961 { 4962 struct mbuf *last = NULL; 4963 int padlen; 4964 4965 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4966 4967 /* if there's only the packet-header and we can pad there, use it. */ 4968 if (pkt->m_pkthdr.len == pkt->m_len && 4969 M_TRAILINGSPACE(pkt) >= padlen) { 4970 last = pkt; 4971 } else { 4972 /* 4973 * Walk packet chain to find last mbuf. We will either 4974 * pad there, or append a new mbuf and pad it 4975 * (thus perhaps avoiding the bcm5700 dma-min bug). 4976 */ 4977 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4978 continue; /* do nothing */ 4979 } 4980 4981 /* `last' now points to last in chain. */ 4982 if (M_TRAILINGSPACE(last) < padlen) { 4983 /* Allocate new empty mbuf, pad it. Compact later. */ 4984 struct mbuf *n; 4985 MGET(n, M_DONTWAIT, MT_DATA); 4986 if (n == NULL) 4987 return ENOBUFS; 4988 n->m_len = 0; 4989 last->m_next = n; 4990 last = n; 4991 } 4992 } 4993 4994 KDASSERT(!M_READONLY(last)); 4995 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 4996 4997 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 4998 memset(mtod(last, char *) + last->m_len, 0, padlen); 4999 last->m_len += padlen; 5000 pkt->m_pkthdr.len += padlen; 5001 return 0; 5002 } 5003 5004 /* 5005 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5006 */ 5007 static inline int 5008 bge_compact_dma_runt(struct mbuf *pkt) 5009 { 5010 struct mbuf *m, *prev; 5011 int totlen; 5012 5013 prev = NULL; 5014 totlen = 0; 5015 5016 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 5017 int mlen = m->m_len; 5018 int shortfall = 8 - mlen ; 5019 5020 totlen += mlen; 5021 if (mlen == 0) 5022 continue; 5023 if (mlen >= 8) 5024 continue; 5025 5026 /* 5027 * If we get here, mbuf data is too small for DMA engine. 5028 * Try to fix by shuffling data to prev or next in chain. 5029 * If that fails, do a compacting deep-copy of the whole chain. 5030 */ 5031 5032 /* Internal frag. If fits in prev, copy it there. */ 5033 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5034 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5035 prev->m_len += mlen; 5036 m->m_len = 0; 5037 /* XXX stitch chain */ 5038 prev->m_next = m_free(m); 5039 m = prev; 5040 continue; 5041 } else if (m->m_next != NULL && 5042 M_TRAILINGSPACE(m) >= shortfall && 5043 m->m_next->m_len >= (8 + shortfall)) { 5044 /* m is writable and have enough data in next, pull up. */ 5045 5046 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5047 shortfall); 5048 m->m_len += shortfall; 5049 m->m_next->m_len -= shortfall; 5050 m->m_next->m_data += shortfall; 5051 } else if (m->m_next == NULL || 1) { 5052 /* 5053 * Got a runt at the very end of the packet. 5054 * borrow data from the tail of the preceding mbuf and 5055 * update its length in-place. (The original data is 5056 * still valid, so we can do this even if prev is not 5057 * writable.) 5058 */ 5059 5060 /* 5061 * If we'd make prev a runt, just move all of its data. 5062 */ 5063 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5064 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5065 5066 if ((prev->m_len - shortfall) < 8) 5067 shortfall = prev->m_len; 5068 5069 #ifdef notyet /* just do the safe slow thing for now */ 5070 if (!M_READONLY(m)) { 5071 if (M_LEADINGSPACE(m) < shorfall) { 5072 void *m_dat; 5073 m_dat = M_BUFADDR(m); 5074 memmove(m_dat, mtod(m, void*), 5075 m->m_len); 5076 m->m_data = m_dat; 5077 } 5078 } else 5079 #endif /* just do the safe slow thing */ 5080 { 5081 struct mbuf * n = NULL; 5082 int newprevlen = prev->m_len - shortfall; 5083 5084 MGET(n, M_NOWAIT, MT_DATA); 5085 if (n == NULL) 5086 return ENOBUFS; 5087 KASSERT(m->m_len + shortfall < MLEN 5088 /*, 5089 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5090 5091 /* first copy the data we're stealing from prev */ 5092 memcpy(n->m_data, prev->m_data + newprevlen, 5093 shortfall); 5094 5095 /* update prev->m_len accordingly */ 5096 prev->m_len -= shortfall; 5097 5098 /* copy data from runt m */ 5099 memcpy(n->m_data + shortfall, m->m_data, 5100 m->m_len); 5101 5102 /* n holds what we stole from prev, plus m */ 5103 n->m_len = shortfall + m->m_len; 5104 5105 /* stitch n into chain and free m */ 5106 n->m_next = m->m_next; 5107 prev->m_next = n; 5108 /* KASSERT(m->m_next == NULL); */ 5109 m->m_next = NULL; 5110 m_free(m); 5111 m = n; /* for continuing loop */ 5112 } 5113 } 5114 } 5115 return 0; 5116 } 5117 5118 /* 5119 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5120 * pointers to descriptors. 5121 */ 5122 static int 5123 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5124 { 5125 struct bge_tx_bd *f, *prev_f; 5126 uint32_t frag, cur; 5127 uint16_t csum_flags = 0; 5128 uint16_t txbd_tso_flags = 0; 5129 struct txdmamap_pool_entry *dma; 5130 bus_dmamap_t dmamap; 5131 bus_dma_tag_t dmatag; 5132 int i = 0; 5133 int use_tso, maxsegsize, error; 5134 bool have_vtag; 5135 uint16_t vtag; 5136 bool remap; 5137 5138 if (m_head->m_pkthdr.csum_flags) { 5139 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5140 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5141 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5142 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5143 } 5144 5145 /* 5146 * If we were asked to do an outboard checksum, and the NIC 5147 * has the bug where it sometimes adds in the Ethernet padding, 5148 * explicitly pad with zeros so the cksum will be correct either way. 5149 * (For now, do this for all chip versions, until newer 5150 * are confirmed to not require the workaround.) 5151 */ 5152 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5153 #ifdef notyet 5154 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5155 #endif 5156 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5157 goto check_dma_bug; 5158 5159 if (bge_cksum_pad(m_head) != 0) 5160 return ENOBUFS; 5161 5162 check_dma_bug: 5163 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5164 goto doit; 5165 5166 /* 5167 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5168 * less than eight bytes. If we encounter a teeny mbuf 5169 * at the end of a chain, we can pad. Otherwise, copy. 5170 */ 5171 if (bge_compact_dma_runt(m_head) != 0) 5172 return ENOBUFS; 5173 5174 doit: 5175 dma = SLIST_FIRST(&sc->txdma_list); 5176 if (dma == NULL) { 5177 return ENOBUFS; 5178 } 5179 dmamap = dma->dmamap; 5180 dmatag = sc->bge_dmatag; 5181 dma->is_dma32 = false; 5182 5183 /* 5184 * Set up any necessary TSO state before we start packing... 5185 */ 5186 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5187 if (!use_tso) { 5188 maxsegsize = 0; 5189 } else { /* TSO setup */ 5190 unsigned mss; 5191 struct ether_header *eh; 5192 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5193 unsigned bge_hlen; 5194 struct mbuf * m0 = m_head; 5195 struct ip *ip; 5196 struct tcphdr *th; 5197 int iphl, hlen; 5198 5199 /* 5200 * XXX It would be nice if the mbuf pkthdr had offset 5201 * fields for the protocol headers. 5202 */ 5203 5204 eh = mtod(m0, struct ether_header *); 5205 switch (htons(eh->ether_type)) { 5206 case ETHERTYPE_IP: 5207 offset = ETHER_HDR_LEN; 5208 break; 5209 5210 case ETHERTYPE_VLAN: 5211 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5212 break; 5213 5214 default: 5215 /* 5216 * Don't support this protocol or encapsulation. 5217 */ 5218 return ENOBUFS; 5219 } 5220 5221 /* 5222 * TCP/IP headers are in the first mbuf; we can do 5223 * this the easy way. 5224 */ 5225 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5226 hlen = iphl + offset; 5227 if (__predict_false(m0->m_len < 5228 (hlen + sizeof(struct tcphdr)))) { 5229 5230 aprint_error_dev(sc->bge_dev, 5231 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5232 "not handled yet\n", 5233 m0->m_len, hlen+ sizeof(struct tcphdr)); 5234 #ifdef NOTYET 5235 /* 5236 * XXX jonathan (at) NetBSD.org: untested. 5237 * how to force this branch to be taken? 5238 */ 5239 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5240 5241 m_copydata(m0, offset, sizeof(ip), &ip); 5242 m_copydata(m0, hlen, sizeof(th), &th); 5243 5244 ip.ip_len = 0; 5245 5246 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5247 sizeof(ip.ip_len), &ip.ip_len); 5248 5249 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5250 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5251 5252 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5253 sizeof(th.th_sum), &th.th_sum); 5254 5255 hlen += th.th_off << 2; 5256 iptcp_opt_words = hlen; 5257 #else 5258 /* 5259 * if_wm "hard" case not yet supported, can we not 5260 * mandate it out of existence? 5261 */ 5262 (void) ip; (void)th; (void) ip_tcp_hlen; 5263 5264 return ENOBUFS; 5265 #endif 5266 } else { 5267 ip = (struct ip *) (mtod(m0, char *) + offset); 5268 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5269 ip_tcp_hlen = iphl + (th->th_off << 2); 5270 5271 /* Total IP/TCP options, in 32-bit words */ 5272 iptcp_opt_words = (ip_tcp_hlen 5273 - sizeof(struct tcphdr) 5274 - sizeof(struct ip)) >> 2; 5275 } 5276 if (BGE_IS_575X_PLUS(sc)) { 5277 th->th_sum = 0; 5278 csum_flags = 0; 5279 } else { 5280 /* 5281 * XXX jonathan (at) NetBSD.org: 5705 untested. 5282 * Requires TSO firmware patch for 5701/5703/5704. 5283 */ 5284 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5285 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5286 } 5287 5288 mss = m_head->m_pkthdr.segsz; 5289 txbd_tso_flags |= 5290 BGE_TXBDFLAG_CPU_PRE_DMA | 5291 BGE_TXBDFLAG_CPU_POST_DMA; 5292 5293 /* 5294 * Our NIC TSO-assist assumes TSO has standard, optionless 5295 * IPv4 and TCP headers, which total 40 bytes. By default, 5296 * the NIC copies 40 bytes of IP/TCP header from the 5297 * supplied header into the IP/TCP header portion of 5298 * each post-TSO-segment. If the supplied packet has IP or 5299 * TCP options, we need to tell the NIC to copy those extra 5300 * bytes into each post-TSO header, in addition to the normal 5301 * 40-byte IP/TCP header (and to leave space accordingly). 5302 * Unfortunately, the driver encoding of option length 5303 * varies across different ASIC families. 5304 */ 5305 tcp_seg_flags = 0; 5306 bge_hlen = ip_tcp_hlen >> 2; 5307 if (BGE_IS_5717_PLUS(sc)) { 5308 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5309 txbd_tso_flags |= 5310 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5311 } else if (BGE_IS_5705_PLUS(sc)) { 5312 tcp_seg_flags = bge_hlen << 11; 5313 } else { 5314 /* XXX iptcp_opt_words or bge_hlen ? */ 5315 txbd_tso_flags |= iptcp_opt_words << 12; 5316 } 5317 maxsegsize = mss | tcp_seg_flags; 5318 ip->ip_len = htons(mss + ip_tcp_hlen); 5319 ip->ip_sum = 0; 5320 5321 } /* TSO setup */ 5322 5323 have_vtag = vlan_has_tag(m_head); 5324 if (have_vtag) 5325 vtag = vlan_get_tag(m_head); 5326 5327 /* 5328 * Start packing the mbufs in this chain into 5329 * the fragment pointers. Stop when we run out 5330 * of fragments or hit the end of the mbuf chain. 5331 */ 5332 remap = true; 5333 load_again: 5334 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5335 if (__predict_false(error)) { 5336 if (error == EFBIG && remap) { 5337 struct mbuf *m; 5338 remap = false; 5339 m = m_defrag(m_head, M_NOWAIT); 5340 if (m != NULL) { 5341 KASSERT(m == m_head); 5342 goto load_again; 5343 } 5344 } 5345 return error; 5346 } 5347 /* 5348 * Sanity check: avoid coming within 16 descriptors 5349 * of the end of the ring. 5350 */ 5351 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5352 BGE_TSO_PRINTF(("%s: " 5353 " dmamap_load_mbuf too close to ring wrap\n", 5354 device_xname(sc->bge_dev))); 5355 goto fail_unload; 5356 } 5357 5358 /* Iterate over dmap-map fragments. */ 5359 f = prev_f = NULL; 5360 cur = frag = *txidx; 5361 5362 for (i = 0; i < dmamap->dm_nsegs; i++) { 5363 f = &sc->bge_rdata->bge_tx_ring[frag]; 5364 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5365 break; 5366 5367 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5368 f->bge_len = dmamap->dm_segs[i].ds_len; 5369 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5370 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5371 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5372 (prev_f != NULL && 5373 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5374 ) { 5375 /* 5376 * watchdog timeout issue was observed with TSO, 5377 * limiting DMA address space to 32bits seems to 5378 * address the issue. 5379 */ 5380 bus_dmamap_unload(dmatag, dmamap); 5381 dmatag = sc->bge_dmatag32; 5382 dmamap = dma->dmamap32; 5383 dma->is_dma32 = true; 5384 remap = true; 5385 goto load_again; 5386 } 5387 5388 /* 5389 * For 5751 and follow-ons, for TSO we must turn 5390 * off checksum-assist flag in the tx-descr, and 5391 * supply the ASIC-revision-specific encoding 5392 * of TSO flags and segsize. 5393 */ 5394 if (use_tso) { 5395 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5396 f->bge_rsvd = maxsegsize; 5397 f->bge_flags = csum_flags | txbd_tso_flags; 5398 } else { 5399 f->bge_rsvd = 0; 5400 f->bge_flags = 5401 (csum_flags | txbd_tso_flags) & 0x0fff; 5402 } 5403 } else { 5404 f->bge_rsvd = 0; 5405 f->bge_flags = csum_flags; 5406 } 5407 5408 if (have_vtag) { 5409 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5410 f->bge_vlan_tag = vtag; 5411 } else { 5412 f->bge_vlan_tag = 0; 5413 } 5414 prev_f = f; 5415 cur = frag; 5416 BGE_INC(frag, BGE_TX_RING_CNT); 5417 } 5418 5419 if (i < dmamap->dm_nsegs) { 5420 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5421 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5422 goto fail_unload; 5423 } 5424 5425 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5426 BUS_DMASYNC_PREWRITE); 5427 5428 if (frag == sc->bge_tx_saved_considx) { 5429 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5430 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5431 5432 goto fail_unload; 5433 } 5434 5435 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5436 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5437 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5438 sc->txdma[cur] = dma; 5439 sc->bge_txcnt += dmamap->dm_nsegs; 5440 5441 *txidx = frag; 5442 5443 return 0; 5444 5445 fail_unload: 5446 bus_dmamap_unload(dmatag, dmamap); 5447 5448 return ENOBUFS; 5449 } 5450 5451 5452 static void 5453 bge_start(struct ifnet *ifp) 5454 { 5455 struct bge_softc * const sc = ifp->if_softc; 5456 5457 mutex_enter(sc->sc_core_lock); 5458 bge_start_locked(ifp); 5459 mutex_exit(sc->sc_core_lock); 5460 } 5461 5462 /* 5463 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5464 * to the mbuf data regions directly in the transmit descriptors. 5465 */ 5466 static void 5467 bge_start_locked(struct ifnet *ifp) 5468 { 5469 struct bge_softc * const sc = ifp->if_softc; 5470 struct mbuf *m_head = NULL; 5471 struct mbuf *m; 5472 uint32_t prodidx; 5473 int pkts = 0; 5474 int error; 5475 5476 if ((sc->bge_if_flags & IFF_RUNNING) != IFF_RUNNING) 5477 return; 5478 5479 prodidx = sc->bge_tx_prodidx; 5480 5481 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5482 IFQ_POLL(&ifp->if_snd, m_head); 5483 if (m_head == NULL) 5484 break; 5485 5486 #if 0 5487 /* 5488 * XXX 5489 * safety overkill. If this is a fragmented packet chain 5490 * with delayed TCP/UDP checksums, then only encapsulate 5491 * it if we have enough descriptors to handle the entire 5492 * chain at once. 5493 * (paranoia -- may not actually be needed) 5494 */ 5495 if (m_head->m_flags & M_FIRSTFRAG && 5496 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5497 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5498 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5499 ifp->if_flags |= IFF_OACTIVE; 5500 break; 5501 } 5502 } 5503 #endif 5504 5505 /* 5506 * Pack the data into the transmit ring. If we 5507 * don't have room, set the OACTIVE flag and wait 5508 * for the NIC to drain the ring. 5509 */ 5510 error = bge_encap(sc, m_head, &prodidx); 5511 if (__predict_false(error)) { 5512 if (SLIST_EMPTY(&sc->txdma_list)) { 5513 /* just wait for the transmit ring to drain */ 5514 break; 5515 } 5516 IFQ_DEQUEUE(&ifp->if_snd, m); 5517 KASSERT(m == m_head); 5518 m_freem(m_head); 5519 continue; 5520 } 5521 5522 /* now we are committed to transmit the packet */ 5523 IFQ_DEQUEUE(&ifp->if_snd, m); 5524 KASSERT(m == m_head); 5525 pkts++; 5526 5527 /* 5528 * If there's a BPF listener, bounce a copy of this frame 5529 * to him. 5530 */ 5531 bpf_mtap(ifp, m_head, BPF_D_OUT); 5532 } 5533 if (pkts == 0) 5534 return; 5535 5536 /* Transmit */ 5537 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5538 /* 5700 b2 errata */ 5539 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5540 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5541 5542 sc->bge_tx_prodidx = prodidx; 5543 sc->bge_tx_lastsent = time_uptime; 5544 sc->bge_tx_sending = true; 5545 } 5546 5547 static int 5548 bge_init(struct ifnet *ifp) 5549 { 5550 struct bge_softc * const sc = ifp->if_softc; 5551 5552 mutex_enter(sc->sc_core_lock); 5553 int ret = bge_init_locked(ifp); 5554 mutex_exit(sc->sc_core_lock); 5555 5556 return ret; 5557 } 5558 5559 5560 static int 5561 bge_init_locked(struct ifnet *ifp) 5562 { 5563 struct bge_softc * const sc = ifp->if_softc; 5564 const uint16_t *m; 5565 uint32_t mode, reg; 5566 int error = 0; 5567 5568 KASSERT(IFNET_LOCKED(ifp)); 5569 KASSERT(mutex_owned(sc->sc_core_lock)); 5570 KASSERT(ifp == &sc->ethercom.ec_if); 5571 5572 /* Cancel pending I/O and flush buffers. */ 5573 bge_stop_locked(ifp, 0); 5574 5575 bge_stop_fw(sc); 5576 bge_sig_pre_reset(sc, BGE_RESET_START); 5577 bge_reset(sc); 5578 bge_sig_legacy(sc, BGE_RESET_START); 5579 5580 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5581 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5582 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5583 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5584 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5585 5586 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5587 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5588 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5589 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5590 5591 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5592 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5593 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5594 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5595 5596 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5597 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5598 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5599 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5600 } 5601 5602 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5603 pcireg_t aercap; 5604 5605 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5606 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5607 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5608 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5609 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5610 5611 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5612 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5613 | BGE_PCIE_EIDLE_DELAY_13CLK; 5614 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5615 5616 /* Clear correctable error */ 5617 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5618 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5619 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5620 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5621 5622 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5623 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5624 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5625 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5626 } 5627 5628 bge_sig_post_reset(sc, BGE_RESET_START); 5629 5630 bge_chipinit(sc); 5631 5632 /* 5633 * Init the various state machines, ring 5634 * control blocks and firmware. 5635 */ 5636 error = bge_blockinit(sc); 5637 if (error != 0) { 5638 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5639 error); 5640 return error; 5641 } 5642 5643 /* 5718 step 25, 57XX step 54 */ 5644 /* Specify MTU. */ 5645 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5646 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5647 5648 /* 5718 step 23 */ 5649 /* Load our MAC address. */ 5650 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5651 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5652 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5653 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5654 5655 /* Enable or disable promiscuous mode as needed. */ 5656 if (ifp->if_flags & IFF_PROMISC) 5657 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5658 else 5659 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5660 5661 /* Program multicast filter. */ 5662 bge_setmulti(sc); 5663 5664 /* Init RX ring. */ 5665 bge_init_rx_ring_std(sc); 5666 5667 /* 5668 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5669 * memory to insure that the chip has in fact read the first 5670 * entry of the ring. 5671 */ 5672 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5673 u_int i; 5674 for (i = 0; i < 10; i++) { 5675 DELAY(20); 5676 uint32_t v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5677 if (v == (MCLBYTES - ETHER_ALIGN)) 5678 break; 5679 } 5680 if (i == 10) 5681 aprint_error_dev(sc->bge_dev, 5682 "5705 A0 chip failed to load RX ring\n"); 5683 } 5684 5685 /* Init jumbo RX ring. */ 5686 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5687 bge_init_rx_ring_jumbo(sc); 5688 5689 /* Init our RX return ring index */ 5690 sc->bge_rx_saved_considx = 0; 5691 5692 /* Init TX ring. */ 5693 bge_init_tx_ring(sc); 5694 5695 /* 5718 step 63, 57XX step 94 */ 5696 /* Enable TX MAC state machine lockup fix. */ 5697 mode = CSR_READ_4(sc, BGE_TX_MODE); 5698 if (BGE_IS_5755_PLUS(sc) || 5699 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5700 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5701 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5702 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5703 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5704 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5705 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5706 } 5707 5708 /* Turn on transmitter */ 5709 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5710 /* 5718 step 64 */ 5711 DELAY(100); 5712 5713 /* 5718 step 65, 57XX step 95 */ 5714 /* Turn on receiver */ 5715 mode = CSR_READ_4(sc, BGE_RX_MODE); 5716 if (BGE_IS_5755_PLUS(sc)) 5717 mode |= BGE_RXMODE_IPV6_ENABLE; 5718 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5719 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5720 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5721 /* 5718 step 66 */ 5722 DELAY(10); 5723 5724 /* 5718 step 12, 57XX step 37 */ 5725 /* 5726 * XXX Doucments of 5718 series and 577xx say the recommended value 5727 * is 1, but tg3 set 1 only on 57765 series. 5728 */ 5729 if (BGE_IS_57765_PLUS(sc)) 5730 reg = 1; 5731 else 5732 reg = 2; 5733 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5734 5735 /* Tell firmware we're alive. */ 5736 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5737 5738 /* Enable host interrupts. */ 5739 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5740 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5741 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5742 5743 if ((error = bge_ifmedia_upd(ifp)) != 0) 5744 goto out; 5745 5746 /* IFNET_LOCKED asserted above */ 5747 ifp->if_flags |= IFF_RUNNING; 5748 5749 callout_schedule(&sc->bge_timeout, hz); 5750 5751 out: 5752 sc->bge_if_flags = ifp->if_flags; 5753 5754 return error; 5755 } 5756 5757 /* 5758 * Set media options. 5759 */ 5760 static int 5761 bge_ifmedia_upd(struct ifnet *ifp) 5762 { 5763 struct bge_softc * const sc = ifp->if_softc; 5764 struct mii_data * const mii = &sc->bge_mii; 5765 struct ifmedia * const ifm = &sc->bge_ifmedia; 5766 int rc; 5767 5768 /* If this is a 1000baseX NIC, enable the TBI port. */ 5769 if (sc->bge_flags & BGEF_FIBER_TBI) { 5770 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5771 return EINVAL; 5772 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5773 case IFM_AUTO: 5774 /* 5775 * The BCM5704 ASIC appears to have a special 5776 * mechanism for programming the autoneg 5777 * advertisement registers in TBI mode. 5778 */ 5779 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5780 uint32_t sgdig; 5781 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5782 if (sgdig & BGE_SGDIGSTS_DONE) { 5783 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5784 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5785 sgdig |= BGE_SGDIGCFG_AUTO | 5786 BGE_SGDIGCFG_PAUSE_CAP | 5787 BGE_SGDIGCFG_ASYM_PAUSE; 5788 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5789 sgdig | BGE_SGDIGCFG_SEND); 5790 DELAY(5); 5791 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5792 sgdig); 5793 } 5794 } 5795 break; 5796 case IFM_1000_SX: 5797 if ((ifm->ifm_media & IFM_FDX) != 0) { 5798 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5799 BGE_MACMODE_HALF_DUPLEX); 5800 } else { 5801 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5802 BGE_MACMODE_HALF_DUPLEX); 5803 } 5804 DELAY(40); 5805 break; 5806 default: 5807 return EINVAL; 5808 } 5809 /* XXX 802.3x flow control for 1000BASE-SX */ 5810 return 0; 5811 } 5812 5813 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5814 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5815 uint32_t reg; 5816 5817 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5818 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5819 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5820 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5821 } 5822 } 5823 5824 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5825 if ((rc = mii_mediachg(mii)) == ENXIO) 5826 return 0; 5827 5828 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5829 uint32_t reg; 5830 5831 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5832 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5833 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5834 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5835 delay(40); 5836 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5837 } 5838 } 5839 5840 /* 5841 * Force an interrupt so that we will call bge_link_upd 5842 * if needed and clear any pending link state attention. 5843 * Without this we are not getting any further interrupts 5844 * for link state changes and thus will not UP the link and 5845 * not be able to send in bge_start. The only way to get 5846 * things working was to receive a packet and get a RX intr. 5847 */ 5848 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5849 sc->bge_flags & BGEF_IS_5788) 5850 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5851 else 5852 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5853 5854 return rc; 5855 } 5856 5857 /* 5858 * Report current media status. 5859 */ 5860 static void 5861 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5862 { 5863 struct bge_softc * const sc = ifp->if_softc; 5864 struct mii_data * const mii = &sc->bge_mii; 5865 5866 if (sc->bge_flags & BGEF_FIBER_TBI) { 5867 ifmr->ifm_status = IFM_AVALID; 5868 ifmr->ifm_active = IFM_ETHER; 5869 if (CSR_READ_4(sc, BGE_MAC_STS) & 5870 BGE_MACSTAT_TBI_PCS_SYNCHED) 5871 ifmr->ifm_status |= IFM_ACTIVE; 5872 ifmr->ifm_active |= IFM_1000_SX; 5873 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5874 ifmr->ifm_active |= IFM_HDX; 5875 else 5876 ifmr->ifm_active |= IFM_FDX; 5877 return; 5878 } 5879 5880 mii_pollstat(mii); 5881 ifmr->ifm_status = mii->mii_media_status; 5882 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5883 sc->bge_flowflags; 5884 } 5885 5886 static int 5887 bge_ifflags_cb(struct ethercom *ec) 5888 { 5889 struct ifnet * const ifp = &ec->ec_if; 5890 struct bge_softc * const sc = ifp->if_softc; 5891 int ret = 0; 5892 5893 KASSERT(IFNET_LOCKED(ifp)); 5894 mutex_enter(sc->sc_core_lock); 5895 5896 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5897 5898 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 5899 ret = ENETRESET; 5900 } else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 5901 if ((ifp->if_flags & IFF_PROMISC) == 0) 5902 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5903 else 5904 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5905 5906 bge_setmulti(sc); 5907 } 5908 5909 sc->bge_if_flags = ifp->if_flags; 5910 mutex_exit(sc->sc_core_lock); 5911 5912 return ret; 5913 } 5914 5915 static int 5916 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5917 { 5918 struct bge_softc * const sc = ifp->if_softc; 5919 struct ifreq * const ifr = (struct ifreq *) data; 5920 int error = 0; 5921 5922 switch (command) { 5923 case SIOCADDMULTI: 5924 case SIOCDELMULTI: 5925 break; 5926 default: 5927 KASSERT(IFNET_LOCKED(ifp)); 5928 } 5929 5930 const int s = splnet(); 5931 5932 switch (command) { 5933 case SIOCSIFMEDIA: 5934 mutex_enter(sc->sc_core_lock); 5935 /* XXX Flow control is not supported for 1000BASE-SX */ 5936 if (sc->bge_flags & BGEF_FIBER_TBI) { 5937 ifr->ifr_media &= ~IFM_ETH_FMASK; 5938 sc->bge_flowflags = 0; 5939 } 5940 5941 /* Flow control requires full-duplex mode. */ 5942 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5943 (ifr->ifr_media & IFM_FDX) == 0) { 5944 ifr->ifr_media &= ~IFM_ETH_FMASK; 5945 } 5946 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5947 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5948 /* We can do both TXPAUSE and RXPAUSE. */ 5949 ifr->ifr_media |= 5950 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5951 } 5952 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5953 } 5954 mutex_exit(sc->sc_core_lock); 5955 5956 if (sc->bge_flags & BGEF_FIBER_TBI) { 5957 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5958 command); 5959 } else { 5960 struct mii_data * const mii = &sc->bge_mii; 5961 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5962 command); 5963 } 5964 break; 5965 default: 5966 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5967 break; 5968 5969 error = 0; 5970 5971 if (command == SIOCADDMULTI || command == SIOCDELMULTI) { 5972 mutex_enter(sc->sc_core_lock); 5973 if (sc->bge_if_flags & IFF_RUNNING) { 5974 bge_setmulti(sc); 5975 } 5976 mutex_exit(sc->sc_core_lock); 5977 } 5978 break; 5979 } 5980 5981 splx(s); 5982 5983 return error; 5984 } 5985 5986 static bool 5987 bge_watchdog_check(struct bge_softc * const sc) 5988 { 5989 5990 KASSERT(mutex_owned(sc->sc_core_lock)); 5991 5992 if (!sc->bge_tx_sending) 5993 return true; 5994 5995 if (time_uptime - sc->bge_tx_lastsent <= bge_watchdog_timeout) 5996 return true; 5997 5998 /* If pause frames are active then don't reset the hardware. */ 5999 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 6000 const uint32_t status = CSR_READ_4(sc, BGE_RX_STS); 6001 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 6002 /* 6003 * If link partner has us in XOFF state then wait for 6004 * the condition to clear. 6005 */ 6006 CSR_WRITE_4(sc, BGE_RX_STS, status); 6007 sc->bge_tx_lastsent = time_uptime; 6008 return true; 6009 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 6010 (status & BGE_RXSTAT_RCVD_XON) != 0) { 6011 /* 6012 * If link partner has us in XOFF state then wait for 6013 * the condition to clear. 6014 */ 6015 CSR_WRITE_4(sc, BGE_RX_STS, status); 6016 sc->bge_tx_lastsent = time_uptime; 6017 return true; 6018 } 6019 /* 6020 * Any other condition is unexpected and the controller 6021 * should be reset. 6022 */ 6023 } 6024 6025 return false; 6026 } 6027 6028 static bool 6029 bge_watchdog(struct ifnet *ifp) 6030 { 6031 struct bge_softc * const sc = ifp->if_softc; 6032 6033 KASSERT(mutex_owned(sc->sc_core_lock)); 6034 6035 if (!sc->sc_trigger_reset && bge_watchdog_check(sc)) 6036 return true; 6037 6038 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 6039 6040 if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0) 6041 workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL); 6042 6043 return false; 6044 } 6045 6046 /* 6047 * Perform an interface watchdog reset. 6048 */ 6049 static void 6050 bge_handle_reset_work(struct work *work, void *arg) 6051 { 6052 struct bge_softc * const sc = arg; 6053 struct ifnet * const ifp = &sc->ethercom.ec_if; 6054 6055 /* Don't want ioctl operations to happen */ 6056 IFNET_LOCK(ifp); 6057 6058 /* reset the interface. */ 6059 bge_init(ifp); 6060 6061 IFNET_UNLOCK(ifp); 6062 6063 /* 6064 * There are still some upper layer processing which call 6065 * ifp->if_start(). e.g. ALTQ or one CPU system 6066 */ 6067 /* Try to get more packets going. */ 6068 ifp->if_start(ifp); 6069 6070 atomic_store_relaxed(&sc->sc_reset_pending, 0); 6071 } 6072 6073 static void 6074 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 6075 { 6076 int i; 6077 6078 BGE_CLRBIT_FLUSH(sc, reg, bit); 6079 6080 for (i = 0; i < 1000; i++) { 6081 delay(100); 6082 if ((CSR_READ_4(sc, reg) & bit) == 0) 6083 return; 6084 } 6085 6086 /* 6087 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 6088 * on some environment (and once after boot?) 6089 */ 6090 if (reg != BGE_SRS_MODE) 6091 aprint_error_dev(sc->bge_dev, 6092 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 6093 (u_long)reg, bit); 6094 } 6095 6096 6097 static void 6098 bge_stop(struct ifnet *ifp, int disable) 6099 { 6100 struct bge_softc * const sc = ifp->if_softc; 6101 6102 ASSERT_SLEEPABLE(); 6103 6104 mutex_enter(sc->sc_core_lock); 6105 bge_stop_locked(ifp, disable); 6106 mutex_exit(sc->sc_core_lock); 6107 } 6108 6109 /* 6110 * Stop the adapter and free any mbufs allocated to the 6111 * RX and TX lists. 6112 */ 6113 static void 6114 bge_stop_locked(struct ifnet *ifp, int disable) 6115 { 6116 struct bge_softc * const sc = ifp->if_softc; 6117 6118 KASSERT(mutex_owned(sc->sc_core_lock)); 6119 6120 if (disable) { 6121 sc->bge_detaching = true; 6122 callout_halt(&sc->bge_timeout, NULL); 6123 } else 6124 callout_stop(&sc->bge_timeout); 6125 6126 /* Disable host interrupts. */ 6127 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6128 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6129 6130 /* 6131 * Tell firmware we're shutting down. 6132 */ 6133 bge_stop_fw(sc); 6134 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6135 6136 /* 6137 * Disable all of the receiver blocks. 6138 */ 6139 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6140 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6141 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6142 if (BGE_IS_5700_FAMILY(sc)) 6143 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6144 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6145 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6146 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6147 6148 /* 6149 * Disable all of the transmit blocks. 6150 */ 6151 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6152 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6153 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6154 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6155 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6156 if (BGE_IS_5700_FAMILY(sc)) 6157 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6158 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6159 6160 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6161 delay(40); 6162 6163 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6164 6165 /* 6166 * Shut down all of the memory managers and related 6167 * state machines. 6168 */ 6169 /* 5718 step 5a,5b */ 6170 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6171 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6172 if (BGE_IS_5700_FAMILY(sc)) 6173 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6174 6175 /* 5718 step 5c,5d */ 6176 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6177 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6178 6179 if (BGE_IS_5700_FAMILY(sc)) { 6180 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6181 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6182 } 6183 6184 bge_reset(sc); 6185 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6186 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6187 6188 /* 6189 * Keep the ASF firmware running if up. 6190 */ 6191 if (sc->bge_asf_mode & ASF_STACKUP) 6192 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6193 else 6194 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6195 6196 /* Free the RX lists. */ 6197 bge_free_rx_ring_std(sc); 6198 6199 /* Free jumbo RX list. */ 6200 if (BGE_IS_JUMBO_CAPABLE(sc)) 6201 bge_free_rx_ring_jumbo(sc); 6202 6203 /* Free TX buffers. */ 6204 bge_free_tx_ring(sc, disable); 6205 6206 /* 6207 * Isolate/power down the PHY. 6208 */ 6209 if (!(sc->bge_flags & BGEF_FIBER_TBI)) 6210 mii_down(&sc->bge_mii); 6211 6212 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6213 6214 /* Clear MAC's link state (PHY may still have link UP). */ 6215 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6216 6217 ifp->if_flags &= ~IFF_RUNNING; 6218 } 6219 6220 static void 6221 bge_link_upd(struct bge_softc *sc) 6222 { 6223 struct ifnet * const ifp = &sc->ethercom.ec_if; 6224 struct mii_data * const mii = &sc->bge_mii; 6225 uint32_t status; 6226 uint16_t phyval; 6227 int link; 6228 6229 /* Clear 'pending link event' flag */ 6230 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6231 6232 /* 6233 * Process link state changes. 6234 * Grrr. The link status word in the status block does 6235 * not work correctly on the BCM5700 rev AX and BX chips, 6236 * according to all available information. Hence, we have 6237 * to enable MII interrupts in order to properly obtain 6238 * async link changes. Unfortunately, this also means that 6239 * we have to read the MAC status register to detect link 6240 * changes, thereby adding an additional register access to 6241 * the interrupt handler. 6242 */ 6243 6244 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6245 status = CSR_READ_4(sc, BGE_MAC_STS); 6246 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6247 mii_pollstat(mii); 6248 6249 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6250 mii->mii_media_status & IFM_ACTIVE && 6251 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6252 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6253 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6254 (!(mii->mii_media_status & IFM_ACTIVE) || 6255 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6256 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6257 6258 /* Clear the interrupt */ 6259 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6260 BGE_EVTENB_MI_INTERRUPT); 6261 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6262 BRGPHY_MII_ISR, &phyval); 6263 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6264 BRGPHY_MII_IMR, BRGPHY_INTRS); 6265 } 6266 return; 6267 } 6268 6269 if (sc->bge_flags & BGEF_FIBER_TBI) { 6270 status = CSR_READ_4(sc, BGE_MAC_STS); 6271 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6272 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6273 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6274 if (BGE_ASICREV(sc->bge_chipid) 6275 == BGE_ASICREV_BCM5704) { 6276 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6277 BGE_MACMODE_TBI_SEND_CFGS); 6278 DELAY(40); 6279 } 6280 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6281 if_link_state_change(ifp, LINK_STATE_UP); 6282 } 6283 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6284 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6285 if_link_state_change(ifp, LINK_STATE_DOWN); 6286 } 6287 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6288 /* 6289 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6290 * bit in status word always set. Workaround this bug by 6291 * reading PHY link status directly. 6292 */ 6293 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6294 BGE_STS_LINK : 0; 6295 6296 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6297 mii_pollstat(mii); 6298 6299 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6300 mii->mii_media_status & IFM_ACTIVE && 6301 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6302 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6303 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6304 (!(mii->mii_media_status & IFM_ACTIVE) || 6305 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6306 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6307 } 6308 } else { 6309 /* 6310 * For controllers that call mii_tick, we have to poll 6311 * link status. 6312 */ 6313 mii_pollstat(mii); 6314 } 6315 6316 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6317 uint32_t reg, scale; 6318 6319 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6320 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6321 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6322 scale = 65; 6323 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6324 scale = 6; 6325 else 6326 scale = 12; 6327 6328 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6329 ~BGE_MISCCFG_TIMER_PRESCALER; 6330 reg |= scale << 1; 6331 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6332 } 6333 /* Clear the attention */ 6334 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6335 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6336 BGE_MACSTAT_LINK_CHANGED); 6337 } 6338 6339 static int 6340 bge_sysctl_verify(SYSCTLFN_ARGS) 6341 { 6342 int error, t; 6343 struct sysctlnode node; 6344 6345 node = *rnode; 6346 t = *(int*)rnode->sysctl_data; 6347 node.sysctl_data = &t; 6348 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6349 if (error || newp == NULL) 6350 return error; 6351 6352 #if 0 6353 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6354 node.sysctl_num, rnode->sysctl_num)); 6355 #endif 6356 6357 if (node.sysctl_num == bge_rxthresh_nodenum) { 6358 if (t < 0 || t >= NBGE_RX_THRESH) 6359 return EINVAL; 6360 bge_update_all_threshes(t); 6361 } else 6362 return EINVAL; 6363 6364 *(int*)rnode->sysctl_data = t; 6365 6366 return 0; 6367 } 6368 6369 /* 6370 * Set up sysctl(3) MIB, hw.bge.*. 6371 */ 6372 static void 6373 bge_sysctl_init(struct bge_softc *sc) 6374 { 6375 int rc, bge_root_num; 6376 const struct sysctlnode *node; 6377 6378 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6379 0, CTLTYPE_NODE, "bge", 6380 SYSCTL_DESCR("BGE interface controls"), 6381 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6382 goto out; 6383 } 6384 6385 bge_root_num = node->sysctl_num; 6386 6387 /* BGE Rx interrupt mitigation level */ 6388 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6389 CTLFLAG_READWRITE, 6390 CTLTYPE_INT, "rx_lvl", 6391 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6392 bge_sysctl_verify, 0, 6393 &bge_rx_thresh_lvl, 6394 0, CTL_HW, bge_root_num, CTL_CREATE, 6395 CTL_EOL)) != 0) { 6396 goto out; 6397 } 6398 6399 bge_rxthresh_nodenum = node->sysctl_num; 6400 6401 #ifdef BGE_DEBUG 6402 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6403 CTLFLAG_READWRITE, 6404 CTLTYPE_BOOL, "trigger_reset", 6405 SYSCTL_DESCR("Trigger an interface reset"), 6406 NULL, 0, &sc->sc_trigger_reset, 0, CTL_CREATE, 6407 CTL_EOL)) != 0) { 6408 goto out; 6409 } 6410 #endif 6411 return; 6412 6413 out: 6414 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6415 } 6416 6417 #ifdef BGE_DEBUG 6418 void 6419 bge_debug_info(struct bge_softc *sc) 6420 { 6421 6422 printf("Hardware Flags:\n"); 6423 if (BGE_IS_57765_PLUS(sc)) 6424 printf(" - 57765 Plus\n"); 6425 if (BGE_IS_5717_PLUS(sc)) 6426 printf(" - 5717 Plus\n"); 6427 if (BGE_IS_5755_PLUS(sc)) 6428 printf(" - 5755 Plus\n"); 6429 if (BGE_IS_575X_PLUS(sc)) 6430 printf(" - 575X Plus\n"); 6431 if (BGE_IS_5705_PLUS(sc)) 6432 printf(" - 5705 Plus\n"); 6433 if (BGE_IS_5714_FAMILY(sc)) 6434 printf(" - 5714 Family\n"); 6435 if (BGE_IS_5700_FAMILY(sc)) 6436 printf(" - 5700 Family\n"); 6437 if (sc->bge_flags & BGEF_IS_5788) 6438 printf(" - 5788\n"); 6439 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6440 printf(" - Supports Jumbo Frames\n"); 6441 if (sc->bge_flags & BGEF_NO_EEPROM) 6442 printf(" - No EEPROM\n"); 6443 if (sc->bge_flags & BGEF_PCIX) 6444 printf(" - PCI-X Bus\n"); 6445 if (sc->bge_flags & BGEF_PCIE) 6446 printf(" - PCI Express Bus\n"); 6447 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6448 printf(" - RX Alignment Bug\n"); 6449 if (sc->bge_flags & BGEF_APE) 6450 printf(" - APE\n"); 6451 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6452 printf(" - CPMU\n"); 6453 if (sc->bge_flags & BGEF_TSO) 6454 printf(" - TSO\n"); 6455 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6456 printf(" - TAGGED_STATUS\n"); 6457 6458 /* PHY related */ 6459 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6460 printf(" - No 3 LEDs\n"); 6461 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6462 printf(" - CRC bug\n"); 6463 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6464 printf(" - ADC bug\n"); 6465 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6466 printf(" - 5704 A0 bug\n"); 6467 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6468 printf(" - jitter bug\n"); 6469 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6470 printf(" - BER bug\n"); 6471 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6472 printf(" - adjust trim\n"); 6473 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6474 printf(" - no wirespeed\n"); 6475 6476 /* ASF related */ 6477 if (sc->bge_asf_mode & ASF_ENABLE) 6478 printf(" - ASF enable\n"); 6479 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6480 printf(" - ASF new handshake\n"); 6481 if (sc->bge_asf_mode & ASF_STACKUP) 6482 printf(" - ASF stackup\n"); 6483 } 6484 #endif /* BGE_DEBUG */ 6485 6486 static int 6487 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6488 { 6489 prop_dictionary_t dict; 6490 prop_data_t ea; 6491 6492 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6493 return 1; 6494 6495 dict = device_properties(sc->bge_dev); 6496 ea = prop_dictionary_get(dict, "mac-address"); 6497 if (ea != NULL) { 6498 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6499 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6500 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6501 return 0; 6502 } 6503 6504 return 1; 6505 } 6506 6507 static int 6508 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6509 { 6510 uint32_t mac_addr; 6511 6512 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6513 if ((mac_addr >> 16) == 0x484b) { 6514 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6515 ether_addr[1] = (uint8_t)mac_addr; 6516 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6517 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6518 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6519 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6520 ether_addr[5] = (uint8_t)mac_addr; 6521 return 0; 6522 } 6523 return 1; 6524 } 6525 6526 static int 6527 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6528 { 6529 int mac_offset = BGE_EE_MAC_OFFSET; 6530 6531 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6532 mac_offset = BGE_EE_MAC_OFFSET_5906; 6533 6534 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6535 ETHER_ADDR_LEN)); 6536 } 6537 6538 static int 6539 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6540 { 6541 6542 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6543 return 1; 6544 6545 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6546 ETHER_ADDR_LEN)); 6547 } 6548 6549 static int 6550 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6551 { 6552 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6553 /* NOTE: Order is critical */ 6554 bge_get_eaddr_fw, 6555 bge_get_eaddr_mem, 6556 bge_get_eaddr_nvram, 6557 bge_get_eaddr_eeprom, 6558 NULL 6559 }; 6560 const bge_eaddr_fcn_t *func; 6561 6562 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6563 if ((*func)(sc, eaddr) == 0) 6564 break; 6565 } 6566 return *func == NULL ? ENXIO : 0; 6567 } 6568
Indexes created Mon Sep 22 10:09:38 GMT 2025