if_bge.c revision 1.393
1 /* $NetBSD: if_bge.c,v 1.393 2024/07/05 04:31:51 rin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.393 2024/07/05 04:31:51 rin Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/callout.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> 90 #include <sys/kmem.h> 91 #include <sys/mbuf.h> 92 #include <sys/rndsource.h> 93 #include <sys/socket.h> 94 #include <sys/sockio.h> 95 #include <sys/sysctl.h> 96 #include <sys/systm.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 #include <net/bpf.h> 103 104 /* Headers for TCP Segmentation Offload (TSO) */ 105 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 106 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 107 #include <netinet/ip.h> /* for struct ip */ 108 #include <netinet/tcp.h> /* for struct tcphdr */ 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 #include <dev/mii/miidevs.h> 117 #include <dev/mii/brgphyreg.h> 118 119 #include <dev/pci/if_bgereg.h> 120 #include <dev/pci/if_bgevar.h> 121 122 #include <prop/proplib.h> 123 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 127 /* 128 * Tunable thresholds for rx-side bge interrupt mitigation. 129 */ 130 131 /* 132 * The pairs of values below were obtained from empirical measurement 133 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 134 * interrupt for every N packets received, where N is, approximately, 135 * the second value (rx_max_bds) in each pair. The values are chosen 136 * such that moving from one pair to the succeeding pair was observed 137 * to roughly halve interrupt rate under sustained input packet load. 138 * The values were empirically chosen to avoid overflowing internal 139 * limits on the bcm5700: increasing rx_ticks much beyond 600 140 * results in internal wrapping and higher interrupt rates. 141 * The limit of 46 frames was chosen to match NFS workloads. 142 * 143 * These values also work well on bcm5701, bcm5704C, and (less 144 * tested) bcm5703. On other chipsets, (including the Altima chip 145 * family), the larger values may overflow internal chip limits, 146 * leading to increasing interrupt rates rather than lower interrupt 147 * rates. 148 * 149 * Applications using heavy interrupt mitigation (interrupting every 150 * 32 or 46 frames) in both directions may need to increase the TCP 151 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 152 * full link bandwidth, due to ACKs and window updates lingering 153 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 154 */ 155 static const struct bge_load_rx_thresh { 156 int rx_ticks; 157 int rx_max_bds; } 158 bge_rx_threshes[] = { 159 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 160 { 32, 2 }, 161 { 50, 4 }, 162 { 100, 8 }, 163 { 192, 16 }, 164 { 416, 32 }, 165 { 598, 46 } 166 }; 167 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 168 169 /* XXX patchable; should be sysctl'able */ 170 static int bge_auto_thresh = 1; 171 static int bge_rx_thresh_lvl; 172 173 static int bge_rxthresh_nodenum; 174 175 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 176 177 static uint32_t bge_chipid(const struct pci_attach_args *); 178 static int bge_can_use_msi(struct bge_softc *); 179 static int bge_probe(device_t, cfdata_t, void *); 180 static void bge_attach(device_t, device_t, void *); 181 static int bge_detach(device_t, int); 182 static void bge_release_resources(struct bge_softc *); 183 184 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 185 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 186 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 187 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 188 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 189 190 static void bge_txeof(struct bge_softc *); 191 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 192 static void bge_rxeof(struct bge_softc *); 193 194 static void bge_asf_driver_up (struct bge_softc *); 195 static void bge_tick(void *); 196 static void bge_stats_update(struct bge_softc *); 197 static void bge_stats_update_regs(struct bge_softc *); 198 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 199 200 static int bge_intr(void *); 201 static void bge_start(struct ifnet *); 202 static void bge_start_locked(struct ifnet *); 203 static int bge_ifflags_cb(struct ethercom *); 204 static int bge_ioctl(struct ifnet *, u_long, void *); 205 static int bge_init(struct ifnet *); 206 static int bge_init_locked(struct ifnet *); 207 static void bge_stop(struct ifnet *, int); 208 static void bge_stop_locked(struct ifnet *, bool); 209 static bool bge_watchdog_tick(struct ifnet *); 210 static int bge_ifmedia_upd(struct ifnet *); 211 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 212 static void bge_handle_reset_work(struct work *, void *); 213 214 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 215 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 216 217 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 218 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 219 static void bge_setmulti(struct bge_softc *); 220 221 static void bge_handle_events(struct bge_softc *); 222 static int bge_alloc_jumbo_mem(struct bge_softc *); 223 static void bge_free_jumbo_mem(struct bge_softc *); 224 static void *bge_jalloc(struct bge_softc *); 225 static void bge_jfree(struct mbuf *, void *, size_t, void *); 226 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 227 static int bge_init_rx_ring_jumbo(struct bge_softc *); 228 static void bge_free_rx_ring_jumbo(struct bge_softc *); 229 230 static int bge_newbuf_std(struct bge_softc *, int); 231 static int bge_init_rx_ring_std(struct bge_softc *); 232 static void bge_fill_rx_ring_std(struct bge_softc *); 233 static void bge_free_rx_ring_std(struct bge_softc *m); 234 235 static void bge_free_tx_ring(struct bge_softc *m, bool); 236 static int bge_init_tx_ring(struct bge_softc *); 237 238 static int bge_chipinit(struct bge_softc *); 239 static int bge_blockinit(struct bge_softc *); 240 static int bge_phy_addr(struct bge_softc *); 241 static uint32_t bge_readmem_ind(struct bge_softc *, int); 242 static void bge_writemem_ind(struct bge_softc *, int, int); 243 static void bge_writembx(struct bge_softc *, int, int); 244 static void bge_writembx_flush(struct bge_softc *, int, int); 245 static void bge_writemem_direct(struct bge_softc *, int, int); 246 static void bge_writereg_ind(struct bge_softc *, int, int); 247 static void bge_set_max_readrq(struct bge_softc *); 248 249 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 250 static int bge_miibus_writereg(device_t, int, int, uint16_t); 251 static void bge_miibus_statchg(struct ifnet *); 252 253 #define BGE_RESET_SHUTDOWN 0 254 #define BGE_RESET_START 1 255 #define BGE_RESET_SUSPEND 2 256 static void bge_sig_post_reset(struct bge_softc *, int); 257 static void bge_sig_legacy(struct bge_softc *, int); 258 static void bge_sig_pre_reset(struct bge_softc *, int); 259 static void bge_wait_for_event_ack(struct bge_softc *); 260 static void bge_stop_fw(struct bge_softc *); 261 static int bge_reset(struct bge_softc *); 262 static void bge_link_upd(struct bge_softc *); 263 static void bge_sysctl_init(struct bge_softc *); 264 static int bge_sysctl_verify(SYSCTLFN_PROTO); 265 266 static void bge_ape_lock_init(struct bge_softc *); 267 static void bge_ape_read_fw_ver(struct bge_softc *); 268 static int bge_ape_lock(struct bge_softc *, int); 269 static void bge_ape_unlock(struct bge_softc *, int); 270 static void bge_ape_send_event(struct bge_softc *, uint32_t); 271 static void bge_ape_driver_state_change(struct bge_softc *, int); 272 273 #ifdef BGE_DEBUG 274 #define DPRINTF(x) if (bgedebug) printf x 275 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 276 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 277 int bgedebug = 0; 278 int bge_tso_debug = 0; 279 void bge_debug_info(struct bge_softc *); 280 #else 281 #define DPRINTF(x) 282 #define DPRINTFN(n, x) 283 #define BGE_TSO_PRINTF(x) 284 #endif 285 286 #ifdef BGE_EVENT_COUNTERS 287 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 288 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 289 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 290 #else 291 #define BGE_EVCNT_INCR(ev) /* nothing */ 292 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 293 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 294 #endif 295 296 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 297 /* 298 * The BCM5700 documentation seems to indicate that the hardware still has the 299 * Alteon vendor ID burned into it, though it should always be overridden by 300 * the value in the EEPROM. We'll check for it anyway. 301 */ 302 static const struct bge_product { 303 pci_vendor_id_t bp_vendor; 304 pci_product_id_t bp_product; 305 const char *bp_name; 306 } bge_products[] = { 307 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 308 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 309 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 310 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 311 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 312 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 313 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 314 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 315 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 316 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 317 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 318 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 319 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 320 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 321 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 322 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 323 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 324 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 325 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 326 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 328 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 329 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 330 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 331 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 332 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 334 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 336 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 345 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 346 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 347 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 348 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 349 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 350 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 351 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 352 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 353 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 354 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 357 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 358 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 360 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 361 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 362 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 363 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 364 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 366 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 367 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 368 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 369 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 370 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 371 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 372 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 373 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 374 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 375 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 376 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 377 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 378 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 379 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 380 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 381 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 382 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 383 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 397 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 398 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 399 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 400 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 401 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 402 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 403 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 404 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 405 { 0, 0, NULL }, 406 }; 407 408 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 409 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 410 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 411 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 412 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 413 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 414 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 415 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 416 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 417 418 static const struct bge_revision { 419 uint32_t br_chipid; 420 const char *br_name; 421 } bge_revisions[] = { 422 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 423 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 424 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 425 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 426 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 427 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 428 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 429 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 430 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 431 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 432 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 433 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 434 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 435 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 436 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 437 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 438 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 439 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 440 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 441 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 442 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 443 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 444 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 445 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 446 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 447 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 448 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 449 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 450 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 451 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 452 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 453 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 454 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 455 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 456 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 457 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 458 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 459 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 460 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 461 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 462 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 463 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 464 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 465 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 466 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 467 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 468 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 469 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 470 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 471 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 472 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 473 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 474 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 475 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 476 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 477 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 478 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 479 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 480 /* 5754 and 5787 share the same ASIC ID */ 481 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 482 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 483 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 484 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 485 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 486 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 487 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 488 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 489 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 490 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 491 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 492 493 { 0, NULL } 494 }; 495 496 /* 497 * Some defaults for major revisions, so that newer steppings 498 * that we don't know about have a shot at working. 499 */ 500 static const struct bge_revision bge_majorrevs[] = { 501 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 502 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 503 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 504 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 505 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 506 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 507 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 508 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 509 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 510 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 511 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 512 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 513 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 514 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 515 /* 5754 and 5787 share the same ASIC ID */ 516 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 517 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 518 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 519 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 520 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 521 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 522 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 523 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 524 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 525 526 { 0, NULL } 527 }; 528 529 static int bge_allow_asf = 1; 530 531 #ifndef BGE_WATCHDOG_TIMEOUT 532 #define BGE_WATCHDOG_TIMEOUT 5 533 #endif 534 static int bge_watchdog_timeout = BGE_WATCHDOG_TIMEOUT; 535 536 537 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 538 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 539 540 static uint32_t 541 bge_readmem_ind(struct bge_softc *sc, int off) 542 { 543 pcireg_t val; 544 545 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 546 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 547 return 0; 548 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 550 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 551 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 552 return val; 553 } 554 555 static void 556 bge_writemem_ind(struct bge_softc *sc, int off, int val) 557 { 558 559 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 560 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 561 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 562 } 563 564 /* 565 * PCI Express only 566 */ 567 static void 568 bge_set_max_readrq(struct bge_softc *sc) 569 { 570 pcireg_t val; 571 572 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 573 + PCIE_DCSR); 574 val &= ~PCIE_DCSR_MAX_READ_REQ; 575 switch (sc->bge_expmrq) { 576 case 2048: 577 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 578 break; 579 case 4096: 580 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 581 break; 582 default: 583 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 584 break; 585 } 586 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 587 + PCIE_DCSR, val); 588 } 589 590 #ifdef notdef 591 static uint32_t 592 bge_readreg_ind(struct bge_softc *sc, int off) 593 { 594 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 595 return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA); 596 } 597 #endif 598 599 static void 600 bge_writereg_ind(struct bge_softc *sc, int off, int val) 601 { 602 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 603 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 604 } 605 606 static void 607 bge_writemem_direct(struct bge_softc *sc, int off, int val) 608 { 609 CSR_WRITE_4(sc, off, val); 610 } 611 612 static void 613 bge_writembx(struct bge_softc *sc, int off, int val) 614 { 615 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 616 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 617 618 CSR_WRITE_4(sc, off, val); 619 } 620 621 static void 622 bge_writembx_flush(struct bge_softc *sc, int off, int val) 623 { 624 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 625 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 626 627 CSR_WRITE_4_FLUSH(sc, off, val); 628 } 629 630 /* 631 * Clear all stale locks and select the lock for this driver instance. 632 */ 633 void 634 bge_ape_lock_init(struct bge_softc *sc) 635 { 636 struct pci_attach_args *pa = &(sc->bge_pa); 637 uint32_t bit, regbase; 638 int i; 639 640 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 641 regbase = BGE_APE_LOCK_GRANT; 642 else 643 regbase = BGE_APE_PER_LOCK_GRANT; 644 645 /* Clear any stale locks. */ 646 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 647 switch (i) { 648 case BGE_APE_LOCK_PHY0: 649 case BGE_APE_LOCK_PHY1: 650 case BGE_APE_LOCK_PHY2: 651 case BGE_APE_LOCK_PHY3: 652 bit = BGE_APE_LOCK_GRANT_DRIVER0; 653 break; 654 default: 655 if (pa->pa_function == 0) 656 bit = BGE_APE_LOCK_GRANT_DRIVER0; 657 else 658 bit = (1 << pa->pa_function); 659 } 660 APE_WRITE_4(sc, regbase + 4 * i, bit); 661 } 662 663 /* Select the PHY lock based on the device's function number. */ 664 switch (pa->pa_function) { 665 case 0: 666 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 667 break; 668 case 1: 669 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 670 break; 671 case 2: 672 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 673 break; 674 case 3: 675 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 676 break; 677 default: 678 printf("%s: PHY lock not supported on function\n", 679 device_xname(sc->bge_dev)); 680 break; 681 } 682 } 683 684 /* 685 * Check for APE firmware, set flags, and print version info. 686 */ 687 void 688 bge_ape_read_fw_ver(struct bge_softc *sc) 689 { 690 const char *fwtype; 691 uint32_t apedata, features; 692 693 /* Check for a valid APE signature in shared memory. */ 694 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 695 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 696 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 697 return; 698 } 699 700 /* Check if APE firmware is running. */ 701 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 702 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 703 printf("%s: APE signature found but FW status not ready! " 704 "0x%08x\n", device_xname(sc->bge_dev), apedata); 705 return; 706 } 707 708 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 709 710 /* Fetch the APE firmware type and version. */ 711 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 712 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 713 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 714 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 715 fwtype = "NCSI"; 716 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 717 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 718 fwtype = "DASH"; 719 } else 720 fwtype = "UNKN"; 721 722 /* Print the APE firmware version. */ 723 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 724 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 725 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 726 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 727 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 728 } 729 730 int 731 bge_ape_lock(struct bge_softc *sc, int locknum) 732 { 733 struct pci_attach_args *pa = &(sc->bge_pa); 734 uint32_t bit, gnt, req, status; 735 int i, off; 736 737 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 738 return 0; 739 740 /* Lock request/grant registers have different bases. */ 741 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 742 req = BGE_APE_LOCK_REQ; 743 gnt = BGE_APE_LOCK_GRANT; 744 } else { 745 req = BGE_APE_PER_LOCK_REQ; 746 gnt = BGE_APE_PER_LOCK_GRANT; 747 } 748 749 off = 4 * locknum; 750 751 switch (locknum) { 752 case BGE_APE_LOCK_GPIO: 753 /* Lock required when using GPIO. */ 754 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 755 return 0; 756 if (pa->pa_function == 0) 757 bit = BGE_APE_LOCK_REQ_DRIVER0; 758 else 759 bit = (1 << pa->pa_function); 760 break; 761 case BGE_APE_LOCK_GRC: 762 /* Lock required to reset the device. */ 763 if (pa->pa_function == 0) 764 bit = BGE_APE_LOCK_REQ_DRIVER0; 765 else 766 bit = (1 << pa->pa_function); 767 break; 768 case BGE_APE_LOCK_MEM: 769 /* Lock required when accessing certain APE memory. */ 770 if (pa->pa_function == 0) 771 bit = BGE_APE_LOCK_REQ_DRIVER0; 772 else 773 bit = (1 << pa->pa_function); 774 break; 775 case BGE_APE_LOCK_PHY0: 776 case BGE_APE_LOCK_PHY1: 777 case BGE_APE_LOCK_PHY2: 778 case BGE_APE_LOCK_PHY3: 779 /* Lock required when accessing PHYs. */ 780 bit = BGE_APE_LOCK_REQ_DRIVER0; 781 break; 782 default: 783 return EINVAL; 784 } 785 786 /* Request a lock. */ 787 APE_WRITE_4_FLUSH(sc, req + off, bit); 788 789 /* Wait up to 1 second to acquire lock. */ 790 for (i = 0; i < 20000; i++) { 791 status = APE_READ_4(sc, gnt + off); 792 if (status == bit) 793 break; 794 DELAY(50); 795 } 796 797 /* Handle any errors. */ 798 if (status != bit) { 799 printf("%s: APE lock %d request failed! " 800 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 801 device_xname(sc->bge_dev), 802 locknum, req + off, bit & 0xFFFF, gnt + off, 803 status & 0xFFFF); 804 /* Revoke the lock request. */ 805 APE_WRITE_4(sc, gnt + off, bit); 806 return EBUSY; 807 } 808 809 return 0; 810 } 811 812 void 813 bge_ape_unlock(struct bge_softc *sc, int locknum) 814 { 815 struct pci_attach_args *pa = &(sc->bge_pa); 816 uint32_t bit, gnt; 817 int off; 818 819 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 820 return; 821 822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 823 gnt = BGE_APE_LOCK_GRANT; 824 else 825 gnt = BGE_APE_PER_LOCK_GRANT; 826 827 off = 4 * locknum; 828 829 switch (locknum) { 830 case BGE_APE_LOCK_GPIO: 831 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 832 return; 833 if (pa->pa_function == 0) 834 bit = BGE_APE_LOCK_GRANT_DRIVER0; 835 else 836 bit = (1 << pa->pa_function); 837 break; 838 case BGE_APE_LOCK_GRC: 839 if (pa->pa_function == 0) 840 bit = BGE_APE_LOCK_GRANT_DRIVER0; 841 else 842 bit = (1 << pa->pa_function); 843 break; 844 case BGE_APE_LOCK_MEM: 845 if (pa->pa_function == 0) 846 bit = BGE_APE_LOCK_GRANT_DRIVER0; 847 else 848 bit = (1 << pa->pa_function); 849 break; 850 case BGE_APE_LOCK_PHY0: 851 case BGE_APE_LOCK_PHY1: 852 case BGE_APE_LOCK_PHY2: 853 case BGE_APE_LOCK_PHY3: 854 bit = BGE_APE_LOCK_GRANT_DRIVER0; 855 break; 856 default: 857 return; 858 } 859 860 /* Write and flush for consecutive bge_ape_lock() */ 861 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 862 } 863 864 /* 865 * Send an event to the APE firmware. 866 */ 867 void 868 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 869 { 870 uint32_t apedata; 871 int i; 872 873 /* NCSI does not support APE events. */ 874 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 875 return; 876 877 /* Wait up to 1ms for APE to service previous event. */ 878 for (i = 10; i > 0; i--) { 879 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 880 break; 881 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 882 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 883 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 884 BGE_APE_EVENT_STATUS_EVENT_PENDING); 885 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 886 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 887 break; 888 } 889 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 890 DELAY(100); 891 } 892 if (i == 0) { 893 printf("%s: APE event 0x%08x send timed out\n", 894 device_xname(sc->bge_dev), event); 895 } 896 } 897 898 void 899 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 900 { 901 uint32_t apedata, event; 902 903 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 904 return; 905 906 switch (kind) { 907 case BGE_RESET_START: 908 /* If this is the first load, clear the load counter. */ 909 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 910 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 911 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 912 else { 913 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 914 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 915 } 916 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 917 BGE_APE_HOST_SEG_SIG_MAGIC); 918 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 919 BGE_APE_HOST_SEG_LEN_MAGIC); 920 921 /* Add some version info if bge(4) supports it. */ 922 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 923 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 924 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 925 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 926 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 927 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 928 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 929 BGE_APE_HOST_DRVR_STATE_START); 930 event = BGE_APE_EVENT_STATUS_STATE_START; 931 break; 932 case BGE_RESET_SHUTDOWN: 933 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 934 BGE_APE_HOST_DRVR_STATE_UNLOAD); 935 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 936 break; 937 case BGE_RESET_SUSPEND: 938 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 939 break; 940 default: 941 return; 942 } 943 944 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 945 BGE_APE_EVENT_STATUS_STATE_CHNGE); 946 } 947 948 static uint8_t 949 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 950 { 951 uint32_t access, byte = 0; 952 int i; 953 954 /* Lock. */ 955 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 956 for (i = 0; i < 8000; i++) { 957 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 958 break; 959 DELAY(20); 960 } 961 if (i == 8000) 962 return 1; 963 964 /* Enable access. */ 965 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 966 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 967 968 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 969 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 970 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 971 DELAY(10); 972 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 973 DELAY(10); 974 break; 975 } 976 } 977 978 if (i == BGE_TIMEOUT * 10) { 979 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 980 return 1; 981 } 982 983 /* Get result. */ 984 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 985 986 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 987 988 /* Disable access. */ 989 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 990 991 /* Unlock. */ 992 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 993 994 return 0; 995 } 996 997 /* 998 * Read a sequence of bytes from NVRAM. 999 */ 1000 static int 1001 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1002 { 1003 int error = 0, i; 1004 uint8_t byte = 0; 1005 1006 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1007 return 1; 1008 1009 for (i = 0; i < cnt; i++) { 1010 error = bge_nvram_getbyte(sc, off + i, &byte); 1011 if (error) 1012 break; 1013 *(dest + i) = byte; 1014 } 1015 1016 return error ? 1 : 0; 1017 } 1018 1019 /* 1020 * Read a byte of data stored in the EEPROM at address 'addr.' The 1021 * BCM570x supports both the traditional bitbang interface and an 1022 * auto access interface for reading the EEPROM. We use the auto 1023 * access method. 1024 */ 1025 static uint8_t 1026 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1027 { 1028 int i; 1029 uint32_t byte = 0; 1030 1031 /* 1032 * Enable use of auto EEPROM access so we can avoid 1033 * having to use the bitbang method. 1034 */ 1035 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1036 1037 /* Reset the EEPROM, load the clock period. */ 1038 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1039 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1040 DELAY(20); 1041 1042 /* Issue the read EEPROM command. */ 1043 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1044 1045 /* Wait for completion */ 1046 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1047 DELAY(10); 1048 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1049 break; 1050 } 1051 1052 if (i == BGE_TIMEOUT * 10) { 1053 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1054 return 1; 1055 } 1056 1057 /* Get result. */ 1058 byte = CSR_READ_4(sc, BGE_EE_DATA); 1059 1060 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1061 1062 return 0; 1063 } 1064 1065 /* 1066 * Read a sequence of bytes from the EEPROM. 1067 */ 1068 static int 1069 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1070 { 1071 int error = 0, i; 1072 uint8_t byte = 0; 1073 char *dest = destv; 1074 1075 for (i = 0; i < cnt; i++) { 1076 error = bge_eeprom_getbyte(sc, off + i, &byte); 1077 if (error) 1078 break; 1079 *(dest + i) = byte; 1080 } 1081 1082 return error ? 1 : 0; 1083 } 1084 1085 static int 1086 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1087 { 1088 struct bge_softc * const sc = device_private(dev); 1089 uint32_t data; 1090 uint32_t autopoll; 1091 int rv = 0; 1092 int i; 1093 1094 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1095 return -1; 1096 1097 /* Reading with autopolling on may trigger PCI errors */ 1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1099 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1100 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1101 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1102 DELAY(80); 1103 } 1104 1105 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1106 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1107 1108 for (i = 0; i < BGE_TIMEOUT; i++) { 1109 delay(10); 1110 data = CSR_READ_4(sc, BGE_MI_COMM); 1111 if (!(data & BGE_MICOMM_BUSY)) { 1112 DELAY(5); 1113 data = CSR_READ_4(sc, BGE_MI_COMM); 1114 break; 1115 } 1116 } 1117 1118 if (i == BGE_TIMEOUT) { 1119 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1120 rv = ETIMEDOUT; 1121 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1122 /* XXX This error occurs on some devices while attaching. */ 1123 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1124 rv = EIO; 1125 } else 1126 *val = data & BGE_MICOMM_DATA; 1127 1128 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1129 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1130 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1131 DELAY(80); 1132 } 1133 1134 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1135 1136 return rv; 1137 } 1138 1139 static int 1140 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1141 { 1142 struct bge_softc * const sc = device_private(dev); 1143 uint32_t data, autopoll; 1144 int rv = 0; 1145 int i; 1146 1147 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1148 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1149 return 0; 1150 1151 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1152 return -1; 1153 1154 /* Reading with autopolling on may trigger PCI errors */ 1155 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1156 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1157 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1158 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1159 DELAY(80); 1160 } 1161 1162 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1163 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1164 1165 for (i = 0; i < BGE_TIMEOUT; i++) { 1166 delay(10); 1167 data = CSR_READ_4(sc, BGE_MI_COMM); 1168 if (!(data & BGE_MICOMM_BUSY)) { 1169 delay(5); 1170 data = CSR_READ_4(sc, BGE_MI_COMM); 1171 break; 1172 } 1173 } 1174 1175 if (i == BGE_TIMEOUT) { 1176 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1177 rv = ETIMEDOUT; 1178 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1179 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1180 rv = EIO; 1181 } 1182 1183 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1184 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1185 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1186 delay(80); 1187 } 1188 1189 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1190 1191 return rv; 1192 } 1193 1194 static void 1195 bge_miibus_statchg(struct ifnet *ifp) 1196 { 1197 struct bge_softc * const sc = ifp->if_softc; 1198 struct mii_data *mii = &sc->bge_mii; 1199 uint32_t mac_mode, rx_mode, tx_mode; 1200 1201 /* 1202 * Get flow control negotiation result. 1203 */ 1204 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1205 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1206 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1207 1208 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1209 mii->mii_media_status & IFM_ACTIVE && 1210 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1211 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1212 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1213 (!(mii->mii_media_status & IFM_ACTIVE) || 1214 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1215 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1216 1217 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1218 return; 1219 1220 /* Set the port mode (MII/GMII) to match the link speed. */ 1221 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1222 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1223 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1224 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1225 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1226 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1227 mac_mode |= BGE_PORTMODE_GMII; 1228 else 1229 mac_mode |= BGE_PORTMODE_MII; 1230 1231 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1232 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1233 if ((mii->mii_media_active & IFM_FDX) != 0) { 1234 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1235 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1236 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1237 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1238 } else 1239 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1240 1241 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1242 DELAY(40); 1243 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1244 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1245 } 1246 1247 /* 1248 * Update rx threshold levels to values in a particular slot 1249 * of the interrupt-mitigation table bge_rx_threshes. 1250 */ 1251 static void 1252 bge_set_thresh(struct ifnet *ifp, int lvl) 1253 { 1254 struct bge_softc * const sc = ifp->if_softc; 1255 1256 /* 1257 * For now, just save the new Rx-intr thresholds and record 1258 * that a threshold update is pending. Updating the hardware 1259 * registers here (even at splhigh()) is observed to 1260 * occasionally cause glitches where Rx-interrupts are not 1261 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1262 */ 1263 mutex_enter(sc->sc_intr_lock); 1264 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1265 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1266 sc->bge_pending_rxintr_change = true; 1267 mutex_exit(sc->sc_intr_lock); 1268 } 1269 1270 1271 /* 1272 * Update Rx thresholds of all bge devices 1273 */ 1274 static void 1275 bge_update_all_threshes(int lvl) 1276 { 1277 const char * const namebuf = "bge"; 1278 const size_t namelen = strlen(namebuf); 1279 struct ifnet *ifp; 1280 1281 if (lvl < 0) 1282 lvl = 0; 1283 else if (lvl >= NBGE_RX_THRESH) 1284 lvl = NBGE_RX_THRESH - 1; 1285 1286 /* 1287 * Now search all the interfaces for this name/number 1288 */ 1289 int s = pserialize_read_enter(); 1290 IFNET_READER_FOREACH(ifp) { 1291 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1292 continue; 1293 /* We got a match: update if doing auto-threshold-tuning */ 1294 if (bge_auto_thresh) 1295 bge_set_thresh(ifp, lvl); 1296 } 1297 pserialize_read_exit(s); 1298 } 1299 1300 /* 1301 * Handle events that have triggered interrupts. 1302 */ 1303 static void 1304 bge_handle_events(struct bge_softc *sc) 1305 { 1306 1307 return; 1308 } 1309 1310 /* 1311 * Memory management for jumbo frames. 1312 */ 1313 1314 static int 1315 bge_alloc_jumbo_mem(struct bge_softc *sc) 1316 { 1317 char *ptr, *kva; 1318 int i, rseg, state, error; 1319 struct bge_jpool_entry *entry; 1320 1321 state = error = 0; 1322 1323 /* Grab a big chunk o' storage. */ 1324 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1325 &sc->bge_cdata.bge_rx_jumbo_seg, 1, &rseg, BUS_DMA_WAITOK)) { 1326 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1327 return ENOBUFS; 1328 } 1329 1330 state = 1; 1331 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1332 rseg, BGE_JMEM, (void **)&kva, BUS_DMA_WAITOK)) { 1333 aprint_error_dev(sc->bge_dev, 1334 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1335 error = ENOBUFS; 1336 goto out; 1337 } 1338 1339 state = 2; 1340 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1341 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_jumbo_map)) { 1342 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1343 error = ENOBUFS; 1344 goto out; 1345 } 1346 1347 state = 3; 1348 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1349 kva, BGE_JMEM, NULL, BUS_DMA_WAITOK)) { 1350 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1351 error = ENOBUFS; 1352 goto out; 1353 } 1354 1355 state = 4; 1356 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1357 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1358 1359 SLIST_INIT(&sc->bge_jfree_listhead); 1360 SLIST_INIT(&sc->bge_jinuse_listhead); 1361 1362 /* 1363 * Now divide it up into 9K pieces and save the addresses 1364 * in an array. 1365 */ 1366 ptr = sc->bge_cdata.bge_jumbo_buf; 1367 for (i = 0; i < BGE_JSLOTS; i++) { 1368 sc->bge_cdata.bge_jslots[i] = ptr; 1369 ptr += BGE_JLEN; 1370 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 1371 entry->slot = i; 1372 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1373 entry, jpool_entries); 1374 } 1375 out: 1376 if (error != 0) { 1377 switch (state) { 1378 case 4: 1379 bus_dmamap_unload(sc->bge_dmatag, 1380 sc->bge_cdata.bge_rx_jumbo_map); 1381 /* FALLTHROUGH */ 1382 case 3: 1383 bus_dmamap_destroy(sc->bge_dmatag, 1384 sc->bge_cdata.bge_rx_jumbo_map); 1385 /* FALLTHROUGH */ 1386 case 2: 1387 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1388 /* FALLTHROUGH */ 1389 case 1: 1390 bus_dmamem_free(sc->bge_dmatag, 1391 &sc->bge_cdata.bge_rx_jumbo_seg, rseg); 1392 break; 1393 default: 1394 break; 1395 } 1396 } 1397 1398 return error; 1399 } 1400 1401 static void 1402 bge_free_jumbo_mem(struct bge_softc *sc) 1403 { 1404 struct bge_jpool_entry *entry, *tmp; 1405 1406 KASSERT(SLIST_EMPTY(&sc->bge_jinuse_listhead)); 1407 1408 SLIST_FOREACH_SAFE(entry, &sc->bge_jfree_listhead, jpool_entries, tmp) { 1409 kmem_free(entry, sizeof(*entry)); 1410 } 1411 1412 bus_dmamap_unload(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1413 1414 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1415 1416 bus_dmamem_unmap(sc->bge_dmatag, sc->bge_cdata.bge_jumbo_buf, BGE_JMEM); 1417 1418 bus_dmamem_free(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1); 1419 } 1420 1421 /* 1422 * Allocate a jumbo buffer. 1423 */ 1424 static void * 1425 bge_jalloc(struct bge_softc *sc) 1426 { 1427 struct bge_jpool_entry *entry; 1428 1429 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1430 1431 if (entry == NULL) { 1432 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1433 return NULL; 1434 } 1435 1436 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1437 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1438 return sc->bge_cdata.bge_jslots[entry->slot]; 1439 } 1440 1441 /* 1442 * Release a jumbo buffer. 1443 */ 1444 static void 1445 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1446 { 1447 struct bge_jpool_entry *entry; 1448 struct bge_softc * const sc = arg; 1449 1450 if (sc == NULL) 1451 panic("bge_jfree: can't find softc pointer!"); 1452 1453 /* calculate the slot this buffer belongs to */ 1454 int i = ((char *)buf - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1455 1456 if (i < 0 || i >= BGE_JSLOTS) 1457 panic("bge_jfree: asked to free buffer that we don't manage!"); 1458 1459 mutex_enter(sc->sc_intr_lock); 1460 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1461 if (entry == NULL) 1462 panic("bge_jfree: buffer not in use!"); 1463 entry->slot = i; 1464 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1465 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1466 mutex_exit(sc->sc_intr_lock); 1467 1468 if (__predict_true(m != NULL)) 1469 pool_cache_put(mb_cache, m); 1470 } 1471 1472 1473 /* 1474 * Initialize a standard receive ring descriptor. 1475 */ 1476 static int 1477 bge_newbuf_std(struct bge_softc *sc, int i) 1478 { 1479 const bus_dmamap_t dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1480 struct mbuf *m; 1481 1482 MGETHDR(m, M_DONTWAIT, MT_DATA); 1483 if (m == NULL) 1484 return ENOBUFS; 1485 1486 MCLGET(m, M_DONTWAIT); 1487 if (!(m->m_flags & M_EXT)) { 1488 m_freem(m); 1489 return ENOBUFS; 1490 } 1491 m->m_len = m->m_pkthdr.len = MCLBYTES; 1492 1493 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1494 m_adj(m, ETHER_ALIGN); 1495 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m, 1496 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1497 m_freem(m); 1498 return ENOBUFS; 1499 } 1500 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1501 BUS_DMASYNC_PREREAD); 1502 sc->bge_cdata.bge_rx_std_chain[i] = m; 1503 1504 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1505 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1506 i * sizeof(struct bge_rx_bd), 1507 sizeof(struct bge_rx_bd), 1508 BUS_DMASYNC_POSTWRITE); 1509 1510 struct bge_rx_bd * const r = &sc->bge_rdata->bge_rx_std_ring[i]; 1511 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1512 r->bge_flags = BGE_RXBDFLAG_END; 1513 r->bge_len = m->m_len; 1514 r->bge_idx = i; 1515 1516 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1517 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1518 i * sizeof(struct bge_rx_bd), 1519 sizeof(struct bge_rx_bd), 1520 BUS_DMASYNC_PREWRITE); 1521 1522 sc->bge_std_cnt++; 1523 1524 return 0; 1525 } 1526 1527 /* 1528 * Initialize a jumbo receive ring descriptor. This allocates 1529 * a jumbo buffer from the pool managed internally by the driver. 1530 */ 1531 static int 1532 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1533 { 1534 struct mbuf *m_new = NULL; 1535 struct bge_rx_bd *r; 1536 void *buf = NULL; 1537 1538 if (m == NULL) { 1539 1540 /* Allocate the mbuf. */ 1541 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1542 if (m_new == NULL) 1543 return ENOBUFS; 1544 1545 /* Allocate the jumbo buffer */ 1546 buf = bge_jalloc(sc); 1547 if (buf == NULL) { 1548 m_freem(m_new); 1549 aprint_error_dev(sc->bge_dev, 1550 "jumbo allocation failed -- packet dropped!\n"); 1551 return ENOBUFS; 1552 } 1553 1554 /* Attach the buffer to the mbuf. */ 1555 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1556 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1557 bge_jfree, sc); 1558 m_new->m_flags |= M_EXT_RW; 1559 } else { 1560 m_new = m; 1561 buf = m_new->m_data = m_new->m_ext.ext_buf; 1562 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1563 } 1564 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1565 m_adj(m_new, ETHER_ALIGN); 1566 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1567 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1568 BGE_JLEN, BUS_DMASYNC_PREREAD); 1569 1570 /* Set up the descriptor. */ 1571 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1572 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1573 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1574 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1575 r->bge_len = m_new->m_len; 1576 r->bge_idx = i; 1577 1578 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1579 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1580 i * sizeof(struct bge_rx_bd), 1581 sizeof(struct bge_rx_bd), 1582 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1583 1584 return 0; 1585 } 1586 1587 static int 1588 bge_init_rx_ring_std(struct bge_softc *sc) 1589 { 1590 bus_dmamap_t dmamap; 1591 int error = 0; 1592 u_int i; 1593 1594 if (sc->bge_flags & BGEF_RXRING_VALID) 1595 return 0; 1596 1597 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1598 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1599 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dmamap); 1600 if (error) 1601 goto uncreate; 1602 1603 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1604 memset(&sc->bge_rdata->bge_rx_std_ring[i], 0, 1605 sizeof(struct bge_rx_bd)); 1606 } 1607 1608 sc->bge_std = i - 1; 1609 sc->bge_std_cnt = 0; 1610 bge_fill_rx_ring_std(sc); 1611 1612 sc->bge_flags |= BGEF_RXRING_VALID; 1613 1614 return 0; 1615 1616 uncreate: 1617 while (--i) { 1618 bus_dmamap_destroy(sc->bge_dmatag, 1619 sc->bge_cdata.bge_rx_std_map[i]); 1620 } 1621 return error; 1622 } 1623 1624 static void 1625 bge_fill_rx_ring_std(struct bge_softc *sc) 1626 { 1627 int i = sc->bge_std; 1628 bool post = false; 1629 1630 while (sc->bge_std_cnt < BGE_STD_RX_RING_CNT) { 1631 BGE_INC(i, BGE_STD_RX_RING_CNT); 1632 1633 if (bge_newbuf_std(sc, i) != 0) 1634 break; 1635 1636 sc->bge_std = i; 1637 post = true; 1638 } 1639 1640 if (post) 1641 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1642 } 1643 1644 1645 static void 1646 bge_free_rx_ring_std(struct bge_softc *sc) 1647 { 1648 1649 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1650 return; 1651 1652 for (u_int i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1653 const bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i]; 1654 struct mbuf * const m = sc->bge_cdata.bge_rx_std_chain[i]; 1655 if (m != NULL) { 1656 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 1657 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1658 bus_dmamap_unload(sc->bge_dmatag, dmap); 1659 m_freem(m); 1660 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1661 } 1662 bus_dmamap_destroy(sc->bge_dmatag, 1663 sc->bge_cdata.bge_rx_std_map[i]); 1664 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1665 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1666 sizeof(struct bge_rx_bd)); 1667 } 1668 1669 sc->bge_flags &= ~BGEF_RXRING_VALID; 1670 } 1671 1672 static int 1673 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1674 { 1675 int i; 1676 volatile struct bge_rcb *rcb; 1677 1678 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1679 return 0; 1680 1681 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1682 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1683 return ENOBUFS; 1684 } 1685 1686 sc->bge_jumbo = i - 1; 1687 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1688 1689 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1690 rcb->bge_maxlen_flags = 0; 1691 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1692 1693 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1694 1695 return 0; 1696 } 1697 1698 static void 1699 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1700 { 1701 int i; 1702 1703 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1704 return; 1705 1706 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1707 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1708 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1709 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1710 sizeof(struct bge_rx_bd)); 1711 } 1712 1713 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1714 } 1715 1716 static void 1717 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1718 { 1719 int i; 1720 struct txdmamap_pool_entry *dma; 1721 1722 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1723 return; 1724 1725 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1726 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1727 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1728 sc->bge_cdata.bge_tx_chain[i] = NULL; 1729 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1730 link); 1731 sc->txdma[i] = 0; 1732 } 1733 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1734 sizeof(struct bge_tx_bd)); 1735 } 1736 1737 if (disable) { 1738 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1739 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1740 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1741 if (sc->bge_dma64) { 1742 bus_dmamap_destroy(sc->bge_dmatag32, 1743 dma->dmamap32); 1744 } 1745 kmem_free(dma, sizeof(*dma)); 1746 } 1747 SLIST_INIT(&sc->txdma_list); 1748 } 1749 1750 sc->bge_flags &= ~BGEF_TXRING_VALID; 1751 } 1752 1753 static int 1754 bge_init_tx_ring(struct bge_softc *sc) 1755 { 1756 struct ifnet * const ifp = &sc->ethercom.ec_if; 1757 int i; 1758 bus_dmamap_t dmamap, dmamap32; 1759 bus_size_t maxsegsz; 1760 struct txdmamap_pool_entry *dma; 1761 1762 if (sc->bge_flags & BGEF_TXRING_VALID) 1763 return 0; 1764 1765 sc->bge_txcnt = 0; 1766 sc->bge_tx_saved_considx = 0; 1767 1768 /* Initialize transmit producer index for host-memory send ring. */ 1769 sc->bge_tx_prodidx = 0; 1770 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1771 /* 5700 b2 errata */ 1772 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1773 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1774 1775 /* NIC-memory send ring not used; initialize to zero. */ 1776 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1777 /* 5700 b2 errata */ 1778 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1779 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1780 1781 /* Limit DMA segment size for some chips */ 1782 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1783 (ifp->if_mtu <= ETHERMTU)) 1784 maxsegsz = 2048; 1785 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1786 maxsegsz = 4096; 1787 else 1788 maxsegsz = ETHER_MAX_LEN_JUMBO; 1789 1790 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1791 goto alloc_done; 1792 1793 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1794 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1795 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1796 &dmamap)) 1797 return ENOBUFS; 1798 if (dmamap == NULL) 1799 panic("dmamap NULL in bge_init_tx_ring"); 1800 if (sc->bge_dma64) { 1801 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1802 BGE_NTXSEG, maxsegsz, 0, 1803 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1804 &dmamap32)) { 1805 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1806 return ENOBUFS; 1807 } 1808 if (dmamap32 == NULL) 1809 panic("dmamap32 NULL in bge_init_tx_ring"); 1810 } else 1811 dmamap32 = dmamap; 1812 dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP); 1813 if (dma == NULL) { 1814 aprint_error_dev(sc->bge_dev, 1815 "can't alloc txdmamap_pool_entry\n"); 1816 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1817 if (sc->bge_dma64) 1818 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1819 return ENOMEM; 1820 } 1821 dma->dmamap = dmamap; 1822 dma->dmamap32 = dmamap32; 1823 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1824 } 1825 alloc_done: 1826 sc->bge_flags |= BGEF_TXRING_VALID; 1827 1828 return 0; 1829 } 1830 1831 static void 1832 bge_setmulti(struct bge_softc *sc) 1833 { 1834 struct ethercom * const ec = &sc->ethercom; 1835 struct ether_multi *enm; 1836 struct ether_multistep step; 1837 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1838 uint32_t h; 1839 int i; 1840 1841 KASSERT(mutex_owned(sc->sc_core_lock)); 1842 if (sc->bge_if_flags & IFF_PROMISC) 1843 goto allmulti; 1844 1845 /* Now program new ones. */ 1846 ETHER_LOCK(ec); 1847 ETHER_FIRST_MULTI(step, ec, enm); 1848 while (enm != NULL) { 1849 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1850 /* 1851 * We must listen to a range of multicast addresses. 1852 * For now, just accept all multicasts, rather than 1853 * trying to set only those filter bits needed to match 1854 * the range. (At this time, the only use of address 1855 * ranges is for IP multicast routing, for which the 1856 * range is big enough to require all bits set.) 1857 */ 1858 ETHER_UNLOCK(ec); 1859 goto allmulti; 1860 } 1861 1862 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1863 1864 /* Just want the 7 least-significant bits. */ 1865 h &= 0x7f; 1866 1867 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1868 ETHER_NEXT_MULTI(step, enm); 1869 } 1870 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1871 ETHER_UNLOCK(ec); 1872 1873 goto setit; 1874 1875 allmulti: 1876 ETHER_LOCK(ec); 1877 ec->ec_flags |= ETHER_F_ALLMULTI; 1878 ETHER_UNLOCK(ec); 1879 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1880 1881 setit: 1882 for (i = 0; i < 4; i++) 1883 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1884 } 1885 1886 static void 1887 bge_sig_pre_reset(struct bge_softc *sc, int type) 1888 { 1889 1890 /* 1891 * Some chips don't like this so only do this if ASF is enabled 1892 */ 1893 if (sc->bge_asf_mode) 1894 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1895 1896 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1897 switch (type) { 1898 case BGE_RESET_START: 1899 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1900 BGE_FW_DRV_STATE_START); 1901 break; 1902 case BGE_RESET_SHUTDOWN: 1903 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1904 BGE_FW_DRV_STATE_UNLOAD); 1905 break; 1906 case BGE_RESET_SUSPEND: 1907 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1908 BGE_FW_DRV_STATE_SUSPEND); 1909 break; 1910 } 1911 } 1912 1913 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1914 bge_ape_driver_state_change(sc, type); 1915 } 1916 1917 static void 1918 bge_sig_post_reset(struct bge_softc *sc, int type) 1919 { 1920 1921 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1922 switch (type) { 1923 case BGE_RESET_START: 1924 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1925 BGE_FW_DRV_STATE_START_DONE); 1926 /* START DONE */ 1927 break; 1928 case BGE_RESET_SHUTDOWN: 1929 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1930 BGE_FW_DRV_STATE_UNLOAD_DONE); 1931 break; 1932 } 1933 } 1934 1935 if (type == BGE_RESET_SHUTDOWN) 1936 bge_ape_driver_state_change(sc, type); 1937 } 1938 1939 static void 1940 bge_sig_legacy(struct bge_softc *sc, int type) 1941 { 1942 1943 if (sc->bge_asf_mode) { 1944 switch (type) { 1945 case BGE_RESET_START: 1946 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1947 BGE_FW_DRV_STATE_START); 1948 break; 1949 case BGE_RESET_SHUTDOWN: 1950 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1951 BGE_FW_DRV_STATE_UNLOAD); 1952 break; 1953 } 1954 } 1955 } 1956 1957 static void 1958 bge_wait_for_event_ack(struct bge_softc *sc) 1959 { 1960 int i; 1961 1962 /* wait up to 2500usec */ 1963 for (i = 0; i < 250; i++) { 1964 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1965 BGE_RX_CPU_DRV_EVENT)) 1966 break; 1967 DELAY(10); 1968 } 1969 } 1970 1971 static void 1972 bge_stop_fw(struct bge_softc *sc) 1973 { 1974 1975 if (sc->bge_asf_mode) { 1976 bge_wait_for_event_ack(sc); 1977 1978 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1979 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1980 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1981 1982 bge_wait_for_event_ack(sc); 1983 } 1984 } 1985 1986 static int 1987 bge_poll_fw(struct bge_softc *sc) 1988 { 1989 uint32_t val; 1990 int i; 1991 1992 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1993 for (i = 0; i < BGE_TIMEOUT; i++) { 1994 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1995 if (val & BGE_VCPU_STATUS_INIT_DONE) 1996 break; 1997 DELAY(100); 1998 } 1999 if (i >= BGE_TIMEOUT) { 2000 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2001 return -1; 2002 } 2003 } else { 2004 /* 2005 * Poll the value location we just wrote until 2006 * we see the 1's complement of the magic number. 2007 * This indicates that the firmware initialization 2008 * is complete. 2009 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2010 */ 2011 for (i = 0; i < BGE_TIMEOUT; i++) { 2012 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2013 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2014 break; 2015 DELAY(10); 2016 } 2017 2018 if ((i >= BGE_TIMEOUT) 2019 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2020 aprint_error_dev(sc->bge_dev, 2021 "firmware handshake timed out, val = %x\n", val); 2022 return -1; 2023 } 2024 } 2025 2026 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2027 /* tg3 says we have to wait extra time */ 2028 delay(10 * 1000); 2029 } 2030 2031 return 0; 2032 } 2033 2034 int 2035 bge_phy_addr(struct bge_softc *sc) 2036 { 2037 struct pci_attach_args *pa = &(sc->bge_pa); 2038 int phy_addr = 1; 2039 2040 /* 2041 * PHY address mapping for various devices. 2042 * 2043 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2044 * ---------+-------+-------+-------+-------+ 2045 * BCM57XX | 1 | X | X | X | 2046 * BCM5704 | 1 | X | 1 | X | 2047 * BCM5717 | 1 | 8 | 2 | 9 | 2048 * BCM5719 | 1 | 8 | 2 | 9 | 2049 * BCM5720 | 1 | 8 | 2 | 9 | 2050 * 2051 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2052 * ---------+-------+-------+-------+-------+ 2053 * BCM57XX | X | X | X | X | 2054 * BCM5704 | X | X | X | X | 2055 * BCM5717 | X | X | X | X | 2056 * BCM5719 | 3 | 10 | 4 | 11 | 2057 * BCM5720 | X | X | X | X | 2058 * 2059 * Other addresses may respond but they are not 2060 * IEEE compliant PHYs and should be ignored. 2061 */ 2062 switch (BGE_ASICREV(sc->bge_chipid)) { 2063 case BGE_ASICREV_BCM5717: 2064 case BGE_ASICREV_BCM5719: 2065 case BGE_ASICREV_BCM5720: 2066 phy_addr = pa->pa_function; 2067 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2068 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2069 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2070 } else { 2071 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2072 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2073 } 2074 } 2075 2076 return phy_addr; 2077 } 2078 2079 /* 2080 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2081 * self-test results. 2082 */ 2083 static int 2084 bge_chipinit(struct bge_softc *sc) 2085 { 2086 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2087 int i; 2088 2089 /* Set endianness before we access any non-PCI registers. */ 2090 misc_ctl = BGE_INIT; 2091 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2092 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2093 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2094 misc_ctl); 2095 2096 /* 2097 * Clear the MAC statistics block in the NIC's 2098 * internal memory. 2099 */ 2100 for (i = BGE_STATS_BLOCK; 2101 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2102 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2103 2104 for (i = BGE_STATUS_BLOCK; 2105 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2106 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2107 2108 /* 5717 workaround from tg3 */ 2109 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2110 /* Save */ 2111 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2112 2113 /* Temporary modify MODE_CTL to control TLP */ 2114 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2115 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2116 2117 /* Control TLP */ 2118 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2119 BGE_TLP_PHYCTL1); 2120 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2121 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2122 2123 /* Restore */ 2124 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2125 } 2126 2127 if (BGE_IS_57765_FAMILY(sc)) { 2128 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2129 /* Save */ 2130 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2131 2132 /* Temporary modify MODE_CTL to control TLP */ 2133 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2134 CSR_WRITE_4(sc, BGE_MODE_CTL, 2135 reg | BGE_MODECTL_PCIE_TLPADDR1); 2136 2137 /* Control TLP */ 2138 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2139 BGE_TLP_PHYCTL5); 2140 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2141 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2142 2143 /* Restore */ 2144 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2145 } 2146 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2147 /* 2148 * For the 57766 and non Ax versions of 57765, bootcode 2149 * needs to setup the PCIE Fast Training Sequence (FTS) 2150 * value to prevent transmit hangs. 2151 */ 2152 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2153 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2154 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2155 2156 /* Save */ 2157 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2158 2159 /* Temporary modify MODE_CTL to control TLP */ 2160 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2161 CSR_WRITE_4(sc, BGE_MODE_CTL, 2162 reg | BGE_MODECTL_PCIE_TLPADDR0); 2163 2164 /* Control TLP */ 2165 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2166 BGE_TLP_FTSMAX); 2167 reg &= ~BGE_TLP_FTSMAX_MSK; 2168 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2169 reg | BGE_TLP_FTSMAX_VAL); 2170 2171 /* Restore */ 2172 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2173 } 2174 2175 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2176 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2177 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2178 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2179 } 2180 2181 /* Set up the PCI DMA control register. */ 2182 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2183 if (sc->bge_flags & BGEF_PCIE) { 2184 /* Read watermark not used, 128 bytes for write. */ 2185 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2186 device_xname(sc->bge_dev))); 2187 if (sc->bge_mps >= 256) 2188 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2189 else 2190 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2191 } else if (sc->bge_flags & BGEF_PCIX) { 2192 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2193 device_xname(sc->bge_dev))); 2194 /* PCI-X bus */ 2195 if (BGE_IS_5714_FAMILY(sc)) { 2196 /* 256 bytes for read and write. */ 2197 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2198 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2199 2200 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2201 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2202 else 2203 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2204 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2205 /* 2206 * In the BCM5703, the DMA read watermark should 2207 * be set to less than or equal to the maximum 2208 * memory read byte count of the PCI-X command 2209 * register. 2210 */ 2211 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2212 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2213 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2214 /* 1536 bytes for read, 384 bytes for write. */ 2215 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2216 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2217 } else { 2218 /* 384 bytes for read and write. */ 2219 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2220 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2221 (0x0F); 2222 } 2223 2224 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2225 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2226 uint32_t tmp; 2227 2228 /* Set ONEDMA_ATONCE for hardware workaround. */ 2229 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2230 if (tmp == 6 || tmp == 7) 2231 dma_rw_ctl |= 2232 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2233 2234 /* Set PCI-X DMA write workaround. */ 2235 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2236 } 2237 } else { 2238 /* Conventional PCI bus: 256 bytes for read and write. */ 2239 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2240 device_xname(sc->bge_dev))); 2241 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2242 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2243 2244 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2245 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2246 dma_rw_ctl |= 0x0F; 2247 } 2248 2249 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2250 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2251 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2252 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2253 2254 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2255 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2256 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2257 2258 if (BGE_IS_57765_PLUS(sc)) { 2259 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2260 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2261 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2262 2263 /* 2264 * Enable HW workaround for controllers that misinterpret 2265 * a status tag update and leave interrupts permanently 2266 * disabled. 2267 */ 2268 if (!BGE_IS_57765_FAMILY(sc) && 2269 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2270 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2271 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2272 } 2273 2274 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2275 dma_rw_ctl); 2276 2277 /* 2278 * Set up general mode register. 2279 */ 2280 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2281 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2282 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2283 /* Retain Host-2-BMC settings written by APE firmware. */ 2284 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2285 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2286 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2287 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2288 } 2289 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2290 BGE_MODECTL_TX_NO_PHDR_CSUM; 2291 2292 /* 2293 * BCM5701 B5 have a bug causing data corruption when using 2294 * 64-bit DMA reads, which can be terminated early and then 2295 * completed later as 32-bit accesses, in combination with 2296 * certain bridges. 2297 */ 2298 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2299 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2300 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2301 2302 /* 2303 * Tell the firmware the driver is running 2304 */ 2305 if (sc->bge_asf_mode & ASF_STACKUP) 2306 mode_ctl |= BGE_MODECTL_STACKUP; 2307 2308 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2309 2310 /* 2311 * Disable memory write invalidate. Apparently it is not supported 2312 * properly by these devices. 2313 */ 2314 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2315 PCI_COMMAND_INVALIDATE_ENABLE); 2316 2317 #ifdef __brokenalpha__ 2318 /* 2319 * Must insure that we do not cross an 8K (bytes) boundary 2320 * for DMA reads. Our highest limit is 1K bytes. This is a 2321 * restriction on some ALPHA platforms with early revision 2322 * 21174 PCI chipsets, such as the AlphaPC 164lx 2323 */ 2324 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2325 #endif 2326 2327 /* Set the timer prescaler (always 66MHz) */ 2328 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2329 2330 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2331 DELAY(40); /* XXX */ 2332 2333 /* Put PHY into ready state */ 2334 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2335 DELAY(40); 2336 } 2337 2338 return 0; 2339 } 2340 2341 static int 2342 bge_blockinit(struct bge_softc *sc) 2343 { 2344 volatile struct bge_rcb *rcb; 2345 bus_size_t rcb_addr; 2346 struct ifnet * const ifp = &sc->ethercom.ec_if; 2347 bge_hostaddr taddr; 2348 uint32_t dmactl, rdmareg, mimode, val; 2349 int i, limit; 2350 2351 /* 2352 * Initialize the memory window pointer register so that 2353 * we can access the first 32K of internal NIC RAM. This will 2354 * allow us to set up the TX send ring RCBs and the RX return 2355 * ring RCBs, plus other things which live in NIC memory. 2356 */ 2357 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2358 2359 if (!BGE_IS_5705_PLUS(sc)) { 2360 /* 57XX step 33 */ 2361 /* Configure mbuf memory pool */ 2362 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2363 2364 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2365 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2366 else 2367 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2368 2369 /* 57XX step 34 */ 2370 /* Configure DMA resource pool */ 2371 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2372 BGE_DMA_DESCRIPTORS); 2373 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2374 } 2375 2376 /* 5718 step 11, 57XX step 35 */ 2377 /* 2378 * Configure mbuf pool watermarks. New broadcom docs strongly 2379 * recommend these. 2380 */ 2381 if (BGE_IS_5717_PLUS(sc)) { 2382 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2383 if (ifp->if_mtu > ETHERMTU) { 2384 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2385 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2386 } else { 2387 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2388 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2389 } 2390 } else if (BGE_IS_5705_PLUS(sc)) { 2391 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2392 2393 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2394 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2395 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2396 } else { 2397 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2398 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2399 } 2400 } else { 2401 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2402 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2403 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2404 } 2405 2406 /* 57XX step 36 */ 2407 /* Configure DMA resource watermarks */ 2408 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2409 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2410 2411 /* 5718 step 13, 57XX step 38 */ 2412 /* Enable buffer manager */ 2413 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2414 /* 2415 * Change the arbitration algorithm of TXMBUF read request to 2416 * round-robin instead of priority based for BCM5719. When 2417 * TXFIFO is almost empty, RDMA will hold its request until 2418 * TXFIFO is not almost empty. 2419 */ 2420 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2421 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2422 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2423 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2424 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2425 val |= BGE_BMANMODE_LOMBUF_ATTN; 2426 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2427 2428 /* 57XX step 39 */ 2429 /* Poll for buffer manager start indication */ 2430 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2431 DELAY(10); 2432 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2433 break; 2434 } 2435 2436 if (i == BGE_TIMEOUT * 2) { 2437 aprint_error_dev(sc->bge_dev, 2438 "buffer manager failed to start\n"); 2439 return ENXIO; 2440 } 2441 2442 /* 57XX step 40 */ 2443 /* Enable flow-through queues */ 2444 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2445 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2446 2447 /* Wait until queue initialization is complete */ 2448 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2449 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2450 break; 2451 DELAY(10); 2452 } 2453 2454 if (i == BGE_TIMEOUT * 2) { 2455 aprint_error_dev(sc->bge_dev, 2456 "flow-through queue init failed\n"); 2457 return ENXIO; 2458 } 2459 2460 /* 2461 * Summary of rings supported by the controller: 2462 * 2463 * Standard Receive Producer Ring 2464 * - This ring is used to feed receive buffers for "standard" 2465 * sized frames (typically 1536 bytes) to the controller. 2466 * 2467 * Jumbo Receive Producer Ring 2468 * - This ring is used to feed receive buffers for jumbo sized 2469 * frames (i.e. anything bigger than the "standard" frames) 2470 * to the controller. 2471 * 2472 * Mini Receive Producer Ring 2473 * - This ring is used to feed receive buffers for "mini" 2474 * sized frames to the controller. 2475 * - This feature required external memory for the controller 2476 * but was never used in a production system. Should always 2477 * be disabled. 2478 * 2479 * Receive Return Ring 2480 * - After the controller has placed an incoming frame into a 2481 * receive buffer that buffer is moved into a receive return 2482 * ring. The driver is then responsible to passing the 2483 * buffer up to the stack. Many versions of the controller 2484 * support multiple RR rings. 2485 * 2486 * Send Ring 2487 * - This ring is used for outgoing frames. Many versions of 2488 * the controller support multiple send rings. 2489 */ 2490 2491 /* 5718 step 15, 57XX step 41 */ 2492 /* Initialize the standard RX ring control block */ 2493 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2494 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2495 /* 5718 step 16 */ 2496 if (BGE_IS_57765_PLUS(sc)) { 2497 /* 2498 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2499 * Bits 15-2 : Maximum RX frame size 2500 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2501 * Bit 0 : Reserved 2502 */ 2503 rcb->bge_maxlen_flags = 2504 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2505 } else if (BGE_IS_5705_PLUS(sc)) { 2506 /* 2507 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2508 * Bits 15-2 : Reserved (should be 0) 2509 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2510 * Bit 0 : Reserved 2511 */ 2512 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2513 } else { 2514 /* 2515 * Ring size is always XXX entries 2516 * Bits 31-16: Maximum RX frame size 2517 * Bits 15-2 : Reserved (should be 0) 2518 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2519 * Bit 0 : Reserved 2520 */ 2521 rcb->bge_maxlen_flags = 2522 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2523 } 2524 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2525 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2526 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2527 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2528 else 2529 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2530 /* Write the standard receive producer ring control block. */ 2531 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2532 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2533 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2534 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2535 2536 /* Reset the standard receive producer ring producer index. */ 2537 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2538 2539 /* 57XX step 42 */ 2540 /* 2541 * Initialize the jumbo RX ring control block 2542 * We set the 'ring disabled' bit in the flags 2543 * field until we're actually ready to start 2544 * using this ring (i.e. once we set the MTU 2545 * high enough to require it). 2546 */ 2547 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2548 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2549 BGE_HOSTADDR(rcb->bge_hostaddr, 2550 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2551 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2552 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2553 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2554 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2555 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2556 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2557 else 2558 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2559 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2560 rcb->bge_hostaddr.bge_addr_hi); 2561 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2562 rcb->bge_hostaddr.bge_addr_lo); 2563 /* Program the jumbo receive producer ring RCB parameters. */ 2564 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2565 rcb->bge_maxlen_flags); 2566 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2567 /* Reset the jumbo receive producer ring producer index. */ 2568 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2569 } 2570 2571 /* 57XX step 43 */ 2572 /* Disable the mini receive producer ring RCB. */ 2573 if (BGE_IS_5700_FAMILY(sc)) { 2574 /* Set up dummy disabled mini ring RCB */ 2575 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2576 rcb->bge_maxlen_flags = 2577 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2578 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2579 rcb->bge_maxlen_flags); 2580 /* Reset the mini receive producer ring producer index. */ 2581 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2582 2583 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2584 offsetof(struct bge_ring_data, bge_info), 2585 sizeof(struct bge_gib), 2586 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2587 } 2588 2589 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2590 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2591 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2592 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2593 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2594 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2595 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2596 } 2597 /* 5718 step 14, 57XX step 44 */ 2598 /* 2599 * The BD ring replenish thresholds control how often the 2600 * hardware fetches new BD's from the producer rings in host 2601 * memory. Setting the value too low on a busy system can 2602 * starve the hardware and reduce the throughput. 2603 * 2604 * Set the BD ring replenish thresholds. The recommended 2605 * values are 1/8th the number of descriptors allocated to 2606 * each ring, but since we try to avoid filling the entire 2607 * ring we set these to the minimal value of 8. This needs to 2608 * be done on several of the supported chip revisions anyway, 2609 * to work around HW bugs. 2610 */ 2611 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2612 if (BGE_IS_JUMBO_CAPABLE(sc)) 2613 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2614 2615 /* 5718 step 18 */ 2616 if (BGE_IS_5717_PLUS(sc)) { 2617 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2618 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2619 } 2620 2621 /* 57XX step 45 */ 2622 /* 2623 * Disable all send rings by setting the 'ring disabled' bit 2624 * in the flags field of all the TX send ring control blocks, 2625 * located in NIC memory. 2626 */ 2627 if (BGE_IS_5700_FAMILY(sc)) { 2628 /* 5700 to 5704 had 16 send rings. */ 2629 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2630 } else if (BGE_IS_5717_PLUS(sc)) { 2631 limit = BGE_TX_RINGS_5717_MAX; 2632 } else if (BGE_IS_57765_FAMILY(sc) || 2633 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2634 limit = BGE_TX_RINGS_57765_MAX; 2635 } else 2636 limit = 1; 2637 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2638 for (i = 0; i < limit; i++) { 2639 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2640 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2641 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2642 rcb_addr += sizeof(struct bge_rcb); 2643 } 2644 2645 /* 57XX step 46 and 47 */ 2646 /* Configure send ring RCB 0 (we use only the first ring) */ 2647 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2648 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2649 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2650 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2651 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2652 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2653 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2654 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2655 else 2656 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2657 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2658 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2659 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2660 2661 /* 57XX step 48 */ 2662 /* 2663 * Disable all receive return rings by setting the 2664 * 'ring disabled' bit in the flags field of all the receive 2665 * return ring control blocks, located in NIC memory. 2666 */ 2667 if (BGE_IS_5717_PLUS(sc)) { 2668 /* Should be 17, use 16 until we get an SRAM map. */ 2669 limit = 16; 2670 } else if (BGE_IS_5700_FAMILY(sc)) 2671 limit = BGE_RX_RINGS_MAX; 2672 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2673 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2674 BGE_IS_57765_FAMILY(sc)) 2675 limit = 4; 2676 else 2677 limit = 1; 2678 /* Disable all receive return rings */ 2679 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2680 for (i = 0; i < limit; i++) { 2681 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2682 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2683 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2684 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2685 BGE_RCB_FLAG_RING_DISABLED)); 2686 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2687 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2688 (i * (sizeof(uint64_t))), 0); 2689 rcb_addr += sizeof(struct bge_rcb); 2690 } 2691 2692 /* 57XX step 49 */ 2693 /* 2694 * Set up receive return ring 0. Note that the NIC address 2695 * for RX return rings is 0x0. The return rings live entirely 2696 * within the host, so the nicaddr field in the RCB isn't used. 2697 */ 2698 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2699 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2700 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2701 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2702 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2703 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2704 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2705 2706 /* 5718 step 24, 57XX step 53 */ 2707 /* Set random backoff seed for TX */ 2708 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2709 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2710 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2711 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2712 BGE_TX_BACKOFF_SEED_MASK); 2713 2714 /* 5718 step 26, 57XX step 55 */ 2715 /* Set inter-packet gap */ 2716 val = 0x2620; 2717 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2718 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2719 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2720 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2721 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2722 2723 /* 5718 step 27, 57XX step 56 */ 2724 /* 2725 * Specify which ring to use for packets that don't match 2726 * any RX rules. 2727 */ 2728 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2729 2730 /* 5718 step 28, 57XX step 57 */ 2731 /* 2732 * Configure number of RX lists. One interrupt distribution 2733 * list, sixteen active lists, one bad frames class. 2734 */ 2735 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2736 2737 /* 5718 step 29, 57XX step 58 */ 2738 /* Initialize RX list placement stats mask. */ 2739 if (BGE_IS_575X_PLUS(sc)) { 2740 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2741 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2742 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2743 } else 2744 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2745 2746 /* 5718 step 30, 57XX step 59 */ 2747 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2748 2749 /* 5718 step 33, 57XX step 62 */ 2750 /* Disable host coalescing until we get it set up */ 2751 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2752 2753 /* 5718 step 34, 57XX step 63 */ 2754 /* Poll to make sure it's shut down. */ 2755 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2756 DELAY(10); 2757 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2758 break; 2759 } 2760 2761 if (i == BGE_TIMEOUT * 2) { 2762 aprint_error_dev(sc->bge_dev, 2763 "host coalescing engine failed to idle\n"); 2764 return ENXIO; 2765 } 2766 2767 /* 5718 step 35, 36, 37 */ 2768 /* Set up host coalescing defaults */ 2769 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2770 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2771 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2772 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2773 if (!(BGE_IS_5705_PLUS(sc))) { 2774 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2775 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2776 } 2777 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2778 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2779 2780 /* Set up address of statistics block */ 2781 if (BGE_IS_5700_FAMILY(sc)) { 2782 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2783 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2784 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2785 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2786 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2787 } 2788 2789 /* 5718 step 38 */ 2790 /* Set up address of status block */ 2791 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2792 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2793 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2794 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2795 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2796 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2797 2798 /* Set up status block size. */ 2799 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2800 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2801 val = BGE_STATBLKSZ_FULL; 2802 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2803 } else { 2804 val = BGE_STATBLKSZ_32BYTE; 2805 bzero(&sc->bge_rdata->bge_status_block, 32); 2806 } 2807 2808 /* 5718 step 39, 57XX step 73 */ 2809 /* Turn on host coalescing state machine */ 2810 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2811 2812 /* 5718 step 40, 57XX step 74 */ 2813 /* Turn on RX BD completion state machine and enable attentions */ 2814 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2815 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2816 2817 /* 5718 step 41, 57XX step 75 */ 2818 /* Turn on RX list placement state machine */ 2819 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2820 2821 /* 57XX step 76 */ 2822 /* Turn on RX list selector state machine. */ 2823 if (!(BGE_IS_5705_PLUS(sc))) 2824 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2825 2826 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2827 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2828 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2829 BGE_MACMODE_FRMHDR_DMA_ENB; 2830 2831 if (sc->bge_flags & BGEF_FIBER_TBI) 2832 val |= BGE_PORTMODE_TBI; 2833 else if (sc->bge_flags & BGEF_FIBER_MII) 2834 val |= BGE_PORTMODE_GMII; 2835 else 2836 val |= BGE_PORTMODE_MII; 2837 2838 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2839 /* Allow APE to send/receive frames. */ 2840 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2841 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2842 2843 /* Turn on DMA, clear stats */ 2844 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2845 /* 5718 step 44 */ 2846 DELAY(40); 2847 2848 /* 5718 step 45, 57XX step 79 */ 2849 /* Set misc. local control, enable interrupts on attentions */ 2850 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2851 if (BGE_IS_5717_PLUS(sc)) { 2852 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2853 /* 5718 step 46 */ 2854 DELAY(100); 2855 } 2856 2857 /* 57XX step 81 */ 2858 /* Turn on DMA completion state machine */ 2859 if (!(BGE_IS_5705_PLUS(sc))) 2860 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2861 2862 /* 5718 step 47, 57XX step 82 */ 2863 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2864 2865 /* 5718 step 48 */ 2866 /* Enable host coalescing bug fix. */ 2867 if (BGE_IS_5755_PLUS(sc)) 2868 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2869 2870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2871 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2872 2873 /* Turn on write DMA state machine */ 2874 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2875 /* 5718 step 49 */ 2876 DELAY(40); 2877 2878 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2879 2880 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2881 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2882 2883 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2884 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2885 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2886 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2887 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2888 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2889 2890 if (sc->bge_flags & BGEF_PCIE) 2891 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2892 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2893 if (ifp->if_mtu <= ETHERMTU) 2894 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2895 } 2896 if (sc->bge_flags & BGEF_TSO) { 2897 val |= BGE_RDMAMODE_TSO4_ENABLE; 2898 if (BGE_IS_5717_PLUS(sc)) 2899 val |= BGE_RDMAMODE_TSO6_ENABLE; 2900 } 2901 2902 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2903 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2904 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2905 BGE_RDMAMODE_H2BNC_VLAN_DET; 2906 /* 2907 * Allow multiple outstanding read requests from 2908 * non-LSO read DMA engine. 2909 */ 2910 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2911 } 2912 2913 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2914 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2915 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2916 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2917 BGE_IS_57765_PLUS(sc)) { 2918 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2919 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2920 else 2921 rdmareg = BGE_RDMA_RSRVCTRL; 2922 dmactl = CSR_READ_4(sc, rdmareg); 2923 /* 2924 * Adjust tx margin to prevent TX data corruption and 2925 * fix internal FIFO overflow. 2926 */ 2927 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2928 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2929 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2930 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2931 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2932 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2933 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2934 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2935 } 2936 /* 2937 * Enable fix for read DMA FIFO overruns. 2938 * The fix is to limit the number of RX BDs 2939 * the hardware would fetch at a time. 2940 */ 2941 CSR_WRITE_4(sc, rdmareg, dmactl | 2942 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2943 } 2944 2945 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2946 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2947 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2948 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2949 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2950 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2951 /* 2952 * Allow 4KB burst length reads for non-LSO frames. 2953 * Enable 512B burst length reads for buffer descriptors. 2954 */ 2955 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2956 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2957 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2958 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2959 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2960 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2961 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2962 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2963 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2964 } 2965 /* Turn on read DMA state machine */ 2966 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2967 /* 5718 step 52 */ 2968 delay(40); 2969 2970 if (sc->bge_flags & BGEF_RDMA_BUG) { 2971 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2972 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2973 if ((val & 0xFFFF) > BGE_FRAMELEN) 2974 break; 2975 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2976 break; 2977 } 2978 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2979 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2980 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2981 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2982 else 2983 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2984 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2985 } 2986 } 2987 2988 /* 5718 step 56, 57XX step 84 */ 2989 /* Turn on RX data completion state machine */ 2990 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2991 2992 /* Turn on RX data and RX BD initiator state machine */ 2993 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2994 2995 /* 57XX step 85 */ 2996 /* Turn on Mbuf cluster free state machine */ 2997 if (!BGE_IS_5705_PLUS(sc)) 2998 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2999 3000 /* 5718 step 57, 57XX step 86 */ 3001 /* Turn on send data completion state machine */ 3002 val = BGE_SDCMODE_ENABLE; 3003 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3004 val |= BGE_SDCMODE_CDELAY; 3005 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3006 3007 /* 5718 step 58 */ 3008 /* Turn on send BD completion state machine */ 3009 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3010 3011 /* 57XX step 88 */ 3012 /* Turn on RX BD initiator state machine */ 3013 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3014 3015 /* 5718 step 60, 57XX step 90 */ 3016 /* Turn on send data initiator state machine */ 3017 if (sc->bge_flags & BGEF_TSO) { 3018 /* XXX: magic value from Linux driver */ 3019 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3020 BGE_SDIMODE_HW_LSO_PRE_DMA); 3021 } else 3022 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3023 3024 /* 5718 step 61, 57XX step 91 */ 3025 /* Turn on send BD initiator state machine */ 3026 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3027 3028 /* 5718 step 62, 57XX step 92 */ 3029 /* Turn on send BD selector state machine */ 3030 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3031 3032 /* 5718 step 31, 57XX step 60 */ 3033 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3034 /* 5718 step 32, 57XX step 61 */ 3035 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3036 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3037 3038 /* ack/clear link change events */ 3039 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3040 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3041 BGE_MACSTAT_LINK_CHANGED); 3042 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3043 3044 /* 3045 * Enable attention when the link has changed state for 3046 * devices that use auto polling. 3047 */ 3048 if (sc->bge_flags & BGEF_FIBER_TBI) { 3049 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3050 } else { 3051 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3052 mimode = BGE_MIMODE_500KHZ_CONST; 3053 else 3054 mimode = BGE_MIMODE_BASE; 3055 /* 5718 step 68. 5718 step 69 (optionally). */ 3056 if (BGE_IS_5700_FAMILY(sc) || 3057 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3058 mimode |= BGE_MIMODE_AUTOPOLL; 3059 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3060 } 3061 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3062 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3063 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3064 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3065 BGE_EVTENB_MI_INTERRUPT); 3066 } 3067 3068 /* 3069 * Clear any pending link state attention. 3070 * Otherwise some link state change events may be lost until attention 3071 * is cleared by bge_intr() -> bge_link_upd() sequence. 3072 * It's not necessary on newer BCM chips - perhaps enabling link 3073 * state change attentions implies clearing pending attention. 3074 */ 3075 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3076 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3077 BGE_MACSTAT_LINK_CHANGED); 3078 3079 /* Enable link state change attentions. */ 3080 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3081 3082 return 0; 3083 } 3084 3085 static const struct bge_revision * 3086 bge_lookup_rev(uint32_t chipid) 3087 { 3088 const struct bge_revision *br; 3089 3090 for (br = bge_revisions; br->br_name != NULL; br++) { 3091 if (br->br_chipid == chipid) 3092 return br; 3093 } 3094 3095 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3096 if (br->br_chipid == BGE_ASICREV(chipid)) 3097 return br; 3098 } 3099 3100 return NULL; 3101 } 3102 3103 static const struct bge_product * 3104 bge_lookup(const struct pci_attach_args *pa) 3105 { 3106 const struct bge_product *bp; 3107 3108 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3109 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3110 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3111 return bp; 3112 } 3113 3114 return NULL; 3115 } 3116 3117 static uint32_t 3118 bge_chipid(const struct pci_attach_args *pa) 3119 { 3120 uint32_t id; 3121 3122 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3123 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3124 3125 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3126 switch (PCI_PRODUCT(pa->pa_id)) { 3127 case PCI_PRODUCT_BROADCOM_BCM5717: 3128 case PCI_PRODUCT_BROADCOM_BCM5718: 3129 case PCI_PRODUCT_BROADCOM_BCM5719: 3130 case PCI_PRODUCT_BROADCOM_BCM5720: 3131 case PCI_PRODUCT_BROADCOM_BCM5725: 3132 case PCI_PRODUCT_BROADCOM_BCM5727: 3133 case PCI_PRODUCT_BROADCOM_BCM5762: 3134 case PCI_PRODUCT_BROADCOM_BCM57764: 3135 case PCI_PRODUCT_BROADCOM_BCM57767: 3136 case PCI_PRODUCT_BROADCOM_BCM57787: 3137 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3138 BGE_PCI_GEN2_PRODID_ASICREV); 3139 break; 3140 case PCI_PRODUCT_BROADCOM_BCM57761: 3141 case PCI_PRODUCT_BROADCOM_BCM57762: 3142 case PCI_PRODUCT_BROADCOM_BCM57765: 3143 case PCI_PRODUCT_BROADCOM_BCM57766: 3144 case PCI_PRODUCT_BROADCOM_BCM57781: 3145 case PCI_PRODUCT_BROADCOM_BCM57782: 3146 case PCI_PRODUCT_BROADCOM_BCM57785: 3147 case PCI_PRODUCT_BROADCOM_BCM57786: 3148 case PCI_PRODUCT_BROADCOM_BCM57791: 3149 case PCI_PRODUCT_BROADCOM_BCM57795: 3150 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3151 BGE_PCI_GEN15_PRODID_ASICREV); 3152 break; 3153 default: 3154 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3155 BGE_PCI_PRODID_ASICREV); 3156 break; 3157 } 3158 } 3159 3160 return id; 3161 } 3162 3163 /* 3164 * Return true if MSI can be used with this device. 3165 */ 3166 static int 3167 bge_can_use_msi(struct bge_softc *sc) 3168 { 3169 int can_use_msi = 0; 3170 3171 switch (BGE_ASICREV(sc->bge_chipid)) { 3172 case BGE_ASICREV_BCM5714_A0: 3173 case BGE_ASICREV_BCM5714: 3174 /* 3175 * Apparently, MSI doesn't work when these chips are 3176 * configured in single-port mode. 3177 */ 3178 break; 3179 case BGE_ASICREV_BCM5750: 3180 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3181 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3182 can_use_msi = 1; 3183 break; 3184 default: 3185 if (BGE_IS_575X_PLUS(sc)) 3186 can_use_msi = 1; 3187 } 3188 return can_use_msi; 3189 } 3190 3191 /* 3192 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3193 * against our list and return its name if we find a match. Note 3194 * that since the Broadcom controller contains VPD support, we 3195 * can get the device name string from the controller itself instead 3196 * of the compiled-in string. This is a little slow, but it guarantees 3197 * we'll always announce the right product name. 3198 */ 3199 static int 3200 bge_probe(device_t parent, cfdata_t match, void *aux) 3201 { 3202 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3203 3204 if (bge_lookup(pa) != NULL) 3205 return 1; 3206 3207 return 0; 3208 } 3209 3210 static void 3211 bge_attach(device_t parent, device_t self, void *aux) 3212 { 3213 struct bge_softc * const sc = device_private(self); 3214 struct pci_attach_args * const pa = aux; 3215 prop_dictionary_t dict; 3216 const struct bge_product *bp; 3217 const struct bge_revision *br; 3218 pci_chipset_tag_t pc; 3219 const char *intrstr = NULL; 3220 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3221 uint32_t command; 3222 struct ifnet *ifp; 3223 struct mii_data * const mii = &sc->bge_mii; 3224 uint32_t misccfg, mimode, macmode; 3225 void * kva; 3226 u_char eaddr[ETHER_ADDR_LEN]; 3227 pcireg_t memtype, subid, reg; 3228 bus_addr_t memaddr; 3229 uint32_t pm_ctl; 3230 bool no_seeprom; 3231 int capmask, trys; 3232 int mii_flags; 3233 int map_flags; 3234 char intrbuf[PCI_INTRSTR_LEN]; 3235 3236 bp = bge_lookup(pa); 3237 KASSERT(bp != NULL); 3238 3239 sc->sc_pc = pa->pa_pc; 3240 sc->sc_pcitag = pa->pa_tag; 3241 sc->bge_dev = self; 3242 3243 sc->bge_pa = *pa; 3244 pc = sc->sc_pc; 3245 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3246 3247 aprint_naive(": Ethernet controller\n"); 3248 aprint_normal(": %s Ethernet\n", bp->bp_name); 3249 3250 /* 3251 * Map control/status registers. 3252 */ 3253 DPRINTFN(5, ("Map control/status regs\n")); 3254 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3255 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3256 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3257 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3258 3259 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3260 aprint_error_dev(sc->bge_dev, 3261 "failed to enable memory mapping!\n"); 3262 return; 3263 } 3264 3265 DPRINTFN(5, ("pci_mem_find\n")); 3266 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3267 switch (memtype) { 3268 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3269 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3270 #if 0 3271 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3272 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3273 &memaddr, &sc->bge_bsize) == 0) 3274 break; 3275 #else 3276 /* 3277 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3278 * system get NMI on boot (PR#48451). This problem might not be 3279 * the driver's bug but our PCI common part's bug. Until we 3280 * find a real reason, we ignore the prefetchable bit. 3281 */ 3282 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3283 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3284 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3285 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3286 map_flags, &sc->bge_bhandle) == 0) { 3287 sc->bge_btag = pa->pa_memt; 3288 break; 3289 } 3290 } 3291 #endif 3292 /* FALLTHROUGH */ 3293 default: 3294 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3295 return; 3296 } 3297 3298 sc->bge_stopping = false; 3299 sc->bge_txrx_stopping = false; 3300 3301 /* Save various chip information. */ 3302 sc->bge_chipid = bge_chipid(pa); 3303 sc->bge_phy_addr = bge_phy_addr(sc); 3304 3305 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3306 &sc->bge_pciecap, NULL) != 0) { 3307 /* PCIe */ 3308 sc->bge_flags |= BGEF_PCIE; 3309 /* Extract supported maximum payload size. */ 3310 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3311 sc->bge_pciecap + PCIE_DCAP); 3312 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3313 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3314 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3315 sc->bge_expmrq = 2048; 3316 else 3317 sc->bge_expmrq = 4096; 3318 bge_set_max_readrq(sc); 3319 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3320 /* PCIe without PCIe cap */ 3321 sc->bge_flags |= BGEF_PCIE; 3322 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3323 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3324 /* PCI-X */ 3325 sc->bge_flags |= BGEF_PCIX; 3326 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3327 &sc->bge_pcixcap, NULL) == 0) 3328 aprint_error_dev(sc->bge_dev, 3329 "unable to find PCIX capability\n"); 3330 } 3331 3332 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3333 /* 3334 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3335 * can clobber the chip's PCI config-space power control 3336 * registers, leaving the card in D3 powersave state. We do 3337 * not have memory-mapped registers in this state, so force 3338 * device into D0 state before starting initialization. 3339 */ 3340 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3341 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3342 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3343 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3344 DELAY(1000); /* 27 usec is allegedly sufficient */ 3345 } 3346 3347 /* Save chipset family. */ 3348 switch (BGE_ASICREV(sc->bge_chipid)) { 3349 case BGE_ASICREV_BCM5717: 3350 case BGE_ASICREV_BCM5719: 3351 case BGE_ASICREV_BCM5720: 3352 sc->bge_flags |= BGEF_5717_PLUS; 3353 /* FALLTHROUGH */ 3354 case BGE_ASICREV_BCM5762: 3355 case BGE_ASICREV_BCM57765: 3356 case BGE_ASICREV_BCM57766: 3357 if (!BGE_IS_5717_PLUS(sc)) 3358 sc->bge_flags |= BGEF_57765_FAMILY; 3359 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3360 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3361 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3362 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3363 /* 3364 * Enable work around for DMA engine miscalculation 3365 * of TXMBUF available space. 3366 */ 3367 sc->bge_flags |= BGEF_RDMA_BUG; 3368 3369 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3370 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3371 /* Jumbo frame on BCM5719 A0 does not work. */ 3372 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3373 } 3374 } 3375 break; 3376 case BGE_ASICREV_BCM5755: 3377 case BGE_ASICREV_BCM5761: 3378 case BGE_ASICREV_BCM5784: 3379 case BGE_ASICREV_BCM5785: 3380 case BGE_ASICREV_BCM5787: 3381 case BGE_ASICREV_BCM57780: 3382 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3383 break; 3384 case BGE_ASICREV_BCM5700: 3385 case BGE_ASICREV_BCM5701: 3386 case BGE_ASICREV_BCM5703: 3387 case BGE_ASICREV_BCM5704: 3388 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3389 break; 3390 case BGE_ASICREV_BCM5714_A0: 3391 case BGE_ASICREV_BCM5780: 3392 case BGE_ASICREV_BCM5714: 3393 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3394 /* FALLTHROUGH */ 3395 case BGE_ASICREV_BCM5750: 3396 case BGE_ASICREV_BCM5752: 3397 case BGE_ASICREV_BCM5906: 3398 sc->bge_flags |= BGEF_575X_PLUS; 3399 /* FALLTHROUGH */ 3400 case BGE_ASICREV_BCM5705: 3401 sc->bge_flags |= BGEF_5705_PLUS; 3402 break; 3403 } 3404 3405 /* Identify chips with APE processor. */ 3406 switch (BGE_ASICREV(sc->bge_chipid)) { 3407 case BGE_ASICREV_BCM5717: 3408 case BGE_ASICREV_BCM5719: 3409 case BGE_ASICREV_BCM5720: 3410 case BGE_ASICREV_BCM5761: 3411 case BGE_ASICREV_BCM5762: 3412 sc->bge_flags |= BGEF_APE; 3413 break; 3414 } 3415 3416 /* 3417 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3418 * not actually a MAC controller bug but an issue with the embedded 3419 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3420 */ 3421 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3422 sc->bge_flags |= BGEF_40BIT_BUG; 3423 3424 /* Chips with APE need BAR2 access for APE registers/memory. */ 3425 if ((sc->bge_flags & BGEF_APE) != 0) { 3426 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3427 #if 0 3428 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3429 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3430 &sc->bge_apesize)) { 3431 aprint_error_dev(sc->bge_dev, 3432 "couldn't map BAR2 memory\n"); 3433 return; 3434 } 3435 #else 3436 /* 3437 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3438 * system get NMI on boot (PR#48451). This problem might not be 3439 * the driver's bug but our PCI common part's bug. Until we 3440 * find a real reason, we ignore the prefetchable bit. 3441 */ 3442 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3443 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3444 aprint_error_dev(sc->bge_dev, 3445 "couldn't map BAR2 memory\n"); 3446 return; 3447 } 3448 3449 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3450 if (bus_space_map(pa->pa_memt, memaddr, 3451 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3452 aprint_error_dev(sc->bge_dev, 3453 "couldn't map BAR2 memory\n"); 3454 return; 3455 } 3456 sc->bge_apetag = pa->pa_memt; 3457 #endif 3458 3459 /* Enable APE register/memory access by host driver. */ 3460 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3461 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3462 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3463 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3464 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3465 3466 bge_ape_lock_init(sc); 3467 bge_ape_read_fw_ver(sc); 3468 } 3469 3470 /* Identify the chips that use an CPMU. */ 3471 if (BGE_IS_5717_PLUS(sc) || 3472 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3473 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3474 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3475 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3476 sc->bge_flags |= BGEF_CPMU_PRESENT; 3477 3478 /* 3479 * When using the BCM5701 in PCI-X mode, data corruption has 3480 * been observed in the first few bytes of some received packets. 3481 * Aligning the packet buffer in memory eliminates the corruption. 3482 * Unfortunately, this misaligns the packet payloads. On platforms 3483 * which do not support unaligned accesses, we will realign the 3484 * payloads by copying the received packets. 3485 */ 3486 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3487 sc->bge_flags & BGEF_PCIX) 3488 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3489 3490 if (BGE_IS_5700_FAMILY(sc)) 3491 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3492 3493 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3494 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3495 3496 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3497 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3498 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3499 sc->bge_flags |= BGEF_IS_5788; 3500 3501 /* 3502 * Some controllers seem to require a special firmware to use 3503 * TSO. But the firmware is not available to FreeBSD and Linux 3504 * claims that the TSO performed by the firmware is slower than 3505 * hardware based TSO. Moreover the firmware based TSO has one 3506 * known bug which can't handle TSO if ethernet header + IP/TCP 3507 * header is greater than 80 bytes. The workaround for the TSO 3508 * bug exist but it seems it's too expensive than not using 3509 * TSO at all. Some hardware also have the TSO bug so limit 3510 * the TSO to the controllers that are not affected TSO issues 3511 * (e.g. 5755 or higher). 3512 */ 3513 if (BGE_IS_5755_PLUS(sc)) { 3514 /* 3515 * BCM5754 and BCM5787 shares the same ASIC id so 3516 * explicit device id check is required. 3517 */ 3518 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3519 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3520 sc->bge_flags |= BGEF_TSO; 3521 /* TSO on BCM5719 A0 does not work. */ 3522 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3523 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3524 sc->bge_flags &= ~BGEF_TSO; 3525 } 3526 3527 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3528 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3529 (misccfg == 0x4000 || misccfg == 0x8000)) || 3530 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3531 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3532 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3533 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3534 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3535 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3536 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3537 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3538 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3539 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3540 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3541 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3542 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3543 /* These chips are 10/100 only. */ 3544 capmask &= ~BMSR_EXTSTAT; 3545 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3546 } 3547 3548 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3549 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3550 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3551 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3552 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3553 3554 /* Set various PHY bug flags. */ 3555 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3556 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3557 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3558 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3559 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3560 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3561 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3562 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3563 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3564 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3565 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3566 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3567 if (BGE_IS_5705_PLUS(sc) && 3568 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3569 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3570 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3571 !BGE_IS_57765_PLUS(sc)) { 3572 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3573 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3574 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3575 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3576 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3577 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3578 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3579 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3580 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3581 } else 3582 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3583 } 3584 3585 /* 3586 * SEEPROM check. 3587 * First check if firmware knows we do not have SEEPROM. 3588 */ 3589 if (prop_dictionary_get_bool(device_properties(self), 3590 "without-seeprom", &no_seeprom) && no_seeprom) 3591 sc->bge_flags |= BGEF_NO_EEPROM; 3592 3593 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3594 sc->bge_flags |= BGEF_NO_EEPROM; 3595 3596 /* Now check the 'ROM failed' bit on the RX CPU */ 3597 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3598 sc->bge_flags |= BGEF_NO_EEPROM; 3599 3600 sc->bge_asf_mode = 0; 3601 /* No ASF if APE present. */ 3602 if ((sc->bge_flags & BGEF_APE) == 0) { 3603 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3604 BGE_SRAM_DATA_SIG_MAGIC)) { 3605 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3606 BGE_HWCFG_ASF) { 3607 sc->bge_asf_mode |= ASF_ENABLE; 3608 sc->bge_asf_mode |= ASF_STACKUP; 3609 if (BGE_IS_575X_PLUS(sc)) 3610 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3611 } 3612 } 3613 } 3614 3615 int counts[PCI_INTR_TYPE_SIZE] = { 3616 [PCI_INTR_TYPE_INTX] = 1, 3617 [PCI_INTR_TYPE_MSI] = 1, 3618 [PCI_INTR_TYPE_MSIX] = 1, 3619 }; 3620 int max_type = PCI_INTR_TYPE_MSIX; 3621 3622 if (!bge_can_use_msi(sc)) { 3623 /* MSI broken, allow only INTx */ 3624 max_type = PCI_INTR_TYPE_INTX; 3625 } 3626 3627 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3628 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3629 return; 3630 } 3631 3632 DPRINTFN(5, ("pci_intr_string\n")); 3633 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3634 sizeof(intrbuf)); 3635 DPRINTFN(5, ("pci_intr_establish\n")); 3636 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3637 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3638 if (sc->bge_intrhand == NULL) { 3639 pci_intr_release(pc, sc->bge_pihp, 1); 3640 sc->bge_pihp = NULL; 3641 3642 aprint_error_dev(self, "couldn't establish interrupt"); 3643 if (intrstr != NULL) 3644 aprint_error(" at %s", intrstr); 3645 aprint_error("\n"); 3646 return; 3647 } 3648 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3649 3650 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3651 case PCI_INTR_TYPE_MSIX: 3652 case PCI_INTR_TYPE_MSI: 3653 KASSERT(bge_can_use_msi(sc)); 3654 sc->bge_flags |= BGEF_MSI; 3655 break; 3656 default: 3657 /* nothing to do */ 3658 break; 3659 } 3660 3661 char wqname[MAXCOMLEN]; 3662 snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->bge_dev)); 3663 int error = workqueue_create(&sc->sc_reset_wq, wqname, 3664 bge_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK, 3665 WQ_MPSAFE); 3666 if (error) { 3667 aprint_error_dev(sc->bge_dev, 3668 "unable to create reset workqueue\n"); 3669 return; 3670 } 3671 3672 3673 /* 3674 * All controllers except BCM5700 supports tagged status but 3675 * we use tagged status only for MSI case on BCM5717. Otherwise 3676 * MSI on BCM5717 does not work. 3677 */ 3678 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3679 sc->bge_flags |= BGEF_TAGGED_STATUS; 3680 3681 /* 3682 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3683 * lock in bge_reset(). 3684 */ 3685 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3686 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3687 delay(1000); 3688 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3689 3690 bge_stop_fw(sc); 3691 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3692 if (bge_reset(sc)) 3693 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3694 3695 /* 3696 * Read the hardware config word in the first 32k of NIC internal 3697 * memory, or fall back to the config word in the EEPROM. 3698 * Note: on some BCM5700 cards, this value appears to be unset. 3699 */ 3700 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3701 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3702 BGE_SRAM_DATA_SIG_MAGIC) { 3703 uint32_t tmp; 3704 3705 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3706 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3707 BGE_SRAM_DATA_VER_SHIFT; 3708 if ((0 < tmp) && (tmp < 0x100)) 3709 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3710 if (sc->bge_flags & BGEF_PCIE) 3711 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3712 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3713 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3714 if (BGE_IS_5717_PLUS(sc)) 3715 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3716 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3717 bge_read_eeprom(sc, (void *)&hwcfg, 3718 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3719 hwcfg = be32toh(hwcfg); 3720 } 3721 aprint_normal_dev(sc->bge_dev, 3722 "HW config %08x, %08x, %08x, %08x %08x\n", 3723 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3724 3725 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3726 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3727 3728 if (bge_chipinit(sc)) { 3729 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3730 bge_release_resources(sc); 3731 return; 3732 } 3733 3734 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3735 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3736 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3737 DELAY(100); 3738 } 3739 3740 /* Set MI_MODE */ 3741 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3742 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3743 mimode |= BGE_MIMODE_500KHZ_CONST; 3744 else 3745 mimode |= BGE_MIMODE_BASE; 3746 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3747 DELAY(80); 3748 3749 /* 3750 * Get station address from the EEPROM. 3751 */ 3752 if (bge_get_eaddr(sc, eaddr)) { 3753 aprint_error_dev(sc->bge_dev, 3754 "failed to read station address\n"); 3755 bge_release_resources(sc); 3756 return; 3757 } 3758 3759 br = bge_lookup_rev(sc->bge_chipid); 3760 3761 if (br == NULL) { 3762 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3763 sc->bge_chipid); 3764 } else { 3765 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3766 br->br_name, sc->bge_chipid); 3767 } 3768 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3769 3770 /* Allocate the general information block and ring buffers. */ 3771 if (pci_dma64_available(pa)) { 3772 sc->bge_dmatag = pa->pa_dmat64; 3773 sc->bge_dmatag32 = pa->pa_dmat; 3774 sc->bge_dma64 = true; 3775 } else { 3776 sc->bge_dmatag = pa->pa_dmat; 3777 sc->bge_dmatag32 = pa->pa_dmat; 3778 sc->bge_dma64 = false; 3779 } 3780 3781 /* 40bit DMA workaround */ 3782 if (sizeof(bus_addr_t) > 4) { 3783 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3784 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3785 3786 if (bus_dmatag_subregion(olddmatag, 0, 3787 (bus_addr_t)__MASK(40), 3788 &(sc->bge_dmatag), BUS_DMA_WAITOK) != 0) { 3789 aprint_error_dev(self, 3790 "WARNING: failed to restrict dma range," 3791 " falling back to parent bus dma range\n"); 3792 sc->bge_dmatag = olddmatag; 3793 } 3794 } 3795 } 3796 SLIST_INIT(&sc->txdma_list); 3797 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3798 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3799 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3800 &sc->bge_ring_rseg, BUS_DMA_WAITOK)) { 3801 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3802 return; 3803 } 3804 DPRINTFN(5, ("bus_dmamem_map\n")); 3805 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3806 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3807 BUS_DMA_WAITOK)) { 3808 aprint_error_dev(sc->bge_dev, 3809 "can't map DMA buffers (%zu bytes)\n", 3810 sizeof(struct bge_ring_data)); 3811 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3812 sc->bge_ring_rseg); 3813 return; 3814 } 3815 DPRINTFN(5, ("bus_dmamap_create\n")); 3816 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3817 sizeof(struct bge_ring_data), 0, 3818 BUS_DMA_WAITOK, &sc->bge_ring_map)) { 3819 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3820 bus_dmamem_unmap(sc->bge_dmatag, kva, 3821 sizeof(struct bge_ring_data)); 3822 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3823 sc->bge_ring_rseg); 3824 return; 3825 } 3826 DPRINTFN(5, ("bus_dmamap_load\n")); 3827 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3828 sizeof(struct bge_ring_data), NULL, 3829 BUS_DMA_WAITOK)) { 3830 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3831 bus_dmamem_unmap(sc->bge_dmatag, kva, 3832 sizeof(struct bge_ring_data)); 3833 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3834 sc->bge_ring_rseg); 3835 return; 3836 } 3837 3838 DPRINTFN(5, ("bzero\n")); 3839 sc->bge_rdata = (struct bge_ring_data *)kva; 3840 3841 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3842 3843 /* Try to allocate memory for jumbo buffers. */ 3844 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3845 if (bge_alloc_jumbo_mem(sc)) { 3846 aprint_error_dev(sc->bge_dev, 3847 "jumbo buffer allocation failed\n"); 3848 } else 3849 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3850 } 3851 3852 /* Set default tuneable values. */ 3853 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3854 sc->bge_rx_coal_ticks = 150; 3855 sc->bge_rx_max_coal_bds = 64; 3856 sc->bge_tx_coal_ticks = 300; 3857 sc->bge_tx_max_coal_bds = 400; 3858 if (BGE_IS_5705_PLUS(sc)) { 3859 sc->bge_tx_coal_ticks = (12 * 5); 3860 sc->bge_tx_max_coal_bds = (12 * 5); 3861 aprint_verbose_dev(sc->bge_dev, 3862 "setting short Tx thresholds\n"); 3863 } 3864 3865 if (BGE_IS_5717_PLUS(sc)) 3866 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3867 else if (BGE_IS_5705_PLUS(sc)) 3868 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3869 else 3870 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3871 3872 sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NONE); 3873 sc->sc_intr_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 3874 3875 /* Set up ifnet structure */ 3876 ifp = &sc->ethercom.ec_if; 3877 ifp->if_softc = sc; 3878 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3879 ifp->if_extflags = IFEF_MPSAFE; 3880 ifp->if_ioctl = bge_ioctl; 3881 ifp->if_stop = bge_stop; 3882 ifp->if_start = bge_start; 3883 ifp->if_init = bge_init; 3884 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3885 IFQ_SET_READY(&ifp->if_snd); 3886 DPRINTFN(5, ("strcpy if_xname\n")); 3887 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3888 3889 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3890 sc->ethercom.ec_if.if_capabilities |= 3891 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3892 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3893 sc->ethercom.ec_if.if_capabilities |= 3894 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3895 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3896 #endif 3897 sc->ethercom.ec_capabilities |= 3898 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3899 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3900 3901 if (sc->bge_flags & BGEF_TSO) 3902 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3903 3904 /* 3905 * Do MII setup. 3906 */ 3907 DPRINTFN(5, ("mii setup\n")); 3908 mii->mii_ifp = ifp; 3909 mii->mii_readreg = bge_miibus_readreg; 3910 mii->mii_writereg = bge_miibus_writereg; 3911 mii->mii_statchg = bge_miibus_statchg; 3912 3913 /* 3914 * Figure out what sort of media we have by checking the hardware 3915 * config word. Note: on some BCM5700 cards, this value appears to be 3916 * unset. If that's the case, we have to rely on identifying the NIC 3917 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3918 * The SysKonnect SK-9D41 is a 1000baseSX card. 3919 */ 3920 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3921 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3922 if (BGE_IS_5705_PLUS(sc)) { 3923 sc->bge_flags |= BGEF_FIBER_MII; 3924 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3925 } else 3926 sc->bge_flags |= BGEF_FIBER_TBI; 3927 } 3928 3929 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3930 if (BGE_IS_JUMBO_CAPABLE(sc)) 3931 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3932 3933 /* set phyflags and chipid before mii_attach() */ 3934 dict = device_properties(self); 3935 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3936 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3937 3938 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3939 macmode &= ~BGE_MACMODE_PORTMODE; 3940 /* Initialize ifmedia structures. */ 3941 if (sc->bge_flags & BGEF_FIBER_TBI) { 3942 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3943 macmode | BGE_PORTMODE_TBI); 3944 DELAY(40); 3945 3946 struct ifmedia * const ifm = &sc->bge_ifmedia; 3947 sc->ethercom.ec_ifmedia = ifm; 3948 3949 ifmedia_init_with_lock(ifm, IFM_IMASK, 3950 bge_ifmedia_upd, bge_ifmedia_sts, sc->sc_intr_lock); 3951 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX, 0, NULL); 3952 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 3953 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 3954 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 3955 /* Pretend the user requested this setting */ 3956 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3957 } else { 3958 uint16_t phyreg; 3959 int rv; 3960 /* 3961 * Do transceiver setup and tell the firmware the 3962 * driver is down so we can try to get access the 3963 * probe if ASF is running. Retry a couple of times 3964 * if we get a conflict with the ASF firmware accessing 3965 * the PHY. 3966 */ 3967 if (sc->bge_flags & BGEF_FIBER_MII) 3968 macmode |= BGE_PORTMODE_GMII; 3969 else 3970 macmode |= BGE_PORTMODE_MII; 3971 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3972 DELAY(40); 3973 3974 /* 3975 * Do transceiver setup and tell the firmware the 3976 * driver is down so we can try to get access the 3977 * probe if ASF is running. Retry a couple of times 3978 * if we get a conflict with the ASF firmware accessing 3979 * the PHY. 3980 */ 3981 trys = 0; 3982 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3983 sc->ethercom.ec_mii = mii; 3984 ifmedia_init_with_lock(&mii->mii_media, 0, bge_ifmedia_upd, 3985 bge_ifmedia_sts, sc->sc_intr_lock); 3986 mii_flags = MIIF_DOPAUSE; 3987 if (sc->bge_flags & BGEF_FIBER_MII) 3988 mii_flags |= MIIF_HAVEFIBER; 3989 again: 3990 bge_asf_driver_up(sc); 3991 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 3992 MII_BMCR, &phyreg); 3993 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 3994 int i; 3995 3996 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 3997 MII_BMCR, BMCR_RESET); 3998 /* Wait up to 500ms for it to complete. */ 3999 for (i = 0; i < 500; i++) { 4000 bge_miibus_readreg(sc->bge_dev, 4001 sc->bge_phy_addr, MII_BMCR, &phyreg); 4002 if ((phyreg & BMCR_RESET) == 0) 4003 break; 4004 DELAY(1000); 4005 } 4006 } 4007 4008 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 4009 MII_OFFSET_ANY, mii_flags); 4010 4011 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 4012 goto again; 4013 4014 if (LIST_EMPTY(&mii->mii_phys)) { 4015 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4016 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 4017 0, NULL); 4018 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 4019 } else 4020 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 4021 4022 /* 4023 * Now tell the firmware we are going up after probing the PHY 4024 */ 4025 if (sc->bge_asf_mode & ASF_STACKUP) 4026 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4027 } 4028 4029 /* 4030 * Call MI attach routine. 4031 */ 4032 DPRINTFN(5, ("if_initialize\n")); 4033 if_initialize(ifp); 4034 ifp->if_percpuq = if_percpuq_create(ifp); 4035 if_deferred_start_init(ifp, NULL); 4036 if_register(ifp); 4037 4038 DPRINTFN(5, ("ether_ifattach\n")); 4039 ether_ifattach(ifp, eaddr); 4040 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4041 4042 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4043 RND_TYPE_NET, RND_FLAG_DEFAULT); 4044 #ifdef BGE_EVENT_COUNTERS 4045 /* 4046 * Attach event counters. 4047 */ 4048 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4049 NULL, device_xname(sc->bge_dev), "intr"); 4050 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4051 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4052 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4053 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4054 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4055 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4056 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4057 NULL, device_xname(sc->bge_dev), "tx_xon"); 4058 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4059 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4060 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4061 NULL, device_xname(sc->bge_dev), "rx_xon"); 4062 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4063 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4064 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4065 NULL, device_xname(sc->bge_dev), "xoffentered"); 4066 #endif /* BGE_EVENT_COUNTERS */ 4067 DPRINTFN(5, ("callout_init\n")); 4068 callout_init(&sc->bge_timeout, CALLOUT_MPSAFE); 4069 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4070 4071 if (pmf_device_register(self, NULL, NULL)) 4072 pmf_class_network_register(self, ifp); 4073 else 4074 aprint_error_dev(self, "couldn't establish power handler\n"); 4075 4076 bge_sysctl_init(sc); 4077 4078 #ifdef BGE_DEBUG 4079 bge_debug_info(sc); 4080 #endif 4081 } 4082 4083 /* 4084 * Stop all chip I/O so that the kernel's probe routines don't 4085 * get confused by errant DMAs when rebooting. 4086 */ 4087 static int 4088 bge_detach(device_t self, int flags __unused) 4089 { 4090 struct bge_softc * const sc = device_private(self); 4091 struct ifnet * const ifp = &sc->ethercom.ec_if; 4092 4093 IFNET_LOCK(ifp); 4094 4095 /* Stop the interface. Callouts are stopped in it. */ 4096 bge_stop(ifp, 1); 4097 sc->bge_detaching = true; 4098 4099 IFNET_UNLOCK(ifp); 4100 4101 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4102 4103 ether_ifdetach(ifp); 4104 if_detach(ifp); 4105 4106 /* Delete all remaining media. */ 4107 ifmedia_fini(&sc->bge_mii.mii_media); 4108 4109 bge_release_resources(sc); 4110 4111 return 0; 4112 } 4113 4114 static void 4115 bge_release_resources(struct bge_softc *sc) 4116 { 4117 4118 /* Detach sysctl */ 4119 if (sc->bge_log != NULL) 4120 sysctl_teardown(&sc->bge_log); 4121 4122 #ifdef BGE_EVENT_COUNTERS 4123 /* Detach event counters. */ 4124 evcnt_detach(&sc->bge_ev_intr); 4125 evcnt_detach(&sc->bge_ev_intr_spurious); 4126 evcnt_detach(&sc->bge_ev_intr_spurious2); 4127 evcnt_detach(&sc->bge_ev_tx_xoff); 4128 evcnt_detach(&sc->bge_ev_tx_xon); 4129 evcnt_detach(&sc->bge_ev_rx_xoff); 4130 evcnt_detach(&sc->bge_ev_rx_xon); 4131 evcnt_detach(&sc->bge_ev_rx_macctl); 4132 evcnt_detach(&sc->bge_ev_xoffentered); 4133 #endif /* BGE_EVENT_COUNTERS */ 4134 4135 /* Disestablish the interrupt handler */ 4136 if (sc->bge_intrhand != NULL) { 4137 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4138 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4139 sc->bge_intrhand = NULL; 4140 } 4141 4142 if (sc->bge_cdata.bge_jumbo_buf != NULL) 4143 bge_free_jumbo_mem(sc); 4144 4145 if (sc->bge_dmatag != NULL) { 4146 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4147 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4148 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4149 sizeof(struct bge_ring_data)); 4150 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4151 sc->bge_ring_rseg); 4152 } 4153 4154 /* Unmap the device registers */ 4155 if (sc->bge_bsize != 0) { 4156 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4157 sc->bge_bsize = 0; 4158 } 4159 4160 /* Unmap the APE registers */ 4161 if (sc->bge_apesize != 0) { 4162 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4163 sc->bge_apesize); 4164 sc->bge_apesize = 0; 4165 } 4166 } 4167 4168 static int 4169 bge_reset(struct bge_softc *sc) 4170 { 4171 uint32_t cachesize, command; 4172 uint32_t reset, mac_mode, mac_mode_mask; 4173 pcireg_t devctl, reg; 4174 int i, val; 4175 void (*write_op)(struct bge_softc *, int, int); 4176 4177 /* Make mask for BGE_MAC_MODE register. */ 4178 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4179 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4180 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4181 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4182 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4183 4184 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4185 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4186 if (sc->bge_flags & BGEF_PCIE) 4187 write_op = bge_writemem_direct; 4188 else 4189 write_op = bge_writemem_ind; 4190 } else 4191 write_op = bge_writereg_ind; 4192 4193 /* 57XX step 4 */ 4194 /* Acquire the NVM lock */ 4195 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4196 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4197 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4198 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4199 for (i = 0; i < 8000; i++) { 4200 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4201 BGE_NVRAMSWARB_GNT1) 4202 break; 4203 DELAY(20); 4204 } 4205 if (i == 8000) { 4206 printf("%s: NVRAM lock timedout!\n", 4207 device_xname(sc->bge_dev)); 4208 } 4209 } 4210 4211 /* Take APE lock when performing reset. */ 4212 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4213 4214 /* 57XX step 3 */ 4215 /* Save some important PCI state. */ 4216 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4217 /* 5718 reset step 3 */ 4218 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4219 4220 /* 5718 reset step 5, 57XX step 5b-5d */ 4221 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4222 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4223 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4224 4225 /* XXX ???: Disable fastboot on controllers that support it. */ 4226 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4227 BGE_IS_5755_PLUS(sc)) 4228 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4229 4230 /* 5718 reset step 2, 57XX step 6 */ 4231 /* 4232 * Write the magic number to SRAM at offset 0xB50. 4233 * When firmware finishes its initialization it will 4234 * write ~BGE_MAGIC_NUMBER to the same location. 4235 */ 4236 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4237 4238 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4239 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4240 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4241 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4242 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4243 } 4244 4245 /* 5718 reset step 6, 57XX step 7 */ 4246 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4247 /* 4248 * XXX: from FreeBSD/Linux; no documentation 4249 */ 4250 if (sc->bge_flags & BGEF_PCIE) { 4251 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4252 !BGE_IS_57765_PLUS(sc) && 4253 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4254 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4255 /* PCI Express 1.0 system */ 4256 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4257 BGE_PHY_PCIE_SCRAM_MODE); 4258 } 4259 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4260 /* 4261 * Prevent PCI Express link training 4262 * during global reset. 4263 */ 4264 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4265 reset |= (1 << 29); 4266 } 4267 } 4268 4269 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4270 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4271 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4272 i | BGE_VCPU_STATUS_DRV_RESET); 4273 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4274 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4275 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4276 } 4277 4278 /* 4279 * Set GPHY Power Down Override to leave GPHY 4280 * powered up in D0 uninitialized. 4281 */ 4282 if (BGE_IS_5705_PLUS(sc) && 4283 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4284 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4285 4286 /* Issue global reset */ 4287 write_op(sc, BGE_MISC_CFG, reset); 4288 4289 /* 5718 reset step 7, 57XX step 8 */ 4290 if (sc->bge_flags & BGEF_PCIE) 4291 delay(100*1000); /* too big */ 4292 else 4293 delay(1000); 4294 4295 if (sc->bge_flags & BGEF_PCIE) { 4296 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4297 DELAY(500000); 4298 /* XXX: Magic Numbers */ 4299 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4300 BGE_PCI_UNKNOWN0); 4301 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4302 BGE_PCI_UNKNOWN0, 4303 reg | (1 << 15)); 4304 } 4305 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4306 sc->bge_pciecap + PCIE_DCSR); 4307 /* Clear enable no snoop and disable relaxed ordering. */ 4308 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4309 PCIE_DCSR_ENA_NO_SNOOP); 4310 4311 /* Set PCIE max payload size to 128 for older PCIe devices */ 4312 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4313 devctl &= ~(0x00e0); 4314 /* Clear device status register. Write 1b to clear */ 4315 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4316 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4317 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4318 sc->bge_pciecap + PCIE_DCSR, devctl); 4319 bge_set_max_readrq(sc); 4320 } 4321 4322 /* From Linux: dummy read to flush PCI posted writes */ 4323 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4324 4325 /* 4326 * Reset some of the PCI state that got zapped by reset 4327 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4328 * set, too. 4329 */ 4330 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4331 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4332 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4333 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4334 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4335 (sc->bge_flags & BGEF_PCIX) != 0) 4336 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4337 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4338 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4339 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4340 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4341 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4342 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4343 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4344 4345 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4346 if (sc->bge_flags & BGEF_PCIX) { 4347 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4348 + PCIX_CMD); 4349 /* Set max memory read byte count to 2K */ 4350 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4351 reg &= ~PCIX_CMD_BYTECNT_MASK; 4352 reg |= PCIX_CMD_BCNT_2048; 4353 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4354 /* 4355 * For 5704, set max outstanding split transaction 4356 * field to 0 (0 means it supports 1 request) 4357 */ 4358 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4359 | PCIX_CMD_BYTECNT_MASK); 4360 reg |= PCIX_CMD_BCNT_2048; 4361 } 4362 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4363 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4364 } 4365 4366 /* 5718 reset step 10, 57XX step 12 */ 4367 /* Enable memory arbiter. */ 4368 if (BGE_IS_5714_FAMILY(sc)) { 4369 val = CSR_READ_4(sc, BGE_MARB_MODE); 4370 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4371 } else 4372 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4373 4374 /* XXX 5721, 5751 and 5752 */ 4375 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4376 /* Step 19: */ 4377 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4378 /* Step 20: */ 4379 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4380 } 4381 4382 /* 5718 reset step 12, 57XX step 15 and 16 */ 4383 /* Fix up byte swapping */ 4384 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4385 4386 /* 5718 reset step 13, 57XX step 17 */ 4387 /* Poll until the firmware initialization is complete */ 4388 bge_poll_fw(sc); 4389 4390 /* 57XX step 21 */ 4391 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4392 pcireg_t msidata; 4393 4394 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4395 BGE_PCI_MSI_DATA); 4396 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4397 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4398 msidata); 4399 } 4400 4401 /* 57XX step 18 */ 4402 /* Write mac mode. */ 4403 val = CSR_READ_4(sc, BGE_MAC_MODE); 4404 /* Restore mac_mode_mask's bits using mac_mode */ 4405 val = (val & ~mac_mode_mask) | mac_mode; 4406 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4407 DELAY(40); 4408 4409 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4410 4411 /* 4412 * The 5704 in TBI mode apparently needs some special 4413 * adjustment to insure the SERDES drive level is set 4414 * to 1.2V. 4415 */ 4416 if (sc->bge_flags & BGEF_FIBER_TBI && 4417 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4418 uint32_t serdescfg; 4419 4420 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4421 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4422 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4423 } 4424 4425 if (sc->bge_flags & BGEF_PCIE && 4426 !BGE_IS_57765_PLUS(sc) && 4427 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4428 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4429 uint32_t v; 4430 4431 /* Enable PCI Express bug fix */ 4432 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4433 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4434 v | BGE_TLP_DATA_FIFO_PROTECT); 4435 } 4436 4437 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4438 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4439 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4440 4441 return 0; 4442 } 4443 4444 /* 4445 * Frame reception handling. This is called if there's a frame 4446 * on the receive return list. 4447 * 4448 * Note: we have to be able to handle two possibilities here: 4449 * 1) the frame is from the jumbo receive ring 4450 * 2) the frame is from the standard receive ring 4451 */ 4452 4453 static void 4454 bge_rxeof(struct bge_softc *sc) 4455 { 4456 struct ifnet * const ifp = &sc->ethercom.ec_if; 4457 uint16_t rx_prod, rx_cons; 4458 int stdcnt = 0, jumbocnt = 0; 4459 bus_dmamap_t dmamap; 4460 bus_addr_t offset, toff; 4461 bus_size_t tlen; 4462 int tosync; 4463 4464 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4465 offsetof(struct bge_ring_data, bge_status_block), 4466 sizeof(struct bge_status_block), 4467 BUS_DMASYNC_POSTREAD); 4468 4469 rx_cons = sc->bge_rx_saved_considx; 4470 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4471 4472 /* Nothing to do */ 4473 if (rx_cons == rx_prod) 4474 return; 4475 4476 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4477 tosync = rx_prod - rx_cons; 4478 4479 if (tosync != 0) 4480 rnd_add_uint32(&sc->rnd_source, tosync); 4481 4482 toff = offset + (rx_cons * sizeof(struct bge_rx_bd)); 4483 4484 if (tosync < 0) { 4485 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4486 sizeof(struct bge_rx_bd); 4487 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4488 toff, tlen, BUS_DMASYNC_POSTREAD); 4489 tosync = rx_prod; 4490 toff = offset; 4491 } 4492 4493 if (tosync != 0) { 4494 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4495 toff, tosync * sizeof(struct bge_rx_bd), 4496 BUS_DMASYNC_POSTREAD); 4497 } 4498 4499 while (rx_cons != rx_prod) { 4500 struct bge_rx_bd *cur_rx; 4501 uint32_t rxidx; 4502 struct mbuf *m = NULL; 4503 4504 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4505 4506 rxidx = cur_rx->bge_idx; 4507 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4508 4509 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4510 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4511 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4512 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4513 jumbocnt++; 4514 bus_dmamap_sync(sc->bge_dmatag, 4515 sc->bge_cdata.bge_rx_jumbo_map, 4516 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4517 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4518 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4519 if_statinc(ifp, if_ierrors); 4520 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4521 continue; 4522 } 4523 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4524 NULL) == ENOBUFS) { 4525 if_statinc(ifp, if_ierrors); 4526 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4527 continue; 4528 } 4529 } else { 4530 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4531 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4532 4533 stdcnt++; 4534 sc->bge_std_cnt--; 4535 4536 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4537 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4538 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4539 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4540 4541 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4542 m_free(m); 4543 if_statinc(ifp, if_ierrors); 4544 continue; 4545 } 4546 } 4547 4548 #ifndef __NO_STRICT_ALIGNMENT 4549 /* 4550 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4551 * the Rx buffer has the layer-2 header unaligned. 4552 * If our CPU requires alignment, re-align by copying. 4553 */ 4554 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4555 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4556 cur_rx->bge_len); 4557 m->m_data += ETHER_ALIGN; 4558 } 4559 #endif 4560 4561 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4562 m_set_rcvif(m, ifp); 4563 4564 bge_rxcsum(sc, cur_rx, m); 4565 4566 /* 4567 * If we received a packet with a vlan tag, pass it 4568 * to vlan_input() instead of ether_input(). 4569 */ 4570 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4571 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4572 4573 if_percpuq_enqueue(ifp->if_percpuq, m); 4574 } 4575 4576 sc->bge_rx_saved_considx = rx_cons; 4577 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4578 if (stdcnt) 4579 bge_fill_rx_ring_std(sc); 4580 if (jumbocnt) 4581 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4582 } 4583 4584 static void 4585 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4586 { 4587 4588 if (BGE_IS_57765_PLUS(sc)) { 4589 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4590 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4591 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4592 if ((cur_rx->bge_error_flag & 4593 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4594 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4595 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4596 m->m_pkthdr.csum_data = 4597 cur_rx->bge_tcp_udp_csum; 4598 m->m_pkthdr.csum_flags |= 4599 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4600 } 4601 } 4602 } else { 4603 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4604 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4605 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4606 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4607 /* 4608 * Rx transport checksum-offload may also 4609 * have bugs with packets which, when transmitted, 4610 * were `runts' requiring padding. 4611 */ 4612 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4613 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4614 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4615 m->m_pkthdr.csum_data = 4616 cur_rx->bge_tcp_udp_csum; 4617 m->m_pkthdr.csum_flags |= 4618 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4619 } 4620 } 4621 } 4622 4623 static void 4624 bge_txeof(struct bge_softc *sc) 4625 { 4626 struct ifnet * const ifp = &sc->ethercom.ec_if; 4627 struct bge_tx_bd *cur_tx = NULL; 4628 struct txdmamap_pool_entry *dma; 4629 bus_addr_t offset, toff; 4630 bus_size_t tlen; 4631 int tosync; 4632 struct mbuf *m; 4633 4634 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4635 offsetof(struct bge_ring_data, bge_status_block), 4636 sizeof(struct bge_status_block), 4637 BUS_DMASYNC_POSTREAD); 4638 4639 const uint16_t hw_cons_idx = 4640 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx; 4641 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4642 tosync = hw_cons_idx - sc->bge_tx_saved_considx; 4643 4644 if (tosync != 0) 4645 rnd_add_uint32(&sc->rnd_source, tosync); 4646 4647 toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd)); 4648 4649 if (tosync < 0) { 4650 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4651 sizeof(struct bge_tx_bd); 4652 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4653 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4654 tosync = hw_cons_idx; 4655 toff = offset; 4656 } 4657 4658 if (tosync != 0) { 4659 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4660 toff, tosync * sizeof(struct bge_tx_bd), 4661 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4662 } 4663 4664 /* 4665 * Go through our tx ring and free mbufs for those 4666 * frames that have been sent. 4667 */ 4668 while (sc->bge_tx_saved_considx != hw_cons_idx) { 4669 uint32_t idx = sc->bge_tx_saved_considx; 4670 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4671 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4672 if_statinc(ifp, if_opackets); 4673 m = sc->bge_cdata.bge_tx_chain[idx]; 4674 if (m != NULL) { 4675 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4676 dma = sc->txdma[idx]; 4677 if (dma->is_dma32) { 4678 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4679 0, dma->dmamap32->dm_mapsize, 4680 BUS_DMASYNC_POSTWRITE); 4681 bus_dmamap_unload( 4682 sc->bge_dmatag32, dma->dmamap32); 4683 } else { 4684 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4685 0, dma->dmamap->dm_mapsize, 4686 BUS_DMASYNC_POSTWRITE); 4687 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4688 } 4689 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4690 sc->txdma[idx] = NULL; 4691 4692 m_freem(m); 4693 } 4694 sc->bge_txcnt--; 4695 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4696 sc->bge_tx_sending = false; 4697 } 4698 } 4699 4700 static int 4701 bge_intr(void *xsc) 4702 { 4703 struct bge_softc * const sc = xsc; 4704 struct ifnet * const ifp = &sc->ethercom.ec_if; 4705 uint32_t pcistate, statusword, statustag; 4706 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4707 4708 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4709 if (BGE_IS_5717_PLUS(sc)) 4710 intrmask = 0; 4711 4712 mutex_enter(sc->sc_intr_lock); 4713 if (sc->bge_txrx_stopping) { 4714 mutex_exit(sc->sc_intr_lock); 4715 return 1; 4716 } 4717 4718 /* 4719 * It is possible for the interrupt to arrive before 4720 * the status block is updated prior to the interrupt. 4721 * Reading the PCI State register will confirm whether the 4722 * interrupt is ours and will flush the status block. 4723 */ 4724 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4725 4726 /* read status word from status block */ 4727 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4728 offsetof(struct bge_ring_data, bge_status_block), 4729 sizeof(struct bge_status_block), 4730 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4731 statusword = sc->bge_rdata->bge_status_block.bge_status; 4732 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4733 4734 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4735 if (sc->bge_lasttag == statustag && 4736 (~pcistate & intrmask)) { 4737 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4738 mutex_exit(sc->sc_intr_lock); 4739 return 0; 4740 } 4741 sc->bge_lasttag = statustag; 4742 } else { 4743 if (!(statusword & BGE_STATFLAG_UPDATED) && 4744 !(~pcistate & intrmask)) { 4745 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4746 mutex_exit(sc->sc_intr_lock); 4747 return 0; 4748 } 4749 statustag = 0; 4750 } 4751 /* Ack interrupt and stop others from occurring. */ 4752 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4753 BGE_EVCNT_INCR(sc->bge_ev_intr); 4754 4755 /* clear status word */ 4756 sc->bge_rdata->bge_status_block.bge_status = 0; 4757 4758 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4759 offsetof(struct bge_ring_data, bge_status_block), 4760 sizeof(struct bge_status_block), 4761 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4762 4763 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4764 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4765 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4766 bge_link_upd(sc); 4767 4768 /* Check RX return ring producer/consumer */ 4769 bge_rxeof(sc); 4770 4771 /* Check TX ring producer/consumer */ 4772 bge_txeof(sc); 4773 4774 if (sc->bge_pending_rxintr_change) { 4775 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4776 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4777 4778 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4779 DELAY(10); 4780 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4781 4782 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4783 DELAY(10); 4784 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4785 4786 sc->bge_pending_rxintr_change = false; 4787 } 4788 bge_handle_events(sc); 4789 4790 /* Re-enable interrupts. */ 4791 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4792 4793 if_schedule_deferred_start(ifp); 4794 4795 mutex_exit(sc->sc_intr_lock); 4796 4797 return 1; 4798 } 4799 4800 static void 4801 bge_asf_driver_up(struct bge_softc *sc) 4802 { 4803 if (sc->bge_asf_mode & ASF_STACKUP) { 4804 /* Send ASF heartbeat approx. every 2s */ 4805 if (sc->bge_asf_count) 4806 sc->bge_asf_count --; 4807 else { 4808 sc->bge_asf_count = 2; 4809 4810 bge_wait_for_event_ack(sc); 4811 4812 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4813 BGE_FW_CMD_DRV_ALIVE3); 4814 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4815 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4816 BGE_FW_HB_TIMEOUT_SEC); 4817 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4818 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4819 BGE_RX_CPU_DRV_EVENT); 4820 } 4821 } 4822 } 4823 4824 static void 4825 bge_tick(void *xsc) 4826 { 4827 struct bge_softc * const sc = xsc; 4828 struct ifnet * const ifp = &sc->ethercom.ec_if; 4829 struct mii_data * const mii = &sc->bge_mii; 4830 4831 mutex_enter(sc->sc_core_lock); 4832 if (sc->bge_stopping) { 4833 mutex_exit(sc->sc_core_lock); 4834 return; 4835 } 4836 4837 if (BGE_IS_5705_PLUS(sc)) 4838 bge_stats_update_regs(sc); 4839 else 4840 bge_stats_update(sc); 4841 4842 if (sc->bge_flags & BGEF_FIBER_TBI) { 4843 /* 4844 * Since in TBI mode auto-polling can't be used we should poll 4845 * link status manually. Here we register pending link event 4846 * and trigger interrupt. 4847 */ 4848 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4849 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4850 } else { 4851 /* 4852 * Do not touch PHY if we have link up. This could break 4853 * IPMI/ASF mode or produce extra input errors. 4854 * (extra input errors was reported for bcm5701 & bcm5704). 4855 */ 4856 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4857 mutex_enter(sc->sc_intr_lock); 4858 mii_tick(mii); 4859 mutex_exit(sc->sc_intr_lock); 4860 } 4861 } 4862 4863 bge_asf_driver_up(sc); 4864 4865 const bool ok = bge_watchdog_tick(ifp); 4866 if (ok) 4867 callout_schedule(&sc->bge_timeout, hz); 4868 4869 mutex_exit(sc->sc_core_lock); 4870 } 4871 4872 static void 4873 bge_stats_update_regs(struct bge_softc *sc) 4874 { 4875 struct ifnet * const ifp = &sc->ethercom.ec_if; 4876 4877 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4878 4879 if_statadd_ref(ifp, nsr, if_collisions, 4880 CSR_READ_4(sc, BGE_MAC_STATS + 4881 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4882 4883 /* 4884 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4885 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4886 * (silicon bug). There's no reliable workaround so just 4887 * ignore the counter 4888 */ 4889 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4890 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4891 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4892 if_statadd_ref(ifp, nsr, if_ierrors, 4893 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4894 } 4895 if_statadd_ref(ifp, nsr, if_ierrors, 4896 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4897 if_statadd_ref(ifp, nsr, if_ierrors, 4898 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4899 4900 IF_STAT_PUTREF(ifp); 4901 4902 if (sc->bge_flags & BGEF_RDMA_BUG) { 4903 uint32_t val, ucast, mcast, bcast; 4904 4905 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4906 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4907 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4908 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4909 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4910 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4911 4912 /* 4913 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4914 * frames, it's safe to disable workaround for DMA engine's 4915 * miscalculation of TXMBUF space. 4916 */ 4917 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4918 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4919 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4920 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4921 else 4922 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4923 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4924 sc->bge_flags &= ~BGEF_RDMA_BUG; 4925 } 4926 } 4927 } 4928 4929 static void 4930 bge_stats_update(struct bge_softc *sc) 4931 { 4932 struct ifnet * const ifp = &sc->ethercom.ec_if; 4933 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4934 4935 #define READ_STAT(sc, stats, stat) \ 4936 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4937 4938 uint64_t collisions = 4939 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4940 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4941 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4942 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4943 4944 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4945 sc->bge_if_collisions = collisions; 4946 4947 4948 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4949 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4950 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4951 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4952 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4953 READ_STAT(sc, stats, 4954 xoffPauseFramesReceived.bge_addr_lo)); 4955 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4956 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4957 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4958 READ_STAT(sc, stats, 4959 macControlFramesReceived.bge_addr_lo)); 4960 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4961 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4962 4963 #undef READ_STAT 4964 } 4965 4966 /* 4967 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4968 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4969 * but when such padded frames employ the bge IP/TCP checksum offload, 4970 * the hardware checksum assist gives incorrect results (possibly 4971 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4972 * If we pad such runts with zeros, the onboard checksum comes out correct. 4973 */ 4974 static inline int 4975 bge_cksum_pad(struct mbuf *pkt) 4976 { 4977 struct mbuf *last = NULL; 4978 int padlen; 4979 4980 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 4981 4982 /* if there's only the packet-header and we can pad there, use it. */ 4983 if (pkt->m_pkthdr.len == pkt->m_len && 4984 M_TRAILINGSPACE(pkt) >= padlen) { 4985 last = pkt; 4986 } else { 4987 /* 4988 * Walk packet chain to find last mbuf. We will either 4989 * pad there, or append a new mbuf and pad it 4990 * (thus perhaps avoiding the bcm5700 dma-min bug). 4991 */ 4992 for (last = pkt; last->m_next != NULL; last = last->m_next) { 4993 continue; /* do nothing */ 4994 } 4995 4996 /* `last' now points to last in chain. */ 4997 if (M_TRAILINGSPACE(last) < padlen) { 4998 /* Allocate new empty mbuf, pad it. Compact later. */ 4999 struct mbuf *n; 5000 MGET(n, M_DONTWAIT, MT_DATA); 5001 if (n == NULL) 5002 return ENOBUFS; 5003 n->m_len = 0; 5004 last->m_next = n; 5005 last = n; 5006 } 5007 } 5008 5009 KDASSERT(!M_READONLY(last)); 5010 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 5011 5012 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 5013 memset(mtod(last, char *) + last->m_len, 0, padlen); 5014 last->m_len += padlen; 5015 pkt->m_pkthdr.len += padlen; 5016 return 0; 5017 } 5018 5019 /* 5020 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5021 */ 5022 static inline int 5023 bge_compact_dma_runt(struct mbuf *pkt) 5024 { 5025 struct mbuf *m, *prev; 5026 int totlen; 5027 5028 prev = NULL; 5029 totlen = 0; 5030 5031 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 5032 int mlen = m->m_len; 5033 int shortfall = 8 - mlen ; 5034 5035 totlen += mlen; 5036 if (mlen == 0) 5037 continue; 5038 if (mlen >= 8) 5039 continue; 5040 5041 /* 5042 * If we get here, mbuf data is too small for DMA engine. 5043 * Try to fix by shuffling data to prev or next in chain. 5044 * If that fails, do a compacting deep-copy of the whole chain. 5045 */ 5046 5047 /* Internal frag. If fits in prev, copy it there. */ 5048 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5049 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5050 prev->m_len += mlen; 5051 m->m_len = 0; 5052 /* XXX stitch chain */ 5053 prev->m_next = m_free(m); 5054 m = prev; 5055 continue; 5056 } else if (m->m_next != NULL && 5057 M_TRAILINGSPACE(m) >= shortfall && 5058 m->m_next->m_len >= (8 + shortfall)) { 5059 /* m is writable and have enough data in next, pull up. */ 5060 5061 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5062 shortfall); 5063 m->m_len += shortfall; 5064 m->m_next->m_len -= shortfall; 5065 m->m_next->m_data += shortfall; 5066 } else if (m->m_next == NULL || 1) { 5067 /* 5068 * Got a runt at the very end of the packet. 5069 * borrow data from the tail of the preceding mbuf and 5070 * update its length in-place. (The original data is 5071 * still valid, so we can do this even if prev is not 5072 * writable.) 5073 */ 5074 5075 /* 5076 * If we'd make prev a runt, just move all of its data. 5077 */ 5078 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5079 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5080 5081 if ((prev->m_len - shortfall) < 8) 5082 shortfall = prev->m_len; 5083 5084 #ifdef notyet /* just do the safe slow thing for now */ 5085 if (!M_READONLY(m)) { 5086 if (M_LEADINGSPACE(m) < shorfall) { 5087 void *m_dat; 5088 m_dat = M_BUFADDR(m); 5089 memmove(m_dat, mtod(m, void*), 5090 m->m_len); 5091 m->m_data = m_dat; 5092 } 5093 } else 5094 #endif /* just do the safe slow thing */ 5095 { 5096 struct mbuf * n = NULL; 5097 int newprevlen = prev->m_len - shortfall; 5098 5099 MGET(n, M_NOWAIT, MT_DATA); 5100 if (n == NULL) 5101 return ENOBUFS; 5102 KASSERT(m->m_len + shortfall < MLEN 5103 /*, 5104 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5105 5106 /* first copy the data we're stealing from prev */ 5107 memcpy(n->m_data, prev->m_data + newprevlen, 5108 shortfall); 5109 5110 /* update prev->m_len accordingly */ 5111 prev->m_len -= shortfall; 5112 5113 /* copy data from runt m */ 5114 memcpy(n->m_data + shortfall, m->m_data, 5115 m->m_len); 5116 5117 /* n holds what we stole from prev, plus m */ 5118 n->m_len = shortfall + m->m_len; 5119 5120 /* stitch n into chain and free m */ 5121 n->m_next = m->m_next; 5122 prev->m_next = n; 5123 /* KASSERT(m->m_next == NULL); */ 5124 m->m_next = NULL; 5125 m_free(m); 5126 m = n; /* for continuing loop */ 5127 } 5128 } 5129 } 5130 return 0; 5131 } 5132 5133 /* 5134 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5135 * pointers to descriptors. 5136 */ 5137 static int 5138 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5139 { 5140 struct bge_tx_bd *f, *prev_f; 5141 uint32_t frag, cur; 5142 uint16_t csum_flags = 0; 5143 uint16_t txbd_tso_flags = 0; 5144 struct txdmamap_pool_entry *dma; 5145 bus_dmamap_t dmamap; 5146 bus_dma_tag_t dmatag; 5147 int i = 0; 5148 int use_tso, maxsegsize, error; 5149 bool have_vtag; 5150 uint16_t vtag; 5151 bool remap; 5152 5153 if (m_head->m_pkthdr.csum_flags) { 5154 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5155 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5156 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5157 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5158 } 5159 5160 /* 5161 * If we were asked to do an outboard checksum, and the NIC 5162 * has the bug where it sometimes adds in the Ethernet padding, 5163 * explicitly pad with zeros so the cksum will be correct either way. 5164 * (For now, do this for all chip versions, until newer 5165 * are confirmed to not require the workaround.) 5166 */ 5167 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5168 #ifdef notyet 5169 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5170 #endif 5171 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5172 goto check_dma_bug; 5173 5174 if (bge_cksum_pad(m_head) != 0) 5175 return ENOBUFS; 5176 5177 check_dma_bug: 5178 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5179 goto doit; 5180 5181 /* 5182 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5183 * less than eight bytes. If we encounter a teeny mbuf 5184 * at the end of a chain, we can pad. Otherwise, copy. 5185 */ 5186 if (bge_compact_dma_runt(m_head) != 0) 5187 return ENOBUFS; 5188 5189 doit: 5190 dma = SLIST_FIRST(&sc->txdma_list); 5191 if (dma == NULL) { 5192 return ENOBUFS; 5193 } 5194 dmamap = dma->dmamap; 5195 dmatag = sc->bge_dmatag; 5196 dma->is_dma32 = false; 5197 5198 /* 5199 * Set up any necessary TSO state before we start packing... 5200 */ 5201 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5202 if (!use_tso) { 5203 maxsegsize = 0; 5204 } else { /* TSO setup */ 5205 unsigned mss; 5206 struct ether_header *eh; 5207 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5208 unsigned bge_hlen; 5209 struct mbuf * m0 = m_head; 5210 struct ip *ip; 5211 struct tcphdr *th; 5212 int iphl, hlen; 5213 5214 /* 5215 * XXX It would be nice if the mbuf pkthdr had offset 5216 * fields for the protocol headers. 5217 */ 5218 5219 eh = mtod(m0, struct ether_header *); 5220 switch (htons(eh->ether_type)) { 5221 case ETHERTYPE_IP: 5222 offset = ETHER_HDR_LEN; 5223 break; 5224 5225 case ETHERTYPE_VLAN: 5226 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5227 break; 5228 5229 default: 5230 /* 5231 * Don't support this protocol or encapsulation. 5232 */ 5233 return ENOBUFS; 5234 } 5235 5236 /* 5237 * TCP/IP headers are in the first mbuf; we can do 5238 * this the easy way. 5239 */ 5240 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5241 hlen = iphl + offset; 5242 if (__predict_false(m0->m_len < 5243 (hlen + sizeof(struct tcphdr)))) { 5244 5245 aprint_error_dev(sc->bge_dev, 5246 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5247 "not handled yet\n", 5248 m0->m_len, hlen+ sizeof(struct tcphdr)); 5249 #ifdef NOTYET 5250 /* 5251 * XXX jonathan (at) NetBSD.org: untested. 5252 * how to force this branch to be taken? 5253 */ 5254 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5255 5256 m_copydata(m0, offset, sizeof(ip), &ip); 5257 m_copydata(m0, hlen, sizeof(th), &th); 5258 5259 ip.ip_len = 0; 5260 5261 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5262 sizeof(ip.ip_len), &ip.ip_len); 5263 5264 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5265 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5266 5267 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5268 sizeof(th.th_sum), &th.th_sum); 5269 5270 hlen += th.th_off << 2; 5271 iptcp_opt_words = hlen; 5272 #else 5273 /* 5274 * if_wm "hard" case not yet supported, can we not 5275 * mandate it out of existence? 5276 */ 5277 (void) ip; (void)th; (void) ip_tcp_hlen; 5278 5279 return ENOBUFS; 5280 #endif 5281 } else { 5282 ip = (struct ip *) (mtod(m0, char *) + offset); 5283 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5284 ip_tcp_hlen = iphl + (th->th_off << 2); 5285 5286 /* Total IP/TCP options, in 32-bit words */ 5287 iptcp_opt_words = (ip_tcp_hlen 5288 - sizeof(struct tcphdr) 5289 - sizeof(struct ip)) >> 2; 5290 } 5291 if (BGE_IS_575X_PLUS(sc)) { 5292 th->th_sum = 0; 5293 csum_flags = 0; 5294 } else { 5295 /* 5296 * XXX jonathan (at) NetBSD.org: 5705 untested. 5297 * Requires TSO firmware patch for 5701/5703/5704. 5298 */ 5299 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5300 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5301 } 5302 5303 mss = m_head->m_pkthdr.segsz; 5304 txbd_tso_flags |= 5305 BGE_TXBDFLAG_CPU_PRE_DMA | 5306 BGE_TXBDFLAG_CPU_POST_DMA; 5307 5308 /* 5309 * Our NIC TSO-assist assumes TSO has standard, optionless 5310 * IPv4 and TCP headers, which total 40 bytes. By default, 5311 * the NIC copies 40 bytes of IP/TCP header from the 5312 * supplied header into the IP/TCP header portion of 5313 * each post-TSO-segment. If the supplied packet has IP or 5314 * TCP options, we need to tell the NIC to copy those extra 5315 * bytes into each post-TSO header, in addition to the normal 5316 * 40-byte IP/TCP header (and to leave space accordingly). 5317 * Unfortunately, the driver encoding of option length 5318 * varies across different ASIC families. 5319 */ 5320 tcp_seg_flags = 0; 5321 bge_hlen = ip_tcp_hlen >> 2; 5322 if (BGE_IS_5717_PLUS(sc)) { 5323 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5324 txbd_tso_flags |= 5325 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5326 } else if (BGE_IS_5705_PLUS(sc)) { 5327 tcp_seg_flags = bge_hlen << 11; 5328 } else { 5329 /* XXX iptcp_opt_words or bge_hlen ? */ 5330 txbd_tso_flags |= iptcp_opt_words << 12; 5331 } 5332 maxsegsize = mss | tcp_seg_flags; 5333 ip->ip_len = htons(mss + ip_tcp_hlen); 5334 ip->ip_sum = 0; 5335 5336 } /* TSO setup */ 5337 5338 have_vtag = vlan_has_tag(m_head); 5339 if (have_vtag) 5340 vtag = vlan_get_tag(m_head); 5341 5342 /* 5343 * Start packing the mbufs in this chain into 5344 * the fragment pointers. Stop when we run out 5345 * of fragments or hit the end of the mbuf chain. 5346 */ 5347 remap = true; 5348 load_again: 5349 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5350 if (__predict_false(error)) { 5351 if (error == EFBIG && remap) { 5352 struct mbuf *m; 5353 remap = false; 5354 m = m_defrag(m_head, M_NOWAIT); 5355 if (m != NULL) { 5356 KASSERT(m == m_head); 5357 goto load_again; 5358 } 5359 } 5360 return error; 5361 } 5362 /* 5363 * Sanity check: avoid coming within 16 descriptors 5364 * of the end of the ring. 5365 */ 5366 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5367 BGE_TSO_PRINTF(("%s: " 5368 " dmamap_load_mbuf too close to ring wrap\n", 5369 device_xname(sc->bge_dev))); 5370 goto fail_unload; 5371 } 5372 5373 /* Iterate over dmap-map fragments. */ 5374 f = prev_f = NULL; 5375 cur = frag = *txidx; 5376 5377 for (i = 0; i < dmamap->dm_nsegs; i++) { 5378 f = &sc->bge_rdata->bge_tx_ring[frag]; 5379 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5380 break; 5381 5382 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5383 f->bge_len = dmamap->dm_segs[i].ds_len; 5384 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5385 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5386 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5387 (prev_f != NULL && 5388 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5389 ) { 5390 /* 5391 * watchdog timeout issue was observed with TSO, 5392 * limiting DMA address space to 32bits seems to 5393 * address the issue. 5394 */ 5395 bus_dmamap_unload(dmatag, dmamap); 5396 dmatag = sc->bge_dmatag32; 5397 dmamap = dma->dmamap32; 5398 dma->is_dma32 = true; 5399 remap = true; 5400 goto load_again; 5401 } 5402 5403 /* 5404 * For 5751 and follow-ons, for TSO we must turn 5405 * off checksum-assist flag in the tx-descr, and 5406 * supply the ASIC-revision-specific encoding 5407 * of TSO flags and segsize. 5408 */ 5409 if (use_tso) { 5410 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5411 f->bge_rsvd = maxsegsize; 5412 f->bge_flags = csum_flags | txbd_tso_flags; 5413 } else { 5414 f->bge_rsvd = 0; 5415 f->bge_flags = 5416 (csum_flags | txbd_tso_flags) & 0x0fff; 5417 } 5418 } else { 5419 f->bge_rsvd = 0; 5420 f->bge_flags = csum_flags; 5421 } 5422 5423 if (have_vtag) { 5424 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5425 f->bge_vlan_tag = vtag; 5426 } else { 5427 f->bge_vlan_tag = 0; 5428 } 5429 prev_f = f; 5430 cur = frag; 5431 BGE_INC(frag, BGE_TX_RING_CNT); 5432 } 5433 5434 if (i < dmamap->dm_nsegs) { 5435 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5436 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5437 goto fail_unload; 5438 } 5439 5440 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5441 BUS_DMASYNC_PREWRITE); 5442 5443 if (frag == sc->bge_tx_saved_considx) { 5444 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5445 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5446 5447 goto fail_unload; 5448 } 5449 5450 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5451 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5452 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5453 sc->txdma[cur] = dma; 5454 sc->bge_txcnt += dmamap->dm_nsegs; 5455 5456 *txidx = frag; 5457 5458 return 0; 5459 5460 fail_unload: 5461 bus_dmamap_unload(dmatag, dmamap); 5462 5463 return ENOBUFS; 5464 } 5465 5466 5467 static void 5468 bge_start(struct ifnet *ifp) 5469 { 5470 struct bge_softc * const sc = ifp->if_softc; 5471 5472 mutex_enter(sc->sc_intr_lock); 5473 if (!sc->bge_txrx_stopping) 5474 bge_start_locked(ifp); 5475 mutex_exit(sc->sc_intr_lock); 5476 } 5477 5478 /* 5479 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5480 * to the mbuf data regions directly in the transmit descriptors. 5481 */ 5482 static void 5483 bge_start_locked(struct ifnet *ifp) 5484 { 5485 struct bge_softc * const sc = ifp->if_softc; 5486 struct mbuf *m_head = NULL; 5487 struct mbuf *m; 5488 uint32_t prodidx; 5489 int pkts = 0; 5490 int error; 5491 5492 KASSERT(mutex_owned(sc->sc_intr_lock)); 5493 5494 prodidx = sc->bge_tx_prodidx; 5495 5496 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5497 IFQ_POLL(&ifp->if_snd, m_head); 5498 if (m_head == NULL) 5499 break; 5500 5501 #if 0 5502 /* 5503 * XXX 5504 * safety overkill. If this is a fragmented packet chain 5505 * with delayed TCP/UDP checksums, then only encapsulate 5506 * it if we have enough descriptors to handle the entire 5507 * chain at once. 5508 * (paranoia -- may not actually be needed) 5509 */ 5510 if (m_head->m_flags & M_FIRSTFRAG && 5511 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5512 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5513 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5514 ifp->if_flags |= IFF_OACTIVE; 5515 break; 5516 } 5517 } 5518 #endif 5519 5520 /* 5521 * Pack the data into the transmit ring. If we 5522 * don't have room, set the OACTIVE flag and wait 5523 * for the NIC to drain the ring. 5524 */ 5525 error = bge_encap(sc, m_head, &prodidx); 5526 if (__predict_false(error)) { 5527 if (SLIST_EMPTY(&sc->txdma_list)) { 5528 /* just wait for the transmit ring to drain */ 5529 break; 5530 } 5531 IFQ_DEQUEUE(&ifp->if_snd, m); 5532 KASSERT(m == m_head); 5533 m_freem(m_head); 5534 continue; 5535 } 5536 5537 /* now we are committed to transmit the packet */ 5538 IFQ_DEQUEUE(&ifp->if_snd, m); 5539 KASSERT(m == m_head); 5540 pkts++; 5541 5542 /* 5543 * If there's a BPF listener, bounce a copy of this frame 5544 * to him. 5545 */ 5546 bpf_mtap(ifp, m_head, BPF_D_OUT); 5547 } 5548 if (pkts == 0) 5549 return; 5550 5551 /* Transmit */ 5552 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5553 /* 5700 b2 errata */ 5554 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5555 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5556 5557 sc->bge_tx_prodidx = prodidx; 5558 sc->bge_tx_lastsent = time_uptime; 5559 sc->bge_tx_sending = true; 5560 } 5561 5562 static int 5563 bge_init(struct ifnet *ifp) 5564 { 5565 struct bge_softc * const sc = ifp->if_softc; 5566 5567 KASSERT(IFNET_LOCKED(ifp)); 5568 5569 if (sc->bge_detaching) 5570 return ENXIO; 5571 5572 mutex_enter(sc->sc_core_lock); 5573 int ret = bge_init_locked(ifp); 5574 mutex_exit(sc->sc_core_lock); 5575 5576 return ret; 5577 } 5578 5579 5580 static int 5581 bge_init_locked(struct ifnet *ifp) 5582 { 5583 struct bge_softc * const sc = ifp->if_softc; 5584 const uint16_t *m; 5585 uint32_t mode, reg; 5586 int error = 0; 5587 5588 ASSERT_SLEEPABLE(); 5589 KASSERT(IFNET_LOCKED(ifp)); 5590 KASSERT(mutex_owned(sc->sc_core_lock)); 5591 KASSERT(ifp == &sc->ethercom.ec_if); 5592 5593 /* Cancel pending I/O and flush buffers. */ 5594 bge_stop_locked(ifp, false); 5595 5596 bge_stop_fw(sc); 5597 bge_sig_pre_reset(sc, BGE_RESET_START); 5598 bge_reset(sc); 5599 bge_sig_legacy(sc, BGE_RESET_START); 5600 5601 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5602 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5603 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5604 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5605 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5606 5607 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5608 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5609 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5610 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5611 5612 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5613 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5614 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5615 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5616 5617 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5618 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5619 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5620 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5621 } 5622 5623 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5624 pcireg_t aercap; 5625 5626 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5627 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5628 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5629 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5630 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5631 5632 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5633 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5634 | BGE_PCIE_EIDLE_DELAY_13CLK; 5635 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5636 5637 /* Clear correctable error */ 5638 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5639 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5640 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5641 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5642 5643 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5644 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5645 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5646 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5647 } 5648 5649 bge_sig_post_reset(sc, BGE_RESET_START); 5650 5651 bge_chipinit(sc); 5652 5653 /* 5654 * Init the various state machines, ring 5655 * control blocks and firmware. 5656 */ 5657 error = bge_blockinit(sc); 5658 if (error != 0) { 5659 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5660 error); 5661 return error; 5662 } 5663 5664 /* 5718 step 25, 57XX step 54 */ 5665 /* Specify MTU. */ 5666 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5667 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5668 5669 /* 5718 step 23 */ 5670 /* Load our MAC address. */ 5671 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5672 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5673 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5674 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5675 5676 /* Enable or disable promiscuous mode as needed. */ 5677 if (ifp->if_flags & IFF_PROMISC) 5678 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5679 else 5680 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5681 5682 /* Program multicast filter. */ 5683 bge_setmulti(sc); 5684 5685 /* Init RX ring. */ 5686 bge_init_rx_ring_std(sc); 5687 5688 /* 5689 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5690 * memory to insure that the chip has in fact read the first 5691 * entry of the ring. 5692 */ 5693 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5694 u_int i; 5695 for (i = 0; i < 10; i++) { 5696 DELAY(20); 5697 uint32_t v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5698 if (v == (MCLBYTES - ETHER_ALIGN)) 5699 break; 5700 } 5701 if (i == 10) 5702 aprint_error_dev(sc->bge_dev, 5703 "5705 A0 chip failed to load RX ring\n"); 5704 } 5705 5706 /* Init jumbo RX ring. */ 5707 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5708 bge_init_rx_ring_jumbo(sc); 5709 5710 /* Init our RX return ring index */ 5711 sc->bge_rx_saved_considx = 0; 5712 5713 /* Init TX ring. */ 5714 bge_init_tx_ring(sc); 5715 5716 /* 5718 step 63, 57XX step 94 */ 5717 /* Enable TX MAC state machine lockup fix. */ 5718 mode = CSR_READ_4(sc, BGE_TX_MODE); 5719 if (BGE_IS_5755_PLUS(sc) || 5720 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5721 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5722 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5723 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5724 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5725 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5726 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5727 } 5728 5729 /* Turn on transmitter */ 5730 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5731 /* 5718 step 64 */ 5732 DELAY(100); 5733 5734 /* 5718 step 65, 57XX step 95 */ 5735 /* Turn on receiver */ 5736 mode = CSR_READ_4(sc, BGE_RX_MODE); 5737 if (BGE_IS_5755_PLUS(sc)) 5738 mode |= BGE_RXMODE_IPV6_ENABLE; 5739 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5740 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5741 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5742 /* 5718 step 66 */ 5743 DELAY(10); 5744 5745 /* 5718 step 12, 57XX step 37 */ 5746 /* 5747 * XXX Documents of 5718 series and 577xx say the recommended value 5748 * is 1, but tg3 set 1 only on 57765 series. 5749 */ 5750 if (BGE_IS_57765_PLUS(sc)) 5751 reg = 1; 5752 else 5753 reg = 2; 5754 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5755 5756 /* Tell firmware we're alive. */ 5757 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5758 5759 /* Enable host interrupts. */ 5760 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5761 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5762 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5763 5764 mutex_enter(sc->sc_intr_lock); 5765 if ((error = bge_ifmedia_upd(ifp)) == 0) { 5766 sc->bge_stopping = false; 5767 sc->bge_txrx_stopping = false; 5768 5769 /* IFNET_LOCKED asserted above */ 5770 ifp->if_flags |= IFF_RUNNING; 5771 5772 callout_schedule(&sc->bge_timeout, hz); 5773 } 5774 mutex_exit(sc->sc_intr_lock); 5775 5776 sc->bge_if_flags = ifp->if_flags; 5777 5778 return error; 5779 } 5780 5781 /* 5782 * Set media options. 5783 */ 5784 static int 5785 bge_ifmedia_upd(struct ifnet *ifp) 5786 { 5787 struct bge_softc * const sc = ifp->if_softc; 5788 struct mii_data * const mii = &sc->bge_mii; 5789 struct ifmedia * const ifm = &sc->bge_ifmedia; 5790 int rc; 5791 5792 KASSERT(mutex_owned(sc->sc_intr_lock)); 5793 5794 /* If this is a 1000baseX NIC, enable the TBI port. */ 5795 if (sc->bge_flags & BGEF_FIBER_TBI) { 5796 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5797 return EINVAL; 5798 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5799 case IFM_AUTO: 5800 /* 5801 * The BCM5704 ASIC appears to have a special 5802 * mechanism for programming the autoneg 5803 * advertisement registers in TBI mode. 5804 */ 5805 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5806 uint32_t sgdig; 5807 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5808 if (sgdig & BGE_SGDIGSTS_DONE) { 5809 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5810 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5811 sgdig |= BGE_SGDIGCFG_AUTO | 5812 BGE_SGDIGCFG_PAUSE_CAP | 5813 BGE_SGDIGCFG_ASYM_PAUSE; 5814 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5815 sgdig | BGE_SGDIGCFG_SEND); 5816 DELAY(5); 5817 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5818 sgdig); 5819 } 5820 } 5821 break; 5822 case IFM_1000_SX: 5823 if ((ifm->ifm_media & IFM_FDX) != 0) { 5824 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5825 BGE_MACMODE_HALF_DUPLEX); 5826 } else { 5827 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5828 BGE_MACMODE_HALF_DUPLEX); 5829 } 5830 DELAY(40); 5831 break; 5832 default: 5833 return EINVAL; 5834 } 5835 /* XXX 802.3x flow control for 1000BASE-SX */ 5836 return 0; 5837 } 5838 5839 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5840 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5841 uint32_t reg; 5842 5843 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5844 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5845 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5846 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5847 } 5848 } 5849 5850 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5851 if ((rc = mii_mediachg(mii)) == ENXIO) 5852 return 0; 5853 5854 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5855 uint32_t reg; 5856 5857 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5858 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5859 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5860 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5861 delay(40); 5862 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5863 } 5864 } 5865 5866 /* 5867 * Force an interrupt so that we will call bge_link_upd 5868 * if needed and clear any pending link state attention. 5869 * Without this we are not getting any further interrupts 5870 * for link state changes and thus will not UP the link and 5871 * not be able to send in bge_start. The only way to get 5872 * things working was to receive a packet and get a RX intr. 5873 */ 5874 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5875 sc->bge_flags & BGEF_IS_5788) 5876 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5877 else 5878 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5879 5880 return rc; 5881 } 5882 5883 /* 5884 * Report current media status. 5885 */ 5886 static void 5887 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5888 { 5889 struct bge_softc * const sc = ifp->if_softc; 5890 struct mii_data * const mii = &sc->bge_mii; 5891 5892 KASSERT(mutex_owned(sc->sc_intr_lock)); 5893 5894 if (sc->bge_flags & BGEF_FIBER_TBI) { 5895 ifmr->ifm_status = IFM_AVALID; 5896 ifmr->ifm_active = IFM_ETHER; 5897 if (CSR_READ_4(sc, BGE_MAC_STS) & 5898 BGE_MACSTAT_TBI_PCS_SYNCHED) 5899 ifmr->ifm_status |= IFM_ACTIVE; 5900 ifmr->ifm_active |= IFM_1000_SX; 5901 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5902 ifmr->ifm_active |= IFM_HDX; 5903 else 5904 ifmr->ifm_active |= IFM_FDX; 5905 return; 5906 } 5907 5908 mii_pollstat(mii); 5909 ifmr->ifm_status = mii->mii_media_status; 5910 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5911 sc->bge_flowflags; 5912 } 5913 5914 static int 5915 bge_ifflags_cb(struct ethercom *ec) 5916 { 5917 struct ifnet * const ifp = &ec->ec_if; 5918 struct bge_softc * const sc = ifp->if_softc; 5919 int ret = 0; 5920 5921 KASSERT(IFNET_LOCKED(ifp)); 5922 mutex_enter(sc->sc_core_lock); 5923 5924 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5925 5926 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 5927 ret = ENETRESET; 5928 } else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 5929 if ((ifp->if_flags & IFF_PROMISC) == 0) 5930 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5931 else 5932 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5933 5934 bge_setmulti(sc); 5935 } 5936 5937 sc->bge_if_flags = ifp->if_flags; 5938 mutex_exit(sc->sc_core_lock); 5939 5940 return ret; 5941 } 5942 5943 static int 5944 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5945 { 5946 struct bge_softc * const sc = ifp->if_softc; 5947 struct ifreq * const ifr = (struct ifreq *) data; 5948 int error = 0; 5949 5950 switch (command) { 5951 case SIOCADDMULTI: 5952 case SIOCDELMULTI: 5953 break; 5954 default: 5955 KASSERT(IFNET_LOCKED(ifp)); 5956 } 5957 5958 const int s = splnet(); 5959 5960 switch (command) { 5961 case SIOCSIFMEDIA: 5962 mutex_enter(sc->sc_core_lock); 5963 /* XXX Flow control is not supported for 1000BASE-SX */ 5964 if (sc->bge_flags & BGEF_FIBER_TBI) { 5965 ifr->ifr_media &= ~IFM_ETH_FMASK; 5966 sc->bge_flowflags = 0; 5967 } 5968 5969 /* Flow control requires full-duplex mode. */ 5970 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5971 (ifr->ifr_media & IFM_FDX) == 0) { 5972 ifr->ifr_media &= ~IFM_ETH_FMASK; 5973 } 5974 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5975 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5976 /* We can do both TXPAUSE and RXPAUSE. */ 5977 ifr->ifr_media |= 5978 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5979 } 5980 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5981 } 5982 mutex_exit(sc->sc_core_lock); 5983 5984 if (sc->bge_flags & BGEF_FIBER_TBI) { 5985 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5986 command); 5987 } else { 5988 struct mii_data * const mii = &sc->bge_mii; 5989 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 5990 command); 5991 } 5992 break; 5993 default: 5994 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 5995 break; 5996 5997 error = 0; 5998 5999 if (command == SIOCADDMULTI || command == SIOCDELMULTI) { 6000 mutex_enter(sc->sc_core_lock); 6001 if (sc->bge_if_flags & IFF_RUNNING) { 6002 bge_setmulti(sc); 6003 } 6004 mutex_exit(sc->sc_core_lock); 6005 } 6006 break; 6007 } 6008 6009 splx(s); 6010 6011 return error; 6012 } 6013 6014 static bool 6015 bge_watchdog_check(struct bge_softc * const sc) 6016 { 6017 6018 KASSERT(mutex_owned(sc->sc_core_lock)); 6019 6020 if (!sc->bge_tx_sending) 6021 return true; 6022 6023 if (time_uptime - sc->bge_tx_lastsent <= bge_watchdog_timeout) 6024 return true; 6025 6026 /* If pause frames are active then don't reset the hardware. */ 6027 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 6028 const uint32_t status = CSR_READ_4(sc, BGE_RX_STS); 6029 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 6030 /* 6031 * If link partner has us in XOFF state then wait for 6032 * the condition to clear. 6033 */ 6034 CSR_WRITE_4(sc, BGE_RX_STS, status); 6035 sc->bge_tx_lastsent = time_uptime; 6036 return true; 6037 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 6038 (status & BGE_RXSTAT_RCVD_XON) != 0) { 6039 /* 6040 * If link partner has us in XOFF state then wait for 6041 * the condition to clear. 6042 */ 6043 CSR_WRITE_4(sc, BGE_RX_STS, status); 6044 sc->bge_tx_lastsent = time_uptime; 6045 return true; 6046 } 6047 /* 6048 * Any other condition is unexpected and the controller 6049 * should be reset. 6050 */ 6051 } 6052 6053 return false; 6054 } 6055 6056 static bool 6057 bge_watchdog_tick(struct ifnet *ifp) 6058 { 6059 struct bge_softc * const sc = ifp->if_softc; 6060 6061 KASSERT(mutex_owned(sc->sc_core_lock)); 6062 6063 if (!sc->sc_trigger_reset && bge_watchdog_check(sc)) 6064 return true; 6065 6066 if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0) 6067 workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL); 6068 6069 return false; 6070 } 6071 6072 /* 6073 * Perform an interface watchdog reset. 6074 */ 6075 static void 6076 bge_handle_reset_work(struct work *work, void *arg) 6077 { 6078 struct bge_softc * const sc = arg; 6079 struct ifnet * const ifp = &sc->ethercom.ec_if; 6080 6081 printf("%s: watchdog timeout -- resetting\n", ifp->if_xname); 6082 6083 /* Don't want ioctl operations to happen */ 6084 IFNET_LOCK(ifp); 6085 6086 /* reset the interface. */ 6087 bge_init(ifp); 6088 6089 IFNET_UNLOCK(ifp); 6090 6091 /* 6092 * There are still some upper layer processing which call 6093 * ifp->if_start(). e.g. ALTQ or one CPU system 6094 */ 6095 /* Try to get more packets going. */ 6096 ifp->if_start(ifp); 6097 6098 atomic_store_relaxed(&sc->sc_reset_pending, 0); 6099 } 6100 6101 static void 6102 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 6103 { 6104 int i; 6105 6106 BGE_CLRBIT_FLUSH(sc, reg, bit); 6107 6108 for (i = 0; i < 1000; i++) { 6109 delay(100); 6110 if ((CSR_READ_4(sc, reg) & bit) == 0) 6111 return; 6112 } 6113 6114 /* 6115 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 6116 * on some environment (and once after boot?) 6117 */ 6118 if (reg != BGE_SRS_MODE) 6119 aprint_error_dev(sc->bge_dev, 6120 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 6121 (u_long)reg, bit); 6122 } 6123 6124 6125 static void 6126 bge_stop(struct ifnet *ifp, int disable) 6127 { 6128 struct bge_softc * const sc = ifp->if_softc; 6129 6130 ASSERT_SLEEPABLE(); 6131 KASSERT(IFNET_LOCKED(ifp)); 6132 6133 mutex_enter(sc->sc_core_lock); 6134 bge_stop_locked(ifp, disable ? true : false); 6135 mutex_exit(sc->sc_core_lock); 6136 } 6137 6138 /* 6139 * Stop the adapter and free any mbufs allocated to the 6140 * RX and TX lists. 6141 */ 6142 static void 6143 bge_stop_locked(struct ifnet *ifp, bool disable) 6144 { 6145 struct bge_softc * const sc = ifp->if_softc; 6146 6147 ASSERT_SLEEPABLE(); 6148 KASSERT(IFNET_LOCKED(ifp)); 6149 KASSERT(mutex_owned(sc->sc_core_lock)); 6150 6151 sc->bge_stopping = true; 6152 6153 mutex_enter(sc->sc_intr_lock); 6154 sc->bge_txrx_stopping = true; 6155 mutex_exit(sc->sc_intr_lock); 6156 6157 callout_halt(&sc->bge_timeout, sc->sc_core_lock); 6158 6159 /* Disable host interrupts. */ 6160 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6161 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6162 6163 /* 6164 * Tell firmware we're shutting down. 6165 */ 6166 bge_stop_fw(sc); 6167 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6168 6169 /* 6170 * Disable all of the receiver blocks. 6171 */ 6172 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6173 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6174 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6175 if (BGE_IS_5700_FAMILY(sc)) 6176 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6177 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6178 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6179 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6180 6181 /* 6182 * Disable all of the transmit blocks. 6183 */ 6184 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6185 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6186 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6187 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6188 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6189 if (BGE_IS_5700_FAMILY(sc)) 6190 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6191 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6192 6193 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6194 delay(40); 6195 6196 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6197 6198 /* 6199 * Shut down all of the memory managers and related 6200 * state machines. 6201 */ 6202 /* 5718 step 5a,5b */ 6203 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6204 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6205 if (BGE_IS_5700_FAMILY(sc)) 6206 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6207 6208 /* 5718 step 5c,5d */ 6209 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6210 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6211 6212 if (BGE_IS_5700_FAMILY(sc)) { 6213 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6214 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6215 } 6216 6217 bge_reset(sc); 6218 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6219 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6220 6221 /* 6222 * Keep the ASF firmware running if up. 6223 */ 6224 if (sc->bge_asf_mode & ASF_STACKUP) 6225 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6226 else 6227 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6228 6229 /* Free the RX lists. */ 6230 bge_free_rx_ring_std(sc); 6231 6232 /* Free jumbo RX list. */ 6233 if (BGE_IS_JUMBO_CAPABLE(sc)) 6234 bge_free_rx_ring_jumbo(sc); 6235 6236 /* Free TX buffers. */ 6237 bge_free_tx_ring(sc, disable); 6238 6239 /* 6240 * Isolate/power down the PHY. 6241 */ 6242 if (!(sc->bge_flags & BGEF_FIBER_TBI)) { 6243 mutex_enter(sc->sc_intr_lock); 6244 mii_down(&sc->bge_mii); 6245 mutex_exit(sc->sc_intr_lock); 6246 } 6247 6248 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6249 6250 /* Clear MAC's link state (PHY may still have link UP). */ 6251 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6252 6253 ifp->if_flags &= ~IFF_RUNNING; 6254 6255 sc->bge_if_flags = ifp->if_flags; 6256 } 6257 6258 static void 6259 bge_link_upd(struct bge_softc *sc) 6260 { 6261 struct ifnet * const ifp = &sc->ethercom.ec_if; 6262 struct mii_data * const mii = &sc->bge_mii; 6263 uint32_t status; 6264 uint16_t phyval; 6265 int link; 6266 6267 KASSERT(sc->sc_intr_lock); 6268 6269 /* Clear 'pending link event' flag */ 6270 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6271 6272 /* 6273 * Process link state changes. 6274 * Grrr. The link status word in the status block does 6275 * not work correctly on the BCM5700 rev AX and BX chips, 6276 * according to all available information. Hence, we have 6277 * to enable MII interrupts in order to properly obtain 6278 * async link changes. Unfortunately, this also means that 6279 * we have to read the MAC status register to detect link 6280 * changes, thereby adding an additional register access to 6281 * the interrupt handler. 6282 */ 6283 6284 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6285 status = CSR_READ_4(sc, BGE_MAC_STS); 6286 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6287 mii_pollstat(mii); 6288 6289 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6290 mii->mii_media_status & IFM_ACTIVE && 6291 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6292 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6293 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6294 (!(mii->mii_media_status & IFM_ACTIVE) || 6295 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6296 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6297 6298 /* Clear the interrupt */ 6299 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6300 BGE_EVTENB_MI_INTERRUPT); 6301 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6302 BRGPHY_MII_ISR, &phyval); 6303 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6304 BRGPHY_MII_IMR, BRGPHY_INTRS); 6305 } 6306 return; 6307 } 6308 6309 if (sc->bge_flags & BGEF_FIBER_TBI) { 6310 status = CSR_READ_4(sc, BGE_MAC_STS); 6311 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6312 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6313 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6314 if (BGE_ASICREV(sc->bge_chipid) 6315 == BGE_ASICREV_BCM5704) { 6316 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6317 BGE_MACMODE_TBI_SEND_CFGS); 6318 DELAY(40); 6319 } 6320 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6321 if_link_state_change(ifp, LINK_STATE_UP); 6322 } 6323 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6324 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6325 if_link_state_change(ifp, LINK_STATE_DOWN); 6326 } 6327 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6328 /* 6329 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6330 * bit in status word always set. Workaround this bug by 6331 * reading PHY link status directly. 6332 */ 6333 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6334 BGE_STS_LINK : 0; 6335 6336 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6337 mii_pollstat(mii); 6338 6339 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6340 mii->mii_media_status & IFM_ACTIVE && 6341 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6342 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6343 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6344 (!(mii->mii_media_status & IFM_ACTIVE) || 6345 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6346 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6347 } 6348 } else { 6349 /* 6350 * For controllers that call mii_tick, we have to poll 6351 * link status. 6352 */ 6353 mii_pollstat(mii); 6354 } 6355 6356 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6357 uint32_t reg, scale; 6358 6359 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6360 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6361 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6362 scale = 65; 6363 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6364 scale = 6; 6365 else 6366 scale = 12; 6367 6368 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6369 ~BGE_MISCCFG_TIMER_PRESCALER; 6370 reg |= scale << 1; 6371 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6372 } 6373 /* Clear the attention */ 6374 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6375 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6376 BGE_MACSTAT_LINK_CHANGED); 6377 } 6378 6379 static int 6380 bge_sysctl_verify(SYSCTLFN_ARGS) 6381 { 6382 int error, t; 6383 struct sysctlnode node; 6384 6385 node = *rnode; 6386 t = *(int*)rnode->sysctl_data; 6387 node.sysctl_data = &t; 6388 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6389 if (error || newp == NULL) 6390 return error; 6391 6392 #if 0 6393 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6394 node.sysctl_num, rnode->sysctl_num)); 6395 #endif 6396 6397 if (node.sysctl_num == bge_rxthresh_nodenum) { 6398 if (t < 0 || t >= NBGE_RX_THRESH) 6399 return EINVAL; 6400 bge_update_all_threshes(t); 6401 } else 6402 return EINVAL; 6403 6404 *(int*)rnode->sysctl_data = t; 6405 6406 return 0; 6407 } 6408 6409 /* 6410 * Set up sysctl(3) MIB, hw.bge.*. 6411 */ 6412 static void 6413 bge_sysctl_init(struct bge_softc *sc) 6414 { 6415 int rc, bge_root_num; 6416 const struct sysctlnode *node; 6417 6418 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6419 0, CTLTYPE_NODE, "bge", 6420 SYSCTL_DESCR("BGE interface controls"), 6421 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6422 goto out; 6423 } 6424 6425 bge_root_num = node->sysctl_num; 6426 6427 /* BGE Rx interrupt mitigation level */ 6428 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6429 CTLFLAG_READWRITE, 6430 CTLTYPE_INT, "rx_lvl", 6431 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6432 bge_sysctl_verify, 0, 6433 &bge_rx_thresh_lvl, 6434 0, CTL_HW, bge_root_num, CTL_CREATE, 6435 CTL_EOL)) != 0) { 6436 goto out; 6437 } 6438 6439 bge_rxthresh_nodenum = node->sysctl_num; 6440 6441 #ifdef BGE_DEBUG 6442 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6443 CTLFLAG_READWRITE, 6444 CTLTYPE_BOOL, "trigger_reset", 6445 SYSCTL_DESCR("Trigger an interface reset"), 6446 NULL, 0, &sc->sc_trigger_reset, 0, CTL_CREATE, 6447 CTL_EOL)) != 0) { 6448 goto out; 6449 } 6450 #endif 6451 return; 6452 6453 out: 6454 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6455 } 6456 6457 #ifdef BGE_DEBUG 6458 void 6459 bge_debug_info(struct bge_softc *sc) 6460 { 6461 6462 printf("Hardware Flags:\n"); 6463 if (BGE_IS_57765_PLUS(sc)) 6464 printf(" - 57765 Plus\n"); 6465 if (BGE_IS_5717_PLUS(sc)) 6466 printf(" - 5717 Plus\n"); 6467 if (BGE_IS_5755_PLUS(sc)) 6468 printf(" - 5755 Plus\n"); 6469 if (BGE_IS_575X_PLUS(sc)) 6470 printf(" - 575X Plus\n"); 6471 if (BGE_IS_5705_PLUS(sc)) 6472 printf(" - 5705 Plus\n"); 6473 if (BGE_IS_5714_FAMILY(sc)) 6474 printf(" - 5714 Family\n"); 6475 if (BGE_IS_5700_FAMILY(sc)) 6476 printf(" - 5700 Family\n"); 6477 if (sc->bge_flags & BGEF_IS_5788) 6478 printf(" - 5788\n"); 6479 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6480 printf(" - Supports Jumbo Frames\n"); 6481 if (sc->bge_flags & BGEF_NO_EEPROM) 6482 printf(" - No EEPROM\n"); 6483 if (sc->bge_flags & BGEF_PCIX) 6484 printf(" - PCI-X Bus\n"); 6485 if (sc->bge_flags & BGEF_PCIE) 6486 printf(" - PCI Express Bus\n"); 6487 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6488 printf(" - RX Alignment Bug\n"); 6489 if (sc->bge_flags & BGEF_APE) 6490 printf(" - APE\n"); 6491 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6492 printf(" - CPMU\n"); 6493 if (sc->bge_flags & BGEF_TSO) 6494 printf(" - TSO\n"); 6495 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6496 printf(" - TAGGED_STATUS\n"); 6497 6498 /* PHY related */ 6499 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6500 printf(" - No 3 LEDs\n"); 6501 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6502 printf(" - CRC bug\n"); 6503 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6504 printf(" - ADC bug\n"); 6505 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6506 printf(" - 5704 A0 bug\n"); 6507 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6508 printf(" - jitter bug\n"); 6509 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6510 printf(" - BER bug\n"); 6511 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6512 printf(" - adjust trim\n"); 6513 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6514 printf(" - no wirespeed\n"); 6515 6516 /* ASF related */ 6517 if (sc->bge_asf_mode & ASF_ENABLE) 6518 printf(" - ASF enable\n"); 6519 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6520 printf(" - ASF new handshake\n"); 6521 if (sc->bge_asf_mode & ASF_STACKUP) 6522 printf(" - ASF stackup\n"); 6523 } 6524 #endif /* BGE_DEBUG */ 6525 6526 static int 6527 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6528 { 6529 prop_dictionary_t dict; 6530 prop_data_t ea; 6531 6532 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6533 return 1; 6534 6535 dict = device_properties(sc->bge_dev); 6536 ea = prop_dictionary_get(dict, "mac-address"); 6537 if (ea != NULL) { 6538 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6539 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6540 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6541 return 0; 6542 } 6543 6544 return 1; 6545 } 6546 6547 static int 6548 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6549 { 6550 uint32_t mac_addr; 6551 6552 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6553 if ((mac_addr >> 16) == 0x484b) { 6554 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6555 ether_addr[1] = (uint8_t)mac_addr; 6556 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6557 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6558 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6559 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6560 ether_addr[5] = (uint8_t)mac_addr; 6561 return 0; 6562 } 6563 return 1; 6564 } 6565 6566 static int 6567 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6568 { 6569 int mac_offset = BGE_EE_MAC_OFFSET; 6570 6571 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6572 mac_offset = BGE_EE_MAC_OFFSET_5906; 6573 6574 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6575 ETHER_ADDR_LEN)); 6576 } 6577 6578 static int 6579 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6580 { 6581 6582 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6583 return 1; 6584 6585 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6586 ETHER_ADDR_LEN)); 6587 } 6588 6589 static int 6590 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6591 { 6592 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6593 /* NOTE: Order is critical */ 6594 bge_get_eaddr_fw, 6595 bge_get_eaddr_mem, 6596 bge_get_eaddr_nvram, 6597 bge_get_eaddr_eeprom, 6598 NULL 6599 }; 6600 const bge_eaddr_fcn_t *func; 6601 6602 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6603 if ((*func)(sc, eaddr) == 0) 6604 break; 6605 } 6606 return *func == NULL ? ENXIO : 0; 6607 } 6608
Indexes created Wed Sep 24 15:09:51 GMT 2025