if_bge.c revision 1.396
1 /* $NetBSD: if_bge.c,v 1.396 2024/09/14 07:01:33 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.396 2024/09/14 07:01:33 skrll Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/callout.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> 90 #include <sys/kmem.h> 91 #include <sys/mbuf.h> 92 #include <sys/rndsource.h> 93 #include <sys/socket.h> 94 #include <sys/sockio.h> 95 #include <sys/sysctl.h> 96 #include <sys/systm.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 #include <net/bpf.h> 103 104 /* Headers for TCP Segmentation Offload (TSO) */ 105 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 106 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 107 #include <netinet/ip.h> /* for struct ip */ 108 #include <netinet/tcp.h> /* for struct tcphdr */ 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 #include <dev/mii/miidevs.h> 117 #include <dev/mii/brgphyreg.h> 118 119 #include <dev/pci/if_bgereg.h> 120 #include <dev/pci/if_bgevar.h> 121 122 #include <prop/proplib.h> 123 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 127 /* 128 * Tunable thresholds for rx-side bge interrupt mitigation. 129 */ 130 131 /* 132 * The pairs of values below were obtained from empirical measurement 133 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 134 * interrupt for every N packets received, where N is, approximately, 135 * the second value (rx_max_bds) in each pair. The values are chosen 136 * such that moving from one pair to the succeeding pair was observed 137 * to roughly halve interrupt rate under sustained input packet load. 138 * The values were empirically chosen to avoid overflowing internal 139 * limits on the bcm5700: increasing rx_ticks much beyond 600 140 * results in internal wrapping and higher interrupt rates. 141 * The limit of 46 frames was chosen to match NFS workloads. 142 * 143 * These values also work well on bcm5701, bcm5704C, and (less 144 * tested) bcm5703. On other chipsets, (including the Altima chip 145 * family), the larger values may overflow internal chip limits, 146 * leading to increasing interrupt rates rather than lower interrupt 147 * rates. 148 * 149 * Applications using heavy interrupt mitigation (interrupting every 150 * 32 or 46 frames) in both directions may need to increase the TCP 151 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 152 * full link bandwidth, due to ACKs and window updates lingering 153 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 154 */ 155 static const struct bge_load_rx_thresh { 156 int rx_ticks; 157 int rx_max_bds; } 158 bge_rx_threshes[] = { 159 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 160 { 32, 2 }, 161 { 50, 4 }, 162 { 100, 8 }, 163 { 192, 16 }, 164 { 416, 32 }, 165 { 598, 46 } 166 }; 167 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 168 169 /* XXX patchable; should be sysctl'able */ 170 static int bge_auto_thresh = 1; 171 static int bge_rx_thresh_lvl; 172 173 static int bge_rxthresh_nodenum; 174 175 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 176 177 static uint32_t bge_chipid(const struct pci_attach_args *); 178 static int bge_can_use_msi(struct bge_softc *); 179 static int bge_probe(device_t, cfdata_t, void *); 180 static void bge_attach(device_t, device_t, void *); 181 static int bge_detach(device_t, int); 182 static void bge_release_resources(struct bge_softc *); 183 184 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 185 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 186 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 187 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 188 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 189 190 static void bge_txeof(struct bge_softc *); 191 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 192 static void bge_rxeof(struct bge_softc *); 193 194 static void bge_asf_driver_up (struct bge_softc *); 195 static void bge_tick(void *); 196 static void bge_stats_update(struct bge_softc *); 197 static void bge_stats_update_regs(struct bge_softc *); 198 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 199 200 static int bge_intr(void *); 201 static void bge_start(struct ifnet *); 202 static void bge_start_locked(struct ifnet *); 203 static int bge_ifflags_cb(struct ethercom *); 204 static int bge_ioctl(struct ifnet *, u_long, void *); 205 static int bge_init(struct ifnet *); 206 static void bge_stop(struct ifnet *, int); 207 static bool bge_watchdog_tick(struct ifnet *); 208 static int bge_ifmedia_upd(struct ifnet *); 209 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 210 static void bge_handle_reset_work(struct work *, void *); 211 212 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 213 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 214 215 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 216 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 217 static void bge_setmulti(struct bge_softc *); 218 219 static void bge_handle_events(struct bge_softc *); 220 static int bge_alloc_jumbo_mem(struct bge_softc *); 221 static void bge_free_jumbo_mem(struct bge_softc *); 222 static void *bge_jalloc(struct bge_softc *); 223 static void bge_jfree(struct mbuf *, void *, size_t, void *); 224 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 225 static int bge_init_rx_ring_jumbo(struct bge_softc *); 226 static void bge_free_rx_ring_jumbo(struct bge_softc *); 227 228 static int bge_newbuf_std(struct bge_softc *, int); 229 static int bge_init_rx_ring_std(struct bge_softc *); 230 static void bge_fill_rx_ring_std(struct bge_softc *); 231 static void bge_free_rx_ring_std(struct bge_softc *m); 232 233 static void bge_free_tx_ring(struct bge_softc *m, bool); 234 static int bge_init_tx_ring(struct bge_softc *); 235 236 static int bge_chipinit(struct bge_softc *); 237 static int bge_blockinit(struct bge_softc *); 238 static int bge_phy_addr(struct bge_softc *); 239 static uint32_t bge_readmem_ind(struct bge_softc *, int); 240 static void bge_writemem_ind(struct bge_softc *, int, int); 241 static void bge_writembx(struct bge_softc *, int, int); 242 static void bge_writembx_flush(struct bge_softc *, int, int); 243 static void bge_writemem_direct(struct bge_softc *, int, int); 244 static void bge_writereg_ind(struct bge_softc *, int, int); 245 static void bge_set_max_readrq(struct bge_softc *); 246 247 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 248 static int bge_miibus_writereg(device_t, int, int, uint16_t); 249 static void bge_miibus_statchg(struct ifnet *); 250 251 #define BGE_RESET_SHUTDOWN 0 252 #define BGE_RESET_START 1 253 #define BGE_RESET_SUSPEND 2 254 static void bge_sig_post_reset(struct bge_softc *, int); 255 static void bge_sig_legacy(struct bge_softc *, int); 256 static void bge_sig_pre_reset(struct bge_softc *, int); 257 static void bge_wait_for_event_ack(struct bge_softc *); 258 static void bge_stop_fw(struct bge_softc *); 259 static int bge_reset(struct bge_softc *); 260 static void bge_link_upd(struct bge_softc *); 261 static void bge_sysctl_init(struct bge_softc *); 262 static int bge_sysctl_verify(SYSCTLFN_PROTO); 263 264 static void bge_ape_lock_init(struct bge_softc *); 265 static void bge_ape_read_fw_ver(struct bge_softc *); 266 static int bge_ape_lock(struct bge_softc *, int); 267 static void bge_ape_unlock(struct bge_softc *, int); 268 static void bge_ape_send_event(struct bge_softc *, uint32_t); 269 static void bge_ape_driver_state_change(struct bge_softc *, int); 270 271 #ifdef BGE_DEBUG 272 #define DPRINTF(x) if (bgedebug) printf x 273 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 274 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 275 int bgedebug = 0; 276 int bge_tso_debug = 0; 277 void bge_debug_info(struct bge_softc *); 278 #else 279 #define DPRINTF(x) 280 #define DPRINTFN(n, x) 281 #define BGE_TSO_PRINTF(x) 282 #endif 283 284 #ifdef BGE_EVENT_COUNTERS 285 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 286 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 287 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 288 #else 289 #define BGE_EVCNT_INCR(ev) /* nothing */ 290 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 291 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 292 #endif 293 294 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 295 /* 296 * The BCM5700 documentation seems to indicate that the hardware still has the 297 * Alteon vendor ID burned into it, though it should always be overridden by 298 * the value in the EEPROM. We'll check for it anyway. 299 */ 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 306 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 307 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 308 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 309 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 310 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 311 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 312 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 313 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 314 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 315 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 316 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 317 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 319 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 320 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 321 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 322 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 323 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 324 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 325 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 326 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 328 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 329 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 330 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 331 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 332 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 334 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 336 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 345 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 346 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 348 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 349 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 350 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 351 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 352 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 353 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 354 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 357 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 358 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 360 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 361 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 362 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 363 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 364 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 367 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 368 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 369 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 370 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 371 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 372 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 373 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 375 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 376 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 377 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 378 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 379 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 380 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 381 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 382 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 383 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 397 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 398 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 399 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 400 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 401 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 402 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 403 { 0, 0, NULL }, 404 }; 405 406 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 407 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 408 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 409 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 410 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 411 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 412 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 413 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 414 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 415 416 static const struct bge_revision { 417 uint32_t br_chipid; 418 const char *br_name; 419 } bge_revisions[] = { 420 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 421 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 422 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 423 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 424 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 425 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 426 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 427 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 428 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 429 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 430 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 431 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 432 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 433 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 434 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 435 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 436 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 437 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 438 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 439 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 440 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 441 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 442 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 443 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 444 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 445 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 446 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 447 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 448 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 449 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 450 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 451 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 452 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 453 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 454 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 455 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 456 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 457 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 458 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 459 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 460 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 461 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 462 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 463 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 464 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 465 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 466 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 467 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 468 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 469 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 470 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 471 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 472 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 473 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 474 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 475 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 476 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 477 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 478 /* 5754 and 5787 share the same ASIC ID */ 479 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 480 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 481 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 482 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 483 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 484 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 485 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 486 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 487 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 488 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 489 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 490 491 { 0, NULL } 492 }; 493 494 /* 495 * Some defaults for major revisions, so that newer steppings 496 * that we don't know about have a shot at working. 497 */ 498 static const struct bge_revision bge_majorrevs[] = { 499 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 500 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 501 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 502 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 503 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 504 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 505 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 506 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 507 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 508 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 509 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 510 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 511 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 512 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 513 /* 5754 and 5787 share the same ASIC ID */ 514 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 515 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 516 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 517 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 518 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 519 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 520 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 521 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 522 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 523 524 { 0, NULL } 525 }; 526 527 static int bge_allow_asf = 1; 528 529 #ifndef BGE_WATCHDOG_TIMEOUT 530 #define BGE_WATCHDOG_TIMEOUT 5 531 #endif 532 static int bge_watchdog_timeout = BGE_WATCHDOG_TIMEOUT; 533 534 535 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 536 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 537 538 static uint32_t 539 bge_readmem_ind(struct bge_softc *sc, int off) 540 { 541 pcireg_t val; 542 543 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 544 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 545 return 0; 546 547 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 548 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 550 return val; 551 } 552 553 static void 554 bge_writemem_ind(struct bge_softc *sc, int off, int val) 555 { 556 557 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 558 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 559 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 560 } 561 562 /* 563 * PCI Express only 564 */ 565 static void 566 bge_set_max_readrq(struct bge_softc *sc) 567 { 568 pcireg_t val; 569 570 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 571 + PCIE_DCSR); 572 val &= ~PCIE_DCSR_MAX_READ_REQ; 573 switch (sc->bge_expmrq) { 574 case 2048: 575 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 576 break; 577 case 4096: 578 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 579 break; 580 default: 581 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 582 break; 583 } 584 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 585 + PCIE_DCSR, val); 586 } 587 588 #ifdef notdef 589 static uint32_t 590 bge_readreg_ind(struct bge_softc *sc, int off) 591 { 592 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 593 return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA); 594 } 595 #endif 596 597 static void 598 bge_writereg_ind(struct bge_softc *sc, int off, int val) 599 { 600 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 601 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 602 } 603 604 static void 605 bge_writemem_direct(struct bge_softc *sc, int off, int val) 606 { 607 CSR_WRITE_4(sc, off, val); 608 } 609 610 static void 611 bge_writembx(struct bge_softc *sc, int off, int val) 612 { 613 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 614 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 615 616 CSR_WRITE_4(sc, off, val); 617 } 618 619 static void 620 bge_writembx_flush(struct bge_softc *sc, int off, int val) 621 { 622 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 623 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 624 625 CSR_WRITE_4_FLUSH(sc, off, val); 626 } 627 628 /* 629 * Clear all stale locks and select the lock for this driver instance. 630 */ 631 void 632 bge_ape_lock_init(struct bge_softc *sc) 633 { 634 struct pci_attach_args *pa = &(sc->bge_pa); 635 uint32_t bit, regbase; 636 int i; 637 638 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 639 regbase = BGE_APE_LOCK_GRANT; 640 else 641 regbase = BGE_APE_PER_LOCK_GRANT; 642 643 /* Clear any stale locks. */ 644 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 645 switch (i) { 646 case BGE_APE_LOCK_PHY0: 647 case BGE_APE_LOCK_PHY1: 648 case BGE_APE_LOCK_PHY2: 649 case BGE_APE_LOCK_PHY3: 650 bit = BGE_APE_LOCK_GRANT_DRIVER0; 651 break; 652 default: 653 if (pa->pa_function == 0) 654 bit = BGE_APE_LOCK_GRANT_DRIVER0; 655 else 656 bit = (1 << pa->pa_function); 657 } 658 APE_WRITE_4(sc, regbase + 4 * i, bit); 659 } 660 661 /* Select the PHY lock based on the device's function number. */ 662 switch (pa->pa_function) { 663 case 0: 664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 665 break; 666 case 1: 667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 668 break; 669 case 2: 670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 671 break; 672 case 3: 673 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 674 break; 675 default: 676 printf("%s: PHY lock not supported on function\n", 677 device_xname(sc->bge_dev)); 678 break; 679 } 680 } 681 682 /* 683 * Check for APE firmware, set flags, and print version info. 684 */ 685 void 686 bge_ape_read_fw_ver(struct bge_softc *sc) 687 { 688 const char *fwtype; 689 uint32_t apedata, features; 690 691 /* Check for a valid APE signature in shared memory. */ 692 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 693 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 694 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 695 return; 696 } 697 698 /* Check if APE firmware is running. */ 699 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 700 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 701 printf("%s: APE signature found but FW status not ready! " 702 "0x%08x\n", device_xname(sc->bge_dev), apedata); 703 return; 704 } 705 706 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 707 708 /* Fetch the APE firmware type and version. */ 709 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 710 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 711 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 712 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 713 fwtype = "NCSI"; 714 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 715 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 716 fwtype = "DASH"; 717 } else 718 fwtype = "UNKN"; 719 720 /* Print the APE firmware version. */ 721 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 722 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 723 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 724 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 725 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 726 } 727 728 int 729 bge_ape_lock(struct bge_softc *sc, int locknum) 730 { 731 struct pci_attach_args *pa = &(sc->bge_pa); 732 uint32_t bit, gnt, req, status; 733 int i, off; 734 735 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 736 return 0; 737 738 /* Lock request/grant registers have different bases. */ 739 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 740 req = BGE_APE_LOCK_REQ; 741 gnt = BGE_APE_LOCK_GRANT; 742 } else { 743 req = BGE_APE_PER_LOCK_REQ; 744 gnt = BGE_APE_PER_LOCK_GRANT; 745 } 746 747 off = 4 * locknum; 748 749 switch (locknum) { 750 case BGE_APE_LOCK_GPIO: 751 /* Lock required when using GPIO. */ 752 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 753 return 0; 754 if (pa->pa_function == 0) 755 bit = BGE_APE_LOCK_REQ_DRIVER0; 756 else 757 bit = (1 << pa->pa_function); 758 break; 759 case BGE_APE_LOCK_GRC: 760 /* Lock required to reset the device. */ 761 if (pa->pa_function == 0) 762 bit = BGE_APE_LOCK_REQ_DRIVER0; 763 else 764 bit = (1 << pa->pa_function); 765 break; 766 case BGE_APE_LOCK_MEM: 767 /* Lock required when accessing certain APE memory. */ 768 if (pa->pa_function == 0) 769 bit = BGE_APE_LOCK_REQ_DRIVER0; 770 else 771 bit = (1 << pa->pa_function); 772 break; 773 case BGE_APE_LOCK_PHY0: 774 case BGE_APE_LOCK_PHY1: 775 case BGE_APE_LOCK_PHY2: 776 case BGE_APE_LOCK_PHY3: 777 /* Lock required when accessing PHYs. */ 778 bit = BGE_APE_LOCK_REQ_DRIVER0; 779 break; 780 default: 781 return EINVAL; 782 } 783 784 /* Request a lock. */ 785 APE_WRITE_4_FLUSH(sc, req + off, bit); 786 787 /* Wait up to 1 second to acquire lock. */ 788 for (i = 0; i < 20000; i++) { 789 status = APE_READ_4(sc, gnt + off); 790 if (status == bit) 791 break; 792 DELAY(50); 793 } 794 795 /* Handle any errors. */ 796 if (status != bit) { 797 printf("%s: APE lock %d request failed! " 798 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 799 device_xname(sc->bge_dev), 800 locknum, req + off, bit & 0xFFFF, gnt + off, 801 status & 0xFFFF); 802 /* Revoke the lock request. */ 803 APE_WRITE_4(sc, gnt + off, bit); 804 return EBUSY; 805 } 806 807 return 0; 808 } 809 810 void 811 bge_ape_unlock(struct bge_softc *sc, int locknum) 812 { 813 struct pci_attach_args *pa = &(sc->bge_pa); 814 uint32_t bit, gnt; 815 int off; 816 817 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 818 return; 819 820 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 821 gnt = BGE_APE_LOCK_GRANT; 822 else 823 gnt = BGE_APE_PER_LOCK_GRANT; 824 825 off = 4 * locknum; 826 827 switch (locknum) { 828 case BGE_APE_LOCK_GPIO: 829 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 830 return; 831 if (pa->pa_function == 0) 832 bit = BGE_APE_LOCK_GRANT_DRIVER0; 833 else 834 bit = (1 << pa->pa_function); 835 break; 836 case BGE_APE_LOCK_GRC: 837 if (pa->pa_function == 0) 838 bit = BGE_APE_LOCK_GRANT_DRIVER0; 839 else 840 bit = (1 << pa->pa_function); 841 break; 842 case BGE_APE_LOCK_MEM: 843 if (pa->pa_function == 0) 844 bit = BGE_APE_LOCK_GRANT_DRIVER0; 845 else 846 bit = (1 << pa->pa_function); 847 break; 848 case BGE_APE_LOCK_PHY0: 849 case BGE_APE_LOCK_PHY1: 850 case BGE_APE_LOCK_PHY2: 851 case BGE_APE_LOCK_PHY3: 852 bit = BGE_APE_LOCK_GRANT_DRIVER0; 853 break; 854 default: 855 return; 856 } 857 858 /* Write and flush for consecutive bge_ape_lock() */ 859 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 860 } 861 862 /* 863 * Send an event to the APE firmware. 864 */ 865 void 866 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 867 { 868 uint32_t apedata; 869 int i; 870 871 /* NCSI does not support APE events. */ 872 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 873 return; 874 875 /* Wait up to 1ms for APE to service previous event. */ 876 for (i = 10; i > 0; i--) { 877 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 878 break; 879 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 880 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 881 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 882 BGE_APE_EVENT_STATUS_EVENT_PENDING); 883 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 884 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 885 break; 886 } 887 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 888 DELAY(100); 889 } 890 if (i == 0) { 891 printf("%s: APE event 0x%08x send timed out\n", 892 device_xname(sc->bge_dev), event); 893 } 894 } 895 896 void 897 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 898 { 899 uint32_t apedata, event; 900 901 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 902 return; 903 904 switch (kind) { 905 case BGE_RESET_START: 906 /* If this is the first load, clear the load counter. */ 907 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 908 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 909 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 910 else { 911 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 912 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 913 } 914 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 915 BGE_APE_HOST_SEG_SIG_MAGIC); 916 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 917 BGE_APE_HOST_SEG_LEN_MAGIC); 918 919 /* Add some version info if bge(4) supports it. */ 920 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 921 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 922 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 923 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 924 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 925 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 926 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 927 BGE_APE_HOST_DRVR_STATE_START); 928 event = BGE_APE_EVENT_STATUS_STATE_START; 929 break; 930 case BGE_RESET_SHUTDOWN: 931 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 932 BGE_APE_HOST_DRVR_STATE_UNLOAD); 933 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 934 break; 935 case BGE_RESET_SUSPEND: 936 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 937 break; 938 default: 939 return; 940 } 941 942 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 943 BGE_APE_EVENT_STATUS_STATE_CHNGE); 944 } 945 946 static uint8_t 947 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 948 { 949 uint32_t access, byte = 0; 950 int i; 951 952 /* Lock. */ 953 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 954 for (i = 0; i < 8000; i++) { 955 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 956 break; 957 DELAY(20); 958 } 959 if (i == 8000) 960 return 1; 961 962 /* Enable access. */ 963 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 964 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 965 966 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 967 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 968 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 969 DELAY(10); 970 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 971 DELAY(10); 972 break; 973 } 974 } 975 976 if (i == BGE_TIMEOUT * 10) { 977 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 978 return 1; 979 } 980 981 /* Get result. */ 982 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 983 984 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 985 986 /* Disable access. */ 987 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 988 989 /* Unlock. */ 990 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 991 992 return 0; 993 } 994 995 /* 996 * Read a sequence of bytes from NVRAM. 997 */ 998 static int 999 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1000 { 1001 int error = 0, i; 1002 uint8_t byte = 0; 1003 1004 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1005 return 1; 1006 1007 for (i = 0; i < cnt; i++) { 1008 error = bge_nvram_getbyte(sc, off + i, &byte); 1009 if (error) 1010 break; 1011 *(dest + i) = byte; 1012 } 1013 1014 return error ? 1 : 0; 1015 } 1016 1017 /* 1018 * Read a byte of data stored in the EEPROM at address 'addr.' The 1019 * BCM570x supports both the traditional bitbang interface and an 1020 * auto access interface for reading the EEPROM. We use the auto 1021 * access method. 1022 */ 1023 static uint8_t 1024 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1025 { 1026 int i; 1027 uint32_t byte = 0; 1028 1029 /* 1030 * Enable use of auto EEPROM access so we can avoid 1031 * having to use the bitbang method. 1032 */ 1033 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1034 1035 /* Reset the EEPROM, load the clock period. */ 1036 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1037 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1038 DELAY(20); 1039 1040 /* Issue the read EEPROM command. */ 1041 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1042 1043 /* Wait for completion */ 1044 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1045 DELAY(10); 1046 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1047 break; 1048 } 1049 1050 if (i == BGE_TIMEOUT * 10) { 1051 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1052 return 1; 1053 } 1054 1055 /* Get result. */ 1056 byte = CSR_READ_4(sc, BGE_EE_DATA); 1057 1058 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1059 1060 return 0; 1061 } 1062 1063 /* 1064 * Read a sequence of bytes from the EEPROM. 1065 */ 1066 static int 1067 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1068 { 1069 int error = 0, i; 1070 uint8_t byte = 0; 1071 char *dest = destv; 1072 1073 for (i = 0; i < cnt; i++) { 1074 error = bge_eeprom_getbyte(sc, off + i, &byte); 1075 if (error) 1076 break; 1077 *(dest + i) = byte; 1078 } 1079 1080 return error ? 1 : 0; 1081 } 1082 1083 static int 1084 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1085 { 1086 struct bge_softc * const sc = device_private(dev); 1087 uint32_t data; 1088 uint32_t autopoll; 1089 int rv = 0; 1090 int i; 1091 1092 KASSERT(mutex_owned(sc->sc_intr_lock)); 1093 1094 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1095 return -1; 1096 1097 /* Reading with autopolling on may trigger PCI errors */ 1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1099 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1100 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1101 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1102 DELAY(80); 1103 } 1104 1105 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1106 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1107 1108 for (i = 0; i < BGE_TIMEOUT; i++) { 1109 delay(10); 1110 data = CSR_READ_4(sc, BGE_MI_COMM); 1111 if (!(data & BGE_MICOMM_BUSY)) { 1112 DELAY(5); 1113 data = CSR_READ_4(sc, BGE_MI_COMM); 1114 break; 1115 } 1116 } 1117 1118 if (i == BGE_TIMEOUT) { 1119 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1120 rv = ETIMEDOUT; 1121 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1122 /* XXX This error occurs on some devices while attaching. */ 1123 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1124 rv = EIO; 1125 } else 1126 *val = data & BGE_MICOMM_DATA; 1127 1128 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1129 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1130 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1131 DELAY(80); 1132 } 1133 1134 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1135 1136 return rv; 1137 } 1138 1139 static int 1140 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1141 { 1142 struct bge_softc * const sc = device_private(dev); 1143 uint32_t data, autopoll; 1144 int rv = 0; 1145 int i; 1146 1147 KASSERT(mutex_owned(sc->sc_intr_lock)); 1148 1149 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1150 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1151 return 0; 1152 1153 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1154 return -1; 1155 1156 /* Reading with autopolling on may trigger PCI errors */ 1157 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1158 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1159 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1160 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1161 DELAY(80); 1162 } 1163 1164 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1165 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1166 1167 for (i = 0; i < BGE_TIMEOUT; i++) { 1168 delay(10); 1169 data = CSR_READ_4(sc, BGE_MI_COMM); 1170 if (!(data & BGE_MICOMM_BUSY)) { 1171 delay(5); 1172 data = CSR_READ_4(sc, BGE_MI_COMM); 1173 break; 1174 } 1175 } 1176 1177 if (i == BGE_TIMEOUT) { 1178 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1179 rv = ETIMEDOUT; 1180 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1181 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1182 rv = EIO; 1183 } 1184 1185 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1186 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1187 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1188 delay(80); 1189 } 1190 1191 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1192 1193 return rv; 1194 } 1195 1196 static void 1197 bge_miibus_statchg(struct ifnet *ifp) 1198 { 1199 struct bge_softc * const sc = ifp->if_softc; 1200 struct mii_data *mii = &sc->bge_mii; 1201 uint32_t mac_mode, rx_mode, tx_mode; 1202 1203 KASSERT(mutex_owned(sc->sc_intr_lock)); 1204 1205 /* 1206 * Get flow control negotiation result. 1207 */ 1208 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1209 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1210 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1211 1212 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1213 mii->mii_media_status & IFM_ACTIVE && 1214 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1215 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1216 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1217 (!(mii->mii_media_status & IFM_ACTIVE) || 1218 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1219 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1220 1221 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1222 return; 1223 1224 /* Set the port mode (MII/GMII) to match the link speed. */ 1225 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1226 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1227 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1228 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1229 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1230 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1231 mac_mode |= BGE_PORTMODE_GMII; 1232 else 1233 mac_mode |= BGE_PORTMODE_MII; 1234 1235 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1236 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1237 if ((mii->mii_media_active & IFM_FDX) != 0) { 1238 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1239 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1240 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1241 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1242 } else 1243 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1244 1245 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1246 DELAY(40); 1247 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1248 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1249 } 1250 1251 /* 1252 * Update rx threshold levels to values in a particular slot 1253 * of the interrupt-mitigation table bge_rx_threshes. 1254 */ 1255 static void 1256 bge_set_thresh(struct ifnet *ifp, int lvl) 1257 { 1258 struct bge_softc * const sc = ifp->if_softc; 1259 1260 /* 1261 * For now, just save the new Rx-intr thresholds and record 1262 * that a threshold update is pending. Updating the hardware 1263 * registers here (even at splhigh()) is observed to 1264 * occasionally cause glitches where Rx-interrupts are not 1265 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1266 */ 1267 mutex_enter(sc->sc_intr_lock); 1268 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1269 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1270 sc->bge_pending_rxintr_change = true; 1271 mutex_exit(sc->sc_intr_lock); 1272 } 1273 1274 1275 /* 1276 * Update Rx thresholds of all bge devices 1277 */ 1278 static void 1279 bge_update_all_threshes(int lvl) 1280 { 1281 const char * const namebuf = "bge"; 1282 const size_t namelen = strlen(namebuf); 1283 struct ifnet *ifp; 1284 1285 if (lvl < 0) 1286 lvl = 0; 1287 else if (lvl >= NBGE_RX_THRESH) 1288 lvl = NBGE_RX_THRESH - 1; 1289 1290 /* 1291 * Now search all the interfaces for this name/number 1292 */ 1293 int s = pserialize_read_enter(); 1294 IFNET_READER_FOREACH(ifp) { 1295 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1296 continue; 1297 /* We got a match: update if doing auto-threshold-tuning */ 1298 if (bge_auto_thresh) 1299 bge_set_thresh(ifp, lvl); 1300 } 1301 pserialize_read_exit(s); 1302 } 1303 1304 /* 1305 * Handle events that have triggered interrupts. 1306 */ 1307 static void 1308 bge_handle_events(struct bge_softc *sc) 1309 { 1310 1311 return; 1312 } 1313 1314 /* 1315 * Memory management for jumbo frames. 1316 */ 1317 1318 static int 1319 bge_alloc_jumbo_mem(struct bge_softc *sc) 1320 { 1321 char *ptr, *kva; 1322 int i, rseg, state, error; 1323 struct bge_jpool_entry *entry; 1324 1325 state = error = 0; 1326 1327 /* Grab a big chunk o' storage. */ 1328 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1329 &sc->bge_cdata.bge_rx_jumbo_seg, 1, &rseg, BUS_DMA_WAITOK)) { 1330 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1331 return ENOBUFS; 1332 } 1333 1334 state = 1; 1335 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1336 rseg, BGE_JMEM, (void **)&kva, BUS_DMA_WAITOK)) { 1337 aprint_error_dev(sc->bge_dev, 1338 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1339 error = ENOBUFS; 1340 goto out; 1341 } 1342 1343 state = 2; 1344 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1345 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_jumbo_map)) { 1346 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1347 error = ENOBUFS; 1348 goto out; 1349 } 1350 1351 state = 3; 1352 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1353 kva, BGE_JMEM, NULL, BUS_DMA_WAITOK)) { 1354 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1355 error = ENOBUFS; 1356 goto out; 1357 } 1358 1359 state = 4; 1360 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1361 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1362 1363 SLIST_INIT(&sc->bge_jfree_listhead); 1364 SLIST_INIT(&sc->bge_jinuse_listhead); 1365 1366 /* 1367 * Now divide it up into 9K pieces and save the addresses 1368 * in an array. 1369 */ 1370 ptr = sc->bge_cdata.bge_jumbo_buf; 1371 for (i = 0; i < BGE_JSLOTS; i++) { 1372 sc->bge_cdata.bge_jslots[i] = ptr; 1373 ptr += BGE_JLEN; 1374 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 1375 entry->slot = i; 1376 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1377 entry, jpool_entries); 1378 } 1379 out: 1380 if (error != 0) { 1381 switch (state) { 1382 case 4: 1383 bus_dmamap_unload(sc->bge_dmatag, 1384 sc->bge_cdata.bge_rx_jumbo_map); 1385 /* FALLTHROUGH */ 1386 case 3: 1387 bus_dmamap_destroy(sc->bge_dmatag, 1388 sc->bge_cdata.bge_rx_jumbo_map); 1389 /* FALLTHROUGH */ 1390 case 2: 1391 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1392 /* FALLTHROUGH */ 1393 case 1: 1394 bus_dmamem_free(sc->bge_dmatag, 1395 &sc->bge_cdata.bge_rx_jumbo_seg, rseg); 1396 break; 1397 default: 1398 break; 1399 } 1400 } 1401 1402 return error; 1403 } 1404 1405 static void 1406 bge_free_jumbo_mem(struct bge_softc *sc) 1407 { 1408 struct bge_jpool_entry *entry, *tmp; 1409 1410 KASSERT(SLIST_EMPTY(&sc->bge_jinuse_listhead)); 1411 1412 SLIST_FOREACH_SAFE(entry, &sc->bge_jfree_listhead, jpool_entries, tmp) { 1413 kmem_free(entry, sizeof(*entry)); 1414 } 1415 1416 bus_dmamap_unload(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1417 1418 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1419 1420 bus_dmamem_unmap(sc->bge_dmatag, sc->bge_cdata.bge_jumbo_buf, BGE_JMEM); 1421 1422 bus_dmamem_free(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1); 1423 } 1424 1425 /* 1426 * Allocate a jumbo buffer. 1427 */ 1428 static void * 1429 bge_jalloc(struct bge_softc *sc) 1430 { 1431 struct bge_jpool_entry *entry; 1432 1433 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1434 1435 if (entry == NULL) { 1436 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1437 return NULL; 1438 } 1439 1440 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1441 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1442 return sc->bge_cdata.bge_jslots[entry->slot]; 1443 } 1444 1445 /* 1446 * Release a jumbo buffer. 1447 */ 1448 static void 1449 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1450 { 1451 struct bge_jpool_entry *entry; 1452 struct bge_softc * const sc = arg; 1453 1454 if (sc == NULL) 1455 panic("bge_jfree: can't find softc pointer!"); 1456 1457 /* calculate the slot this buffer belongs to */ 1458 int i = ((char *)buf - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1459 1460 if (i < 0 || i >= BGE_JSLOTS) 1461 panic("bge_jfree: asked to free buffer that we don't manage!"); 1462 1463 mutex_enter(sc->sc_intr_lock); 1464 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1465 if (entry == NULL) 1466 panic("bge_jfree: buffer not in use!"); 1467 entry->slot = i; 1468 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1469 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1470 mutex_exit(sc->sc_intr_lock); 1471 1472 if (__predict_true(m != NULL)) 1473 pool_cache_put(mb_cache, m); 1474 } 1475 1476 1477 /* 1478 * Initialize a standard receive ring descriptor. 1479 */ 1480 static int 1481 bge_newbuf_std(struct bge_softc *sc, int i) 1482 { 1483 const bus_dmamap_t dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1484 struct mbuf *m; 1485 1486 MGETHDR(m, M_DONTWAIT, MT_DATA); 1487 if (m == NULL) 1488 return ENOBUFS; 1489 1490 MCLGET(m, M_DONTWAIT); 1491 if (!(m->m_flags & M_EXT)) { 1492 m_freem(m); 1493 return ENOBUFS; 1494 } 1495 m->m_len = m->m_pkthdr.len = MCLBYTES; 1496 1497 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1498 m_adj(m, ETHER_ALIGN); 1499 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m, 1500 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1501 m_freem(m); 1502 return ENOBUFS; 1503 } 1504 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1505 BUS_DMASYNC_PREREAD); 1506 sc->bge_cdata.bge_rx_std_chain[i] = m; 1507 1508 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1509 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1510 i * sizeof(struct bge_rx_bd), 1511 sizeof(struct bge_rx_bd), 1512 BUS_DMASYNC_POSTWRITE); 1513 1514 struct bge_rx_bd * const r = &sc->bge_rdata->bge_rx_std_ring[i]; 1515 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1516 r->bge_flags = BGE_RXBDFLAG_END; 1517 r->bge_len = m->m_len; 1518 r->bge_idx = i; 1519 1520 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1521 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1522 i * sizeof(struct bge_rx_bd), 1523 sizeof(struct bge_rx_bd), 1524 BUS_DMASYNC_PREWRITE); 1525 1526 sc->bge_std_cnt++; 1527 1528 return 0; 1529 } 1530 1531 /* 1532 * Initialize a jumbo receive ring descriptor. This allocates 1533 * a jumbo buffer from the pool managed internally by the driver. 1534 */ 1535 static int 1536 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1537 { 1538 struct mbuf *m_new = NULL; 1539 struct bge_rx_bd *r; 1540 void *buf = NULL; 1541 1542 if (m == NULL) { 1543 1544 /* Allocate the mbuf. */ 1545 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1546 if (m_new == NULL) 1547 return ENOBUFS; 1548 1549 /* Allocate the jumbo buffer */ 1550 buf = bge_jalloc(sc); 1551 if (buf == NULL) { 1552 m_freem(m_new); 1553 aprint_error_dev(sc->bge_dev, 1554 "jumbo allocation failed -- packet dropped!\n"); 1555 return ENOBUFS; 1556 } 1557 1558 /* Attach the buffer to the mbuf. */ 1559 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1560 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1561 bge_jfree, sc); 1562 m_new->m_flags |= M_EXT_RW; 1563 } else { 1564 m_new = m; 1565 buf = m_new->m_data = m_new->m_ext.ext_buf; 1566 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1567 } 1568 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1569 m_adj(m_new, ETHER_ALIGN); 1570 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1571 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1572 BGE_JLEN, BUS_DMASYNC_PREREAD); 1573 1574 /* Set up the descriptor. */ 1575 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1576 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1577 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1578 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1579 r->bge_len = m_new->m_len; 1580 r->bge_idx = i; 1581 1582 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1583 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1584 i * sizeof(struct bge_rx_bd), 1585 sizeof(struct bge_rx_bd), 1586 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1587 1588 return 0; 1589 } 1590 1591 static int 1592 bge_init_rx_ring_std(struct bge_softc *sc) 1593 { 1594 bus_dmamap_t dmamap; 1595 int error = 0; 1596 u_int i; 1597 1598 if (sc->bge_flags & BGEF_RXRING_VALID) 1599 return 0; 1600 1601 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1602 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1603 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dmamap); 1604 if (error) 1605 goto uncreate; 1606 1607 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1608 memset(&sc->bge_rdata->bge_rx_std_ring[i], 0, 1609 sizeof(struct bge_rx_bd)); 1610 } 1611 1612 sc->bge_std = i - 1; 1613 sc->bge_std_cnt = 0; 1614 bge_fill_rx_ring_std(sc); 1615 1616 sc->bge_flags |= BGEF_RXRING_VALID; 1617 1618 return 0; 1619 1620 uncreate: 1621 while (--i) { 1622 bus_dmamap_destroy(sc->bge_dmatag, 1623 sc->bge_cdata.bge_rx_std_map[i]); 1624 } 1625 return error; 1626 } 1627 1628 static void 1629 bge_fill_rx_ring_std(struct bge_softc *sc) 1630 { 1631 int i = sc->bge_std; 1632 bool post = false; 1633 1634 while (sc->bge_std_cnt < BGE_STD_RX_RING_CNT) { 1635 BGE_INC(i, BGE_STD_RX_RING_CNT); 1636 1637 if (bge_newbuf_std(sc, i) != 0) 1638 break; 1639 1640 sc->bge_std = i; 1641 post = true; 1642 } 1643 1644 if (post) 1645 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1646 } 1647 1648 1649 static void 1650 bge_free_rx_ring_std(struct bge_softc *sc) 1651 { 1652 1653 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1654 return; 1655 1656 for (u_int i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1657 const bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i]; 1658 struct mbuf * const m = sc->bge_cdata.bge_rx_std_chain[i]; 1659 if (m != NULL) { 1660 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 1661 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1662 bus_dmamap_unload(sc->bge_dmatag, dmap); 1663 m_freem(m); 1664 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1665 } 1666 bus_dmamap_destroy(sc->bge_dmatag, 1667 sc->bge_cdata.bge_rx_std_map[i]); 1668 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1669 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1670 sizeof(struct bge_rx_bd)); 1671 } 1672 1673 sc->bge_flags &= ~BGEF_RXRING_VALID; 1674 } 1675 1676 static int 1677 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1678 { 1679 int i; 1680 volatile struct bge_rcb *rcb; 1681 1682 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1683 return 0; 1684 1685 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1686 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1687 return ENOBUFS; 1688 } 1689 1690 sc->bge_jumbo = i - 1; 1691 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1692 1693 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1694 rcb->bge_maxlen_flags = 0; 1695 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1696 1697 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1698 1699 return 0; 1700 } 1701 1702 static void 1703 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1704 { 1705 int i; 1706 1707 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1708 return; 1709 1710 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1711 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1712 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1713 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1714 sizeof(struct bge_rx_bd)); 1715 } 1716 1717 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1718 } 1719 1720 static void 1721 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1722 { 1723 int i; 1724 struct txdmamap_pool_entry *dma; 1725 1726 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1727 return; 1728 1729 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1730 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1731 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1732 sc->bge_cdata.bge_tx_chain[i] = NULL; 1733 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1734 link); 1735 sc->txdma[i] = 0; 1736 } 1737 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1738 sizeof(struct bge_tx_bd)); 1739 } 1740 1741 if (disable) { 1742 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1743 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1744 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1745 if (sc->bge_dma64) { 1746 bus_dmamap_destroy(sc->bge_dmatag32, 1747 dma->dmamap32); 1748 } 1749 kmem_free(dma, sizeof(*dma)); 1750 } 1751 SLIST_INIT(&sc->txdma_list); 1752 } 1753 1754 sc->bge_flags &= ~BGEF_TXRING_VALID; 1755 } 1756 1757 static int 1758 bge_init_tx_ring(struct bge_softc *sc) 1759 { 1760 struct ifnet * const ifp = &sc->ethercom.ec_if; 1761 int i; 1762 bus_dmamap_t dmamap, dmamap32; 1763 bus_size_t maxsegsz; 1764 struct txdmamap_pool_entry *dma; 1765 1766 if (sc->bge_flags & BGEF_TXRING_VALID) 1767 return 0; 1768 1769 sc->bge_txcnt = 0; 1770 sc->bge_tx_saved_considx = 0; 1771 1772 /* Initialize transmit producer index for host-memory send ring. */ 1773 sc->bge_tx_prodidx = 0; 1774 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1775 /* 5700 b2 errata */ 1776 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1777 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1778 1779 /* NIC-memory send ring not used; initialize to zero. */ 1780 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1781 /* 5700 b2 errata */ 1782 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1783 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1784 1785 /* Limit DMA segment size for some chips */ 1786 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1787 (ifp->if_mtu <= ETHERMTU)) 1788 maxsegsz = 2048; 1789 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1790 maxsegsz = 4096; 1791 else 1792 maxsegsz = ETHER_MAX_LEN_JUMBO; 1793 1794 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1795 goto alloc_done; 1796 1797 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1798 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1799 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1800 &dmamap)) 1801 return ENOBUFS; 1802 if (dmamap == NULL) 1803 panic("dmamap NULL in bge_init_tx_ring"); 1804 if (sc->bge_dma64) { 1805 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1806 BGE_NTXSEG, maxsegsz, 0, 1807 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1808 &dmamap32)) { 1809 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1810 return ENOBUFS; 1811 } 1812 if (dmamap32 == NULL) 1813 panic("dmamap32 NULL in bge_init_tx_ring"); 1814 } else 1815 dmamap32 = dmamap; 1816 dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP); 1817 if (dma == NULL) { 1818 aprint_error_dev(sc->bge_dev, 1819 "can't alloc txdmamap_pool_entry\n"); 1820 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1821 if (sc->bge_dma64) 1822 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1823 return ENOMEM; 1824 } 1825 dma->dmamap = dmamap; 1826 dma->dmamap32 = dmamap32; 1827 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1828 } 1829 alloc_done: 1830 sc->bge_flags |= BGEF_TXRING_VALID; 1831 1832 return 0; 1833 } 1834 1835 static void 1836 bge_setmulti(struct bge_softc *sc) 1837 { 1838 struct ethercom * const ec = &sc->ethercom; 1839 struct ether_multi *enm; 1840 struct ether_multistep step; 1841 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1842 uint32_t h; 1843 int i; 1844 1845 KASSERT(mutex_owned(sc->sc_mcast_lock)); 1846 if (sc->bge_if_flags & IFF_PROMISC) 1847 goto allmulti; 1848 1849 /* Now program new ones. */ 1850 ETHER_LOCK(ec); 1851 ETHER_FIRST_MULTI(step, ec, enm); 1852 while (enm != NULL) { 1853 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1854 /* 1855 * We must listen to a range of multicast addresses. 1856 * For now, just accept all multicasts, rather than 1857 * trying to set only those filter bits needed to match 1858 * the range. (At this time, the only use of address 1859 * ranges is for IP multicast routing, for which the 1860 * range is big enough to require all bits set.) 1861 */ 1862 ETHER_UNLOCK(ec); 1863 goto allmulti; 1864 } 1865 1866 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1867 1868 /* Just want the 7 least-significant bits. */ 1869 h &= 0x7f; 1870 1871 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1872 ETHER_NEXT_MULTI(step, enm); 1873 } 1874 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1875 ETHER_UNLOCK(ec); 1876 1877 goto setit; 1878 1879 allmulti: 1880 ETHER_LOCK(ec); 1881 ec->ec_flags |= ETHER_F_ALLMULTI; 1882 ETHER_UNLOCK(ec); 1883 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1884 1885 setit: 1886 for (i = 0; i < 4; i++) 1887 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1888 } 1889 1890 static void 1891 bge_sig_pre_reset(struct bge_softc *sc, int type) 1892 { 1893 1894 /* 1895 * Some chips don't like this so only do this if ASF is enabled 1896 */ 1897 if (sc->bge_asf_mode) 1898 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1899 1900 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1901 switch (type) { 1902 case BGE_RESET_START: 1903 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1904 BGE_FW_DRV_STATE_START); 1905 break; 1906 case BGE_RESET_SHUTDOWN: 1907 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1908 BGE_FW_DRV_STATE_UNLOAD); 1909 break; 1910 case BGE_RESET_SUSPEND: 1911 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1912 BGE_FW_DRV_STATE_SUSPEND); 1913 break; 1914 } 1915 } 1916 1917 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1918 bge_ape_driver_state_change(sc, type); 1919 } 1920 1921 static void 1922 bge_sig_post_reset(struct bge_softc *sc, int type) 1923 { 1924 1925 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1926 switch (type) { 1927 case BGE_RESET_START: 1928 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1929 BGE_FW_DRV_STATE_START_DONE); 1930 /* START DONE */ 1931 break; 1932 case BGE_RESET_SHUTDOWN: 1933 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1934 BGE_FW_DRV_STATE_UNLOAD_DONE); 1935 break; 1936 } 1937 } 1938 1939 if (type == BGE_RESET_SHUTDOWN) 1940 bge_ape_driver_state_change(sc, type); 1941 } 1942 1943 static void 1944 bge_sig_legacy(struct bge_softc *sc, int type) 1945 { 1946 1947 if (sc->bge_asf_mode) { 1948 switch (type) { 1949 case BGE_RESET_START: 1950 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1951 BGE_FW_DRV_STATE_START); 1952 break; 1953 case BGE_RESET_SHUTDOWN: 1954 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1955 BGE_FW_DRV_STATE_UNLOAD); 1956 break; 1957 } 1958 } 1959 } 1960 1961 static void 1962 bge_wait_for_event_ack(struct bge_softc *sc) 1963 { 1964 int i; 1965 1966 /* wait up to 2500usec */ 1967 for (i = 0; i < 250; i++) { 1968 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1969 BGE_RX_CPU_DRV_EVENT)) 1970 break; 1971 DELAY(10); 1972 } 1973 } 1974 1975 static void 1976 bge_stop_fw(struct bge_softc *sc) 1977 { 1978 1979 if (sc->bge_asf_mode) { 1980 bge_wait_for_event_ack(sc); 1981 1982 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1983 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1984 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1985 1986 bge_wait_for_event_ack(sc); 1987 } 1988 } 1989 1990 static int 1991 bge_poll_fw(struct bge_softc *sc) 1992 { 1993 uint32_t val; 1994 int i; 1995 1996 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1997 for (i = 0; i < BGE_TIMEOUT; i++) { 1998 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1999 if (val & BGE_VCPU_STATUS_INIT_DONE) 2000 break; 2001 DELAY(100); 2002 } 2003 if (i >= BGE_TIMEOUT) { 2004 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2005 return -1; 2006 } 2007 } else { 2008 /* 2009 * Poll the value location we just wrote until 2010 * we see the 1's complement of the magic number. 2011 * This indicates that the firmware initialization 2012 * is complete. 2013 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2014 */ 2015 for (i = 0; i < BGE_TIMEOUT; i++) { 2016 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2017 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2018 break; 2019 DELAY(10); 2020 } 2021 2022 if ((i >= BGE_TIMEOUT) 2023 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2024 aprint_error_dev(sc->bge_dev, 2025 "firmware handshake timed out, val = %x\n", val); 2026 return -1; 2027 } 2028 } 2029 2030 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2031 /* tg3 says we have to wait extra time */ 2032 delay(10 * 1000); 2033 } 2034 2035 return 0; 2036 } 2037 2038 int 2039 bge_phy_addr(struct bge_softc *sc) 2040 { 2041 struct pci_attach_args *pa = &(sc->bge_pa); 2042 int phy_addr = 1; 2043 2044 /* 2045 * PHY address mapping for various devices. 2046 * 2047 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2048 * ---------+-------+-------+-------+-------+ 2049 * BCM57XX | 1 | X | X | X | 2050 * BCM5704 | 1 | X | 1 | X | 2051 * BCM5717 | 1 | 8 | 2 | 9 | 2052 * BCM5719 | 1 | 8 | 2 | 9 | 2053 * BCM5720 | 1 | 8 | 2 | 9 | 2054 * 2055 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2056 * ---------+-------+-------+-------+-------+ 2057 * BCM57XX | X | X | X | X | 2058 * BCM5704 | X | X | X | X | 2059 * BCM5717 | X | X | X | X | 2060 * BCM5719 | 3 | 10 | 4 | 11 | 2061 * BCM5720 | X | X | X | X | 2062 * 2063 * Other addresses may respond but they are not 2064 * IEEE compliant PHYs and should be ignored. 2065 */ 2066 switch (BGE_ASICREV(sc->bge_chipid)) { 2067 case BGE_ASICREV_BCM5717: 2068 case BGE_ASICREV_BCM5719: 2069 case BGE_ASICREV_BCM5720: 2070 phy_addr = pa->pa_function; 2071 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2072 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2073 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2074 } else { 2075 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2076 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2077 } 2078 } 2079 2080 return phy_addr; 2081 } 2082 2083 /* 2084 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2085 * self-test results. 2086 */ 2087 static int 2088 bge_chipinit(struct bge_softc *sc) 2089 { 2090 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2091 int i; 2092 2093 /* Set endianness before we access any non-PCI registers. */ 2094 misc_ctl = BGE_INIT; 2095 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2096 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2097 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2098 misc_ctl); 2099 2100 /* 2101 * Clear the MAC statistics block in the NIC's 2102 * internal memory. 2103 */ 2104 for (i = BGE_STATS_BLOCK; 2105 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2106 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2107 2108 for (i = BGE_STATUS_BLOCK; 2109 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2110 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2111 2112 /* 5717 workaround from tg3 */ 2113 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2114 /* Save */ 2115 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2116 2117 /* Temporary modify MODE_CTL to control TLP */ 2118 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2119 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2120 2121 /* Control TLP */ 2122 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2123 BGE_TLP_PHYCTL1); 2124 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2125 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2126 2127 /* Restore */ 2128 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2129 } 2130 2131 if (BGE_IS_57765_FAMILY(sc)) { 2132 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2133 /* Save */ 2134 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2135 2136 /* Temporary modify MODE_CTL to control TLP */ 2137 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2138 CSR_WRITE_4(sc, BGE_MODE_CTL, 2139 reg | BGE_MODECTL_PCIE_TLPADDR1); 2140 2141 /* Control TLP */ 2142 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2143 BGE_TLP_PHYCTL5); 2144 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2145 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2146 2147 /* Restore */ 2148 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2149 } 2150 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2151 /* 2152 * For the 57766 and non Ax versions of 57765, bootcode 2153 * needs to setup the PCIE Fast Training Sequence (FTS) 2154 * value to prevent transmit hangs. 2155 */ 2156 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2157 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2158 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2159 2160 /* Save */ 2161 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2162 2163 /* Temporary modify MODE_CTL to control TLP */ 2164 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2165 CSR_WRITE_4(sc, BGE_MODE_CTL, 2166 reg | BGE_MODECTL_PCIE_TLPADDR0); 2167 2168 /* Control TLP */ 2169 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2170 BGE_TLP_FTSMAX); 2171 reg &= ~BGE_TLP_FTSMAX_MSK; 2172 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2173 reg | BGE_TLP_FTSMAX_VAL); 2174 2175 /* Restore */ 2176 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2177 } 2178 2179 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2180 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2181 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2182 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2183 } 2184 2185 /* Set up the PCI DMA control register. */ 2186 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2187 if (sc->bge_flags & BGEF_PCIE) { 2188 /* Read watermark not used, 128 bytes for write. */ 2189 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2190 device_xname(sc->bge_dev))); 2191 if (sc->bge_mps >= 256) 2192 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2193 else 2194 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2195 } else if (sc->bge_flags & BGEF_PCIX) { 2196 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2197 device_xname(sc->bge_dev))); 2198 /* PCI-X bus */ 2199 if (BGE_IS_5714_FAMILY(sc)) { 2200 /* 256 bytes for read and write. */ 2201 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2202 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2203 2204 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2205 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2206 else 2207 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2208 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2209 /* 2210 * In the BCM5703, the DMA read watermark should 2211 * be set to less than or equal to the maximum 2212 * memory read byte count of the PCI-X command 2213 * register. 2214 */ 2215 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2216 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2217 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2218 /* 1536 bytes for read, 384 bytes for write. */ 2219 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2220 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2221 } else { 2222 /* 384 bytes for read and write. */ 2223 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2224 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2225 (0x0F); 2226 } 2227 2228 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2229 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2230 uint32_t tmp; 2231 2232 /* Set ONEDMA_ATONCE for hardware workaround. */ 2233 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2234 if (tmp == 6 || tmp == 7) 2235 dma_rw_ctl |= 2236 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2237 2238 /* Set PCI-X DMA write workaround. */ 2239 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2240 } 2241 } else { 2242 /* Conventional PCI bus: 256 bytes for read and write. */ 2243 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2244 device_xname(sc->bge_dev))); 2245 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2246 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2247 2248 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2249 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2250 dma_rw_ctl |= 0x0F; 2251 } 2252 2253 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2254 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2255 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2256 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2257 2258 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2259 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2260 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2261 2262 if (BGE_IS_57765_PLUS(sc)) { 2263 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2264 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2265 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2266 2267 /* 2268 * Enable HW workaround for controllers that misinterpret 2269 * a status tag update and leave interrupts permanently 2270 * disabled. 2271 */ 2272 if (!BGE_IS_57765_FAMILY(sc) && 2273 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2274 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2275 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2276 } 2277 2278 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2279 dma_rw_ctl); 2280 2281 /* 2282 * Set up general mode register. 2283 */ 2284 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2285 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2286 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2287 /* Retain Host-2-BMC settings written by APE firmware. */ 2288 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2289 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2290 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2291 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2292 } 2293 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2294 BGE_MODECTL_TX_NO_PHDR_CSUM; 2295 2296 /* 2297 * BCM5701 B5 have a bug causing data corruption when using 2298 * 64-bit DMA reads, which can be terminated early and then 2299 * completed later as 32-bit accesses, in combination with 2300 * certain bridges. 2301 */ 2302 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2303 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2304 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2305 2306 /* 2307 * Tell the firmware the driver is running 2308 */ 2309 if (sc->bge_asf_mode & ASF_STACKUP) 2310 mode_ctl |= BGE_MODECTL_STACKUP; 2311 2312 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2313 2314 /* 2315 * Disable memory write invalidate. Apparently it is not supported 2316 * properly by these devices. 2317 */ 2318 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2319 PCI_COMMAND_INVALIDATE_ENABLE); 2320 2321 #ifdef __brokenalpha__ 2322 /* 2323 * Must insure that we do not cross an 8K (bytes) boundary 2324 * for DMA reads. Our highest limit is 1K bytes. This is a 2325 * restriction on some ALPHA platforms with early revision 2326 * 21174 PCI chipsets, such as the AlphaPC 164lx 2327 */ 2328 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2329 #endif 2330 2331 /* Set the timer prescaler (always 66MHz) */ 2332 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2333 2334 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2335 DELAY(40); /* XXX */ 2336 2337 /* Put PHY into ready state */ 2338 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2339 DELAY(40); 2340 } 2341 2342 return 0; 2343 } 2344 2345 static int 2346 bge_blockinit(struct bge_softc *sc) 2347 { 2348 volatile struct bge_rcb *rcb; 2349 bus_size_t rcb_addr; 2350 struct ifnet * const ifp = &sc->ethercom.ec_if; 2351 bge_hostaddr taddr; 2352 uint32_t dmactl, rdmareg, mimode, val; 2353 int i, limit; 2354 2355 /* 2356 * Initialize the memory window pointer register so that 2357 * we can access the first 32K of internal NIC RAM. This will 2358 * allow us to set up the TX send ring RCBs and the RX return 2359 * ring RCBs, plus other things which live in NIC memory. 2360 */ 2361 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2362 2363 if (!BGE_IS_5705_PLUS(sc)) { 2364 /* 57XX step 33 */ 2365 /* Configure mbuf memory pool */ 2366 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2367 2368 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2369 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2370 else 2371 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2372 2373 /* 57XX step 34 */ 2374 /* Configure DMA resource pool */ 2375 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2376 BGE_DMA_DESCRIPTORS); 2377 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2378 } 2379 2380 /* 5718 step 11, 57XX step 35 */ 2381 /* 2382 * Configure mbuf pool watermarks. New broadcom docs strongly 2383 * recommend these. 2384 */ 2385 if (BGE_IS_5717_PLUS(sc)) { 2386 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2387 if (ifp->if_mtu > ETHERMTU) { 2388 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2389 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2390 } else { 2391 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2392 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2393 } 2394 } else if (BGE_IS_5705_PLUS(sc)) { 2395 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2396 2397 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2398 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2399 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2400 } else { 2401 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2402 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2403 } 2404 } else { 2405 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2406 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2407 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2408 } 2409 2410 /* 57XX step 36 */ 2411 /* Configure DMA resource watermarks */ 2412 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2413 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2414 2415 /* 5718 step 13, 57XX step 38 */ 2416 /* Enable buffer manager */ 2417 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2418 /* 2419 * Change the arbitration algorithm of TXMBUF read request to 2420 * round-robin instead of priority based for BCM5719. When 2421 * TXFIFO is almost empty, RDMA will hold its request until 2422 * TXFIFO is not almost empty. 2423 */ 2424 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2425 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2426 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2427 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2428 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2429 val |= BGE_BMANMODE_LOMBUF_ATTN; 2430 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2431 2432 /* 57XX step 39 */ 2433 /* Poll for buffer manager start indication */ 2434 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2435 DELAY(10); 2436 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2437 break; 2438 } 2439 2440 if (i == BGE_TIMEOUT * 2) { 2441 aprint_error_dev(sc->bge_dev, 2442 "buffer manager failed to start\n"); 2443 return ENXIO; 2444 } 2445 2446 /* 57XX step 40 */ 2447 /* Enable flow-through queues */ 2448 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2449 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2450 2451 /* Wait until queue initialization is complete */ 2452 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2453 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2454 break; 2455 DELAY(10); 2456 } 2457 2458 if (i == BGE_TIMEOUT * 2) { 2459 aprint_error_dev(sc->bge_dev, 2460 "flow-through queue init failed\n"); 2461 return ENXIO; 2462 } 2463 2464 /* 2465 * Summary of rings supported by the controller: 2466 * 2467 * Standard Receive Producer Ring 2468 * - This ring is used to feed receive buffers for "standard" 2469 * sized frames (typically 1536 bytes) to the controller. 2470 * 2471 * Jumbo Receive Producer Ring 2472 * - This ring is used to feed receive buffers for jumbo sized 2473 * frames (i.e. anything bigger than the "standard" frames) 2474 * to the controller. 2475 * 2476 * Mini Receive Producer Ring 2477 * - This ring is used to feed receive buffers for "mini" 2478 * sized frames to the controller. 2479 * - This feature required external memory for the controller 2480 * but was never used in a production system. Should always 2481 * be disabled. 2482 * 2483 * Receive Return Ring 2484 * - After the controller has placed an incoming frame into a 2485 * receive buffer that buffer is moved into a receive return 2486 * ring. The driver is then responsible to passing the 2487 * buffer up to the stack. Many versions of the controller 2488 * support multiple RR rings. 2489 * 2490 * Send Ring 2491 * - This ring is used for outgoing frames. Many versions of 2492 * the controller support multiple send rings. 2493 */ 2494 2495 /* 5718 step 15, 57XX step 41 */ 2496 /* Initialize the standard RX ring control block */ 2497 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2498 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2499 /* 5718 step 16 */ 2500 if (BGE_IS_57765_PLUS(sc)) { 2501 /* 2502 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2503 * Bits 15-2 : Maximum RX frame size 2504 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2505 * Bit 0 : Reserved 2506 */ 2507 rcb->bge_maxlen_flags = 2508 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2509 } else if (BGE_IS_5705_PLUS(sc)) { 2510 /* 2511 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2512 * Bits 15-2 : Reserved (should be 0) 2513 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2514 * Bit 0 : Reserved 2515 */ 2516 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2517 } else { 2518 /* 2519 * Ring size is always XXX entries 2520 * Bits 31-16: Maximum RX frame size 2521 * Bits 15-2 : Reserved (should be 0) 2522 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2523 * Bit 0 : Reserved 2524 */ 2525 rcb->bge_maxlen_flags = 2526 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2527 } 2528 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2529 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2530 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2531 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2532 else 2533 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2534 /* Write the standard receive producer ring control block. */ 2535 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2537 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2538 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2539 2540 /* Reset the standard receive producer ring producer index. */ 2541 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2542 2543 /* 57XX step 42 */ 2544 /* 2545 * Initialize the jumbo RX ring control block 2546 * We set the 'ring disabled' bit in the flags 2547 * field until we're actually ready to start 2548 * using this ring (i.e. once we set the MTU 2549 * high enough to require it). 2550 */ 2551 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2552 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2553 BGE_HOSTADDR(rcb->bge_hostaddr, 2554 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2555 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2556 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2557 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2558 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2559 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2560 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2561 else 2562 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2563 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2564 rcb->bge_hostaddr.bge_addr_hi); 2565 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2566 rcb->bge_hostaddr.bge_addr_lo); 2567 /* Program the jumbo receive producer ring RCB parameters. */ 2568 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2569 rcb->bge_maxlen_flags); 2570 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2571 /* Reset the jumbo receive producer ring producer index. */ 2572 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2573 } 2574 2575 /* 57XX step 43 */ 2576 /* Disable the mini receive producer ring RCB. */ 2577 if (BGE_IS_5700_FAMILY(sc)) { 2578 /* Set up dummy disabled mini ring RCB */ 2579 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2580 rcb->bge_maxlen_flags = 2581 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2582 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2583 rcb->bge_maxlen_flags); 2584 /* Reset the mini receive producer ring producer index. */ 2585 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2586 2587 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2588 offsetof(struct bge_ring_data, bge_info), 2589 sizeof(struct bge_gib), 2590 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2591 } 2592 2593 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2594 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2595 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2596 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2597 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2598 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2599 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2600 } 2601 /* 5718 step 14, 57XX step 44 */ 2602 /* 2603 * The BD ring replenish thresholds control how often the 2604 * hardware fetches new BD's from the producer rings in host 2605 * memory. Setting the value too low on a busy system can 2606 * starve the hardware and reduce the throughput. 2607 * 2608 * Set the BD ring replenish thresholds. The recommended 2609 * values are 1/8th the number of descriptors allocated to 2610 * each ring, but since we try to avoid filling the entire 2611 * ring we set these to the minimal value of 8. This needs to 2612 * be done on several of the supported chip revisions anyway, 2613 * to work around HW bugs. 2614 */ 2615 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2616 if (BGE_IS_JUMBO_CAPABLE(sc)) 2617 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2618 2619 /* 5718 step 18 */ 2620 if (BGE_IS_5717_PLUS(sc)) { 2621 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2622 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2623 } 2624 2625 /* 57XX step 45 */ 2626 /* 2627 * Disable all send rings by setting the 'ring disabled' bit 2628 * in the flags field of all the TX send ring control blocks, 2629 * located in NIC memory. 2630 */ 2631 if (BGE_IS_5700_FAMILY(sc)) { 2632 /* 5700 to 5704 had 16 send rings. */ 2633 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2634 } else if (BGE_IS_5717_PLUS(sc)) { 2635 limit = BGE_TX_RINGS_5717_MAX; 2636 } else if (BGE_IS_57765_FAMILY(sc) || 2637 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2638 limit = BGE_TX_RINGS_57765_MAX; 2639 } else 2640 limit = 1; 2641 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2642 for (i = 0; i < limit; i++) { 2643 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2644 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2645 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2646 rcb_addr += sizeof(struct bge_rcb); 2647 } 2648 2649 /* 57XX step 46 and 47 */ 2650 /* Configure send ring RCB 0 (we use only the first ring) */ 2651 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2652 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2653 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2654 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2655 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2656 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2657 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2658 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2659 else 2660 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2661 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2662 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2663 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2664 2665 /* 57XX step 48 */ 2666 /* 2667 * Disable all receive return rings by setting the 2668 * 'ring disabled' bit in the flags field of all the receive 2669 * return ring control blocks, located in NIC memory. 2670 */ 2671 if (BGE_IS_5717_PLUS(sc)) { 2672 /* Should be 17, use 16 until we get an SRAM map. */ 2673 limit = 16; 2674 } else if (BGE_IS_5700_FAMILY(sc)) 2675 limit = BGE_RX_RINGS_MAX; 2676 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2677 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2678 BGE_IS_57765_FAMILY(sc)) 2679 limit = 4; 2680 else 2681 limit = 1; 2682 /* Disable all receive return rings */ 2683 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2684 for (i = 0; i < limit; i++) { 2685 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2686 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2687 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2688 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2689 BGE_RCB_FLAG_RING_DISABLED)); 2690 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2691 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2692 (i * (sizeof(uint64_t))), 0); 2693 rcb_addr += sizeof(struct bge_rcb); 2694 } 2695 2696 /* 57XX step 49 */ 2697 /* 2698 * Set up receive return ring 0. Note that the NIC address 2699 * for RX return rings is 0x0. The return rings live entirely 2700 * within the host, so the nicaddr field in the RCB isn't used. 2701 */ 2702 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2703 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2704 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2705 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2706 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2707 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2708 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2709 2710 /* 5718 step 24, 57XX step 53 */ 2711 /* Set random backoff seed for TX */ 2712 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2713 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2714 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2715 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2716 BGE_TX_BACKOFF_SEED_MASK); 2717 2718 /* 5718 step 26, 57XX step 55 */ 2719 /* Set inter-packet gap */ 2720 val = 0x2620; 2721 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2722 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2723 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2724 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2725 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2726 2727 /* 5718 step 27, 57XX step 56 */ 2728 /* 2729 * Specify which ring to use for packets that don't match 2730 * any RX rules. 2731 */ 2732 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2733 2734 /* 5718 step 28, 57XX step 57 */ 2735 /* 2736 * Configure number of RX lists. One interrupt distribution 2737 * list, sixteen active lists, one bad frames class. 2738 */ 2739 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2740 2741 /* 5718 step 29, 57XX step 58 */ 2742 /* Initialize RX list placement stats mask. */ 2743 if (BGE_IS_575X_PLUS(sc)) { 2744 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2745 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2746 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2747 } else 2748 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2749 2750 /* 5718 step 30, 57XX step 59 */ 2751 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2752 2753 /* 5718 step 33, 57XX step 62 */ 2754 /* Disable host coalescing until we get it set up */ 2755 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2756 2757 /* 5718 step 34, 57XX step 63 */ 2758 /* Poll to make sure it's shut down. */ 2759 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2760 DELAY(10); 2761 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2762 break; 2763 } 2764 2765 if (i == BGE_TIMEOUT * 2) { 2766 aprint_error_dev(sc->bge_dev, 2767 "host coalescing engine failed to idle\n"); 2768 return ENXIO; 2769 } 2770 2771 /* 5718 step 35, 36, 37 */ 2772 /* Set up host coalescing defaults */ 2773 mutex_enter(sc->sc_intr_lock); 2774 const uint32_t rx_coal_ticks = sc->bge_rx_coal_ticks; 2775 const uint32_t tx_coal_ticks = sc->bge_tx_coal_ticks; 2776 const uint32_t rx_max_coal_bds = sc->bge_rx_max_coal_bds; 2777 const uint32_t tx_max_coal_bds = sc->bge_tx_max_coal_bds; 2778 mutex_exit(sc->sc_intr_lock); 2779 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_coal_ticks); 2780 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, tx_coal_ticks); 2781 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_max_coal_bds); 2782 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, tx_max_coal_bds); 2783 if (!(BGE_IS_5705_PLUS(sc))) { 2784 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2785 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2786 } 2787 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2788 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2789 2790 /* Set up address of statistics block */ 2791 if (BGE_IS_5700_FAMILY(sc)) { 2792 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2793 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2794 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2795 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2796 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2797 } 2798 2799 /* 5718 step 38 */ 2800 /* Set up address of status block */ 2801 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2802 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2803 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2804 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2805 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2806 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2807 2808 /* Set up status block size. */ 2809 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2810 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2811 val = BGE_STATBLKSZ_FULL; 2812 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2813 } else { 2814 val = BGE_STATBLKSZ_32BYTE; 2815 bzero(&sc->bge_rdata->bge_status_block, 32); 2816 } 2817 2818 /* 5718 step 39, 57XX step 73 */ 2819 /* Turn on host coalescing state machine */ 2820 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2821 2822 /* 5718 step 40, 57XX step 74 */ 2823 /* Turn on RX BD completion state machine and enable attentions */ 2824 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2825 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2826 2827 /* 5718 step 41, 57XX step 75 */ 2828 /* Turn on RX list placement state machine */ 2829 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2830 2831 /* 57XX step 76 */ 2832 /* Turn on RX list selector state machine. */ 2833 if (!(BGE_IS_5705_PLUS(sc))) 2834 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2835 2836 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2837 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2838 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2839 BGE_MACMODE_FRMHDR_DMA_ENB; 2840 2841 if (sc->bge_flags & BGEF_FIBER_TBI) 2842 val |= BGE_PORTMODE_TBI; 2843 else if (sc->bge_flags & BGEF_FIBER_MII) 2844 val |= BGE_PORTMODE_GMII; 2845 else 2846 val |= BGE_PORTMODE_MII; 2847 2848 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2849 /* Allow APE to send/receive frames. */ 2850 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2851 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2852 2853 /* Turn on DMA, clear stats */ 2854 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2855 /* 5718 step 44 */ 2856 DELAY(40); 2857 2858 /* 5718 step 45, 57XX step 79 */ 2859 /* Set misc. local control, enable interrupts on attentions */ 2860 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2861 if (BGE_IS_5717_PLUS(sc)) { 2862 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2863 /* 5718 step 46 */ 2864 DELAY(100); 2865 } 2866 2867 /* 57XX step 81 */ 2868 /* Turn on DMA completion state machine */ 2869 if (!(BGE_IS_5705_PLUS(sc))) 2870 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2871 2872 /* 5718 step 47, 57XX step 82 */ 2873 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2874 2875 /* 5718 step 48 */ 2876 /* Enable host coalescing bug fix. */ 2877 if (BGE_IS_5755_PLUS(sc)) 2878 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2879 2880 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2881 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2882 2883 /* Turn on write DMA state machine */ 2884 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2885 /* 5718 step 49 */ 2886 DELAY(40); 2887 2888 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2889 2890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2891 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2892 2893 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2894 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2895 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2896 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2897 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2898 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2899 2900 if (sc->bge_flags & BGEF_PCIE) 2901 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2902 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2903 if (ifp->if_mtu <= ETHERMTU) 2904 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2905 } 2906 if (sc->bge_flags & BGEF_TSO) { 2907 val |= BGE_RDMAMODE_TSO4_ENABLE; 2908 if (BGE_IS_5717_PLUS(sc)) 2909 val |= BGE_RDMAMODE_TSO6_ENABLE; 2910 } 2911 2912 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2913 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2914 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2915 BGE_RDMAMODE_H2BNC_VLAN_DET; 2916 /* 2917 * Allow multiple outstanding read requests from 2918 * non-LSO read DMA engine. 2919 */ 2920 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2921 } 2922 2923 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2924 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2925 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2926 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2927 BGE_IS_57765_PLUS(sc)) { 2928 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2929 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2930 else 2931 rdmareg = BGE_RDMA_RSRVCTRL; 2932 dmactl = CSR_READ_4(sc, rdmareg); 2933 /* 2934 * Adjust tx margin to prevent TX data corruption and 2935 * fix internal FIFO overflow. 2936 */ 2937 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2938 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2939 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2940 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2941 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2942 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2943 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2944 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2945 } 2946 /* 2947 * Enable fix for read DMA FIFO overruns. 2948 * The fix is to limit the number of RX BDs 2949 * the hardware would fetch at a time. 2950 */ 2951 CSR_WRITE_4(sc, rdmareg, dmactl | 2952 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2953 } 2954 2955 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2956 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2957 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2958 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2959 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2960 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2961 /* 2962 * Allow 4KB burst length reads for non-LSO frames. 2963 * Enable 512B burst length reads for buffer descriptors. 2964 */ 2965 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2966 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2967 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2968 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2969 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2970 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2971 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2972 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2973 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2974 } 2975 /* Turn on read DMA state machine */ 2976 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2977 /* 5718 step 52 */ 2978 delay(40); 2979 2980 if (sc->bge_flags & BGEF_RDMA_BUG) { 2981 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2982 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2983 if ((val & 0xFFFF) > BGE_FRAMELEN) 2984 break; 2985 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2986 break; 2987 } 2988 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2989 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2990 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2991 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2992 else 2993 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2994 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2995 } 2996 } 2997 2998 /* 5718 step 56, 57XX step 84 */ 2999 /* Turn on RX data completion state machine */ 3000 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3001 3002 /* Turn on RX data and RX BD initiator state machine */ 3003 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3004 3005 /* 57XX step 85 */ 3006 /* Turn on Mbuf cluster free state machine */ 3007 if (!BGE_IS_5705_PLUS(sc)) 3008 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3009 3010 /* 5718 step 57, 57XX step 86 */ 3011 /* Turn on send data completion state machine */ 3012 val = BGE_SDCMODE_ENABLE; 3013 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3014 val |= BGE_SDCMODE_CDELAY; 3015 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3016 3017 /* 5718 step 58 */ 3018 /* Turn on send BD completion state machine */ 3019 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3020 3021 /* 57XX step 88 */ 3022 /* Turn on RX BD initiator state machine */ 3023 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3024 3025 /* 5718 step 60, 57XX step 90 */ 3026 /* Turn on send data initiator state machine */ 3027 if (sc->bge_flags & BGEF_TSO) { 3028 /* XXX: magic value from Linux driver */ 3029 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3030 BGE_SDIMODE_HW_LSO_PRE_DMA); 3031 } else 3032 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3033 3034 /* 5718 step 61, 57XX step 91 */ 3035 /* Turn on send BD initiator state machine */ 3036 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3037 3038 /* 5718 step 62, 57XX step 92 */ 3039 /* Turn on send BD selector state machine */ 3040 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3041 3042 /* 5718 step 31, 57XX step 60 */ 3043 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3044 /* 5718 step 32, 57XX step 61 */ 3045 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3046 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3047 3048 /* ack/clear link change events */ 3049 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3050 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3051 BGE_MACSTAT_LINK_CHANGED); 3052 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3053 3054 /* 3055 * Enable attention when the link has changed state for 3056 * devices that use auto polling. 3057 */ 3058 if (sc->bge_flags & BGEF_FIBER_TBI) { 3059 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3060 } else { 3061 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3062 mimode = BGE_MIMODE_500KHZ_CONST; 3063 else 3064 mimode = BGE_MIMODE_BASE; 3065 /* 5718 step 68. 5718 step 69 (optionally). */ 3066 if (BGE_IS_5700_FAMILY(sc) || 3067 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3068 mimode |= BGE_MIMODE_AUTOPOLL; 3069 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3070 } 3071 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3072 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3073 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3074 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3075 BGE_EVTENB_MI_INTERRUPT); 3076 } 3077 3078 /* 3079 * Clear any pending link state attention. 3080 * Otherwise some link state change events may be lost until attention 3081 * is cleared by bge_intr() -> bge_link_upd() sequence. 3082 * It's not necessary on newer BCM chips - perhaps enabling link 3083 * state change attentions implies clearing pending attention. 3084 */ 3085 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3086 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3087 BGE_MACSTAT_LINK_CHANGED); 3088 3089 /* Enable link state change attentions. */ 3090 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3091 3092 return 0; 3093 } 3094 3095 static const struct bge_revision * 3096 bge_lookup_rev(uint32_t chipid) 3097 { 3098 const struct bge_revision *br; 3099 3100 for (br = bge_revisions; br->br_name != NULL; br++) { 3101 if (br->br_chipid == chipid) 3102 return br; 3103 } 3104 3105 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3106 if (br->br_chipid == BGE_ASICREV(chipid)) 3107 return br; 3108 } 3109 3110 return NULL; 3111 } 3112 3113 static const struct bge_product * 3114 bge_lookup(const struct pci_attach_args *pa) 3115 { 3116 const struct bge_product *bp; 3117 3118 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3119 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3120 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3121 return bp; 3122 } 3123 3124 return NULL; 3125 } 3126 3127 static uint32_t 3128 bge_chipid(const struct pci_attach_args *pa) 3129 { 3130 uint32_t id; 3131 3132 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3133 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3134 3135 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3136 switch (PCI_PRODUCT(pa->pa_id)) { 3137 case PCI_PRODUCT_BROADCOM_BCM5717: 3138 case PCI_PRODUCT_BROADCOM_BCM5718: 3139 case PCI_PRODUCT_BROADCOM_BCM5719: 3140 case PCI_PRODUCT_BROADCOM_BCM5720: 3141 case PCI_PRODUCT_BROADCOM_BCM5725: 3142 case PCI_PRODUCT_BROADCOM_BCM5727: 3143 case PCI_PRODUCT_BROADCOM_BCM5762: 3144 case PCI_PRODUCT_BROADCOM_BCM57764: 3145 case PCI_PRODUCT_BROADCOM_BCM57767: 3146 case PCI_PRODUCT_BROADCOM_BCM57787: 3147 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3148 BGE_PCI_GEN2_PRODID_ASICREV); 3149 break; 3150 case PCI_PRODUCT_BROADCOM_BCM57761: 3151 case PCI_PRODUCT_BROADCOM_BCM57762: 3152 case PCI_PRODUCT_BROADCOM_BCM57765: 3153 case PCI_PRODUCT_BROADCOM_BCM57766: 3154 case PCI_PRODUCT_BROADCOM_BCM57781: 3155 case PCI_PRODUCT_BROADCOM_BCM57782: 3156 case PCI_PRODUCT_BROADCOM_BCM57785: 3157 case PCI_PRODUCT_BROADCOM_BCM57786: 3158 case PCI_PRODUCT_BROADCOM_BCM57791: 3159 case PCI_PRODUCT_BROADCOM_BCM57795: 3160 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3161 BGE_PCI_GEN15_PRODID_ASICREV); 3162 break; 3163 default: 3164 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3165 BGE_PCI_PRODID_ASICREV); 3166 break; 3167 } 3168 } 3169 3170 return id; 3171 } 3172 3173 /* 3174 * Return true if MSI can be used with this device. 3175 */ 3176 static int 3177 bge_can_use_msi(struct bge_softc *sc) 3178 { 3179 int can_use_msi = 0; 3180 3181 switch (BGE_ASICREV(sc->bge_chipid)) { 3182 case BGE_ASICREV_BCM5714_A0: 3183 case BGE_ASICREV_BCM5714: 3184 /* 3185 * Apparently, MSI doesn't work when these chips are 3186 * configured in single-port mode. 3187 */ 3188 break; 3189 case BGE_ASICREV_BCM5750: 3190 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3191 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3192 can_use_msi = 1; 3193 break; 3194 default: 3195 if (BGE_IS_575X_PLUS(sc)) 3196 can_use_msi = 1; 3197 } 3198 return can_use_msi; 3199 } 3200 3201 /* 3202 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3203 * against our list and return its name if we find a match. Note 3204 * that since the Broadcom controller contains VPD support, we 3205 * can get the device name string from the controller itself instead 3206 * of the compiled-in string. This is a little slow, but it guarantees 3207 * we'll always announce the right product name. 3208 */ 3209 static int 3210 bge_probe(device_t parent, cfdata_t match, void *aux) 3211 { 3212 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3213 3214 if (bge_lookup(pa) != NULL) 3215 return 1; 3216 3217 return 0; 3218 } 3219 3220 static void 3221 bge_attach(device_t parent, device_t self, void *aux) 3222 { 3223 struct bge_softc * const sc = device_private(self); 3224 struct pci_attach_args * const pa = aux; 3225 prop_dictionary_t dict; 3226 const struct bge_product *bp; 3227 const struct bge_revision *br; 3228 pci_chipset_tag_t pc; 3229 const char *intrstr = NULL; 3230 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3231 uint32_t command; 3232 struct ifnet *ifp; 3233 struct mii_data * const mii = &sc->bge_mii; 3234 uint32_t misccfg, mimode, macmode; 3235 void * kva; 3236 u_char eaddr[ETHER_ADDR_LEN]; 3237 pcireg_t memtype, subid, reg; 3238 bus_addr_t memaddr; 3239 uint32_t pm_ctl; 3240 bool no_seeprom; 3241 int capmask, trys; 3242 int mii_flags; 3243 int map_flags; 3244 char intrbuf[PCI_INTRSTR_LEN]; 3245 3246 bp = bge_lookup(pa); 3247 KASSERT(bp != NULL); 3248 3249 sc->sc_pc = pa->pa_pc; 3250 sc->sc_pcitag = pa->pa_tag; 3251 sc->bge_dev = self; 3252 3253 sc->bge_pa = *pa; 3254 pc = sc->sc_pc; 3255 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3256 3257 aprint_naive(": Ethernet controller\n"); 3258 aprint_normal(": %s Ethernet\n", bp->bp_name); 3259 3260 /* 3261 * Map control/status registers. 3262 */ 3263 DPRINTFN(5, ("Map control/status regs\n")); 3264 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3265 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3266 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3267 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3268 3269 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3270 aprint_error_dev(sc->bge_dev, 3271 "failed to enable memory mapping!\n"); 3272 return; 3273 } 3274 3275 DPRINTFN(5, ("pci_mem_find\n")); 3276 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3277 switch (memtype) { 3278 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3279 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3280 #if 0 3281 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3282 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3283 &memaddr, &sc->bge_bsize) == 0) 3284 break; 3285 #else 3286 /* 3287 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3288 * system get NMI on boot (PR#48451). This problem might not be 3289 * the driver's bug but our PCI common part's bug. Until we 3290 * find a real reason, we ignore the prefetchable bit. 3291 */ 3292 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3293 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3294 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3295 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3296 map_flags, &sc->bge_bhandle) == 0) { 3297 sc->bge_btag = pa->pa_memt; 3298 break; 3299 } 3300 } 3301 #endif 3302 /* FALLTHROUGH */ 3303 default: 3304 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3305 return; 3306 } 3307 3308 sc->bge_txrx_stopping = false; 3309 3310 /* Save various chip information. */ 3311 sc->bge_chipid = bge_chipid(pa); 3312 sc->bge_phy_addr = bge_phy_addr(sc); 3313 3314 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3315 &sc->bge_pciecap, NULL) != 0) { 3316 /* PCIe */ 3317 sc->bge_flags |= BGEF_PCIE; 3318 /* Extract supported maximum payload size. */ 3319 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3320 sc->bge_pciecap + PCIE_DCAP); 3321 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3322 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3323 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3324 sc->bge_expmrq = 2048; 3325 else 3326 sc->bge_expmrq = 4096; 3327 bge_set_max_readrq(sc); 3328 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3329 /* PCIe without PCIe cap */ 3330 sc->bge_flags |= BGEF_PCIE; 3331 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3332 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3333 /* PCI-X */ 3334 sc->bge_flags |= BGEF_PCIX; 3335 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3336 &sc->bge_pcixcap, NULL) == 0) 3337 aprint_error_dev(sc->bge_dev, 3338 "unable to find PCIX capability\n"); 3339 } 3340 3341 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3342 /* 3343 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3344 * can clobber the chip's PCI config-space power control 3345 * registers, leaving the card in D3 powersave state. We do 3346 * not have memory-mapped registers in this state, so force 3347 * device into D0 state before starting initialization. 3348 */ 3349 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3350 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3351 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3352 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3353 DELAY(1000); /* 27 usec is allegedly sufficient */ 3354 } 3355 3356 /* Save chipset family. */ 3357 switch (BGE_ASICREV(sc->bge_chipid)) { 3358 case BGE_ASICREV_BCM5717: 3359 case BGE_ASICREV_BCM5719: 3360 case BGE_ASICREV_BCM5720: 3361 sc->bge_flags |= BGEF_5717_PLUS; 3362 /* FALLTHROUGH */ 3363 case BGE_ASICREV_BCM5762: 3364 case BGE_ASICREV_BCM57765: 3365 case BGE_ASICREV_BCM57766: 3366 if (!BGE_IS_5717_PLUS(sc)) 3367 sc->bge_flags |= BGEF_57765_FAMILY; 3368 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3369 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3370 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3371 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3372 /* 3373 * Enable work around for DMA engine miscalculation 3374 * of TXMBUF available space. 3375 */ 3376 sc->bge_flags |= BGEF_RDMA_BUG; 3377 3378 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3379 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3380 /* Jumbo frame on BCM5719 A0 does not work. */ 3381 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3382 } 3383 } 3384 break; 3385 case BGE_ASICREV_BCM5755: 3386 case BGE_ASICREV_BCM5761: 3387 case BGE_ASICREV_BCM5784: 3388 case BGE_ASICREV_BCM5785: 3389 case BGE_ASICREV_BCM5787: 3390 case BGE_ASICREV_BCM57780: 3391 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3392 break; 3393 case BGE_ASICREV_BCM5700: 3394 case BGE_ASICREV_BCM5701: 3395 case BGE_ASICREV_BCM5703: 3396 case BGE_ASICREV_BCM5704: 3397 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3398 break; 3399 case BGE_ASICREV_BCM5714_A0: 3400 case BGE_ASICREV_BCM5780: 3401 case BGE_ASICREV_BCM5714: 3402 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3403 /* FALLTHROUGH */ 3404 case BGE_ASICREV_BCM5750: 3405 case BGE_ASICREV_BCM5752: 3406 case BGE_ASICREV_BCM5906: 3407 sc->bge_flags |= BGEF_575X_PLUS; 3408 /* FALLTHROUGH */ 3409 case BGE_ASICREV_BCM5705: 3410 sc->bge_flags |= BGEF_5705_PLUS; 3411 break; 3412 } 3413 3414 /* Identify chips with APE processor. */ 3415 switch (BGE_ASICREV(sc->bge_chipid)) { 3416 case BGE_ASICREV_BCM5717: 3417 case BGE_ASICREV_BCM5719: 3418 case BGE_ASICREV_BCM5720: 3419 case BGE_ASICREV_BCM5761: 3420 case BGE_ASICREV_BCM5762: 3421 sc->bge_flags |= BGEF_APE; 3422 break; 3423 } 3424 3425 /* 3426 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3427 * not actually a MAC controller bug but an issue with the embedded 3428 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3429 */ 3430 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3431 sc->bge_flags |= BGEF_40BIT_BUG; 3432 3433 /* Chips with APE need BAR2 access for APE registers/memory. */ 3434 if ((sc->bge_flags & BGEF_APE) != 0) { 3435 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3436 #if 0 3437 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3438 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3439 &sc->bge_apesize)) { 3440 aprint_error_dev(sc->bge_dev, 3441 "couldn't map BAR2 memory\n"); 3442 return; 3443 } 3444 #else 3445 /* 3446 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3447 * system get NMI on boot (PR#48451). This problem might not be 3448 * the driver's bug but our PCI common part's bug. Until we 3449 * find a real reason, we ignore the prefetchable bit. 3450 */ 3451 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3452 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3453 aprint_error_dev(sc->bge_dev, 3454 "couldn't map BAR2 memory\n"); 3455 return; 3456 } 3457 3458 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3459 if (bus_space_map(pa->pa_memt, memaddr, 3460 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3461 aprint_error_dev(sc->bge_dev, 3462 "couldn't map BAR2 memory\n"); 3463 return; 3464 } 3465 sc->bge_apetag = pa->pa_memt; 3466 #endif 3467 3468 /* Enable APE register/memory access by host driver. */ 3469 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3470 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3471 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3472 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3473 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3474 3475 bge_ape_lock_init(sc); 3476 bge_ape_read_fw_ver(sc); 3477 } 3478 3479 /* Identify the chips that use an CPMU. */ 3480 if (BGE_IS_5717_PLUS(sc) || 3481 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3482 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3483 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3485 sc->bge_flags |= BGEF_CPMU_PRESENT; 3486 3487 /* 3488 * When using the BCM5701 in PCI-X mode, data corruption has 3489 * been observed in the first few bytes of some received packets. 3490 * Aligning the packet buffer in memory eliminates the corruption. 3491 * Unfortunately, this misaligns the packet payloads. On platforms 3492 * which do not support unaligned accesses, we will realign the 3493 * payloads by copying the received packets. 3494 */ 3495 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3496 sc->bge_flags & BGEF_PCIX) 3497 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3498 3499 if (BGE_IS_5700_FAMILY(sc)) 3500 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3501 3502 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3503 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3504 3505 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3506 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3507 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3508 sc->bge_flags |= BGEF_IS_5788; 3509 3510 /* 3511 * Some controllers seem to require a special firmware to use 3512 * TSO. But the firmware is not available to FreeBSD and Linux 3513 * claims that the TSO performed by the firmware is slower than 3514 * hardware based TSO. Moreover the firmware based TSO has one 3515 * known bug which can't handle TSO if ethernet header + IP/TCP 3516 * header is greater than 80 bytes. The workaround for the TSO 3517 * bug exist but it seems it's too expensive than not using 3518 * TSO at all. Some hardware also have the TSO bug so limit 3519 * the TSO to the controllers that are not affected TSO issues 3520 * (e.g. 5755 or higher). 3521 */ 3522 if (BGE_IS_5755_PLUS(sc)) { 3523 /* 3524 * BCM5754 and BCM5787 shares the same ASIC id so 3525 * explicit device id check is required. 3526 */ 3527 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3528 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3529 sc->bge_flags |= BGEF_TSO; 3530 /* TSO on BCM5719 A0 does not work. */ 3531 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3532 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3533 sc->bge_flags &= ~BGEF_TSO; 3534 } 3535 3536 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3537 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3538 (misccfg == 0x4000 || misccfg == 0x8000)) || 3539 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3540 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3541 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3542 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3543 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3544 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3545 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3546 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3547 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3548 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3549 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3550 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3551 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3552 /* These chips are 10/100 only. */ 3553 capmask &= ~BMSR_EXTSTAT; 3554 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3555 } 3556 3557 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3558 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3559 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3560 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3561 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3562 3563 /* Set various PHY bug flags. */ 3564 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3565 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3566 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3567 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3568 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3569 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3570 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3571 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3572 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3573 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3574 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3575 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3576 if (BGE_IS_5705_PLUS(sc) && 3577 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3578 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3579 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3580 !BGE_IS_57765_PLUS(sc)) { 3581 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3582 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3583 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3584 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3585 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3586 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3587 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3588 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3589 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3590 } else 3591 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3592 } 3593 3594 /* 3595 * SEEPROM check. 3596 * First check if firmware knows we do not have SEEPROM. 3597 */ 3598 if (prop_dictionary_get_bool(device_properties(self), 3599 "without-seeprom", &no_seeprom) && no_seeprom) 3600 sc->bge_flags |= BGEF_NO_EEPROM; 3601 3602 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3603 sc->bge_flags |= BGEF_NO_EEPROM; 3604 3605 /* Now check the 'ROM failed' bit on the RX CPU */ 3606 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3607 sc->bge_flags |= BGEF_NO_EEPROM; 3608 3609 sc->bge_asf_mode = 0; 3610 /* No ASF if APE present. */ 3611 if ((sc->bge_flags & BGEF_APE) == 0) { 3612 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3613 BGE_SRAM_DATA_SIG_MAGIC)) { 3614 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3615 BGE_HWCFG_ASF) { 3616 sc->bge_asf_mode |= ASF_ENABLE; 3617 sc->bge_asf_mode |= ASF_STACKUP; 3618 if (BGE_IS_575X_PLUS(sc)) 3619 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3620 } 3621 } 3622 } 3623 3624 int counts[PCI_INTR_TYPE_SIZE] = { 3625 [PCI_INTR_TYPE_INTX] = 1, 3626 [PCI_INTR_TYPE_MSI] = 1, 3627 [PCI_INTR_TYPE_MSIX] = 1, 3628 }; 3629 int max_type = PCI_INTR_TYPE_MSIX; 3630 3631 if (!bge_can_use_msi(sc)) { 3632 /* MSI broken, allow only INTx */ 3633 max_type = PCI_INTR_TYPE_INTX; 3634 } 3635 3636 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3637 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3638 return; 3639 } 3640 3641 DPRINTFN(5, ("pci_intr_string\n")); 3642 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3643 sizeof(intrbuf)); 3644 DPRINTFN(5, ("pci_intr_establish\n")); 3645 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3646 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3647 if (sc->bge_intrhand == NULL) { 3648 pci_intr_release(pc, sc->bge_pihp, 1); 3649 sc->bge_pihp = NULL; 3650 3651 aprint_error_dev(self, "couldn't establish interrupt"); 3652 if (intrstr != NULL) 3653 aprint_error(" at %s", intrstr); 3654 aprint_error("\n"); 3655 return; 3656 } 3657 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3658 3659 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3660 case PCI_INTR_TYPE_MSIX: 3661 case PCI_INTR_TYPE_MSI: 3662 KASSERT(bge_can_use_msi(sc)); 3663 sc->bge_flags |= BGEF_MSI; 3664 break; 3665 default: 3666 /* nothing to do */ 3667 break; 3668 } 3669 3670 char wqname[MAXCOMLEN]; 3671 snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->bge_dev)); 3672 int error = workqueue_create(&sc->sc_reset_wq, wqname, 3673 bge_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK, 3674 WQ_MPSAFE); 3675 if (error) { 3676 aprint_error_dev(sc->bge_dev, 3677 "unable to create reset workqueue\n"); 3678 return; 3679 } 3680 3681 3682 /* 3683 * All controllers except BCM5700 supports tagged status but 3684 * we use tagged status only for MSI case on BCM5717. Otherwise 3685 * MSI on BCM5717 does not work. 3686 */ 3687 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3688 sc->bge_flags |= BGEF_TAGGED_STATUS; 3689 3690 /* 3691 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3692 * lock in bge_reset(). 3693 */ 3694 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3695 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3696 delay(1000); 3697 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3698 3699 bge_stop_fw(sc); 3700 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3701 if (bge_reset(sc)) 3702 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3703 3704 /* 3705 * Read the hardware config word in the first 32k of NIC internal 3706 * memory, or fall back to the config word in the EEPROM. 3707 * Note: on some BCM5700 cards, this value appears to be unset. 3708 */ 3709 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3710 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3711 BGE_SRAM_DATA_SIG_MAGIC) { 3712 uint32_t tmp; 3713 3714 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3715 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3716 BGE_SRAM_DATA_VER_SHIFT; 3717 if ((0 < tmp) && (tmp < 0x100)) 3718 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3719 if (sc->bge_flags & BGEF_PCIE) 3720 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3721 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3722 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3723 if (BGE_IS_5717_PLUS(sc)) 3724 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3725 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3726 bge_read_eeprom(sc, (void *)&hwcfg, 3727 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3728 hwcfg = be32toh(hwcfg); 3729 } 3730 aprint_normal_dev(sc->bge_dev, 3731 "HW config %08x, %08x, %08x, %08x %08x\n", 3732 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3733 3734 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3735 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3736 3737 if (bge_chipinit(sc)) { 3738 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3739 bge_release_resources(sc); 3740 return; 3741 } 3742 3743 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3744 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3745 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3746 DELAY(100); 3747 } 3748 3749 /* Set MI_MODE */ 3750 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3751 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3752 mimode |= BGE_MIMODE_500KHZ_CONST; 3753 else 3754 mimode |= BGE_MIMODE_BASE; 3755 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3756 DELAY(80); 3757 3758 /* 3759 * Get station address from the EEPROM. 3760 */ 3761 if (bge_get_eaddr(sc, eaddr)) { 3762 aprint_error_dev(sc->bge_dev, 3763 "failed to read station address\n"); 3764 bge_release_resources(sc); 3765 return; 3766 } 3767 3768 br = bge_lookup_rev(sc->bge_chipid); 3769 3770 if (br == NULL) { 3771 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3772 sc->bge_chipid); 3773 } else { 3774 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3775 br->br_name, sc->bge_chipid); 3776 } 3777 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3778 3779 /* Allocate the general information block and ring buffers. */ 3780 if (pci_dma64_available(pa)) { 3781 sc->bge_dmatag = pa->pa_dmat64; 3782 sc->bge_dmatag32 = pa->pa_dmat; 3783 sc->bge_dma64 = true; 3784 } else { 3785 sc->bge_dmatag = pa->pa_dmat; 3786 sc->bge_dmatag32 = pa->pa_dmat; 3787 sc->bge_dma64 = false; 3788 } 3789 3790 /* 40bit DMA workaround */ 3791 if (sizeof(bus_addr_t) > 4) { 3792 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3793 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3794 3795 if (bus_dmatag_subregion(olddmatag, 0, 3796 (bus_addr_t)__MASK(40), 3797 &(sc->bge_dmatag), BUS_DMA_WAITOK) != 0) { 3798 aprint_error_dev(self, 3799 "WARNING: failed to restrict dma range," 3800 " falling back to parent bus dma range\n"); 3801 sc->bge_dmatag = olddmatag; 3802 } 3803 } 3804 } 3805 SLIST_INIT(&sc->txdma_list); 3806 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3807 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3808 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3809 &sc->bge_ring_rseg, BUS_DMA_WAITOK)) { 3810 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3811 return; 3812 } 3813 DPRINTFN(5, ("bus_dmamem_map\n")); 3814 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3815 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3816 BUS_DMA_WAITOK)) { 3817 aprint_error_dev(sc->bge_dev, 3818 "can't map DMA buffers (%zu bytes)\n", 3819 sizeof(struct bge_ring_data)); 3820 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3821 sc->bge_ring_rseg); 3822 return; 3823 } 3824 DPRINTFN(5, ("bus_dmamap_create\n")); 3825 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3826 sizeof(struct bge_ring_data), 0, 3827 BUS_DMA_WAITOK, &sc->bge_ring_map)) { 3828 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3829 bus_dmamem_unmap(sc->bge_dmatag, kva, 3830 sizeof(struct bge_ring_data)); 3831 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3832 sc->bge_ring_rseg); 3833 return; 3834 } 3835 DPRINTFN(5, ("bus_dmamap_load\n")); 3836 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3837 sizeof(struct bge_ring_data), NULL, 3838 BUS_DMA_WAITOK)) { 3839 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3840 bus_dmamem_unmap(sc->bge_dmatag, kva, 3841 sizeof(struct bge_ring_data)); 3842 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3843 sc->bge_ring_rseg); 3844 return; 3845 } 3846 3847 DPRINTFN(5, ("bzero\n")); 3848 sc->bge_rdata = (struct bge_ring_data *)kva; 3849 3850 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3851 3852 /* Try to allocate memory for jumbo buffers. */ 3853 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3854 if (bge_alloc_jumbo_mem(sc)) { 3855 aprint_error_dev(sc->bge_dev, 3856 "jumbo buffer allocation failed\n"); 3857 } else 3858 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3859 } 3860 3861 /* Set default tuneable values. */ 3862 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3863 sc->bge_rx_coal_ticks = 150; 3864 sc->bge_rx_max_coal_bds = 64; 3865 sc->bge_tx_coal_ticks = 300; 3866 sc->bge_tx_max_coal_bds = 400; 3867 if (BGE_IS_5705_PLUS(sc)) { 3868 sc->bge_tx_coal_ticks = (12 * 5); 3869 sc->bge_tx_max_coal_bds = (12 * 5); 3870 aprint_verbose_dev(sc->bge_dev, 3871 "setting short Tx thresholds\n"); 3872 } 3873 3874 if (BGE_IS_5717_PLUS(sc)) 3875 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3876 else if (BGE_IS_5705_PLUS(sc)) 3877 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3878 else 3879 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3880 3881 sc->sc_mcast_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 3882 sc->sc_intr_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 3883 3884 /* Set up ifnet structure */ 3885 ifp = &sc->ethercom.ec_if; 3886 ifp->if_softc = sc; 3887 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3888 ifp->if_extflags = IFEF_MPSAFE; 3889 ifp->if_ioctl = bge_ioctl; 3890 ifp->if_stop = bge_stop; 3891 ifp->if_start = bge_start; 3892 ifp->if_init = bge_init; 3893 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3894 IFQ_SET_READY(&ifp->if_snd); 3895 DPRINTFN(5, ("strcpy if_xname\n")); 3896 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3897 3898 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3899 sc->ethercom.ec_if.if_capabilities |= 3900 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3901 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3902 sc->ethercom.ec_if.if_capabilities |= 3903 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3904 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3905 #endif 3906 sc->ethercom.ec_capabilities |= 3907 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3908 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3909 3910 if (sc->bge_flags & BGEF_TSO) 3911 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3912 3913 /* 3914 * Do MII setup. 3915 */ 3916 DPRINTFN(5, ("mii setup\n")); 3917 mii->mii_ifp = ifp; 3918 mii->mii_readreg = bge_miibus_readreg; 3919 mii->mii_writereg = bge_miibus_writereg; 3920 mii->mii_statchg = bge_miibus_statchg; 3921 3922 /* 3923 * Figure out what sort of media we have by checking the hardware 3924 * config word. Note: on some BCM5700 cards, this value appears to be 3925 * unset. If that's the case, we have to rely on identifying the NIC 3926 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3927 * The SysKonnect SK-9D41 is a 1000baseSX card. 3928 */ 3929 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3930 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3931 if (BGE_IS_5705_PLUS(sc)) { 3932 sc->bge_flags |= BGEF_FIBER_MII; 3933 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3934 } else 3935 sc->bge_flags |= BGEF_FIBER_TBI; 3936 } 3937 3938 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3939 if (BGE_IS_JUMBO_CAPABLE(sc)) 3940 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3941 3942 /* set phyflags and chipid before mii_attach() */ 3943 dict = device_properties(self); 3944 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3945 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3946 3947 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3948 macmode &= ~BGE_MACMODE_PORTMODE; 3949 /* Initialize ifmedia structures. */ 3950 if (sc->bge_flags & BGEF_FIBER_TBI) { 3951 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3952 macmode | BGE_PORTMODE_TBI); 3953 DELAY(40); 3954 3955 struct ifmedia * const ifm = &sc->bge_ifmedia; 3956 sc->ethercom.ec_ifmedia = ifm; 3957 3958 ifmedia_init_with_lock(ifm, IFM_IMASK, 3959 bge_ifmedia_upd, bge_ifmedia_sts, sc->sc_intr_lock); 3960 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX, 0, NULL); 3961 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 3962 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 3963 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 3964 /* Pretend the user requested this setting */ 3965 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3966 } else { 3967 uint16_t phyreg; 3968 int rv; 3969 /* 3970 * Do transceiver setup and tell the firmware the 3971 * driver is down so we can try to get access the 3972 * probe if ASF is running. Retry a couple of times 3973 * if we get a conflict with the ASF firmware accessing 3974 * the PHY. 3975 */ 3976 if (sc->bge_flags & BGEF_FIBER_MII) 3977 macmode |= BGE_PORTMODE_GMII; 3978 else 3979 macmode |= BGE_PORTMODE_MII; 3980 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3981 DELAY(40); 3982 3983 /* 3984 * Do transceiver setup and tell the firmware the 3985 * driver is down so we can try to get access the 3986 * probe if ASF is running. Retry a couple of times 3987 * if we get a conflict with the ASF firmware accessing 3988 * the PHY. 3989 */ 3990 trys = 0; 3991 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3992 sc->ethercom.ec_mii = mii; 3993 ifmedia_init_with_lock(&mii->mii_media, 0, bge_ifmedia_upd, 3994 bge_ifmedia_sts, sc->sc_intr_lock); 3995 mii_flags = MIIF_DOPAUSE; 3996 if (sc->bge_flags & BGEF_FIBER_MII) 3997 mii_flags |= MIIF_HAVEFIBER; 3998 again: 3999 bge_asf_driver_up(sc); 4000 mutex_enter(sc->sc_intr_lock); 4001 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 4002 MII_BMCR, &phyreg); 4003 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 4004 int i; 4005 4006 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 4007 MII_BMCR, BMCR_RESET); 4008 /* Wait up to 500ms for it to complete. */ 4009 for (i = 0; i < 500; i++) { 4010 bge_miibus_readreg(sc->bge_dev, 4011 sc->bge_phy_addr, MII_BMCR, &phyreg); 4012 if ((phyreg & BMCR_RESET) == 0) 4013 break; 4014 DELAY(1000); 4015 } 4016 } 4017 mutex_exit(sc->sc_intr_lock); 4018 4019 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 4020 MII_OFFSET_ANY, mii_flags); 4021 4022 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 4023 goto again; 4024 4025 if (LIST_EMPTY(&mii->mii_phys)) { 4026 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4027 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 4028 0, NULL); 4029 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 4030 } else 4031 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 4032 4033 /* 4034 * Now tell the firmware we are going up after probing the PHY 4035 */ 4036 if (sc->bge_asf_mode & ASF_STACKUP) 4037 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4038 } 4039 4040 /* 4041 * Call MI attach routine. 4042 */ 4043 DPRINTFN(5, ("if_initialize\n")); 4044 if_initialize(ifp); 4045 ifp->if_percpuq = if_percpuq_create(ifp); 4046 if_deferred_start_init(ifp, NULL); 4047 if_register(ifp); 4048 4049 DPRINTFN(5, ("ether_ifattach\n")); 4050 ether_ifattach(ifp, eaddr); 4051 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4052 4053 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4054 RND_TYPE_NET, RND_FLAG_DEFAULT); 4055 #ifdef BGE_EVENT_COUNTERS 4056 /* 4057 * Attach event counters. 4058 */ 4059 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4060 NULL, device_xname(sc->bge_dev), "intr"); 4061 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4062 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4063 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4064 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4065 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4066 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4067 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4068 NULL, device_xname(sc->bge_dev), "tx_xon"); 4069 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4070 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4071 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4072 NULL, device_xname(sc->bge_dev), "rx_xon"); 4073 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4074 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4075 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4076 NULL, device_xname(sc->bge_dev), "xoffentered"); 4077 #endif /* BGE_EVENT_COUNTERS */ 4078 DPRINTFN(5, ("callout_init\n")); 4079 callout_init(&sc->bge_timeout, CALLOUT_MPSAFE); 4080 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4081 4082 if (pmf_device_register(self, NULL, NULL)) 4083 pmf_class_network_register(self, ifp); 4084 else 4085 aprint_error_dev(self, "couldn't establish power handler\n"); 4086 4087 bge_sysctl_init(sc); 4088 4089 #ifdef BGE_DEBUG 4090 bge_debug_info(sc); 4091 #endif 4092 4093 sc->bge_attached = true; 4094 } 4095 4096 /* 4097 * Stop all chip I/O so that the kernel's probe routines don't 4098 * get confused by errant DMAs when rebooting. 4099 */ 4100 static int 4101 bge_detach(device_t self, int flags __unused) 4102 { 4103 struct bge_softc * const sc = device_private(self); 4104 struct ifnet * const ifp = &sc->ethercom.ec_if; 4105 4106 if (!sc->bge_attached) 4107 return 0; 4108 4109 IFNET_LOCK(ifp); 4110 4111 /* Stop the interface. Callouts are stopped in it. */ 4112 bge_stop(ifp, 1); 4113 sc->bge_detaching = true; 4114 4115 IFNET_UNLOCK(ifp); 4116 4117 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4118 4119 ether_ifdetach(ifp); 4120 if_detach(ifp); 4121 4122 /* Delete all remaining media. */ 4123 ifmedia_fini(&sc->bge_mii.mii_media); 4124 4125 bge_release_resources(sc); 4126 4127 return 0; 4128 } 4129 4130 static void 4131 bge_release_resources(struct bge_softc *sc) 4132 { 4133 4134 /* Detach sysctl */ 4135 if (sc->bge_log != NULL) 4136 sysctl_teardown(&sc->bge_log); 4137 4138 callout_destroy(&sc->bge_timeout); 4139 4140 #ifdef BGE_EVENT_COUNTERS 4141 /* Detach event counters. */ 4142 evcnt_detach(&sc->bge_ev_intr); 4143 evcnt_detach(&sc->bge_ev_intr_spurious); 4144 evcnt_detach(&sc->bge_ev_intr_spurious2); 4145 evcnt_detach(&sc->bge_ev_tx_xoff); 4146 evcnt_detach(&sc->bge_ev_tx_xon); 4147 evcnt_detach(&sc->bge_ev_rx_xoff); 4148 evcnt_detach(&sc->bge_ev_rx_xon); 4149 evcnt_detach(&sc->bge_ev_rx_macctl); 4150 evcnt_detach(&sc->bge_ev_xoffentered); 4151 #endif /* BGE_EVENT_COUNTERS */ 4152 4153 /* Disestablish the interrupt handler */ 4154 if (sc->bge_intrhand != NULL) { 4155 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4156 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4157 sc->bge_intrhand = NULL; 4158 } 4159 4160 if (sc->bge_cdata.bge_jumbo_buf != NULL) 4161 bge_free_jumbo_mem(sc); 4162 4163 if (sc->bge_dmatag != NULL) { 4164 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4165 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4166 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4167 sizeof(struct bge_ring_data)); 4168 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4169 sc->bge_ring_rseg); 4170 } 4171 4172 /* Unmap the device registers */ 4173 if (sc->bge_bsize != 0) { 4174 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4175 sc->bge_bsize = 0; 4176 } 4177 4178 /* Unmap the APE registers */ 4179 if (sc->bge_apesize != 0) { 4180 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4181 sc->bge_apesize); 4182 sc->bge_apesize = 0; 4183 } 4184 if (sc->sc_intr_lock) { 4185 mutex_obj_free(sc->sc_intr_lock); 4186 sc->sc_intr_lock = NULL; 4187 } 4188 if (sc->sc_mcast_lock) { 4189 mutex_obj_free(sc->sc_mcast_lock); 4190 sc->sc_mcast_lock = NULL; 4191 } 4192 } 4193 4194 static int 4195 bge_reset(struct bge_softc *sc) 4196 { 4197 uint32_t cachesize, command; 4198 uint32_t reset, mac_mode, mac_mode_mask; 4199 pcireg_t devctl, reg; 4200 int i, val; 4201 void (*write_op)(struct bge_softc *, int, int); 4202 4203 /* Make mask for BGE_MAC_MODE register. */ 4204 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4205 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4206 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4207 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4208 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4209 4210 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4211 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4212 if (sc->bge_flags & BGEF_PCIE) 4213 write_op = bge_writemem_direct; 4214 else 4215 write_op = bge_writemem_ind; 4216 } else 4217 write_op = bge_writereg_ind; 4218 4219 /* 57XX step 4 */ 4220 /* Acquire the NVM lock */ 4221 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4222 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4223 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4224 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4225 for (i = 0; i < 8000; i++) { 4226 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4227 BGE_NVRAMSWARB_GNT1) 4228 break; 4229 DELAY(20); 4230 } 4231 if (i == 8000) { 4232 printf("%s: NVRAM lock timedout!\n", 4233 device_xname(sc->bge_dev)); 4234 } 4235 } 4236 4237 /* Take APE lock when performing reset. */ 4238 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4239 4240 /* 57XX step 3 */ 4241 /* Save some important PCI state. */ 4242 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4243 /* 5718 reset step 3 */ 4244 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4245 4246 /* 5718 reset step 5, 57XX step 5b-5d */ 4247 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4248 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4249 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4250 4251 /* XXX ???: Disable fastboot on controllers that support it. */ 4252 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4253 BGE_IS_5755_PLUS(sc)) 4254 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4255 4256 /* 5718 reset step 2, 57XX step 6 */ 4257 /* 4258 * Write the magic number to SRAM at offset 0xB50. 4259 * When firmware finishes its initialization it will 4260 * write ~BGE_MAGIC_NUMBER to the same location. 4261 */ 4262 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4263 4264 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4265 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4266 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4267 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4268 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4269 } 4270 4271 /* 5718 reset step 6, 57XX step 7 */ 4272 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4273 /* 4274 * XXX: from FreeBSD/Linux; no documentation 4275 */ 4276 if (sc->bge_flags & BGEF_PCIE) { 4277 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4278 !BGE_IS_57765_PLUS(sc) && 4279 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4280 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4281 /* PCI Express 1.0 system */ 4282 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4283 BGE_PHY_PCIE_SCRAM_MODE); 4284 } 4285 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4286 /* 4287 * Prevent PCI Express link training 4288 * during global reset. 4289 */ 4290 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4291 reset |= (1 << 29); 4292 } 4293 } 4294 4295 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4296 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4297 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4298 i | BGE_VCPU_STATUS_DRV_RESET); 4299 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4300 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4301 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4302 } 4303 4304 /* 4305 * Set GPHY Power Down Override to leave GPHY 4306 * powered up in D0 uninitialized. 4307 */ 4308 if (BGE_IS_5705_PLUS(sc) && 4309 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4310 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4311 4312 /* Issue global reset */ 4313 write_op(sc, BGE_MISC_CFG, reset); 4314 4315 /* 5718 reset step 7, 57XX step 8 */ 4316 if (sc->bge_flags & BGEF_PCIE) 4317 delay(100*1000); /* too big */ 4318 else 4319 delay(1000); 4320 4321 if (sc->bge_flags & BGEF_PCIE) { 4322 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4323 DELAY(500000); 4324 /* XXX: Magic Numbers */ 4325 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4326 BGE_PCI_UNKNOWN0); 4327 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4328 BGE_PCI_UNKNOWN0, 4329 reg | (1 << 15)); 4330 } 4331 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4332 sc->bge_pciecap + PCIE_DCSR); 4333 /* Clear enable no snoop and disable relaxed ordering. */ 4334 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4335 PCIE_DCSR_ENA_NO_SNOOP); 4336 4337 /* Set PCIE max payload size to 128 for older PCIe devices */ 4338 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4339 devctl &= ~(0x00e0); 4340 /* Clear device status register. Write 1b to clear */ 4341 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4342 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4343 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4344 sc->bge_pciecap + PCIE_DCSR, devctl); 4345 bge_set_max_readrq(sc); 4346 } 4347 4348 /* From Linux: dummy read to flush PCI posted writes */ 4349 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4350 4351 /* 4352 * Reset some of the PCI state that got zapped by reset 4353 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4354 * set, too. 4355 */ 4356 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4357 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4358 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4359 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4360 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4361 (sc->bge_flags & BGEF_PCIX) != 0) 4362 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4363 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4364 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4365 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4366 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4367 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4368 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4369 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4370 4371 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4372 if (sc->bge_flags & BGEF_PCIX) { 4373 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4374 + PCIX_CMD); 4375 /* Set max memory read byte count to 2K */ 4376 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4377 reg &= ~PCIX_CMD_BYTECNT_MASK; 4378 reg |= PCIX_CMD_BCNT_2048; 4379 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4380 /* 4381 * For 5704, set max outstanding split transaction 4382 * field to 0 (0 means it supports 1 request) 4383 */ 4384 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4385 | PCIX_CMD_BYTECNT_MASK); 4386 reg |= PCIX_CMD_BCNT_2048; 4387 } 4388 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4389 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4390 } 4391 4392 /* 5718 reset step 10, 57XX step 12 */ 4393 /* Enable memory arbiter. */ 4394 if (BGE_IS_5714_FAMILY(sc)) { 4395 val = CSR_READ_4(sc, BGE_MARB_MODE); 4396 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4397 } else 4398 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4399 4400 /* XXX 5721, 5751 and 5752 */ 4401 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4402 /* Step 19: */ 4403 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4404 /* Step 20: */ 4405 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4406 } 4407 4408 /* 5718 reset step 12, 57XX step 15 and 16 */ 4409 /* Fix up byte swapping */ 4410 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4411 4412 /* 5718 reset step 13, 57XX step 17 */ 4413 /* Poll until the firmware initialization is complete */ 4414 bge_poll_fw(sc); 4415 4416 /* 57XX step 21 */ 4417 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4418 pcireg_t msidata; 4419 4420 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4421 BGE_PCI_MSI_DATA); 4422 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4423 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4424 msidata); 4425 } 4426 4427 /* 57XX step 18 */ 4428 /* Write mac mode. */ 4429 val = CSR_READ_4(sc, BGE_MAC_MODE); 4430 /* Restore mac_mode_mask's bits using mac_mode */ 4431 val = (val & ~mac_mode_mask) | mac_mode; 4432 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4433 DELAY(40); 4434 4435 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4436 4437 /* 4438 * The 5704 in TBI mode apparently needs some special 4439 * adjustment to insure the SERDES drive level is set 4440 * to 1.2V. 4441 */ 4442 if (sc->bge_flags & BGEF_FIBER_TBI && 4443 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4444 uint32_t serdescfg; 4445 4446 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4447 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4448 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4449 } 4450 4451 if (sc->bge_flags & BGEF_PCIE && 4452 !BGE_IS_57765_PLUS(sc) && 4453 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4454 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4455 uint32_t v; 4456 4457 /* Enable PCI Express bug fix */ 4458 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4459 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4460 v | BGE_TLP_DATA_FIFO_PROTECT); 4461 } 4462 4463 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4464 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4465 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4466 4467 return 0; 4468 } 4469 4470 /* 4471 * Frame reception handling. This is called if there's a frame 4472 * on the receive return list. 4473 * 4474 * Note: we have to be able to handle two possibilities here: 4475 * 1) the frame is from the jumbo receive ring 4476 * 2) the frame is from the standard receive ring 4477 */ 4478 4479 static void 4480 bge_rxeof(struct bge_softc *sc) 4481 { 4482 struct ifnet * const ifp = &sc->ethercom.ec_if; 4483 uint16_t rx_prod, rx_cons; 4484 int stdcnt = 0, jumbocnt = 0; 4485 bus_dmamap_t dmamap; 4486 bus_addr_t offset, toff; 4487 bus_size_t tlen; 4488 int tosync; 4489 4490 KASSERT(mutex_owned(sc->sc_intr_lock)); 4491 4492 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4493 offsetof(struct bge_ring_data, bge_status_block), 4494 sizeof(struct bge_status_block), 4495 BUS_DMASYNC_POSTREAD); 4496 4497 rx_cons = sc->bge_rx_saved_considx; 4498 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4499 4500 /* Nothing to do */ 4501 if (rx_cons == rx_prod) 4502 return; 4503 4504 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4505 tosync = rx_prod - rx_cons; 4506 4507 if (tosync != 0) 4508 rnd_add_uint32(&sc->rnd_source, tosync); 4509 4510 toff = offset + (rx_cons * sizeof(struct bge_rx_bd)); 4511 4512 if (tosync < 0) { 4513 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4514 sizeof(struct bge_rx_bd); 4515 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4516 toff, tlen, BUS_DMASYNC_POSTREAD); 4517 tosync = rx_prod; 4518 toff = offset; 4519 } 4520 4521 if (tosync != 0) { 4522 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4523 toff, tosync * sizeof(struct bge_rx_bd), 4524 BUS_DMASYNC_POSTREAD); 4525 } 4526 4527 while (rx_cons != rx_prod) { 4528 struct bge_rx_bd *cur_rx; 4529 uint32_t rxidx; 4530 struct mbuf *m = NULL; 4531 4532 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4533 4534 rxidx = cur_rx->bge_idx; 4535 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4536 4537 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4538 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4539 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4540 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4541 jumbocnt++; 4542 bus_dmamap_sync(sc->bge_dmatag, 4543 sc->bge_cdata.bge_rx_jumbo_map, 4544 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4545 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4546 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4547 if_statinc(ifp, if_ierrors); 4548 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4549 continue; 4550 } 4551 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4552 NULL) == ENOBUFS) { 4553 if_statinc(ifp, if_ierrors); 4554 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4555 continue; 4556 } 4557 } else { 4558 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4559 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4560 4561 stdcnt++; 4562 sc->bge_std_cnt--; 4563 4564 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4565 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4566 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4567 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4568 4569 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4570 m_free(m); 4571 if_statinc(ifp, if_ierrors); 4572 continue; 4573 } 4574 } 4575 4576 #ifndef __NO_STRICT_ALIGNMENT 4577 /* 4578 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4579 * the Rx buffer has the layer-2 header unaligned. 4580 * If our CPU requires alignment, re-align by copying. 4581 */ 4582 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4583 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4584 cur_rx->bge_len); 4585 m->m_data += ETHER_ALIGN; 4586 } 4587 #endif 4588 4589 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4590 m_set_rcvif(m, ifp); 4591 4592 bge_rxcsum(sc, cur_rx, m); 4593 4594 /* 4595 * If we received a packet with a vlan tag, pass it 4596 * to vlan_input() instead of ether_input(). 4597 */ 4598 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4599 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4600 4601 if_percpuq_enqueue(ifp->if_percpuq, m); 4602 } 4603 4604 sc->bge_rx_saved_considx = rx_cons; 4605 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4606 if (stdcnt) 4607 bge_fill_rx_ring_std(sc); 4608 if (jumbocnt) 4609 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4610 } 4611 4612 static void 4613 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4614 { 4615 4616 if (BGE_IS_57765_PLUS(sc)) { 4617 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4618 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4619 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4620 if ((cur_rx->bge_error_flag & 4621 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4622 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4623 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4624 m->m_pkthdr.csum_data = 4625 cur_rx->bge_tcp_udp_csum; 4626 m->m_pkthdr.csum_flags |= 4627 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4628 } 4629 } 4630 } else { 4631 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4632 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4633 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4634 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4635 /* 4636 * Rx transport checksum-offload may also 4637 * have bugs with packets which, when transmitted, 4638 * were `runts' requiring padding. 4639 */ 4640 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4641 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4642 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4643 m->m_pkthdr.csum_data = 4644 cur_rx->bge_tcp_udp_csum; 4645 m->m_pkthdr.csum_flags |= 4646 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4647 } 4648 } 4649 } 4650 4651 static void 4652 bge_txeof(struct bge_softc *sc) 4653 { 4654 struct ifnet * const ifp = &sc->ethercom.ec_if; 4655 struct bge_tx_bd *cur_tx = NULL; 4656 struct txdmamap_pool_entry *dma; 4657 bus_addr_t offset, toff; 4658 bus_size_t tlen; 4659 int tosync; 4660 struct mbuf *m; 4661 4662 KASSERT(mutex_owned(sc->sc_intr_lock)); 4663 4664 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4665 offsetof(struct bge_ring_data, bge_status_block), 4666 sizeof(struct bge_status_block), 4667 BUS_DMASYNC_POSTREAD); 4668 4669 const uint16_t hw_cons_idx = 4670 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx; 4671 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4672 tosync = hw_cons_idx - sc->bge_tx_saved_considx; 4673 4674 if (tosync != 0) 4675 rnd_add_uint32(&sc->rnd_source, tosync); 4676 4677 toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd)); 4678 4679 if (tosync < 0) { 4680 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4681 sizeof(struct bge_tx_bd); 4682 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4683 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4684 tosync = hw_cons_idx; 4685 toff = offset; 4686 } 4687 4688 if (tosync != 0) { 4689 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4690 toff, tosync * sizeof(struct bge_tx_bd), 4691 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4692 } 4693 4694 /* 4695 * Go through our tx ring and free mbufs for those 4696 * frames that have been sent. 4697 */ 4698 while (sc->bge_tx_saved_considx != hw_cons_idx) { 4699 uint32_t idx = sc->bge_tx_saved_considx; 4700 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4701 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4702 if_statinc(ifp, if_opackets); 4703 m = sc->bge_cdata.bge_tx_chain[idx]; 4704 if (m != NULL) { 4705 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4706 dma = sc->txdma[idx]; 4707 if (dma->is_dma32) { 4708 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4709 0, dma->dmamap32->dm_mapsize, 4710 BUS_DMASYNC_POSTWRITE); 4711 bus_dmamap_unload( 4712 sc->bge_dmatag32, dma->dmamap32); 4713 } else { 4714 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4715 0, dma->dmamap->dm_mapsize, 4716 BUS_DMASYNC_POSTWRITE); 4717 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4718 } 4719 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4720 sc->txdma[idx] = NULL; 4721 4722 m_freem(m); 4723 } 4724 sc->bge_txcnt--; 4725 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4726 sc->bge_tx_sending = false; 4727 } 4728 } 4729 4730 static int 4731 bge_intr(void *xsc) 4732 { 4733 struct bge_softc * const sc = xsc; 4734 struct ifnet * const ifp = &sc->ethercom.ec_if; 4735 uint32_t pcistate, statusword, statustag; 4736 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4737 4738 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4739 if (BGE_IS_5717_PLUS(sc)) 4740 intrmask = 0; 4741 4742 mutex_enter(sc->sc_intr_lock); 4743 if (sc->bge_txrx_stopping) { 4744 mutex_exit(sc->sc_intr_lock); 4745 return 1; 4746 } 4747 4748 /* 4749 * It is possible for the interrupt to arrive before 4750 * the status block is updated prior to the interrupt. 4751 * Reading the PCI State register will confirm whether the 4752 * interrupt is ours and will flush the status block. 4753 */ 4754 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4755 4756 /* read status word from status block */ 4757 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4758 offsetof(struct bge_ring_data, bge_status_block), 4759 sizeof(struct bge_status_block), 4760 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4761 statusword = sc->bge_rdata->bge_status_block.bge_status; 4762 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4763 4764 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4765 if (sc->bge_lasttag == statustag && 4766 (~pcistate & intrmask)) { 4767 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4768 mutex_exit(sc->sc_intr_lock); 4769 return 0; 4770 } 4771 sc->bge_lasttag = statustag; 4772 } else { 4773 if (!(statusword & BGE_STATFLAG_UPDATED) && 4774 !(~pcistate & intrmask)) { 4775 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4776 mutex_exit(sc->sc_intr_lock); 4777 return 0; 4778 } 4779 statustag = 0; 4780 } 4781 /* Ack interrupt and stop others from occurring. */ 4782 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4783 BGE_EVCNT_INCR(sc->bge_ev_intr); 4784 4785 /* clear status word */ 4786 sc->bge_rdata->bge_status_block.bge_status = 0; 4787 4788 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4789 offsetof(struct bge_ring_data, bge_status_block), 4790 sizeof(struct bge_status_block), 4791 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4792 4793 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4794 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4795 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4796 bge_link_upd(sc); 4797 4798 /* Check RX return ring producer/consumer */ 4799 bge_rxeof(sc); 4800 4801 /* Check TX ring producer/consumer */ 4802 bge_txeof(sc); 4803 4804 if (sc->bge_pending_rxintr_change) { 4805 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4806 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4807 4808 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4809 DELAY(10); 4810 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4811 4812 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4813 DELAY(10); 4814 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4815 4816 sc->bge_pending_rxintr_change = false; 4817 } 4818 bge_handle_events(sc); 4819 4820 /* Re-enable interrupts. */ 4821 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4822 4823 if_schedule_deferred_start(ifp); 4824 4825 mutex_exit(sc->sc_intr_lock); 4826 4827 return 1; 4828 } 4829 4830 static void 4831 bge_asf_driver_up(struct bge_softc *sc) 4832 { 4833 if (sc->bge_asf_mode & ASF_STACKUP) { 4834 /* Send ASF heartbeat approx. every 2s */ 4835 if (sc->bge_asf_count) 4836 sc->bge_asf_count --; 4837 else { 4838 sc->bge_asf_count = 2; 4839 4840 bge_wait_for_event_ack(sc); 4841 4842 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4843 BGE_FW_CMD_DRV_ALIVE3); 4844 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4845 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4846 BGE_FW_HB_TIMEOUT_SEC); 4847 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4848 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4849 BGE_RX_CPU_DRV_EVENT); 4850 } 4851 } 4852 } 4853 4854 static void 4855 bge_tick(void *xsc) 4856 { 4857 struct bge_softc * const sc = xsc; 4858 struct ifnet * const ifp = &sc->ethercom.ec_if; 4859 struct mii_data * const mii = &sc->bge_mii; 4860 4861 mutex_enter(sc->sc_intr_lock); 4862 4863 if (BGE_IS_5705_PLUS(sc)) 4864 bge_stats_update_regs(sc); 4865 else 4866 bge_stats_update(sc); 4867 4868 if (sc->bge_flags & BGEF_FIBER_TBI) { 4869 /* 4870 * Since in TBI mode auto-polling can't be used we should poll 4871 * link status manually. Here we register pending link event 4872 * and trigger interrupt. 4873 */ 4874 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4875 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4876 } else { 4877 /* 4878 * Do not touch PHY if we have link up. This could break 4879 * IPMI/ASF mode or produce extra input errors. 4880 * (extra input errors was reported for bcm5701 & bcm5704). 4881 */ 4882 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4883 mii_tick(mii); 4884 } 4885 } 4886 4887 bge_asf_driver_up(sc); 4888 4889 const bool ok = bge_watchdog_tick(ifp); 4890 if (ok) 4891 callout_schedule(&sc->bge_timeout, hz); 4892 mutex_exit(sc->sc_intr_lock); 4893 } 4894 4895 static void 4896 bge_stats_update_regs(struct bge_softc *sc) 4897 { 4898 struct ifnet * const ifp = &sc->ethercom.ec_if; 4899 4900 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4901 4902 if_statadd_ref(ifp, nsr, if_collisions, 4903 CSR_READ_4(sc, BGE_MAC_STATS + 4904 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4905 4906 /* 4907 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4908 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4909 * (silicon bug). There's no reliable workaround so just 4910 * ignore the counter 4911 */ 4912 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4913 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4914 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4915 if_statadd_ref(ifp, nsr, if_ierrors, 4916 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4917 } 4918 if_statadd_ref(ifp, nsr, if_ierrors, 4919 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4920 if_statadd_ref(ifp, nsr, if_ierrors, 4921 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4922 4923 IF_STAT_PUTREF(ifp); 4924 4925 if (sc->bge_flags & BGEF_RDMA_BUG) { 4926 uint32_t val, ucast, mcast, bcast; 4927 4928 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4929 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4930 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4931 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4932 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4933 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4934 4935 /* 4936 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4937 * frames, it's safe to disable workaround for DMA engine's 4938 * miscalculation of TXMBUF space. 4939 */ 4940 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4941 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4942 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4943 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4944 else 4945 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4946 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4947 sc->bge_flags &= ~BGEF_RDMA_BUG; 4948 } 4949 } 4950 } 4951 4952 static void 4953 bge_stats_update(struct bge_softc *sc) 4954 { 4955 struct ifnet * const ifp = &sc->ethercom.ec_if; 4956 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4957 4958 #define READ_STAT(sc, stats, stat) \ 4959 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4960 4961 uint64_t collisions = 4962 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4963 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4964 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4965 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4966 4967 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4968 sc->bge_if_collisions = collisions; 4969 4970 4971 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4972 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4973 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4974 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4975 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4976 READ_STAT(sc, stats, 4977 xoffPauseFramesReceived.bge_addr_lo)); 4978 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4979 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4980 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4981 READ_STAT(sc, stats, 4982 macControlFramesReceived.bge_addr_lo)); 4983 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4984 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4985 4986 #undef READ_STAT 4987 } 4988 4989 /* 4990 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4991 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4992 * but when such padded frames employ the bge IP/TCP checksum offload, 4993 * the hardware checksum assist gives incorrect results (possibly 4994 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4995 * If we pad such runts with zeros, the onboard checksum comes out correct. 4996 */ 4997 static inline int 4998 bge_cksum_pad(struct mbuf *pkt) 4999 { 5000 struct mbuf *last = NULL; 5001 int padlen; 5002 5003 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 5004 5005 /* if there's only the packet-header and we can pad there, use it. */ 5006 if (pkt->m_pkthdr.len == pkt->m_len && 5007 M_TRAILINGSPACE(pkt) >= padlen) { 5008 last = pkt; 5009 } else { 5010 /* 5011 * Walk packet chain to find last mbuf. We will either 5012 * pad there, or append a new mbuf and pad it 5013 * (thus perhaps avoiding the bcm5700 dma-min bug). 5014 */ 5015 for (last = pkt; last->m_next != NULL; last = last->m_next) { 5016 continue; /* do nothing */ 5017 } 5018 5019 /* `last' now points to last in chain. */ 5020 if (M_TRAILINGSPACE(last) < padlen) { 5021 /* Allocate new empty mbuf, pad it. Compact later. */ 5022 struct mbuf *n; 5023 MGET(n, M_DONTWAIT, MT_DATA); 5024 if (n == NULL) 5025 return ENOBUFS; 5026 n->m_len = 0; 5027 last->m_next = n; 5028 last = n; 5029 } 5030 } 5031 5032 KDASSERT(!M_READONLY(last)); 5033 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 5034 5035 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 5036 memset(mtod(last, char *) + last->m_len, 0, padlen); 5037 last->m_len += padlen; 5038 pkt->m_pkthdr.len += padlen; 5039 return 0; 5040 } 5041 5042 /* 5043 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5044 */ 5045 static inline int 5046 bge_compact_dma_runt(struct mbuf *pkt) 5047 { 5048 struct mbuf *m, *prev; 5049 int totlen; 5050 5051 prev = NULL; 5052 totlen = 0; 5053 5054 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 5055 int mlen = m->m_len; 5056 int shortfall = 8 - mlen ; 5057 5058 totlen += mlen; 5059 if (mlen == 0) 5060 continue; 5061 if (mlen >= 8) 5062 continue; 5063 5064 /* 5065 * If we get here, mbuf data is too small for DMA engine. 5066 * Try to fix by shuffling data to prev or next in chain. 5067 * If that fails, do a compacting deep-copy of the whole chain. 5068 */ 5069 5070 /* Internal frag. If fits in prev, copy it there. */ 5071 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5072 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5073 prev->m_len += mlen; 5074 m->m_len = 0; 5075 /* XXX stitch chain */ 5076 prev->m_next = m_free(m); 5077 m = prev; 5078 continue; 5079 } else if (m->m_next != NULL && 5080 M_TRAILINGSPACE(m) >= shortfall && 5081 m->m_next->m_len >= (8 + shortfall)) { 5082 /* m is writable and have enough data in next, pull up. */ 5083 5084 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5085 shortfall); 5086 m->m_len += shortfall; 5087 m->m_next->m_len -= shortfall; 5088 m->m_next->m_data += shortfall; 5089 } else if (m->m_next == NULL || 1) { 5090 /* 5091 * Got a runt at the very end of the packet. 5092 * borrow data from the tail of the preceding mbuf and 5093 * update its length in-place. (The original data is 5094 * still valid, so we can do this even if prev is not 5095 * writable.) 5096 */ 5097 5098 /* 5099 * If we'd make prev a runt, just move all of its data. 5100 */ 5101 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5102 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5103 5104 if ((prev->m_len - shortfall) < 8) 5105 shortfall = prev->m_len; 5106 5107 #ifdef notyet /* just do the safe slow thing for now */ 5108 if (!M_READONLY(m)) { 5109 if (M_LEADINGSPACE(m) < shorfall) { 5110 void *m_dat; 5111 m_dat = M_BUFADDR(m); 5112 memmove(m_dat, mtod(m, void*), 5113 m->m_len); 5114 m->m_data = m_dat; 5115 } 5116 } else 5117 #endif /* just do the safe slow thing */ 5118 { 5119 struct mbuf * n = NULL; 5120 int newprevlen = prev->m_len - shortfall; 5121 5122 MGET(n, M_NOWAIT, MT_DATA); 5123 if (n == NULL) 5124 return ENOBUFS; 5125 KASSERT(m->m_len + shortfall < MLEN 5126 /*, 5127 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5128 5129 /* first copy the data we're stealing from prev */ 5130 memcpy(n->m_data, prev->m_data + newprevlen, 5131 shortfall); 5132 5133 /* update prev->m_len accordingly */ 5134 prev->m_len -= shortfall; 5135 5136 /* copy data from runt m */ 5137 memcpy(n->m_data + shortfall, m->m_data, 5138 m->m_len); 5139 5140 /* n holds what we stole from prev, plus m */ 5141 n->m_len = shortfall + m->m_len; 5142 5143 /* stitch n into chain and free m */ 5144 n->m_next = m->m_next; 5145 prev->m_next = n; 5146 /* KASSERT(m->m_next == NULL); */ 5147 m->m_next = NULL; 5148 m_free(m); 5149 m = n; /* for continuing loop */ 5150 } 5151 } 5152 } 5153 return 0; 5154 } 5155 5156 /* 5157 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5158 * pointers to descriptors. 5159 */ 5160 static int 5161 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5162 { 5163 struct bge_tx_bd *f, *prev_f; 5164 uint32_t frag, cur; 5165 uint16_t csum_flags = 0; 5166 uint16_t txbd_tso_flags = 0; 5167 struct txdmamap_pool_entry *dma; 5168 bus_dmamap_t dmamap; 5169 bus_dma_tag_t dmatag; 5170 int i = 0; 5171 int use_tso, maxsegsize, error; 5172 bool have_vtag; 5173 uint16_t vtag; 5174 bool remap; 5175 5176 KASSERT(mutex_owned(sc->sc_intr_lock)); 5177 5178 if (m_head->m_pkthdr.csum_flags) { 5179 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5180 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5181 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5182 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5183 } 5184 5185 /* 5186 * If we were asked to do an outboard checksum, and the NIC 5187 * has the bug where it sometimes adds in the Ethernet padding, 5188 * explicitly pad with zeros so the cksum will be correct either way. 5189 * (For now, do this for all chip versions, until newer 5190 * are confirmed to not require the workaround.) 5191 */ 5192 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5193 #ifdef notyet 5194 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5195 #endif 5196 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5197 goto check_dma_bug; 5198 5199 if (bge_cksum_pad(m_head) != 0) 5200 return ENOBUFS; 5201 5202 check_dma_bug: 5203 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5204 goto doit; 5205 5206 /* 5207 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5208 * less than eight bytes. If we encounter a teeny mbuf 5209 * at the end of a chain, we can pad. Otherwise, copy. 5210 */ 5211 if (bge_compact_dma_runt(m_head) != 0) 5212 return ENOBUFS; 5213 5214 doit: 5215 dma = SLIST_FIRST(&sc->txdma_list); 5216 if (dma == NULL) { 5217 return ENOBUFS; 5218 } 5219 dmamap = dma->dmamap; 5220 dmatag = sc->bge_dmatag; 5221 dma->is_dma32 = false; 5222 5223 /* 5224 * Set up any necessary TSO state before we start packing... 5225 */ 5226 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5227 if (!use_tso) { 5228 maxsegsize = 0; 5229 } else { /* TSO setup */ 5230 unsigned mss; 5231 struct ether_header *eh; 5232 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5233 unsigned bge_hlen; 5234 struct mbuf * m0 = m_head; 5235 struct ip *ip; 5236 struct tcphdr *th; 5237 int iphl, hlen; 5238 5239 /* 5240 * XXX It would be nice if the mbuf pkthdr had offset 5241 * fields for the protocol headers. 5242 */ 5243 5244 eh = mtod(m0, struct ether_header *); 5245 switch (htons(eh->ether_type)) { 5246 case ETHERTYPE_IP: 5247 offset = ETHER_HDR_LEN; 5248 break; 5249 5250 case ETHERTYPE_VLAN: 5251 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5252 break; 5253 5254 default: 5255 /* 5256 * Don't support this protocol or encapsulation. 5257 */ 5258 return ENOBUFS; 5259 } 5260 5261 /* 5262 * TCP/IP headers are in the first mbuf; we can do 5263 * this the easy way. 5264 */ 5265 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5266 hlen = iphl + offset; 5267 if (__predict_false(m0->m_len < 5268 (hlen + sizeof(struct tcphdr)))) { 5269 5270 aprint_error_dev(sc->bge_dev, 5271 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5272 "not handled yet\n", 5273 m0->m_len, hlen+ sizeof(struct tcphdr)); 5274 #ifdef NOTYET 5275 /* 5276 * XXX jonathan (at) NetBSD.org: untested. 5277 * how to force this branch to be taken? 5278 */ 5279 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5280 5281 m_copydata(m0, offset, sizeof(ip), &ip); 5282 m_copydata(m0, hlen, sizeof(th), &th); 5283 5284 ip.ip_len = 0; 5285 5286 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5287 sizeof(ip.ip_len), &ip.ip_len); 5288 5289 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5290 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5291 5292 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5293 sizeof(th.th_sum), &th.th_sum); 5294 5295 hlen += th.th_off << 2; 5296 iptcp_opt_words = hlen; 5297 #else 5298 /* 5299 * if_wm "hard" case not yet supported, can we not 5300 * mandate it out of existence? 5301 */ 5302 (void) ip; (void)th; (void) ip_tcp_hlen; 5303 5304 return ENOBUFS; 5305 #endif 5306 } else { 5307 ip = (struct ip *) (mtod(m0, char *) + offset); 5308 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5309 ip_tcp_hlen = iphl + (th->th_off << 2); 5310 5311 /* Total IP/TCP options, in 32-bit words */ 5312 iptcp_opt_words = (ip_tcp_hlen 5313 - sizeof(struct tcphdr) 5314 - sizeof(struct ip)) >> 2; 5315 } 5316 if (BGE_IS_575X_PLUS(sc)) { 5317 th->th_sum = 0; 5318 csum_flags = 0; 5319 } else { 5320 /* 5321 * XXX jonathan (at) NetBSD.org: 5705 untested. 5322 * Requires TSO firmware patch for 5701/5703/5704. 5323 */ 5324 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5325 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5326 } 5327 5328 mss = m_head->m_pkthdr.segsz; 5329 txbd_tso_flags |= 5330 BGE_TXBDFLAG_CPU_PRE_DMA | 5331 BGE_TXBDFLAG_CPU_POST_DMA; 5332 5333 /* 5334 * Our NIC TSO-assist assumes TSO has standard, optionless 5335 * IPv4 and TCP headers, which total 40 bytes. By default, 5336 * the NIC copies 40 bytes of IP/TCP header from the 5337 * supplied header into the IP/TCP header portion of 5338 * each post-TSO-segment. If the supplied packet has IP or 5339 * TCP options, we need to tell the NIC to copy those extra 5340 * bytes into each post-TSO header, in addition to the normal 5341 * 40-byte IP/TCP header (and to leave space accordingly). 5342 * Unfortunately, the driver encoding of option length 5343 * varies across different ASIC families. 5344 */ 5345 tcp_seg_flags = 0; 5346 bge_hlen = ip_tcp_hlen >> 2; 5347 if (BGE_IS_5717_PLUS(sc)) { 5348 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5349 txbd_tso_flags |= 5350 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5351 } else if (BGE_IS_5705_PLUS(sc)) { 5352 tcp_seg_flags = bge_hlen << 11; 5353 } else { 5354 /* XXX iptcp_opt_words or bge_hlen ? */ 5355 txbd_tso_flags |= iptcp_opt_words << 12; 5356 } 5357 maxsegsize = mss | tcp_seg_flags; 5358 ip->ip_len = htons(mss + ip_tcp_hlen); 5359 ip->ip_sum = 0; 5360 5361 } /* TSO setup */ 5362 5363 have_vtag = vlan_has_tag(m_head); 5364 if (have_vtag) 5365 vtag = vlan_get_tag(m_head); 5366 5367 /* 5368 * Start packing the mbufs in this chain into 5369 * the fragment pointers. Stop when we run out 5370 * of fragments or hit the end of the mbuf chain. 5371 */ 5372 remap = true; 5373 load_again: 5374 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5375 if (__predict_false(error)) { 5376 if (error == EFBIG && remap) { 5377 struct mbuf *m; 5378 remap = false; 5379 m = m_defrag(m_head, M_NOWAIT); 5380 if (m != NULL) { 5381 KASSERT(m == m_head); 5382 goto load_again; 5383 } 5384 } 5385 return error; 5386 } 5387 /* 5388 * Sanity check: avoid coming within 16 descriptors 5389 * of the end of the ring. 5390 */ 5391 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5392 BGE_TSO_PRINTF(("%s: " 5393 " dmamap_load_mbuf too close to ring wrap\n", 5394 device_xname(sc->bge_dev))); 5395 goto fail_unload; 5396 } 5397 5398 /* Iterate over dmap-map fragments. */ 5399 f = prev_f = NULL; 5400 cur = frag = *txidx; 5401 5402 for (i = 0; i < dmamap->dm_nsegs; i++) { 5403 f = &sc->bge_rdata->bge_tx_ring[frag]; 5404 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5405 break; 5406 5407 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5408 f->bge_len = dmamap->dm_segs[i].ds_len; 5409 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5410 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5411 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5412 (prev_f != NULL && 5413 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5414 ) { 5415 /* 5416 * watchdog timeout issue was observed with TSO, 5417 * limiting DMA address space to 32bits seems to 5418 * address the issue. 5419 */ 5420 bus_dmamap_unload(dmatag, dmamap); 5421 dmatag = sc->bge_dmatag32; 5422 dmamap = dma->dmamap32; 5423 dma->is_dma32 = true; 5424 remap = true; 5425 goto load_again; 5426 } 5427 5428 /* 5429 * For 5751 and follow-ons, for TSO we must turn 5430 * off checksum-assist flag in the tx-descr, and 5431 * supply the ASIC-revision-specific encoding 5432 * of TSO flags and segsize. 5433 */ 5434 if (use_tso) { 5435 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5436 f->bge_rsvd = maxsegsize; 5437 f->bge_flags = csum_flags | txbd_tso_flags; 5438 } else { 5439 f->bge_rsvd = 0; 5440 f->bge_flags = 5441 (csum_flags | txbd_tso_flags) & 0x0fff; 5442 } 5443 } else { 5444 f->bge_rsvd = 0; 5445 f->bge_flags = csum_flags; 5446 } 5447 5448 if (have_vtag) { 5449 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5450 f->bge_vlan_tag = vtag; 5451 } else { 5452 f->bge_vlan_tag = 0; 5453 } 5454 prev_f = f; 5455 cur = frag; 5456 BGE_INC(frag, BGE_TX_RING_CNT); 5457 } 5458 5459 if (i < dmamap->dm_nsegs) { 5460 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5461 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5462 goto fail_unload; 5463 } 5464 5465 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5466 BUS_DMASYNC_PREWRITE); 5467 5468 if (frag == sc->bge_tx_saved_considx) { 5469 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5470 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5471 5472 goto fail_unload; 5473 } 5474 5475 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5476 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5477 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5478 sc->txdma[cur] = dma; 5479 sc->bge_txcnt += dmamap->dm_nsegs; 5480 5481 *txidx = frag; 5482 5483 return 0; 5484 5485 fail_unload: 5486 bus_dmamap_unload(dmatag, dmamap); 5487 5488 return ENOBUFS; 5489 } 5490 5491 5492 static void 5493 bge_start(struct ifnet *ifp) 5494 { 5495 struct bge_softc * const sc = ifp->if_softc; 5496 5497 mutex_enter(sc->sc_intr_lock); 5498 if (!sc->bge_txrx_stopping) 5499 bge_start_locked(ifp); 5500 mutex_exit(sc->sc_intr_lock); 5501 } 5502 5503 /* 5504 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5505 * to the mbuf data regions directly in the transmit descriptors. 5506 */ 5507 static void 5508 bge_start_locked(struct ifnet *ifp) 5509 { 5510 struct bge_softc * const sc = ifp->if_softc; 5511 struct mbuf *m_head = NULL; 5512 struct mbuf *m; 5513 uint32_t prodidx; 5514 int pkts = 0; 5515 int error; 5516 5517 KASSERT(mutex_owned(sc->sc_intr_lock)); 5518 5519 prodidx = sc->bge_tx_prodidx; 5520 5521 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5522 IFQ_POLL(&ifp->if_snd, m_head); 5523 if (m_head == NULL) 5524 break; 5525 5526 #if 0 5527 /* 5528 * XXX 5529 * safety overkill. If this is a fragmented packet chain 5530 * with delayed TCP/UDP checksums, then only encapsulate 5531 * it if we have enough descriptors to handle the entire 5532 * chain at once. 5533 * (paranoia -- may not actually be needed) 5534 */ 5535 if (m_head->m_flags & M_FIRSTFRAG && 5536 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5537 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5538 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5539 ifp->if_flags |= IFF_OACTIVE; 5540 break; 5541 } 5542 } 5543 #endif 5544 5545 /* 5546 * Pack the data into the transmit ring. If we 5547 * don't have room, set the OACTIVE flag and wait 5548 * for the NIC to drain the ring. 5549 */ 5550 error = bge_encap(sc, m_head, &prodidx); 5551 if (__predict_false(error)) { 5552 if (SLIST_EMPTY(&sc->txdma_list)) { 5553 /* just wait for the transmit ring to drain */ 5554 break; 5555 } 5556 IFQ_DEQUEUE(&ifp->if_snd, m); 5557 KASSERT(m == m_head); 5558 m_freem(m_head); 5559 continue; 5560 } 5561 5562 /* now we are committed to transmit the packet */ 5563 IFQ_DEQUEUE(&ifp->if_snd, m); 5564 KASSERT(m == m_head); 5565 pkts++; 5566 5567 /* 5568 * If there's a BPF listener, bounce a copy of this frame 5569 * to him. 5570 */ 5571 bpf_mtap(ifp, m_head, BPF_D_OUT); 5572 } 5573 if (pkts == 0) 5574 return; 5575 5576 /* Transmit */ 5577 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5578 /* 5700 b2 errata */ 5579 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5580 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5581 5582 sc->bge_tx_prodidx = prodidx; 5583 sc->bge_tx_lastsent = time_uptime; 5584 sc->bge_tx_sending = true; 5585 } 5586 5587 static int 5588 bge_init(struct ifnet *ifp) 5589 { 5590 struct bge_softc * const sc = ifp->if_softc; 5591 const uint16_t *m; 5592 uint32_t mode, reg; 5593 int error = 0; 5594 5595 ASSERT_SLEEPABLE(); 5596 KASSERT(IFNET_LOCKED(ifp)); 5597 KASSERT(ifp == &sc->ethercom.ec_if); 5598 5599 if (sc->bge_detaching) 5600 return ENXIO; 5601 5602 /* Cancel pending I/O and flush buffers. */ 5603 bge_stop(ifp, 0); 5604 5605 bge_stop_fw(sc); 5606 bge_sig_pre_reset(sc, BGE_RESET_START); 5607 bge_reset(sc); 5608 bge_sig_legacy(sc, BGE_RESET_START); 5609 5610 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5611 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5612 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5613 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5614 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5615 5616 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5617 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5618 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5619 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5620 5621 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5622 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5623 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5624 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5625 5626 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5627 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5628 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5629 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5630 } 5631 5632 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5633 pcireg_t aercap; 5634 5635 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5636 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5637 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5638 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5639 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5640 5641 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5642 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5643 | BGE_PCIE_EIDLE_DELAY_13CLK; 5644 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5645 5646 /* Clear correctable error */ 5647 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5648 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5649 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5650 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5651 5652 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5653 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5654 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5655 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5656 } 5657 5658 bge_sig_post_reset(sc, BGE_RESET_START); 5659 5660 bge_chipinit(sc); 5661 5662 /* 5663 * Init the various state machines, ring 5664 * control blocks and firmware. 5665 */ 5666 error = bge_blockinit(sc); 5667 if (error != 0) { 5668 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5669 error); 5670 return error; 5671 } 5672 5673 /* 5718 step 25, 57XX step 54 */ 5674 /* Specify MTU. */ 5675 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5676 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5677 5678 /* 5718 step 23 */ 5679 /* Load our MAC address. */ 5680 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5681 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5682 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5683 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5684 5685 /* Enable or disable promiscuous mode as needed. */ 5686 if (ifp->if_flags & IFF_PROMISC) 5687 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5688 else 5689 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5690 5691 /* Program multicast filter. */ 5692 mutex_enter(sc->sc_mcast_lock); 5693 bge_setmulti(sc); 5694 mutex_exit(sc->sc_mcast_lock); 5695 5696 /* Init RX ring. */ 5697 bge_init_rx_ring_std(sc); 5698 5699 /* 5700 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5701 * memory to insure that the chip has in fact read the first 5702 * entry of the ring. 5703 */ 5704 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5705 u_int i; 5706 for (i = 0; i < 10; i++) { 5707 DELAY(20); 5708 uint32_t v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5709 if (v == (MCLBYTES - ETHER_ALIGN)) 5710 break; 5711 } 5712 if (i == 10) 5713 aprint_error_dev(sc->bge_dev, 5714 "5705 A0 chip failed to load RX ring\n"); 5715 } 5716 5717 /* Init jumbo RX ring. */ 5718 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5719 bge_init_rx_ring_jumbo(sc); 5720 5721 /* Init our RX return ring index */ 5722 sc->bge_rx_saved_considx = 0; 5723 5724 /* Init TX ring. */ 5725 bge_init_tx_ring(sc); 5726 5727 /* 5718 step 63, 57XX step 94 */ 5728 /* Enable TX MAC state machine lockup fix. */ 5729 mode = CSR_READ_4(sc, BGE_TX_MODE); 5730 if (BGE_IS_5755_PLUS(sc) || 5731 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5732 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5733 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5734 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5735 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5736 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5737 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5738 } 5739 5740 /* Turn on transmitter */ 5741 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5742 /* 5718 step 64 */ 5743 DELAY(100); 5744 5745 /* 5718 step 65, 57XX step 95 */ 5746 /* Turn on receiver */ 5747 mode = CSR_READ_4(sc, BGE_RX_MODE); 5748 if (BGE_IS_5755_PLUS(sc)) 5749 mode |= BGE_RXMODE_IPV6_ENABLE; 5750 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5751 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5752 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5753 /* 5718 step 66 */ 5754 DELAY(10); 5755 5756 /* 5718 step 12, 57XX step 37 */ 5757 /* 5758 * XXX Documents of 5718 series and 577xx say the recommended value 5759 * is 1, but tg3 set 1 only on 57765 series. 5760 */ 5761 if (BGE_IS_57765_PLUS(sc)) 5762 reg = 1; 5763 else 5764 reg = 2; 5765 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5766 5767 /* Tell firmware we're alive. */ 5768 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5769 5770 /* Enable host interrupts. */ 5771 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5772 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5773 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5774 5775 mutex_enter(sc->sc_intr_lock); 5776 if ((error = bge_ifmedia_upd(ifp)) == 0) { 5777 sc->bge_txrx_stopping = false; 5778 5779 /* IFNET_LOCKED asserted above */ 5780 ifp->if_flags |= IFF_RUNNING; 5781 5782 callout_schedule(&sc->bge_timeout, hz); 5783 } 5784 mutex_exit(sc->sc_intr_lock); 5785 5786 mutex_enter(sc->sc_mcast_lock); 5787 sc->bge_if_flags = ifp->if_flags; 5788 mutex_exit(sc->sc_mcast_lock); 5789 5790 return error; 5791 } 5792 5793 /* 5794 * Set media options. 5795 */ 5796 static int 5797 bge_ifmedia_upd(struct ifnet *ifp) 5798 { 5799 struct bge_softc * const sc = ifp->if_softc; 5800 struct mii_data * const mii = &sc->bge_mii; 5801 struct ifmedia * const ifm = &sc->bge_ifmedia; 5802 int rc; 5803 5804 KASSERT(mutex_owned(sc->sc_intr_lock)); 5805 5806 /* If this is a 1000baseX NIC, enable the TBI port. */ 5807 if (sc->bge_flags & BGEF_FIBER_TBI) { 5808 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5809 return EINVAL; 5810 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5811 case IFM_AUTO: 5812 /* 5813 * The BCM5704 ASIC appears to have a special 5814 * mechanism for programming the autoneg 5815 * advertisement registers in TBI mode. 5816 */ 5817 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5818 uint32_t sgdig; 5819 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5820 if (sgdig & BGE_SGDIGSTS_DONE) { 5821 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5822 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5823 sgdig |= BGE_SGDIGCFG_AUTO | 5824 BGE_SGDIGCFG_PAUSE_CAP | 5825 BGE_SGDIGCFG_ASYM_PAUSE; 5826 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5827 sgdig | BGE_SGDIGCFG_SEND); 5828 DELAY(5); 5829 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5830 sgdig); 5831 } 5832 } 5833 break; 5834 case IFM_1000_SX: 5835 if ((ifm->ifm_media & IFM_FDX) != 0) { 5836 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5837 BGE_MACMODE_HALF_DUPLEX); 5838 } else { 5839 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5840 BGE_MACMODE_HALF_DUPLEX); 5841 } 5842 DELAY(40); 5843 break; 5844 default: 5845 return EINVAL; 5846 } 5847 /* XXX 802.3x flow control for 1000BASE-SX */ 5848 return 0; 5849 } 5850 5851 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5852 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5853 uint32_t reg; 5854 5855 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5856 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5857 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5858 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5859 } 5860 } 5861 5862 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5863 if ((rc = mii_mediachg(mii)) == ENXIO) 5864 return 0; 5865 5866 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5867 uint32_t reg; 5868 5869 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5870 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5871 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5872 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5873 delay(40); 5874 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5875 } 5876 } 5877 5878 /* 5879 * Force an interrupt so that we will call bge_link_upd 5880 * if needed and clear any pending link state attention. 5881 * Without this we are not getting any further interrupts 5882 * for link state changes and thus will not UP the link and 5883 * not be able to send in bge_start. The only way to get 5884 * things working was to receive a packet and get a RX intr. 5885 */ 5886 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5887 sc->bge_flags & BGEF_IS_5788) 5888 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5889 else 5890 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5891 5892 return rc; 5893 } 5894 5895 /* 5896 * Report current media status. 5897 */ 5898 static void 5899 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5900 { 5901 struct bge_softc * const sc = ifp->if_softc; 5902 struct mii_data * const mii = &sc->bge_mii; 5903 5904 KASSERT(mutex_owned(sc->sc_intr_lock)); 5905 5906 if (sc->bge_flags & BGEF_FIBER_TBI) { 5907 ifmr->ifm_status = IFM_AVALID; 5908 ifmr->ifm_active = IFM_ETHER; 5909 if (CSR_READ_4(sc, BGE_MAC_STS) & 5910 BGE_MACSTAT_TBI_PCS_SYNCHED) 5911 ifmr->ifm_status |= IFM_ACTIVE; 5912 ifmr->ifm_active |= IFM_1000_SX; 5913 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5914 ifmr->ifm_active |= IFM_HDX; 5915 else 5916 ifmr->ifm_active |= IFM_FDX; 5917 return; 5918 } 5919 5920 mii_pollstat(mii); 5921 ifmr->ifm_status = mii->mii_media_status; 5922 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5923 sc->bge_flowflags; 5924 } 5925 5926 static int 5927 bge_ifflags_cb(struct ethercom *ec) 5928 { 5929 struct ifnet * const ifp = &ec->ec_if; 5930 struct bge_softc * const sc = ifp->if_softc; 5931 int ret = 0; 5932 5933 KASSERT(IFNET_LOCKED(ifp)); 5934 mutex_enter(sc->sc_mcast_lock); 5935 5936 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5937 sc->bge_if_flags = ifp->if_flags; 5938 5939 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 5940 ret = ENETRESET; 5941 } else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 5942 if ((ifp->if_flags & IFF_PROMISC) == 0) 5943 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5944 else 5945 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5946 5947 bge_setmulti(sc); 5948 } 5949 5950 mutex_exit(sc->sc_mcast_lock); 5951 5952 return ret; 5953 } 5954 5955 static int 5956 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5957 { 5958 struct bge_softc * const sc = ifp->if_softc; 5959 struct ifreq * const ifr = (struct ifreq *) data; 5960 int error = 0; 5961 5962 switch (command) { 5963 case SIOCADDMULTI: 5964 case SIOCDELMULTI: 5965 break; 5966 default: 5967 KASSERT(IFNET_LOCKED(ifp)); 5968 } 5969 5970 const int s = splnet(); 5971 5972 switch (command) { 5973 case SIOCSIFMEDIA: 5974 mutex_enter(sc->sc_intr_lock); 5975 /* XXX Flow control is not supported for 1000BASE-SX */ 5976 if (sc->bge_flags & BGEF_FIBER_TBI) { 5977 ifr->ifr_media &= ~IFM_ETH_FMASK; 5978 sc->bge_flowflags = 0; 5979 } 5980 5981 /* Flow control requires full-duplex mode. */ 5982 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5983 (ifr->ifr_media & IFM_FDX) == 0) { 5984 ifr->ifr_media &= ~IFM_ETH_FMASK; 5985 } 5986 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5987 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5988 /* We can do both TXPAUSE and RXPAUSE. */ 5989 ifr->ifr_media |= 5990 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5991 } 5992 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5993 } 5994 mutex_exit(sc->sc_intr_lock); 5995 5996 if (sc->bge_flags & BGEF_FIBER_TBI) { 5997 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 5998 command); 5999 } else { 6000 struct mii_data * const mii = &sc->bge_mii; 6001 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 6002 command); 6003 } 6004 break; 6005 default: 6006 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 6007 break; 6008 6009 error = 0; 6010 6011 if (command == SIOCADDMULTI || command == SIOCDELMULTI) { 6012 mutex_enter(sc->sc_mcast_lock); 6013 if (sc->bge_if_flags & IFF_RUNNING) { 6014 bge_setmulti(sc); 6015 } 6016 mutex_exit(sc->sc_mcast_lock); 6017 } 6018 break; 6019 } 6020 6021 splx(s); 6022 6023 return error; 6024 } 6025 6026 static bool 6027 bge_watchdog_check(struct bge_softc * const sc) 6028 { 6029 6030 KASSERT(mutex_owned(sc->sc_intr_lock)); 6031 6032 if (!sc->bge_tx_sending) 6033 return true; 6034 6035 if (time_uptime - sc->bge_tx_lastsent <= bge_watchdog_timeout) 6036 return true; 6037 6038 /* If pause frames are active then don't reset the hardware. */ 6039 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 6040 const uint32_t status = CSR_READ_4(sc, BGE_RX_STS); 6041 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 6042 /* 6043 * If link partner has us in XOFF state then wait for 6044 * the condition to clear. 6045 */ 6046 CSR_WRITE_4(sc, BGE_RX_STS, status); 6047 sc->bge_tx_lastsent = time_uptime; 6048 return true; 6049 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 6050 (status & BGE_RXSTAT_RCVD_XON) != 0) { 6051 /* 6052 * If link partner has us in XOFF state then wait for 6053 * the condition to clear. 6054 */ 6055 CSR_WRITE_4(sc, BGE_RX_STS, status); 6056 sc->bge_tx_lastsent = time_uptime; 6057 return true; 6058 } 6059 /* 6060 * Any other condition is unexpected and the controller 6061 * should be reset. 6062 */ 6063 } 6064 6065 return false; 6066 } 6067 6068 static bool 6069 bge_watchdog_tick(struct ifnet *ifp) 6070 { 6071 struct bge_softc * const sc = ifp->if_softc; 6072 6073 KASSERT(mutex_owned(sc->sc_intr_lock)); 6074 6075 if (!sc->sc_trigger_reset && bge_watchdog_check(sc)) 6076 return true; 6077 6078 if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0) 6079 workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL); 6080 6081 return false; 6082 } 6083 6084 /* 6085 * Perform an interface watchdog reset. 6086 */ 6087 static void 6088 bge_handle_reset_work(struct work *work, void *arg) 6089 { 6090 struct bge_softc * const sc = arg; 6091 struct ifnet * const ifp = &sc->ethercom.ec_if; 6092 6093 printf("%s: watchdog timeout -- resetting\n", ifp->if_xname); 6094 6095 /* Don't want ioctl operations to happen */ 6096 IFNET_LOCK(ifp); 6097 6098 /* reset the interface. */ 6099 bge_init(ifp); 6100 6101 IFNET_UNLOCK(ifp); 6102 6103 /* 6104 * There are still some upper layer processing which call 6105 * ifp->if_start(). e.g. ALTQ or one CPU system 6106 */ 6107 /* Try to get more packets going. */ 6108 ifp->if_start(ifp); 6109 6110 atomic_store_relaxed(&sc->sc_reset_pending, 0); 6111 } 6112 6113 static void 6114 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 6115 { 6116 int i; 6117 6118 BGE_CLRBIT_FLUSH(sc, reg, bit); 6119 6120 for (i = 0; i < 1000; i++) { 6121 delay(100); 6122 if ((CSR_READ_4(sc, reg) & bit) == 0) 6123 return; 6124 } 6125 6126 /* 6127 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 6128 * on some environment (and once after boot?) 6129 */ 6130 if (reg != BGE_SRS_MODE) 6131 aprint_error_dev(sc->bge_dev, 6132 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 6133 (u_long)reg, bit); 6134 } 6135 6136 /* 6137 * Stop the adapter and free any mbufs allocated to the 6138 * RX and TX lists. 6139 */ 6140 static void 6141 bge_stop(struct ifnet *ifp, int disable) 6142 { 6143 struct bge_softc * const sc = ifp->if_softc; 6144 6145 ASSERT_SLEEPABLE(); 6146 KASSERT(IFNET_LOCKED(ifp)); 6147 6148 mutex_enter(sc->sc_intr_lock); 6149 sc->bge_txrx_stopping = true; 6150 mutex_exit(sc->sc_intr_lock); 6151 6152 callout_halt(&sc->bge_timeout, NULL); 6153 6154 /* Disable host interrupts. */ 6155 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6156 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6157 6158 /* 6159 * Tell firmware we're shutting down. 6160 */ 6161 bge_stop_fw(sc); 6162 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6163 6164 /* 6165 * Disable all of the receiver blocks. 6166 */ 6167 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6168 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6169 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6170 if (BGE_IS_5700_FAMILY(sc)) 6171 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6172 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6173 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6174 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6175 6176 /* 6177 * Disable all of the transmit blocks. 6178 */ 6179 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6180 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6181 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6182 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6183 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6184 if (BGE_IS_5700_FAMILY(sc)) 6185 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6186 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6187 6188 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6189 delay(40); 6190 6191 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6192 6193 /* 6194 * Shut down all of the memory managers and related 6195 * state machines. 6196 */ 6197 /* 5718 step 5a,5b */ 6198 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6199 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6200 if (BGE_IS_5700_FAMILY(sc)) 6201 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6202 6203 /* 5718 step 5c,5d */ 6204 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6205 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6206 6207 if (BGE_IS_5700_FAMILY(sc)) { 6208 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6209 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6210 } 6211 6212 bge_reset(sc); 6213 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6214 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6215 6216 /* 6217 * Keep the ASF firmware running if up. 6218 */ 6219 if (sc->bge_asf_mode & ASF_STACKUP) 6220 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6221 else 6222 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6223 6224 /* Free the RX lists. */ 6225 bge_free_rx_ring_std(sc); 6226 6227 /* Free jumbo RX list. */ 6228 if (BGE_IS_JUMBO_CAPABLE(sc)) 6229 bge_free_rx_ring_jumbo(sc); 6230 6231 /* Free TX buffers. */ 6232 bge_free_tx_ring(sc, disable); 6233 6234 /* 6235 * Isolate/power down the PHY. 6236 */ 6237 if (!(sc->bge_flags & BGEF_FIBER_TBI)) { 6238 mutex_enter(sc->sc_intr_lock); 6239 mii_down(&sc->bge_mii); 6240 mutex_exit(sc->sc_intr_lock); 6241 } 6242 6243 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6244 6245 /* Clear MAC's link state (PHY may still have link UP). */ 6246 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6247 6248 ifp->if_flags &= ~IFF_RUNNING; 6249 6250 mutex_enter(sc->sc_mcast_lock); 6251 sc->bge_if_flags = ifp->if_flags; 6252 mutex_exit(sc->sc_mcast_lock); 6253 } 6254 6255 static void 6256 bge_link_upd(struct bge_softc *sc) 6257 { 6258 struct ifnet * const ifp = &sc->ethercom.ec_if; 6259 struct mii_data * const mii = &sc->bge_mii; 6260 uint32_t status; 6261 uint16_t phyval; 6262 int link; 6263 6264 KASSERT(sc->sc_intr_lock); 6265 6266 /* Clear 'pending link event' flag */ 6267 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6268 6269 /* 6270 * Process link state changes. 6271 * Grrr. The link status word in the status block does 6272 * not work correctly on the BCM5700 rev AX and BX chips, 6273 * according to all available information. Hence, we have 6274 * to enable MII interrupts in order to properly obtain 6275 * async link changes. Unfortunately, this also means that 6276 * we have to read the MAC status register to detect link 6277 * changes, thereby adding an additional register access to 6278 * the interrupt handler. 6279 */ 6280 6281 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6282 status = CSR_READ_4(sc, BGE_MAC_STS); 6283 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6284 mii_pollstat(mii); 6285 6286 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6287 mii->mii_media_status & IFM_ACTIVE && 6288 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6289 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6290 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6291 (!(mii->mii_media_status & IFM_ACTIVE) || 6292 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6293 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6294 6295 /* Clear the interrupt */ 6296 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6297 BGE_EVTENB_MI_INTERRUPT); 6298 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6299 BRGPHY_MII_ISR, &phyval); 6300 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6301 BRGPHY_MII_IMR, BRGPHY_INTRS); 6302 } 6303 return; 6304 } 6305 6306 if (sc->bge_flags & BGEF_FIBER_TBI) { 6307 status = CSR_READ_4(sc, BGE_MAC_STS); 6308 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6309 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6310 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6311 if (BGE_ASICREV(sc->bge_chipid) 6312 == BGE_ASICREV_BCM5704) { 6313 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6314 BGE_MACMODE_TBI_SEND_CFGS); 6315 DELAY(40); 6316 } 6317 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6318 if_link_state_change(ifp, LINK_STATE_UP); 6319 } 6320 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6321 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6322 if_link_state_change(ifp, LINK_STATE_DOWN); 6323 } 6324 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6325 /* 6326 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6327 * bit in status word always set. Workaround this bug by 6328 * reading PHY link status directly. 6329 */ 6330 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6331 BGE_STS_LINK : 0; 6332 6333 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6334 mii_pollstat(mii); 6335 6336 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6337 mii->mii_media_status & IFM_ACTIVE && 6338 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6339 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6340 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6341 (!(mii->mii_media_status & IFM_ACTIVE) || 6342 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6343 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6344 } 6345 } else { 6346 /* 6347 * For controllers that call mii_tick, we have to poll 6348 * link status. 6349 */ 6350 mii_pollstat(mii); 6351 } 6352 6353 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6354 uint32_t reg, scale; 6355 6356 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6357 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6358 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6359 scale = 65; 6360 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6361 scale = 6; 6362 else 6363 scale = 12; 6364 6365 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6366 ~BGE_MISCCFG_TIMER_PRESCALER; 6367 reg |= scale << 1; 6368 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6369 } 6370 /* Clear the attention */ 6371 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6372 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6373 BGE_MACSTAT_LINK_CHANGED); 6374 } 6375 6376 static int 6377 bge_sysctl_verify(SYSCTLFN_ARGS) 6378 { 6379 int error, t; 6380 struct sysctlnode node; 6381 6382 node = *rnode; 6383 t = *(int*)rnode->sysctl_data; 6384 node.sysctl_data = &t; 6385 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6386 if (error || newp == NULL) 6387 return error; 6388 6389 #if 0 6390 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6391 node.sysctl_num, rnode->sysctl_num)); 6392 #endif 6393 6394 if (node.sysctl_num == bge_rxthresh_nodenum) { 6395 if (t < 0 || t >= NBGE_RX_THRESH) 6396 return EINVAL; 6397 bge_update_all_threshes(t); 6398 } else 6399 return EINVAL; 6400 6401 *(int*)rnode->sysctl_data = t; 6402 6403 return 0; 6404 } 6405 6406 /* 6407 * Set up sysctl(3) MIB, hw.bge.*. 6408 */ 6409 static void 6410 bge_sysctl_init(struct bge_softc *sc) 6411 { 6412 int rc, bge_root_num; 6413 const struct sysctlnode *node; 6414 6415 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6416 0, CTLTYPE_NODE, "bge", 6417 SYSCTL_DESCR("BGE interface controls"), 6418 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6419 goto out; 6420 } 6421 6422 bge_root_num = node->sysctl_num; 6423 6424 /* BGE Rx interrupt mitigation level */ 6425 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6426 CTLFLAG_READWRITE, 6427 CTLTYPE_INT, "rx_lvl", 6428 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6429 bge_sysctl_verify, 0, 6430 &bge_rx_thresh_lvl, 6431 0, CTL_HW, bge_root_num, CTL_CREATE, 6432 CTL_EOL)) != 0) { 6433 goto out; 6434 } 6435 6436 bge_rxthresh_nodenum = node->sysctl_num; 6437 6438 #ifdef BGE_DEBUG 6439 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6440 CTLFLAG_READWRITE, 6441 CTLTYPE_BOOL, "trigger_reset", 6442 SYSCTL_DESCR("Trigger an interface reset"), 6443 NULL, 0, &sc->sc_trigger_reset, 0, CTL_CREATE, 6444 CTL_EOL)) != 0) { 6445 goto out; 6446 } 6447 #endif 6448 return; 6449 6450 out: 6451 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6452 } 6453 6454 #ifdef BGE_DEBUG 6455 void 6456 bge_debug_info(struct bge_softc *sc) 6457 { 6458 6459 printf("Hardware Flags:\n"); 6460 if (BGE_IS_57765_PLUS(sc)) 6461 printf(" - 57765 Plus\n"); 6462 if (BGE_IS_5717_PLUS(sc)) 6463 printf(" - 5717 Plus\n"); 6464 if (BGE_IS_5755_PLUS(sc)) 6465 printf(" - 5755 Plus\n"); 6466 if (BGE_IS_575X_PLUS(sc)) 6467 printf(" - 575X Plus\n"); 6468 if (BGE_IS_5705_PLUS(sc)) 6469 printf(" - 5705 Plus\n"); 6470 if (BGE_IS_5714_FAMILY(sc)) 6471 printf(" - 5714 Family\n"); 6472 if (BGE_IS_5700_FAMILY(sc)) 6473 printf(" - 5700 Family\n"); 6474 if (sc->bge_flags & BGEF_IS_5788) 6475 printf(" - 5788\n"); 6476 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6477 printf(" - Supports Jumbo Frames\n"); 6478 if (sc->bge_flags & BGEF_NO_EEPROM) 6479 printf(" - No EEPROM\n"); 6480 if (sc->bge_flags & BGEF_PCIX) 6481 printf(" - PCI-X Bus\n"); 6482 if (sc->bge_flags & BGEF_PCIE) 6483 printf(" - PCI Express Bus\n"); 6484 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6485 printf(" - RX Alignment Bug\n"); 6486 if (sc->bge_flags & BGEF_APE) 6487 printf(" - APE\n"); 6488 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6489 printf(" - CPMU\n"); 6490 if (sc->bge_flags & BGEF_TSO) 6491 printf(" - TSO\n"); 6492 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6493 printf(" - TAGGED_STATUS\n"); 6494 6495 /* PHY related */ 6496 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6497 printf(" - No 3 LEDs\n"); 6498 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6499 printf(" - CRC bug\n"); 6500 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6501 printf(" - ADC bug\n"); 6502 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6503 printf(" - 5704 A0 bug\n"); 6504 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6505 printf(" - jitter bug\n"); 6506 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6507 printf(" - BER bug\n"); 6508 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6509 printf(" - adjust trim\n"); 6510 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6511 printf(" - no wirespeed\n"); 6512 6513 /* ASF related */ 6514 if (sc->bge_asf_mode & ASF_ENABLE) 6515 printf(" - ASF enable\n"); 6516 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6517 printf(" - ASF new handshake\n"); 6518 if (sc->bge_asf_mode & ASF_STACKUP) 6519 printf(" - ASF stackup\n"); 6520 } 6521 #endif /* BGE_DEBUG */ 6522 6523 static int 6524 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6525 { 6526 prop_dictionary_t dict; 6527 prop_data_t ea; 6528 6529 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6530 return 1; 6531 6532 dict = device_properties(sc->bge_dev); 6533 ea = prop_dictionary_get(dict, "mac-address"); 6534 if (ea != NULL) { 6535 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6536 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6537 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6538 return 0; 6539 } 6540 6541 return 1; 6542 } 6543 6544 static int 6545 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6546 { 6547 uint32_t mac_addr; 6548 6549 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6550 if ((mac_addr >> 16) == 0x484b) { 6551 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6552 ether_addr[1] = (uint8_t)mac_addr; 6553 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6554 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6555 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6556 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6557 ether_addr[5] = (uint8_t)mac_addr; 6558 return 0; 6559 } 6560 return 1; 6561 } 6562 6563 static int 6564 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6565 { 6566 int mac_offset = BGE_EE_MAC_OFFSET; 6567 6568 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6569 mac_offset = BGE_EE_MAC_OFFSET_5906; 6570 6571 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6572 ETHER_ADDR_LEN)); 6573 } 6574 6575 static int 6576 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6577 { 6578 6579 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6580 return 1; 6581 6582 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6583 ETHER_ADDR_LEN)); 6584 } 6585 6586 static int 6587 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6588 { 6589 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6590 /* NOTE: Order is critical */ 6591 bge_get_eaddr_fw, 6592 bge_get_eaddr_mem, 6593 bge_get_eaddr_nvram, 6594 bge_get_eaddr_eeprom, 6595 NULL 6596 }; 6597 const bge_eaddr_fcn_t *func; 6598 6599 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6600 if ((*func)(sc, eaddr) == 0) 6601 break; 6602 } 6603 return *func == NULL ? ENXIO : 0; 6604 } 6605
Indexes created Wed Sep 24 05:09:52 GMT 2025