if_bge.c revision 1.398
1 /* $NetBSD: if_bge.c,v 1.398 2025/05/26 08:27:04 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.398 2025/05/26 08:27:04 bouyer Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/callout.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> 90 #include <sys/kmem.h> 91 #include <sys/mbuf.h> 92 #include <sys/rndsource.h> 93 #include <sys/socket.h> 94 #include <sys/sockio.h> 95 #include <sys/sysctl.h> 96 #include <sys/systm.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 #include <net/bpf.h> 103 104 /* Headers for TCP Segmentation Offload (TSO) */ 105 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 106 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 107 #include <netinet/ip.h> /* for struct ip */ 108 #include <netinet/tcp.h> /* for struct tcphdr */ 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 #include <dev/mii/miidevs.h> 117 #include <dev/mii/brgphyreg.h> 118 119 #include <dev/pci/if_bgereg.h> 120 #include <dev/pci/if_bgevar.h> 121 122 #include <prop/proplib.h> 123 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 127 /* 128 * Tunable thresholds for rx-side bge interrupt mitigation. 129 */ 130 131 /* 132 * The pairs of values below were obtained from empirical measurement 133 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 134 * interrupt for every N packets received, where N is, approximately, 135 * the second value (rx_max_bds) in each pair. The values are chosen 136 * such that moving from one pair to the succeeding pair was observed 137 * to roughly halve interrupt rate under sustained input packet load. 138 * The values were empirically chosen to avoid overflowing internal 139 * limits on the bcm5700: increasing rx_ticks much beyond 600 140 * results in internal wrapping and higher interrupt rates. 141 * The limit of 46 frames was chosen to match NFS workloads. 142 * 143 * These values also work well on bcm5701, bcm5704C, and (less 144 * tested) bcm5703. On other chipsets, (including the Altima chip 145 * family), the larger values may overflow internal chip limits, 146 * leading to increasing interrupt rates rather than lower interrupt 147 * rates. 148 * 149 * Applications using heavy interrupt mitigation (interrupting every 150 * 32 or 46 frames) in both directions may need to increase the TCP 151 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 152 * full link bandwidth, due to ACKs and window updates lingering 153 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 154 */ 155 static const struct bge_load_rx_thresh { 156 int rx_ticks; 157 int rx_max_bds; } 158 bge_rx_threshes[] = { 159 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 160 { 32, 2 }, 161 { 50, 4 }, 162 { 100, 8 }, 163 { 192, 16 }, 164 { 416, 32 }, 165 { 598, 46 } 166 }; 167 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 168 169 /* XXX patchable; should be sysctl'able */ 170 static int bge_auto_thresh = 1; 171 static int bge_rx_thresh_lvl; 172 173 static int bge_rxthresh_nodenum; 174 175 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 176 177 static uint32_t bge_chipid(const struct pci_attach_args *); 178 static int bge_can_use_msi(struct bge_softc *); 179 static int bge_probe(device_t, cfdata_t, void *); 180 static void bge_attach(device_t, device_t, void *); 181 static int bge_detach(device_t, int); 182 static void bge_release_resources(struct bge_softc *); 183 184 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 185 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 186 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 187 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 188 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 189 190 static void bge_txeof(struct bge_softc *); 191 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 192 static void bge_rxeof(struct bge_softc *); 193 194 static void bge_asf_driver_up (struct bge_softc *); 195 static void bge_tick(void *); 196 static void bge_stats_update(struct bge_softc *); 197 static void bge_stats_update_regs(struct bge_softc *); 198 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 199 200 static int bge_intr(void *); 201 static void bge_start(struct ifnet *); 202 static void bge_start_locked(struct ifnet *); 203 static int bge_ifflags_cb(struct ethercom *); 204 static int bge_ioctl(struct ifnet *, u_long, void *); 205 static int bge_init(struct ifnet *); 206 static void bge_stop(struct ifnet *, int); 207 static bool bge_watchdog_tick(struct ifnet *); 208 static int bge_ifmedia_upd(struct ifnet *); 209 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 210 static void bge_handle_reset_work(struct work *, void *); 211 212 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 213 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 214 215 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 216 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 217 static void bge_setmulti(struct bge_softc *); 218 219 static void bge_handle_events(struct bge_softc *); 220 static int bge_alloc_jumbo_mem(struct bge_softc *); 221 static void bge_free_jumbo_mem(struct bge_softc *); 222 static void *bge_jalloc(struct bge_softc *); 223 static void bge_jfree(struct mbuf *, void *, size_t, void *); 224 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 225 static int bge_init_rx_ring_jumbo(struct bge_softc *); 226 static void bge_free_rx_ring_jumbo(struct bge_softc *); 227 228 static int bge_newbuf_std(struct bge_softc *, int); 229 static int bge_init_rx_ring_std(struct bge_softc *); 230 static void bge_fill_rx_ring_std(struct bge_softc *); 231 static void bge_free_rx_ring_std(struct bge_softc *m); 232 233 static void bge_free_tx_ring(struct bge_softc *m, bool); 234 static int bge_init_tx_ring(struct bge_softc *); 235 236 static int bge_chipinit(struct bge_softc *); 237 static int bge_blockinit(struct bge_softc *); 238 static int bge_phy_addr(struct bge_softc *); 239 static uint32_t bge_readmem_ind(struct bge_softc *, int); 240 static void bge_writemem_ind(struct bge_softc *, int, int); 241 static void bge_writembx(struct bge_softc *, int, int); 242 static void bge_writembx_flush(struct bge_softc *, int, int); 243 static void bge_writemem_direct(struct bge_softc *, int, int); 244 static void bge_writereg_ind(struct bge_softc *, int, int); 245 static void bge_set_max_readrq(struct bge_softc *); 246 247 static int bge_miibus_readreg(device_t, int, int, uint16_t *); 248 static int bge_miibus_writereg(device_t, int, int, uint16_t); 249 static void bge_miibus_statchg(struct ifnet *); 250 251 #define BGE_RESET_SHUTDOWN 0 252 #define BGE_RESET_START 1 253 #define BGE_RESET_SUSPEND 2 254 static void bge_sig_post_reset(struct bge_softc *, int); 255 static void bge_sig_legacy(struct bge_softc *, int); 256 static void bge_sig_pre_reset(struct bge_softc *, int); 257 static void bge_wait_for_event_ack(struct bge_softc *); 258 static void bge_stop_fw(struct bge_softc *); 259 static int bge_reset(struct bge_softc *); 260 static void bge_link_upd(struct bge_softc *); 261 static void bge_sysctl_init(struct bge_softc *); 262 static int bge_sysctl_verify(SYSCTLFN_PROTO); 263 264 static void bge_ape_lock_init(struct bge_softc *); 265 static void bge_ape_read_fw_ver(struct bge_softc *); 266 static int bge_ape_lock(struct bge_softc *, int); 267 static void bge_ape_unlock(struct bge_softc *, int); 268 static void bge_ape_send_event(struct bge_softc *, uint32_t); 269 static void bge_ape_driver_state_change(struct bge_softc *, int); 270 271 #ifdef BGE_DEBUG 272 #define DPRINTF(x) if (bgedebug) printf x 273 #define DPRINTFN(n, x) if (bgedebug >= (n)) printf x 274 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 275 int bgedebug = 0; 276 int bge_tso_debug = 0; 277 void bge_debug_info(struct bge_softc *); 278 #else 279 #define DPRINTF(x) 280 #define DPRINTFN(n, x) 281 #define BGE_TSO_PRINTF(x) 282 #endif 283 284 #ifdef BGE_EVENT_COUNTERS 285 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 286 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 287 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 288 #else 289 #define BGE_EVCNT_INCR(ev) /* nothing */ 290 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 291 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 292 #endif 293 294 #define VIDDID(a, b) PCI_VENDOR_ ## a, PCI_PRODUCT_ ## a ## _ ## b 295 /* 296 * The BCM5700 documentation seems to indicate that the hardware still has the 297 * Alteon vendor ID burned into it, though it should always be overridden by 298 * the value in the EEPROM. We'll check for it anyway. 299 */ 300 static const struct bge_product { 301 pci_vendor_id_t bp_vendor; 302 pci_product_id_t bp_product; 303 const char *bp_name; 304 } bge_products[] = { 305 { VIDDID(ALTEON, BCM5700), "Broadcom BCM5700 Gigabit" }, 306 { VIDDID(ALTEON, BCM5701), "Broadcom BCM5701 Gigabit" }, 307 { VIDDID(ALTIMA, AC1000), "Altima AC1000 Gigabit" }, 308 { VIDDID(ALTIMA, AC1001), "Altima AC1001 Gigabit" }, 309 { VIDDID(ALTIMA, AC1003), "Altima AC1003 Gigabit" }, 310 { VIDDID(ALTIMA, AC9100), "Altima AC9100 Gigabit" }, 311 { VIDDID(APPLE, BCM5701), "APPLE BCM5701 Gigabit" }, 312 { VIDDID(BROADCOM, BCM5700), "Broadcom BCM5700 Gigabit" }, 313 { VIDDID(BROADCOM, BCM5701), "Broadcom BCM5701 Gigabit" }, 314 { VIDDID(BROADCOM, BCM5702), "Broadcom BCM5702 Gigabit" }, 315 { VIDDID(BROADCOM, BCM5702FE), "Broadcom BCM5702FE Fast" }, 316 { VIDDID(BROADCOM, BCM5702X), "Broadcom BCM5702X Gigabit" }, 317 { VIDDID(BROADCOM, BCM5703), "Broadcom BCM5703 Gigabit" }, 318 { VIDDID(BROADCOM, BCM5703X), "Broadcom BCM5703X Gigabit" }, 319 { VIDDID(BROADCOM, BCM5703_ALT),"Broadcom BCM5703 Gigabit" }, 320 { VIDDID(BROADCOM, BCM5704C), "Broadcom BCM5704C Dual Gigabit" }, 321 { VIDDID(BROADCOM, BCM5704S), "Broadcom BCM5704S Dual Gigabit" }, 322 { VIDDID(BROADCOM, BCM5704S_ALT),"Broadcom BCM5704S Dual Gigabit" }, 323 { VIDDID(BROADCOM, BCM5705), "Broadcom BCM5705 Gigabit" }, 324 { VIDDID(BROADCOM, BCM5705F), "Broadcom BCM5705F Gigabit" }, 325 { VIDDID(BROADCOM, BCM5705K), "Broadcom BCM5705K Gigabit" }, 326 { VIDDID(BROADCOM, BCM5705M), "Broadcom BCM5705M Gigabit" }, 327 { VIDDID(BROADCOM, BCM5705M_ALT),"Broadcom BCM5705M Gigabit" }, 328 { VIDDID(BROADCOM, BCM5714), "Broadcom BCM5714 Gigabit" }, 329 { VIDDID(BROADCOM, BCM5714S), "Broadcom BCM5714S Gigabit" }, 330 { VIDDID(BROADCOM, BCM5715), "Broadcom BCM5715 Gigabit" }, 331 { VIDDID(BROADCOM, BCM5715S), "Broadcom BCM5715S Gigabit" }, 332 { VIDDID(BROADCOM, BCM5717), "Broadcom BCM5717 Gigabit" }, 333 { VIDDID(BROADCOM, BCM5717C), "Broadcom BCM5717 Gigabit" }, 334 { VIDDID(BROADCOM, BCM5718), "Broadcom BCM5718 Gigabit" }, 335 { VIDDID(BROADCOM, BCM5719), "Broadcom BCM5719 Gigabit" }, 336 { VIDDID(BROADCOM, BCM5720), "Broadcom BCM5720 Gigabit" }, 337 { VIDDID(BROADCOM, BCM5721), "Broadcom BCM5721 Gigabit" }, 338 { VIDDID(BROADCOM, BCM5722), "Broadcom BCM5722 Gigabit" }, 339 { VIDDID(BROADCOM, BCM5723), "Broadcom BCM5723 Gigabit" }, 340 { VIDDID(BROADCOM, BCM5725), "Broadcom BCM5725 Gigabit" }, 341 { VIDDID(BROADCOM, BCM5727), "Broadcom BCM5727 Gigabit" }, 342 { VIDDID(BROADCOM, BCM5750), "Broadcom BCM5750 Gigabit" }, 343 { VIDDID(BROADCOM, BCM5751), "Broadcom BCM5751 Gigabit" }, 344 { VIDDID(BROADCOM, BCM5751F), "Broadcom BCM5751F Gigabit" }, 345 { VIDDID(BROADCOM, BCM5751M), "Broadcom BCM5751M Gigabit" }, 346 { VIDDID(BROADCOM, BCM5752), "Broadcom BCM5752 Gigabit" }, 347 { VIDDID(BROADCOM, BCM5752M), "Broadcom BCM5752M Gigabit" }, 348 { VIDDID(BROADCOM, BCM5753), "Broadcom BCM5753 Gigabit" }, 349 { VIDDID(BROADCOM, BCM5753F), "Broadcom BCM5753F Gigabit" }, 350 { VIDDID(BROADCOM, BCM5753M), "Broadcom BCM5753M Gigabit" }, 351 { VIDDID(BROADCOM, BCM5754), "Broadcom BCM5754 Gigabit" }, 352 { VIDDID(BROADCOM, BCM5754M), "Broadcom BCM5754M Gigabit" }, 353 { VIDDID(BROADCOM, BCM5755), "Broadcom BCM5755 Gigabit" }, 354 { VIDDID(BROADCOM, BCM5755M), "Broadcom BCM5755M Gigabit" }, 355 { VIDDID(BROADCOM, BCM5756), "Broadcom BCM5756 Gigabit" }, 356 { VIDDID(BROADCOM, BCM5761), "Broadcom BCM5761 Gigabit" }, 357 { VIDDID(BROADCOM, BCM5761E), "Broadcom BCM5761E Gigabit" }, 358 { VIDDID(BROADCOM, BCM5761S), "Broadcom BCM5761S Gigabit" }, 359 { VIDDID(BROADCOM, BCM5761SE), "Broadcom BCM5761SE Gigabit" }, 360 { VIDDID(BROADCOM, BCM5762), "Broadcom BCM5762 Gigabit" }, 361 { VIDDID(BROADCOM, BCM5764), "Broadcom BCM5764 Gigabit" }, 362 { VIDDID(BROADCOM, BCM5780), "Broadcom BCM5780 Gigabit" }, 363 { VIDDID(BROADCOM, BCM5780S), "Broadcom BCM5780S Gigabit" }, 364 { VIDDID(BROADCOM, BCM5781), "Broadcom BCM5781 Gigabit" }, 365 { VIDDID(BROADCOM, BCM5782), "Broadcom BCM5782 Gigabit" }, 366 { VIDDID(BROADCOM, BCM5784M), "BCM5784M NetLink 1000baseT" }, 367 { VIDDID(BROADCOM, BCM5785F), "BCM5785F NetLink 10/100" }, 368 { VIDDID(BROADCOM, BCM5785G), "BCM5785G NetLink 1000baseT" }, 369 { VIDDID(BROADCOM, BCM5786), "Broadcom BCM5786 Gigabit" }, 370 { VIDDID(BROADCOM, BCM5787), "Broadcom BCM5787 Gigabit" }, 371 { VIDDID(BROADCOM, BCM5787F), "Broadcom BCM5787F 10/100" }, 372 { VIDDID(BROADCOM, BCM5787M), "Broadcom BCM5787M Gigabit" }, 373 { VIDDID(BROADCOM, BCM5788), "Broadcom BCM5788 Gigabit" }, 374 { VIDDID(BROADCOM, BCM5789), "Broadcom BCM5789 Gigabit" }, 375 { VIDDID(BROADCOM, BCM5901), "Broadcom BCM5901 Fast" }, 376 { VIDDID(BROADCOM, BCM5901A2), "Broadcom BCM5901A2 Fast" }, 377 { VIDDID(BROADCOM, BCM5903M), "Broadcom BCM5903M Fast" }, 378 { VIDDID(BROADCOM, BCM5906), "Broadcom BCM5906 Fast" }, 379 { VIDDID(BROADCOM, BCM5906M), "Broadcom BCM5906M Fast" }, 380 { VIDDID(BROADCOM, BCM57760), "Broadcom BCM57760 Gigabit" }, 381 { VIDDID(BROADCOM, BCM57761), "Broadcom BCM57761 Gigabit" }, 382 { VIDDID(BROADCOM, BCM57762), "Broadcom BCM57762 Gigabit" }, 383 { VIDDID(BROADCOM, BCM57764), "Broadcom BCM57764 Gigabit" }, 384 { VIDDID(BROADCOM, BCM57765), "Broadcom BCM57765 Gigabit" }, 385 { VIDDID(BROADCOM, BCM57766), "Broadcom BCM57766 Gigabit" }, 386 { VIDDID(BROADCOM, BCM57767), "Broadcom BCM57767 Gigabit" }, 387 { VIDDID(BROADCOM, BCM57780), "Broadcom BCM57780 Gigabit" }, 388 { VIDDID(BROADCOM, BCM57781), "Broadcom BCM57781 Gigabit" }, 389 { VIDDID(BROADCOM, BCM57782), "Broadcom BCM57782 Gigabit" }, 390 { VIDDID(BROADCOM, BCM57785), "Broadcom BCM57785 Gigabit" }, 391 { VIDDID(BROADCOM, BCM57786), "Broadcom BCM57786 Gigabit" }, 392 { VIDDID(BROADCOM, BCM57787), "Broadcom BCM57787 Gigabit" }, 393 { VIDDID(BROADCOM, BCM57788), "Broadcom BCM57788 Gigabit" }, 394 { VIDDID(BROADCOM, BCM57790), "Broadcom BCM57790 Gigabit" }, 395 { VIDDID(BROADCOM, BCM57791), "Broadcom BCM57791 Gigabit" }, 396 { VIDDID(BROADCOM, BCM57795), "Broadcom BCM57795 Gigabit" }, 397 { VIDDID(SCHNEIDERKOCH, SK_9DX1),"SysKonnect SK-9Dx1 Gigabit" }, 398 { VIDDID(SCHNEIDERKOCH, SK_9MXX),"SysKonnect SK-9Mxx Gigabit" }, 399 { VIDDID(3COM, 3C996), "3Com 3c996 Gigabit" }, 400 { VIDDID(FUJITSU4, PW008GE4), "Fujitsu PW008GE4 Gigabit" }, 401 { VIDDID(FUJITSU4, PW008GE5), "Fujitsu PW008GE5 Gigabit" }, 402 { VIDDID(FUJITSU4, PP250_450_LAN),"Fujitsu Primepower 250/450 Gigabit" }, 403 { 0, 0, NULL }, 404 }; 405 406 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) 407 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) 408 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) 409 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) 410 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) 411 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) 412 #define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) 413 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) 414 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) 415 416 static const struct bge_revision { 417 uint32_t br_chipid; 418 const char *br_name; 419 } bge_revisions[] = { 420 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 421 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 422 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 423 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 424 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 425 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 426 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 427 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 428 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 429 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 430 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 431 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 432 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 433 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 434 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 435 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 436 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 437 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 438 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 439 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 440 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 441 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 442 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 443 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 444 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 445 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 446 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 447 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 448 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 449 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 450 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 451 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 452 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 453 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 454 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 455 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 456 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 457 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 458 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 459 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 460 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 461 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 462 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 463 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 464 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 465 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 466 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 467 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 468 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 469 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 470 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 471 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 472 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 473 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 474 { BGE_CHIPID_BCM5762_B0, "BCM5762 B0" }, 475 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 476 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 477 { BGE_CHIPID_BCM5784_B0, "BCM5784 B0" }, 478 /* 5754 and 5787 share the same ASIC ID */ 479 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 480 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 481 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 482 { BGE_CHIPID_BCM5906_A0, "BCM5906 A0" }, 483 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 484 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 485 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 486 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 487 { BGE_CHIPID_BCM57766_A0, "BCM57766 A0" }, 488 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 489 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 490 491 { 0, NULL } 492 }; 493 494 /* 495 * Some defaults for major revisions, so that newer steppings 496 * that we don't know about have a shot at working. 497 */ 498 static const struct bge_revision bge_majorrevs[] = { 499 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 500 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 501 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 502 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 503 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 504 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 505 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 506 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 507 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 508 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 509 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 510 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 511 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 512 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 513 /* 5754 and 5787 share the same ASIC ID */ 514 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 515 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 516 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 517 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 518 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 519 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 520 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 521 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 522 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 523 524 { 0, NULL } 525 }; 526 527 static int bge_allow_asf = 1; 528 529 #ifndef BGE_WATCHDOG_TIMEOUT 530 #define BGE_WATCHDOG_TIMEOUT 5 531 #endif 532 static int bge_watchdog_timeout = BGE_WATCHDOG_TIMEOUT; 533 534 535 CFATTACH_DECL3_NEW(bge, sizeof(struct bge_softc), 536 bge_probe, bge_attach, bge_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 537 538 static uint32_t 539 bge_readmem_ind(struct bge_softc *sc, int off) 540 { 541 pcireg_t val; 542 543 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 544 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 545 return 0; 546 547 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 548 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 550 return val; 551 } 552 553 static void 554 bge_writemem_ind(struct bge_softc *sc, int off, int val) 555 { 556 557 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 558 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 559 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 560 } 561 562 /* 563 * PCI Express only 564 */ 565 static void 566 bge_set_max_readrq(struct bge_softc *sc) 567 { 568 pcireg_t val; 569 570 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 571 + PCIE_DCSR); 572 val &= ~PCIE_DCSR_MAX_READ_REQ; 573 switch (sc->bge_expmrq) { 574 case 2048: 575 val |= BGE_PCIE_DEVCTL_MAX_READRQ_2048; 576 break; 577 case 4096: 578 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 579 break; 580 default: 581 panic("incorrect expmrq value(%d)", sc->bge_expmrq); 582 break; 583 } 584 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 585 + PCIE_DCSR, val); 586 } 587 588 #ifdef notdef 589 static uint32_t 590 bge_readreg_ind(struct bge_softc *sc, int off) 591 { 592 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 593 return pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA); 594 } 595 #endif 596 597 static void 598 bge_writereg_ind(struct bge_softc *sc, int off, int val) 599 { 600 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 601 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 602 } 603 604 static void 605 bge_writemem_direct(struct bge_softc *sc, int off, int val) 606 { 607 CSR_WRITE_4(sc, off, val); 608 } 609 610 static void 611 bge_writembx(struct bge_softc *sc, int off, int val) 612 { 613 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 614 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 615 616 CSR_WRITE_4(sc, off, val); 617 } 618 619 static void 620 bge_writembx_flush(struct bge_softc *sc, int off, int val) 621 { 622 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 623 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 624 625 CSR_WRITE_4_FLUSH(sc, off, val); 626 } 627 628 /* 629 * Clear all stale locks and select the lock for this driver instance. 630 */ 631 void 632 bge_ape_lock_init(struct bge_softc *sc) 633 { 634 struct pci_attach_args *pa = &(sc->bge_pa); 635 uint32_t bit, regbase; 636 int i; 637 638 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 639 regbase = BGE_APE_LOCK_GRANT; 640 else 641 regbase = BGE_APE_PER_LOCK_GRANT; 642 643 /* Clear any stale locks. */ 644 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 645 switch (i) { 646 case BGE_APE_LOCK_PHY0: 647 case BGE_APE_LOCK_PHY1: 648 case BGE_APE_LOCK_PHY2: 649 case BGE_APE_LOCK_PHY3: 650 bit = BGE_APE_LOCK_GRANT_DRIVER0; 651 break; 652 default: 653 if (pa->pa_function == 0) 654 bit = BGE_APE_LOCK_GRANT_DRIVER0; 655 else 656 bit = (1 << pa->pa_function); 657 } 658 APE_WRITE_4(sc, regbase + 4 * i, bit); 659 } 660 661 /* Select the PHY lock based on the device's function number. */ 662 switch (pa->pa_function) { 663 case 0: 664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 665 break; 666 case 1: 667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 668 break; 669 case 2: 670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 671 break; 672 case 3: 673 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 674 break; 675 default: 676 printf("%s: PHY lock not supported on function\n", 677 device_xname(sc->bge_dev)); 678 break; 679 } 680 } 681 682 /* 683 * Check for APE firmware, set flags, and print version info. 684 */ 685 void 686 bge_ape_read_fw_ver(struct bge_softc *sc) 687 { 688 const char *fwtype; 689 uint32_t apedata, features; 690 691 /* Check for a valid APE signature in shared memory. */ 692 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 693 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 694 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 695 return; 696 } 697 698 /* Check if APE firmware is running. */ 699 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 700 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 701 printf("%s: APE signature found but FW status not ready! " 702 "0x%08x\n", device_xname(sc->bge_dev), apedata); 703 return; 704 } 705 706 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 707 708 /* Fetch the APE firmware type and version. */ 709 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 710 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 711 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 712 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 713 fwtype = "NCSI"; 714 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 715 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 716 fwtype = "DASH"; 717 } else 718 fwtype = "UNKN"; 719 720 /* Print the APE firmware version. */ 721 aprint_normal_dev(sc->bge_dev, "APE firmware %s %d.%d.%d.%d\n", fwtype, 722 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 723 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 724 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 725 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 726 } 727 728 int 729 bge_ape_lock(struct bge_softc *sc, int locknum) 730 { 731 struct pci_attach_args *pa = &(sc->bge_pa); 732 uint32_t bit, gnt, req, status; 733 int i, off; 734 735 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 736 return 0; 737 738 /* Lock request/grant registers have different bases. */ 739 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 740 req = BGE_APE_LOCK_REQ; 741 gnt = BGE_APE_LOCK_GRANT; 742 } else { 743 req = BGE_APE_PER_LOCK_REQ; 744 gnt = BGE_APE_PER_LOCK_GRANT; 745 } 746 747 off = 4 * locknum; 748 749 switch (locknum) { 750 case BGE_APE_LOCK_GPIO: 751 /* Lock required when using GPIO. */ 752 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 753 return 0; 754 if (pa->pa_function == 0) 755 bit = BGE_APE_LOCK_REQ_DRIVER0; 756 else 757 bit = (1 << pa->pa_function); 758 break; 759 case BGE_APE_LOCK_GRC: 760 /* Lock required to reset the device. */ 761 if (pa->pa_function == 0) 762 bit = BGE_APE_LOCK_REQ_DRIVER0; 763 else 764 bit = (1 << pa->pa_function); 765 break; 766 case BGE_APE_LOCK_MEM: 767 /* Lock required when accessing certain APE memory. */ 768 if (pa->pa_function == 0) 769 bit = BGE_APE_LOCK_REQ_DRIVER0; 770 else 771 bit = (1 << pa->pa_function); 772 break; 773 case BGE_APE_LOCK_PHY0: 774 case BGE_APE_LOCK_PHY1: 775 case BGE_APE_LOCK_PHY2: 776 case BGE_APE_LOCK_PHY3: 777 /* Lock required when accessing PHYs. */ 778 bit = BGE_APE_LOCK_REQ_DRIVER0; 779 break; 780 default: 781 return EINVAL; 782 } 783 784 /* Request a lock. */ 785 APE_WRITE_4_FLUSH(sc, req + off, bit); 786 787 /* Wait up to 1 second to acquire lock. */ 788 for (i = 0; i < 20000; i++) { 789 status = APE_READ_4(sc, gnt + off); 790 if (status == bit) 791 break; 792 DELAY(50); 793 } 794 795 /* Handle any errors. */ 796 if (status != bit) { 797 printf("%s: APE lock %d request failed! " 798 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 799 device_xname(sc->bge_dev), 800 locknum, req + off, bit & 0xFFFF, gnt + off, 801 status & 0xFFFF); 802 /* Revoke the lock request. */ 803 APE_WRITE_4(sc, gnt + off, bit); 804 return EBUSY; 805 } 806 807 return 0; 808 } 809 810 void 811 bge_ape_unlock(struct bge_softc *sc, int locknum) 812 { 813 struct pci_attach_args *pa = &(sc->bge_pa); 814 uint32_t bit, gnt; 815 int off; 816 817 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 818 return; 819 820 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 821 gnt = BGE_APE_LOCK_GRANT; 822 else 823 gnt = BGE_APE_PER_LOCK_GRANT; 824 825 off = 4 * locknum; 826 827 switch (locknum) { 828 case BGE_APE_LOCK_GPIO: 829 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 830 return; 831 if (pa->pa_function == 0) 832 bit = BGE_APE_LOCK_GRANT_DRIVER0; 833 else 834 bit = (1 << pa->pa_function); 835 break; 836 case BGE_APE_LOCK_GRC: 837 if (pa->pa_function == 0) 838 bit = BGE_APE_LOCK_GRANT_DRIVER0; 839 else 840 bit = (1 << pa->pa_function); 841 break; 842 case BGE_APE_LOCK_MEM: 843 if (pa->pa_function == 0) 844 bit = BGE_APE_LOCK_GRANT_DRIVER0; 845 else 846 bit = (1 << pa->pa_function); 847 break; 848 case BGE_APE_LOCK_PHY0: 849 case BGE_APE_LOCK_PHY1: 850 case BGE_APE_LOCK_PHY2: 851 case BGE_APE_LOCK_PHY3: 852 bit = BGE_APE_LOCK_GRANT_DRIVER0; 853 break; 854 default: 855 return; 856 } 857 858 /* Write and flush for consecutive bge_ape_lock() */ 859 APE_WRITE_4_FLUSH(sc, gnt + off, bit); 860 } 861 862 /* 863 * Send an event to the APE firmware. 864 */ 865 void 866 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 867 { 868 uint32_t apedata; 869 int i; 870 871 /* NCSI does not support APE events. */ 872 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 873 return; 874 875 /* Wait up to 1ms for APE to service previous event. */ 876 for (i = 10; i > 0; i--) { 877 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 878 break; 879 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 880 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 881 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 882 BGE_APE_EVENT_STATUS_EVENT_PENDING); 883 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 884 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 885 break; 886 } 887 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 888 DELAY(100); 889 } 890 if (i == 0) { 891 printf("%s: APE event 0x%08x send timed out\n", 892 device_xname(sc->bge_dev), event); 893 } 894 } 895 896 void 897 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 898 { 899 uint32_t apedata, event; 900 901 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 902 return; 903 904 switch (kind) { 905 case BGE_RESET_START: 906 /* If this is the first load, clear the load counter. */ 907 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 908 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 909 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 910 else { 911 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 912 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 913 } 914 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 915 BGE_APE_HOST_SEG_SIG_MAGIC); 916 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 917 BGE_APE_HOST_SEG_LEN_MAGIC); 918 919 /* Add some version info if bge(4) supports it. */ 920 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 921 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 922 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 923 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 924 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 925 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 926 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 927 BGE_APE_HOST_DRVR_STATE_START); 928 event = BGE_APE_EVENT_STATUS_STATE_START; 929 break; 930 case BGE_RESET_SHUTDOWN: 931 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 932 BGE_APE_HOST_DRVR_STATE_UNLOAD); 933 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 934 break; 935 case BGE_RESET_SUSPEND: 936 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 937 break; 938 default: 939 return; 940 } 941 942 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 943 BGE_APE_EVENT_STATUS_STATE_CHNGE); 944 } 945 946 static uint8_t 947 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 948 { 949 uint32_t access, byte = 0; 950 int i; 951 952 /* Lock. */ 953 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 954 for (i = 0; i < 8000; i++) { 955 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 956 break; 957 DELAY(20); 958 } 959 if (i == 8000) 960 return 1; 961 962 /* Enable access. */ 963 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 964 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 965 966 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 967 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 968 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 969 DELAY(10); 970 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 971 DELAY(10); 972 break; 973 } 974 } 975 976 if (i == BGE_TIMEOUT * 10) { 977 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 978 return 1; 979 } 980 981 /* Get result. */ 982 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 983 984 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 985 986 /* Disable access. */ 987 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 988 989 /* Unlock. */ 990 CSR_WRITE_4_FLUSH(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 991 992 return 0; 993 } 994 995 /* 996 * Read a sequence of bytes from NVRAM. 997 */ 998 static int 999 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 1000 { 1001 int error = 0, i; 1002 uint8_t byte = 0; 1003 1004 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 1005 return 1; 1006 1007 for (i = 0; i < cnt; i++) { 1008 error = bge_nvram_getbyte(sc, off + i, &byte); 1009 if (error) 1010 break; 1011 *(dest + i) = byte; 1012 } 1013 1014 return error ? 1 : 0; 1015 } 1016 1017 /* 1018 * Read a byte of data stored in the EEPROM at address 'addr.' The 1019 * BCM570x supports both the traditional bitbang interface and an 1020 * auto access interface for reading the EEPROM. We use the auto 1021 * access method. 1022 */ 1023 static uint8_t 1024 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1025 { 1026 int i; 1027 uint32_t byte = 0; 1028 1029 /* 1030 * Enable use of auto EEPROM access so we can avoid 1031 * having to use the bitbang method. 1032 */ 1033 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1034 1035 /* Reset the EEPROM, load the clock period. */ 1036 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 1037 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1038 DELAY(20); 1039 1040 /* Issue the read EEPROM command. */ 1041 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1042 1043 /* Wait for completion */ 1044 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1045 DELAY(10); 1046 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1047 break; 1048 } 1049 1050 if (i == BGE_TIMEOUT * 10) { 1051 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 1052 return 1; 1053 } 1054 1055 /* Get result. */ 1056 byte = CSR_READ_4(sc, BGE_EE_DATA); 1057 1058 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1059 1060 return 0; 1061 } 1062 1063 /* 1064 * Read a sequence of bytes from the EEPROM. 1065 */ 1066 static int 1067 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 1068 { 1069 int error = 0, i; 1070 uint8_t byte = 0; 1071 char *dest = destv; 1072 1073 for (i = 0; i < cnt; i++) { 1074 error = bge_eeprom_getbyte(sc, off + i, &byte); 1075 if (error) 1076 break; 1077 *(dest + i) = byte; 1078 } 1079 1080 return error ? 1 : 0; 1081 } 1082 1083 static int 1084 bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 1085 { 1086 struct bge_softc * const sc = device_private(dev); 1087 uint32_t data; 1088 uint32_t autopoll; 1089 int rv = 0; 1090 int i; 1091 1092 KASSERT(mutex_owned(sc->sc_intr_lock)); 1093 1094 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1095 return -1; 1096 1097 /* Reading with autopolling on may trigger PCI errors */ 1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1099 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1100 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1101 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1102 DELAY(80); 1103 } 1104 1105 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1106 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1107 1108 for (i = 0; i < BGE_TIMEOUT; i++) { 1109 delay(10); 1110 data = CSR_READ_4(sc, BGE_MI_COMM); 1111 if (!(data & BGE_MICOMM_BUSY)) { 1112 DELAY(5); 1113 data = CSR_READ_4(sc, BGE_MI_COMM); 1114 break; 1115 } 1116 } 1117 1118 if (i == BGE_TIMEOUT) { 1119 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1120 rv = ETIMEDOUT; 1121 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1122 /* XXX This error occurs on some devices while attaching. */ 1123 aprint_debug_dev(sc->bge_dev, "PHY read I/O error\n"); 1124 rv = EIO; 1125 } else 1126 *val = data & BGE_MICOMM_DATA; 1127 1128 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1129 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1130 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1131 DELAY(80); 1132 } 1133 1134 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1135 1136 return rv; 1137 } 1138 1139 static int 1140 bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 1141 { 1142 struct bge_softc * const sc = device_private(dev); 1143 uint32_t data, autopoll; 1144 int rv = 0; 1145 int i; 1146 1147 KASSERT(mutex_owned(sc->sc_intr_lock)); 1148 1149 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1150 (reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL)) 1151 return 0; 1152 1153 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1154 return -1; 1155 1156 /* Reading with autopolling on may trigger PCI errors */ 1157 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1158 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1159 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1160 BGE_CLRBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1161 DELAY(80); 1162 } 1163 1164 CSR_WRITE_4_FLUSH(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1165 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1166 1167 for (i = 0; i < BGE_TIMEOUT; i++) { 1168 delay(10); 1169 data = CSR_READ_4(sc, BGE_MI_COMM); 1170 if (!(data & BGE_MICOMM_BUSY)) { 1171 delay(5); 1172 data = CSR_READ_4(sc, BGE_MI_COMM); 1173 break; 1174 } 1175 } 1176 1177 if (i == BGE_TIMEOUT) { 1178 aprint_error_dev(sc->bge_dev, "PHY write timed out\n"); 1179 rv = ETIMEDOUT; 1180 } else if ((data & BGE_MICOMM_READFAIL) != 0) { 1181 aprint_error_dev(sc->bge_dev, "PHY write I/O error\n"); 1182 rv = EIO; 1183 } 1184 1185 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1186 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1187 BGE_SETBIT_FLUSH(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1188 delay(80); 1189 } 1190 1191 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1192 1193 return rv; 1194 } 1195 1196 static void 1197 bge_miibus_statchg(struct ifnet *ifp) 1198 { 1199 struct bge_softc * const sc = ifp->if_softc; 1200 struct mii_data *mii = &sc->bge_mii; 1201 uint32_t mac_mode, rx_mode, tx_mode; 1202 1203 KASSERT(mutex_owned(sc->sc_intr_lock)); 1204 1205 /* 1206 * Get flow control negotiation result. 1207 */ 1208 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1209 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1210 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1211 1212 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1213 mii->mii_media_status & IFM_ACTIVE && 1214 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1215 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1216 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1217 (!(mii->mii_media_status & IFM_ACTIVE) || 1218 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1219 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1220 1221 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1222 return; 1223 1224 /* Set the port mode (MII/GMII) to match the link speed. */ 1225 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1226 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1227 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1228 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1229 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1230 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1231 mac_mode |= BGE_PORTMODE_GMII; 1232 else 1233 mac_mode |= BGE_PORTMODE_MII; 1234 1235 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1236 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1237 if ((mii->mii_media_active & IFM_FDX) != 0) { 1238 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1239 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1240 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1241 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1242 } else 1243 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1244 1245 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, mac_mode); 1246 DELAY(40); 1247 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1248 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1249 } 1250 1251 /* 1252 * Update rx threshold levels to values in a particular slot 1253 * of the interrupt-mitigation table bge_rx_threshes. 1254 */ 1255 static void 1256 bge_set_thresh(struct ifnet *ifp, int lvl) 1257 { 1258 struct bge_softc * const sc = ifp->if_softc; 1259 1260 /* 1261 * For now, just save the new Rx-intr thresholds and record 1262 * that a threshold update is pending. Updating the hardware 1263 * registers here (even at splhigh()) is observed to 1264 * occasionally cause glitches where Rx-interrupts are not 1265 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 1266 */ 1267 mutex_enter(sc->sc_intr_lock); 1268 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1269 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1270 sc->bge_pending_rxintr_change = true; 1271 mutex_exit(sc->sc_intr_lock); 1272 } 1273 1274 1275 /* 1276 * Update Rx thresholds of all bge devices 1277 */ 1278 static void 1279 bge_update_all_threshes(int lvl) 1280 { 1281 const char * const namebuf = "bge"; 1282 const size_t namelen = strlen(namebuf); 1283 struct ifnet *ifp; 1284 1285 if (lvl < 0) 1286 lvl = 0; 1287 else if (lvl >= NBGE_RX_THRESH) 1288 lvl = NBGE_RX_THRESH - 1; 1289 1290 /* 1291 * Now search all the interfaces for this name/number 1292 */ 1293 int s = pserialize_read_enter(); 1294 IFNET_READER_FOREACH(ifp) { 1295 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1296 continue; 1297 /* We got a match: update if doing auto-threshold-tuning */ 1298 if (bge_auto_thresh) 1299 bge_set_thresh(ifp, lvl); 1300 } 1301 pserialize_read_exit(s); 1302 } 1303 1304 /* 1305 * Handle events that have triggered interrupts. 1306 */ 1307 static void 1308 bge_handle_events(struct bge_softc *sc) 1309 { 1310 1311 return; 1312 } 1313 1314 /* 1315 * Memory management for jumbo frames. 1316 */ 1317 1318 static int 1319 bge_alloc_jumbo_mem(struct bge_softc *sc) 1320 { 1321 char *ptr, *kva; 1322 int i, rseg, state, error; 1323 struct bge_jpool_entry *entry; 1324 1325 state = error = 0; 1326 1327 /* Grab a big chunk o' storage. */ 1328 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1329 &sc->bge_cdata.bge_rx_jumbo_seg, 1, &rseg, BUS_DMA_WAITOK)) { 1330 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1331 return ENOBUFS; 1332 } 1333 1334 state = 1; 1335 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1336 rseg, BGE_JMEM, (void **)&kva, BUS_DMA_WAITOK)) { 1337 aprint_error_dev(sc->bge_dev, 1338 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1339 error = ENOBUFS; 1340 goto out; 1341 } 1342 1343 state = 2; 1344 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1345 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_jumbo_map)) { 1346 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1347 error = ENOBUFS; 1348 goto out; 1349 } 1350 1351 state = 3; 1352 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1353 kva, BGE_JMEM, NULL, BUS_DMA_WAITOK)) { 1354 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1355 error = ENOBUFS; 1356 goto out; 1357 } 1358 1359 state = 4; 1360 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1361 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1362 1363 SLIST_INIT(&sc->bge_jfree_listhead); 1364 SLIST_INIT(&sc->bge_jinuse_listhead); 1365 1366 /* 1367 * Now divide it up into 9K pieces and save the addresses 1368 * in an array. 1369 */ 1370 ptr = sc->bge_cdata.bge_jumbo_buf; 1371 for (i = 0; i < BGE_JSLOTS; i++) { 1372 sc->bge_cdata.bge_jslots[i] = ptr; 1373 ptr += BGE_JLEN; 1374 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 1375 entry->slot = i; 1376 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1377 entry, jpool_entries); 1378 } 1379 out: 1380 if (error != 0) { 1381 switch (state) { 1382 case 4: 1383 bus_dmamap_unload(sc->bge_dmatag, 1384 sc->bge_cdata.bge_rx_jumbo_map); 1385 /* FALLTHROUGH */ 1386 case 3: 1387 bus_dmamap_destroy(sc->bge_dmatag, 1388 sc->bge_cdata.bge_rx_jumbo_map); 1389 /* FALLTHROUGH */ 1390 case 2: 1391 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1392 /* FALLTHROUGH */ 1393 case 1: 1394 bus_dmamem_free(sc->bge_dmatag, 1395 &sc->bge_cdata.bge_rx_jumbo_seg, rseg); 1396 break; 1397 default: 1398 break; 1399 } 1400 } 1401 1402 return error; 1403 } 1404 1405 static void 1406 bge_free_jumbo_mem(struct bge_softc *sc) 1407 { 1408 struct bge_jpool_entry *entry, *tmp; 1409 1410 KASSERT(SLIST_EMPTY(&sc->bge_jinuse_listhead)); 1411 1412 SLIST_FOREACH_SAFE(entry, &sc->bge_jfree_listhead, jpool_entries, tmp) { 1413 kmem_free(entry, sizeof(*entry)); 1414 } 1415 1416 bus_dmamap_unload(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1417 1418 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map); 1419 1420 bus_dmamem_unmap(sc->bge_dmatag, sc->bge_cdata.bge_jumbo_buf, BGE_JMEM); 1421 1422 bus_dmamem_free(sc->bge_dmatag, &sc->bge_cdata.bge_rx_jumbo_seg, 1); 1423 } 1424 1425 /* 1426 * Allocate a jumbo buffer. 1427 */ 1428 static void * 1429 bge_jalloc(struct bge_softc *sc) 1430 { 1431 struct bge_jpool_entry *entry; 1432 1433 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1434 1435 if (entry == NULL) { 1436 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1437 return NULL; 1438 } 1439 1440 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1441 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1442 return sc->bge_cdata.bge_jslots[entry->slot]; 1443 } 1444 1445 /* 1446 * Release a jumbo buffer. 1447 */ 1448 static void 1449 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1450 { 1451 struct bge_jpool_entry *entry; 1452 struct bge_softc * const sc = arg; 1453 1454 if (sc == NULL) 1455 panic("bge_jfree: can't find softc pointer!"); 1456 1457 /* calculate the slot this buffer belongs to */ 1458 int i = ((char *)buf - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1459 1460 if (i < 0 || i >= BGE_JSLOTS) 1461 panic("bge_jfree: asked to free buffer that we don't manage!"); 1462 1463 mutex_enter(sc->sc_intr_lock); 1464 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1465 if (entry == NULL) 1466 panic("bge_jfree: buffer not in use!"); 1467 entry->slot = i; 1468 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1469 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1470 mutex_exit(sc->sc_intr_lock); 1471 1472 if (__predict_true(m != NULL)) 1473 pool_cache_put(mb_cache, m); 1474 } 1475 1476 1477 /* 1478 * Initialize a standard receive ring descriptor. 1479 */ 1480 static int 1481 bge_newbuf_std(struct bge_softc *sc, int i) 1482 { 1483 const bus_dmamap_t dmamap = sc->bge_cdata.bge_rx_std_map[i]; 1484 struct mbuf *m; 1485 1486 MGETHDR(m, M_DONTWAIT, MT_DATA); 1487 if (m == NULL) 1488 return ENOBUFS; 1489 MCLAIM(m, &sc->ethercom.ec_rx_mowner); 1490 1491 MCLGET(m, M_DONTWAIT); 1492 if (!(m->m_flags & M_EXT)) { 1493 m_freem(m); 1494 return ENOBUFS; 1495 } 1496 m->m_len = m->m_pkthdr.len = MCLBYTES; 1497 1498 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1499 m_adj(m, ETHER_ALIGN); 1500 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m, 1501 BUS_DMA_READ | BUS_DMA_NOWAIT)) { 1502 m_freem(m); 1503 return ENOBUFS; 1504 } 1505 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1506 BUS_DMASYNC_PREREAD); 1507 sc->bge_cdata.bge_rx_std_chain[i] = m; 1508 1509 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1510 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1511 i * sizeof(struct bge_rx_bd), 1512 sizeof(struct bge_rx_bd), 1513 BUS_DMASYNC_POSTWRITE); 1514 1515 struct bge_rx_bd * const r = &sc->bge_rdata->bge_rx_std_ring[i]; 1516 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1517 r->bge_flags = BGE_RXBDFLAG_END; 1518 r->bge_len = m->m_len; 1519 r->bge_idx = i; 1520 1521 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1522 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1523 i * sizeof(struct bge_rx_bd), 1524 sizeof(struct bge_rx_bd), 1525 BUS_DMASYNC_PREWRITE); 1526 1527 sc->bge_std_cnt++; 1528 1529 return 0; 1530 } 1531 1532 /* 1533 * Initialize a jumbo receive ring descriptor. This allocates 1534 * a jumbo buffer from the pool managed internally by the driver. 1535 */ 1536 static int 1537 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1538 { 1539 struct mbuf *m_new = NULL; 1540 struct bge_rx_bd *r; 1541 void *buf = NULL; 1542 1543 if (m == NULL) { 1544 1545 /* Allocate the mbuf. */ 1546 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1547 if (m_new == NULL) 1548 return ENOBUFS; 1549 MCLAIM(m, &sc->ethercom.ec_rx_mowner); 1550 1551 /* Allocate the jumbo buffer */ 1552 buf = bge_jalloc(sc); 1553 if (buf == NULL) { 1554 m_freem(m_new); 1555 aprint_error_dev(sc->bge_dev, 1556 "jumbo allocation failed -- packet dropped!\n"); 1557 return ENOBUFS; 1558 } 1559 1560 /* Attach the buffer to the mbuf. */ 1561 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1562 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1563 bge_jfree, sc); 1564 m_new->m_flags |= M_EXT_RW; 1565 } else { 1566 m_new = m; 1567 buf = m_new->m_data = m_new->m_ext.ext_buf; 1568 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1569 } 1570 if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) 1571 m_adj(m_new, ETHER_ALIGN); 1572 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1573 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 1574 BGE_JLEN, BUS_DMASYNC_PREREAD); 1575 1576 /* Set up the descriptor. */ 1577 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1578 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1579 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1580 r->bge_flags = BGE_RXBDFLAG_END | BGE_RXBDFLAG_JUMBO_RING; 1581 r->bge_len = m_new->m_len; 1582 r->bge_idx = i; 1583 1584 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1585 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1586 i * sizeof(struct bge_rx_bd), 1587 sizeof(struct bge_rx_bd), 1588 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1589 1590 return 0; 1591 } 1592 1593 static int 1594 bge_init_rx_ring_std(struct bge_softc *sc) 1595 { 1596 bus_dmamap_t dmamap; 1597 int error = 0; 1598 u_int i; 1599 1600 if (sc->bge_flags & BGEF_RXRING_VALID) 1601 return 0; 1602 1603 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1604 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1605 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dmamap); 1606 if (error) 1607 goto uncreate; 1608 1609 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1610 memset(&sc->bge_rdata->bge_rx_std_ring[i], 0, 1611 sizeof(struct bge_rx_bd)); 1612 } 1613 1614 sc->bge_std = i - 1; 1615 sc->bge_std_cnt = 0; 1616 bge_fill_rx_ring_std(sc); 1617 1618 sc->bge_flags |= BGEF_RXRING_VALID; 1619 1620 return 0; 1621 1622 uncreate: 1623 while (--i) { 1624 bus_dmamap_destroy(sc->bge_dmatag, 1625 sc->bge_cdata.bge_rx_std_map[i]); 1626 } 1627 return error; 1628 } 1629 1630 static void 1631 bge_fill_rx_ring_std(struct bge_softc *sc) 1632 { 1633 int i = sc->bge_std; 1634 bool post = false; 1635 1636 while (sc->bge_std_cnt < BGE_STD_RX_RING_CNT) { 1637 BGE_INC(i, BGE_STD_RX_RING_CNT); 1638 1639 if (bge_newbuf_std(sc, i) != 0) 1640 break; 1641 1642 sc->bge_std = i; 1643 post = true; 1644 } 1645 1646 if (post) 1647 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1648 } 1649 1650 1651 static void 1652 bge_free_rx_ring_std(struct bge_softc *sc) 1653 { 1654 1655 if (!(sc->bge_flags & BGEF_RXRING_VALID)) 1656 return; 1657 1658 for (u_int i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1659 const bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i]; 1660 struct mbuf * const m = sc->bge_cdata.bge_rx_std_chain[i]; 1661 if (m != NULL) { 1662 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 1663 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1664 bus_dmamap_unload(sc->bge_dmatag, dmap); 1665 m_freem(m); 1666 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1667 } 1668 bus_dmamap_destroy(sc->bge_dmatag, 1669 sc->bge_cdata.bge_rx_std_map[i]); 1670 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1671 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1672 sizeof(struct bge_rx_bd)); 1673 } 1674 1675 sc->bge_flags &= ~BGEF_RXRING_VALID; 1676 } 1677 1678 static int 1679 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1680 { 1681 int i; 1682 volatile struct bge_rcb *rcb; 1683 1684 if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) 1685 return 0; 1686 1687 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1688 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1689 return ENOBUFS; 1690 } 1691 1692 sc->bge_jumbo = i - 1; 1693 sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; 1694 1695 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1696 rcb->bge_maxlen_flags = 0; 1697 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1698 1699 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1700 1701 return 0; 1702 } 1703 1704 static void 1705 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1706 { 1707 int i; 1708 1709 if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) 1710 return; 1711 1712 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1713 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1714 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1715 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1716 sizeof(struct bge_rx_bd)); 1717 } 1718 1719 sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; 1720 } 1721 1722 static void 1723 bge_free_tx_ring(struct bge_softc *sc, bool disable) 1724 { 1725 int i; 1726 struct txdmamap_pool_entry *dma; 1727 1728 if (!(sc->bge_flags & BGEF_TXRING_VALID)) 1729 return; 1730 1731 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1732 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1733 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1734 sc->bge_cdata.bge_tx_chain[i] = NULL; 1735 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1736 link); 1737 sc->txdma[i] = 0; 1738 } 1739 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1740 sizeof(struct bge_tx_bd)); 1741 } 1742 1743 if (disable) { 1744 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1745 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1746 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1747 if (sc->bge_dma64) { 1748 bus_dmamap_destroy(sc->bge_dmatag32, 1749 dma->dmamap32); 1750 } 1751 kmem_free(dma, sizeof(*dma)); 1752 } 1753 SLIST_INIT(&sc->txdma_list); 1754 } 1755 1756 sc->bge_flags &= ~BGEF_TXRING_VALID; 1757 } 1758 1759 static int 1760 bge_init_tx_ring(struct bge_softc *sc) 1761 { 1762 struct ifnet * const ifp = &sc->ethercom.ec_if; 1763 int i; 1764 bus_dmamap_t dmamap, dmamap32; 1765 bus_size_t maxsegsz; 1766 struct txdmamap_pool_entry *dma; 1767 1768 if (sc->bge_flags & BGEF_TXRING_VALID) 1769 return 0; 1770 1771 sc->bge_txcnt = 0; 1772 sc->bge_tx_saved_considx = 0; 1773 1774 /* Initialize transmit producer index for host-memory send ring. */ 1775 sc->bge_tx_prodidx = 0; 1776 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1777 /* 5700 b2 errata */ 1778 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1779 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1780 1781 /* NIC-memory send ring not used; initialize to zero. */ 1782 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1783 /* 5700 b2 errata */ 1784 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1785 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1786 1787 /* Limit DMA segment size for some chips */ 1788 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && 1789 (ifp->if_mtu <= ETHERMTU)) 1790 maxsegsz = 2048; 1791 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1792 maxsegsz = 4096; 1793 else 1794 maxsegsz = ETHER_MAX_LEN_JUMBO; 1795 1796 if (SLIST_FIRST(&sc->txdma_list) != NULL) 1797 goto alloc_done; 1798 1799 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1800 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1801 BGE_NTXSEG, maxsegsz, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1802 &dmamap)) 1803 return ENOBUFS; 1804 if (dmamap == NULL) 1805 panic("dmamap NULL in bge_init_tx_ring"); 1806 if (sc->bge_dma64) { 1807 if (bus_dmamap_create(sc->bge_dmatag32, BGE_TXDMA_MAX, 1808 BGE_NTXSEG, maxsegsz, 0, 1809 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1810 &dmamap32)) { 1811 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1812 return ENOBUFS; 1813 } 1814 if (dmamap32 == NULL) 1815 panic("dmamap32 NULL in bge_init_tx_ring"); 1816 } else 1817 dmamap32 = dmamap; 1818 dma = kmem_alloc(sizeof(*dma), KM_NOSLEEP); 1819 if (dma == NULL) { 1820 aprint_error_dev(sc->bge_dev, 1821 "can't alloc txdmamap_pool_entry\n"); 1822 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1823 if (sc->bge_dma64) 1824 bus_dmamap_destroy(sc->bge_dmatag32, dmamap32); 1825 return ENOMEM; 1826 } 1827 dma->dmamap = dmamap; 1828 dma->dmamap32 = dmamap32; 1829 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1830 } 1831 alloc_done: 1832 sc->bge_flags |= BGEF_TXRING_VALID; 1833 1834 return 0; 1835 } 1836 1837 static void 1838 bge_setmulti(struct bge_softc *sc) 1839 { 1840 struct ethercom * const ec = &sc->ethercom; 1841 struct ether_multi *enm; 1842 struct ether_multistep step; 1843 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1844 uint32_t h; 1845 int i; 1846 1847 KASSERT(mutex_owned(sc->sc_mcast_lock)); 1848 if (sc->bge_if_flags & IFF_PROMISC) 1849 goto allmulti; 1850 1851 /* Now program new ones. */ 1852 ETHER_LOCK(ec); 1853 ETHER_FIRST_MULTI(step, ec, enm); 1854 while (enm != NULL) { 1855 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1856 /* 1857 * We must listen to a range of multicast addresses. 1858 * For now, just accept all multicasts, rather than 1859 * trying to set only those filter bits needed to match 1860 * the range. (At this time, the only use of address 1861 * ranges is for IP multicast routing, for which the 1862 * range is big enough to require all bits set.) 1863 */ 1864 ETHER_UNLOCK(ec); 1865 goto allmulti; 1866 } 1867 1868 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1869 1870 /* Just want the 7 least-significant bits. */ 1871 h &= 0x7f; 1872 1873 hashes[(h & 0x60) >> 5] |= 1U << (h & 0x1F); 1874 ETHER_NEXT_MULTI(step, enm); 1875 } 1876 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1877 ETHER_UNLOCK(ec); 1878 1879 goto setit; 1880 1881 allmulti: 1882 ETHER_LOCK(ec); 1883 ec->ec_flags |= ETHER_F_ALLMULTI; 1884 ETHER_UNLOCK(ec); 1885 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1886 1887 setit: 1888 for (i = 0; i < 4; i++) 1889 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1890 } 1891 1892 static void 1893 bge_sig_pre_reset(struct bge_softc *sc, int type) 1894 { 1895 1896 /* 1897 * Some chips don't like this so only do this if ASF is enabled 1898 */ 1899 if (sc->bge_asf_mode) 1900 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1901 1902 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1903 switch (type) { 1904 case BGE_RESET_START: 1905 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1906 BGE_FW_DRV_STATE_START); 1907 break; 1908 case BGE_RESET_SHUTDOWN: 1909 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1910 BGE_FW_DRV_STATE_UNLOAD); 1911 break; 1912 case BGE_RESET_SUSPEND: 1913 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1914 BGE_FW_DRV_STATE_SUSPEND); 1915 break; 1916 } 1917 } 1918 1919 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1920 bge_ape_driver_state_change(sc, type); 1921 } 1922 1923 static void 1924 bge_sig_post_reset(struct bge_softc *sc, int type) 1925 { 1926 1927 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1928 switch (type) { 1929 case BGE_RESET_START: 1930 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1931 BGE_FW_DRV_STATE_START_DONE); 1932 /* START DONE */ 1933 break; 1934 case BGE_RESET_SHUTDOWN: 1935 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1936 BGE_FW_DRV_STATE_UNLOAD_DONE); 1937 break; 1938 } 1939 } 1940 1941 if (type == BGE_RESET_SHUTDOWN) 1942 bge_ape_driver_state_change(sc, type); 1943 } 1944 1945 static void 1946 bge_sig_legacy(struct bge_softc *sc, int type) 1947 { 1948 1949 if (sc->bge_asf_mode) { 1950 switch (type) { 1951 case BGE_RESET_START: 1952 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1953 BGE_FW_DRV_STATE_START); 1954 break; 1955 case BGE_RESET_SHUTDOWN: 1956 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1957 BGE_FW_DRV_STATE_UNLOAD); 1958 break; 1959 } 1960 } 1961 } 1962 1963 static void 1964 bge_wait_for_event_ack(struct bge_softc *sc) 1965 { 1966 int i; 1967 1968 /* wait up to 2500usec */ 1969 for (i = 0; i < 250; i++) { 1970 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1971 BGE_RX_CPU_DRV_EVENT)) 1972 break; 1973 DELAY(10); 1974 } 1975 } 1976 1977 static void 1978 bge_stop_fw(struct bge_softc *sc) 1979 { 1980 1981 if (sc->bge_asf_mode) { 1982 bge_wait_for_event_ack(sc); 1983 1984 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1985 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 1986 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1987 1988 bge_wait_for_event_ack(sc); 1989 } 1990 } 1991 1992 static int 1993 bge_poll_fw(struct bge_softc *sc) 1994 { 1995 uint32_t val; 1996 int i; 1997 1998 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1999 for (i = 0; i < BGE_TIMEOUT; i++) { 2000 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2001 if (val & BGE_VCPU_STATUS_INIT_DONE) 2002 break; 2003 DELAY(100); 2004 } 2005 if (i >= BGE_TIMEOUT) { 2006 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2007 return -1; 2008 } 2009 } else { 2010 /* 2011 * Poll the value location we just wrote until 2012 * we see the 1's complement of the magic number. 2013 * This indicates that the firmware initialization 2014 * is complete. 2015 * XXX 1000ms for Flash and 10000ms for SEEPROM. 2016 */ 2017 for (i = 0; i < BGE_TIMEOUT; i++) { 2018 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 2019 if (val == ~BGE_SRAM_FW_MB_MAGIC) 2020 break; 2021 DELAY(10); 2022 } 2023 2024 if ((i >= BGE_TIMEOUT) 2025 && ((sc->bge_flags & BGEF_NO_EEPROM) == 0)) { 2026 aprint_error_dev(sc->bge_dev, 2027 "firmware handshake timed out, val = %x\n", val); 2028 return -1; 2029 } 2030 } 2031 2032 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2033 /* tg3 says we have to wait extra time */ 2034 delay(10 * 1000); 2035 } 2036 2037 return 0; 2038 } 2039 2040 int 2041 bge_phy_addr(struct bge_softc *sc) 2042 { 2043 struct pci_attach_args *pa = &(sc->bge_pa); 2044 int phy_addr = 1; 2045 2046 /* 2047 * PHY address mapping for various devices. 2048 * 2049 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2050 * ---------+-------+-------+-------+-------+ 2051 * BCM57XX | 1 | X | X | X | 2052 * BCM5704 | 1 | X | 1 | X | 2053 * BCM5717 | 1 | 8 | 2 | 9 | 2054 * BCM5719 | 1 | 8 | 2 | 9 | 2055 * BCM5720 | 1 | 8 | 2 | 9 | 2056 * 2057 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 2058 * ---------+-------+-------+-------+-------+ 2059 * BCM57XX | X | X | X | X | 2060 * BCM5704 | X | X | X | X | 2061 * BCM5717 | X | X | X | X | 2062 * BCM5719 | 3 | 10 | 4 | 11 | 2063 * BCM5720 | X | X | X | X | 2064 * 2065 * Other addresses may respond but they are not 2066 * IEEE compliant PHYs and should be ignored. 2067 */ 2068 switch (BGE_ASICREV(sc->bge_chipid)) { 2069 case BGE_ASICREV_BCM5717: 2070 case BGE_ASICREV_BCM5719: 2071 case BGE_ASICREV_BCM5720: 2072 phy_addr = pa->pa_function; 2073 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 2074 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 2075 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 2076 } else { 2077 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2078 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 2079 } 2080 } 2081 2082 return phy_addr; 2083 } 2084 2085 /* 2086 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2087 * self-test results. 2088 */ 2089 static int 2090 bge_chipinit(struct bge_softc *sc) 2091 { 2092 uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg; 2093 int i; 2094 2095 /* Set endianness before we access any non-PCI registers. */ 2096 misc_ctl = BGE_INIT; 2097 if (sc->bge_flags & BGEF_TAGGED_STATUS) 2098 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 2099 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2100 misc_ctl); 2101 2102 /* 2103 * Clear the MAC statistics block in the NIC's 2104 * internal memory. 2105 */ 2106 for (i = BGE_STATS_BLOCK; 2107 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 2108 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2109 2110 for (i = BGE_STATUS_BLOCK; 2111 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 2112 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 2113 2114 /* 5717 workaround from tg3 */ 2115 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2116 /* Save */ 2117 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2118 2119 /* Temporary modify MODE_CTL to control TLP */ 2120 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2121 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1); 2122 2123 /* Control TLP */ 2124 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2125 BGE_TLP_PHYCTL1); 2126 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1, 2127 reg | BGE_TLP_PHYCTL1_EN_L1PLLPD); 2128 2129 /* Restore */ 2130 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2131 } 2132 2133 if (BGE_IS_57765_FAMILY(sc)) { 2134 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { 2135 /* Save */ 2136 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2137 2138 /* Temporary modify MODE_CTL to control TLP */ 2139 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2140 CSR_WRITE_4(sc, BGE_MODE_CTL, 2141 reg | BGE_MODECTL_PCIE_TLPADDR1); 2142 2143 /* Control TLP */ 2144 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2145 BGE_TLP_PHYCTL5); 2146 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5, 2147 reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ); 2148 2149 /* Restore */ 2150 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2151 } 2152 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 2153 /* 2154 * For the 57766 and non Ax versions of 57765, bootcode 2155 * needs to setup the PCIE Fast Training Sequence (FTS) 2156 * value to prevent transmit hangs. 2157 */ 2158 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL); 2159 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 2160 reg | BGE_CPMU_PADRNG_CTL_RDIV2); 2161 2162 /* Save */ 2163 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); 2164 2165 /* Temporary modify MODE_CTL to control TLP */ 2166 reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK; 2167 CSR_WRITE_4(sc, BGE_MODE_CTL, 2168 reg | BGE_MODECTL_PCIE_TLPADDR0); 2169 2170 /* Control TLP */ 2171 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG + 2172 BGE_TLP_FTSMAX); 2173 reg &= ~BGE_TLP_FTSMAX_MSK; 2174 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX, 2175 reg | BGE_TLP_FTSMAX_VAL); 2176 2177 /* Restore */ 2178 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2179 } 2180 2181 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 2182 reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK; 2183 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 2184 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 2185 } 2186 2187 /* Set up the PCI DMA control register. */ 2188 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 2189 if (sc->bge_flags & BGEF_PCIE) { 2190 /* Read watermark not used, 128 bytes for write. */ 2191 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 2192 device_xname(sc->bge_dev))); 2193 if (sc->bge_mps >= 256) 2194 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2195 else 2196 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2197 } else if (sc->bge_flags & BGEF_PCIX) { 2198 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 2199 device_xname(sc->bge_dev))); 2200 /* PCI-X bus */ 2201 if (BGE_IS_5714_FAMILY(sc)) { 2202 /* 256 bytes for read and write. */ 2203 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 2204 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 2205 2206 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 2207 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2208 else 2209 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 2210 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 2211 /* 2212 * In the BCM5703, the DMA read watermark should 2213 * be set to less than or equal to the maximum 2214 * memory read byte count of the PCI-X command 2215 * register. 2216 */ 2217 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 2218 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2219 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2220 /* 1536 bytes for read, 384 bytes for write. */ 2221 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2222 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 2223 } else { 2224 /* 384 bytes for read and write. */ 2225 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 2226 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 2227 (0x0F); 2228 } 2229 2230 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2231 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2232 uint32_t tmp; 2233 2234 /* Set ONEDMA_ATONCE for hardware workaround. */ 2235 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 2236 if (tmp == 6 || tmp == 7) 2237 dma_rw_ctl |= 2238 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 2239 2240 /* Set PCI-X DMA write workaround. */ 2241 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 2242 } 2243 } else { 2244 /* Conventional PCI bus: 256 bytes for read and write. */ 2245 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 2246 device_xname(sc->bge_dev))); 2247 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 2248 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 2249 2250 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 2251 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 2252 dma_rw_ctl |= 0x0F; 2253 } 2254 2255 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2256 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 2257 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 2258 BGE_PCIDMARWCTL_ASRT_ALL_BE; 2259 2260 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2261 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2262 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 2263 2264 if (BGE_IS_57765_PLUS(sc)) { 2265 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 2266 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 2267 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 2268 2269 /* 2270 * Enable HW workaround for controllers that misinterpret 2271 * a status tag update and leave interrupts permanently 2272 * disabled. 2273 */ 2274 if (!BGE_IS_57765_FAMILY(sc) && 2275 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2276 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 2277 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 2278 } 2279 2280 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 2281 dma_rw_ctl); 2282 2283 /* 2284 * Set up general mode register. 2285 */ 2286 mode_ctl = BGE_DMA_SWAP_OPTIONS; 2287 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2288 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2289 /* Retain Host-2-BMC settings written by APE firmware. */ 2290 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 2291 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 2292 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 2293 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 2294 } 2295 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 2296 BGE_MODECTL_TX_NO_PHDR_CSUM; 2297 2298 /* 2299 * BCM5701 B5 have a bug causing data corruption when using 2300 * 64-bit DMA reads, which can be terminated early and then 2301 * completed later as 32-bit accesses, in combination with 2302 * certain bridges. 2303 */ 2304 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2305 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 2306 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 2307 2308 /* 2309 * Tell the firmware the driver is running 2310 */ 2311 if (sc->bge_asf_mode & ASF_STACKUP) 2312 mode_ctl |= BGE_MODECTL_STACKUP; 2313 2314 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 2315 2316 /* 2317 * Disable memory write invalidate. Apparently it is not supported 2318 * properly by these devices. 2319 */ 2320 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 2321 PCI_COMMAND_INVALIDATE_ENABLE); 2322 2323 #ifdef __brokenalpha__ 2324 /* 2325 * Must insure that we do not cross an 8K (bytes) boundary 2326 * for DMA reads. Our highest limit is 1K bytes. This is a 2327 * restriction on some ALPHA platforms with early revision 2328 * 21174 PCI chipsets, such as the AlphaPC 164lx 2329 */ 2330 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 2331 #endif 2332 2333 /* Set the timer prescaler (always 66MHz) */ 2334 CSR_WRITE_4_FLUSH(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2335 2336 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2337 DELAY(40); /* XXX */ 2338 2339 /* Put PHY into ready state */ 2340 BGE_CLRBIT_FLUSH(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 2341 DELAY(40); 2342 } 2343 2344 return 0; 2345 } 2346 2347 static int 2348 bge_blockinit(struct bge_softc *sc) 2349 { 2350 volatile struct bge_rcb *rcb; 2351 bus_size_t rcb_addr; 2352 struct ifnet * const ifp = &sc->ethercom.ec_if; 2353 bge_hostaddr taddr; 2354 uint32_t dmactl, rdmareg, mimode, val; 2355 int i, limit; 2356 2357 /* 2358 * Initialize the memory window pointer register so that 2359 * we can access the first 32K of internal NIC RAM. This will 2360 * allow us to set up the TX send ring RCBs and the RX return 2361 * ring RCBs, plus other things which live in NIC memory. 2362 */ 2363 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 2364 2365 if (!BGE_IS_5705_PLUS(sc)) { 2366 /* 57XX step 33 */ 2367 /* Configure mbuf memory pool */ 2368 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 2369 2370 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2371 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 2372 else 2373 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 2374 2375 /* 57XX step 34 */ 2376 /* Configure DMA resource pool */ 2377 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 2378 BGE_DMA_DESCRIPTORS); 2379 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 2380 } 2381 2382 /* 5718 step 11, 57XX step 35 */ 2383 /* 2384 * Configure mbuf pool watermarks. New broadcom docs strongly 2385 * recommend these. 2386 */ 2387 if (BGE_IS_5717_PLUS(sc)) { 2388 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2389 if (ifp->if_mtu > ETHERMTU) { 2390 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2391 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2392 } else { 2393 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2394 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2395 } 2396 } else if (BGE_IS_5705_PLUS(sc)) { 2397 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2398 2399 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2400 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2401 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2402 } else { 2403 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2404 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2405 } 2406 } else { 2407 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2408 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2409 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2410 } 2411 2412 /* 57XX step 36 */ 2413 /* Configure DMA resource watermarks */ 2414 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2415 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2416 2417 /* 5718 step 13, 57XX step 38 */ 2418 /* Enable buffer manager */ 2419 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_ATTN; 2420 /* 2421 * Change the arbitration algorithm of TXMBUF read request to 2422 * round-robin instead of priority based for BCM5719. When 2423 * TXFIFO is almost empty, RDMA will hold its request until 2424 * TXFIFO is not almost empty. 2425 */ 2426 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2427 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2428 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2429 sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2430 sc->bge_chipid == BGE_CHIPID_BCM5720_A0) 2431 val |= BGE_BMANMODE_LOMBUF_ATTN; 2432 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2433 2434 /* 57XX step 39 */ 2435 /* Poll for buffer manager start indication */ 2436 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2437 DELAY(10); 2438 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2439 break; 2440 } 2441 2442 if (i == BGE_TIMEOUT * 2) { 2443 aprint_error_dev(sc->bge_dev, 2444 "buffer manager failed to start\n"); 2445 return ENXIO; 2446 } 2447 2448 /* 57XX step 40 */ 2449 /* Enable flow-through queues */ 2450 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2451 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2452 2453 /* Wait until queue initialization is complete */ 2454 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2455 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2456 break; 2457 DELAY(10); 2458 } 2459 2460 if (i == BGE_TIMEOUT * 2) { 2461 aprint_error_dev(sc->bge_dev, 2462 "flow-through queue init failed\n"); 2463 return ENXIO; 2464 } 2465 2466 /* 2467 * Summary of rings supported by the controller: 2468 * 2469 * Standard Receive Producer Ring 2470 * - This ring is used to feed receive buffers for "standard" 2471 * sized frames (typically 1536 bytes) to the controller. 2472 * 2473 * Jumbo Receive Producer Ring 2474 * - This ring is used to feed receive buffers for jumbo sized 2475 * frames (i.e. anything bigger than the "standard" frames) 2476 * to the controller. 2477 * 2478 * Mini Receive Producer Ring 2479 * - This ring is used to feed receive buffers for "mini" 2480 * sized frames to the controller. 2481 * - This feature required external memory for the controller 2482 * but was never used in a production system. Should always 2483 * be disabled. 2484 * 2485 * Receive Return Ring 2486 * - After the controller has placed an incoming frame into a 2487 * receive buffer that buffer is moved into a receive return 2488 * ring. The driver is then responsible to passing the 2489 * buffer up to the stack. Many versions of the controller 2490 * support multiple RR rings. 2491 * 2492 * Send Ring 2493 * - This ring is used for outgoing frames. Many versions of 2494 * the controller support multiple send rings. 2495 */ 2496 2497 /* 5718 step 15, 57XX step 41 */ 2498 /* Initialize the standard RX ring control block */ 2499 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2500 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2501 /* 5718 step 16 */ 2502 if (BGE_IS_57765_PLUS(sc)) { 2503 /* 2504 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2505 * Bits 15-2 : Maximum RX frame size 2506 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2507 * Bit 0 : Reserved 2508 */ 2509 rcb->bge_maxlen_flags = 2510 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2511 } else if (BGE_IS_5705_PLUS(sc)) { 2512 /* 2513 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2514 * Bits 15-2 : Reserved (should be 0) 2515 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2516 * Bit 0 : Reserved 2517 */ 2518 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2519 } else { 2520 /* 2521 * Ring size is always XXX entries 2522 * Bits 31-16: Maximum RX frame size 2523 * Bits 15-2 : Reserved (should be 0) 2524 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2525 * Bit 0 : Reserved 2526 */ 2527 rcb->bge_maxlen_flags = 2528 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2529 } 2530 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2531 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2532 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2533 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2534 else 2535 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2536 /* Write the standard receive producer ring control block. */ 2537 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2538 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2539 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2540 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2541 2542 /* Reset the standard receive producer ring producer index. */ 2543 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2544 2545 /* 57XX step 42 */ 2546 /* 2547 * Initialize the jumbo RX ring control block 2548 * We set the 'ring disabled' bit in the flags 2549 * field until we're actually ready to start 2550 * using this ring (i.e. once we set the MTU 2551 * high enough to require it). 2552 */ 2553 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2554 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2555 BGE_HOSTADDR(rcb->bge_hostaddr, 2556 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2557 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2558 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2559 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2560 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2561 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2562 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2563 else 2564 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2565 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2566 rcb->bge_hostaddr.bge_addr_hi); 2567 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2568 rcb->bge_hostaddr.bge_addr_lo); 2569 /* Program the jumbo receive producer ring RCB parameters. */ 2570 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2571 rcb->bge_maxlen_flags); 2572 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2573 /* Reset the jumbo receive producer ring producer index. */ 2574 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2575 } 2576 2577 /* 57XX step 43 */ 2578 /* Disable the mini receive producer ring RCB. */ 2579 if (BGE_IS_5700_FAMILY(sc)) { 2580 /* Set up dummy disabled mini ring RCB */ 2581 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2582 rcb->bge_maxlen_flags = 2583 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2584 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2585 rcb->bge_maxlen_flags); 2586 /* Reset the mini receive producer ring producer index. */ 2587 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2588 2589 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2590 offsetof(struct bge_ring_data, bge_info), 2591 sizeof(struct bge_gib), 2592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2593 } 2594 2595 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2596 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2597 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2598 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2599 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2600 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2601 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2602 } 2603 /* 5718 step 14, 57XX step 44 */ 2604 /* 2605 * The BD ring replenish thresholds control how often the 2606 * hardware fetches new BD's from the producer rings in host 2607 * memory. Setting the value too low on a busy system can 2608 * starve the hardware and reduce the throughput. 2609 * 2610 * Set the BD ring replenish thresholds. The recommended 2611 * values are 1/8th the number of descriptors allocated to 2612 * each ring, but since we try to avoid filling the entire 2613 * ring we set these to the minimal value of 8. This needs to 2614 * be done on several of the supported chip revisions anyway, 2615 * to work around HW bugs. 2616 */ 2617 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2618 if (BGE_IS_JUMBO_CAPABLE(sc)) 2619 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2620 2621 /* 5718 step 18 */ 2622 if (BGE_IS_5717_PLUS(sc)) { 2623 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2624 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2625 } 2626 2627 /* 57XX step 45 */ 2628 /* 2629 * Disable all send rings by setting the 'ring disabled' bit 2630 * in the flags field of all the TX send ring control blocks, 2631 * located in NIC memory. 2632 */ 2633 if (BGE_IS_5700_FAMILY(sc)) { 2634 /* 5700 to 5704 had 16 send rings. */ 2635 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2636 } else if (BGE_IS_5717_PLUS(sc)) { 2637 limit = BGE_TX_RINGS_5717_MAX; 2638 } else if (BGE_IS_57765_FAMILY(sc) || 2639 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2640 limit = BGE_TX_RINGS_57765_MAX; 2641 } else 2642 limit = 1; 2643 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2644 for (i = 0; i < limit; i++) { 2645 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2646 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2647 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2648 rcb_addr += sizeof(struct bge_rcb); 2649 } 2650 2651 /* 57XX step 46 and 47 */ 2652 /* Configure send ring RCB 0 (we use only the first ring) */ 2653 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2654 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2655 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2656 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2657 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2658 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2659 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2660 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2661 else 2662 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2663 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2664 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2665 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2666 2667 /* 57XX step 48 */ 2668 /* 2669 * Disable all receive return rings by setting the 2670 * 'ring disabled' bit in the flags field of all the receive 2671 * return ring control blocks, located in NIC memory. 2672 */ 2673 if (BGE_IS_5717_PLUS(sc)) { 2674 /* Should be 17, use 16 until we get an SRAM map. */ 2675 limit = 16; 2676 } else if (BGE_IS_5700_FAMILY(sc)) 2677 limit = BGE_RX_RINGS_MAX; 2678 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2679 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2680 BGE_IS_57765_FAMILY(sc)) 2681 limit = 4; 2682 else 2683 limit = 1; 2684 /* Disable all receive return rings */ 2685 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2686 for (i = 0; i < limit; i++) { 2687 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2688 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2689 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2690 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2691 BGE_RCB_FLAG_RING_DISABLED)); 2692 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2693 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2694 (i * (sizeof(uint64_t))), 0); 2695 rcb_addr += sizeof(struct bge_rcb); 2696 } 2697 2698 /* 57XX step 49 */ 2699 /* 2700 * Set up receive return ring 0. Note that the NIC address 2701 * for RX return rings is 0x0. The return rings live entirely 2702 * within the host, so the nicaddr field in the RCB isn't used. 2703 */ 2704 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2705 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2706 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2707 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2708 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2709 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2710 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2711 2712 /* 5718 step 24, 57XX step 53 */ 2713 /* Set random backoff seed for TX */ 2714 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2715 (CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2716 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2717 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5]) & 2718 BGE_TX_BACKOFF_SEED_MASK); 2719 2720 /* 5718 step 26, 57XX step 55 */ 2721 /* Set inter-packet gap */ 2722 val = 0x2620; 2723 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2724 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2725 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2726 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2727 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2728 2729 /* 5718 step 27, 57XX step 56 */ 2730 /* 2731 * Specify which ring to use for packets that don't match 2732 * any RX rules. 2733 */ 2734 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2735 2736 /* 5718 step 28, 57XX step 57 */ 2737 /* 2738 * Configure number of RX lists. One interrupt distribution 2739 * list, sixteen active lists, one bad frames class. 2740 */ 2741 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2742 2743 /* 5718 step 29, 57XX step 58 */ 2744 /* Initialize RX list placement stats mask. */ 2745 if (BGE_IS_575X_PLUS(sc)) { 2746 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK); 2747 val &= ~BGE_RXLPSTATCONTROL_DACK_FIX; 2748 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val); 2749 } else 2750 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2751 2752 /* 5718 step 30, 57XX step 59 */ 2753 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2754 2755 /* 5718 step 33, 57XX step 62 */ 2756 /* Disable host coalescing until we get it set up */ 2757 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2758 2759 /* 5718 step 34, 57XX step 63 */ 2760 /* Poll to make sure it's shut down. */ 2761 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2762 DELAY(10); 2763 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2764 break; 2765 } 2766 2767 if (i == BGE_TIMEOUT * 2) { 2768 aprint_error_dev(sc->bge_dev, 2769 "host coalescing engine failed to idle\n"); 2770 return ENXIO; 2771 } 2772 2773 /* 5718 step 35, 36, 37 */ 2774 /* Set up host coalescing defaults */ 2775 mutex_enter(sc->sc_intr_lock); 2776 const uint32_t rx_coal_ticks = sc->bge_rx_coal_ticks; 2777 const uint32_t tx_coal_ticks = sc->bge_tx_coal_ticks; 2778 const uint32_t rx_max_coal_bds = sc->bge_rx_max_coal_bds; 2779 const uint32_t tx_max_coal_bds = sc->bge_tx_max_coal_bds; 2780 mutex_exit(sc->sc_intr_lock); 2781 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_coal_ticks); 2782 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, tx_coal_ticks); 2783 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_max_coal_bds); 2784 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, tx_max_coal_bds); 2785 if (!(BGE_IS_5705_PLUS(sc))) { 2786 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2787 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2788 } 2789 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2790 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2791 2792 /* Set up address of statistics block */ 2793 if (BGE_IS_5700_FAMILY(sc)) { 2794 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2795 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2796 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2797 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2798 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2799 } 2800 2801 /* 5718 step 38 */ 2802 /* Set up address of status block */ 2803 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2804 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2805 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2806 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2807 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2808 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2809 2810 /* Set up status block size. */ 2811 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2812 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2813 val = BGE_STATBLKSZ_FULL; 2814 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2815 } else { 2816 val = BGE_STATBLKSZ_32BYTE; 2817 bzero(&sc->bge_rdata->bge_status_block, 32); 2818 } 2819 2820 /* 5718 step 39, 57XX step 73 */ 2821 /* Turn on host coalescing state machine */ 2822 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2823 2824 /* 5718 step 40, 57XX step 74 */ 2825 /* Turn on RX BD completion state machine and enable attentions */ 2826 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2827 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2828 2829 /* 5718 step 41, 57XX step 75 */ 2830 /* Turn on RX list placement state machine */ 2831 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2832 2833 /* 57XX step 76 */ 2834 /* Turn on RX list selector state machine. */ 2835 if (!(BGE_IS_5705_PLUS(sc))) 2836 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2837 2838 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2839 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2840 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2841 BGE_MACMODE_FRMHDR_DMA_ENB; 2842 2843 if (sc->bge_flags & BGEF_FIBER_TBI) 2844 val |= BGE_PORTMODE_TBI; 2845 else if (sc->bge_flags & BGEF_FIBER_MII) 2846 val |= BGE_PORTMODE_GMII; 2847 else 2848 val |= BGE_PORTMODE_MII; 2849 2850 /* 5718 step 42 and 43, 57XX step 77 and 78 */ 2851 /* Allow APE to send/receive frames. */ 2852 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2853 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2854 2855 /* Turn on DMA, clear stats */ 2856 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 2857 /* 5718 step 44 */ 2858 DELAY(40); 2859 2860 /* 5718 step 45, 57XX step 79 */ 2861 /* Set misc. local control, enable interrupts on attentions */ 2862 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2863 if (BGE_IS_5717_PLUS(sc)) { 2864 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */ 2865 /* 5718 step 46 */ 2866 DELAY(100); 2867 } 2868 2869 /* 57XX step 81 */ 2870 /* Turn on DMA completion state machine */ 2871 if (!(BGE_IS_5705_PLUS(sc))) 2872 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2873 2874 /* 5718 step 47, 57XX step 82 */ 2875 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2876 2877 /* 5718 step 48 */ 2878 /* Enable host coalescing bug fix. */ 2879 if (BGE_IS_5755_PLUS(sc)) 2880 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2881 2882 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2883 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2884 2885 /* Turn on write DMA state machine */ 2886 CSR_WRITE_4_FLUSH(sc, BGE_WDMA_MODE, val); 2887 /* 5718 step 49 */ 2888 DELAY(40); 2889 2890 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2891 2892 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2893 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2894 2895 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2896 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2897 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2898 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2899 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2900 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2901 2902 if (sc->bge_flags & BGEF_PCIE) 2903 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2904 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 2905 if (ifp->if_mtu <= ETHERMTU) 2906 val |= BGE_RDMAMODE_JMB_2K_MMRR; 2907 } 2908 if (sc->bge_flags & BGEF_TSO) { 2909 val |= BGE_RDMAMODE_TSO4_ENABLE; 2910 if (BGE_IS_5717_PLUS(sc)) 2911 val |= BGE_RDMAMODE_TSO6_ENABLE; 2912 } 2913 2914 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2915 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2916 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2917 BGE_RDMAMODE_H2BNC_VLAN_DET; 2918 /* 2919 * Allow multiple outstanding read requests from 2920 * non-LSO read DMA engine. 2921 */ 2922 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2923 } 2924 2925 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2926 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2927 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2928 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2929 BGE_IS_57765_PLUS(sc)) { 2930 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2931 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2932 else 2933 rdmareg = BGE_RDMA_RSRVCTRL; 2934 dmactl = CSR_READ_4(sc, rdmareg); 2935 /* 2936 * Adjust tx margin to prevent TX data corruption and 2937 * fix internal FIFO overflow. 2938 */ 2939 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2940 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2941 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2942 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2943 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2944 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2945 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2946 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2947 } 2948 /* 2949 * Enable fix for read DMA FIFO overruns. 2950 * The fix is to limit the number of RX BDs 2951 * the hardware would fetch at a time. 2952 */ 2953 CSR_WRITE_4(sc, rdmareg, dmactl | 2954 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2955 } 2956 2957 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2958 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2959 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2960 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2961 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2962 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2963 /* 2964 * Allow 4KB burst length reads for non-LSO frames. 2965 * Enable 512B burst length reads for buffer descriptors. 2966 */ 2967 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2968 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2969 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2970 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2971 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2972 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2973 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2974 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2975 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2976 } 2977 /* Turn on read DMA state machine */ 2978 CSR_WRITE_4_FLUSH(sc, BGE_RDMA_MODE, val); 2979 /* 5718 step 52 */ 2980 delay(40); 2981 2982 if (sc->bge_flags & BGEF_RDMA_BUG) { 2983 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2984 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2985 if ((val & 0xFFFF) > BGE_FRAMELEN) 2986 break; 2987 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2988 break; 2989 } 2990 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2991 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2992 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2993 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2994 else 2995 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2996 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2997 } 2998 } 2999 3000 /* 5718 step 56, 57XX step 84 */ 3001 /* Turn on RX data completion state machine */ 3002 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3003 3004 /* Turn on RX data and RX BD initiator state machine */ 3005 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 3006 3007 /* 57XX step 85 */ 3008 /* Turn on Mbuf cluster free state machine */ 3009 if (!BGE_IS_5705_PLUS(sc)) 3010 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3011 3012 /* 5718 step 57, 57XX step 86 */ 3013 /* Turn on send data completion state machine */ 3014 val = BGE_SDCMODE_ENABLE; 3015 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 3016 val |= BGE_SDCMODE_CDELAY; 3017 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 3018 3019 /* 5718 step 58 */ 3020 /* Turn on send BD completion state machine */ 3021 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3022 3023 /* 57XX step 88 */ 3024 /* Turn on RX BD initiator state machine */ 3025 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3026 3027 /* 5718 step 60, 57XX step 90 */ 3028 /* Turn on send data initiator state machine */ 3029 if (sc->bge_flags & BGEF_TSO) { 3030 /* XXX: magic value from Linux driver */ 3031 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 3032 BGE_SDIMODE_HW_LSO_PRE_DMA); 3033 } else 3034 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3035 3036 /* 5718 step 61, 57XX step 91 */ 3037 /* Turn on send BD initiator state machine */ 3038 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3039 3040 /* 5718 step 62, 57XX step 92 */ 3041 /* Turn on send BD selector state machine */ 3042 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3043 3044 /* 5718 step 31, 57XX step 60 */ 3045 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 3046 /* 5718 step 32, 57XX step 61 */ 3047 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 3048 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 3049 3050 /* ack/clear link change events */ 3051 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3052 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3053 BGE_MACSTAT_LINK_CHANGED); 3054 CSR_WRITE_4(sc, BGE_MI_STS, 0); 3055 3056 /* 3057 * Enable attention when the link has changed state for 3058 * devices that use auto polling. 3059 */ 3060 if (sc->bge_flags & BGEF_FIBER_TBI) { 3061 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 3062 } else { 3063 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3064 mimode = BGE_MIMODE_500KHZ_CONST; 3065 else 3066 mimode = BGE_MIMODE_BASE; 3067 /* 5718 step 68. 5718 step 69 (optionally). */ 3068 if (BGE_IS_5700_FAMILY(sc) || 3069 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 3070 mimode |= BGE_MIMODE_AUTOPOLL; 3071 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 3072 } 3073 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3074 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 3075 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 3076 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3077 BGE_EVTENB_MI_INTERRUPT); 3078 } 3079 3080 /* 3081 * Clear any pending link state attention. 3082 * Otherwise some link state change events may be lost until attention 3083 * is cleared by bge_intr() -> bge_link_upd() sequence. 3084 * It's not necessary on newer BCM chips - perhaps enabling link 3085 * state change attentions implies clearing pending attention. 3086 */ 3087 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 3088 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 3089 BGE_MACSTAT_LINK_CHANGED); 3090 3091 /* Enable link state change attentions. */ 3092 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 3093 3094 return 0; 3095 } 3096 3097 static const struct bge_revision * 3098 bge_lookup_rev(uint32_t chipid) 3099 { 3100 const struct bge_revision *br; 3101 3102 for (br = bge_revisions; br->br_name != NULL; br++) { 3103 if (br->br_chipid == chipid) 3104 return br; 3105 } 3106 3107 for (br = bge_majorrevs; br->br_name != NULL; br++) { 3108 if (br->br_chipid == BGE_ASICREV(chipid)) 3109 return br; 3110 } 3111 3112 return NULL; 3113 } 3114 3115 static const struct bge_product * 3116 bge_lookup(const struct pci_attach_args *pa) 3117 { 3118 const struct bge_product *bp; 3119 3120 for (bp = bge_products; bp->bp_name != NULL; bp++) { 3121 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 3122 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 3123 return bp; 3124 } 3125 3126 return NULL; 3127 } 3128 3129 static uint32_t 3130 bge_chipid(const struct pci_attach_args *pa) 3131 { 3132 uint32_t id; 3133 3134 id = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 3135 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 3136 3137 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 3138 switch (PCI_PRODUCT(pa->pa_id)) { 3139 case PCI_PRODUCT_BROADCOM_BCM5717: 3140 case PCI_PRODUCT_BROADCOM_BCM5718: 3141 case PCI_PRODUCT_BROADCOM_BCM5719: 3142 case PCI_PRODUCT_BROADCOM_BCM5720: 3143 case PCI_PRODUCT_BROADCOM_BCM5725: 3144 case PCI_PRODUCT_BROADCOM_BCM5727: 3145 case PCI_PRODUCT_BROADCOM_BCM5762: 3146 case PCI_PRODUCT_BROADCOM_BCM57764: 3147 case PCI_PRODUCT_BROADCOM_BCM57767: 3148 case PCI_PRODUCT_BROADCOM_BCM57787: 3149 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3150 BGE_PCI_GEN2_PRODID_ASICREV); 3151 break; 3152 case PCI_PRODUCT_BROADCOM_BCM57761: 3153 case PCI_PRODUCT_BROADCOM_BCM57762: 3154 case PCI_PRODUCT_BROADCOM_BCM57765: 3155 case PCI_PRODUCT_BROADCOM_BCM57766: 3156 case PCI_PRODUCT_BROADCOM_BCM57781: 3157 case PCI_PRODUCT_BROADCOM_BCM57782: 3158 case PCI_PRODUCT_BROADCOM_BCM57785: 3159 case PCI_PRODUCT_BROADCOM_BCM57786: 3160 case PCI_PRODUCT_BROADCOM_BCM57791: 3161 case PCI_PRODUCT_BROADCOM_BCM57795: 3162 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3163 BGE_PCI_GEN15_PRODID_ASICREV); 3164 break; 3165 default: 3166 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 3167 BGE_PCI_PRODID_ASICREV); 3168 break; 3169 } 3170 } 3171 3172 return id; 3173 } 3174 3175 /* 3176 * Return true if MSI can be used with this device. 3177 */ 3178 static int 3179 bge_can_use_msi(struct bge_softc *sc) 3180 { 3181 int can_use_msi = 0; 3182 3183 switch (BGE_ASICREV(sc->bge_chipid)) { 3184 case BGE_ASICREV_BCM5714_A0: 3185 case BGE_ASICREV_BCM5714: 3186 /* 3187 * Apparently, MSI doesn't work when these chips are 3188 * configured in single-port mode. 3189 */ 3190 break; 3191 case BGE_ASICREV_BCM5750: 3192 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 3193 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 3194 can_use_msi = 1; 3195 break; 3196 default: 3197 if (BGE_IS_575X_PLUS(sc)) 3198 can_use_msi = 1; 3199 } 3200 return can_use_msi; 3201 } 3202 3203 /* 3204 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 3205 * against our list and return its name if we find a match. Note 3206 * that since the Broadcom controller contains VPD support, we 3207 * can get the device name string from the controller itself instead 3208 * of the compiled-in string. This is a little slow, but it guarantees 3209 * we'll always announce the right product name. 3210 */ 3211 static int 3212 bge_probe(device_t parent, cfdata_t match, void *aux) 3213 { 3214 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 3215 3216 if (bge_lookup(pa) != NULL) 3217 return 1; 3218 3219 return 0; 3220 } 3221 3222 static void 3223 bge_attach(device_t parent, device_t self, void *aux) 3224 { 3225 struct bge_softc * const sc = device_private(self); 3226 struct pci_attach_args * const pa = aux; 3227 prop_dictionary_t dict; 3228 const struct bge_product *bp; 3229 const struct bge_revision *br; 3230 pci_chipset_tag_t pc; 3231 const char *intrstr = NULL; 3232 uint32_t hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5; 3233 uint32_t command; 3234 struct ifnet *ifp; 3235 struct mii_data * const mii = &sc->bge_mii; 3236 uint32_t misccfg, mimode, macmode; 3237 void * kva; 3238 u_char eaddr[ETHER_ADDR_LEN]; 3239 pcireg_t memtype, subid, reg; 3240 bus_addr_t memaddr; 3241 uint32_t pm_ctl; 3242 bool no_seeprom; 3243 int capmask, trys; 3244 int mii_flags; 3245 int map_flags; 3246 char intrbuf[PCI_INTRSTR_LEN]; 3247 3248 bp = bge_lookup(pa); 3249 KASSERT(bp != NULL); 3250 3251 sc->sc_pc = pa->pa_pc; 3252 sc->sc_pcitag = pa->pa_tag; 3253 sc->bge_dev = self; 3254 3255 sc->bge_pa = *pa; 3256 pc = sc->sc_pc; 3257 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 3258 3259 aprint_naive(": Ethernet controller\n"); 3260 aprint_normal(": %s Ethernet\n", bp->bp_name); 3261 3262 /* 3263 * Map control/status registers. 3264 */ 3265 DPRINTFN(5, ("Map control/status regs\n")); 3266 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3267 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3268 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 3269 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 3270 3271 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 3272 aprint_error_dev(sc->bge_dev, 3273 "failed to enable memory mapping!\n"); 3274 return; 3275 } 3276 3277 DPRINTFN(5, ("pci_mem_find\n")); 3278 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 3279 switch (memtype) { 3280 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 3281 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 3282 #if 0 3283 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 3284 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 3285 &memaddr, &sc->bge_bsize) == 0) 3286 break; 3287 #else 3288 /* 3289 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3290 * system get NMI on boot (PR#48451). This problem might not be 3291 * the driver's bug but our PCI common part's bug. Until we 3292 * find a real reason, we ignore the prefetchable bit. 3293 */ 3294 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0, 3295 memtype, &memaddr, &sc->bge_bsize, &map_flags) == 0) { 3296 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3297 if (bus_space_map(pa->pa_memt, memaddr, sc->bge_bsize, 3298 map_flags, &sc->bge_bhandle) == 0) { 3299 sc->bge_btag = pa->pa_memt; 3300 break; 3301 } 3302 } 3303 #endif 3304 /* FALLTHROUGH */ 3305 default: 3306 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 3307 return; 3308 } 3309 3310 sc->bge_txrx_stopping = false; 3311 3312 /* Save various chip information. */ 3313 sc->bge_chipid = bge_chipid(pa); 3314 sc->bge_phy_addr = bge_phy_addr(sc); 3315 3316 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 3317 &sc->bge_pciecap, NULL) != 0) { 3318 /* PCIe */ 3319 sc->bge_flags |= BGEF_PCIE; 3320 /* Extract supported maximum payload size. */ 3321 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3322 sc->bge_pciecap + PCIE_DCAP); 3323 sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD); 3324 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3325 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3326 sc->bge_expmrq = 2048; 3327 else 3328 sc->bge_expmrq = 4096; 3329 bge_set_max_readrq(sc); 3330 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) { 3331 /* PCIe without PCIe cap */ 3332 sc->bge_flags |= BGEF_PCIE; 3333 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 3334 BGE_PCISTATE_PCI_BUSMODE) == 0) { 3335 /* PCI-X */ 3336 sc->bge_flags |= BGEF_PCIX; 3337 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 3338 &sc->bge_pcixcap, NULL) == 0) 3339 aprint_error_dev(sc->bge_dev, 3340 "unable to find PCIX capability\n"); 3341 } 3342 3343 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) { 3344 /* 3345 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 3346 * can clobber the chip's PCI config-space power control 3347 * registers, leaving the card in D3 powersave state. We do 3348 * not have memory-mapped registers in this state, so force 3349 * device into D0 state before starting initialization. 3350 */ 3351 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 3352 pm_ctl &= ~(PCI_PWR_D0 | PCI_PWR_D1 | PCI_PWR_D2 | PCI_PWR_D3); 3353 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 3354 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 3355 DELAY(1000); /* 27 usec is allegedly sufficient */ 3356 } 3357 3358 /* Save chipset family. */ 3359 switch (BGE_ASICREV(sc->bge_chipid)) { 3360 case BGE_ASICREV_BCM5717: 3361 case BGE_ASICREV_BCM5719: 3362 case BGE_ASICREV_BCM5720: 3363 sc->bge_flags |= BGEF_5717_PLUS; 3364 /* FALLTHROUGH */ 3365 case BGE_ASICREV_BCM5762: 3366 case BGE_ASICREV_BCM57765: 3367 case BGE_ASICREV_BCM57766: 3368 if (!BGE_IS_5717_PLUS(sc)) 3369 sc->bge_flags |= BGEF_57765_FAMILY; 3370 sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | 3371 BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; 3372 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 3373 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 3374 /* 3375 * Enable work around for DMA engine miscalculation 3376 * of TXMBUF available space. 3377 */ 3378 sc->bge_flags |= BGEF_RDMA_BUG; 3379 3380 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3381 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) { 3382 /* Jumbo frame on BCM5719 A0 does not work. */ 3383 sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; 3384 } 3385 } 3386 break; 3387 case BGE_ASICREV_BCM5755: 3388 case BGE_ASICREV_BCM5761: 3389 case BGE_ASICREV_BCM5784: 3390 case BGE_ASICREV_BCM5785: 3391 case BGE_ASICREV_BCM5787: 3392 case BGE_ASICREV_BCM57780: 3393 sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; 3394 break; 3395 case BGE_ASICREV_BCM5700: 3396 case BGE_ASICREV_BCM5701: 3397 case BGE_ASICREV_BCM5703: 3398 case BGE_ASICREV_BCM5704: 3399 sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; 3400 break; 3401 case BGE_ASICREV_BCM5714_A0: 3402 case BGE_ASICREV_BCM5780: 3403 case BGE_ASICREV_BCM5714: 3404 sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; 3405 /* FALLTHROUGH */ 3406 case BGE_ASICREV_BCM5750: 3407 case BGE_ASICREV_BCM5752: 3408 case BGE_ASICREV_BCM5906: 3409 sc->bge_flags |= BGEF_575X_PLUS; 3410 /* FALLTHROUGH */ 3411 case BGE_ASICREV_BCM5705: 3412 sc->bge_flags |= BGEF_5705_PLUS; 3413 break; 3414 } 3415 3416 /* Identify chips with APE processor. */ 3417 switch (BGE_ASICREV(sc->bge_chipid)) { 3418 case BGE_ASICREV_BCM5717: 3419 case BGE_ASICREV_BCM5719: 3420 case BGE_ASICREV_BCM5720: 3421 case BGE_ASICREV_BCM5761: 3422 case BGE_ASICREV_BCM5762: 3423 sc->bge_flags |= BGEF_APE; 3424 break; 3425 } 3426 3427 /* 3428 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3429 * not actually a MAC controller bug but an issue with the embedded 3430 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3431 */ 3432 if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) 3433 sc->bge_flags |= BGEF_40BIT_BUG; 3434 3435 /* Chips with APE need BAR2 access for APE registers/memory. */ 3436 if ((sc->bge_flags & BGEF_APE) != 0) { 3437 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 3438 #if 0 3439 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 3440 &sc->bge_apetag, &sc->bge_apehandle, NULL, 3441 &sc->bge_apesize)) { 3442 aprint_error_dev(sc->bge_dev, 3443 "couldn't map BAR2 memory\n"); 3444 return; 3445 } 3446 #else 3447 /* 3448 * Workaround for PCI prefetchable bit. Some BCM5717-5720 based 3449 * system get NMI on boot (PR#48451). This problem might not be 3450 * the driver's bug but our PCI common part's bug. Until we 3451 * find a real reason, we ignore the prefetchable bit. 3452 */ 3453 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2, 3454 memtype, &memaddr, &sc->bge_apesize, &map_flags) != 0) { 3455 aprint_error_dev(sc->bge_dev, 3456 "couldn't map BAR2 memory\n"); 3457 return; 3458 } 3459 3460 map_flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 3461 if (bus_space_map(pa->pa_memt, memaddr, 3462 sc->bge_apesize, map_flags, &sc->bge_apehandle) != 0) { 3463 aprint_error_dev(sc->bge_dev, 3464 "couldn't map BAR2 memory\n"); 3465 return; 3466 } 3467 sc->bge_apetag = pa->pa_memt; 3468 #endif 3469 3470 /* Enable APE register/memory access by host driver. */ 3471 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 3472 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3473 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3474 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3475 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 3476 3477 bge_ape_lock_init(sc); 3478 bge_ape_read_fw_ver(sc); 3479 } 3480 3481 /* Identify the chips that use an CPMU. */ 3482 if (BGE_IS_5717_PLUS(sc) || 3483 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3484 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 3486 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 3487 sc->bge_flags |= BGEF_CPMU_PRESENT; 3488 3489 /* 3490 * When using the BCM5701 in PCI-X mode, data corruption has 3491 * been observed in the first few bytes of some received packets. 3492 * Aligning the packet buffer in memory eliminates the corruption. 3493 * Unfortunately, this misaligns the packet payloads. On platforms 3494 * which do not support unaligned accesses, we will realign the 3495 * payloads by copying the received packets. 3496 */ 3497 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 3498 sc->bge_flags & BGEF_PCIX) 3499 sc->bge_flags |= BGEF_RX_ALIGNBUG; 3500 3501 if (BGE_IS_5700_FAMILY(sc)) 3502 sc->bge_flags |= BGEF_JUMBO_CAPABLE; 3503 3504 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 3505 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 3506 3507 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3508 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3509 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 3510 sc->bge_flags |= BGEF_IS_5788; 3511 3512 /* 3513 * Some controllers seem to require a special firmware to use 3514 * TSO. But the firmware is not available to FreeBSD and Linux 3515 * claims that the TSO performed by the firmware is slower than 3516 * hardware based TSO. Moreover the firmware based TSO has one 3517 * known bug which can't handle TSO if ethernet header + IP/TCP 3518 * header is greater than 80 bytes. The workaround for the TSO 3519 * bug exist but it seems it's too expensive than not using 3520 * TSO at all. Some hardware also have the TSO bug so limit 3521 * the TSO to the controllers that are not affected TSO issues 3522 * (e.g. 5755 or higher). 3523 */ 3524 if (BGE_IS_5755_PLUS(sc)) { 3525 /* 3526 * BCM5754 and BCM5787 shares the same ASIC id so 3527 * explicit device id check is required. 3528 */ 3529 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 3530 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 3531 sc->bge_flags |= BGEF_TSO; 3532 /* TSO on BCM5719 A0 does not work. */ 3533 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && 3534 (sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) 3535 sc->bge_flags &= ~BGEF_TSO; 3536 } 3537 3538 capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ 3539 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 3540 (misccfg == 0x4000 || misccfg == 0x8000)) || 3541 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3542 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3543 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 3544 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 3545 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 3546 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 3547 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 3548 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 3549 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 3550 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 3551 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 3552 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 3553 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3554 /* These chips are 10/100 only. */ 3555 capmask &= ~BMSR_EXTSTAT; 3556 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3557 } 3558 3559 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3560 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 3561 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3562 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3563 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3564 3565 /* Set various PHY bug flags. */ 3566 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3567 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3568 sc->bge_phy_flags |= BGEPHYF_CRC_BUG; 3569 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 3570 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 3571 sc->bge_phy_flags |= BGEPHYF_ADC_BUG; 3572 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3573 sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; 3574 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3575 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 3576 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 3577 sc->bge_phy_flags |= BGEPHYF_NO_3LED; 3578 if (BGE_IS_5705_PLUS(sc) && 3579 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 3580 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3581 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 3582 !BGE_IS_57765_PLUS(sc)) { 3583 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 3584 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 3585 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 3586 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 3587 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 3588 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 3589 sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; 3590 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 3591 sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; 3592 } else 3593 sc->bge_phy_flags |= BGEPHYF_BER_BUG; 3594 } 3595 3596 /* 3597 * SEEPROM check. 3598 * First check if firmware knows we do not have SEEPROM. 3599 */ 3600 if (prop_dictionary_get_bool(device_properties(self), 3601 "without-seeprom", &no_seeprom) && no_seeprom) 3602 sc->bge_flags |= BGEF_NO_EEPROM; 3603 3604 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 3605 sc->bge_flags |= BGEF_NO_EEPROM; 3606 3607 /* Now check the 'ROM failed' bit on the RX CPU */ 3608 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 3609 sc->bge_flags |= BGEF_NO_EEPROM; 3610 3611 sc->bge_asf_mode = 0; 3612 /* No ASF if APE present. */ 3613 if ((sc->bge_flags & BGEF_APE) == 0) { 3614 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3615 BGE_SRAM_DATA_SIG_MAGIC)) { 3616 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3617 BGE_HWCFG_ASF) { 3618 sc->bge_asf_mode |= ASF_ENABLE; 3619 sc->bge_asf_mode |= ASF_STACKUP; 3620 if (BGE_IS_575X_PLUS(sc)) 3621 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3622 } 3623 } 3624 } 3625 3626 int counts[PCI_INTR_TYPE_SIZE] = { 3627 [PCI_INTR_TYPE_INTX] = 1, 3628 [PCI_INTR_TYPE_MSI] = 1, 3629 [PCI_INTR_TYPE_MSIX] = 1, 3630 }; 3631 int max_type = PCI_INTR_TYPE_MSIX; 3632 3633 if (!bge_can_use_msi(sc)) { 3634 /* MSI broken, allow only INTx */ 3635 max_type = PCI_INTR_TYPE_INTX; 3636 } 3637 3638 if (pci_intr_alloc(pa, &sc->bge_pihp, counts, max_type) != 0) { 3639 aprint_error_dev(sc->bge_dev, "couldn't alloc interrupt\n"); 3640 return; 3641 } 3642 3643 DPRINTFN(5, ("pci_intr_string\n")); 3644 intrstr = pci_intr_string(pc, sc->bge_pihp[0], intrbuf, 3645 sizeof(intrbuf)); 3646 pci_intr_setattr(pc, &sc->bge_pihp[0], PCI_INTR_MPSAFE, true); 3647 DPRINTFN(5, ("pci_intr_establish\n")); 3648 sc->bge_intrhand = pci_intr_establish_xname(pc, sc->bge_pihp[0], 3649 IPL_NET, bge_intr, sc, device_xname(sc->bge_dev)); 3650 if (sc->bge_intrhand == NULL) { 3651 pci_intr_release(pc, sc->bge_pihp, 1); 3652 sc->bge_pihp = NULL; 3653 3654 aprint_error_dev(self, "couldn't establish interrupt"); 3655 if (intrstr != NULL) 3656 aprint_error(" at %s", intrstr); 3657 aprint_error("\n"); 3658 return; 3659 } 3660 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 3661 3662 switch (pci_intr_type(pc, sc->bge_pihp[0])) { 3663 case PCI_INTR_TYPE_MSIX: 3664 case PCI_INTR_TYPE_MSI: 3665 KASSERT(bge_can_use_msi(sc)); 3666 sc->bge_flags |= BGEF_MSI; 3667 break; 3668 default: 3669 /* nothing to do */ 3670 break; 3671 } 3672 3673 char wqname[MAXCOMLEN]; 3674 snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->bge_dev)); 3675 int error = workqueue_create(&sc->sc_reset_wq, wqname, 3676 bge_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK, 3677 WQ_MPSAFE); 3678 if (error) { 3679 aprint_error_dev(sc->bge_dev, 3680 "unable to create reset workqueue\n"); 3681 return; 3682 } 3683 3684 3685 /* 3686 * All controllers except BCM5700 supports tagged status but 3687 * we use tagged status only for MSI case on BCM5717. Otherwise 3688 * MSI on BCM5717 does not work. 3689 */ 3690 if (BGE_IS_57765_PLUS(sc) && sc->bge_flags & BGEF_MSI) 3691 sc->bge_flags |= BGEF_TAGGED_STATUS; 3692 3693 /* 3694 * Reset NVRAM before bge_reset(). It's required to acquire NVRAM 3695 * lock in bge_reset(). 3696 */ 3697 CSR_WRITE_4_FLUSH(sc, BGE_EE_ADDR, 3698 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 3699 delay(1000); 3700 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 3701 3702 bge_stop_fw(sc); 3703 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3704 if (bge_reset(sc)) 3705 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 3706 3707 /* 3708 * Read the hardware config word in the first 32k of NIC internal 3709 * memory, or fall back to the config word in the EEPROM. 3710 * Note: on some BCM5700 cards, this value appears to be unset. 3711 */ 3712 hwcfg = hwcfg2 = hwcfg3 = hwcfg4 = hwcfg5 = 0; 3713 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3714 BGE_SRAM_DATA_SIG_MAGIC) { 3715 uint32_t tmp; 3716 3717 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3718 tmp = bge_readmem_ind(sc, BGE_SRAM_DATA_VER) >> 3719 BGE_SRAM_DATA_VER_SHIFT; 3720 if ((0 < tmp) && (tmp < 0x100)) 3721 hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); 3722 if (sc->bge_flags & BGEF_PCIE) 3723 hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); 3724 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 3725 hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); 3726 if (BGE_IS_5717_PLUS(sc)) 3727 hwcfg5 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_5); 3728 } else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { 3729 bge_read_eeprom(sc, (void *)&hwcfg, 3730 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 3731 hwcfg = be32toh(hwcfg); 3732 } 3733 aprint_normal_dev(sc->bge_dev, 3734 "HW config %08x, %08x, %08x, %08x %08x\n", 3735 hwcfg, hwcfg2, hwcfg3, hwcfg4, hwcfg5); 3736 3737 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3738 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3739 3740 if (bge_chipinit(sc)) { 3741 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 3742 bge_release_resources(sc); 3743 return; 3744 } 3745 3746 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3747 BGE_SETBIT_FLUSH(sc, BGE_MISC_LOCAL_CTL, 3748 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUTEN1); 3749 DELAY(100); 3750 } 3751 3752 /* Set MI_MODE */ 3753 mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 3754 if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) 3755 mimode |= BGE_MIMODE_500KHZ_CONST; 3756 else 3757 mimode |= BGE_MIMODE_BASE; 3758 CSR_WRITE_4_FLUSH(sc, BGE_MI_MODE, mimode); 3759 DELAY(80); 3760 3761 /* 3762 * Get station address from the EEPROM. 3763 */ 3764 if (bge_get_eaddr(sc, eaddr)) { 3765 aprint_error_dev(sc->bge_dev, 3766 "failed to read station address\n"); 3767 bge_release_resources(sc); 3768 return; 3769 } 3770 3771 br = bge_lookup_rev(sc->bge_chipid); 3772 3773 if (br == NULL) { 3774 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 3775 sc->bge_chipid); 3776 } else { 3777 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 3778 br->br_name, sc->bge_chipid); 3779 } 3780 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 3781 3782 /* Allocate the general information block and ring buffers. */ 3783 if (pci_dma64_available(pa)) { 3784 sc->bge_dmatag = pa->pa_dmat64; 3785 sc->bge_dmatag32 = pa->pa_dmat; 3786 sc->bge_dma64 = true; 3787 } else { 3788 sc->bge_dmatag = pa->pa_dmat; 3789 sc->bge_dmatag32 = pa->pa_dmat; 3790 sc->bge_dma64 = false; 3791 } 3792 3793 /* 40bit DMA workaround */ 3794 if (sizeof(bus_addr_t) > 4) { 3795 if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { 3796 bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ 3797 3798 if (bus_dmatag_subregion(olddmatag, 0, 3799 (bus_addr_t)__MASK(40), 3800 &(sc->bge_dmatag), BUS_DMA_WAITOK) != 0) { 3801 aprint_error_dev(self, 3802 "WARNING: failed to restrict dma range," 3803 " falling back to parent bus dma range\n"); 3804 sc->bge_dmatag = olddmatag; 3805 } 3806 } 3807 } 3808 SLIST_INIT(&sc->txdma_list); 3809 DPRINTFN(5, ("bus_dmamem_alloc\n")); 3810 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 3811 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, 3812 &sc->bge_ring_rseg, BUS_DMA_WAITOK)) { 3813 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 3814 return; 3815 } 3816 DPRINTFN(5, ("bus_dmamem_map\n")); 3817 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 3818 sc->bge_ring_rseg, sizeof(struct bge_ring_data), &kva, 3819 BUS_DMA_WAITOK)) { 3820 aprint_error_dev(sc->bge_dev, 3821 "can't map DMA buffers (%zu bytes)\n", 3822 sizeof(struct bge_ring_data)); 3823 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3824 sc->bge_ring_rseg); 3825 return; 3826 } 3827 DPRINTFN(5, ("bus_dmamap_create\n")); 3828 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 3829 sizeof(struct bge_ring_data), 0, 3830 BUS_DMA_WAITOK, &sc->bge_ring_map)) { 3831 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 3832 bus_dmamem_unmap(sc->bge_dmatag, kva, 3833 sizeof(struct bge_ring_data)); 3834 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3835 sc->bge_ring_rseg); 3836 return; 3837 } 3838 DPRINTFN(5, ("bus_dmamap_load\n")); 3839 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 3840 sizeof(struct bge_ring_data), NULL, 3841 BUS_DMA_WAITOK)) { 3842 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3843 bus_dmamem_unmap(sc->bge_dmatag, kva, 3844 sizeof(struct bge_ring_data)); 3845 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 3846 sc->bge_ring_rseg); 3847 return; 3848 } 3849 3850 DPRINTFN(5, ("bzero\n")); 3851 sc->bge_rdata = (struct bge_ring_data *)kva; 3852 3853 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 3854 3855 /* Try to allocate memory for jumbo buffers. */ 3856 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3857 if (bge_alloc_jumbo_mem(sc)) { 3858 aprint_error_dev(sc->bge_dev, 3859 "jumbo buffer allocation failed\n"); 3860 } else 3861 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 3862 } 3863 3864 /* Set default tuneable values. */ 3865 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3866 sc->bge_rx_coal_ticks = 150; 3867 sc->bge_rx_max_coal_bds = 64; 3868 sc->bge_tx_coal_ticks = 300; 3869 sc->bge_tx_max_coal_bds = 400; 3870 if (BGE_IS_5705_PLUS(sc)) { 3871 sc->bge_tx_coal_ticks = (12 * 5); 3872 sc->bge_tx_max_coal_bds = (12 * 5); 3873 aprint_verbose_dev(sc->bge_dev, 3874 "setting short Tx thresholds\n"); 3875 } 3876 3877 if (BGE_IS_5717_PLUS(sc)) 3878 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3879 else if (BGE_IS_5705_PLUS(sc)) 3880 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3881 else 3882 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3883 3884 sc->sc_mcast_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 3885 sc->sc_intr_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 3886 3887 /* Set up ifnet structure */ 3888 ifp = &sc->ethercom.ec_if; 3889 ifp->if_softc = sc; 3890 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3891 ifp->if_extflags = IFEF_MPSAFE; 3892 ifp->if_ioctl = bge_ioctl; 3893 ifp->if_stop = bge_stop; 3894 ifp->if_start = bge_start; 3895 ifp->if_init = bge_init; 3896 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 3897 IFQ_SET_READY(&ifp->if_snd); 3898 DPRINTFN(5, ("strcpy if_xname\n")); 3899 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 3900 3901 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3902 sc->ethercom.ec_if.if_capabilities |= 3903 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 3904 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 3905 sc->ethercom.ec_if.if_capabilities |= 3906 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 3907 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 3908 #endif 3909 sc->ethercom.ec_capabilities |= 3910 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 3911 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 3912 3913 if (sc->bge_flags & BGEF_TSO) 3914 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 3915 3916 /* 3917 * Do MII setup. 3918 */ 3919 DPRINTFN(5, ("mii setup\n")); 3920 mii->mii_ifp = ifp; 3921 mii->mii_readreg = bge_miibus_readreg; 3922 mii->mii_writereg = bge_miibus_writereg; 3923 mii->mii_statchg = bge_miibus_statchg; 3924 3925 /* 3926 * Figure out what sort of media we have by checking the hardware 3927 * config word. Note: on some BCM5700 cards, this value appears to be 3928 * unset. If that's the case, we have to rely on identifying the NIC 3929 * by its PCI subsystem ID, as we do below for the SysKonnect SK-9D41. 3930 * The SysKonnect SK-9D41 is a 1000baseSX card. 3931 */ 3932 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3933 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3934 if (BGE_IS_5705_PLUS(sc)) { 3935 sc->bge_flags |= BGEF_FIBER_MII; 3936 sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; 3937 } else 3938 sc->bge_flags |= BGEF_FIBER_TBI; 3939 } 3940 3941 /* Set bge_phy_flags before prop_dictionary_set_uint32() */ 3942 if (BGE_IS_JUMBO_CAPABLE(sc)) 3943 sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; 3944 3945 /* set phyflags and chipid before mii_attach() */ 3946 dict = device_properties(self); 3947 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); 3948 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 3949 3950 macmode = CSR_READ_4(sc, BGE_MAC_MODE); 3951 macmode &= ~BGE_MACMODE_PORTMODE; 3952 /* Initialize ifmedia structures. */ 3953 if (sc->bge_flags & BGEF_FIBER_TBI) { 3954 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, 3955 macmode | BGE_PORTMODE_TBI); 3956 DELAY(40); 3957 3958 struct ifmedia * const ifm = &sc->bge_ifmedia; 3959 sc->ethercom.ec_ifmedia = ifm; 3960 3961 ifmedia_init_with_lock(ifm, IFM_IMASK, 3962 bge_ifmedia_upd, bge_ifmedia_sts, sc->sc_intr_lock); 3963 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX, 0, NULL); 3964 ifmedia_add(ifm, IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 3965 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 3966 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 3967 /* Pretend the user requested this setting */ 3968 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3969 } else { 3970 uint16_t phyreg; 3971 int rv; 3972 /* 3973 * Do transceiver setup and tell the firmware the 3974 * driver is down so we can try to get access the 3975 * probe if ASF is running. Retry a couple of times 3976 * if we get a conflict with the ASF firmware accessing 3977 * the PHY. 3978 */ 3979 if (sc->bge_flags & BGEF_FIBER_MII) 3980 macmode |= BGE_PORTMODE_GMII; 3981 else 3982 macmode |= BGE_PORTMODE_MII; 3983 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, macmode); 3984 DELAY(40); 3985 3986 /* 3987 * Do transceiver setup and tell the firmware the 3988 * driver is down so we can try to get access the 3989 * probe if ASF is running. Retry a couple of times 3990 * if we get a conflict with the ASF firmware accessing 3991 * the PHY. 3992 */ 3993 trys = 0; 3994 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3995 sc->ethercom.ec_mii = mii; 3996 ifmedia_init_with_lock(&mii->mii_media, 0, bge_ifmedia_upd, 3997 bge_ifmedia_sts, sc->sc_intr_lock); 3998 mii_flags = MIIF_DOPAUSE; 3999 if (sc->bge_flags & BGEF_FIBER_MII) 4000 mii_flags |= MIIF_HAVEFIBER; 4001 again: 4002 bge_asf_driver_up(sc); 4003 mutex_enter(sc->sc_intr_lock); 4004 rv = bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 4005 MII_BMCR, &phyreg); 4006 if ((rv != 0) || ((phyreg & BMCR_PDOWN) != 0)) { 4007 int i; 4008 4009 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 4010 MII_BMCR, BMCR_RESET); 4011 /* Wait up to 500ms for it to complete. */ 4012 for (i = 0; i < 500; i++) { 4013 bge_miibus_readreg(sc->bge_dev, 4014 sc->bge_phy_addr, MII_BMCR, &phyreg); 4015 if ((phyreg & BMCR_RESET) == 0) 4016 break; 4017 DELAY(1000); 4018 } 4019 } 4020 mutex_exit(sc->sc_intr_lock); 4021 4022 mii_attach(sc->bge_dev, mii, capmask, sc->bge_phy_addr, 4023 MII_OFFSET_ANY, mii_flags); 4024 4025 if (LIST_EMPTY(&mii->mii_phys) && (trys++ < 4)) 4026 goto again; 4027 4028 if (LIST_EMPTY(&mii->mii_phys)) { 4029 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 4030 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 4031 0, NULL); 4032 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 4033 } else 4034 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 4035 4036 /* 4037 * Now tell the firmware we are going up after probing the PHY 4038 */ 4039 if (sc->bge_asf_mode & ASF_STACKUP) 4040 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4041 } 4042 4043 /* 4044 * Call MI attach routine. 4045 */ 4046 DPRINTFN(5, ("if_initialize\n")); 4047 if_initialize(ifp); 4048 ifp->if_percpuq = if_percpuq_create(ifp); 4049 if_deferred_start_init(ifp, NULL); 4050 if_register(ifp); 4051 4052 DPRINTFN(5, ("ether_ifattach\n")); 4053 ether_ifattach(ifp, eaddr); 4054 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 4055 4056 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 4057 RND_TYPE_NET, RND_FLAG_DEFAULT); 4058 #ifdef BGE_EVENT_COUNTERS 4059 /* 4060 * Attach event counters. 4061 */ 4062 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 4063 NULL, device_xname(sc->bge_dev), "intr"); 4064 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious, EVCNT_TYPE_INTR, 4065 NULL, device_xname(sc->bge_dev), "intr_spurious"); 4066 evcnt_attach_dynamic(&sc->bge_ev_intr_spurious2, EVCNT_TYPE_INTR, 4067 NULL, device_xname(sc->bge_dev), "intr_spurious2"); 4068 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 4069 NULL, device_xname(sc->bge_dev), "tx_xoff"); 4070 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 4071 NULL, device_xname(sc->bge_dev), "tx_xon"); 4072 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 4073 NULL, device_xname(sc->bge_dev), "rx_xoff"); 4074 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 4075 NULL, device_xname(sc->bge_dev), "rx_xon"); 4076 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 4077 NULL, device_xname(sc->bge_dev), "rx_macctl"); 4078 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 4079 NULL, device_xname(sc->bge_dev), "xoffentered"); 4080 #endif /* BGE_EVENT_COUNTERS */ 4081 DPRINTFN(5, ("callout_init\n")); 4082 callout_init(&sc->bge_timeout, CALLOUT_MPSAFE); 4083 callout_setfunc(&sc->bge_timeout, bge_tick, sc); 4084 4085 if (pmf_device_register(self, NULL, NULL)) 4086 pmf_class_network_register(self, ifp); 4087 else 4088 aprint_error_dev(self, "couldn't establish power handler\n"); 4089 4090 bge_sysctl_init(sc); 4091 4092 #ifdef BGE_DEBUG 4093 bge_debug_info(sc); 4094 #endif 4095 4096 sc->bge_attached = true; 4097 } 4098 4099 /* 4100 * Stop all chip I/O so that the kernel's probe routines don't 4101 * get confused by errant DMAs when rebooting. 4102 */ 4103 static int 4104 bge_detach(device_t self, int flags __unused) 4105 { 4106 struct bge_softc * const sc = device_private(self); 4107 struct ifnet * const ifp = &sc->ethercom.ec_if; 4108 4109 if (!sc->bge_attached) 4110 return 0; 4111 4112 IFNET_LOCK(ifp); 4113 4114 /* Stop the interface. Callouts are stopped in it. */ 4115 bge_stop(ifp, 1); 4116 sc->bge_detaching = true; 4117 4118 IFNET_UNLOCK(ifp); 4119 4120 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 4121 4122 ether_ifdetach(ifp); 4123 if_detach(ifp); 4124 4125 /* Delete all remaining media. */ 4126 ifmedia_fini(&sc->bge_mii.mii_media); 4127 4128 bge_release_resources(sc); 4129 4130 return 0; 4131 } 4132 4133 static void 4134 bge_release_resources(struct bge_softc *sc) 4135 { 4136 4137 /* Detach sysctl */ 4138 if (sc->bge_log != NULL) 4139 sysctl_teardown(&sc->bge_log); 4140 4141 callout_destroy(&sc->bge_timeout); 4142 4143 #ifdef BGE_EVENT_COUNTERS 4144 /* Detach event counters. */ 4145 evcnt_detach(&sc->bge_ev_intr); 4146 evcnt_detach(&sc->bge_ev_intr_spurious); 4147 evcnt_detach(&sc->bge_ev_intr_spurious2); 4148 evcnt_detach(&sc->bge_ev_tx_xoff); 4149 evcnt_detach(&sc->bge_ev_tx_xon); 4150 evcnt_detach(&sc->bge_ev_rx_xoff); 4151 evcnt_detach(&sc->bge_ev_rx_xon); 4152 evcnt_detach(&sc->bge_ev_rx_macctl); 4153 evcnt_detach(&sc->bge_ev_xoffentered); 4154 #endif /* BGE_EVENT_COUNTERS */ 4155 4156 /* Disestablish the interrupt handler */ 4157 if (sc->bge_intrhand != NULL) { 4158 pci_intr_disestablish(sc->sc_pc, sc->bge_intrhand); 4159 pci_intr_release(sc->sc_pc, sc->bge_pihp, 1); 4160 sc->bge_intrhand = NULL; 4161 } 4162 4163 if (sc->bge_cdata.bge_jumbo_buf != NULL) 4164 bge_free_jumbo_mem(sc); 4165 4166 if (sc->bge_dmatag != NULL) { 4167 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 4168 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 4169 bus_dmamem_unmap(sc->bge_dmatag, (void *)sc->bge_rdata, 4170 sizeof(struct bge_ring_data)); 4171 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, 4172 sc->bge_ring_rseg); 4173 } 4174 4175 /* Unmap the device registers */ 4176 if (sc->bge_bsize != 0) { 4177 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 4178 sc->bge_bsize = 0; 4179 } 4180 4181 /* Unmap the APE registers */ 4182 if (sc->bge_apesize != 0) { 4183 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 4184 sc->bge_apesize); 4185 sc->bge_apesize = 0; 4186 } 4187 if (sc->sc_intr_lock) { 4188 mutex_obj_free(sc->sc_intr_lock); 4189 sc->sc_intr_lock = NULL; 4190 } 4191 if (sc->sc_mcast_lock) { 4192 mutex_obj_free(sc->sc_mcast_lock); 4193 sc->sc_mcast_lock = NULL; 4194 } 4195 } 4196 4197 static int 4198 bge_reset(struct bge_softc *sc) 4199 { 4200 uint32_t cachesize, command; 4201 uint32_t reset, mac_mode, mac_mode_mask; 4202 pcireg_t devctl, reg; 4203 int i, val; 4204 void (*write_op)(struct bge_softc *, int, int); 4205 4206 /* Make mask for BGE_MAC_MODE register. */ 4207 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4208 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4209 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4210 /* Keep mac_mode_mask's bits of BGE_MAC_MODE register into mac_mode */ 4211 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4212 4213 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4214 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 4215 if (sc->bge_flags & BGEF_PCIE) 4216 write_op = bge_writemem_direct; 4217 else 4218 write_op = bge_writemem_ind; 4219 } else 4220 write_op = bge_writereg_ind; 4221 4222 /* 57XX step 4 */ 4223 /* Acquire the NVM lock */ 4224 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && 4225 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 4226 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 4227 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4228 for (i = 0; i < 8000; i++) { 4229 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4230 BGE_NVRAMSWARB_GNT1) 4231 break; 4232 DELAY(20); 4233 } 4234 if (i == 8000) { 4235 printf("%s: NVRAM lock timedout!\n", 4236 device_xname(sc->bge_dev)); 4237 } 4238 } 4239 4240 /* Take APE lock when performing reset. */ 4241 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4242 4243 /* 57XX step 3 */ 4244 /* Save some important PCI state. */ 4245 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 4246 /* 5718 reset step 3 */ 4247 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4248 4249 /* 5718 reset step 5, 57XX step 5b-5d */ 4250 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4251 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4252 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4253 4254 /* XXX ???: Disable fastboot on controllers that support it. */ 4255 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 4256 BGE_IS_5755_PLUS(sc)) 4257 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 4258 4259 /* 5718 reset step 2, 57XX step 6 */ 4260 /* 4261 * Write the magic number to SRAM at offset 0xB50. 4262 * When firmware finishes its initialization it will 4263 * write ~BGE_MAGIC_NUMBER to the same location. 4264 */ 4265 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4266 4267 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 4268 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 4269 val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 4270 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 4271 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val); 4272 } 4273 4274 /* 5718 reset step 6, 57XX step 7 */ 4275 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4276 /* 4277 * XXX: from FreeBSD/Linux; no documentation 4278 */ 4279 if (sc->bge_flags & BGEF_PCIE) { 4280 if ((BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) && 4281 !BGE_IS_57765_PLUS(sc) && 4282 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == 4283 (BGE_PHY_PCIE_LTASS_MODE | BGE_PHY_PCIE_SCRAM_MODE))) { 4284 /* PCI Express 1.0 system */ 4285 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG, 4286 BGE_PHY_PCIE_SCRAM_MODE); 4287 } 4288 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4289 /* 4290 * Prevent PCI Express link training 4291 * during global reset. 4292 */ 4293 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4294 reset |= (1 << 29); 4295 } 4296 } 4297 4298 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4299 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 4300 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4301 i | BGE_VCPU_STATUS_DRV_RESET); 4302 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4303 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4304 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4305 } 4306 4307 /* 4308 * Set GPHY Power Down Override to leave GPHY 4309 * powered up in D0 uninitialized. 4310 */ 4311 if (BGE_IS_5705_PLUS(sc) && 4312 (sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4313 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4314 4315 /* Issue global reset */ 4316 write_op(sc, BGE_MISC_CFG, reset); 4317 4318 /* 5718 reset step 7, 57XX step 8 */ 4319 if (sc->bge_flags & BGEF_PCIE) 4320 delay(100*1000); /* too big */ 4321 else 4322 delay(1000); 4323 4324 if (sc->bge_flags & BGEF_PCIE) { 4325 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4326 DELAY(500000); 4327 /* XXX: Magic Numbers */ 4328 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4329 BGE_PCI_UNKNOWN0); 4330 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4331 BGE_PCI_UNKNOWN0, 4332 reg | (1 << 15)); 4333 } 4334 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4335 sc->bge_pciecap + PCIE_DCSR); 4336 /* Clear enable no snoop and disable relaxed ordering. */ 4337 devctl &= ~(PCIE_DCSR_ENA_RELAX_ORD | 4338 PCIE_DCSR_ENA_NO_SNOOP); 4339 4340 /* Set PCIE max payload size to 128 for older PCIe devices */ 4341 if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) 4342 devctl &= ~(0x00e0); 4343 /* Clear device status register. Write 1b to clear */ 4344 devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED 4345 | PCIE_DCSR_NFED | PCIE_DCSR_CED; 4346 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 4347 sc->bge_pciecap + PCIE_DCSR, devctl); 4348 bge_set_max_readrq(sc); 4349 } 4350 4351 /* From Linux: dummy read to flush PCI posted writes */ 4352 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 4353 4354 /* 4355 * Reset some of the PCI state that got zapped by reset 4356 * To modify the PCISTATE register, BGE_PCIMISCCTL_PCISTATE_RW must be 4357 * set, too. 4358 */ 4359 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 4360 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4361 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 4362 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4363 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4364 (sc->bge_flags & BGEF_PCIX) != 0) 4365 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4366 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4367 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4368 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4369 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4370 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE, val); 4371 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 4372 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 4373 4374 /* 57xx step 11: disable PCI-X Relaxed Ordering. */ 4375 if (sc->bge_flags & BGEF_PCIX) { 4376 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4377 + PCIX_CMD); 4378 /* Set max memory read byte count to 2K */ 4379 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 4380 reg &= ~PCIX_CMD_BYTECNT_MASK; 4381 reg |= PCIX_CMD_BCNT_2048; 4382 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ 4383 /* 4384 * For 5704, set max outstanding split transaction 4385 * field to 0 (0 means it supports 1 request) 4386 */ 4387 reg &= ~(PCIX_CMD_SPLTRANS_MASK 4388 | PCIX_CMD_BYTECNT_MASK); 4389 reg |= PCIX_CMD_BCNT_2048; 4390 } 4391 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 4392 + PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); 4393 } 4394 4395 /* 5718 reset step 10, 57XX step 12 */ 4396 /* Enable memory arbiter. */ 4397 if (BGE_IS_5714_FAMILY(sc)) { 4398 val = CSR_READ_4(sc, BGE_MARB_MODE); 4399 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4400 } else 4401 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4402 4403 /* XXX 5721, 5751 and 5752 */ 4404 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 4405 /* Step 19: */ 4406 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 4407 /* Step 20: */ 4408 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 4409 } 4410 4411 /* 5718 reset step 12, 57XX step 15 and 16 */ 4412 /* Fix up byte swapping */ 4413 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 4414 4415 /* 5718 reset step 13, 57XX step 17 */ 4416 /* Poll until the firmware initialization is complete */ 4417 bge_poll_fw(sc); 4418 4419 /* 57XX step 21 */ 4420 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 4421 pcireg_t msidata; 4422 4423 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 4424 BGE_PCI_MSI_DATA); 4425 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 4426 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 4427 msidata); 4428 } 4429 4430 /* 57XX step 18 */ 4431 /* Write mac mode. */ 4432 val = CSR_READ_4(sc, BGE_MAC_MODE); 4433 /* Restore mac_mode_mask's bits using mac_mode */ 4434 val = (val & ~mac_mode_mask) | mac_mode; 4435 CSR_WRITE_4_FLUSH(sc, BGE_MAC_MODE, val); 4436 DELAY(40); 4437 4438 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4439 4440 /* 4441 * The 5704 in TBI mode apparently needs some special 4442 * adjustment to insure the SERDES drive level is set 4443 * to 1.2V. 4444 */ 4445 if (sc->bge_flags & BGEF_FIBER_TBI && 4446 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4447 uint32_t serdescfg; 4448 4449 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 4450 serdescfg = (serdescfg & ~0xFFF) | 0x880; 4451 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 4452 } 4453 4454 if (sc->bge_flags & BGEF_PCIE && 4455 !BGE_IS_57765_PLUS(sc) && 4456 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4457 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 4458 uint32_t v; 4459 4460 /* Enable PCI Express bug fix */ 4461 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG); 4462 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG, 4463 v | BGE_TLP_DATA_FIFO_PROTECT); 4464 } 4465 4466 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 4467 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4468 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4469 4470 return 0; 4471 } 4472 4473 /* 4474 * Frame reception handling. This is called if there's a frame 4475 * on the receive return list. 4476 * 4477 * Note: we have to be able to handle two possibilities here: 4478 * 1) the frame is from the jumbo receive ring 4479 * 2) the frame is from the standard receive ring 4480 */ 4481 4482 static void 4483 bge_rxeof(struct bge_softc *sc) 4484 { 4485 struct ifnet * const ifp = &sc->ethercom.ec_if; 4486 uint16_t rx_prod, rx_cons; 4487 int stdcnt = 0, jumbocnt = 0; 4488 bus_dmamap_t dmamap; 4489 bus_addr_t offset, toff; 4490 bus_size_t tlen; 4491 int tosync; 4492 4493 KASSERT(mutex_owned(sc->sc_intr_lock)); 4494 4495 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4496 offsetof(struct bge_ring_data, bge_status_block), 4497 sizeof(struct bge_status_block), 4498 BUS_DMASYNC_POSTREAD); 4499 4500 rx_cons = sc->bge_rx_saved_considx; 4501 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 4502 4503 /* Nothing to do */ 4504 if (rx_cons == rx_prod) 4505 return; 4506 4507 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 4508 tosync = rx_prod - rx_cons; 4509 4510 if (tosync != 0) 4511 rnd_add_uint32(&sc->rnd_source, tosync); 4512 4513 toff = offset + (rx_cons * sizeof(struct bge_rx_bd)); 4514 4515 if (tosync < 0) { 4516 tlen = (sc->bge_return_ring_cnt - rx_cons) * 4517 sizeof(struct bge_rx_bd); 4518 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4519 toff, tlen, BUS_DMASYNC_POSTREAD); 4520 tosync = rx_prod; 4521 toff = offset; 4522 } 4523 4524 if (tosync != 0) { 4525 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4526 toff, tosync * sizeof(struct bge_rx_bd), 4527 BUS_DMASYNC_POSTREAD); 4528 } 4529 4530 while (rx_cons != rx_prod) { 4531 struct bge_rx_bd *cur_rx; 4532 uint32_t rxidx; 4533 struct mbuf *m = NULL; 4534 4535 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 4536 4537 rxidx = cur_rx->bge_idx; 4538 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4539 4540 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4541 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4542 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4543 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 4544 jumbocnt++; 4545 bus_dmamap_sync(sc->bge_dmatag, 4546 sc->bge_cdata.bge_rx_jumbo_map, 4547 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 4548 BGE_JLEN, BUS_DMASYNC_POSTREAD); 4549 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4550 if_statinc(ifp, if_ierrors); 4551 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4552 continue; 4553 } 4554 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 4555 NULL) == ENOBUFS) { 4556 if_statinc(ifp, if_ierrors); 4557 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 4558 continue; 4559 } 4560 } else { 4561 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4562 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 4563 4564 stdcnt++; 4565 sc->bge_std_cnt--; 4566 4567 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 4568 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 4569 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 4570 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4571 4572 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4573 m_free(m); 4574 if_statinc(ifp, if_ierrors); 4575 continue; 4576 } 4577 } 4578 4579 #ifndef __NO_STRICT_ALIGNMENT 4580 /* 4581 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 4582 * the Rx buffer has the layer-2 header unaligned. 4583 * If our CPU requires alignment, re-align by copying. 4584 */ 4585 if (sc->bge_flags & BGEF_RX_ALIGNBUG) { 4586 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 4587 cur_rx->bge_len); 4588 m->m_data += ETHER_ALIGN; 4589 } 4590 #endif 4591 4592 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4593 m_set_rcvif(m, ifp); 4594 4595 bge_rxcsum(sc, cur_rx, m); 4596 4597 /* 4598 * If we received a packet with a vlan tag, pass it 4599 * to vlan_input() instead of ether_input(). 4600 */ 4601 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 4602 vlan_set_tag(m, cur_rx->bge_vlan_tag); 4603 4604 if_percpuq_enqueue(ifp->if_percpuq, m); 4605 } 4606 4607 sc->bge_rx_saved_considx = rx_cons; 4608 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4609 if (stdcnt) 4610 bge_fill_rx_ring_std(sc); 4611 if (jumbocnt) 4612 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 4613 } 4614 4615 static void 4616 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4617 { 4618 4619 if (BGE_IS_57765_PLUS(sc)) { 4620 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4621 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4622 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4623 if ((cur_rx->bge_error_flag & 4624 BGE_RXERRFLAG_IP_CSUM_NOK) != 0) 4625 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4626 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4627 m->m_pkthdr.csum_data = 4628 cur_rx->bge_tcp_udp_csum; 4629 m->m_pkthdr.csum_flags |= 4630 (M_CSUM_TCPv4 | M_CSUM_UDPv4 |M_CSUM_DATA); 4631 } 4632 } 4633 } else { 4634 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) 4635 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 4636 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 4637 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 4638 /* 4639 * Rx transport checksum-offload may also 4640 * have bugs with packets which, when transmitted, 4641 * were `runts' requiring padding. 4642 */ 4643 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4644 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 4645 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 4646 m->m_pkthdr.csum_data = 4647 cur_rx->bge_tcp_udp_csum; 4648 m->m_pkthdr.csum_flags |= 4649 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_DATA); 4650 } 4651 } 4652 } 4653 4654 static void 4655 bge_txeof(struct bge_softc *sc) 4656 { 4657 struct ifnet * const ifp = &sc->ethercom.ec_if; 4658 struct bge_tx_bd *cur_tx = NULL; 4659 struct txdmamap_pool_entry *dma; 4660 bus_addr_t offset, toff; 4661 bus_size_t tlen; 4662 int tosync; 4663 struct mbuf *m; 4664 4665 KASSERT(mutex_owned(sc->sc_intr_lock)); 4666 4667 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4668 offsetof(struct bge_ring_data, bge_status_block), 4669 sizeof(struct bge_status_block), 4670 BUS_DMASYNC_POSTREAD); 4671 4672 const uint16_t hw_cons_idx = 4673 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx; 4674 offset = offsetof(struct bge_ring_data, bge_tx_ring); 4675 tosync = hw_cons_idx - sc->bge_tx_saved_considx; 4676 4677 if (tosync != 0) 4678 rnd_add_uint32(&sc->rnd_source, tosync); 4679 4680 toff = offset + (sc->bge_tx_saved_considx * sizeof(struct bge_tx_bd)); 4681 4682 if (tosync < 0) { 4683 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 4684 sizeof(struct bge_tx_bd); 4685 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4686 toff, tlen, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4687 tosync = hw_cons_idx; 4688 toff = offset; 4689 } 4690 4691 if (tosync != 0) { 4692 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4693 toff, tosync * sizeof(struct bge_tx_bd), 4694 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4695 } 4696 4697 /* 4698 * Go through our tx ring and free mbufs for those 4699 * frames that have been sent. 4700 */ 4701 while (sc->bge_tx_saved_considx != hw_cons_idx) { 4702 uint32_t idx = sc->bge_tx_saved_considx; 4703 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 4704 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4705 if_statinc(ifp, if_opackets); 4706 m = sc->bge_cdata.bge_tx_chain[idx]; 4707 if (m != NULL) { 4708 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4709 dma = sc->txdma[idx]; 4710 if (dma->is_dma32) { 4711 bus_dmamap_sync(sc->bge_dmatag32, dma->dmamap32, 4712 0, dma->dmamap32->dm_mapsize, 4713 BUS_DMASYNC_POSTWRITE); 4714 bus_dmamap_unload( 4715 sc->bge_dmatag32, dma->dmamap32); 4716 } else { 4717 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 4718 0, dma->dmamap->dm_mapsize, 4719 BUS_DMASYNC_POSTWRITE); 4720 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 4721 } 4722 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 4723 sc->txdma[idx] = NULL; 4724 4725 m_freem(m); 4726 } 4727 sc->bge_txcnt--; 4728 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4729 sc->bge_tx_sending = false; 4730 } 4731 } 4732 4733 static int 4734 bge_intr(void *xsc) 4735 { 4736 struct bge_softc * const sc = xsc; 4737 struct ifnet * const ifp = &sc->ethercom.ec_if; 4738 uint32_t pcistate, statusword, statustag; 4739 uint32_t intrmask = BGE_PCISTATE_INTR_NOT_ACTIVE; 4740 4741 /* 5717 and newer chips have no BGE_PCISTATE_INTR_NOT_ACTIVE bit */ 4742 if (BGE_IS_5717_PLUS(sc)) 4743 intrmask = 0; 4744 4745 mutex_enter(sc->sc_intr_lock); 4746 if (sc->bge_txrx_stopping) { 4747 mutex_exit(sc->sc_intr_lock); 4748 return 1; 4749 } 4750 4751 /* 4752 * It is possible for the interrupt to arrive before 4753 * the status block is updated prior to the interrupt. 4754 * Reading the PCI State register will confirm whether the 4755 * interrupt is ours and will flush the status block. 4756 */ 4757 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE); 4758 4759 /* read status word from status block */ 4760 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4761 offsetof(struct bge_ring_data, bge_status_block), 4762 sizeof(struct bge_status_block), 4763 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4764 statusword = sc->bge_rdata->bge_status_block.bge_status; 4765 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 4766 4767 if (sc->bge_flags & BGEF_TAGGED_STATUS) { 4768 if (sc->bge_lasttag == statustag && 4769 (~pcistate & intrmask)) { 4770 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious); 4771 mutex_exit(sc->sc_intr_lock); 4772 return 0; 4773 } 4774 sc->bge_lasttag = statustag; 4775 } else { 4776 if (!(statusword & BGE_STATFLAG_UPDATED) && 4777 !(~pcistate & intrmask)) { 4778 BGE_EVCNT_INCR(sc->bge_ev_intr_spurious2); 4779 mutex_exit(sc->sc_intr_lock); 4780 return 0; 4781 } 4782 statustag = 0; 4783 } 4784 /* Ack interrupt and stop others from occurring. */ 4785 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 4786 BGE_EVCNT_INCR(sc->bge_ev_intr); 4787 4788 /* clear status word */ 4789 sc->bge_rdata->bge_status_block.bge_status = 0; 4790 4791 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 4792 offsetof(struct bge_ring_data, bge_status_block), 4793 sizeof(struct bge_status_block), 4794 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4795 4796 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4797 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 4798 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 4799 bge_link_upd(sc); 4800 4801 /* Check RX return ring producer/consumer */ 4802 bge_rxeof(sc); 4803 4804 /* Check TX ring producer/consumer */ 4805 bge_txeof(sc); 4806 4807 if (sc->bge_pending_rxintr_change) { 4808 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 4809 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 4810 4811 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 4812 DELAY(10); 4813 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4814 4815 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 4816 DELAY(10); 4817 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4818 4819 sc->bge_pending_rxintr_change = false; 4820 } 4821 bge_handle_events(sc); 4822 4823 /* Re-enable interrupts. */ 4824 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, statustag); 4825 4826 if_schedule_deferred_start(ifp); 4827 4828 mutex_exit(sc->sc_intr_lock); 4829 4830 return 1; 4831 } 4832 4833 static void 4834 bge_asf_driver_up(struct bge_softc *sc) 4835 { 4836 if (sc->bge_asf_mode & ASF_STACKUP) { 4837 /* Send ASF heartbeat approx. every 2s */ 4838 if (sc->bge_asf_count) 4839 sc->bge_asf_count --; 4840 else { 4841 sc->bge_asf_count = 2; 4842 4843 bge_wait_for_event_ack(sc); 4844 4845 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4846 BGE_FW_CMD_DRV_ALIVE3); 4847 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4848 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4849 BGE_FW_HB_TIMEOUT_SEC); 4850 CSR_WRITE_4_FLUSH(sc, BGE_RX_CPU_EVENT, 4851 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4852 BGE_RX_CPU_DRV_EVENT); 4853 } 4854 } 4855 } 4856 4857 static void 4858 bge_tick(void *xsc) 4859 { 4860 struct bge_softc * const sc = xsc; 4861 struct ifnet * const ifp = &sc->ethercom.ec_if; 4862 struct mii_data * const mii = &sc->bge_mii; 4863 4864 mutex_enter(sc->sc_intr_lock); 4865 4866 if (BGE_IS_5705_PLUS(sc)) 4867 bge_stats_update_regs(sc); 4868 else 4869 bge_stats_update(sc); 4870 4871 if (sc->bge_flags & BGEF_FIBER_TBI) { 4872 /* 4873 * Since in TBI mode auto-polling can't be used we should poll 4874 * link status manually. Here we register pending link event 4875 * and trigger interrupt. 4876 */ 4877 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4878 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4879 } else { 4880 /* 4881 * Do not touch PHY if we have link up. This could break 4882 * IPMI/ASF mode or produce extra input errors. 4883 * (extra input errors was reported for bcm5701 & bcm5704). 4884 */ 4885 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4886 mii_tick(mii); 4887 } 4888 } 4889 4890 bge_asf_driver_up(sc); 4891 4892 const bool ok = bge_watchdog_tick(ifp); 4893 if (ok) 4894 callout_schedule(&sc->bge_timeout, hz); 4895 mutex_exit(sc->sc_intr_lock); 4896 } 4897 4898 static void 4899 bge_stats_update_regs(struct bge_softc *sc) 4900 { 4901 struct ifnet * const ifp = &sc->ethercom.ec_if; 4902 4903 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 4904 4905 if_statadd_ref(ifp, nsr, if_collisions, 4906 CSR_READ_4(sc, BGE_MAC_STATS + 4907 offsetof(struct bge_mac_stats_regs, etherStatsCollisions))); 4908 4909 /* 4910 * On BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0, 4911 * RXLP_LOCSTAT_IFIN_DROPS includes unwanted multicast frames 4912 * (silicon bug). There's no reliable workaround so just 4913 * ignore the counter 4914 */ 4915 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 4916 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4917 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) { 4918 if_statadd_ref(ifp, nsr, if_ierrors, 4919 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4920 } 4921 if_statadd_ref(ifp, nsr, if_ierrors, 4922 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS)); 4923 if_statadd_ref(ifp, nsr, if_ierrors, 4924 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS)); 4925 4926 IF_STAT_PUTREF(ifp); 4927 4928 if (sc->bge_flags & BGEF_RDMA_BUG) { 4929 uint32_t val, ucast, mcast, bcast; 4930 4931 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 4932 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 4933 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 4934 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 4935 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 4936 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 4937 4938 /* 4939 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4940 * frames, it's safe to disable workaround for DMA engine's 4941 * miscalculation of TXMBUF space. 4942 */ 4943 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 4944 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4945 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 4946 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4947 else 4948 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4949 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4950 sc->bge_flags &= ~BGEF_RDMA_BUG; 4951 } 4952 } 4953 } 4954 4955 static void 4956 bge_stats_update(struct bge_softc *sc) 4957 { 4958 struct ifnet * const ifp = &sc->ethercom.ec_if; 4959 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4960 4961 #define READ_STAT(sc, stats, stat) \ 4962 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4963 4964 uint64_t collisions = 4965 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 4966 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 4967 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 4968 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)); 4969 4970 if_statadd(ifp, if_collisions, collisions - sc->bge_if_collisions); 4971 sc->bge_if_collisions = collisions; 4972 4973 4974 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 4975 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 4976 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 4977 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 4978 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 4979 READ_STAT(sc, stats, 4980 xoffPauseFramesReceived.bge_addr_lo)); 4981 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 4982 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 4983 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 4984 READ_STAT(sc, stats, 4985 macControlFramesReceived.bge_addr_lo)); 4986 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 4987 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 4988 4989 #undef READ_STAT 4990 } 4991 4992 /* 4993 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4994 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4995 * but when such padded frames employ the bge IP/TCP checksum offload, 4996 * the hardware checksum assist gives incorrect results (possibly 4997 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4998 * If we pad such runts with zeros, the onboard checksum comes out correct. 4999 */ 5000 static inline int 5001 bge_cksum_pad(struct mbuf *pkt) 5002 { 5003 struct mbuf *last = NULL; 5004 int padlen; 5005 5006 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 5007 5008 /* if there's only the packet-header and we can pad there, use it. */ 5009 if (pkt->m_pkthdr.len == pkt->m_len && 5010 M_TRAILINGSPACE(pkt) >= padlen) { 5011 last = pkt; 5012 } else { 5013 /* 5014 * Walk packet chain to find last mbuf. We will either 5015 * pad there, or append a new mbuf and pad it 5016 * (thus perhaps avoiding the bcm5700 dma-min bug). 5017 */ 5018 for (last = pkt; last->m_next != NULL; last = last->m_next) { 5019 continue; /* do nothing */ 5020 } 5021 5022 /* `last' now points to last in chain. */ 5023 if (M_TRAILINGSPACE(last) < padlen) { 5024 /* Allocate new empty mbuf, pad it. Compact later. */ 5025 struct mbuf *n; 5026 MGET(n, M_DONTWAIT, MT_DATA); 5027 if (n == NULL) 5028 return ENOBUFS; 5029 MCLAIM(n, last->m_owner); 5030 n->m_len = 0; 5031 last->m_next = n; 5032 last = n; 5033 } 5034 } 5035 5036 KDASSERT(!M_READONLY(last)); 5037 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 5038 5039 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 5040 memset(mtod(last, char *) + last->m_len, 0, padlen); 5041 last->m_len += padlen; 5042 pkt->m_pkthdr.len += padlen; 5043 return 0; 5044 } 5045 5046 /* 5047 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 5048 */ 5049 static inline int 5050 bge_compact_dma_runt(struct mbuf *pkt) 5051 { 5052 struct mbuf *m, *prev; 5053 int totlen; 5054 5055 prev = NULL; 5056 totlen = 0; 5057 5058 for (m = pkt; m != NULL; prev = m, m = m->m_next) { 5059 int mlen = m->m_len; 5060 int shortfall = 8 - mlen ; 5061 5062 totlen += mlen; 5063 if (mlen == 0) 5064 continue; 5065 if (mlen >= 8) 5066 continue; 5067 5068 /* 5069 * If we get here, mbuf data is too small for DMA engine. 5070 * Try to fix by shuffling data to prev or next in chain. 5071 * If that fails, do a compacting deep-copy of the whole chain. 5072 */ 5073 5074 /* Internal frag. If fits in prev, copy it there. */ 5075 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 5076 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 5077 prev->m_len += mlen; 5078 m->m_len = 0; 5079 /* XXX stitch chain */ 5080 prev->m_next = m_free(m); 5081 m = prev; 5082 continue; 5083 } else if (m->m_next != NULL && 5084 M_TRAILINGSPACE(m) >= shortfall && 5085 m->m_next->m_len >= (8 + shortfall)) { 5086 /* m is writable and have enough data in next, pull up. */ 5087 5088 memcpy(m->m_data + m->m_len, m->m_next->m_data, 5089 shortfall); 5090 m->m_len += shortfall; 5091 m->m_next->m_len -= shortfall; 5092 m->m_next->m_data += shortfall; 5093 } else if (m->m_next == NULL || 1) { 5094 /* 5095 * Got a runt at the very end of the packet. 5096 * borrow data from the tail of the preceding mbuf and 5097 * update its length in-place. (The original data is 5098 * still valid, so we can do this even if prev is not 5099 * writable.) 5100 */ 5101 5102 /* 5103 * If we'd make prev a runt, just move all of its data. 5104 */ 5105 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 5106 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 5107 5108 if ((prev->m_len - shortfall) < 8) 5109 shortfall = prev->m_len; 5110 5111 #ifdef notyet /* just do the safe slow thing for now */ 5112 if (!M_READONLY(m)) { 5113 if (M_LEADINGSPACE(m) < shorfall) { 5114 void *m_dat; 5115 m_dat = M_BUFADDR(m); 5116 memmove(m_dat, mtod(m, void*), 5117 m->m_len); 5118 m->m_data = m_dat; 5119 } 5120 } else 5121 #endif /* just do the safe slow thing */ 5122 { 5123 struct mbuf * n = NULL; 5124 int newprevlen = prev->m_len - shortfall; 5125 5126 MGET(n, M_NOWAIT, MT_DATA); 5127 if (n == NULL) 5128 return ENOBUFS; 5129 MCLAIM(n, prev->m_owner); 5130 KASSERT(m->m_len + shortfall < MLEN 5131 /*, 5132 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 5133 5134 /* first copy the data we're stealing from prev */ 5135 memcpy(n->m_data, prev->m_data + newprevlen, 5136 shortfall); 5137 5138 /* update prev->m_len accordingly */ 5139 prev->m_len -= shortfall; 5140 5141 /* copy data from runt m */ 5142 memcpy(n->m_data + shortfall, m->m_data, 5143 m->m_len); 5144 5145 /* n holds what we stole from prev, plus m */ 5146 n->m_len = shortfall + m->m_len; 5147 5148 /* stitch n into chain and free m */ 5149 n->m_next = m->m_next; 5150 prev->m_next = n; 5151 /* KASSERT(m->m_next == NULL); */ 5152 m->m_next = NULL; 5153 m_free(m); 5154 m = n; /* for continuing loop */ 5155 } 5156 } 5157 } 5158 return 0; 5159 } 5160 5161 /* 5162 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5163 * pointers to descriptors. 5164 */ 5165 static int 5166 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 5167 { 5168 struct bge_tx_bd *f, *prev_f; 5169 uint32_t frag, cur; 5170 uint16_t csum_flags = 0; 5171 uint16_t txbd_tso_flags = 0; 5172 struct txdmamap_pool_entry *dma; 5173 bus_dmamap_t dmamap; 5174 bus_dma_tag_t dmatag; 5175 int i = 0; 5176 int use_tso, maxsegsize, error; 5177 bool have_vtag; 5178 uint16_t vtag; 5179 bool remap; 5180 5181 KASSERT(mutex_owned(sc->sc_intr_lock)); 5182 5183 if (m_head->m_pkthdr.csum_flags) { 5184 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 5185 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5186 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 |M_CSUM_UDPv4)) 5187 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5188 } 5189 5190 /* 5191 * If we were asked to do an outboard checksum, and the NIC 5192 * has the bug where it sometimes adds in the Ethernet padding, 5193 * explicitly pad with zeros so the cksum will be correct either way. 5194 * (For now, do this for all chip versions, until newer 5195 * are confirmed to not require the workaround.) 5196 */ 5197 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 5198 #ifdef notyet 5199 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 5200 #endif 5201 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 5202 goto check_dma_bug; 5203 5204 if (bge_cksum_pad(m_head) != 0) 5205 return ENOBUFS; 5206 5207 check_dma_bug: 5208 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 5209 goto doit; 5210 5211 /* 5212 * bcm5700 Revision B silicon cannot handle DMA descriptors with 5213 * less than eight bytes. If we encounter a teeny mbuf 5214 * at the end of a chain, we can pad. Otherwise, copy. 5215 */ 5216 if (bge_compact_dma_runt(m_head) != 0) 5217 return ENOBUFS; 5218 5219 doit: 5220 dma = SLIST_FIRST(&sc->txdma_list); 5221 if (dma == NULL) { 5222 return ENOBUFS; 5223 } 5224 dmamap = dma->dmamap; 5225 dmatag = sc->bge_dmatag; 5226 dma->is_dma32 = false; 5227 5228 /* 5229 * Set up any necessary TSO state before we start packing... 5230 */ 5231 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 5232 if (!use_tso) { 5233 maxsegsize = 0; 5234 } else { /* TSO setup */ 5235 unsigned mss; 5236 struct ether_header *eh; 5237 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 5238 unsigned bge_hlen; 5239 struct mbuf * m0 = m_head; 5240 struct ip *ip; 5241 struct tcphdr *th; 5242 int iphl, hlen; 5243 5244 /* 5245 * XXX It would be nice if the mbuf pkthdr had offset 5246 * fields for the protocol headers. 5247 */ 5248 5249 eh = mtod(m0, struct ether_header *); 5250 switch (htons(eh->ether_type)) { 5251 case ETHERTYPE_IP: 5252 offset = ETHER_HDR_LEN; 5253 break; 5254 5255 case ETHERTYPE_VLAN: 5256 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5257 break; 5258 5259 default: 5260 /* 5261 * Don't support this protocol or encapsulation. 5262 */ 5263 return ENOBUFS; 5264 } 5265 5266 /* 5267 * TCP/IP headers are in the first mbuf; we can do 5268 * this the easy way. 5269 */ 5270 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5271 hlen = iphl + offset; 5272 if (__predict_false(m0->m_len < 5273 (hlen + sizeof(struct tcphdr)))) { 5274 5275 aprint_error_dev(sc->bge_dev, 5276 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 5277 "not handled yet\n", 5278 m0->m_len, hlen+ sizeof(struct tcphdr)); 5279 #ifdef NOTYET 5280 /* 5281 * XXX jonathan (at) NetBSD.org: untested. 5282 * how to force this branch to be taken? 5283 */ 5284 BGE_EVCNT_INCR(sc->bge_ev_txtsopain); 5285 5286 m_copydata(m0, offset, sizeof(ip), &ip); 5287 m_copydata(m0, hlen, sizeof(th), &th); 5288 5289 ip.ip_len = 0; 5290 5291 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 5292 sizeof(ip.ip_len), &ip.ip_len); 5293 5294 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 5295 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 5296 5297 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 5298 sizeof(th.th_sum), &th.th_sum); 5299 5300 hlen += th.th_off << 2; 5301 iptcp_opt_words = hlen; 5302 #else 5303 /* 5304 * if_wm "hard" case not yet supported, can we not 5305 * mandate it out of existence? 5306 */ 5307 (void) ip; (void)th; (void) ip_tcp_hlen; 5308 5309 return ENOBUFS; 5310 #endif 5311 } else { 5312 ip = (struct ip *) (mtod(m0, char *) + offset); 5313 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 5314 ip_tcp_hlen = iphl + (th->th_off << 2); 5315 5316 /* Total IP/TCP options, in 32-bit words */ 5317 iptcp_opt_words = (ip_tcp_hlen 5318 - sizeof(struct tcphdr) 5319 - sizeof(struct ip)) >> 2; 5320 } 5321 if (BGE_IS_575X_PLUS(sc)) { 5322 th->th_sum = 0; 5323 csum_flags = 0; 5324 } else { 5325 /* 5326 * XXX jonathan (at) NetBSD.org: 5705 untested. 5327 * Requires TSO firmware patch for 5701/5703/5704. 5328 */ 5329 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 5330 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 5331 } 5332 5333 mss = m_head->m_pkthdr.segsz; 5334 txbd_tso_flags |= 5335 BGE_TXBDFLAG_CPU_PRE_DMA | 5336 BGE_TXBDFLAG_CPU_POST_DMA; 5337 5338 /* 5339 * Our NIC TSO-assist assumes TSO has standard, optionless 5340 * IPv4 and TCP headers, which total 40 bytes. By default, 5341 * the NIC copies 40 bytes of IP/TCP header from the 5342 * supplied header into the IP/TCP header portion of 5343 * each post-TSO-segment. If the supplied packet has IP or 5344 * TCP options, we need to tell the NIC to copy those extra 5345 * bytes into each post-TSO header, in addition to the normal 5346 * 40-byte IP/TCP header (and to leave space accordingly). 5347 * Unfortunately, the driver encoding of option length 5348 * varies across different ASIC families. 5349 */ 5350 tcp_seg_flags = 0; 5351 bge_hlen = ip_tcp_hlen >> 2; 5352 if (BGE_IS_5717_PLUS(sc)) { 5353 tcp_seg_flags = (bge_hlen & 0x3) << 14; 5354 txbd_tso_flags |= 5355 ((bge_hlen & 0xF8) << 7) | ((bge_hlen & 0x4) << 2); 5356 } else if (BGE_IS_5705_PLUS(sc)) { 5357 tcp_seg_flags = bge_hlen << 11; 5358 } else { 5359 /* XXX iptcp_opt_words or bge_hlen ? */ 5360 txbd_tso_flags |= iptcp_opt_words << 12; 5361 } 5362 maxsegsize = mss | tcp_seg_flags; 5363 ip->ip_len = htons(mss + ip_tcp_hlen); 5364 ip->ip_sum = 0; 5365 5366 } /* TSO setup */ 5367 5368 have_vtag = vlan_has_tag(m_head); 5369 if (have_vtag) 5370 vtag = vlan_get_tag(m_head); 5371 5372 /* 5373 * Start packing the mbufs in this chain into 5374 * the fragment pointers. Stop when we run out 5375 * of fragments or hit the end of the mbuf chain. 5376 */ 5377 remap = true; 5378 load_again: 5379 error = bus_dmamap_load_mbuf(dmatag, dmamap, m_head, BUS_DMA_NOWAIT); 5380 if (__predict_false(error)) { 5381 if (error == EFBIG && remap) { 5382 struct mbuf *m; 5383 remap = false; 5384 m = m_defrag(m_head, M_NOWAIT); 5385 if (m != NULL) { 5386 KASSERT(m == m_head); 5387 goto load_again; 5388 } 5389 } 5390 return error; 5391 } 5392 /* 5393 * Sanity check: avoid coming within 16 descriptors 5394 * of the end of the ring. 5395 */ 5396 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 5397 BGE_TSO_PRINTF(("%s: " 5398 " dmamap_load_mbuf too close to ring wrap\n", 5399 device_xname(sc->bge_dev))); 5400 goto fail_unload; 5401 } 5402 5403 /* Iterate over dmap-map fragments. */ 5404 f = prev_f = NULL; 5405 cur = frag = *txidx; 5406 5407 for (i = 0; i < dmamap->dm_nsegs; i++) { 5408 f = &sc->bge_rdata->bge_tx_ring[frag]; 5409 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 5410 break; 5411 5412 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 5413 f->bge_len = dmamap->dm_segs[i].ds_len; 5414 if (sizeof(bus_addr_t) > 4 && dma->is_dma32 == false && use_tso && ( 5415 (dmamap->dm_segs[i].ds_addr & 0xffffffff00000000) != 5416 ((dmamap->dm_segs[i].ds_addr + f->bge_len) & 0xffffffff00000000) || 5417 (prev_f != NULL && 5418 prev_f->bge_addr.bge_addr_hi != f->bge_addr.bge_addr_hi)) 5419 ) { 5420 /* 5421 * watchdog timeout issue was observed with TSO, 5422 * limiting DMA address space to 32bits seems to 5423 * address the issue. 5424 */ 5425 bus_dmamap_unload(dmatag, dmamap); 5426 dmatag = sc->bge_dmatag32; 5427 dmamap = dma->dmamap32; 5428 dma->is_dma32 = true; 5429 remap = true; 5430 goto load_again; 5431 } 5432 5433 /* 5434 * For 5751 and follow-ons, for TSO we must turn 5435 * off checksum-assist flag in the tx-descr, and 5436 * supply the ASIC-revision-specific encoding 5437 * of TSO flags and segsize. 5438 */ 5439 if (use_tso) { 5440 if (BGE_IS_575X_PLUS(sc) || i == 0) { 5441 f->bge_rsvd = maxsegsize; 5442 f->bge_flags = csum_flags | txbd_tso_flags; 5443 } else { 5444 f->bge_rsvd = 0; 5445 f->bge_flags = 5446 (csum_flags | txbd_tso_flags) & 0x0fff; 5447 } 5448 } else { 5449 f->bge_rsvd = 0; 5450 f->bge_flags = csum_flags; 5451 } 5452 5453 if (have_vtag) { 5454 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 5455 f->bge_vlan_tag = vtag; 5456 } else { 5457 f->bge_vlan_tag = 0; 5458 } 5459 prev_f = f; 5460 cur = frag; 5461 BGE_INC(frag, BGE_TX_RING_CNT); 5462 } 5463 5464 if (i < dmamap->dm_nsegs) { 5465 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 5466 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 5467 goto fail_unload; 5468 } 5469 5470 bus_dmamap_sync(dmatag, dmamap, 0, dmamap->dm_mapsize, 5471 BUS_DMASYNC_PREWRITE); 5472 5473 if (frag == sc->bge_tx_saved_considx) { 5474 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 5475 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 5476 5477 goto fail_unload; 5478 } 5479 5480 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 5481 sc->bge_cdata.bge_tx_chain[cur] = m_head; 5482 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 5483 sc->txdma[cur] = dma; 5484 sc->bge_txcnt += dmamap->dm_nsegs; 5485 5486 *txidx = frag; 5487 5488 return 0; 5489 5490 fail_unload: 5491 bus_dmamap_unload(dmatag, dmamap); 5492 5493 return ENOBUFS; 5494 } 5495 5496 5497 static void 5498 bge_start(struct ifnet *ifp) 5499 { 5500 struct bge_softc * const sc = ifp->if_softc; 5501 5502 mutex_enter(sc->sc_intr_lock); 5503 if (!sc->bge_txrx_stopping) 5504 bge_start_locked(ifp); 5505 mutex_exit(sc->sc_intr_lock); 5506 } 5507 5508 /* 5509 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5510 * to the mbuf data regions directly in the transmit descriptors. 5511 */ 5512 static void 5513 bge_start_locked(struct ifnet *ifp) 5514 { 5515 struct bge_softc * const sc = ifp->if_softc; 5516 struct mbuf *m_head = NULL; 5517 struct mbuf *m; 5518 uint32_t prodidx; 5519 int pkts = 0; 5520 int error; 5521 5522 KASSERT(mutex_owned(sc->sc_intr_lock)); 5523 5524 prodidx = sc->bge_tx_prodidx; 5525 5526 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 5527 IFQ_POLL(&ifp->if_snd, m_head); 5528 if (m_head == NULL) 5529 break; 5530 5531 #if 0 5532 /* 5533 * XXX 5534 * safety overkill. If this is a fragmented packet chain 5535 * with delayed TCP/UDP checksums, then only encapsulate 5536 * it if we have enough descriptors to handle the entire 5537 * chain at once. 5538 * (paranoia -- may not actually be needed) 5539 */ 5540 if (m_head->m_flags & M_FIRSTFRAG && 5541 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 5542 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 5543 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 5544 ifp->if_flags |= IFF_OACTIVE; 5545 break; 5546 } 5547 } 5548 #endif 5549 5550 /* 5551 * Pack the data into the transmit ring. If we 5552 * don't have room, set the OACTIVE flag and wait 5553 * for the NIC to drain the ring. 5554 */ 5555 error = bge_encap(sc, m_head, &prodidx); 5556 if (__predict_false(error)) { 5557 if (SLIST_EMPTY(&sc->txdma_list)) { 5558 /* just wait for the transmit ring to drain */ 5559 break; 5560 } 5561 IFQ_DEQUEUE(&ifp->if_snd, m); 5562 KASSERT(m == m_head); 5563 m_freem(m_head); 5564 continue; 5565 } 5566 5567 /* now we are committed to transmit the packet */ 5568 IFQ_DEQUEUE(&ifp->if_snd, m); 5569 KASSERT(m == m_head); 5570 pkts++; 5571 5572 /* 5573 * If there's a BPF listener, bounce a copy of this frame 5574 * to him. 5575 */ 5576 bpf_mtap(ifp, m_head, BPF_D_OUT); 5577 } 5578 if (pkts == 0) 5579 return; 5580 5581 /* Transmit */ 5582 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5583 /* 5700 b2 errata */ 5584 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 5585 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5586 5587 sc->bge_tx_prodidx = prodidx; 5588 sc->bge_tx_lastsent = time_uptime; 5589 sc->bge_tx_sending = true; 5590 } 5591 5592 static int 5593 bge_init(struct ifnet *ifp) 5594 { 5595 struct bge_softc * const sc = ifp->if_softc; 5596 const uint16_t *m; 5597 uint32_t mode, reg; 5598 int error = 0; 5599 5600 ASSERT_SLEEPABLE(); 5601 KASSERT(IFNET_LOCKED(ifp)); 5602 KASSERT(ifp == &sc->ethercom.ec_if); 5603 5604 if (sc->bge_detaching) 5605 return ENXIO; 5606 5607 /* Cancel pending I/O and flush buffers. */ 5608 bge_stop(ifp, 0); 5609 5610 bge_stop_fw(sc); 5611 bge_sig_pre_reset(sc, BGE_RESET_START); 5612 bge_reset(sc); 5613 bge_sig_legacy(sc, BGE_RESET_START); 5614 5615 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5616 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5617 reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE | 5618 BGE_CPMU_CTRL_LINK_IDLE_MODE); 5619 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5620 5621 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK); 5622 reg &= ~BGE_CPMU_LSPD_10MB_CLK; 5623 reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25; 5624 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg); 5625 5626 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD); 5627 reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK; 5628 reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25; 5629 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg); 5630 5631 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC); 5632 reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK; 5633 reg |= BGE_CPMU_HST_ACC_MACCLK_6_25; 5634 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg); 5635 } 5636 5637 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) { 5638 pcireg_t aercap; 5639 5640 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH); 5641 reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK) 5642 | BGE_PCIE_PWRMNG_L1THRESH_4MS 5643 | BGE_PCIE_PWRMNG_EXTASPMTMR_EN; 5644 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg); 5645 5646 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY); 5647 reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK) 5648 | BGE_PCIE_EIDLE_DELAY_13CLK; 5649 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg); 5650 5651 /* Clear correctable error */ 5652 if (pci_get_ext_capability(sc->sc_pc, sc->sc_pcitag, 5653 PCI_EXTCAP_AER, &aercap, NULL) != 0) 5654 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 5655 aercap + PCI_AER_COR_STATUS, 0xffffffff); 5656 5657 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL); 5658 reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN) 5659 | BGE_PCIE_LINKCTL_L1_PLL_PDDIS; 5660 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg); 5661 } 5662 5663 bge_sig_post_reset(sc, BGE_RESET_START); 5664 5665 bge_chipinit(sc); 5666 5667 /* 5668 * Init the various state machines, ring 5669 * control blocks and firmware. 5670 */ 5671 error = bge_blockinit(sc); 5672 if (error != 0) { 5673 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 5674 error); 5675 return error; 5676 } 5677 5678 /* 5718 step 25, 57XX step 54 */ 5679 /* Specify MTU. */ 5680 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5681 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 5682 5683 /* 5718 step 23 */ 5684 /* Load our MAC address. */ 5685 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 5686 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5687 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, 5688 ((uint32_t)htons(m[1]) << 16) | htons(m[2])); 5689 5690 /* Enable or disable promiscuous mode as needed. */ 5691 if (ifp->if_flags & IFF_PROMISC) 5692 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5693 else 5694 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5695 5696 /* Program multicast filter. */ 5697 mutex_enter(sc->sc_mcast_lock); 5698 bge_setmulti(sc); 5699 mutex_exit(sc->sc_mcast_lock); 5700 5701 /* Init RX ring. */ 5702 bge_init_rx_ring_std(sc); 5703 5704 /* 5705 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5706 * memory to insure that the chip has in fact read the first 5707 * entry of the ring. 5708 */ 5709 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5710 u_int i; 5711 for (i = 0; i < 10; i++) { 5712 DELAY(20); 5713 uint32_t v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5714 if (v == (MCLBYTES - ETHER_ALIGN)) 5715 break; 5716 } 5717 if (i == 10) 5718 aprint_error_dev(sc->bge_dev, 5719 "5705 A0 chip failed to load RX ring\n"); 5720 } 5721 5722 /* Init jumbo RX ring. */ 5723 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 5724 bge_init_rx_ring_jumbo(sc); 5725 5726 /* Init our RX return ring index */ 5727 sc->bge_rx_saved_considx = 0; 5728 5729 /* Init TX ring. */ 5730 bge_init_tx_ring(sc); 5731 5732 /* 5718 step 63, 57XX step 94 */ 5733 /* Enable TX MAC state machine lockup fix. */ 5734 mode = CSR_READ_4(sc, BGE_TX_MODE); 5735 if (BGE_IS_5755_PLUS(sc) || 5736 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 5737 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5738 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 5739 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 5740 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5741 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5742 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5743 } 5744 5745 /* Turn on transmitter */ 5746 CSR_WRITE_4_FLUSH(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5747 /* 5718 step 64 */ 5748 DELAY(100); 5749 5750 /* 5718 step 65, 57XX step 95 */ 5751 /* Turn on receiver */ 5752 mode = CSR_READ_4(sc, BGE_RX_MODE); 5753 if (BGE_IS_5755_PLUS(sc)) 5754 mode |= BGE_RXMODE_IPV6_ENABLE; 5755 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 5756 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5757 CSR_WRITE_4_FLUSH(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5758 /* 5718 step 66 */ 5759 DELAY(10); 5760 5761 /* 5718 step 12, 57XX step 37 */ 5762 /* 5763 * XXX Documents of 5718 series and 577xx say the recommended value 5764 * is 1, but tg3 set 1 only on 57765 series. 5765 */ 5766 if (BGE_IS_57765_PLUS(sc)) 5767 reg = 1; 5768 else 5769 reg = 2; 5770 CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); 5771 5772 /* Tell firmware we're alive. */ 5773 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5774 5775 /* Enable host interrupts. */ 5776 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5777 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5778 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 0); 5779 5780 mutex_enter(sc->sc_intr_lock); 5781 if ((error = bge_ifmedia_upd(ifp)) == 0) { 5782 sc->bge_txrx_stopping = false; 5783 5784 /* IFNET_LOCKED asserted above */ 5785 ifp->if_flags |= IFF_RUNNING; 5786 5787 callout_schedule(&sc->bge_timeout, hz); 5788 } 5789 mutex_exit(sc->sc_intr_lock); 5790 5791 mutex_enter(sc->sc_mcast_lock); 5792 sc->bge_if_flags = ifp->if_flags; 5793 mutex_exit(sc->sc_mcast_lock); 5794 5795 return error; 5796 } 5797 5798 /* 5799 * Set media options. 5800 */ 5801 static int 5802 bge_ifmedia_upd(struct ifnet *ifp) 5803 { 5804 struct bge_softc * const sc = ifp->if_softc; 5805 struct mii_data * const mii = &sc->bge_mii; 5806 struct ifmedia * const ifm = &sc->bge_ifmedia; 5807 int rc; 5808 5809 KASSERT(mutex_owned(sc->sc_intr_lock)); 5810 5811 /* If this is a 1000baseX NIC, enable the TBI port. */ 5812 if (sc->bge_flags & BGEF_FIBER_TBI) { 5813 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5814 return EINVAL; 5815 switch (IFM_SUBTYPE(ifm->ifm_media)) { 5816 case IFM_AUTO: 5817 /* 5818 * The BCM5704 ASIC appears to have a special 5819 * mechanism for programming the autoneg 5820 * advertisement registers in TBI mode. 5821 */ 5822 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 5823 uint32_t sgdig; 5824 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5825 if (sgdig & BGE_SGDIGSTS_DONE) { 5826 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5827 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5828 sgdig |= BGE_SGDIGCFG_AUTO | 5829 BGE_SGDIGCFG_PAUSE_CAP | 5830 BGE_SGDIGCFG_ASYM_PAUSE; 5831 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5832 sgdig | BGE_SGDIGCFG_SEND); 5833 DELAY(5); 5834 CSR_WRITE_4_FLUSH(sc, BGE_SGDIG_CFG, 5835 sgdig); 5836 } 5837 } 5838 break; 5839 case IFM_1000_SX: 5840 if ((ifm->ifm_media & IFM_FDX) != 0) { 5841 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 5842 BGE_MACMODE_HALF_DUPLEX); 5843 } else { 5844 BGE_SETBIT_FLUSH(sc, BGE_MAC_MODE, 5845 BGE_MACMODE_HALF_DUPLEX); 5846 } 5847 DELAY(40); 5848 break; 5849 default: 5850 return EINVAL; 5851 } 5852 /* XXX 802.3x flow control for 1000BASE-SX */ 5853 return 0; 5854 } 5855 5856 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784) && 5857 (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5784_AX)) { 5858 uint32_t reg; 5859 5860 reg = CSR_READ_4(sc, BGE_CPMU_CTRL); 5861 if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) { 5862 reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY; 5863 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg); 5864 } 5865 } 5866 5867 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 5868 if ((rc = mii_mediachg(mii)) == ENXIO) 5869 return 0; 5870 5871 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 5872 uint32_t reg; 5873 5874 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK); 5875 if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK) 5876 == (BGE_CPMU_LSPD_1000MB_MACCLK_12_5)) { 5877 reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK; 5878 delay(40); 5879 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg); 5880 } 5881 } 5882 5883 /* 5884 * Force an interrupt so that we will call bge_link_upd 5885 * if needed and clear any pending link state attention. 5886 * Without this we are not getting any further interrupts 5887 * for link state changes and thus will not UP the link and 5888 * not be able to send in bge_start. The only way to get 5889 * things working was to receive a packet and get a RX intr. 5890 */ 5891 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 5892 sc->bge_flags & BGEF_IS_5788) 5893 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5894 else 5895 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5896 5897 return rc; 5898 } 5899 5900 /* 5901 * Report current media status. 5902 */ 5903 static void 5904 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5905 { 5906 struct bge_softc * const sc = ifp->if_softc; 5907 struct mii_data * const mii = &sc->bge_mii; 5908 5909 KASSERT(mutex_owned(sc->sc_intr_lock)); 5910 5911 if (sc->bge_flags & BGEF_FIBER_TBI) { 5912 ifmr->ifm_status = IFM_AVALID; 5913 ifmr->ifm_active = IFM_ETHER; 5914 if (CSR_READ_4(sc, BGE_MAC_STS) & 5915 BGE_MACSTAT_TBI_PCS_SYNCHED) 5916 ifmr->ifm_status |= IFM_ACTIVE; 5917 ifmr->ifm_active |= IFM_1000_SX; 5918 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5919 ifmr->ifm_active |= IFM_HDX; 5920 else 5921 ifmr->ifm_active |= IFM_FDX; 5922 return; 5923 } 5924 5925 mii_pollstat(mii); 5926 ifmr->ifm_status = mii->mii_media_status; 5927 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 5928 sc->bge_flowflags; 5929 } 5930 5931 static int 5932 bge_ifflags_cb(struct ethercom *ec) 5933 { 5934 struct ifnet * const ifp = &ec->ec_if; 5935 struct bge_softc * const sc = ifp->if_softc; 5936 int ret = 0; 5937 5938 KASSERT(IFNET_LOCKED(ifp)); 5939 mutex_enter(sc->sc_mcast_lock); 5940 5941 u_short change = ifp->if_flags ^ sc->bge_if_flags; 5942 sc->bge_if_flags = ifp->if_flags; 5943 5944 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 5945 ret = ENETRESET; 5946 } else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 5947 if ((ifp->if_flags & IFF_PROMISC) == 0) 5948 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5949 else 5950 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 5951 5952 bge_setmulti(sc); 5953 } 5954 5955 mutex_exit(sc->sc_mcast_lock); 5956 5957 return ret; 5958 } 5959 5960 static int 5961 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 5962 { 5963 struct bge_softc * const sc = ifp->if_softc; 5964 struct ifreq * const ifr = (struct ifreq *) data; 5965 int error = 0; 5966 5967 switch (command) { 5968 case SIOCADDMULTI: 5969 case SIOCDELMULTI: 5970 break; 5971 default: 5972 KASSERT(IFNET_LOCKED(ifp)); 5973 } 5974 5975 const int s = splnet(); 5976 5977 switch (command) { 5978 case SIOCSIFMEDIA: 5979 mutex_enter(sc->sc_intr_lock); 5980 /* XXX Flow control is not supported for 1000BASE-SX */ 5981 if (sc->bge_flags & BGEF_FIBER_TBI) { 5982 ifr->ifr_media &= ~IFM_ETH_FMASK; 5983 sc->bge_flowflags = 0; 5984 } 5985 5986 /* Flow control requires full-duplex mode. */ 5987 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 5988 (ifr->ifr_media & IFM_FDX) == 0) { 5989 ifr->ifr_media &= ~IFM_ETH_FMASK; 5990 } 5991 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 5992 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 5993 /* We can do both TXPAUSE and RXPAUSE. */ 5994 ifr->ifr_media |= 5995 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 5996 } 5997 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 5998 } 5999 mutex_exit(sc->sc_intr_lock); 6000 6001 if (sc->bge_flags & BGEF_FIBER_TBI) { 6002 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 6003 command); 6004 } else { 6005 struct mii_data * const mii = &sc->bge_mii; 6006 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 6007 command); 6008 } 6009 break; 6010 default: 6011 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 6012 break; 6013 6014 error = 0; 6015 6016 if (command == SIOCADDMULTI || command == SIOCDELMULTI) { 6017 mutex_enter(sc->sc_mcast_lock); 6018 if (sc->bge_if_flags & IFF_RUNNING) { 6019 bge_setmulti(sc); 6020 } 6021 mutex_exit(sc->sc_mcast_lock); 6022 } 6023 break; 6024 } 6025 6026 splx(s); 6027 6028 return error; 6029 } 6030 6031 static bool 6032 bge_watchdog_check(struct bge_softc * const sc) 6033 { 6034 6035 KASSERT(mutex_owned(sc->sc_intr_lock)); 6036 6037 if (!sc->bge_tx_sending) 6038 return true; 6039 6040 if (time_uptime - sc->bge_tx_lastsent <= bge_watchdog_timeout) 6041 return true; 6042 6043 /* If pause frames are active then don't reset the hardware. */ 6044 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 6045 const uint32_t status = CSR_READ_4(sc, BGE_RX_STS); 6046 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 6047 /* 6048 * If link partner has us in XOFF state then wait for 6049 * the condition to clear. 6050 */ 6051 CSR_WRITE_4(sc, BGE_RX_STS, status); 6052 sc->bge_tx_lastsent = time_uptime; 6053 return true; 6054 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 6055 (status & BGE_RXSTAT_RCVD_XON) != 0) { 6056 /* 6057 * If link partner has us in XOFF state then wait for 6058 * the condition to clear. 6059 */ 6060 CSR_WRITE_4(sc, BGE_RX_STS, status); 6061 sc->bge_tx_lastsent = time_uptime; 6062 return true; 6063 } 6064 /* 6065 * Any other condition is unexpected and the controller 6066 * should be reset. 6067 */ 6068 } 6069 6070 return false; 6071 } 6072 6073 static bool 6074 bge_watchdog_tick(struct ifnet *ifp) 6075 { 6076 struct bge_softc * const sc = ifp->if_softc; 6077 6078 KASSERT(mutex_owned(sc->sc_intr_lock)); 6079 6080 if (!sc->sc_trigger_reset && bge_watchdog_check(sc)) 6081 return true; 6082 6083 if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0) 6084 workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL); 6085 6086 return false; 6087 } 6088 6089 /* 6090 * Perform an interface watchdog reset. 6091 */ 6092 static void 6093 bge_handle_reset_work(struct work *work, void *arg) 6094 { 6095 struct bge_softc * const sc = arg; 6096 struct ifnet * const ifp = &sc->ethercom.ec_if; 6097 6098 printf("%s: watchdog timeout -- resetting\n", ifp->if_xname); 6099 6100 /* Don't want ioctl operations to happen */ 6101 IFNET_LOCK(ifp); 6102 6103 /* reset the interface. */ 6104 bge_init(ifp); 6105 6106 IFNET_UNLOCK(ifp); 6107 6108 /* 6109 * There are still some upper layer processing which call 6110 * ifp->if_start(). e.g. ALTQ or one CPU system 6111 */ 6112 /* Try to get more packets going. */ 6113 ifp->if_start(ifp); 6114 6115 atomic_store_relaxed(&sc->sc_reset_pending, 0); 6116 } 6117 6118 static void 6119 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 6120 { 6121 int i; 6122 6123 BGE_CLRBIT_FLUSH(sc, reg, bit); 6124 6125 for (i = 0; i < 1000; i++) { 6126 delay(100); 6127 if ((CSR_READ_4(sc, reg) & bit) == 0) 6128 return; 6129 } 6130 6131 /* 6132 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 6133 * on some environment (and once after boot?) 6134 */ 6135 if (reg != BGE_SRS_MODE) 6136 aprint_error_dev(sc->bge_dev, 6137 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 6138 (u_long)reg, bit); 6139 } 6140 6141 /* 6142 * Stop the adapter and free any mbufs allocated to the 6143 * RX and TX lists. 6144 */ 6145 static void 6146 bge_stop(struct ifnet *ifp, int disable) 6147 { 6148 struct bge_softc * const sc = ifp->if_softc; 6149 6150 ASSERT_SLEEPABLE(); 6151 KASSERT(IFNET_LOCKED(ifp)); 6152 6153 mutex_enter(sc->sc_intr_lock); 6154 sc->bge_txrx_stopping = true; 6155 mutex_exit(sc->sc_intr_lock); 6156 6157 callout_halt(&sc->bge_timeout, NULL); 6158 6159 /* Disable host interrupts. */ 6160 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 6161 bge_writembx_flush(sc, BGE_MBX_IRQ0_LO, 1); 6162 6163 /* 6164 * Tell firmware we're shutting down. 6165 */ 6166 bge_stop_fw(sc); 6167 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 6168 6169 /* 6170 * Disable all of the receiver blocks. 6171 */ 6172 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 6173 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 6174 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 6175 if (BGE_IS_5700_FAMILY(sc)) 6176 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 6177 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6178 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6179 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6180 6181 /* 6182 * Disable all of the transmit blocks. 6183 */ 6184 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6185 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6186 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6187 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6188 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6189 if (BGE_IS_5700_FAMILY(sc)) 6190 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6191 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6192 6193 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB); 6194 delay(40); 6195 6196 bge_stop_block(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 6197 6198 /* 6199 * Shut down all of the memory managers and related 6200 * state machines. 6201 */ 6202 /* 5718 step 5a,5b */ 6203 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6204 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6205 if (BGE_IS_5700_FAMILY(sc)) 6206 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6207 6208 /* 5718 step 5c,5d */ 6209 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6210 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6211 6212 if (BGE_IS_5700_FAMILY(sc)) { 6213 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6214 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6215 } 6216 6217 bge_reset(sc); 6218 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6219 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6220 6221 /* 6222 * Keep the ASF firmware running if up. 6223 */ 6224 if (sc->bge_asf_mode & ASF_STACKUP) 6225 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6226 else 6227 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6228 6229 /* Free the RX lists. */ 6230 bge_free_rx_ring_std(sc); 6231 6232 /* Free jumbo RX list. */ 6233 if (BGE_IS_JUMBO_CAPABLE(sc)) 6234 bge_free_rx_ring_jumbo(sc); 6235 6236 /* Free TX buffers. */ 6237 bge_free_tx_ring(sc, disable); 6238 6239 /* 6240 * Isolate/power down the PHY. 6241 */ 6242 if (!(sc->bge_flags & BGEF_FIBER_TBI)) { 6243 mutex_enter(sc->sc_intr_lock); 6244 mii_down(&sc->bge_mii); 6245 mutex_exit(sc->sc_intr_lock); 6246 } 6247 6248 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6249 6250 /* Clear MAC's link state (PHY may still have link UP). */ 6251 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6252 6253 ifp->if_flags &= ~IFF_RUNNING; 6254 6255 mutex_enter(sc->sc_mcast_lock); 6256 sc->bge_if_flags = ifp->if_flags; 6257 mutex_exit(sc->sc_mcast_lock); 6258 } 6259 6260 static void 6261 bge_link_upd(struct bge_softc *sc) 6262 { 6263 struct ifnet * const ifp = &sc->ethercom.ec_if; 6264 struct mii_data * const mii = &sc->bge_mii; 6265 uint32_t status; 6266 uint16_t phyval; 6267 int link; 6268 6269 KASSERT(sc->sc_intr_lock); 6270 6271 /* Clear 'pending link event' flag */ 6272 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 6273 6274 /* 6275 * Process link state changes. 6276 * Grrr. The link status word in the status block does 6277 * not work correctly on the BCM5700 rev AX and BX chips, 6278 * according to all available information. Hence, we have 6279 * to enable MII interrupts in order to properly obtain 6280 * async link changes. Unfortunately, this also means that 6281 * we have to read the MAC status register to detect link 6282 * changes, thereby adding an additional register access to 6283 * the interrupt handler. 6284 */ 6285 6286 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 6287 status = CSR_READ_4(sc, BGE_MAC_STS); 6288 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6289 mii_pollstat(mii); 6290 6291 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6292 mii->mii_media_status & IFM_ACTIVE && 6293 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6294 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6295 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6296 (!(mii->mii_media_status & IFM_ACTIVE) || 6297 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6298 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6299 6300 /* Clear the interrupt */ 6301 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6302 BGE_EVTENB_MI_INTERRUPT); 6303 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6304 BRGPHY_MII_ISR, &phyval); 6305 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6306 BRGPHY_MII_IMR, BRGPHY_INTRS); 6307 } 6308 return; 6309 } 6310 6311 if (sc->bge_flags & BGEF_FIBER_TBI) { 6312 status = CSR_READ_4(sc, BGE_MAC_STS); 6313 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6314 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 6315 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6316 if (BGE_ASICREV(sc->bge_chipid) 6317 == BGE_ASICREV_BCM5704) { 6318 BGE_CLRBIT_FLUSH(sc, BGE_MAC_MODE, 6319 BGE_MACMODE_TBI_SEND_CFGS); 6320 DELAY(40); 6321 } 6322 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6323 if_link_state_change(ifp, LINK_STATE_UP); 6324 } 6325 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 6326 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6327 if_link_state_change(ifp, LINK_STATE_DOWN); 6328 } 6329 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 6330 /* 6331 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 6332 * bit in status word always set. Workaround this bug by 6333 * reading PHY link status directly. 6334 */ 6335 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 6336 BGE_STS_LINK : 0; 6337 6338 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 6339 mii_pollstat(mii); 6340 6341 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 6342 mii->mii_media_status & IFM_ACTIVE && 6343 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 6344 BGE_STS_SETBIT(sc, BGE_STS_LINK); 6345 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 6346 (!(mii->mii_media_status & IFM_ACTIVE) || 6347 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 6348 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 6349 } 6350 } else { 6351 /* 6352 * For controllers that call mii_tick, we have to poll 6353 * link status. 6354 */ 6355 mii_pollstat(mii); 6356 } 6357 6358 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5784_AX) { 6359 uint32_t reg, scale; 6360 6361 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) & 6362 BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK; 6363 if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5) 6364 scale = 65; 6365 else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25) 6366 scale = 6; 6367 else 6368 scale = 12; 6369 6370 reg = CSR_READ_4(sc, BGE_MISC_CFG) & 6371 ~BGE_MISCCFG_TIMER_PRESCALER; 6372 reg |= scale << 1; 6373 CSR_WRITE_4(sc, BGE_MISC_CFG, reg); 6374 } 6375 /* Clear the attention */ 6376 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6377 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6378 BGE_MACSTAT_LINK_CHANGED); 6379 } 6380 6381 static int 6382 bge_sysctl_verify(SYSCTLFN_ARGS) 6383 { 6384 int error, t; 6385 struct sysctlnode node; 6386 6387 node = *rnode; 6388 t = *(int*)rnode->sysctl_data; 6389 node.sysctl_data = &t; 6390 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6391 if (error || newp == NULL) 6392 return error; 6393 6394 #if 0 6395 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 6396 node.sysctl_num, rnode->sysctl_num)); 6397 #endif 6398 6399 if (node.sysctl_num == bge_rxthresh_nodenum) { 6400 if (t < 0 || t >= NBGE_RX_THRESH) 6401 return EINVAL; 6402 bge_update_all_threshes(t); 6403 } else 6404 return EINVAL; 6405 6406 *(int*)rnode->sysctl_data = t; 6407 6408 return 0; 6409 } 6410 6411 /* 6412 * Set up sysctl(3) MIB, hw.bge.*. 6413 */ 6414 static void 6415 bge_sysctl_init(struct bge_softc *sc) 6416 { 6417 int rc, bge_root_num; 6418 const struct sysctlnode *node; 6419 6420 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6421 0, CTLTYPE_NODE, "bge", 6422 SYSCTL_DESCR("BGE interface controls"), 6423 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 6424 goto out; 6425 } 6426 6427 bge_root_num = node->sysctl_num; 6428 6429 /* BGE Rx interrupt mitigation level */ 6430 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6431 CTLFLAG_READWRITE, 6432 CTLTYPE_INT, "rx_lvl", 6433 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 6434 bge_sysctl_verify, 0, 6435 &bge_rx_thresh_lvl, 6436 0, CTL_HW, bge_root_num, CTL_CREATE, 6437 CTL_EOL)) != 0) { 6438 goto out; 6439 } 6440 6441 bge_rxthresh_nodenum = node->sysctl_num; 6442 6443 #ifdef BGE_DEBUG 6444 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 6445 CTLFLAG_READWRITE, 6446 CTLTYPE_BOOL, "trigger_reset", 6447 SYSCTL_DESCR("Trigger an interface reset"), 6448 NULL, 0, &sc->sc_trigger_reset, 0, CTL_CREATE, 6449 CTL_EOL)) != 0) { 6450 goto out; 6451 } 6452 #endif 6453 return; 6454 6455 out: 6456 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 6457 } 6458 6459 #ifdef BGE_DEBUG 6460 void 6461 bge_debug_info(struct bge_softc *sc) 6462 { 6463 6464 printf("Hardware Flags:\n"); 6465 if (BGE_IS_57765_PLUS(sc)) 6466 printf(" - 57765 Plus\n"); 6467 if (BGE_IS_5717_PLUS(sc)) 6468 printf(" - 5717 Plus\n"); 6469 if (BGE_IS_5755_PLUS(sc)) 6470 printf(" - 5755 Plus\n"); 6471 if (BGE_IS_575X_PLUS(sc)) 6472 printf(" - 575X Plus\n"); 6473 if (BGE_IS_5705_PLUS(sc)) 6474 printf(" - 5705 Plus\n"); 6475 if (BGE_IS_5714_FAMILY(sc)) 6476 printf(" - 5714 Family\n"); 6477 if (BGE_IS_5700_FAMILY(sc)) 6478 printf(" - 5700 Family\n"); 6479 if (sc->bge_flags & BGEF_IS_5788) 6480 printf(" - 5788\n"); 6481 if (sc->bge_flags & BGEF_JUMBO_CAPABLE) 6482 printf(" - Supports Jumbo Frames\n"); 6483 if (sc->bge_flags & BGEF_NO_EEPROM) 6484 printf(" - No EEPROM\n"); 6485 if (sc->bge_flags & BGEF_PCIX) 6486 printf(" - PCI-X Bus\n"); 6487 if (sc->bge_flags & BGEF_PCIE) 6488 printf(" - PCI Express Bus\n"); 6489 if (sc->bge_flags & BGEF_RX_ALIGNBUG) 6490 printf(" - RX Alignment Bug\n"); 6491 if (sc->bge_flags & BGEF_APE) 6492 printf(" - APE\n"); 6493 if (sc->bge_flags & BGEF_CPMU_PRESENT) 6494 printf(" - CPMU\n"); 6495 if (sc->bge_flags & BGEF_TSO) 6496 printf(" - TSO\n"); 6497 if (sc->bge_flags & BGEF_TAGGED_STATUS) 6498 printf(" - TAGGED_STATUS\n"); 6499 6500 /* PHY related */ 6501 if (sc->bge_phy_flags & BGEPHYF_NO_3LED) 6502 printf(" - No 3 LEDs\n"); 6503 if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) 6504 printf(" - CRC bug\n"); 6505 if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) 6506 printf(" - ADC bug\n"); 6507 if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) 6508 printf(" - 5704 A0 bug\n"); 6509 if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) 6510 printf(" - jitter bug\n"); 6511 if (sc->bge_phy_flags & BGEPHYF_BER_BUG) 6512 printf(" - BER bug\n"); 6513 if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) 6514 printf(" - adjust trim\n"); 6515 if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) 6516 printf(" - no wirespeed\n"); 6517 6518 /* ASF related */ 6519 if (sc->bge_asf_mode & ASF_ENABLE) 6520 printf(" - ASF enable\n"); 6521 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) 6522 printf(" - ASF new handshake\n"); 6523 if (sc->bge_asf_mode & ASF_STACKUP) 6524 printf(" - ASF stackup\n"); 6525 } 6526 #endif /* BGE_DEBUG */ 6527 6528 static int 6529 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6530 { 6531 prop_dictionary_t dict; 6532 prop_data_t ea; 6533 6534 if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) 6535 return 1; 6536 6537 dict = device_properties(sc->bge_dev); 6538 ea = prop_dictionary_get(dict, "mac-address"); 6539 if (ea != NULL) { 6540 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 6541 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 6542 memcpy(ether_addr, prop_data_value(ea), ETHER_ADDR_LEN); 6543 return 0; 6544 } 6545 6546 return 1; 6547 } 6548 6549 static int 6550 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6551 { 6552 uint32_t mac_addr; 6553 6554 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6555 if ((mac_addr >> 16) == 0x484b) { 6556 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6557 ether_addr[1] = (uint8_t)mac_addr; 6558 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6559 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6560 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6561 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6562 ether_addr[5] = (uint8_t)mac_addr; 6563 return 0; 6564 } 6565 return 1; 6566 } 6567 6568 static int 6569 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6570 { 6571 int mac_offset = BGE_EE_MAC_OFFSET; 6572 6573 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6574 mac_offset = BGE_EE_MAC_OFFSET_5906; 6575 6576 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6577 ETHER_ADDR_LEN)); 6578 } 6579 6580 static int 6581 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6582 { 6583 6584 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 6585 return 1; 6586 6587 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6588 ETHER_ADDR_LEN)); 6589 } 6590 6591 static int 6592 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6593 { 6594 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6595 /* NOTE: Order is critical */ 6596 bge_get_eaddr_fw, 6597 bge_get_eaddr_mem, 6598 bge_get_eaddr_nvram, 6599 bge_get_eaddr_eeprom, 6600 NULL 6601 }; 6602 const bge_eaddr_fcn_t *func; 6603 6604 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6605 if ((*func)(sc, eaddr) == 0) 6606 break; 6607 } 6608 return *func == NULL ? ENXIO : 0; 6609 } 6610
Indexes created Thu Sep 25 02:09:54 GMT 2025