if_bge.c revision 1.43
1 /* $NetBSD: if_bge.c,v 1.43 2003/07/14 15:47:24 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.43 2003/07/14 15:47:24 lukem Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/miidevs.h> 120 #include <dev/mii/brgphyreg.h> 121 122 #include <dev/pci/if_bgereg.h> 123 124 #include <uvm/uvm_extern.h> 125 126 int bge_probe(struct device *, struct cfdata *, void *); 127 void bge_attach(struct device *, struct device *, void *); 128 void bge_release_resources(struct bge_softc *); 129 void bge_txeof(struct bge_softc *); 130 void bge_rxeof(struct bge_softc *); 131 132 void bge_tick(void *); 133 void bge_stats_update(struct bge_softc *); 134 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 135 136 int bge_intr(void *); 137 void bge_start(struct ifnet *); 138 int bge_ioctl(struct ifnet *, u_long, caddr_t); 139 int bge_init(struct ifnet *); 140 void bge_stop(struct bge_softc *); 141 void bge_watchdog(struct ifnet *); 142 void bge_shutdown(void *); 143 int bge_ifmedia_upd(struct ifnet *); 144 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 145 146 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 147 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 148 149 void bge_setmulti(struct bge_softc *); 150 151 void bge_handle_events(struct bge_softc *); 152 int bge_alloc_jumbo_mem(struct bge_softc *); 153 void bge_free_jumbo_mem(struct bge_softc *); 154 void *bge_jalloc(struct bge_softc *); 155 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 156 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 157 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 158 int bge_init_rx_ring_std(struct bge_softc *); 159 void bge_free_rx_ring_std(struct bge_softc *); 160 int bge_init_rx_ring_jumbo(struct bge_softc *); 161 void bge_free_rx_ring_jumbo(struct bge_softc *); 162 void bge_free_tx_ring(struct bge_softc *); 163 int bge_init_tx_ring(struct bge_softc *); 164 165 int bge_chipinit(struct bge_softc *); 166 int bge_blockinit(struct bge_softc *); 167 int bge_setpowerstate(struct bge_softc *, int); 168 169 #ifdef notdef 170 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 171 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 172 void bge_vpd_read(struct bge_softc *); 173 #endif 174 175 u_int32_t bge_readmem_ind(struct bge_softc *, int); 176 void bge_writemem_ind(struct bge_softc *, int, int); 177 #ifdef notdef 178 u_int32_t bge_readreg_ind(struct bge_softc *, int); 179 #endif 180 void bge_writereg_ind(struct bge_softc *, int, int); 181 182 int bge_miibus_readreg(struct device *, int, int); 183 void bge_miibus_writereg(struct device *, int, int, int); 184 void bge_miibus_statchg(struct device *); 185 186 void bge_reset(struct bge_softc *); 187 188 void bge_dump_status(struct bge_softc *); 189 void bge_dump_rxbd(struct bge_rx_bd *); 190 191 #define BGE_DEBUG 192 #ifdef BGE_DEBUG 193 #define DPRINTF(x) if (bgedebug) printf x 194 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 195 int bgedebug = 0; 196 #else 197 #define DPRINTF(x) 198 #define DPRINTFN(n,x) 199 #endif 200 201 /* Various chip quirks. */ 202 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 203 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 204 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 205 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 206 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 207 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 208 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 209 210 /* following bugs are common to bcm5700 rev B, all flavours */ 211 #define BGE_QUIRK_5700_COMMON \ 212 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 213 214 CFATTACH_DECL(bge, sizeof(struct bge_softc), 215 bge_probe, bge_attach, NULL, NULL); 216 217 u_int32_t 218 bge_readmem_ind(sc, off) 219 struct bge_softc *sc; 220 int off; 221 { 222 struct pci_attach_args *pa = &(sc->bge_pa); 223 pcireg_t val; 224 225 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 226 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 227 return val; 228 } 229 230 void 231 bge_writemem_ind(sc, off, val) 232 struct bge_softc *sc; 233 int off, val; 234 { 235 struct pci_attach_args *pa = &(sc->bge_pa); 236 237 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 238 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 239 } 240 241 #ifdef notdef 242 u_int32_t 243 bge_readreg_ind(sc, off) 244 struct bge_softc *sc; 245 int off; 246 { 247 struct pci_attach_args *pa = &(sc->bge_pa); 248 249 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 250 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 251 } 252 #endif 253 254 void 255 bge_writereg_ind(sc, off, val) 256 struct bge_softc *sc; 257 int off, val; 258 { 259 struct pci_attach_args *pa = &(sc->bge_pa); 260 261 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 262 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 263 } 264 265 #ifdef notdef 266 u_int8_t 267 bge_vpd_readbyte(sc, addr) 268 struct bge_softc *sc; 269 int addr; 270 { 271 int i; 272 u_int32_t val; 273 struct pci_attach_args *pa = &(sc->bge_pa); 274 275 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 276 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 277 DELAY(10); 278 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 279 BGE_VPD_FLAG) 280 break; 281 } 282 283 if (i == BGE_TIMEOUT) { 284 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 285 return(0); 286 } 287 288 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 289 290 return((val >> ((addr % 4) * 8)) & 0xFF); 291 } 292 293 void 294 bge_vpd_read_res(sc, res, addr) 295 struct bge_softc *sc; 296 struct vpd_res *res; 297 int addr; 298 { 299 int i; 300 u_int8_t *ptr; 301 302 ptr = (u_int8_t *)res; 303 for (i = 0; i < sizeof(struct vpd_res); i++) 304 ptr[i] = bge_vpd_readbyte(sc, i + addr); 305 } 306 307 void 308 bge_vpd_read(sc) 309 struct bge_softc *sc; 310 { 311 int pos = 0, i; 312 struct vpd_res res; 313 314 if (sc->bge_vpd_prodname != NULL) 315 free(sc->bge_vpd_prodname, M_DEVBUF); 316 if (sc->bge_vpd_readonly != NULL) 317 free(sc->bge_vpd_readonly, M_DEVBUF); 318 sc->bge_vpd_prodname = NULL; 319 sc->bge_vpd_readonly = NULL; 320 321 bge_vpd_read_res(sc, &res, pos); 322 323 if (res.vr_id != VPD_RES_ID) { 324 printf("%s: bad VPD resource id: expected %x got %x\n", 325 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 326 return; 327 } 328 329 pos += sizeof(res); 330 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 331 if (sc->bge_vpd_prodname == NULL) 332 panic("bge_vpd_read"); 333 for (i = 0; i < res.vr_len; i++) 334 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 335 sc->bge_vpd_prodname[i] = '\0'; 336 pos += i; 337 338 bge_vpd_read_res(sc, &res, pos); 339 340 if (res.vr_id != VPD_RES_READ) { 341 printf("%s: bad VPD resource id: expected %x got %x\n", 342 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 343 return; 344 } 345 346 pos += sizeof(res); 347 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 348 if (sc->bge_vpd_readonly == NULL) 349 panic("bge_vpd_read"); 350 for (i = 0; i < res.vr_len + 1; i++) 351 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 352 } 353 #endif 354 355 /* 356 * Read a byte of data stored in the EEPROM at address 'addr.' The 357 * BCM570x supports both the traditional bitbang interface and an 358 * auto access interface for reading the EEPROM. We use the auto 359 * access method. 360 */ 361 u_int8_t 362 bge_eeprom_getbyte(sc, addr, dest) 363 struct bge_softc *sc; 364 int addr; 365 u_int8_t *dest; 366 { 367 int i; 368 u_int32_t byte = 0; 369 370 /* 371 * Enable use of auto EEPROM access so we can avoid 372 * having to use the bitbang method. 373 */ 374 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 375 376 /* Reset the EEPROM, load the clock period. */ 377 CSR_WRITE_4(sc, BGE_EE_ADDR, 378 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 379 DELAY(20); 380 381 /* Issue the read EEPROM command. */ 382 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 383 384 /* Wait for completion */ 385 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 386 DELAY(10); 387 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 388 break; 389 } 390 391 if (i == BGE_TIMEOUT) { 392 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 393 return(0); 394 } 395 396 /* Get result. */ 397 byte = CSR_READ_4(sc, BGE_EE_DATA); 398 399 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 400 401 return(0); 402 } 403 404 /* 405 * Read a sequence of bytes from the EEPROM. 406 */ 407 int 408 bge_read_eeprom(sc, dest, off, cnt) 409 struct bge_softc *sc; 410 caddr_t dest; 411 int off; 412 int cnt; 413 { 414 int err = 0, i; 415 u_int8_t byte = 0; 416 417 for (i = 0; i < cnt; i++) { 418 err = bge_eeprom_getbyte(sc, off + i, &byte); 419 if (err) 420 break; 421 *(dest + i) = byte; 422 } 423 424 return(err ? 1 : 0); 425 } 426 427 int 428 bge_miibus_readreg(dev, phy, reg) 429 struct device *dev; 430 int phy, reg; 431 { 432 struct bge_softc *sc = (struct bge_softc *)dev; 433 struct ifnet *ifp; 434 u_int32_t val; 435 u_int32_t saved_autopoll; 436 int i; 437 438 ifp = &sc->ethercom.ec_if; 439 440 /* 441 * Several chips with builtin PHYs will incorrectly answer to 442 * other PHY instances than the builtin PHY at id 1. 443 */ 444 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 445 return(0); 446 447 /* Reading with autopolling on may trigger PCI errors */ 448 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 449 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 450 CSR_WRITE_4(sc, BGE_MI_MODE, 451 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 452 DELAY(40); 453 } 454 455 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 456 BGE_MIPHY(phy)|BGE_MIREG(reg)); 457 458 for (i = 0; i < BGE_TIMEOUT; i++) { 459 val = CSR_READ_4(sc, BGE_MI_COMM); 460 if (!(val & BGE_MICOMM_BUSY)) 461 break; 462 delay(10); 463 } 464 465 if (i == BGE_TIMEOUT) { 466 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 467 val = 0; 468 goto done; 469 } 470 471 val = CSR_READ_4(sc, BGE_MI_COMM); 472 473 done: 474 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 475 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 476 DELAY(40); 477 } 478 479 if (val & BGE_MICOMM_READFAIL) 480 return(0); 481 482 return(val & 0xFFFF); 483 } 484 485 void 486 bge_miibus_writereg(dev, phy, reg, val) 487 struct device *dev; 488 int phy, reg, val; 489 { 490 struct bge_softc *sc = (struct bge_softc *)dev; 491 u_int32_t saved_autopoll; 492 int i; 493 494 /* Touching the PHY while autopolling is on may trigger PCI errors */ 495 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 496 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 497 delay(40); 498 CSR_WRITE_4(sc, BGE_MI_MODE, 499 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 500 delay(10); /* 40 usec is supposed to be adequate */ 501 } 502 503 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 504 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 505 506 for (i = 0; i < BGE_TIMEOUT; i++) { 507 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 508 break; 509 delay(10); 510 } 511 512 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 513 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 514 delay(40); 515 } 516 517 if (i == BGE_TIMEOUT) { 518 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 519 } 520 } 521 522 void 523 bge_miibus_statchg(dev) 524 struct device *dev; 525 { 526 struct bge_softc *sc = (struct bge_softc *)dev; 527 struct mii_data *mii = &sc->bge_mii; 528 529 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 530 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 531 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 532 } else { 533 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 534 } 535 536 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 537 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 538 } else { 539 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 540 } 541 } 542 543 /* 544 * Handle events that have triggered interrupts. 545 */ 546 void 547 bge_handle_events(sc) 548 struct bge_softc *sc; 549 { 550 551 return; 552 } 553 554 /* 555 * Memory management for jumbo frames. 556 */ 557 558 int 559 bge_alloc_jumbo_mem(sc) 560 struct bge_softc *sc; 561 { 562 caddr_t ptr, kva; 563 bus_dma_segment_t seg; 564 int i, rseg, state, error; 565 struct bge_jpool_entry *entry; 566 567 state = error = 0; 568 569 /* Grab a big chunk o' storage. */ 570 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 571 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 572 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 573 return ENOBUFS; 574 } 575 576 state = 1; 577 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 578 BUS_DMA_NOWAIT)) { 579 printf("%s: can't map DMA buffers (%d bytes)\n", 580 sc->bge_dev.dv_xname, (int)BGE_JMEM); 581 error = ENOBUFS; 582 goto out; 583 } 584 585 state = 2; 586 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 587 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 588 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 589 error = ENOBUFS; 590 goto out; 591 } 592 593 state = 3; 594 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 595 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 596 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 597 error = ENOBUFS; 598 goto out; 599 } 600 601 state = 4; 602 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 603 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 604 605 SLIST_INIT(&sc->bge_jfree_listhead); 606 SLIST_INIT(&sc->bge_jinuse_listhead); 607 608 /* 609 * Now divide it up into 9K pieces and save the addresses 610 * in an array. 611 */ 612 ptr = sc->bge_cdata.bge_jumbo_buf; 613 for (i = 0; i < BGE_JSLOTS; i++) { 614 sc->bge_cdata.bge_jslots[i] = ptr; 615 ptr += BGE_JLEN; 616 entry = malloc(sizeof(struct bge_jpool_entry), 617 M_DEVBUF, M_NOWAIT); 618 if (entry == NULL) { 619 printf("%s: no memory for jumbo buffer queue!\n", 620 sc->bge_dev.dv_xname); 621 error = ENOBUFS; 622 goto out; 623 } 624 entry->slot = i; 625 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 626 entry, jpool_entries); 627 } 628 out: 629 if (error != 0) { 630 switch (state) { 631 case 4: 632 bus_dmamap_unload(sc->bge_dmatag, 633 sc->bge_cdata.bge_rx_jumbo_map); 634 case 3: 635 bus_dmamap_destroy(sc->bge_dmatag, 636 sc->bge_cdata.bge_rx_jumbo_map); 637 case 2: 638 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 639 case 1: 640 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 641 break; 642 default: 643 break; 644 } 645 } 646 647 return error; 648 } 649 650 /* 651 * Allocate a jumbo buffer. 652 */ 653 void * 654 bge_jalloc(sc) 655 struct bge_softc *sc; 656 { 657 struct bge_jpool_entry *entry; 658 659 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 660 661 if (entry == NULL) { 662 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 663 return(NULL); 664 } 665 666 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 667 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 668 return(sc->bge_cdata.bge_jslots[entry->slot]); 669 } 670 671 /* 672 * Release a jumbo buffer. 673 */ 674 void 675 bge_jfree(m, buf, size, arg) 676 struct mbuf *m; 677 caddr_t buf; 678 size_t size; 679 void *arg; 680 { 681 struct bge_jpool_entry *entry; 682 struct bge_softc *sc; 683 int i, s; 684 685 /* Extract the softc struct pointer. */ 686 sc = (struct bge_softc *)arg; 687 688 if (sc == NULL) 689 panic("bge_jfree: can't find softc pointer!"); 690 691 /* calculate the slot this buffer belongs to */ 692 693 i = ((caddr_t)buf 694 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 695 696 if ((i < 0) || (i >= BGE_JSLOTS)) 697 panic("bge_jfree: asked to free buffer that we don't manage!"); 698 699 s = splvm(); 700 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 701 if (entry == NULL) 702 panic("bge_jfree: buffer not in use!"); 703 entry->slot = i; 704 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 705 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 706 707 if (__predict_true(m != NULL)) 708 pool_cache_put(&mbpool_cache, m); 709 splx(s); 710 } 711 712 713 /* 714 * Intialize a standard receive ring descriptor. 715 */ 716 int 717 bge_newbuf_std(sc, i, m, dmamap) 718 struct bge_softc *sc; 719 int i; 720 struct mbuf *m; 721 bus_dmamap_t dmamap; 722 { 723 struct mbuf *m_new = NULL; 724 struct bge_rx_bd *r; 725 int error; 726 727 if (dmamap == NULL) { 728 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 729 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 730 if (error != 0) 731 return error; 732 } 733 734 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 735 736 if (m == NULL) { 737 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 738 if (m_new == NULL) { 739 return(ENOBUFS); 740 } 741 742 MCLGET(m_new, M_DONTWAIT); 743 if (!(m_new->m_flags & M_EXT)) { 744 m_freem(m_new); 745 return(ENOBUFS); 746 } 747 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 748 if (!sc->bge_rx_alignment_bug) 749 m_adj(m_new, ETHER_ALIGN); 750 751 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 752 BUS_DMA_READ|BUS_DMA_NOWAIT)) 753 return(ENOBUFS); 754 } else { 755 m_new = m; 756 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 757 m_new->m_data = m_new->m_ext.ext_buf; 758 if (!sc->bge_rx_alignment_bug) 759 m_adj(m_new, ETHER_ALIGN); 760 } 761 762 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 763 r = &sc->bge_rdata->bge_rx_std_ring[i]; 764 bge_set_hostaddr(&r->bge_addr, 765 dmamap->dm_segs[0].ds_addr); 766 r->bge_flags = BGE_RXBDFLAG_END; 767 r->bge_len = m_new->m_len; 768 r->bge_idx = i; 769 770 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 771 offsetof(struct bge_ring_data, bge_rx_std_ring) + 772 i * sizeof (struct bge_rx_bd), 773 sizeof (struct bge_rx_bd), 774 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 775 776 return(0); 777 } 778 779 /* 780 * Initialize a jumbo receive ring descriptor. This allocates 781 * a jumbo buffer from the pool managed internally by the driver. 782 */ 783 int 784 bge_newbuf_jumbo(sc, i, m) 785 struct bge_softc *sc; 786 int i; 787 struct mbuf *m; 788 { 789 struct mbuf *m_new = NULL; 790 struct bge_rx_bd *r; 791 792 if (m == NULL) { 793 caddr_t *buf = NULL; 794 795 /* Allocate the mbuf. */ 796 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 797 if (m_new == NULL) { 798 return(ENOBUFS); 799 } 800 801 /* Allocate the jumbo buffer */ 802 buf = bge_jalloc(sc); 803 if (buf == NULL) { 804 m_freem(m_new); 805 printf("%s: jumbo allocation failed " 806 "-- packet dropped!\n", sc->bge_dev.dv_xname); 807 return(ENOBUFS); 808 } 809 810 /* Attach the buffer to the mbuf. */ 811 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 812 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 813 bge_jfree, sc); 814 } else { 815 m_new = m; 816 m_new->m_data = m_new->m_ext.ext_buf; 817 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 818 } 819 820 if (!sc->bge_rx_alignment_bug) 821 m_adj(m_new, ETHER_ALIGN); 822 /* Set up the descriptor. */ 823 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 824 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 825 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 826 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 827 r->bge_len = m_new->m_len; 828 r->bge_idx = i; 829 830 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 831 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 832 i * sizeof (struct bge_rx_bd), 833 sizeof (struct bge_rx_bd), 834 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 835 836 return(0); 837 } 838 839 /* 840 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 841 * that's 1MB or memory, which is a lot. For now, we fill only the first 842 * 256 ring entries and hope that our CPU is fast enough to keep up with 843 * the NIC. 844 */ 845 int 846 bge_init_rx_ring_std(sc) 847 struct bge_softc *sc; 848 { 849 int i; 850 851 if (sc->bge_flags & BGE_RXRING_VALID) 852 return 0; 853 854 for (i = 0; i < BGE_SSLOTS; i++) { 855 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 856 return(ENOBUFS); 857 } 858 859 sc->bge_std = i - 1; 860 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 861 862 sc->bge_flags |= BGE_RXRING_VALID; 863 864 return(0); 865 } 866 867 void 868 bge_free_rx_ring_std(sc) 869 struct bge_softc *sc; 870 { 871 int i; 872 873 if (!(sc->bge_flags & BGE_RXRING_VALID)) 874 return; 875 876 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 877 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 878 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 879 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 880 bus_dmamap_destroy(sc->bge_dmatag, 881 sc->bge_cdata.bge_rx_std_map[i]); 882 } 883 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 884 sizeof(struct bge_rx_bd)); 885 } 886 887 sc->bge_flags &= ~BGE_RXRING_VALID; 888 } 889 890 int 891 bge_init_rx_ring_jumbo(sc) 892 struct bge_softc *sc; 893 { 894 int i; 895 volatile struct bge_rcb *rcb; 896 897 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 898 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 899 return(ENOBUFS); 900 }; 901 902 sc->bge_jumbo = i - 1; 903 904 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 905 rcb->bge_maxlen_flags = 0; 906 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 907 908 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 909 910 return(0); 911 } 912 913 void 914 bge_free_rx_ring_jumbo(sc) 915 struct bge_softc *sc; 916 { 917 int i; 918 919 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 920 return; 921 922 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 923 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 924 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 925 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 926 } 927 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 928 sizeof(struct bge_rx_bd)); 929 } 930 931 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 932 } 933 934 void 935 bge_free_tx_ring(sc) 936 struct bge_softc *sc; 937 { 938 int i, freed; 939 struct txdmamap_pool_entry *dma; 940 941 if (!(sc->bge_flags & BGE_TXRING_VALID)) 942 return; 943 944 freed = 0; 945 946 for (i = 0; i < BGE_TX_RING_CNT; i++) { 947 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 948 freed++; 949 m_freem(sc->bge_cdata.bge_tx_chain[i]); 950 sc->bge_cdata.bge_tx_chain[i] = NULL; 951 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 952 link); 953 sc->txdma[i] = 0; 954 } 955 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 956 sizeof(struct bge_tx_bd)); 957 } 958 959 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 960 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 961 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 962 free(dma, M_DEVBUF); 963 } 964 965 sc->bge_flags &= ~BGE_TXRING_VALID; 966 } 967 968 int 969 bge_init_tx_ring(sc) 970 struct bge_softc *sc; 971 { 972 int i; 973 bus_dmamap_t dmamap; 974 struct txdmamap_pool_entry *dma; 975 976 if (sc->bge_flags & BGE_TXRING_VALID) 977 return 0; 978 979 sc->bge_txcnt = 0; 980 sc->bge_tx_saved_considx = 0; 981 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 982 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 983 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 984 985 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 986 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 987 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 988 989 SLIST_INIT(&sc->txdma_list); 990 for (i = 0; i < BGE_RSLOTS; i++) { 991 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 992 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 993 &dmamap)) 994 return(ENOBUFS); 995 if (dmamap == NULL) 996 panic("dmamap NULL in bge_init_tx_ring"); 997 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 998 if (dma == NULL) { 999 printf("%s: can't alloc txdmamap_pool_entry\n", 1000 sc->bge_dev.dv_xname); 1001 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1002 return (ENOMEM); 1003 } 1004 dma->dmamap = dmamap; 1005 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1006 } 1007 1008 sc->bge_flags |= BGE_TXRING_VALID; 1009 1010 return(0); 1011 } 1012 1013 void 1014 bge_setmulti(sc) 1015 struct bge_softc *sc; 1016 { 1017 struct ethercom *ac = &sc->ethercom; 1018 struct ifnet *ifp = &ac->ec_if; 1019 struct ether_multi *enm; 1020 struct ether_multistep step; 1021 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1022 u_int32_t h; 1023 int i; 1024 1025 if (ifp->if_flags & IFF_PROMISC) 1026 goto allmulti; 1027 1028 /* Now program new ones. */ 1029 ETHER_FIRST_MULTI(step, ac, enm); 1030 while (enm != NULL) { 1031 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1032 /* 1033 * We must listen to a range of multicast addresses. 1034 * For now, just accept all multicasts, rather than 1035 * trying to set only those filter bits needed to match 1036 * the range. (At this time, the only use of address 1037 * ranges is for IP multicast routing, for which the 1038 * range is big enough to require all bits set.) 1039 */ 1040 goto allmulti; 1041 } 1042 1043 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1044 1045 /* Just want the 7 least-significant bits. */ 1046 h &= 0x7f; 1047 1048 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1049 ETHER_NEXT_MULTI(step, enm); 1050 } 1051 1052 ifp->if_flags &= ~IFF_ALLMULTI; 1053 goto setit; 1054 1055 allmulti: 1056 ifp->if_flags |= IFF_ALLMULTI; 1057 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1058 1059 setit: 1060 for (i = 0; i < 4; i++) 1061 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1062 } 1063 1064 const int bge_swapbits[] = { 1065 0, 1066 BGE_MODECTL_BYTESWAP_DATA, 1067 BGE_MODECTL_WORDSWAP_DATA, 1068 BGE_MODECTL_BYTESWAP_NONFRAME, 1069 BGE_MODECTL_WORDSWAP_NONFRAME, 1070 1071 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1072 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1073 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1074 1075 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1076 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1077 1078 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1079 1080 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1081 BGE_MODECTL_BYTESWAP_NONFRAME, 1082 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1083 BGE_MODECTL_WORDSWAP_NONFRAME, 1084 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1085 BGE_MODECTL_WORDSWAP_NONFRAME, 1086 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1087 BGE_MODECTL_WORDSWAP_NONFRAME, 1088 1089 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1090 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1091 }; 1092 1093 int bge_swapindex = 0; 1094 1095 /* 1096 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1097 * self-test results. 1098 */ 1099 int 1100 bge_chipinit(sc) 1101 struct bge_softc *sc; 1102 { 1103 u_int32_t cachesize; 1104 int i; 1105 u_int32_t dma_rw_ctl; 1106 struct pci_attach_args *pa = &(sc->bge_pa); 1107 1108 1109 /* Set endianness before we access any non-PCI registers. */ 1110 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1111 BGE_INIT); 1112 1113 /* Set power state to D0. */ 1114 bge_setpowerstate(sc, 0); 1115 1116 /* 1117 * Check the 'ROM failed' bit on the RX CPU to see if 1118 * self-tests passed. 1119 */ 1120 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1121 printf("%s: RX CPU self-diagnostics failed!\n", 1122 sc->bge_dev.dv_xname); 1123 return(ENODEV); 1124 } 1125 1126 /* Clear the MAC control register */ 1127 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1128 1129 /* 1130 * Clear the MAC statistics block in the NIC's 1131 * internal memory. 1132 */ 1133 for (i = BGE_STATS_BLOCK; 1134 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1135 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1136 1137 for (i = BGE_STATUS_BLOCK; 1138 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1139 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1140 1141 /* Set up the PCI DMA control register. */ 1142 if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1143 BGE_PCISTATE_PCI_BUSMODE) { 1144 /* Conventional PCI bus */ 1145 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1146 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1147 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1148 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1149 (0x0F)); 1150 } else { 1151 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1152 /* PCI-X bus */ 1153 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1154 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1155 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1156 (0x0F); 1157 /* 1158 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1159 * for hardware bugs, which means we should also clear 1160 * the low-order MINDMA bits. In addition, the 5704 1161 * uses a different encoding of read/write watermarks. 1162 */ 1163 if (sc->bge_asicrev == BGE_ASICREV_BCM5704_A0 || 1164 sc->bge_asicrev == BGE_ASICREV_BCM5704_A1 || 1165 sc->bge_asicrev == BGE_ASICREV_BCM5704_A2) { 1166 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1167 /* should be 0x1f0000 */ 1168 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1169 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1170 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1171 } 1172 else if ((sc->bge_asicrev >> 28) == 1173 (BGE_ASICREV_BCM5703_A0 >> 28)) { 1174 dma_rw_ctl &= 0xfffffff0; 1175 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1176 } 1177 } 1178 1179 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1180 1181 /* 1182 * Set up general mode register. 1183 */ 1184 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1185 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1186 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1187 BGE_MODECTL_RX_NO_PHDR_CSUM); 1188 1189 /* Get cache line size. */ 1190 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1191 1192 /* 1193 * Avoid violating PCI spec on certain chip revs. 1194 */ 1195 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1196 PCIM_CMD_MWIEN) { 1197 switch(cachesize) { 1198 case 1: 1199 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1200 BGE_PCI_WRITE_BNDRY_16BYTES); 1201 break; 1202 case 2: 1203 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1204 BGE_PCI_WRITE_BNDRY_32BYTES); 1205 break; 1206 case 4: 1207 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1208 BGE_PCI_WRITE_BNDRY_64BYTES); 1209 break; 1210 case 8: 1211 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1212 BGE_PCI_WRITE_BNDRY_128BYTES); 1213 break; 1214 case 16: 1215 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1216 BGE_PCI_WRITE_BNDRY_256BYTES); 1217 break; 1218 case 32: 1219 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1220 BGE_PCI_WRITE_BNDRY_512BYTES); 1221 break; 1222 case 64: 1223 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1224 BGE_PCI_WRITE_BNDRY_1024BYTES); 1225 break; 1226 default: 1227 /* Disable PCI memory write and invalidate. */ 1228 #if 0 1229 if (bootverbose) 1230 printf("%s: cache line size %d not " 1231 "supported; disabling PCI MWI\n", 1232 sc->bge_dev.dv_xname, cachesize); 1233 #endif 1234 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1235 PCIM_CMD_MWIEN); 1236 break; 1237 } 1238 } 1239 1240 /* 1241 * Disable memory write invalidate. Apparently it is not supported 1242 * properly by these devices. 1243 */ 1244 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1245 1246 1247 #ifdef __brokenalpha__ 1248 /* 1249 * Must insure that we do not cross an 8K (bytes) boundary 1250 * for DMA reads. Our highest limit is 1K bytes. This is a 1251 * restriction on some ALPHA platforms with early revision 1252 * 21174 PCI chipsets, such as the AlphaPC 164lx 1253 */ 1254 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1255 #endif 1256 1257 /* Set the timer prescaler (always 66MHz) */ 1258 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1259 1260 return(0); 1261 } 1262 1263 int 1264 bge_blockinit(sc) 1265 struct bge_softc *sc; 1266 { 1267 volatile struct bge_rcb *rcb; 1268 bus_size_t rcb_addr; 1269 int i; 1270 struct ifnet *ifp = &sc->ethercom.ec_if; 1271 bge_hostaddr taddr; 1272 1273 /* 1274 * Initialize the memory window pointer register so that 1275 * we can access the first 32K of internal NIC RAM. This will 1276 * allow us to set up the TX send ring RCBs and the RX return 1277 * ring RCBs, plus other things which live in NIC memory. 1278 */ 1279 1280 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1281 BGE_PCI_MEMWIN_BASEADDR, 0); 1282 1283 /* Configure mbuf memory pool */ 1284 if (sc->bge_extram) { 1285 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1286 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1287 } else { 1288 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1289 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1290 } 1291 1292 /* Configure DMA resource pool */ 1293 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1294 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1295 1296 /* Configure mbuf pool watermarks */ 1297 #ifdef ORIG_WPAUL_VALUES 1298 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1299 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1300 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1301 #else 1302 /* new broadcom docs strongly recommend these: */ 1303 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1304 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1305 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1306 #endif 1307 1308 /* Configure DMA resource watermarks */ 1309 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1310 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1311 1312 /* Enable buffer manager */ 1313 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1314 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1315 1316 /* Poll for buffer manager start indication */ 1317 for (i = 0; i < BGE_TIMEOUT; i++) { 1318 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1319 break; 1320 DELAY(10); 1321 } 1322 1323 if (i == BGE_TIMEOUT) { 1324 printf("%s: buffer manager failed to start\n", 1325 sc->bge_dev.dv_xname); 1326 return(ENXIO); 1327 } 1328 1329 /* Enable flow-through queues */ 1330 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1331 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1332 1333 /* Wait until queue initialization is complete */ 1334 for (i = 0; i < BGE_TIMEOUT; i++) { 1335 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1336 break; 1337 DELAY(10); 1338 } 1339 1340 if (i == BGE_TIMEOUT) { 1341 printf("%s: flow-through queue init failed\n", 1342 sc->bge_dev.dv_xname); 1343 return(ENXIO); 1344 } 1345 1346 /* Initialize the standard RX ring control block */ 1347 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1348 bge_set_hostaddr(&rcb->bge_hostaddr, 1349 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1350 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1351 if (sc->bge_extram) 1352 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1353 else 1354 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1355 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1356 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1357 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1358 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1359 1360 /* 1361 * Initialize the jumbo RX ring control block 1362 * We set the 'ring disabled' bit in the flags 1363 * field until we're actually ready to start 1364 * using this ring (i.e. once we set the MTU 1365 * high enough to require it). 1366 */ 1367 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1368 bge_set_hostaddr(&rcb->bge_hostaddr, 1369 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1370 rcb->bge_maxlen_flags = 1371 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1372 if (sc->bge_extram) 1373 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1374 else 1375 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1376 1377 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1378 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1379 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1380 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1381 1382 /* Set up dummy disabled mini ring RCB */ 1383 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1384 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1385 BGE_RCB_FLAG_RING_DISABLED); 1386 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1387 1388 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1389 offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib), 1390 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1391 1392 /* 1393 * Set the BD ring replentish thresholds. The recommended 1394 * values are 1/8th the number of descriptors allocated to 1395 * each ring. 1396 */ 1397 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1398 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1399 1400 /* 1401 * Disable all unused send rings by setting the 'ring disabled' 1402 * bit in the flags field of all the TX send ring control blocks. 1403 * These are located in NIC memory. 1404 */ 1405 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1406 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1407 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1408 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1409 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1410 rcb_addr += sizeof(struct bge_rcb); 1411 } 1412 1413 /* Configure TX RCB 0 (we use only the first ring) */ 1414 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1415 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1416 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1417 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1418 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1419 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1420 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1421 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1422 1423 /* Disable all unused RX return rings */ 1424 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1425 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1426 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1427 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1428 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1429 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1430 BGE_RCB_FLAG_RING_DISABLED)); 1431 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1432 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1433 (i * (sizeof(u_int64_t))), 0); 1434 rcb_addr += sizeof(struct bge_rcb); 1435 } 1436 1437 /* Initialize RX ring indexes */ 1438 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1439 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1440 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1441 1442 /* 1443 * Set up RX return ring 0 1444 * Note that the NIC address for RX return rings is 0x00000000. 1445 * The return rings live entirely within the host, so the 1446 * nicaddr field in the RCB isn't used. 1447 */ 1448 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1449 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1450 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1451 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1452 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1453 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1454 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT,0)); 1455 1456 /* Set random backoff seed for TX */ 1457 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1458 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1459 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1460 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1461 BGE_TX_BACKOFF_SEED_MASK); 1462 1463 /* Set inter-packet gap */ 1464 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1465 1466 /* 1467 * Specify which ring to use for packets that don't match 1468 * any RX rules. 1469 */ 1470 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1471 1472 /* 1473 * Configure number of RX lists. One interrupt distribution 1474 * list, sixteen active lists, one bad frames class. 1475 */ 1476 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1477 1478 /* Inialize RX list placement stats mask. */ 1479 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1480 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1481 1482 /* Disable host coalescing until we get it set up */ 1483 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1484 1485 /* Poll to make sure it's shut down. */ 1486 for (i = 0; i < BGE_TIMEOUT; i++) { 1487 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1488 break; 1489 DELAY(10); 1490 } 1491 1492 if (i == BGE_TIMEOUT) { 1493 printf("%s: host coalescing engine failed to idle\n", 1494 sc->bge_dev.dv_xname); 1495 return(ENXIO); 1496 } 1497 1498 /* Set up host coalescing defaults */ 1499 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1500 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1501 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1502 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1503 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1504 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1505 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1506 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1507 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1508 1509 /* Set up address of statistics block */ 1510 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1511 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1512 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1513 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1514 1515 /* Set up address of status block */ 1516 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1517 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1518 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1519 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1520 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1521 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1522 1523 /* Turn on host coalescing state machine */ 1524 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1525 1526 /* Turn on RX BD completion state machine and enable attentions */ 1527 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1528 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1529 1530 /* Turn on RX list placement state machine */ 1531 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1532 1533 /* Turn on RX list selector state machine. */ 1534 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1535 1536 /* Turn on DMA, clear stats */ 1537 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1538 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1539 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1540 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1541 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1542 1543 /* Set misc. local control, enable interrupts on attentions */ 1544 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1545 1546 #ifdef notdef 1547 /* Assert GPIO pins for PHY reset */ 1548 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1549 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1550 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1551 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1552 #endif 1553 1554 #if defined(not_quite_yet) 1555 /* Linux driver enables enable gpio pin #1 on 5700s */ 1556 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 1557 sc->bge_local_ctrl_reg |= 1558 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1559 } 1560 #endif 1561 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1562 1563 /* Turn on DMA completion state machine */ 1564 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1565 1566 /* Turn on write DMA state machine */ 1567 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1568 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1569 1570 /* Turn on read DMA state machine */ 1571 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1572 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1573 1574 /* Turn on RX data completion state machine */ 1575 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1576 1577 /* Turn on RX BD initiator state machine */ 1578 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1579 1580 /* Turn on RX data and RX BD initiator state machine */ 1581 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1582 1583 /* Turn on Mbuf cluster free state machine */ 1584 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1585 1586 /* Turn on send BD completion state machine */ 1587 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1588 1589 /* Turn on send data completion state machine */ 1590 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1591 1592 /* Turn on send data initiator state machine */ 1593 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1594 1595 /* Turn on send BD initiator state machine */ 1596 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1597 1598 /* Turn on send BD selector state machine */ 1599 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1600 1601 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1602 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1603 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1604 1605 /* init LED register */ 1606 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1607 1608 /* ack/clear link change events */ 1609 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1610 BGE_MACSTAT_CFG_CHANGED); 1611 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1612 1613 /* Enable PHY auto polling (for MII/GMII only) */ 1614 if (sc->bge_tbi) { 1615 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1616 } else { 1617 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1618 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1619 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1620 BGE_EVTENB_MI_INTERRUPT); 1621 } 1622 1623 /* Enable link state change attentions. */ 1624 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1625 1626 return(0); 1627 } 1628 1629 static const struct bge_revision { 1630 uint32_t br_asicrev; 1631 uint32_t br_quirks; 1632 const char *br_name; 1633 } bge_revisions[] = { 1634 { BGE_ASICREV_BCM5700_A0, 1635 BGE_QUIRK_LINK_STATE_BROKEN, 1636 "BCM5700 A0" }, 1637 1638 { BGE_ASICREV_BCM5700_A1, 1639 BGE_QUIRK_LINK_STATE_BROKEN, 1640 "BCM5700 A1" }, 1641 1642 { BGE_ASICREV_BCM5700_B0, 1643 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1644 "BCM5700 B0" }, 1645 1646 { BGE_ASICREV_BCM5700_B1, 1647 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1648 "BCM5700 B1" }, 1649 1650 { BGE_ASICREV_BCM5700_B2, 1651 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1652 "BCM5700 B2" }, 1653 1654 /* This is treated like a BCM5700 Bx */ 1655 { BGE_ASICREV_BCM5700_ALTIMA, 1656 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1657 "BCM5700 Altima" }, 1658 1659 { BGE_ASICREV_BCM5700_C0, 1660 0, 1661 "BCM5700 C0" }, 1662 1663 { BGE_ASICREV_BCM5701_A0, 1664 0, /*XXX really, just not known */ 1665 "BCM5701 A0" }, 1666 1667 { BGE_ASICREV_BCM5701_B0, 1668 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1669 "BCM5701 B0" }, 1670 1671 { BGE_ASICREV_BCM5701_B2, 1672 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1673 "BCM5701 B2" }, 1674 1675 { BGE_ASICREV_BCM5701_B5, 1676 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1677 "BCM5701 B5" }, 1678 1679 { BGE_ASICREV_BCM5703_A0, 1680 0, 1681 "BCM5703 A0" }, 1682 1683 { BGE_ASICREV_BCM5703_A1, 1684 0, 1685 "BCM5703 A1" }, 1686 1687 { BGE_ASICREV_BCM5703_A2, 1688 BGE_QUIRK_ONLY_PHY_1, 1689 "BCM5703 A2" }, 1690 1691 { BGE_ASICREV_BCM5704_A0, 1692 BGE_QUIRK_ONLY_PHY_1, 1693 "BCM5704 A0" }, 1694 1695 { BGE_ASICREV_BCM5704_A1, 1696 BGE_QUIRK_ONLY_PHY_1, 1697 "BCM5704 A1" }, 1698 1699 { BGE_ASICREV_BCM5704_A2, 1700 BGE_QUIRK_ONLY_PHY_1, 1701 "BCM5704 A2" }, 1702 1703 { 0, 0, NULL } 1704 }; 1705 1706 static const struct bge_revision * 1707 bge_lookup_rev(uint32_t asicrev) 1708 { 1709 const struct bge_revision *br; 1710 1711 for (br = bge_revisions; br->br_name != NULL; br++) { 1712 if (br->br_asicrev == asicrev) 1713 return (br); 1714 } 1715 1716 return (NULL); 1717 } 1718 1719 static const struct bge_product { 1720 pci_vendor_id_t bp_vendor; 1721 pci_product_id_t bp_product; 1722 const char *bp_name; 1723 } bge_products[] = { 1724 /* 1725 * The BCM5700 documentation seems to indicate that the hardware 1726 * still has the Alteon vendor ID burned into it, though it 1727 * should always be overridden by the value in the EEPROM. We'll 1728 * check for it anyway. 1729 */ 1730 { PCI_VENDOR_ALTEON, 1731 PCI_PRODUCT_ALTEON_BCM5700, 1732 "Broadcom BCM5700 Gigabit Ethernet" }, 1733 { PCI_VENDOR_ALTEON, 1734 PCI_PRODUCT_ALTEON_BCM5701, 1735 "Broadcom BCM5701 Gigabit Ethernet" }, 1736 1737 { PCI_VENDOR_ALTIMA, 1738 PCI_PRODUCT_ALTIMA_AC1000, 1739 "Altima AC1000 Gigabit Ethernet" }, 1740 { PCI_VENDOR_ALTIMA, 1741 PCI_PRODUCT_ALTIMA_AC1001, 1742 "Altima AC1001 Gigabit Ethernet" }, 1743 { PCI_VENDOR_ALTIMA, 1744 PCI_PRODUCT_ALTIMA_AC9100, 1745 "Altima AC9100 Gigabit Ethernet" }, 1746 1747 { PCI_VENDOR_BROADCOM, 1748 PCI_PRODUCT_BROADCOM_BCM5700, 1749 "Broadcom BCM5700 Gigabit Ethernet" }, 1750 { PCI_VENDOR_BROADCOM, 1751 PCI_PRODUCT_BROADCOM_BCM5701, 1752 "Broadcom BCM5701 Gigabit Ethernet" }, 1753 { PCI_VENDOR_BROADCOM, 1754 PCI_PRODUCT_BROADCOM_BCM5702, 1755 "Broadcom BCM5702 Gigabit Ethernet" }, 1756 { PCI_VENDOR_BROADCOM, 1757 PCI_PRODUCT_BROADCOM_BCM5702X, 1758 "Broadcom BCM5702X Gigabit Ethernet" }, 1759 { PCI_VENDOR_BROADCOM, 1760 PCI_PRODUCT_BROADCOM_BCM5703, 1761 "Broadcom BCM5703 Gigabit Ethernet" }, 1762 { PCI_VENDOR_BROADCOM, 1763 PCI_PRODUCT_BROADCOM_BCM5703X, 1764 "Broadcom BCM5703X Gigabit Ethernet" }, 1765 { PCI_VENDOR_BROADCOM, 1766 PCI_PRODUCT_BROADCOM_BCM5704C, 1767 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 1768 { PCI_VENDOR_BROADCOM, 1769 PCI_PRODUCT_BROADCOM_BCM5704S, 1770 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 1771 1772 1773 { PCI_VENDOR_SCHNEIDERKOCH, 1774 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1775 "SysKonnect SK-9Dx1 Gigabit Ethernet" }, 1776 1777 { PCI_VENDOR_3COM, 1778 PCI_PRODUCT_3COM_3C996, 1779 "3Com 3c996 Gigabit Ethernet" }, 1780 1781 { 0, 1782 0, 1783 NULL }, 1784 }; 1785 1786 static const struct bge_product * 1787 bge_lookup(const struct pci_attach_args *pa) 1788 { 1789 const struct bge_product *bp; 1790 1791 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1792 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1793 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1794 return (bp); 1795 } 1796 1797 return (NULL); 1798 } 1799 1800 int 1801 bge_setpowerstate(sc, powerlevel) 1802 struct bge_softc *sc; 1803 int powerlevel; 1804 { 1805 #ifdef NOTYET 1806 u_int32_t pm_ctl = 0; 1807 1808 /* XXX FIXME: make sure indirect accesses enabled? */ 1809 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 1810 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 1811 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 1812 1813 /* clear the PME_assert bit and power state bits, enable PME */ 1814 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 1815 pm_ctl &= ~PCIM_PSTAT_DMASK; 1816 pm_ctl |= (1 << 8); 1817 1818 if (powerlevel == 0) { 1819 pm_ctl |= PCIM_PSTAT_D0; 1820 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 1821 pm_ctl, 2); 1822 DELAY(10000); 1823 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1824 DELAY(10000); 1825 1826 #ifdef NOTYET 1827 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 1828 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 1829 #endif 1830 DELAY(40); DELAY(40); DELAY(40); 1831 DELAY(10000); /* above not quite adequate on 5700 */ 1832 return 0; 1833 } 1834 1835 1836 /* 1837 * Entering ACPI power states D1-D3 is achieved by wiggling 1838 * GMII gpio pins. Example code assumes all hardware vendors 1839 * followed Broadom's sample pcb layout. Until we verify that 1840 * for all supported OEM cards, states D1-D3 are unsupported. 1841 */ 1842 printf("%s: power state %d unimplemented; check GPIO pins\n", 1843 sc->bge_dev.dv_xname, powerlevel); 1844 #endif 1845 return EOPNOTSUPP; 1846 } 1847 1848 1849 /* 1850 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1851 * against our list and return its name if we find a match. Note 1852 * that since the Broadcom controller contains VPD support, we 1853 * can get the device name string from the controller itself instead 1854 * of the compiled-in string. This is a little slow, but it guarantees 1855 * we'll always announce the right product name. 1856 */ 1857 int 1858 bge_probe(parent, match, aux) 1859 struct device *parent; 1860 struct cfdata *match; 1861 void *aux; 1862 { 1863 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1864 1865 if (bge_lookup(pa) != NULL) 1866 return (1); 1867 1868 return (0); 1869 } 1870 1871 void 1872 bge_attach(parent, self, aux) 1873 struct device *parent, *self; 1874 void *aux; 1875 { 1876 struct bge_softc *sc = (struct bge_softc *)self; 1877 struct pci_attach_args *pa = aux; 1878 const struct bge_product *bp; 1879 const struct bge_revision *br; 1880 pci_chipset_tag_t pc = pa->pa_pc; 1881 pci_intr_handle_t ih; 1882 const char *intrstr = NULL; 1883 bus_dma_segment_t seg; 1884 int rseg; 1885 u_int32_t hwcfg = 0; 1886 u_int32_t mac_addr = 0; 1887 u_int32_t command; 1888 struct ifnet *ifp; 1889 caddr_t kva; 1890 u_char eaddr[ETHER_ADDR_LEN]; 1891 pcireg_t memtype; 1892 bus_addr_t memaddr; 1893 bus_size_t memsize; 1894 u_int32_t pm_ctl; 1895 1896 bp = bge_lookup(pa); 1897 KASSERT(bp != NULL); 1898 1899 sc->bge_pa = *pa; 1900 1901 aprint_naive(": Ethernet controller\n"); 1902 aprint_normal(": %s\n", bp->bp_name); 1903 1904 /* 1905 * Map control/status registers. 1906 */ 1907 DPRINTFN(5, ("Map control/status regs\n")); 1908 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1909 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1910 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1911 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1912 1913 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1914 aprint_error("%s: failed to enable memory mapping!\n", 1915 sc->bge_dev.dv_xname); 1916 return; 1917 } 1918 1919 DPRINTFN(5, ("pci_mem_find\n")); 1920 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1921 switch (memtype) { 1922 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1923 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1924 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1925 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1926 &memaddr, &memsize) == 0) 1927 break; 1928 default: 1929 aprint_error("%s: can't find mem space\n", 1930 sc->bge_dev.dv_xname); 1931 return; 1932 } 1933 1934 DPRINTFN(5, ("pci_intr_map\n")); 1935 if (pci_intr_map(pa, &ih)) { 1936 aprint_error("%s: couldn't map interrupt\n", 1937 sc->bge_dev.dv_xname); 1938 return; 1939 } 1940 1941 DPRINTFN(5, ("pci_intr_string\n")); 1942 intrstr = pci_intr_string(pc, ih); 1943 1944 DPRINTFN(5, ("pci_intr_establish\n")); 1945 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 1946 1947 if (sc->bge_intrhand == NULL) { 1948 aprint_error("%s: couldn't establish interrupt", 1949 sc->bge_dev.dv_xname); 1950 if (intrstr != NULL) 1951 aprint_normal(" at %s", intrstr); 1952 aprint_normal("\n"); 1953 return; 1954 } 1955 aprint_normal("%s: interrupting at %s\n", 1956 sc->bge_dev.dv_xname, intrstr); 1957 1958 /* 1959 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 1960 * can clobber the chip's PCI config-space power control registers, 1961 * leaving the card in D3 powersave state. 1962 * We do not have memory-mapped registers in this state, 1963 * so force device into D0 state before starting initialization. 1964 */ 1965 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 1966 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 1967 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 1968 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 1969 DELAY(1000); /* 27 usec is allegedly sufficent */ 1970 1971 /* Try to reset the chip. */ 1972 DPRINTFN(5, ("bge_reset\n")); 1973 bge_reset(sc); 1974 1975 if (bge_chipinit(sc)) { 1976 aprint_error("%s: chip initialization failed\n", 1977 sc->bge_dev.dv_xname); 1978 bge_release_resources(sc); 1979 return; 1980 } 1981 1982 /* 1983 * Get station address from the EEPROM. 1984 */ 1985 mac_addr = bge_readmem_ind(sc, 0x0c14); 1986 if ((mac_addr >> 16) == 0x484b) { 1987 eaddr[0] = (u_char)(mac_addr >> 8); 1988 eaddr[1] = (u_char)(mac_addr >> 0); 1989 mac_addr = bge_readmem_ind(sc, 0x0c18); 1990 eaddr[2] = (u_char)(mac_addr >> 24); 1991 eaddr[3] = (u_char)(mac_addr >> 16); 1992 eaddr[4] = (u_char)(mac_addr >> 8); 1993 eaddr[5] = (u_char)(mac_addr >> 0); 1994 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 1995 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1996 aprint_error("%s: failed to read station address\n", 1997 sc->bge_dev.dv_xname); 1998 bge_release_resources(sc); 1999 return; 2000 } 2001 2002 /* 2003 * Save ASIC rev. Look up any quirks associated with this 2004 * ASIC. 2005 */ 2006 sc->bge_asicrev = 2007 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2008 BGE_PCIMISCCTL_ASICREV; 2009 br = bge_lookup_rev(sc->bge_asicrev); 2010 2011 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2012 if (br == NULL) { 2013 aprint_normal("unknown ASIC 0x%08x", sc->bge_asicrev); 2014 sc->bge_quirks = 0; 2015 } else { 2016 aprint_normal("ASIC %s", br->br_name); 2017 sc->bge_quirks = br->br_quirks; 2018 } 2019 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2020 2021 /* Allocate the general information block and ring buffers. */ 2022 if (pci_dma64_available(pa)) 2023 sc->bge_dmatag = pa->pa_dmat64; 2024 else 2025 sc->bge_dmatag = pa->pa_dmat; 2026 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2027 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2028 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2029 aprint_error("%s: can't alloc rx buffers\n", 2030 sc->bge_dev.dv_xname); 2031 return; 2032 } 2033 DPRINTFN(5, ("bus_dmamem_map\n")); 2034 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2035 sizeof(struct bge_ring_data), &kva, 2036 BUS_DMA_NOWAIT)) { 2037 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2038 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2039 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2040 return; 2041 } 2042 DPRINTFN(5, ("bus_dmamem_create\n")); 2043 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2044 sizeof(struct bge_ring_data), 0, 2045 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2046 aprint_error("%s: can't create DMA map\n", 2047 sc->bge_dev.dv_xname); 2048 bus_dmamem_unmap(sc->bge_dmatag, kva, 2049 sizeof(struct bge_ring_data)); 2050 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2051 return; 2052 } 2053 DPRINTFN(5, ("bus_dmamem_load\n")); 2054 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2055 sizeof(struct bge_ring_data), NULL, 2056 BUS_DMA_NOWAIT)) { 2057 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2058 bus_dmamem_unmap(sc->bge_dmatag, kva, 2059 sizeof(struct bge_ring_data)); 2060 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2061 return; 2062 } 2063 2064 DPRINTFN(5, ("bzero\n")); 2065 sc->bge_rdata = (struct bge_ring_data *)kva; 2066 2067 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2068 2069 /* Try to allocate memory for jumbo buffers. */ 2070 if (bge_alloc_jumbo_mem(sc)) { 2071 aprint_error("%s: jumbo buffer allocation failed\n", 2072 sc->bge_dev.dv_xname); 2073 } else 2074 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2075 2076 /* Set default tuneable values. */ 2077 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2078 sc->bge_rx_coal_ticks = 150; 2079 sc->bge_rx_max_coal_bds = 64; 2080 #ifdef ORIG_WPAUL_VALUES 2081 sc->bge_tx_coal_ticks = 150; 2082 sc->bge_tx_max_coal_bds = 128; 2083 #else 2084 sc->bge_tx_coal_ticks = 300; 2085 sc->bge_tx_max_coal_bds = 400; 2086 #endif 2087 2088 /* Set up ifnet structure */ 2089 ifp = &sc->ethercom.ec_if; 2090 ifp->if_softc = sc; 2091 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2092 ifp->if_ioctl = bge_ioctl; 2093 ifp->if_start = bge_start; 2094 ifp->if_init = bge_init; 2095 ifp->if_watchdog = bge_watchdog; 2096 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2097 IFQ_SET_READY(&ifp->if_snd); 2098 DPRINTFN(5, ("bcopy\n")); 2099 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2100 2101 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2102 sc->ethercom.ec_if.if_capabilities |= 2103 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 2104 sc->ethercom.ec_capabilities |= 2105 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2106 2107 /* 2108 * Do MII setup. 2109 */ 2110 DPRINTFN(5, ("mii setup\n")); 2111 sc->bge_mii.mii_ifp = ifp; 2112 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2113 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2114 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2115 2116 /* 2117 * Figure out what sort of media we have by checking the 2118 * hardware config word in the first 32k of NIC internal memory, 2119 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2120 * cards, this value appears to be unset. If that's the 2121 * case, we have to rely on identifying the NIC by its PCI 2122 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2123 */ 2124 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2125 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2126 } else { 2127 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2128 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2129 hwcfg = be32toh(hwcfg); 2130 } 2131 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2132 sc->bge_tbi = 1; 2133 2134 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2135 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2136 SK_SUBSYSID_9D41) 2137 sc->bge_tbi = 1; 2138 2139 if (sc->bge_tbi) { 2140 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2141 bge_ifmedia_sts); 2142 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2143 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2144 0, NULL); 2145 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2146 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2147 } else { 2148 /* 2149 * Do transceiver setup. 2150 */ 2151 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2152 bge_ifmedia_sts); 2153 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2154 MII_PHY_ANY, MII_OFFSET_ANY, 0); 2155 2156 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2157 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2158 ifmedia_add(&sc->bge_mii.mii_media, 2159 IFM_ETHER|IFM_MANUAL, 0, NULL); 2160 ifmedia_set(&sc->bge_mii.mii_media, 2161 IFM_ETHER|IFM_MANUAL); 2162 } else 2163 ifmedia_set(&sc->bge_mii.mii_media, 2164 IFM_ETHER|IFM_AUTO); 2165 } 2166 2167 /* 2168 * When using the BCM5701 in PCI-X mode, data corruption has 2169 * been observed in the first few bytes of some received packets. 2170 * Aligning the packet buffer in memory eliminates the corruption. 2171 * Unfortunately, this misaligns the packet payloads. On platforms 2172 * which do not support unaligned accesses, we will realign the 2173 * payloads by copying the received packets. 2174 */ 2175 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2176 /* If in PCI-X mode, work around the alignment bug. */ 2177 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2178 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2179 BGE_PCISTATE_PCI_BUSSPEED) 2180 sc->bge_rx_alignment_bug = 1; 2181 } 2182 2183 /* 2184 * Call MI attach routine. 2185 */ 2186 DPRINTFN(5, ("if_attach\n")); 2187 if_attach(ifp); 2188 DPRINTFN(5, ("ether_ifattach\n")); 2189 ether_ifattach(ifp, eaddr); 2190 DPRINTFN(5, ("callout_init\n")); 2191 callout_init(&sc->bge_timeout); 2192 } 2193 2194 void 2195 bge_release_resources(sc) 2196 struct bge_softc *sc; 2197 { 2198 if (sc->bge_vpd_prodname != NULL) 2199 free(sc->bge_vpd_prodname, M_DEVBUF); 2200 2201 if (sc->bge_vpd_readonly != NULL) 2202 free(sc->bge_vpd_readonly, M_DEVBUF); 2203 } 2204 2205 void 2206 bge_reset(sc) 2207 struct bge_softc *sc; 2208 { 2209 struct pci_attach_args *pa = &sc->bge_pa; 2210 u_int32_t cachesize, command, pcistate; 2211 int i, val = 0; 2212 2213 /* Save some important PCI state. */ 2214 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2215 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2216 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2217 2218 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2219 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2220 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2221 2222 /* Issue global reset */ 2223 bge_writereg_ind(sc, BGE_MISC_CFG, 2224 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2225 2226 DELAY(1000); 2227 2228 /* Reset some of the PCI state that got zapped by reset */ 2229 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2230 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2231 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2232 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2233 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2234 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2235 2236 /* Enable memory arbiter. */ 2237 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2238 2239 /* 2240 * Prevent PXE restart: write a magic number to the 2241 * general communications memory at 0xB50. 2242 */ 2243 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2244 2245 /* 2246 * Poll the value location we just wrote until 2247 * we see the 1's complement of the magic number. 2248 * This indicates that the firmware initialization 2249 * is complete. 2250 */ 2251 for (i = 0; i < 750; i++) { 2252 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2253 if (val == ~BGE_MAGIC_NUMBER) 2254 break; 2255 DELAY(1000); 2256 } 2257 2258 if (i == 750) { 2259 printf("%s: firmware handshake timed out, val = %x\n", 2260 sc->bge_dev.dv_xname, val); 2261 return; 2262 } 2263 2264 /* 2265 * XXX Wait for the value of the PCISTATE register to 2266 * return to its original pre-reset state. This is a 2267 * fairly good indicator of reset completion. If we don't 2268 * wait for the reset to fully complete, trying to read 2269 * from the device's non-PCI registers may yield garbage 2270 * results. 2271 */ 2272 for (i = 0; i < BGE_TIMEOUT; i++) { 2273 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2274 pcistate) 2275 break; 2276 DELAY(10); 2277 } 2278 2279 /* Enable memory arbiter. */ 2280 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2281 2282 /* Fix up byte swapping */ 2283 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2284 2285 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2286 2287 DELAY(10000); 2288 } 2289 2290 /* 2291 * Frame reception handling. This is called if there's a frame 2292 * on the receive return list. 2293 * 2294 * Note: we have to be able to handle two possibilities here: 2295 * 1) the frame is from the jumbo recieve ring 2296 * 2) the frame is from the standard receive ring 2297 */ 2298 2299 void 2300 bge_rxeof(sc) 2301 struct bge_softc *sc; 2302 { 2303 struct ifnet *ifp; 2304 int stdcnt = 0, jumbocnt = 0; 2305 int have_tag = 0; 2306 u_int16_t vlan_tag = 0; 2307 bus_dmamap_t dmamap; 2308 bus_addr_t offset, toff; 2309 bus_size_t tlen; 2310 int tosync; 2311 2312 ifp = &sc->ethercom.ec_if; 2313 2314 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2315 offsetof(struct bge_ring_data, bge_status_block), 2316 sizeof (struct bge_status_block), 2317 BUS_DMASYNC_POSTREAD); 2318 2319 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2320 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2321 sc->bge_rx_saved_considx; 2322 2323 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2324 2325 if (tosync < 0) { 2326 tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) * 2327 sizeof (struct bge_rx_bd); 2328 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2329 toff, tlen, BUS_DMASYNC_POSTREAD); 2330 tosync = -tosync; 2331 } 2332 2333 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2334 offset, tosync * sizeof (struct bge_rx_bd), 2335 BUS_DMASYNC_POSTREAD); 2336 2337 while(sc->bge_rx_saved_considx != 2338 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2339 struct bge_rx_bd *cur_rx; 2340 u_int32_t rxidx; 2341 struct mbuf *m = NULL; 2342 2343 cur_rx = &sc->bge_rdata-> 2344 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2345 2346 rxidx = cur_rx->bge_idx; 2347 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 2348 2349 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2350 have_tag = 1; 2351 vlan_tag = cur_rx->bge_vlan_tag; 2352 } 2353 2354 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2355 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2356 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2357 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2358 jumbocnt++; 2359 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2360 ifp->if_ierrors++; 2361 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2362 continue; 2363 } 2364 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2365 NULL)== ENOBUFS) { 2366 ifp->if_ierrors++; 2367 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2368 continue; 2369 } 2370 } else { 2371 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2372 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2373 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2374 stdcnt++; 2375 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2376 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2377 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2378 ifp->if_ierrors++; 2379 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2380 continue; 2381 } 2382 if (bge_newbuf_std(sc, sc->bge_std, 2383 NULL, dmamap) == ENOBUFS) { 2384 ifp->if_ierrors++; 2385 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2386 continue; 2387 } 2388 } 2389 2390 ifp->if_ipackets++; 2391 #ifndef __NO_STRICT_ALIGNMENT 2392 /* 2393 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2394 * the Rx buffer has the layer-2 header unaligned. 2395 * If our CPU requires alignment, re-align by copying. 2396 */ 2397 if (sc->bge_rx_alignment_bug) { 2398 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2399 cur_rx->bge_len); 2400 m->m_data += ETHER_ALIGN; 2401 } 2402 #endif 2403 2404 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2405 m->m_pkthdr.rcvif = ifp; 2406 2407 #if NBPFILTER > 0 2408 /* 2409 * Handle BPF listeners. Let the BPF user see the packet. 2410 */ 2411 if (ifp->if_bpf) 2412 bpf_mtap(ifp->if_bpf, m); 2413 #endif 2414 2415 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) { 2416 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2417 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2418 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2419 #if 0 /* XXX appears to be broken */ 2420 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2421 m->m_pkthdr.csum_data = 2422 cur_rx->bge_tcp_udp_csum; 2423 m->m_pkthdr.csum_flags |= 2424 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA); 2425 } 2426 #endif 2427 } 2428 2429 /* 2430 * If we received a packet with a vlan tag, pass it 2431 * to vlan_input() instead of ether_input(). 2432 */ 2433 if (have_tag) { 2434 struct m_tag *mtag; 2435 2436 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2437 M_NOWAIT); 2438 if (mtag != NULL) { 2439 *(u_int *)(mtag + 1) = vlan_tag; 2440 m_tag_prepend(m, mtag); 2441 have_tag = vlan_tag = 0; 2442 } else { 2443 printf("%s: no mbuf for tag\n", ifp->if_xname); 2444 m_freem(m); 2445 have_tag = vlan_tag = 0; 2446 continue; 2447 } 2448 } 2449 (*ifp->if_input)(ifp, m); 2450 } 2451 2452 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2453 if (stdcnt) 2454 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2455 if (jumbocnt) 2456 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2457 } 2458 2459 void 2460 bge_txeof(sc) 2461 struct bge_softc *sc; 2462 { 2463 struct bge_tx_bd *cur_tx = NULL; 2464 struct ifnet *ifp; 2465 struct txdmamap_pool_entry *dma; 2466 bus_addr_t offset, toff; 2467 bus_size_t tlen; 2468 int tosync; 2469 struct mbuf *m; 2470 2471 ifp = &sc->ethercom.ec_if; 2472 2473 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2474 offsetof(struct bge_ring_data, bge_status_block), 2475 sizeof (struct bge_status_block), 2476 BUS_DMASYNC_POSTREAD); 2477 2478 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2479 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2480 sc->bge_tx_saved_considx; 2481 2482 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2483 2484 if (tosync < 0) { 2485 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2486 sizeof (struct bge_tx_bd); 2487 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2488 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2489 tosync = -tosync; 2490 } 2491 2492 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2493 offset, tosync * sizeof (struct bge_tx_bd), 2494 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2495 2496 /* 2497 * Go through our tx ring and free mbufs for those 2498 * frames that have been sent. 2499 */ 2500 while (sc->bge_tx_saved_considx != 2501 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2502 u_int32_t idx = 0; 2503 2504 idx = sc->bge_tx_saved_considx; 2505 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2506 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2507 ifp->if_opackets++; 2508 m = sc->bge_cdata.bge_tx_chain[idx]; 2509 if (m != NULL) { 2510 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2511 dma = sc->txdma[idx]; 2512 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2513 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2514 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2515 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2516 sc->txdma[idx] = NULL; 2517 2518 m_freem(m); 2519 } 2520 sc->bge_txcnt--; 2521 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2522 ifp->if_timer = 0; 2523 } 2524 2525 if (cur_tx != NULL) 2526 ifp->if_flags &= ~IFF_OACTIVE; 2527 } 2528 2529 int 2530 bge_intr(xsc) 2531 void *xsc; 2532 { 2533 struct bge_softc *sc; 2534 struct ifnet *ifp; 2535 2536 sc = xsc; 2537 ifp = &sc->ethercom.ec_if; 2538 2539 #ifdef notdef 2540 /* Avoid this for now -- checking this register is expensive. */ 2541 /* Make sure this is really our interrupt. */ 2542 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2543 return (0); 2544 #endif 2545 /* Ack interrupt and stop others from occuring. */ 2546 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2547 2548 /* 2549 * Process link state changes. 2550 * Grrr. The link status word in the status block does 2551 * not work correctly on the BCM5700 rev AX and BX chips, 2552 * according to all avaibable information. Hence, we have 2553 * to enable MII interrupts in order to properly obtain 2554 * async link changes. Unfortunately, this also means that 2555 * we have to read the MAC status register to detect link 2556 * changes, thereby adding an additional register access to 2557 * the interrupt handler. 2558 */ 2559 2560 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2561 u_int32_t status; 2562 2563 status = CSR_READ_4(sc, BGE_MAC_STS); 2564 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2565 sc->bge_link = 0; 2566 callout_stop(&sc->bge_timeout); 2567 bge_tick(sc); 2568 /* Clear the interrupt */ 2569 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2570 BGE_EVTENB_MI_INTERRUPT); 2571 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2572 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2573 BRGPHY_INTRS); 2574 } 2575 } else { 2576 if (sc->bge_rdata->bge_status_block.bge_status & 2577 BGE_STATFLAG_LINKSTATE_CHANGED) { 2578 sc->bge_link = 0; 2579 callout_stop(&sc->bge_timeout); 2580 bge_tick(sc); 2581 /* Clear the interrupt */ 2582 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2583 BGE_MACSTAT_CFG_CHANGED); 2584 } 2585 } 2586 2587 if (ifp->if_flags & IFF_RUNNING) { 2588 /* Check RX return ring producer/consumer */ 2589 bge_rxeof(sc); 2590 2591 /* Check TX ring producer/consumer */ 2592 bge_txeof(sc); 2593 } 2594 2595 bge_handle_events(sc); 2596 2597 /* Re-enable interrupts. */ 2598 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2599 2600 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2601 bge_start(ifp); 2602 2603 return (1); 2604 } 2605 2606 void 2607 bge_tick(xsc) 2608 void *xsc; 2609 { 2610 struct bge_softc *sc = xsc; 2611 struct mii_data *mii = &sc->bge_mii; 2612 struct ifmedia *ifm = NULL; 2613 struct ifnet *ifp = &sc->ethercom.ec_if; 2614 int s; 2615 2616 s = splnet(); 2617 2618 bge_stats_update(sc); 2619 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2620 if (sc->bge_link) { 2621 splx(s); 2622 return; 2623 } 2624 2625 if (sc->bge_tbi) { 2626 ifm = &sc->bge_ifmedia; 2627 if (CSR_READ_4(sc, BGE_MAC_STS) & 2628 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2629 sc->bge_link++; 2630 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2631 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2632 bge_start(ifp); 2633 } 2634 splx(s); 2635 return; 2636 } 2637 2638 mii_tick(mii); 2639 2640 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2641 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2642 sc->bge_link++; 2643 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2644 bge_start(ifp); 2645 } 2646 2647 splx(s); 2648 } 2649 2650 void 2651 bge_stats_update(sc) 2652 struct bge_softc *sc; 2653 { 2654 struct ifnet *ifp = &sc->ethercom.ec_if; 2655 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2656 2657 #define READ_STAT(sc, stats, stat) \ 2658 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2659 2660 ifp->if_collisions += 2661 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2662 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2663 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2664 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2665 ifp->if_collisions; 2666 2667 #undef READ_STAT 2668 2669 #ifdef notdef 2670 ifp->if_collisions += 2671 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2672 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2673 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2674 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2675 ifp->if_collisions; 2676 #endif 2677 } 2678 2679 /* 2680 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2681 * pointers to descriptors. 2682 */ 2683 int 2684 bge_encap(sc, m_head, txidx) 2685 struct bge_softc *sc; 2686 struct mbuf *m_head; 2687 u_int32_t *txidx; 2688 { 2689 struct bge_tx_bd *f = NULL; 2690 u_int32_t frag, cur, cnt = 0; 2691 u_int16_t csum_flags = 0; 2692 struct txdmamap_pool_entry *dma; 2693 bus_dmamap_t dmamap; 2694 int i = 0; 2695 struct m_tag *mtag; 2696 struct mbuf *prev, *m; 2697 int totlen, prevlen; 2698 2699 cur = frag = *txidx; 2700 2701 if (m_head->m_pkthdr.csum_flags) { 2702 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2703 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2704 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2705 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2706 } 2707 2708 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 2709 goto doit; 2710 /* 2711 * bcm5700 Revision B silicon cannot handle DMA descriptors with 2712 * less than eight bytes. If we encounter a teeny mbuf 2713 * at the end of a chain, we can pad. Otherwise, copy. 2714 */ 2715 prev = NULL; 2716 totlen = 0; 2717 for (m = m_head; m != NULL; prev = m,m = m->m_next) { 2718 int mlen = m->m_len; 2719 2720 totlen += mlen; 2721 if (mlen == 0) { 2722 /* print a warning? */ 2723 continue; 2724 } 2725 if (mlen >= 8) 2726 continue; 2727 2728 /* If we get here, mbuf data is too small for DMA engine. */ 2729 if (m->m_next != 0) { 2730 /* Internal frag. If fits in prev, copy it there. */ 2731 if (prev && M_TRAILINGSPACE(prev) >= m->m_len && 2732 !M_READONLY(prev)) { 2733 bcopy(m->m_data, 2734 prev->m_data+prev->m_len, 2735 mlen); 2736 prev->m_len += mlen; 2737 m->m_len = 0; 2738 MFREE(m, prev->m_next); /* XXX stitch chain */ 2739 m = prev; 2740 continue; 2741 } else { 2742 struct mbuf *n; 2743 /* slow copy */ 2744 slowcopy: 2745 n = m_dup(m_head, 0, M_COPYALL, M_DONTWAIT); 2746 m_freem(m_head); 2747 if (n == 0) 2748 return 0; 2749 m_head = n; 2750 goto doit; 2751 } 2752 } else if ((totlen -mlen +8) >= 1500) { 2753 goto slowcopy; 2754 } 2755 prevlen = m->m_len; 2756 } 2757 2758 doit: 2759 dma = SLIST_FIRST(&sc->txdma_list); 2760 if (dma == NULL) 2761 return ENOBUFS; 2762 dmamap = dma->dmamap; 2763 2764 /* 2765 * Start packing the mbufs in this chain into 2766 * the fragment pointers. Stop when we run out 2767 * of fragments or hit the end of the mbuf chain. 2768 */ 2769 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 2770 BUS_DMA_NOWAIT)) 2771 return(ENOBUFS); 2772 2773 mtag = sc->ethercom.ec_nvlans ? 2774 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 2775 2776 for (i = 0; i < dmamap->dm_nsegs; i++) { 2777 f = &sc->bge_rdata->bge_tx_ring[frag]; 2778 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2779 break; 2780 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 2781 f->bge_len = dmamap->dm_segs[i].ds_len; 2782 f->bge_flags = csum_flags; 2783 2784 if (mtag != NULL) { 2785 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2786 f->bge_vlan_tag = *(u_int *)(mtag + 1); 2787 } else { 2788 f->bge_vlan_tag = 0; 2789 } 2790 /* 2791 * Sanity check: avoid coming within 16 descriptors 2792 * of the end of the ring. 2793 */ 2794 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2795 return(ENOBUFS); 2796 cur = frag; 2797 BGE_INC(frag, BGE_TX_RING_CNT); 2798 cnt++; 2799 } 2800 2801 if (i < dmamap->dm_nsegs) 2802 return ENOBUFS; 2803 2804 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 2805 BUS_DMASYNC_PREWRITE); 2806 2807 if (frag == sc->bge_tx_saved_considx) 2808 return(ENOBUFS); 2809 2810 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2811 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2812 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 2813 sc->txdma[cur] = dma; 2814 sc->bge_txcnt += cnt; 2815 2816 *txidx = frag; 2817 2818 return(0); 2819 } 2820 2821 /* 2822 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2823 * to the mbuf data regions directly in the transmit descriptors. 2824 */ 2825 void 2826 bge_start(ifp) 2827 struct ifnet *ifp; 2828 { 2829 struct bge_softc *sc; 2830 struct mbuf *m_head = NULL; 2831 u_int32_t prodidx = 0; 2832 int pkts = 0; 2833 2834 sc = ifp->if_softc; 2835 2836 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2837 return; 2838 2839 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2840 2841 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2842 IFQ_POLL(&ifp->if_snd, m_head); 2843 if (m_head == NULL) 2844 break; 2845 2846 #if 0 2847 /* 2848 * XXX 2849 * safety overkill. If this is a fragmented packet chain 2850 * with delayed TCP/UDP checksums, then only encapsulate 2851 * it if we have enough descriptors to handle the entire 2852 * chain at once. 2853 * (paranoia -- may not actually be needed) 2854 */ 2855 if (m_head->m_flags & M_FIRSTFRAG && 2856 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2857 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2858 m_head->m_pkthdr.csum_data + 16) { 2859 ifp->if_flags |= IFF_OACTIVE; 2860 break; 2861 } 2862 } 2863 #endif 2864 2865 /* 2866 * Pack the data into the transmit ring. If we 2867 * don't have room, set the OACTIVE flag and wait 2868 * for the NIC to drain the ring. 2869 */ 2870 if (bge_encap(sc, m_head, &prodidx)) { 2871 ifp->if_flags |= IFF_OACTIVE; 2872 break; 2873 } 2874 2875 /* now we are committed to transmit the packet */ 2876 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2877 pkts++; 2878 2879 #if NBPFILTER > 0 2880 /* 2881 * If there's a BPF listener, bounce a copy of this frame 2882 * to him. 2883 */ 2884 if (ifp->if_bpf) 2885 bpf_mtap(ifp->if_bpf, m_head); 2886 #endif 2887 } 2888 if (pkts == 0) 2889 return; 2890 2891 /* Transmit */ 2892 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2893 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 2894 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2895 2896 /* 2897 * Set a timeout in case the chip goes out to lunch. 2898 */ 2899 ifp->if_timer = 5; 2900 } 2901 2902 int 2903 bge_init(ifp) 2904 struct ifnet *ifp; 2905 { 2906 struct bge_softc *sc = ifp->if_softc; 2907 u_int16_t *m; 2908 int s, error; 2909 2910 s = splnet(); 2911 2912 ifp = &sc->ethercom.ec_if; 2913 2914 /* Cancel pending I/O and flush buffers. */ 2915 bge_stop(sc); 2916 bge_reset(sc); 2917 bge_chipinit(sc); 2918 2919 /* 2920 * Init the various state machines, ring 2921 * control blocks and firmware. 2922 */ 2923 error = bge_blockinit(sc); 2924 if (error != 0) { 2925 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 2926 error); 2927 splx(s); 2928 return error; 2929 } 2930 2931 ifp = &sc->ethercom.ec_if; 2932 2933 /* Specify MTU. */ 2934 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2935 ETHER_HDR_LEN + ETHER_CRC_LEN); 2936 2937 /* Load our MAC address. */ 2938 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 2939 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2940 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2941 2942 /* Enable or disable promiscuous mode as needed. */ 2943 if (ifp->if_flags & IFF_PROMISC) { 2944 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2945 } else { 2946 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2947 } 2948 2949 /* Program multicast filter. */ 2950 bge_setmulti(sc); 2951 2952 /* Init RX ring. */ 2953 bge_init_rx_ring_std(sc); 2954 2955 /* Init jumbo RX ring. */ 2956 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2957 bge_init_rx_ring_jumbo(sc); 2958 2959 /* Init our RX return ring index */ 2960 sc->bge_rx_saved_considx = 0; 2961 2962 /* Init TX ring. */ 2963 bge_init_tx_ring(sc); 2964 2965 /* Turn on transmitter */ 2966 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2967 2968 /* Turn on receiver */ 2969 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2970 2971 /* Tell firmware we're alive. */ 2972 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2973 2974 /* Enable host interrupts. */ 2975 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2976 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2977 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2978 2979 bge_ifmedia_upd(ifp); 2980 2981 ifp->if_flags |= IFF_RUNNING; 2982 ifp->if_flags &= ~IFF_OACTIVE; 2983 2984 splx(s); 2985 2986 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2987 2988 return 0; 2989 } 2990 2991 /* 2992 * Set media options. 2993 */ 2994 int 2995 bge_ifmedia_upd(ifp) 2996 struct ifnet *ifp; 2997 { 2998 struct bge_softc *sc = ifp->if_softc; 2999 struct mii_data *mii = &sc->bge_mii; 3000 struct ifmedia *ifm = &sc->bge_ifmedia; 3001 3002 /* If this is a 1000baseX NIC, enable the TBI port. */ 3003 if (sc->bge_tbi) { 3004 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3005 return(EINVAL); 3006 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3007 case IFM_AUTO: 3008 break; 3009 case IFM_1000_SX: 3010 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3011 BGE_CLRBIT(sc, BGE_MAC_MODE, 3012 BGE_MACMODE_HALF_DUPLEX); 3013 } else { 3014 BGE_SETBIT(sc, BGE_MAC_MODE, 3015 BGE_MACMODE_HALF_DUPLEX); 3016 } 3017 break; 3018 default: 3019 return(EINVAL); 3020 } 3021 return(0); 3022 } 3023 3024 sc->bge_link = 0; 3025 mii_mediachg(mii); 3026 3027 return(0); 3028 } 3029 3030 /* 3031 * Report current media status. 3032 */ 3033 void 3034 bge_ifmedia_sts(ifp, ifmr) 3035 struct ifnet *ifp; 3036 struct ifmediareq *ifmr; 3037 { 3038 struct bge_softc *sc = ifp->if_softc; 3039 struct mii_data *mii = &sc->bge_mii; 3040 3041 if (sc->bge_tbi) { 3042 ifmr->ifm_status = IFM_AVALID; 3043 ifmr->ifm_active = IFM_ETHER; 3044 if (CSR_READ_4(sc, BGE_MAC_STS) & 3045 BGE_MACSTAT_TBI_PCS_SYNCHED) 3046 ifmr->ifm_status |= IFM_ACTIVE; 3047 ifmr->ifm_active |= IFM_1000_SX; 3048 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3049 ifmr->ifm_active |= IFM_HDX; 3050 else 3051 ifmr->ifm_active |= IFM_FDX; 3052 return; 3053 } 3054 3055 mii_pollstat(mii); 3056 ifmr->ifm_active = mii->mii_media_active; 3057 ifmr->ifm_status = mii->mii_media_status; 3058 } 3059 3060 int 3061 bge_ioctl(ifp, command, data) 3062 struct ifnet *ifp; 3063 u_long command; 3064 caddr_t data; 3065 { 3066 struct bge_softc *sc = ifp->if_softc; 3067 struct ifreq *ifr = (struct ifreq *) data; 3068 int s, error = 0; 3069 struct mii_data *mii; 3070 3071 s = splnet(); 3072 3073 switch(command) { 3074 case SIOCSIFFLAGS: 3075 if (ifp->if_flags & IFF_UP) { 3076 /* 3077 * If only the state of the PROMISC flag changed, 3078 * then just use the 'set promisc mode' command 3079 * instead of reinitializing the entire NIC. Doing 3080 * a full re-init means reloading the firmware and 3081 * waiting for it to start up, which may take a 3082 * second or two. 3083 */ 3084 if (ifp->if_flags & IFF_RUNNING && 3085 ifp->if_flags & IFF_PROMISC && 3086 !(sc->bge_if_flags & IFF_PROMISC)) { 3087 BGE_SETBIT(sc, BGE_RX_MODE, 3088 BGE_RXMODE_RX_PROMISC); 3089 } else if (ifp->if_flags & IFF_RUNNING && 3090 !(ifp->if_flags & IFF_PROMISC) && 3091 sc->bge_if_flags & IFF_PROMISC) { 3092 BGE_CLRBIT(sc, BGE_RX_MODE, 3093 BGE_RXMODE_RX_PROMISC); 3094 } else 3095 bge_init(ifp); 3096 } else { 3097 if (ifp->if_flags & IFF_RUNNING) { 3098 bge_stop(sc); 3099 } 3100 } 3101 sc->bge_if_flags = ifp->if_flags; 3102 error = 0; 3103 break; 3104 case SIOCSIFMEDIA: 3105 case SIOCGIFMEDIA: 3106 if (sc->bge_tbi) { 3107 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3108 command); 3109 } else { 3110 mii = &sc->bge_mii; 3111 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3112 command); 3113 } 3114 error = 0; 3115 break; 3116 default: 3117 error = ether_ioctl(ifp, command, data); 3118 if (error == ENETRESET) { 3119 bge_setmulti(sc); 3120 error = 0; 3121 } 3122 break; 3123 } 3124 3125 splx(s); 3126 3127 return(error); 3128 } 3129 3130 void 3131 bge_watchdog(ifp) 3132 struct ifnet *ifp; 3133 { 3134 struct bge_softc *sc; 3135 3136 sc = ifp->if_softc; 3137 3138 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3139 3140 ifp->if_flags &= ~IFF_RUNNING; 3141 bge_init(ifp); 3142 3143 ifp->if_oerrors++; 3144 } 3145 3146 static void 3147 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3148 { 3149 int i; 3150 3151 BGE_CLRBIT(sc, reg, bit); 3152 3153 for (i = 0; i < BGE_TIMEOUT; i++) { 3154 if ((CSR_READ_4(sc, reg) & bit) == 0) 3155 return; 3156 delay(100); 3157 } 3158 3159 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3160 sc->bge_dev.dv_xname, (u_long) reg, bit); 3161 } 3162 3163 /* 3164 * Stop the adapter and free any mbufs allocated to the 3165 * RX and TX lists. 3166 */ 3167 void 3168 bge_stop(sc) 3169 struct bge_softc *sc; 3170 { 3171 struct ifnet *ifp = &sc->ethercom.ec_if; 3172 3173 callout_stop(&sc->bge_timeout); 3174 3175 /* 3176 * Disable all of the receiver blocks 3177 */ 3178 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3179 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3180 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3181 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3182 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3183 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3184 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3185 3186 /* 3187 * Disable all of the transmit blocks 3188 */ 3189 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3190 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3191 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3192 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3193 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3194 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3195 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3196 3197 /* 3198 * Shut down all of the memory managers and related 3199 * state machines. 3200 */ 3201 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3202 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3203 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3204 3205 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3206 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3207 3208 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3209 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3210 3211 /* Disable host interrupts. */ 3212 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3213 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3214 3215 /* 3216 * Tell firmware we're shutting down. 3217 */ 3218 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3219 3220 /* Free the RX lists. */ 3221 bge_free_rx_ring_std(sc); 3222 3223 /* Free jumbo RX list. */ 3224 bge_free_rx_ring_jumbo(sc); 3225 3226 /* Free TX buffers. */ 3227 bge_free_tx_ring(sc); 3228 3229 /* 3230 * Isolate/power down the PHY. 3231 */ 3232 if (!sc->bge_tbi) 3233 mii_down(&sc->bge_mii); 3234 3235 sc->bge_link = 0; 3236 3237 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3238 3239 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3240 } 3241 3242 /* 3243 * Stop all chip I/O so that the kernel's probe routines don't 3244 * get confused by errant DMAs when rebooting. 3245 */ 3246 void 3247 bge_shutdown(xsc) 3248 void *xsc; 3249 { 3250 struct bge_softc *sc = (struct bge_softc *)xsc; 3251 3252 bge_stop(sc); 3253 bge_reset(sc); 3254 } 3255
Indexes created Wed Sep 24 05:09:52 GMT 2025