if_bge.c revision 1.49
1 /* $NetBSD: if_bge.c,v 1.49 2003/08/27 23:13:50 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.49 2003/08/27 23:13:50 fvdl Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/miidevs.h> 120 #include <dev/mii/brgphyreg.h> 121 122 #include <dev/pci/if_bgereg.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 127 128 int bge_probe(struct device *, struct cfdata *, void *); 129 void bge_attach(struct device *, struct device *, void *); 130 void bge_release_resources(struct bge_softc *); 131 void bge_txeof(struct bge_softc *); 132 void bge_rxeof(struct bge_softc *); 133 134 void bge_tick(void *); 135 void bge_stats_update(struct bge_softc *); 136 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 137 static __inline int bge_cksum_pad(struct mbuf *pkt); 138 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 139 140 int bge_intr(void *); 141 void bge_start(struct ifnet *); 142 int bge_ioctl(struct ifnet *, u_long, caddr_t); 143 int bge_init(struct ifnet *); 144 void bge_stop(struct bge_softc *); 145 void bge_watchdog(struct ifnet *); 146 void bge_shutdown(void *); 147 int bge_ifmedia_upd(struct ifnet *); 148 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 149 150 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 151 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 152 153 void bge_setmulti(struct bge_softc *); 154 155 void bge_handle_events(struct bge_softc *); 156 int bge_alloc_jumbo_mem(struct bge_softc *); 157 void bge_free_jumbo_mem(struct bge_softc *); 158 void *bge_jalloc(struct bge_softc *); 159 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 160 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 161 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 162 int bge_init_rx_ring_std(struct bge_softc *); 163 void bge_free_rx_ring_std(struct bge_softc *); 164 int bge_init_rx_ring_jumbo(struct bge_softc *); 165 void bge_free_rx_ring_jumbo(struct bge_softc *); 166 void bge_free_tx_ring(struct bge_softc *); 167 int bge_init_tx_ring(struct bge_softc *); 168 169 int bge_chipinit(struct bge_softc *); 170 int bge_blockinit(struct bge_softc *); 171 int bge_setpowerstate(struct bge_softc *, int); 172 173 #ifdef notdef 174 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 175 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 176 void bge_vpd_read(struct bge_softc *); 177 #endif 178 179 u_int32_t bge_readmem_ind(struct bge_softc *, int); 180 void bge_writemem_ind(struct bge_softc *, int, int); 181 #ifdef notdef 182 u_int32_t bge_readreg_ind(struct bge_softc *, int); 183 #endif 184 void bge_writereg_ind(struct bge_softc *, int, int); 185 186 int bge_miibus_readreg(struct device *, int, int); 187 void bge_miibus_writereg(struct device *, int, int, int); 188 void bge_miibus_statchg(struct device *); 189 190 void bge_reset(struct bge_softc *); 191 192 void bge_dump_status(struct bge_softc *); 193 void bge_dump_rxbd(struct bge_rx_bd *); 194 195 #define BGE_DEBUG 196 #ifdef BGE_DEBUG 197 #define DPRINTF(x) if (bgedebug) printf x 198 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 199 int bgedebug = 0; 200 #else 201 #define DPRINTF(x) 202 #define DPRINTFN(n,x) 203 #endif 204 205 /* Various chip quirks. */ 206 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 207 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 208 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 209 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 210 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 211 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 212 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 213 #define BGE_QUIRK_5705_CORE 0x00000080 214 215 /* following bugs are common to bcm5700 rev B, all flavours */ 216 #define BGE_QUIRK_5700_COMMON \ 217 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 218 219 CFATTACH_DECL(bge, sizeof(struct bge_softc), 220 bge_probe, bge_attach, NULL, NULL); 221 222 u_int32_t 223 bge_readmem_ind(sc, off) 224 struct bge_softc *sc; 225 int off; 226 { 227 struct pci_attach_args *pa = &(sc->bge_pa); 228 pcireg_t val; 229 230 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 231 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 232 return val; 233 } 234 235 void 236 bge_writemem_ind(sc, off, val) 237 struct bge_softc *sc; 238 int off, val; 239 { 240 struct pci_attach_args *pa = &(sc->bge_pa); 241 242 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 243 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 244 } 245 246 #ifdef notdef 247 u_int32_t 248 bge_readreg_ind(sc, off) 249 struct bge_softc *sc; 250 int off; 251 { 252 struct pci_attach_args *pa = &(sc->bge_pa); 253 254 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 255 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 256 } 257 #endif 258 259 void 260 bge_writereg_ind(sc, off, val) 261 struct bge_softc *sc; 262 int off, val; 263 { 264 struct pci_attach_args *pa = &(sc->bge_pa); 265 266 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 267 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 268 } 269 270 #ifdef notdef 271 u_int8_t 272 bge_vpd_readbyte(sc, addr) 273 struct bge_softc *sc; 274 int addr; 275 { 276 int i; 277 u_int32_t val; 278 struct pci_attach_args *pa = &(sc->bge_pa); 279 280 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 281 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 282 DELAY(10); 283 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 284 BGE_VPD_FLAG) 285 break; 286 } 287 288 if (i == BGE_TIMEOUT) { 289 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 290 return(0); 291 } 292 293 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 294 295 return((val >> ((addr % 4) * 8)) & 0xFF); 296 } 297 298 void 299 bge_vpd_read_res(sc, res, addr) 300 struct bge_softc *sc; 301 struct vpd_res *res; 302 int addr; 303 { 304 int i; 305 u_int8_t *ptr; 306 307 ptr = (u_int8_t *)res; 308 for (i = 0; i < sizeof(struct vpd_res); i++) 309 ptr[i] = bge_vpd_readbyte(sc, i + addr); 310 } 311 312 void 313 bge_vpd_read(sc) 314 struct bge_softc *sc; 315 { 316 int pos = 0, i; 317 struct vpd_res res; 318 319 if (sc->bge_vpd_prodname != NULL) 320 free(sc->bge_vpd_prodname, M_DEVBUF); 321 if (sc->bge_vpd_readonly != NULL) 322 free(sc->bge_vpd_readonly, M_DEVBUF); 323 sc->bge_vpd_prodname = NULL; 324 sc->bge_vpd_readonly = NULL; 325 326 bge_vpd_read_res(sc, &res, pos); 327 328 if (res.vr_id != VPD_RES_ID) { 329 printf("%s: bad VPD resource id: expected %x got %x\n", 330 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 331 return; 332 } 333 334 pos += sizeof(res); 335 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 336 if (sc->bge_vpd_prodname == NULL) 337 panic("bge_vpd_read"); 338 for (i = 0; i < res.vr_len; i++) 339 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 340 sc->bge_vpd_prodname[i] = '\0'; 341 pos += i; 342 343 bge_vpd_read_res(sc, &res, pos); 344 345 if (res.vr_id != VPD_RES_READ) { 346 printf("%s: bad VPD resource id: expected %x got %x\n", 347 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 348 return; 349 } 350 351 pos += sizeof(res); 352 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 353 if (sc->bge_vpd_readonly == NULL) 354 panic("bge_vpd_read"); 355 for (i = 0; i < res.vr_len + 1; i++) 356 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 357 } 358 #endif 359 360 /* 361 * Read a byte of data stored in the EEPROM at address 'addr.' The 362 * BCM570x supports both the traditional bitbang interface and an 363 * auto access interface for reading the EEPROM. We use the auto 364 * access method. 365 */ 366 u_int8_t 367 bge_eeprom_getbyte(sc, addr, dest) 368 struct bge_softc *sc; 369 int addr; 370 u_int8_t *dest; 371 { 372 int i; 373 u_int32_t byte = 0; 374 375 /* 376 * Enable use of auto EEPROM access so we can avoid 377 * having to use the bitbang method. 378 */ 379 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 380 381 /* Reset the EEPROM, load the clock period. */ 382 CSR_WRITE_4(sc, BGE_EE_ADDR, 383 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 384 DELAY(20); 385 386 /* Issue the read EEPROM command. */ 387 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 388 389 /* Wait for completion */ 390 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 391 DELAY(10); 392 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 393 break; 394 } 395 396 if (i == BGE_TIMEOUT) { 397 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 398 return(0); 399 } 400 401 /* Get result. */ 402 byte = CSR_READ_4(sc, BGE_EE_DATA); 403 404 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 405 406 return(0); 407 } 408 409 /* 410 * Read a sequence of bytes from the EEPROM. 411 */ 412 int 413 bge_read_eeprom(sc, dest, off, cnt) 414 struct bge_softc *sc; 415 caddr_t dest; 416 int off; 417 int cnt; 418 { 419 int err = 0, i; 420 u_int8_t byte = 0; 421 422 for (i = 0; i < cnt; i++) { 423 err = bge_eeprom_getbyte(sc, off + i, &byte); 424 if (err) 425 break; 426 *(dest + i) = byte; 427 } 428 429 return(err ? 1 : 0); 430 } 431 432 int 433 bge_miibus_readreg(dev, phy, reg) 434 struct device *dev; 435 int phy, reg; 436 { 437 struct bge_softc *sc = (struct bge_softc *)dev; 438 struct ifnet *ifp; 439 u_int32_t val; 440 u_int32_t saved_autopoll; 441 int i; 442 443 ifp = &sc->ethercom.ec_if; 444 445 /* 446 * Several chips with builtin PHYs will incorrectly answer to 447 * other PHY instances than the builtin PHY at id 1. 448 */ 449 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 450 return(0); 451 452 /* Reading with autopolling on may trigger PCI errors */ 453 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 454 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 455 CSR_WRITE_4(sc, BGE_MI_MODE, 456 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 457 DELAY(40); 458 } 459 460 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 461 BGE_MIPHY(phy)|BGE_MIREG(reg)); 462 463 for (i = 0; i < BGE_TIMEOUT; i++) { 464 val = CSR_READ_4(sc, BGE_MI_COMM); 465 if (!(val & BGE_MICOMM_BUSY)) 466 break; 467 delay(10); 468 } 469 470 if (i == BGE_TIMEOUT) { 471 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 472 val = 0; 473 goto done; 474 } 475 476 val = CSR_READ_4(sc, BGE_MI_COMM); 477 478 done: 479 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 480 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 481 DELAY(40); 482 } 483 484 if (val & BGE_MICOMM_READFAIL) 485 return(0); 486 487 return(val & 0xFFFF); 488 } 489 490 void 491 bge_miibus_writereg(dev, phy, reg, val) 492 struct device *dev; 493 int phy, reg, val; 494 { 495 struct bge_softc *sc = (struct bge_softc *)dev; 496 u_int32_t saved_autopoll; 497 int i; 498 499 /* Touching the PHY while autopolling is on may trigger PCI errors */ 500 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 501 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 502 delay(40); 503 CSR_WRITE_4(sc, BGE_MI_MODE, 504 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 505 delay(10); /* 40 usec is supposed to be adequate */ 506 } 507 508 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 509 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 510 511 for (i = 0; i < BGE_TIMEOUT; i++) { 512 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 513 break; 514 delay(10); 515 } 516 517 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 518 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 519 delay(40); 520 } 521 522 if (i == BGE_TIMEOUT) { 523 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 524 } 525 } 526 527 void 528 bge_miibus_statchg(dev) 529 struct device *dev; 530 { 531 struct bge_softc *sc = (struct bge_softc *)dev; 532 struct mii_data *mii = &sc->bge_mii; 533 534 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 535 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 536 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 537 } else { 538 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 539 } 540 541 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 542 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 543 } else { 544 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 545 } 546 } 547 548 /* 549 * Handle events that have triggered interrupts. 550 */ 551 void 552 bge_handle_events(sc) 553 struct bge_softc *sc; 554 { 555 556 return; 557 } 558 559 /* 560 * Memory management for jumbo frames. 561 */ 562 563 int 564 bge_alloc_jumbo_mem(sc) 565 struct bge_softc *sc; 566 { 567 caddr_t ptr, kva; 568 bus_dma_segment_t seg; 569 int i, rseg, state, error; 570 struct bge_jpool_entry *entry; 571 572 state = error = 0; 573 574 /* Grab a big chunk o' storage. */ 575 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 576 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 577 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 578 return ENOBUFS; 579 } 580 581 state = 1; 582 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 583 BUS_DMA_NOWAIT)) { 584 printf("%s: can't map DMA buffers (%d bytes)\n", 585 sc->bge_dev.dv_xname, (int)BGE_JMEM); 586 error = ENOBUFS; 587 goto out; 588 } 589 590 state = 2; 591 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 592 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 593 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 594 error = ENOBUFS; 595 goto out; 596 } 597 598 state = 3; 599 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 600 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 601 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 602 error = ENOBUFS; 603 goto out; 604 } 605 606 state = 4; 607 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 608 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 609 610 SLIST_INIT(&sc->bge_jfree_listhead); 611 SLIST_INIT(&sc->bge_jinuse_listhead); 612 613 /* 614 * Now divide it up into 9K pieces and save the addresses 615 * in an array. 616 */ 617 ptr = sc->bge_cdata.bge_jumbo_buf; 618 for (i = 0; i < BGE_JSLOTS; i++) { 619 sc->bge_cdata.bge_jslots[i] = ptr; 620 ptr += BGE_JLEN; 621 entry = malloc(sizeof(struct bge_jpool_entry), 622 M_DEVBUF, M_NOWAIT); 623 if (entry == NULL) { 624 printf("%s: no memory for jumbo buffer queue!\n", 625 sc->bge_dev.dv_xname); 626 error = ENOBUFS; 627 goto out; 628 } 629 entry->slot = i; 630 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 631 entry, jpool_entries); 632 } 633 out: 634 if (error != 0) { 635 switch (state) { 636 case 4: 637 bus_dmamap_unload(sc->bge_dmatag, 638 sc->bge_cdata.bge_rx_jumbo_map); 639 case 3: 640 bus_dmamap_destroy(sc->bge_dmatag, 641 sc->bge_cdata.bge_rx_jumbo_map); 642 case 2: 643 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 644 case 1: 645 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 646 break; 647 default: 648 break; 649 } 650 } 651 652 return error; 653 } 654 655 /* 656 * Allocate a jumbo buffer. 657 */ 658 void * 659 bge_jalloc(sc) 660 struct bge_softc *sc; 661 { 662 struct bge_jpool_entry *entry; 663 664 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 665 666 if (entry == NULL) { 667 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 668 return(NULL); 669 } 670 671 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 672 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 673 return(sc->bge_cdata.bge_jslots[entry->slot]); 674 } 675 676 /* 677 * Release a jumbo buffer. 678 */ 679 void 680 bge_jfree(m, buf, size, arg) 681 struct mbuf *m; 682 caddr_t buf; 683 size_t size; 684 void *arg; 685 { 686 struct bge_jpool_entry *entry; 687 struct bge_softc *sc; 688 int i, s; 689 690 /* Extract the softc struct pointer. */ 691 sc = (struct bge_softc *)arg; 692 693 if (sc == NULL) 694 panic("bge_jfree: can't find softc pointer!"); 695 696 /* calculate the slot this buffer belongs to */ 697 698 i = ((caddr_t)buf 699 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 700 701 if ((i < 0) || (i >= BGE_JSLOTS)) 702 panic("bge_jfree: asked to free buffer that we don't manage!"); 703 704 s = splvm(); 705 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 706 if (entry == NULL) 707 panic("bge_jfree: buffer not in use!"); 708 entry->slot = i; 709 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 710 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 711 712 if (__predict_true(m != NULL)) 713 pool_cache_put(&mbpool_cache, m); 714 splx(s); 715 } 716 717 718 /* 719 * Intialize a standard receive ring descriptor. 720 */ 721 int 722 bge_newbuf_std(sc, i, m, dmamap) 723 struct bge_softc *sc; 724 int i; 725 struct mbuf *m; 726 bus_dmamap_t dmamap; 727 { 728 struct mbuf *m_new = NULL; 729 struct bge_rx_bd *r; 730 int error; 731 732 if (dmamap == NULL) { 733 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 734 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 735 if (error != 0) 736 return error; 737 } 738 739 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 740 741 if (m == NULL) { 742 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 743 if (m_new == NULL) { 744 return(ENOBUFS); 745 } 746 747 MCLGET(m_new, M_DONTWAIT); 748 if (!(m_new->m_flags & M_EXT)) { 749 m_freem(m_new); 750 return(ENOBUFS); 751 } 752 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 753 if (!sc->bge_rx_alignment_bug) 754 m_adj(m_new, ETHER_ALIGN); 755 756 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 757 BUS_DMA_READ|BUS_DMA_NOWAIT)) 758 return(ENOBUFS); 759 } else { 760 m_new = m; 761 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 762 m_new->m_data = m_new->m_ext.ext_buf; 763 if (!sc->bge_rx_alignment_bug) 764 m_adj(m_new, ETHER_ALIGN); 765 } 766 767 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 768 r = &sc->bge_rdata->bge_rx_std_ring[i]; 769 bge_set_hostaddr(&r->bge_addr, 770 dmamap->dm_segs[0].ds_addr); 771 r->bge_flags = BGE_RXBDFLAG_END; 772 r->bge_len = m_new->m_len; 773 r->bge_idx = i; 774 775 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 776 offsetof(struct bge_ring_data, bge_rx_std_ring) + 777 i * sizeof (struct bge_rx_bd), 778 sizeof (struct bge_rx_bd), 779 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 780 781 return(0); 782 } 783 784 /* 785 * Initialize a jumbo receive ring descriptor. This allocates 786 * a jumbo buffer from the pool managed internally by the driver. 787 */ 788 int 789 bge_newbuf_jumbo(sc, i, m) 790 struct bge_softc *sc; 791 int i; 792 struct mbuf *m; 793 { 794 struct mbuf *m_new = NULL; 795 struct bge_rx_bd *r; 796 797 if (m == NULL) { 798 caddr_t *buf = NULL; 799 800 /* Allocate the mbuf. */ 801 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 802 if (m_new == NULL) { 803 return(ENOBUFS); 804 } 805 806 /* Allocate the jumbo buffer */ 807 buf = bge_jalloc(sc); 808 if (buf == NULL) { 809 m_freem(m_new); 810 printf("%s: jumbo allocation failed " 811 "-- packet dropped!\n", sc->bge_dev.dv_xname); 812 return(ENOBUFS); 813 } 814 815 /* Attach the buffer to the mbuf. */ 816 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 817 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 818 bge_jfree, sc); 819 } else { 820 m_new = m; 821 m_new->m_data = m_new->m_ext.ext_buf; 822 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 823 } 824 825 if (!sc->bge_rx_alignment_bug) 826 m_adj(m_new, ETHER_ALIGN); 827 /* Set up the descriptor. */ 828 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 829 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 830 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 831 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 832 r->bge_len = m_new->m_len; 833 r->bge_idx = i; 834 835 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 836 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 837 i * sizeof (struct bge_rx_bd), 838 sizeof (struct bge_rx_bd), 839 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 840 841 return(0); 842 } 843 844 /* 845 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 846 * that's 1MB or memory, which is a lot. For now, we fill only the first 847 * 256 ring entries and hope that our CPU is fast enough to keep up with 848 * the NIC. 849 */ 850 int 851 bge_init_rx_ring_std(sc) 852 struct bge_softc *sc; 853 { 854 int i; 855 856 if (sc->bge_flags & BGE_RXRING_VALID) 857 return 0; 858 859 for (i = 0; i < BGE_SSLOTS; i++) { 860 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 861 return(ENOBUFS); 862 } 863 864 sc->bge_std = i - 1; 865 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 866 867 sc->bge_flags |= BGE_RXRING_VALID; 868 869 return(0); 870 } 871 872 void 873 bge_free_rx_ring_std(sc) 874 struct bge_softc *sc; 875 { 876 int i; 877 878 if (!(sc->bge_flags & BGE_RXRING_VALID)) 879 return; 880 881 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 882 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 883 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 884 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 885 bus_dmamap_destroy(sc->bge_dmatag, 886 sc->bge_cdata.bge_rx_std_map[i]); 887 } 888 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 889 sizeof(struct bge_rx_bd)); 890 } 891 892 sc->bge_flags &= ~BGE_RXRING_VALID; 893 } 894 895 int 896 bge_init_rx_ring_jumbo(sc) 897 struct bge_softc *sc; 898 { 899 int i; 900 volatile struct bge_rcb *rcb; 901 902 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 903 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 904 return(ENOBUFS); 905 }; 906 907 sc->bge_jumbo = i - 1; 908 909 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 910 rcb->bge_maxlen_flags = 0; 911 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 912 913 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 914 915 return(0); 916 } 917 918 void 919 bge_free_rx_ring_jumbo(sc) 920 struct bge_softc *sc; 921 { 922 int i; 923 924 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 925 return; 926 927 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 928 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 929 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 930 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 931 } 932 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 933 sizeof(struct bge_rx_bd)); 934 } 935 936 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 937 } 938 939 void 940 bge_free_tx_ring(sc) 941 struct bge_softc *sc; 942 { 943 int i, freed; 944 struct txdmamap_pool_entry *dma; 945 946 if (!(sc->bge_flags & BGE_TXRING_VALID)) 947 return; 948 949 freed = 0; 950 951 for (i = 0; i < BGE_TX_RING_CNT; i++) { 952 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 953 freed++; 954 m_freem(sc->bge_cdata.bge_tx_chain[i]); 955 sc->bge_cdata.bge_tx_chain[i] = NULL; 956 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 957 link); 958 sc->txdma[i] = 0; 959 } 960 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 961 sizeof(struct bge_tx_bd)); 962 } 963 964 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 965 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 966 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 967 free(dma, M_DEVBUF); 968 } 969 970 sc->bge_flags &= ~BGE_TXRING_VALID; 971 } 972 973 int 974 bge_init_tx_ring(sc) 975 struct bge_softc *sc; 976 { 977 int i; 978 bus_dmamap_t dmamap; 979 struct txdmamap_pool_entry *dma; 980 981 if (sc->bge_flags & BGE_TXRING_VALID) 982 return 0; 983 984 sc->bge_txcnt = 0; 985 sc->bge_tx_saved_considx = 0; 986 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 987 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 988 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 989 990 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 991 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 992 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 993 994 SLIST_INIT(&sc->txdma_list); 995 for (i = 0; i < BGE_RSLOTS; i++) { 996 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 997 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 998 &dmamap)) 999 return(ENOBUFS); 1000 if (dmamap == NULL) 1001 panic("dmamap NULL in bge_init_tx_ring"); 1002 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1003 if (dma == NULL) { 1004 printf("%s: can't alloc txdmamap_pool_entry\n", 1005 sc->bge_dev.dv_xname); 1006 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1007 return (ENOMEM); 1008 } 1009 dma->dmamap = dmamap; 1010 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1011 } 1012 1013 sc->bge_flags |= BGE_TXRING_VALID; 1014 1015 return(0); 1016 } 1017 1018 void 1019 bge_setmulti(sc) 1020 struct bge_softc *sc; 1021 { 1022 struct ethercom *ac = &sc->ethercom; 1023 struct ifnet *ifp = &ac->ec_if; 1024 struct ether_multi *enm; 1025 struct ether_multistep step; 1026 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1027 u_int32_t h; 1028 int i; 1029 1030 if (ifp->if_flags & IFF_PROMISC) 1031 goto allmulti; 1032 1033 /* Now program new ones. */ 1034 ETHER_FIRST_MULTI(step, ac, enm); 1035 while (enm != NULL) { 1036 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1037 /* 1038 * We must listen to a range of multicast addresses. 1039 * For now, just accept all multicasts, rather than 1040 * trying to set only those filter bits needed to match 1041 * the range. (At this time, the only use of address 1042 * ranges is for IP multicast routing, for which the 1043 * range is big enough to require all bits set.) 1044 */ 1045 goto allmulti; 1046 } 1047 1048 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1049 1050 /* Just want the 7 least-significant bits. */ 1051 h &= 0x7f; 1052 1053 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1054 ETHER_NEXT_MULTI(step, enm); 1055 } 1056 1057 ifp->if_flags &= ~IFF_ALLMULTI; 1058 goto setit; 1059 1060 allmulti: 1061 ifp->if_flags |= IFF_ALLMULTI; 1062 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1063 1064 setit: 1065 for (i = 0; i < 4; i++) 1066 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1067 } 1068 1069 const int bge_swapbits[] = { 1070 0, 1071 BGE_MODECTL_BYTESWAP_DATA, 1072 BGE_MODECTL_WORDSWAP_DATA, 1073 BGE_MODECTL_BYTESWAP_NONFRAME, 1074 BGE_MODECTL_WORDSWAP_NONFRAME, 1075 1076 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1077 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1078 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1079 1080 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1081 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1082 1083 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1084 1085 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1086 BGE_MODECTL_BYTESWAP_NONFRAME, 1087 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1088 BGE_MODECTL_WORDSWAP_NONFRAME, 1089 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1090 BGE_MODECTL_WORDSWAP_NONFRAME, 1091 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1092 BGE_MODECTL_WORDSWAP_NONFRAME, 1093 1094 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1095 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1096 }; 1097 1098 int bge_swapindex = 0; 1099 1100 /* 1101 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1102 * self-test results. 1103 */ 1104 int 1105 bge_chipinit(sc) 1106 struct bge_softc *sc; 1107 { 1108 u_int32_t cachesize; 1109 int i; 1110 u_int32_t dma_rw_ctl; 1111 struct pci_attach_args *pa = &(sc->bge_pa); 1112 1113 1114 /* Set endianness before we access any non-PCI registers. */ 1115 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1116 BGE_INIT); 1117 1118 /* Set power state to D0. */ 1119 bge_setpowerstate(sc, 0); 1120 1121 /* 1122 * Check the 'ROM failed' bit on the RX CPU to see if 1123 * self-tests passed. 1124 */ 1125 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1126 printf("%s: RX CPU self-diagnostics failed!\n", 1127 sc->bge_dev.dv_xname); 1128 return(ENODEV); 1129 } 1130 1131 /* Clear the MAC control register */ 1132 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1133 1134 /* 1135 * Clear the MAC statistics block in the NIC's 1136 * internal memory. 1137 */ 1138 for (i = BGE_STATS_BLOCK; 1139 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1140 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1141 1142 for (i = BGE_STATUS_BLOCK; 1143 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1144 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1145 1146 /* Set up the PCI DMA control register. */ 1147 if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1148 BGE_PCISTATE_PCI_BUSMODE) { 1149 /* Conventional PCI bus */ 1150 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1151 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1152 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1153 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1154 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1155 dma_rw_ctl |= 0x0F; 1156 } 1157 } else { 1158 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1159 /* PCI-X bus */ 1160 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1161 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1162 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1163 (0x0F); 1164 /* 1165 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1166 * for hardware bugs, which means we should also clear 1167 * the low-order MINDMA bits. In addition, the 5704 1168 * uses a different encoding of read/write watermarks. 1169 */ 1170 if (sc->bge_asicrev == BGE_ASICREV_BCM5704_A0 || 1171 sc->bge_asicrev == BGE_ASICREV_BCM5704_A1 || 1172 sc->bge_asicrev == BGE_ASICREV_BCM5704_A2 || 1173 sc->bge_asicrev == BGE_ASICREV_BCM5704_A3) { 1174 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1175 /* should be 0x1f0000 */ 1176 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1177 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1178 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1179 } 1180 else if ((sc->bge_asicrev >> 28) == 1181 (BGE_ASICREV_BCM5703_A0 >> 28)) { 1182 dma_rw_ctl &= 0xfffffff0; 1183 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1184 } 1185 } 1186 1187 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1188 1189 /* 1190 * Set up general mode register. 1191 */ 1192 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1193 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1194 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1195 BGE_MODECTL_RX_NO_PHDR_CSUM); 1196 1197 /* Get cache line size. */ 1198 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1199 1200 /* 1201 * Avoid violating PCI spec on certain chip revs. 1202 */ 1203 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1204 PCIM_CMD_MWIEN) { 1205 switch(cachesize) { 1206 case 1: 1207 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1208 BGE_PCI_WRITE_BNDRY_16BYTES); 1209 break; 1210 case 2: 1211 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1212 BGE_PCI_WRITE_BNDRY_32BYTES); 1213 break; 1214 case 4: 1215 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1216 BGE_PCI_WRITE_BNDRY_64BYTES); 1217 break; 1218 case 8: 1219 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1220 BGE_PCI_WRITE_BNDRY_128BYTES); 1221 break; 1222 case 16: 1223 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1224 BGE_PCI_WRITE_BNDRY_256BYTES); 1225 break; 1226 case 32: 1227 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1228 BGE_PCI_WRITE_BNDRY_512BYTES); 1229 break; 1230 case 64: 1231 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1232 BGE_PCI_WRITE_BNDRY_1024BYTES); 1233 break; 1234 default: 1235 /* Disable PCI memory write and invalidate. */ 1236 #if 0 1237 if (bootverbose) 1238 printf("%s: cache line size %d not " 1239 "supported; disabling PCI MWI\n", 1240 sc->bge_dev.dv_xname, cachesize); 1241 #endif 1242 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1243 PCIM_CMD_MWIEN); 1244 break; 1245 } 1246 } 1247 1248 /* 1249 * Disable memory write invalidate. Apparently it is not supported 1250 * properly by these devices. 1251 */ 1252 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1253 1254 1255 #ifdef __brokenalpha__ 1256 /* 1257 * Must insure that we do not cross an 8K (bytes) boundary 1258 * for DMA reads. Our highest limit is 1K bytes. This is a 1259 * restriction on some ALPHA platforms with early revision 1260 * 21174 PCI chipsets, such as the AlphaPC 164lx 1261 */ 1262 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1263 #endif 1264 1265 /* Set the timer prescaler (always 66MHz) */ 1266 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1267 1268 return(0); 1269 } 1270 1271 int 1272 bge_blockinit(sc) 1273 struct bge_softc *sc; 1274 { 1275 volatile struct bge_rcb *rcb; 1276 bus_size_t rcb_addr; 1277 int i; 1278 struct ifnet *ifp = &sc->ethercom.ec_if; 1279 bge_hostaddr taddr; 1280 1281 /* 1282 * Initialize the memory window pointer register so that 1283 * we can access the first 32K of internal NIC RAM. This will 1284 * allow us to set up the TX send ring RCBs and the RX return 1285 * ring RCBs, plus other things which live in NIC memory. 1286 */ 1287 1288 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1289 BGE_PCI_MEMWIN_BASEADDR, 0); 1290 1291 /* Configure mbuf memory pool */ 1292 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1293 if (sc->bge_extram) { 1294 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1295 BGE_EXT_SSRAM); 1296 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1297 } else { 1298 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1299 BGE_BUFFPOOL_1); 1300 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1301 } 1302 1303 /* Configure DMA resource pool */ 1304 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1305 BGE_DMA_DESCRIPTORS); 1306 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1307 } 1308 1309 /* Configure mbuf pool watermarks */ 1310 #ifdef ORIG_WPAUL_VALUES 1311 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1312 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1313 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1314 #else 1315 /* new broadcom docs strongly recommend these: */ 1316 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1317 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1318 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1319 } else { 1320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1321 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1322 } 1323 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1324 #endif 1325 1326 /* Configure DMA resource watermarks */ 1327 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1328 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1329 1330 /* Enable buffer manager */ 1331 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1332 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1333 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1334 1335 /* Poll for buffer manager start indication */ 1336 for (i = 0; i < BGE_TIMEOUT; i++) { 1337 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1338 break; 1339 DELAY(10); 1340 } 1341 1342 if (i == BGE_TIMEOUT) { 1343 printf("%s: buffer manager failed to start\n", 1344 sc->bge_dev.dv_xname); 1345 return(ENXIO); 1346 } 1347 } 1348 1349 /* Enable flow-through queues */ 1350 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1351 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1352 1353 /* Wait until queue initialization is complete */ 1354 for (i = 0; i < BGE_TIMEOUT; i++) { 1355 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1356 break; 1357 DELAY(10); 1358 } 1359 1360 if (i == BGE_TIMEOUT) { 1361 printf("%s: flow-through queue init failed\n", 1362 sc->bge_dev.dv_xname); 1363 return(ENXIO); 1364 } 1365 1366 /* Initialize the standard RX ring control block */ 1367 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1368 bge_set_hostaddr(&rcb->bge_hostaddr, 1369 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1370 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1371 rcb->bge_maxlen_flags = 1372 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1373 } else { 1374 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1375 } 1376 if (sc->bge_extram) 1377 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1378 else 1379 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1380 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1381 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1382 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1383 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1384 1385 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1386 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1387 } else { 1388 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1389 } 1390 1391 /* 1392 * Initialize the jumbo RX ring control block 1393 * We set the 'ring disabled' bit in the flags 1394 * field until we're actually ready to start 1395 * using this ring (i.e. once we set the MTU 1396 * high enough to require it). 1397 */ 1398 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1399 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1400 bge_set_hostaddr(&rcb->bge_hostaddr, 1401 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1402 rcb->bge_maxlen_flags = 1403 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1404 BGE_RCB_FLAG_RING_DISABLED); 1405 if (sc->bge_extram) 1406 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1407 else 1408 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1409 1410 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1411 rcb->bge_hostaddr.bge_addr_hi); 1412 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1413 rcb->bge_hostaddr.bge_addr_lo); 1414 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1415 rcb->bge_maxlen_flags); 1416 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1417 1418 /* Set up dummy disabled mini ring RCB */ 1419 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1420 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1421 BGE_RCB_FLAG_RING_DISABLED); 1422 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1423 rcb->bge_maxlen_flags); 1424 1425 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1426 offsetof(struct bge_ring_data, bge_info), 1427 sizeof (struct bge_gib), 1428 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1429 } 1430 1431 /* 1432 * Set the BD ring replentish thresholds. The recommended 1433 * values are 1/8th the number of descriptors allocated to 1434 * each ring. 1435 */ 1436 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1437 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1438 1439 /* 1440 * Disable all unused send rings by setting the 'ring disabled' 1441 * bit in the flags field of all the TX send ring control blocks. 1442 * These are located in NIC memory. 1443 */ 1444 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1445 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1446 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1447 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1448 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1449 rcb_addr += sizeof(struct bge_rcb); 1450 } 1451 1452 /* Configure TX RCB 0 (we use only the first ring) */ 1453 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1454 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1455 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1456 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1457 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1458 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1459 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1460 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1461 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1462 } 1463 1464 /* Disable all unused RX return rings */ 1465 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1466 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1467 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1468 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1469 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1470 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1471 BGE_RCB_FLAG_RING_DISABLED)); 1472 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1473 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1474 (i * (sizeof(u_int64_t))), 0); 1475 rcb_addr += sizeof(struct bge_rcb); 1476 } 1477 1478 /* Initialize RX ring indexes */ 1479 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1480 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1481 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1482 1483 /* 1484 * Set up RX return ring 0 1485 * Note that the NIC address for RX return rings is 0x00000000. 1486 * The return rings live entirely within the host, so the 1487 * nicaddr field in the RCB isn't used. 1488 */ 1489 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1490 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1491 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1492 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1493 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1494 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1495 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1496 1497 /* Set random backoff seed for TX */ 1498 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1499 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1500 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1501 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1502 BGE_TX_BACKOFF_SEED_MASK); 1503 1504 /* Set inter-packet gap */ 1505 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1506 1507 /* 1508 * Specify which ring to use for packets that don't match 1509 * any RX rules. 1510 */ 1511 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1512 1513 /* 1514 * Configure number of RX lists. One interrupt distribution 1515 * list, sixteen active lists, one bad frames class. 1516 */ 1517 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1518 1519 /* Inialize RX list placement stats mask. */ 1520 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1521 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1522 1523 /* Disable host coalescing until we get it set up */ 1524 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1525 1526 /* Poll to make sure it's shut down. */ 1527 for (i = 0; i < BGE_TIMEOUT; i++) { 1528 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1529 break; 1530 DELAY(10); 1531 } 1532 1533 if (i == BGE_TIMEOUT) { 1534 printf("%s: host coalescing engine failed to idle\n", 1535 sc->bge_dev.dv_xname); 1536 return(ENXIO); 1537 } 1538 1539 /* Set up host coalescing defaults */ 1540 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1541 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1542 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1543 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1544 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1545 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1546 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1547 } 1548 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1549 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1550 1551 /* Set up address of statistics block */ 1552 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1553 bge_set_hostaddr(&taddr, 1554 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1555 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1556 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1557 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1558 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1559 } 1560 1561 /* Set up address of status block */ 1562 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1563 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1564 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1565 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1566 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1567 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1568 1569 /* Turn on host coalescing state machine */ 1570 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1571 1572 /* Turn on RX BD completion state machine and enable attentions */ 1573 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1574 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1575 1576 /* Turn on RX list placement state machine */ 1577 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1578 1579 /* Turn on RX list selector state machine. */ 1580 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1581 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1582 } 1583 1584 /* Turn on DMA, clear stats */ 1585 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1586 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1587 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1588 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1589 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1590 1591 /* Set misc. local control, enable interrupts on attentions */ 1592 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1593 1594 #ifdef notdef 1595 /* Assert GPIO pins for PHY reset */ 1596 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1597 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1598 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1599 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1600 #endif 1601 1602 #if defined(not_quite_yet) 1603 /* Linux driver enables enable gpio pin #1 on 5700s */ 1604 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 1605 sc->bge_local_ctrl_reg |= 1606 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1607 } 1608 #endif 1609 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1610 1611 /* Turn on DMA completion state machine */ 1612 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1613 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1614 } 1615 1616 /* Turn on write DMA state machine */ 1617 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1618 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1619 1620 /* Turn on read DMA state machine */ 1621 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1622 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1623 1624 /* Turn on RX data completion state machine */ 1625 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1626 1627 /* Turn on RX BD initiator state machine */ 1628 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1629 1630 /* Turn on RX data and RX BD initiator state machine */ 1631 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1632 1633 /* Turn on Mbuf cluster free state machine */ 1634 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1635 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1636 } 1637 1638 /* Turn on send BD completion state machine */ 1639 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1640 1641 /* Turn on send data completion state machine */ 1642 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1643 1644 /* Turn on send data initiator state machine */ 1645 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1646 1647 /* Turn on send BD initiator state machine */ 1648 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1649 1650 /* Turn on send BD selector state machine */ 1651 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1652 1653 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1654 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1655 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1656 1657 /* init LED register */ 1658 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1659 1660 /* ack/clear link change events */ 1661 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1662 BGE_MACSTAT_CFG_CHANGED); 1663 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1664 1665 /* Enable PHY auto polling (for MII/GMII only) */ 1666 if (sc->bge_tbi) { 1667 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1668 } else { 1669 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1670 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1671 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1672 BGE_EVTENB_MI_INTERRUPT); 1673 } 1674 1675 /* Enable link state change attentions. */ 1676 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1677 1678 return(0); 1679 } 1680 1681 static const struct bge_revision { 1682 uint32_t br_asicrev; 1683 uint32_t br_quirks; 1684 const char *br_name; 1685 } bge_revisions[] = { 1686 { BGE_ASICREV_BCM5700_A0, 1687 BGE_QUIRK_LINK_STATE_BROKEN, 1688 "BCM5700 A0" }, 1689 1690 { BGE_ASICREV_BCM5700_A1, 1691 BGE_QUIRK_LINK_STATE_BROKEN, 1692 "BCM5700 A1" }, 1693 1694 { BGE_ASICREV_BCM5700_B0, 1695 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1696 "BCM5700 B0" }, 1697 1698 { BGE_ASICREV_BCM5700_B1, 1699 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1700 "BCM5700 B1" }, 1701 1702 { BGE_ASICREV_BCM5700_B2, 1703 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1704 "BCM5700 B2" }, 1705 1706 /* This is treated like a BCM5700 Bx */ 1707 { BGE_ASICREV_BCM5700_ALTIMA, 1708 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1709 "BCM5700 Altima" }, 1710 1711 { BGE_ASICREV_BCM5700_C0, 1712 0, 1713 "BCM5700 C0" }, 1714 1715 { BGE_ASICREV_BCM5701_A0, 1716 0, /*XXX really, just not known */ 1717 "BCM5701 A0" }, 1718 1719 { BGE_ASICREV_BCM5701_B0, 1720 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1721 "BCM5701 B0" }, 1722 1723 { BGE_ASICREV_BCM5701_B2, 1724 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1725 "BCM5701 B2" }, 1726 1727 { BGE_ASICREV_BCM5701_B5, 1728 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1729 "BCM5701 B5" }, 1730 1731 { BGE_ASICREV_BCM5703_A0, 1732 0, 1733 "BCM5703 A0" }, 1734 1735 { BGE_ASICREV_BCM5703_A1, 1736 0, 1737 "BCM5703 A1" }, 1738 1739 { BGE_ASICREV_BCM5703_A2, 1740 BGE_QUIRK_ONLY_PHY_1, 1741 "BCM5703 A2" }, 1742 1743 { BGE_ASICREV_BCM5704_A0, 1744 BGE_QUIRK_ONLY_PHY_1, 1745 "BCM5704 A0" }, 1746 1747 { BGE_ASICREV_BCM5704_A1, 1748 BGE_QUIRK_ONLY_PHY_1, 1749 "BCM5704 A1" }, 1750 1751 { BGE_ASICREV_BCM5704_A2, 1752 BGE_QUIRK_ONLY_PHY_1, 1753 "BCM5704 A2" }, 1754 1755 { BGE_ASICREV_BCM5704_A3, 1756 BGE_QUIRK_ONLY_PHY_1, 1757 "BCM5704 A3" }, 1758 1759 { BGE_ASICREV_BCM5705_A1, 1760 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1761 "BCM5705 A1" }, 1762 1763 { 0, 0, NULL } 1764 }; 1765 1766 static const struct bge_revision * 1767 bge_lookup_rev(uint32_t asicrev) 1768 { 1769 const struct bge_revision *br; 1770 1771 for (br = bge_revisions; br->br_name != NULL; br++) { 1772 if (br->br_asicrev == asicrev) 1773 return (br); 1774 } 1775 1776 return (NULL); 1777 } 1778 1779 static const struct bge_product { 1780 pci_vendor_id_t bp_vendor; 1781 pci_product_id_t bp_product; 1782 const char *bp_name; 1783 } bge_products[] = { 1784 /* 1785 * The BCM5700 documentation seems to indicate that the hardware 1786 * still has the Alteon vendor ID burned into it, though it 1787 * should always be overridden by the value in the EEPROM. We'll 1788 * check for it anyway. 1789 */ 1790 { PCI_VENDOR_ALTEON, 1791 PCI_PRODUCT_ALTEON_BCM5700, 1792 "Broadcom BCM5700 Gigabit Ethernet" }, 1793 { PCI_VENDOR_ALTEON, 1794 PCI_PRODUCT_ALTEON_BCM5701, 1795 "Broadcom BCM5701 Gigabit Ethernet" }, 1796 1797 { PCI_VENDOR_ALTIMA, 1798 PCI_PRODUCT_ALTIMA_AC1000, 1799 "Altima AC1000 Gigabit Ethernet" }, 1800 { PCI_VENDOR_ALTIMA, 1801 PCI_PRODUCT_ALTIMA_AC1001, 1802 "Altima AC1001 Gigabit Ethernet" }, 1803 { PCI_VENDOR_ALTIMA, 1804 PCI_PRODUCT_ALTIMA_AC9100, 1805 "Altima AC9100 Gigabit Ethernet" }, 1806 1807 { PCI_VENDOR_BROADCOM, 1808 PCI_PRODUCT_BROADCOM_BCM5700, 1809 "Broadcom BCM5700 Gigabit Ethernet" }, 1810 { PCI_VENDOR_BROADCOM, 1811 PCI_PRODUCT_BROADCOM_BCM5701, 1812 "Broadcom BCM5701 Gigabit Ethernet" }, 1813 { PCI_VENDOR_BROADCOM, 1814 PCI_PRODUCT_BROADCOM_BCM5702, 1815 "Broadcom BCM5702 Gigabit Ethernet" }, 1816 { PCI_VENDOR_BROADCOM, 1817 PCI_PRODUCT_BROADCOM_BCM5702X, 1818 "Broadcom BCM5702X Gigabit Ethernet" }, 1819 { PCI_VENDOR_BROADCOM, 1820 PCI_PRODUCT_BROADCOM_BCM5703, 1821 "Broadcom BCM5703 Gigabit Ethernet" }, 1822 { PCI_VENDOR_BROADCOM, 1823 PCI_PRODUCT_BROADCOM_BCM5703X, 1824 "Broadcom BCM5703X Gigabit Ethernet" }, 1825 { PCI_VENDOR_BROADCOM, 1826 PCI_PRODUCT_BROADCOM_BCM5704C, 1827 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 1828 { PCI_VENDOR_BROADCOM, 1829 PCI_PRODUCT_BROADCOM_BCM5704S, 1830 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 1831 { PCI_VENDOR_BROADCOM, 1832 PCI_PRODUCT_BROADCOM_BCM5705M, 1833 "Broadcom BCM5705M Gigabit Ethernet" }, 1834 1835 { PCI_VENDOR_SCHNEIDERKOCH, 1836 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1837 "SysKonnect SK-9Dx1 Gigabit Ethernet" }, 1838 1839 { PCI_VENDOR_3COM, 1840 PCI_PRODUCT_3COM_3C996, 1841 "3Com 3c996 Gigabit Ethernet" }, 1842 1843 { 0, 1844 0, 1845 NULL }, 1846 }; 1847 1848 static const struct bge_product * 1849 bge_lookup(const struct pci_attach_args *pa) 1850 { 1851 const struct bge_product *bp; 1852 1853 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1854 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1855 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1856 return (bp); 1857 } 1858 1859 return (NULL); 1860 } 1861 1862 int 1863 bge_setpowerstate(sc, powerlevel) 1864 struct bge_softc *sc; 1865 int powerlevel; 1866 { 1867 #ifdef NOTYET 1868 u_int32_t pm_ctl = 0; 1869 1870 /* XXX FIXME: make sure indirect accesses enabled? */ 1871 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 1872 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 1873 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 1874 1875 /* clear the PME_assert bit and power state bits, enable PME */ 1876 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 1877 pm_ctl &= ~PCIM_PSTAT_DMASK; 1878 pm_ctl |= (1 << 8); 1879 1880 if (powerlevel == 0) { 1881 pm_ctl |= PCIM_PSTAT_D0; 1882 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 1883 pm_ctl, 2); 1884 DELAY(10000); 1885 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1886 DELAY(10000); 1887 1888 #ifdef NOTYET 1889 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 1890 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 1891 #endif 1892 DELAY(40); DELAY(40); DELAY(40); 1893 DELAY(10000); /* above not quite adequate on 5700 */ 1894 return 0; 1895 } 1896 1897 1898 /* 1899 * Entering ACPI power states D1-D3 is achieved by wiggling 1900 * GMII gpio pins. Example code assumes all hardware vendors 1901 * followed Broadom's sample pcb layout. Until we verify that 1902 * for all supported OEM cards, states D1-D3 are unsupported. 1903 */ 1904 printf("%s: power state %d unimplemented; check GPIO pins\n", 1905 sc->bge_dev.dv_xname, powerlevel); 1906 #endif 1907 return EOPNOTSUPP; 1908 } 1909 1910 1911 /* 1912 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1913 * against our list and return its name if we find a match. Note 1914 * that since the Broadcom controller contains VPD support, we 1915 * can get the device name string from the controller itself instead 1916 * of the compiled-in string. This is a little slow, but it guarantees 1917 * we'll always announce the right product name. 1918 */ 1919 int 1920 bge_probe(parent, match, aux) 1921 struct device *parent; 1922 struct cfdata *match; 1923 void *aux; 1924 { 1925 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1926 1927 if (bge_lookup(pa) != NULL) 1928 return (1); 1929 1930 return (0); 1931 } 1932 1933 void 1934 bge_attach(parent, self, aux) 1935 struct device *parent, *self; 1936 void *aux; 1937 { 1938 struct bge_softc *sc = (struct bge_softc *)self; 1939 struct pci_attach_args *pa = aux; 1940 const struct bge_product *bp; 1941 const struct bge_revision *br; 1942 pci_chipset_tag_t pc = pa->pa_pc; 1943 pci_intr_handle_t ih; 1944 const char *intrstr = NULL; 1945 bus_dma_segment_t seg; 1946 int rseg; 1947 u_int32_t hwcfg = 0; 1948 u_int32_t mac_addr = 0; 1949 u_int32_t command; 1950 struct ifnet *ifp; 1951 caddr_t kva; 1952 u_char eaddr[ETHER_ADDR_LEN]; 1953 pcireg_t memtype; 1954 bus_addr_t memaddr; 1955 bus_size_t memsize; 1956 u_int32_t pm_ctl; 1957 1958 bp = bge_lookup(pa); 1959 KASSERT(bp != NULL); 1960 1961 sc->bge_pa = *pa; 1962 1963 aprint_naive(": Ethernet controller\n"); 1964 aprint_normal(": %s\n", bp->bp_name); 1965 1966 /* 1967 * Map control/status registers. 1968 */ 1969 DPRINTFN(5, ("Map control/status regs\n")); 1970 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1971 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1972 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1973 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1974 1975 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1976 aprint_error("%s: failed to enable memory mapping!\n", 1977 sc->bge_dev.dv_xname); 1978 return; 1979 } 1980 1981 DPRINTFN(5, ("pci_mem_find\n")); 1982 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1983 switch (memtype) { 1984 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1985 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1986 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1987 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1988 &memaddr, &memsize) == 0) 1989 break; 1990 default: 1991 aprint_error("%s: can't find mem space\n", 1992 sc->bge_dev.dv_xname); 1993 return; 1994 } 1995 1996 DPRINTFN(5, ("pci_intr_map\n")); 1997 if (pci_intr_map(pa, &ih)) { 1998 aprint_error("%s: couldn't map interrupt\n", 1999 sc->bge_dev.dv_xname); 2000 return; 2001 } 2002 2003 DPRINTFN(5, ("pci_intr_string\n")); 2004 intrstr = pci_intr_string(pc, ih); 2005 2006 DPRINTFN(5, ("pci_intr_establish\n")); 2007 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2008 2009 if (sc->bge_intrhand == NULL) { 2010 aprint_error("%s: couldn't establish interrupt", 2011 sc->bge_dev.dv_xname); 2012 if (intrstr != NULL) 2013 aprint_normal(" at %s", intrstr); 2014 aprint_normal("\n"); 2015 return; 2016 } 2017 aprint_normal("%s: interrupting at %s\n", 2018 sc->bge_dev.dv_xname, intrstr); 2019 2020 /* 2021 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2022 * can clobber the chip's PCI config-space power control registers, 2023 * leaving the card in D3 powersave state. 2024 * We do not have memory-mapped registers in this state, 2025 * so force device into D0 state before starting initialization. 2026 */ 2027 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2028 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2029 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2030 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2031 DELAY(1000); /* 27 usec is allegedly sufficent */ 2032 2033 /* Try to reset the chip. */ 2034 DPRINTFN(5, ("bge_reset\n")); 2035 bge_reset(sc); 2036 2037 if (bge_chipinit(sc)) { 2038 aprint_error("%s: chip initialization failed\n", 2039 sc->bge_dev.dv_xname); 2040 bge_release_resources(sc); 2041 return; 2042 } 2043 2044 /* 2045 * Get station address from the EEPROM. 2046 */ 2047 mac_addr = bge_readmem_ind(sc, 0x0c14); 2048 if ((mac_addr >> 16) == 0x484b) { 2049 eaddr[0] = (u_char)(mac_addr >> 8); 2050 eaddr[1] = (u_char)(mac_addr >> 0); 2051 mac_addr = bge_readmem_ind(sc, 0x0c18); 2052 eaddr[2] = (u_char)(mac_addr >> 24); 2053 eaddr[3] = (u_char)(mac_addr >> 16); 2054 eaddr[4] = (u_char)(mac_addr >> 8); 2055 eaddr[5] = (u_char)(mac_addr >> 0); 2056 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2057 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2058 aprint_error("%s: failed to read station address\n", 2059 sc->bge_dev.dv_xname); 2060 bge_release_resources(sc); 2061 return; 2062 } 2063 2064 /* 2065 * Save ASIC rev. Look up any quirks associated with this 2066 * ASIC. 2067 */ 2068 sc->bge_asicrev = 2069 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2070 BGE_PCIMISCCTL_ASICREV; 2071 br = bge_lookup_rev(sc->bge_asicrev); 2072 2073 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2074 if (br == NULL) { 2075 aprint_normal("unknown ASIC 0x%08x", sc->bge_asicrev); 2076 sc->bge_quirks = 0; 2077 } else { 2078 aprint_normal("ASIC %s", br->br_name); 2079 sc->bge_quirks = br->br_quirks; 2080 } 2081 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2082 2083 /* Allocate the general information block and ring buffers. */ 2084 if (pci_dma64_available(pa)) 2085 sc->bge_dmatag = pa->pa_dmat64; 2086 else 2087 sc->bge_dmatag = pa->pa_dmat; 2088 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2089 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2090 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2091 aprint_error("%s: can't alloc rx buffers\n", 2092 sc->bge_dev.dv_xname); 2093 return; 2094 } 2095 DPRINTFN(5, ("bus_dmamem_map\n")); 2096 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2097 sizeof(struct bge_ring_data), &kva, 2098 BUS_DMA_NOWAIT)) { 2099 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2100 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2101 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2102 return; 2103 } 2104 DPRINTFN(5, ("bus_dmamem_create\n")); 2105 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2106 sizeof(struct bge_ring_data), 0, 2107 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2108 aprint_error("%s: can't create DMA map\n", 2109 sc->bge_dev.dv_xname); 2110 bus_dmamem_unmap(sc->bge_dmatag, kva, 2111 sizeof(struct bge_ring_data)); 2112 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2113 return; 2114 } 2115 DPRINTFN(5, ("bus_dmamem_load\n")); 2116 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2117 sizeof(struct bge_ring_data), NULL, 2118 BUS_DMA_NOWAIT)) { 2119 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2120 bus_dmamem_unmap(sc->bge_dmatag, kva, 2121 sizeof(struct bge_ring_data)); 2122 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2123 return; 2124 } 2125 2126 DPRINTFN(5, ("bzero\n")); 2127 sc->bge_rdata = (struct bge_ring_data *)kva; 2128 2129 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2130 2131 /* Try to allocate memory for jumbo buffers. */ 2132 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2133 if (bge_alloc_jumbo_mem(sc)) { 2134 aprint_error("%s: jumbo buffer allocation failed\n", 2135 sc->bge_dev.dv_xname); 2136 } else 2137 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2138 } 2139 2140 /* Set default tuneable values. */ 2141 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2142 sc->bge_rx_coal_ticks = 150; 2143 sc->bge_rx_max_coal_bds = 64; 2144 #ifdef ORIG_WPAUL_VALUES 2145 sc->bge_tx_coal_ticks = 150; 2146 sc->bge_tx_max_coal_bds = 128; 2147 #else 2148 sc->bge_tx_coal_ticks = 300; 2149 sc->bge_tx_max_coal_bds = 400; 2150 #endif 2151 2152 /* Set up ifnet structure */ 2153 ifp = &sc->ethercom.ec_if; 2154 ifp->if_softc = sc; 2155 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2156 ifp->if_ioctl = bge_ioctl; 2157 ifp->if_start = bge_start; 2158 ifp->if_init = bge_init; 2159 ifp->if_watchdog = bge_watchdog; 2160 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2161 IFQ_SET_READY(&ifp->if_snd); 2162 DPRINTFN(5, ("bcopy\n")); 2163 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2164 2165 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2166 sc->ethercom.ec_if.if_capabilities |= 2167 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 2168 sc->ethercom.ec_capabilities |= 2169 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2170 2171 /* 2172 * Do MII setup. 2173 */ 2174 DPRINTFN(5, ("mii setup\n")); 2175 sc->bge_mii.mii_ifp = ifp; 2176 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2177 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2178 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2179 2180 /* 2181 * Figure out what sort of media we have by checking the 2182 * hardware config word in the first 32k of NIC internal memory, 2183 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2184 * cards, this value appears to be unset. If that's the 2185 * case, we have to rely on identifying the NIC by its PCI 2186 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2187 */ 2188 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2189 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2190 } else { 2191 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2192 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2193 hwcfg = be32toh(hwcfg); 2194 } 2195 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2196 sc->bge_tbi = 1; 2197 2198 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2199 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2200 SK_SUBSYSID_9D41) 2201 sc->bge_tbi = 1; 2202 2203 if (sc->bge_tbi) { 2204 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2205 bge_ifmedia_sts); 2206 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2207 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2208 0, NULL); 2209 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2210 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2211 } else { 2212 /* 2213 * Do transceiver setup. 2214 */ 2215 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2216 bge_ifmedia_sts); 2217 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2218 MII_PHY_ANY, MII_OFFSET_ANY, 0); 2219 2220 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2221 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2222 ifmedia_add(&sc->bge_mii.mii_media, 2223 IFM_ETHER|IFM_MANUAL, 0, NULL); 2224 ifmedia_set(&sc->bge_mii.mii_media, 2225 IFM_ETHER|IFM_MANUAL); 2226 } else 2227 ifmedia_set(&sc->bge_mii.mii_media, 2228 IFM_ETHER|IFM_AUTO); 2229 } 2230 2231 /* 2232 * When using the BCM5701 in PCI-X mode, data corruption has 2233 * been observed in the first few bytes of some received packets. 2234 * Aligning the packet buffer in memory eliminates the corruption. 2235 * Unfortunately, this misaligns the packet payloads. On platforms 2236 * which do not support unaligned accesses, we will realign the 2237 * payloads by copying the received packets. 2238 */ 2239 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2240 /* If in PCI-X mode, work around the alignment bug. */ 2241 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2242 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2243 BGE_PCISTATE_PCI_BUSSPEED) 2244 sc->bge_rx_alignment_bug = 1; 2245 } 2246 2247 /* 2248 * Call MI attach routine. 2249 */ 2250 DPRINTFN(5, ("if_attach\n")); 2251 if_attach(ifp); 2252 DPRINTFN(5, ("ether_ifattach\n")); 2253 ether_ifattach(ifp, eaddr); 2254 DPRINTFN(5, ("callout_init\n")); 2255 callout_init(&sc->bge_timeout); 2256 } 2257 2258 void 2259 bge_release_resources(sc) 2260 struct bge_softc *sc; 2261 { 2262 if (sc->bge_vpd_prodname != NULL) 2263 free(sc->bge_vpd_prodname, M_DEVBUF); 2264 2265 if (sc->bge_vpd_readonly != NULL) 2266 free(sc->bge_vpd_readonly, M_DEVBUF); 2267 } 2268 2269 void 2270 bge_reset(sc) 2271 struct bge_softc *sc; 2272 { 2273 struct pci_attach_args *pa = &sc->bge_pa; 2274 u_int32_t cachesize, command, pcistate; 2275 int i, val = 0; 2276 2277 /* Save some important PCI state. */ 2278 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2279 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2280 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2281 2282 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2283 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2284 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2285 2286 /* Issue global reset */ 2287 bge_writereg_ind(sc, BGE_MISC_CFG, 2288 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2289 2290 DELAY(1000); 2291 2292 /* Reset some of the PCI state that got zapped by reset */ 2293 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2294 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2295 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2296 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2297 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2298 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2299 2300 /* Enable memory arbiter. */ 2301 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2302 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2303 } 2304 2305 /* 2306 * Prevent PXE restart: write a magic number to the 2307 * general communications memory at 0xB50. 2308 */ 2309 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2310 2311 /* 2312 * Poll the value location we just wrote until 2313 * we see the 1's complement of the magic number. 2314 * This indicates that the firmware initialization 2315 * is complete. 2316 */ 2317 for (i = 0; i < 750; i++) { 2318 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2319 if (val == ~BGE_MAGIC_NUMBER) 2320 break; 2321 DELAY(1000); 2322 } 2323 2324 if (i == 750) { 2325 printf("%s: firmware handshake timed out, val = %x\n", 2326 sc->bge_dev.dv_xname, val); 2327 return; 2328 } 2329 2330 /* 2331 * XXX Wait for the value of the PCISTATE register to 2332 * return to its original pre-reset state. This is a 2333 * fairly good indicator of reset completion. If we don't 2334 * wait for the reset to fully complete, trying to read 2335 * from the device's non-PCI registers may yield garbage 2336 * results. 2337 */ 2338 for (i = 0; i < BGE_TIMEOUT; i++) { 2339 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2340 pcistate) 2341 break; 2342 DELAY(10); 2343 } 2344 2345 /* Enable memory arbiter. */ 2346 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2347 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2348 } 2349 2350 /* Fix up byte swapping */ 2351 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2352 2353 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2354 2355 DELAY(10000); 2356 } 2357 2358 /* 2359 * Frame reception handling. This is called if there's a frame 2360 * on the receive return list. 2361 * 2362 * Note: we have to be able to handle two possibilities here: 2363 * 1) the frame is from the jumbo recieve ring 2364 * 2) the frame is from the standard receive ring 2365 */ 2366 2367 void 2368 bge_rxeof(sc) 2369 struct bge_softc *sc; 2370 { 2371 struct ifnet *ifp; 2372 int stdcnt = 0, jumbocnt = 0; 2373 int have_tag = 0; 2374 u_int16_t vlan_tag = 0; 2375 bus_dmamap_t dmamap; 2376 bus_addr_t offset, toff; 2377 bus_size_t tlen; 2378 int tosync; 2379 2380 ifp = &sc->ethercom.ec_if; 2381 2382 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2383 offsetof(struct bge_ring_data, bge_status_block), 2384 sizeof (struct bge_status_block), 2385 BUS_DMASYNC_POSTREAD); 2386 2387 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2388 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2389 sc->bge_rx_saved_considx; 2390 2391 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2392 2393 if (tosync < 0) { 2394 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2395 sizeof (struct bge_rx_bd); 2396 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2397 toff, tlen, BUS_DMASYNC_POSTREAD); 2398 tosync = -tosync; 2399 } 2400 2401 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2402 offset, tosync * sizeof (struct bge_rx_bd), 2403 BUS_DMASYNC_POSTREAD); 2404 2405 while(sc->bge_rx_saved_considx != 2406 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2407 struct bge_rx_bd *cur_rx; 2408 u_int32_t rxidx; 2409 struct mbuf *m = NULL; 2410 2411 cur_rx = &sc->bge_rdata-> 2412 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2413 2414 rxidx = cur_rx->bge_idx; 2415 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2416 2417 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2418 have_tag = 1; 2419 vlan_tag = cur_rx->bge_vlan_tag; 2420 } 2421 2422 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2423 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2424 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2425 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2426 jumbocnt++; 2427 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2428 ifp->if_ierrors++; 2429 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2430 continue; 2431 } 2432 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2433 NULL)== ENOBUFS) { 2434 ifp->if_ierrors++; 2435 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2436 continue; 2437 } 2438 } else { 2439 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2440 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2441 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2442 stdcnt++; 2443 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2444 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2445 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2446 ifp->if_ierrors++; 2447 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2448 continue; 2449 } 2450 if (bge_newbuf_std(sc, sc->bge_std, 2451 NULL, dmamap) == ENOBUFS) { 2452 ifp->if_ierrors++; 2453 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2454 continue; 2455 } 2456 } 2457 2458 ifp->if_ipackets++; 2459 #ifndef __NO_STRICT_ALIGNMENT 2460 /* 2461 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2462 * the Rx buffer has the layer-2 header unaligned. 2463 * If our CPU requires alignment, re-align by copying. 2464 */ 2465 if (sc->bge_rx_alignment_bug) { 2466 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2467 cur_rx->bge_len); 2468 m->m_data += ETHER_ALIGN; 2469 } 2470 #endif 2471 2472 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2473 m->m_pkthdr.rcvif = ifp; 2474 2475 #if NBPFILTER > 0 2476 /* 2477 * Handle BPF listeners. Let the BPF user see the packet. 2478 */ 2479 if (ifp->if_bpf) 2480 bpf_mtap(ifp->if_bpf, m); 2481 #endif 2482 2483 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2484 2485 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2486 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2487 /* 2488 * Rx transport checksum-offload may also 2489 * have bugs with packets which, when transmitted, 2490 * were `runts' requiring padding. 2491 */ 2492 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2493 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2494 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2495 m->m_pkthdr.csum_data = 2496 cur_rx->bge_tcp_udp_csum; 2497 m->m_pkthdr.csum_flags |= 2498 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2499 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2500 } 2501 2502 /* 2503 * If we received a packet with a vlan tag, pass it 2504 * to vlan_input() instead of ether_input(). 2505 */ 2506 if (have_tag) { 2507 struct m_tag *mtag; 2508 2509 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2510 M_NOWAIT); 2511 if (mtag != NULL) { 2512 *(u_int *)(mtag + 1) = vlan_tag; 2513 m_tag_prepend(m, mtag); 2514 have_tag = vlan_tag = 0; 2515 } else { 2516 printf("%s: no mbuf for tag\n", ifp->if_xname); 2517 m_freem(m); 2518 have_tag = vlan_tag = 0; 2519 continue; 2520 } 2521 } 2522 (*ifp->if_input)(ifp, m); 2523 } 2524 2525 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2526 if (stdcnt) 2527 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2528 if (jumbocnt) 2529 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2530 } 2531 2532 void 2533 bge_txeof(sc) 2534 struct bge_softc *sc; 2535 { 2536 struct bge_tx_bd *cur_tx = NULL; 2537 struct ifnet *ifp; 2538 struct txdmamap_pool_entry *dma; 2539 bus_addr_t offset, toff; 2540 bus_size_t tlen; 2541 int tosync; 2542 struct mbuf *m; 2543 2544 ifp = &sc->ethercom.ec_if; 2545 2546 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2547 offsetof(struct bge_ring_data, bge_status_block), 2548 sizeof (struct bge_status_block), 2549 BUS_DMASYNC_POSTREAD); 2550 2551 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2552 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2553 sc->bge_tx_saved_considx; 2554 2555 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2556 2557 if (tosync < 0) { 2558 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2559 sizeof (struct bge_tx_bd); 2560 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2561 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2562 tosync = -tosync; 2563 } 2564 2565 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2566 offset, tosync * sizeof (struct bge_tx_bd), 2567 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2568 2569 /* 2570 * Go through our tx ring and free mbufs for those 2571 * frames that have been sent. 2572 */ 2573 while (sc->bge_tx_saved_considx != 2574 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2575 u_int32_t idx = 0; 2576 2577 idx = sc->bge_tx_saved_considx; 2578 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2579 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2580 ifp->if_opackets++; 2581 m = sc->bge_cdata.bge_tx_chain[idx]; 2582 if (m != NULL) { 2583 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2584 dma = sc->txdma[idx]; 2585 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2586 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2587 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2588 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2589 sc->txdma[idx] = NULL; 2590 2591 m_freem(m); 2592 } 2593 sc->bge_txcnt--; 2594 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2595 ifp->if_timer = 0; 2596 } 2597 2598 if (cur_tx != NULL) 2599 ifp->if_flags &= ~IFF_OACTIVE; 2600 } 2601 2602 int 2603 bge_intr(xsc) 2604 void *xsc; 2605 { 2606 struct bge_softc *sc; 2607 struct ifnet *ifp; 2608 2609 sc = xsc; 2610 ifp = &sc->ethercom.ec_if; 2611 2612 #ifdef notdef 2613 /* Avoid this for now -- checking this register is expensive. */ 2614 /* Make sure this is really our interrupt. */ 2615 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2616 return (0); 2617 #endif 2618 /* Ack interrupt and stop others from occuring. */ 2619 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2620 2621 /* 2622 * Process link state changes. 2623 * Grrr. The link status word in the status block does 2624 * not work correctly on the BCM5700 rev AX and BX chips, 2625 * according to all avaibable information. Hence, we have 2626 * to enable MII interrupts in order to properly obtain 2627 * async link changes. Unfortunately, this also means that 2628 * we have to read the MAC status register to detect link 2629 * changes, thereby adding an additional register access to 2630 * the interrupt handler. 2631 */ 2632 2633 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2634 u_int32_t status; 2635 2636 status = CSR_READ_4(sc, BGE_MAC_STS); 2637 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2638 sc->bge_link = 0; 2639 callout_stop(&sc->bge_timeout); 2640 bge_tick(sc); 2641 /* Clear the interrupt */ 2642 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2643 BGE_EVTENB_MI_INTERRUPT); 2644 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2645 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2646 BRGPHY_INTRS); 2647 } 2648 } else { 2649 if (sc->bge_rdata->bge_status_block.bge_status & 2650 BGE_STATFLAG_LINKSTATE_CHANGED) { 2651 sc->bge_link = 0; 2652 callout_stop(&sc->bge_timeout); 2653 bge_tick(sc); 2654 /* Clear the interrupt */ 2655 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2656 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2657 BGE_MACSTAT_LINK_CHANGED); 2658 } 2659 } 2660 2661 if (ifp->if_flags & IFF_RUNNING) { 2662 /* Check RX return ring producer/consumer */ 2663 bge_rxeof(sc); 2664 2665 /* Check TX ring producer/consumer */ 2666 bge_txeof(sc); 2667 } 2668 2669 bge_handle_events(sc); 2670 2671 /* Re-enable interrupts. */ 2672 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2673 2674 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2675 bge_start(ifp); 2676 2677 return (1); 2678 } 2679 2680 void 2681 bge_tick(xsc) 2682 void *xsc; 2683 { 2684 struct bge_softc *sc = xsc; 2685 struct mii_data *mii = &sc->bge_mii; 2686 struct ifmedia *ifm = NULL; 2687 struct ifnet *ifp = &sc->ethercom.ec_if; 2688 int s; 2689 2690 s = splnet(); 2691 2692 bge_stats_update(sc); 2693 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2694 if (sc->bge_link) { 2695 splx(s); 2696 return; 2697 } 2698 2699 if (sc->bge_tbi) { 2700 ifm = &sc->bge_ifmedia; 2701 if (CSR_READ_4(sc, BGE_MAC_STS) & 2702 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2703 sc->bge_link++; 2704 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2705 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2706 bge_start(ifp); 2707 } 2708 splx(s); 2709 return; 2710 } 2711 2712 mii_tick(mii); 2713 2714 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2715 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2716 sc->bge_link++; 2717 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2718 bge_start(ifp); 2719 } 2720 2721 splx(s); 2722 } 2723 2724 void 2725 bge_stats_update(sc) 2726 struct bge_softc *sc; 2727 { 2728 struct ifnet *ifp = &sc->ethercom.ec_if; 2729 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2730 bus_size_t rstats = BGE_RX_STATS; 2731 2732 #define READ_RSTAT(sc, stats, stat) \ 2733 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 2734 2735 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2736 ifp->if_collisions += 2737 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 2738 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 2739 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 2740 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 2741 return; 2742 } 2743 2744 #undef READ_RSTAT 2745 #define READ_STAT(sc, stats, stat) \ 2746 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2747 2748 ifp->if_collisions += 2749 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2750 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2751 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2752 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2753 ifp->if_collisions; 2754 2755 #undef READ_STAT 2756 2757 #ifdef notdef 2758 ifp->if_collisions += 2759 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2760 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2761 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2762 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2763 ifp->if_collisions; 2764 #endif 2765 } 2766 2767 /* 2768 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2769 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2770 * but when such padded frames employ the bge IP/TCP checksum offload, 2771 * the hardware checksum assist gives incorrect results (possibly 2772 * from incorporating its own padding into the UDP/TCP checksum; who knows). 2773 * If we pad such runts with zeros, the onboard checksum comes out correct. 2774 */ 2775 static __inline int 2776 bge_cksum_pad(struct mbuf *pkt) 2777 { 2778 struct mbuf *last = NULL; 2779 int padlen; 2780 2781 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 2782 2783 /* if there's only the packet-header and we can pad there, use it. */ 2784 if (pkt->m_pkthdr.len == pkt->m_len && 2785 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 2786 last = pkt; 2787 } else { 2788 /* 2789 * Walk packet chain to find last mbuf. We will either 2790 * pad there, or append a new mbuf and pad it 2791 * (thus perhaps avoiding the bcm5700 dma-min bug). 2792 */ 2793 for (last = pkt; last->m_next != NULL; last = last->m_next) { 2794 (void) 0; /* do nothing*/ 2795 } 2796 2797 /* `last' now points to last in chain. */ 2798 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 2799 (void) 0; /* we can pad here, in-place. */ 2800 } else { 2801 /* Allocate new empty mbuf, pad it. Compact later. */ 2802 struct mbuf *n; 2803 MGET(n, M_DONTWAIT, MT_DATA); 2804 n->m_len = 0; 2805 last->m_next = n; 2806 last = n; 2807 } 2808 } 2809 2810 #ifdef DEBUG 2811 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 2812 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 2813 #endif 2814 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 2815 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 2816 last->m_len += padlen; 2817 pkt->m_pkthdr.len += padlen; 2818 return 0; 2819 } 2820 2821 /* 2822 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 2823 */ 2824 static __inline int 2825 bge_compact_dma_runt(struct mbuf *pkt) 2826 { 2827 struct mbuf *m, *prev; 2828 int totlen, prevlen; 2829 2830 prev = NULL; 2831 totlen = 0; 2832 prevlen = -1; 2833 2834 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 2835 int mlen = m->m_len; 2836 int shortfall = 8 - mlen ; 2837 2838 totlen += mlen; 2839 if (mlen == 0) { 2840 continue; 2841 } 2842 if (mlen >= 8) 2843 continue; 2844 2845 /* If we get here, mbuf data is too small for DMA engine. 2846 * Try to fix by shuffling data to prev or next in chain. 2847 * If that fails, do a compacting deep-copy of the whole chain. 2848 */ 2849 2850 /* Internal frag. If fits in prev, copy it there. */ 2851 if (prev && !M_READONLY(prev) && 2852 M_TRAILINGSPACE(prev) >= m->m_len) { 2853 bcopy(m->m_data, 2854 prev->m_data+prev->m_len, 2855 mlen); 2856 prev->m_len += mlen; 2857 m->m_len = 0; 2858 /* XXX stitch chain */ 2859 prev->m_next = m_free(m); 2860 m = prev; 2861 continue; 2862 } 2863 else if (m->m_next != NULL && !M_READONLY(m) && 2864 M_TRAILINGSPACE(m) >= shortfall && 2865 m->m_next->m_len >= (8 + shortfall)) { 2866 /* m is writable and have enough data in next, pull up. */ 2867 2868 bcopy(m->m_next->m_data, 2869 m->m_data+m->m_len, 2870 shortfall); 2871 m->m_len += shortfall; 2872 m->m_next->m_len -= shortfall; 2873 m->m_next->m_data += shortfall; 2874 } 2875 else if (m->m_next == NULL || 1) { 2876 /* Got a runt at the very end of the packet. 2877 * borrow data from the tail of the preceding mbuf and 2878 * update its length in-place. (The original data is still 2879 * valid, so we can do this even if prev is not writable.) 2880 */ 2881 2882 /* if we'd make prev a runt, just move all of its data. */ 2883 #ifdef DEBUG 2884 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 2885 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 2886 #endif 2887 if ((prev->m_len - shortfall) < 8) 2888 shortfall = prev->m_len; 2889 2890 #ifdef notyet /* just do the safe slow thing for now */ 2891 if (!M_READONLY(m)) { 2892 if (M_LEADINGSPACE(m) < shorfall) { 2893 void *m_dat; 2894 m_dat = (m->m_flags & M_PKTHDR) ? 2895 m->m_pktdat : m->dat; 2896 memmove(m_dat, mtod(m, void*), m->m_len); 2897 m->m_data = m_dat; 2898 } 2899 } else 2900 #endif /* just do the safe slow thing */ 2901 { 2902 struct mbuf * n = NULL; 2903 int newprevlen = prev->m_len - shortfall; 2904 2905 MGET(n, M_NOWAIT, MT_DATA); 2906 if (n == NULL) 2907 return ENOBUFS; 2908 KASSERT(m->m_len + shortfall < MLEN 2909 /*, 2910 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 2911 2912 /* first copy the data we're stealing from prev */ 2913 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 2914 2915 /* update prev->m_len accordingly */ 2916 prev->m_len -= shortfall; 2917 2918 /* copy data from runt m */ 2919 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 2920 2921 /* n holds what we stole from prev, plus m */ 2922 n->m_len = shortfall + m->m_len; 2923 2924 /* stitch n into chain and free m */ 2925 n->m_next = m->m_next; 2926 prev->m_next = n; 2927 /* KASSERT(m->m_next == NULL); */ 2928 m->m_next = NULL; 2929 m_free(m); 2930 m = n; /* for continuing loop */ 2931 } 2932 } 2933 prevlen = m->m_len; 2934 } 2935 return 0; 2936 } 2937 2938 /* 2939 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2940 * pointers to descriptors. 2941 */ 2942 int 2943 bge_encap(sc, m_head, txidx) 2944 struct bge_softc *sc; 2945 struct mbuf *m_head; 2946 u_int32_t *txidx; 2947 { 2948 struct bge_tx_bd *f = NULL; 2949 u_int32_t frag, cur, cnt = 0; 2950 u_int16_t csum_flags = 0; 2951 struct txdmamap_pool_entry *dma; 2952 bus_dmamap_t dmamap; 2953 int i = 0; 2954 struct m_tag *mtag; 2955 2956 cur = frag = *txidx; 2957 2958 if (m_head->m_pkthdr.csum_flags) { 2959 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2960 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2961 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2962 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2963 } 2964 2965 /* 2966 * If we were asked to do an outboard checksum, and the NIC 2967 * has the bug where it sometimes adds in the Ethernet padding, 2968 * explicitly pad with zeros so the cksum will be correct either way. 2969 * (For now, do this for all chip versions, until newer 2970 * are confirmed to not require the workaround.) 2971 */ 2972 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 2973 #ifdef notyet 2974 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 2975 #endif 2976 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 2977 goto check_dma_bug; 2978 2979 if (bge_cksum_pad(m_head) != 0) 2980 return ENOBUFS; 2981 2982 check_dma_bug: 2983 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 2984 goto doit; 2985 /* 2986 * bcm5700 Revision B silicon cannot handle DMA descriptors with 2987 * less than eight bytes. If we encounter a teeny mbuf 2988 * at the end of a chain, we can pad. Otherwise, copy. 2989 */ 2990 if (bge_compact_dma_runt(m_head) != 0) 2991 return ENOBUFS; 2992 2993 doit: 2994 dma = SLIST_FIRST(&sc->txdma_list); 2995 if (dma == NULL) 2996 return ENOBUFS; 2997 dmamap = dma->dmamap; 2998 2999 /* 3000 * Start packing the mbufs in this chain into 3001 * the fragment pointers. Stop when we run out 3002 * of fragments or hit the end of the mbuf chain. 3003 */ 3004 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3005 BUS_DMA_NOWAIT)) 3006 return(ENOBUFS); 3007 3008 mtag = sc->ethercom.ec_nvlans ? 3009 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3010 3011 for (i = 0; i < dmamap->dm_nsegs; i++) { 3012 f = &sc->bge_rdata->bge_tx_ring[frag]; 3013 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3014 break; 3015 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3016 f->bge_len = dmamap->dm_segs[i].ds_len; 3017 f->bge_flags = csum_flags; 3018 3019 if (mtag != NULL) { 3020 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3021 f->bge_vlan_tag = *(u_int *)(mtag + 1); 3022 } else { 3023 f->bge_vlan_tag = 0; 3024 } 3025 /* 3026 * Sanity check: avoid coming within 16 descriptors 3027 * of the end of the ring. 3028 */ 3029 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3030 return(ENOBUFS); 3031 cur = frag; 3032 BGE_INC(frag, BGE_TX_RING_CNT); 3033 cnt++; 3034 } 3035 3036 if (i < dmamap->dm_nsegs) 3037 return ENOBUFS; 3038 3039 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3040 BUS_DMASYNC_PREWRITE); 3041 3042 if (frag == sc->bge_tx_saved_considx) 3043 return(ENOBUFS); 3044 3045 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3046 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3047 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3048 sc->txdma[cur] = dma; 3049 sc->bge_txcnt += cnt; 3050 3051 *txidx = frag; 3052 3053 return(0); 3054 } 3055 3056 /* 3057 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3058 * to the mbuf data regions directly in the transmit descriptors. 3059 */ 3060 void 3061 bge_start(ifp) 3062 struct ifnet *ifp; 3063 { 3064 struct bge_softc *sc; 3065 struct mbuf *m_head = NULL; 3066 u_int32_t prodidx = 0; 3067 int pkts = 0; 3068 3069 sc = ifp->if_softc; 3070 3071 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3072 return; 3073 3074 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3075 3076 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3077 IFQ_POLL(&ifp->if_snd, m_head); 3078 if (m_head == NULL) 3079 break; 3080 3081 #if 0 3082 /* 3083 * XXX 3084 * safety overkill. If this is a fragmented packet chain 3085 * with delayed TCP/UDP checksums, then only encapsulate 3086 * it if we have enough descriptors to handle the entire 3087 * chain at once. 3088 * (paranoia -- may not actually be needed) 3089 */ 3090 if (m_head->m_flags & M_FIRSTFRAG && 3091 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3092 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3093 m_head->m_pkthdr.csum_data + 16) { 3094 ifp->if_flags |= IFF_OACTIVE; 3095 break; 3096 } 3097 } 3098 #endif 3099 3100 /* 3101 * Pack the data into the transmit ring. If we 3102 * don't have room, set the OACTIVE flag and wait 3103 * for the NIC to drain the ring. 3104 */ 3105 if (bge_encap(sc, m_head, &prodidx)) { 3106 ifp->if_flags |= IFF_OACTIVE; 3107 break; 3108 } 3109 3110 /* now we are committed to transmit the packet */ 3111 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3112 pkts++; 3113 3114 #if NBPFILTER > 0 3115 /* 3116 * If there's a BPF listener, bounce a copy of this frame 3117 * to him. 3118 */ 3119 if (ifp->if_bpf) 3120 bpf_mtap(ifp->if_bpf, m_head); 3121 #endif 3122 } 3123 if (pkts == 0) 3124 return; 3125 3126 /* Transmit */ 3127 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3128 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3129 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3130 3131 /* 3132 * Set a timeout in case the chip goes out to lunch. 3133 */ 3134 ifp->if_timer = 5; 3135 } 3136 3137 int 3138 bge_init(ifp) 3139 struct ifnet *ifp; 3140 { 3141 struct bge_softc *sc = ifp->if_softc; 3142 u_int16_t *m; 3143 int s, error; 3144 3145 s = splnet(); 3146 3147 ifp = &sc->ethercom.ec_if; 3148 3149 /* Cancel pending I/O and flush buffers. */ 3150 bge_stop(sc); 3151 bge_reset(sc); 3152 bge_chipinit(sc); 3153 3154 /* 3155 * Init the various state machines, ring 3156 * control blocks and firmware. 3157 */ 3158 error = bge_blockinit(sc); 3159 if (error != 0) { 3160 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3161 error); 3162 splx(s); 3163 return error; 3164 } 3165 3166 ifp = &sc->ethercom.ec_if; 3167 3168 /* Specify MTU. */ 3169 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3170 ETHER_HDR_LEN + ETHER_CRC_LEN); 3171 3172 /* Load our MAC address. */ 3173 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3174 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3175 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3176 3177 /* Enable or disable promiscuous mode as needed. */ 3178 if (ifp->if_flags & IFF_PROMISC) { 3179 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3180 } else { 3181 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3182 } 3183 3184 /* Program multicast filter. */ 3185 bge_setmulti(sc); 3186 3187 /* Init RX ring. */ 3188 bge_init_rx_ring_std(sc); 3189 3190 /* Init jumbo RX ring. */ 3191 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3192 bge_init_rx_ring_jumbo(sc); 3193 3194 /* Init our RX return ring index */ 3195 sc->bge_rx_saved_considx = 0; 3196 3197 /* Init TX ring. */ 3198 bge_init_tx_ring(sc); 3199 3200 /* Turn on transmitter */ 3201 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3202 3203 /* Turn on receiver */ 3204 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3205 3206 /* Tell firmware we're alive. */ 3207 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3208 3209 /* Enable host interrupts. */ 3210 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3211 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3212 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3213 3214 bge_ifmedia_upd(ifp); 3215 3216 ifp->if_flags |= IFF_RUNNING; 3217 ifp->if_flags &= ~IFF_OACTIVE; 3218 3219 splx(s); 3220 3221 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3222 3223 return 0; 3224 } 3225 3226 /* 3227 * Set media options. 3228 */ 3229 int 3230 bge_ifmedia_upd(ifp) 3231 struct ifnet *ifp; 3232 { 3233 struct bge_softc *sc = ifp->if_softc; 3234 struct mii_data *mii = &sc->bge_mii; 3235 struct ifmedia *ifm = &sc->bge_ifmedia; 3236 3237 /* If this is a 1000baseX NIC, enable the TBI port. */ 3238 if (sc->bge_tbi) { 3239 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3240 return(EINVAL); 3241 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3242 case IFM_AUTO: 3243 break; 3244 case IFM_1000_SX: 3245 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3246 BGE_CLRBIT(sc, BGE_MAC_MODE, 3247 BGE_MACMODE_HALF_DUPLEX); 3248 } else { 3249 BGE_SETBIT(sc, BGE_MAC_MODE, 3250 BGE_MACMODE_HALF_DUPLEX); 3251 } 3252 break; 3253 default: 3254 return(EINVAL); 3255 } 3256 return(0); 3257 } 3258 3259 sc->bge_link = 0; 3260 mii_mediachg(mii); 3261 3262 return(0); 3263 } 3264 3265 /* 3266 * Report current media status. 3267 */ 3268 void 3269 bge_ifmedia_sts(ifp, ifmr) 3270 struct ifnet *ifp; 3271 struct ifmediareq *ifmr; 3272 { 3273 struct bge_softc *sc = ifp->if_softc; 3274 struct mii_data *mii = &sc->bge_mii; 3275 3276 if (sc->bge_tbi) { 3277 ifmr->ifm_status = IFM_AVALID; 3278 ifmr->ifm_active = IFM_ETHER; 3279 if (CSR_READ_4(sc, BGE_MAC_STS) & 3280 BGE_MACSTAT_TBI_PCS_SYNCHED) 3281 ifmr->ifm_status |= IFM_ACTIVE; 3282 ifmr->ifm_active |= IFM_1000_SX; 3283 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3284 ifmr->ifm_active |= IFM_HDX; 3285 else 3286 ifmr->ifm_active |= IFM_FDX; 3287 return; 3288 } 3289 3290 mii_pollstat(mii); 3291 ifmr->ifm_active = mii->mii_media_active; 3292 ifmr->ifm_status = mii->mii_media_status; 3293 } 3294 3295 int 3296 bge_ioctl(ifp, command, data) 3297 struct ifnet *ifp; 3298 u_long command; 3299 caddr_t data; 3300 { 3301 struct bge_softc *sc = ifp->if_softc; 3302 struct ifreq *ifr = (struct ifreq *) data; 3303 int s, error = 0; 3304 struct mii_data *mii; 3305 3306 s = splnet(); 3307 3308 switch(command) { 3309 case SIOCSIFFLAGS: 3310 if (ifp->if_flags & IFF_UP) { 3311 /* 3312 * If only the state of the PROMISC flag changed, 3313 * then just use the 'set promisc mode' command 3314 * instead of reinitializing the entire NIC. Doing 3315 * a full re-init means reloading the firmware and 3316 * waiting for it to start up, which may take a 3317 * second or two. 3318 */ 3319 if (ifp->if_flags & IFF_RUNNING && 3320 ifp->if_flags & IFF_PROMISC && 3321 !(sc->bge_if_flags & IFF_PROMISC)) { 3322 BGE_SETBIT(sc, BGE_RX_MODE, 3323 BGE_RXMODE_RX_PROMISC); 3324 } else if (ifp->if_flags & IFF_RUNNING && 3325 !(ifp->if_flags & IFF_PROMISC) && 3326 sc->bge_if_flags & IFF_PROMISC) { 3327 BGE_CLRBIT(sc, BGE_RX_MODE, 3328 BGE_RXMODE_RX_PROMISC); 3329 } else 3330 bge_init(ifp); 3331 } else { 3332 if (ifp->if_flags & IFF_RUNNING) { 3333 bge_stop(sc); 3334 } 3335 } 3336 sc->bge_if_flags = ifp->if_flags; 3337 error = 0; 3338 break; 3339 case SIOCSIFMEDIA: 3340 case SIOCGIFMEDIA: 3341 if (sc->bge_tbi) { 3342 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3343 command); 3344 } else { 3345 mii = &sc->bge_mii; 3346 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3347 command); 3348 } 3349 error = 0; 3350 break; 3351 default: 3352 error = ether_ioctl(ifp, command, data); 3353 if (error == ENETRESET) { 3354 bge_setmulti(sc); 3355 error = 0; 3356 } 3357 break; 3358 } 3359 3360 splx(s); 3361 3362 return(error); 3363 } 3364 3365 void 3366 bge_watchdog(ifp) 3367 struct ifnet *ifp; 3368 { 3369 struct bge_softc *sc; 3370 3371 sc = ifp->if_softc; 3372 3373 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3374 3375 ifp->if_flags &= ~IFF_RUNNING; 3376 bge_init(ifp); 3377 3378 ifp->if_oerrors++; 3379 } 3380 3381 static void 3382 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3383 { 3384 int i; 3385 3386 BGE_CLRBIT(sc, reg, bit); 3387 3388 for (i = 0; i < BGE_TIMEOUT; i++) { 3389 if ((CSR_READ_4(sc, reg) & bit) == 0) 3390 return; 3391 delay(100); 3392 } 3393 3394 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3395 sc->bge_dev.dv_xname, (u_long) reg, bit); 3396 } 3397 3398 /* 3399 * Stop the adapter and free any mbufs allocated to the 3400 * RX and TX lists. 3401 */ 3402 void 3403 bge_stop(sc) 3404 struct bge_softc *sc; 3405 { 3406 struct ifnet *ifp = &sc->ethercom.ec_if; 3407 3408 callout_stop(&sc->bge_timeout); 3409 3410 /* 3411 * Disable all of the receiver blocks 3412 */ 3413 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3414 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3415 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3416 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3417 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3418 } 3419 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3420 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3421 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3422 3423 /* 3424 * Disable all of the transmit blocks 3425 */ 3426 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3427 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3428 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3429 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3430 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3431 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3432 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3433 } 3434 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3435 3436 /* 3437 * Shut down all of the memory managers and related 3438 * state machines. 3439 */ 3440 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3441 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3442 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3443 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3444 } 3445 3446 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3447 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3448 3449 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3450 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3451 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3452 } 3453 3454 /* Disable host interrupts. */ 3455 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3456 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3457 3458 /* 3459 * Tell firmware we're shutting down. 3460 */ 3461 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3462 3463 /* Free the RX lists. */ 3464 bge_free_rx_ring_std(sc); 3465 3466 /* Free jumbo RX list. */ 3467 bge_free_rx_ring_jumbo(sc); 3468 3469 /* Free TX buffers. */ 3470 bge_free_tx_ring(sc); 3471 3472 /* 3473 * Isolate/power down the PHY. 3474 */ 3475 if (!sc->bge_tbi) 3476 mii_down(&sc->bge_mii); 3477 3478 sc->bge_link = 0; 3479 3480 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3481 3482 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3483 } 3484 3485 /* 3486 * Stop all chip I/O so that the kernel's probe routines don't 3487 * get confused by errant DMAs when rebooting. 3488 */ 3489 void 3490 bge_shutdown(xsc) 3491 void *xsc; 3492 { 3493 struct bge_softc *sc = (struct bge_softc *)xsc; 3494 3495 bge_stop(sc); 3496 bge_reset(sc); 3497 } 3498
Indexes created Wed Sep 24 22:09:59 GMT 2025