if_bge.c revision 1.51
1 /* $NetBSD: if_bge.c,v 1.51 2003/10/23 17:41:59 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.51 2003/10/23 17:41:59 fvdl Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/miidevs.h> 120 #include <dev/mii/brgphyreg.h> 121 122 #include <dev/pci/if_bgereg.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 127 128 int bge_probe(struct device *, struct cfdata *, void *); 129 void bge_attach(struct device *, struct device *, void *); 130 void bge_release_resources(struct bge_softc *); 131 void bge_txeof(struct bge_softc *); 132 void bge_rxeof(struct bge_softc *); 133 134 void bge_tick(void *); 135 void bge_stats_update(struct bge_softc *); 136 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 137 static __inline int bge_cksum_pad(struct mbuf *pkt); 138 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 139 140 int bge_intr(void *); 141 void bge_start(struct ifnet *); 142 int bge_ioctl(struct ifnet *, u_long, caddr_t); 143 int bge_init(struct ifnet *); 144 void bge_stop(struct bge_softc *); 145 void bge_watchdog(struct ifnet *); 146 void bge_shutdown(void *); 147 int bge_ifmedia_upd(struct ifnet *); 148 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 149 150 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 151 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 152 153 void bge_setmulti(struct bge_softc *); 154 155 void bge_handle_events(struct bge_softc *); 156 int bge_alloc_jumbo_mem(struct bge_softc *); 157 void bge_free_jumbo_mem(struct bge_softc *); 158 void *bge_jalloc(struct bge_softc *); 159 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 160 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 161 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 162 int bge_init_rx_ring_std(struct bge_softc *); 163 void bge_free_rx_ring_std(struct bge_softc *); 164 int bge_init_rx_ring_jumbo(struct bge_softc *); 165 void bge_free_rx_ring_jumbo(struct bge_softc *); 166 void bge_free_tx_ring(struct bge_softc *); 167 int bge_init_tx_ring(struct bge_softc *); 168 169 int bge_chipinit(struct bge_softc *); 170 int bge_blockinit(struct bge_softc *); 171 int bge_setpowerstate(struct bge_softc *, int); 172 173 #ifdef notdef 174 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 175 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 176 void bge_vpd_read(struct bge_softc *); 177 #endif 178 179 u_int32_t bge_readmem_ind(struct bge_softc *, int); 180 void bge_writemem_ind(struct bge_softc *, int, int); 181 #ifdef notdef 182 u_int32_t bge_readreg_ind(struct bge_softc *, int); 183 #endif 184 void bge_writereg_ind(struct bge_softc *, int, int); 185 186 int bge_miibus_readreg(struct device *, int, int); 187 void bge_miibus_writereg(struct device *, int, int, int); 188 void bge_miibus_statchg(struct device *); 189 190 void bge_reset(struct bge_softc *); 191 192 void bge_dump_status(struct bge_softc *); 193 void bge_dump_rxbd(struct bge_rx_bd *); 194 195 #define BGE_DEBUG 196 #ifdef BGE_DEBUG 197 #define DPRINTF(x) if (bgedebug) printf x 198 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 199 int bgedebug = 0; 200 #else 201 #define DPRINTF(x) 202 #define DPRINTFN(n,x) 203 #endif 204 205 /* Various chip quirks. */ 206 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 207 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 208 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 209 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 210 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 211 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 212 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 213 #define BGE_QUIRK_5705_CORE 0x00000080 214 215 /* following bugs are common to bcm5700 rev B, all flavours */ 216 #define BGE_QUIRK_5700_COMMON \ 217 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 218 219 CFATTACH_DECL(bge, sizeof(struct bge_softc), 220 bge_probe, bge_attach, NULL, NULL); 221 222 u_int32_t 223 bge_readmem_ind(sc, off) 224 struct bge_softc *sc; 225 int off; 226 { 227 struct pci_attach_args *pa = &(sc->bge_pa); 228 pcireg_t val; 229 230 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 231 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 232 return val; 233 } 234 235 void 236 bge_writemem_ind(sc, off, val) 237 struct bge_softc *sc; 238 int off, val; 239 { 240 struct pci_attach_args *pa = &(sc->bge_pa); 241 242 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 243 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 244 } 245 246 #ifdef notdef 247 u_int32_t 248 bge_readreg_ind(sc, off) 249 struct bge_softc *sc; 250 int off; 251 { 252 struct pci_attach_args *pa = &(sc->bge_pa); 253 254 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 255 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 256 } 257 #endif 258 259 void 260 bge_writereg_ind(sc, off, val) 261 struct bge_softc *sc; 262 int off, val; 263 { 264 struct pci_attach_args *pa = &(sc->bge_pa); 265 266 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 267 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 268 } 269 270 #ifdef notdef 271 u_int8_t 272 bge_vpd_readbyte(sc, addr) 273 struct bge_softc *sc; 274 int addr; 275 { 276 int i; 277 u_int32_t val; 278 struct pci_attach_args *pa = &(sc->bge_pa); 279 280 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 281 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 282 DELAY(10); 283 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 284 BGE_VPD_FLAG) 285 break; 286 } 287 288 if (i == BGE_TIMEOUT) { 289 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 290 return(0); 291 } 292 293 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 294 295 return((val >> ((addr % 4) * 8)) & 0xFF); 296 } 297 298 void 299 bge_vpd_read_res(sc, res, addr) 300 struct bge_softc *sc; 301 struct vpd_res *res; 302 int addr; 303 { 304 int i; 305 u_int8_t *ptr; 306 307 ptr = (u_int8_t *)res; 308 for (i = 0; i < sizeof(struct vpd_res); i++) 309 ptr[i] = bge_vpd_readbyte(sc, i + addr); 310 } 311 312 void 313 bge_vpd_read(sc) 314 struct bge_softc *sc; 315 { 316 int pos = 0, i; 317 struct vpd_res res; 318 319 if (sc->bge_vpd_prodname != NULL) 320 free(sc->bge_vpd_prodname, M_DEVBUF); 321 if (sc->bge_vpd_readonly != NULL) 322 free(sc->bge_vpd_readonly, M_DEVBUF); 323 sc->bge_vpd_prodname = NULL; 324 sc->bge_vpd_readonly = NULL; 325 326 bge_vpd_read_res(sc, &res, pos); 327 328 if (res.vr_id != VPD_RES_ID) { 329 printf("%s: bad VPD resource id: expected %x got %x\n", 330 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 331 return; 332 } 333 334 pos += sizeof(res); 335 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 336 if (sc->bge_vpd_prodname == NULL) 337 panic("bge_vpd_read"); 338 for (i = 0; i < res.vr_len; i++) 339 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 340 sc->bge_vpd_prodname[i] = '\0'; 341 pos += i; 342 343 bge_vpd_read_res(sc, &res, pos); 344 345 if (res.vr_id != VPD_RES_READ) { 346 printf("%s: bad VPD resource id: expected %x got %x\n", 347 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 348 return; 349 } 350 351 pos += sizeof(res); 352 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 353 if (sc->bge_vpd_readonly == NULL) 354 panic("bge_vpd_read"); 355 for (i = 0; i < res.vr_len + 1; i++) 356 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 357 } 358 #endif 359 360 /* 361 * Read a byte of data stored in the EEPROM at address 'addr.' The 362 * BCM570x supports both the traditional bitbang interface and an 363 * auto access interface for reading the EEPROM. We use the auto 364 * access method. 365 */ 366 u_int8_t 367 bge_eeprom_getbyte(sc, addr, dest) 368 struct bge_softc *sc; 369 int addr; 370 u_int8_t *dest; 371 { 372 int i; 373 u_int32_t byte = 0; 374 375 /* 376 * Enable use of auto EEPROM access so we can avoid 377 * having to use the bitbang method. 378 */ 379 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 380 381 /* Reset the EEPROM, load the clock period. */ 382 CSR_WRITE_4(sc, BGE_EE_ADDR, 383 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 384 DELAY(20); 385 386 /* Issue the read EEPROM command. */ 387 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 388 389 /* Wait for completion */ 390 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 391 DELAY(10); 392 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 393 break; 394 } 395 396 if (i == BGE_TIMEOUT) { 397 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 398 return(0); 399 } 400 401 /* Get result. */ 402 byte = CSR_READ_4(sc, BGE_EE_DATA); 403 404 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 405 406 return(0); 407 } 408 409 /* 410 * Read a sequence of bytes from the EEPROM. 411 */ 412 int 413 bge_read_eeprom(sc, dest, off, cnt) 414 struct bge_softc *sc; 415 caddr_t dest; 416 int off; 417 int cnt; 418 { 419 int err = 0, i; 420 u_int8_t byte = 0; 421 422 for (i = 0; i < cnt; i++) { 423 err = bge_eeprom_getbyte(sc, off + i, &byte); 424 if (err) 425 break; 426 *(dest + i) = byte; 427 } 428 429 return(err ? 1 : 0); 430 } 431 432 int 433 bge_miibus_readreg(dev, phy, reg) 434 struct device *dev; 435 int phy, reg; 436 { 437 struct bge_softc *sc = (struct bge_softc *)dev; 438 struct ifnet *ifp; 439 u_int32_t val; 440 u_int32_t saved_autopoll; 441 int i; 442 443 ifp = &sc->ethercom.ec_if; 444 445 /* 446 * Several chips with builtin PHYs will incorrectly answer to 447 * other PHY instances than the builtin PHY at id 1. 448 */ 449 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 450 return(0); 451 452 /* Reading with autopolling on may trigger PCI errors */ 453 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 454 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 455 CSR_WRITE_4(sc, BGE_MI_MODE, 456 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 457 DELAY(40); 458 } 459 460 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 461 BGE_MIPHY(phy)|BGE_MIREG(reg)); 462 463 for (i = 0; i < BGE_TIMEOUT; i++) { 464 val = CSR_READ_4(sc, BGE_MI_COMM); 465 if (!(val & BGE_MICOMM_BUSY)) 466 break; 467 delay(10); 468 } 469 470 if (i == BGE_TIMEOUT) { 471 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 472 val = 0; 473 goto done; 474 } 475 476 val = CSR_READ_4(sc, BGE_MI_COMM); 477 478 done: 479 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 480 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 481 DELAY(40); 482 } 483 484 if (val & BGE_MICOMM_READFAIL) 485 return(0); 486 487 return(val & 0xFFFF); 488 } 489 490 void 491 bge_miibus_writereg(dev, phy, reg, val) 492 struct device *dev; 493 int phy, reg, val; 494 { 495 struct bge_softc *sc = (struct bge_softc *)dev; 496 u_int32_t saved_autopoll; 497 int i; 498 499 /* Touching the PHY while autopolling is on may trigger PCI errors */ 500 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 501 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 502 delay(40); 503 CSR_WRITE_4(sc, BGE_MI_MODE, 504 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 505 delay(10); /* 40 usec is supposed to be adequate */ 506 } 507 508 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 509 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 510 511 for (i = 0; i < BGE_TIMEOUT; i++) { 512 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 513 break; 514 delay(10); 515 } 516 517 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 518 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 519 delay(40); 520 } 521 522 if (i == BGE_TIMEOUT) { 523 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 524 } 525 } 526 527 void 528 bge_miibus_statchg(dev) 529 struct device *dev; 530 { 531 struct bge_softc *sc = (struct bge_softc *)dev; 532 struct mii_data *mii = &sc->bge_mii; 533 534 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 535 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 536 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 537 } else { 538 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 539 } 540 541 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 542 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 543 } else { 544 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 545 } 546 } 547 548 /* 549 * Handle events that have triggered interrupts. 550 */ 551 void 552 bge_handle_events(sc) 553 struct bge_softc *sc; 554 { 555 556 return; 557 } 558 559 /* 560 * Memory management for jumbo frames. 561 */ 562 563 int 564 bge_alloc_jumbo_mem(sc) 565 struct bge_softc *sc; 566 { 567 caddr_t ptr, kva; 568 bus_dma_segment_t seg; 569 int i, rseg, state, error; 570 struct bge_jpool_entry *entry; 571 572 state = error = 0; 573 574 /* Grab a big chunk o' storage. */ 575 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 576 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 577 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 578 return ENOBUFS; 579 } 580 581 state = 1; 582 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 583 BUS_DMA_NOWAIT)) { 584 printf("%s: can't map DMA buffers (%d bytes)\n", 585 sc->bge_dev.dv_xname, (int)BGE_JMEM); 586 error = ENOBUFS; 587 goto out; 588 } 589 590 state = 2; 591 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 592 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 593 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 594 error = ENOBUFS; 595 goto out; 596 } 597 598 state = 3; 599 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 600 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 601 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 602 error = ENOBUFS; 603 goto out; 604 } 605 606 state = 4; 607 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 608 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 609 610 SLIST_INIT(&sc->bge_jfree_listhead); 611 SLIST_INIT(&sc->bge_jinuse_listhead); 612 613 /* 614 * Now divide it up into 9K pieces and save the addresses 615 * in an array. 616 */ 617 ptr = sc->bge_cdata.bge_jumbo_buf; 618 for (i = 0; i < BGE_JSLOTS; i++) { 619 sc->bge_cdata.bge_jslots[i] = ptr; 620 ptr += BGE_JLEN; 621 entry = malloc(sizeof(struct bge_jpool_entry), 622 M_DEVBUF, M_NOWAIT); 623 if (entry == NULL) { 624 printf("%s: no memory for jumbo buffer queue!\n", 625 sc->bge_dev.dv_xname); 626 error = ENOBUFS; 627 goto out; 628 } 629 entry->slot = i; 630 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 631 entry, jpool_entries); 632 } 633 out: 634 if (error != 0) { 635 switch (state) { 636 case 4: 637 bus_dmamap_unload(sc->bge_dmatag, 638 sc->bge_cdata.bge_rx_jumbo_map); 639 case 3: 640 bus_dmamap_destroy(sc->bge_dmatag, 641 sc->bge_cdata.bge_rx_jumbo_map); 642 case 2: 643 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 644 case 1: 645 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 646 break; 647 default: 648 break; 649 } 650 } 651 652 return error; 653 } 654 655 /* 656 * Allocate a jumbo buffer. 657 */ 658 void * 659 bge_jalloc(sc) 660 struct bge_softc *sc; 661 { 662 struct bge_jpool_entry *entry; 663 664 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 665 666 if (entry == NULL) { 667 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 668 return(NULL); 669 } 670 671 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 672 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 673 return(sc->bge_cdata.bge_jslots[entry->slot]); 674 } 675 676 /* 677 * Release a jumbo buffer. 678 */ 679 void 680 bge_jfree(m, buf, size, arg) 681 struct mbuf *m; 682 caddr_t buf; 683 size_t size; 684 void *arg; 685 { 686 struct bge_jpool_entry *entry; 687 struct bge_softc *sc; 688 int i, s; 689 690 /* Extract the softc struct pointer. */ 691 sc = (struct bge_softc *)arg; 692 693 if (sc == NULL) 694 panic("bge_jfree: can't find softc pointer!"); 695 696 /* calculate the slot this buffer belongs to */ 697 698 i = ((caddr_t)buf 699 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 700 701 if ((i < 0) || (i >= BGE_JSLOTS)) 702 panic("bge_jfree: asked to free buffer that we don't manage!"); 703 704 s = splvm(); 705 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 706 if (entry == NULL) 707 panic("bge_jfree: buffer not in use!"); 708 entry->slot = i; 709 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 710 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 711 712 if (__predict_true(m != NULL)) 713 pool_cache_put(&mbpool_cache, m); 714 splx(s); 715 } 716 717 718 /* 719 * Intialize a standard receive ring descriptor. 720 */ 721 int 722 bge_newbuf_std(sc, i, m, dmamap) 723 struct bge_softc *sc; 724 int i; 725 struct mbuf *m; 726 bus_dmamap_t dmamap; 727 { 728 struct mbuf *m_new = NULL; 729 struct bge_rx_bd *r; 730 int error; 731 732 if (dmamap == NULL) { 733 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 734 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 735 if (error != 0) 736 return error; 737 } 738 739 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 740 741 if (m == NULL) { 742 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 743 if (m_new == NULL) { 744 return(ENOBUFS); 745 } 746 747 MCLGET(m_new, M_DONTWAIT); 748 if (!(m_new->m_flags & M_EXT)) { 749 m_freem(m_new); 750 return(ENOBUFS); 751 } 752 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 753 if (!sc->bge_rx_alignment_bug) 754 m_adj(m_new, ETHER_ALIGN); 755 756 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 757 BUS_DMA_READ|BUS_DMA_NOWAIT)) 758 return(ENOBUFS); 759 } else { 760 m_new = m; 761 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 762 m_new->m_data = m_new->m_ext.ext_buf; 763 if (!sc->bge_rx_alignment_bug) 764 m_adj(m_new, ETHER_ALIGN); 765 } 766 767 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 768 r = &sc->bge_rdata->bge_rx_std_ring[i]; 769 bge_set_hostaddr(&r->bge_addr, 770 dmamap->dm_segs[0].ds_addr); 771 r->bge_flags = BGE_RXBDFLAG_END; 772 r->bge_len = m_new->m_len; 773 r->bge_idx = i; 774 775 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 776 offsetof(struct bge_ring_data, bge_rx_std_ring) + 777 i * sizeof (struct bge_rx_bd), 778 sizeof (struct bge_rx_bd), 779 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 780 781 return(0); 782 } 783 784 /* 785 * Initialize a jumbo receive ring descriptor. This allocates 786 * a jumbo buffer from the pool managed internally by the driver. 787 */ 788 int 789 bge_newbuf_jumbo(sc, i, m) 790 struct bge_softc *sc; 791 int i; 792 struct mbuf *m; 793 { 794 struct mbuf *m_new = NULL; 795 struct bge_rx_bd *r; 796 797 if (m == NULL) { 798 caddr_t *buf = NULL; 799 800 /* Allocate the mbuf. */ 801 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 802 if (m_new == NULL) { 803 return(ENOBUFS); 804 } 805 806 /* Allocate the jumbo buffer */ 807 buf = bge_jalloc(sc); 808 if (buf == NULL) { 809 m_freem(m_new); 810 printf("%s: jumbo allocation failed " 811 "-- packet dropped!\n", sc->bge_dev.dv_xname); 812 return(ENOBUFS); 813 } 814 815 /* Attach the buffer to the mbuf. */ 816 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 817 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 818 bge_jfree, sc); 819 } else { 820 m_new = m; 821 m_new->m_data = m_new->m_ext.ext_buf; 822 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 823 } 824 825 if (!sc->bge_rx_alignment_bug) 826 m_adj(m_new, ETHER_ALIGN); 827 /* Set up the descriptor. */ 828 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 829 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 830 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 831 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 832 r->bge_len = m_new->m_len; 833 r->bge_idx = i; 834 835 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 836 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 837 i * sizeof (struct bge_rx_bd), 838 sizeof (struct bge_rx_bd), 839 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 840 841 return(0); 842 } 843 844 /* 845 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 846 * that's 1MB or memory, which is a lot. For now, we fill only the first 847 * 256 ring entries and hope that our CPU is fast enough to keep up with 848 * the NIC. 849 */ 850 int 851 bge_init_rx_ring_std(sc) 852 struct bge_softc *sc; 853 { 854 int i; 855 856 if (sc->bge_flags & BGE_RXRING_VALID) 857 return 0; 858 859 for (i = 0; i < BGE_SSLOTS; i++) { 860 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 861 return(ENOBUFS); 862 } 863 864 sc->bge_std = i - 1; 865 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 866 867 sc->bge_flags |= BGE_RXRING_VALID; 868 869 return(0); 870 } 871 872 void 873 bge_free_rx_ring_std(sc) 874 struct bge_softc *sc; 875 { 876 int i; 877 878 if (!(sc->bge_flags & BGE_RXRING_VALID)) 879 return; 880 881 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 882 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 883 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 884 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 885 bus_dmamap_destroy(sc->bge_dmatag, 886 sc->bge_cdata.bge_rx_std_map[i]); 887 } 888 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 889 sizeof(struct bge_rx_bd)); 890 } 891 892 sc->bge_flags &= ~BGE_RXRING_VALID; 893 } 894 895 int 896 bge_init_rx_ring_jumbo(sc) 897 struct bge_softc *sc; 898 { 899 int i; 900 volatile struct bge_rcb *rcb; 901 902 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 903 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 904 return(ENOBUFS); 905 }; 906 907 sc->bge_jumbo = i - 1; 908 909 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 910 rcb->bge_maxlen_flags = 0; 911 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 912 913 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 914 915 return(0); 916 } 917 918 void 919 bge_free_rx_ring_jumbo(sc) 920 struct bge_softc *sc; 921 { 922 int i; 923 924 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 925 return; 926 927 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 928 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 929 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 930 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 931 } 932 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 933 sizeof(struct bge_rx_bd)); 934 } 935 936 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 937 } 938 939 void 940 bge_free_tx_ring(sc) 941 struct bge_softc *sc; 942 { 943 int i, freed; 944 struct txdmamap_pool_entry *dma; 945 946 if (!(sc->bge_flags & BGE_TXRING_VALID)) 947 return; 948 949 freed = 0; 950 951 for (i = 0; i < BGE_TX_RING_CNT; i++) { 952 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 953 freed++; 954 m_freem(sc->bge_cdata.bge_tx_chain[i]); 955 sc->bge_cdata.bge_tx_chain[i] = NULL; 956 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 957 link); 958 sc->txdma[i] = 0; 959 } 960 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 961 sizeof(struct bge_tx_bd)); 962 } 963 964 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 965 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 966 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 967 free(dma, M_DEVBUF); 968 } 969 970 sc->bge_flags &= ~BGE_TXRING_VALID; 971 } 972 973 int 974 bge_init_tx_ring(sc) 975 struct bge_softc *sc; 976 { 977 int i; 978 bus_dmamap_t dmamap; 979 struct txdmamap_pool_entry *dma; 980 981 if (sc->bge_flags & BGE_TXRING_VALID) 982 return 0; 983 984 sc->bge_txcnt = 0; 985 sc->bge_tx_saved_considx = 0; 986 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 987 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 988 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 989 990 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 991 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 992 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 993 994 SLIST_INIT(&sc->txdma_list); 995 for (i = 0; i < BGE_RSLOTS; i++) { 996 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 997 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 998 &dmamap)) 999 return(ENOBUFS); 1000 if (dmamap == NULL) 1001 panic("dmamap NULL in bge_init_tx_ring"); 1002 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1003 if (dma == NULL) { 1004 printf("%s: can't alloc txdmamap_pool_entry\n", 1005 sc->bge_dev.dv_xname); 1006 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1007 return (ENOMEM); 1008 } 1009 dma->dmamap = dmamap; 1010 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1011 } 1012 1013 sc->bge_flags |= BGE_TXRING_VALID; 1014 1015 return(0); 1016 } 1017 1018 void 1019 bge_setmulti(sc) 1020 struct bge_softc *sc; 1021 { 1022 struct ethercom *ac = &sc->ethercom; 1023 struct ifnet *ifp = &ac->ec_if; 1024 struct ether_multi *enm; 1025 struct ether_multistep step; 1026 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1027 u_int32_t h; 1028 int i; 1029 1030 if (ifp->if_flags & IFF_PROMISC) 1031 goto allmulti; 1032 1033 /* Now program new ones. */ 1034 ETHER_FIRST_MULTI(step, ac, enm); 1035 while (enm != NULL) { 1036 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1037 /* 1038 * We must listen to a range of multicast addresses. 1039 * For now, just accept all multicasts, rather than 1040 * trying to set only those filter bits needed to match 1041 * the range. (At this time, the only use of address 1042 * ranges is for IP multicast routing, for which the 1043 * range is big enough to require all bits set.) 1044 */ 1045 goto allmulti; 1046 } 1047 1048 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1049 1050 /* Just want the 7 least-significant bits. */ 1051 h &= 0x7f; 1052 1053 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1054 ETHER_NEXT_MULTI(step, enm); 1055 } 1056 1057 ifp->if_flags &= ~IFF_ALLMULTI; 1058 goto setit; 1059 1060 allmulti: 1061 ifp->if_flags |= IFF_ALLMULTI; 1062 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1063 1064 setit: 1065 for (i = 0; i < 4; i++) 1066 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1067 } 1068 1069 const int bge_swapbits[] = { 1070 0, 1071 BGE_MODECTL_BYTESWAP_DATA, 1072 BGE_MODECTL_WORDSWAP_DATA, 1073 BGE_MODECTL_BYTESWAP_NONFRAME, 1074 BGE_MODECTL_WORDSWAP_NONFRAME, 1075 1076 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1077 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1078 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1079 1080 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1081 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1082 1083 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1084 1085 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1086 BGE_MODECTL_BYTESWAP_NONFRAME, 1087 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1088 BGE_MODECTL_WORDSWAP_NONFRAME, 1089 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1090 BGE_MODECTL_WORDSWAP_NONFRAME, 1091 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1092 BGE_MODECTL_WORDSWAP_NONFRAME, 1093 1094 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1095 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1096 }; 1097 1098 int bge_swapindex = 0; 1099 1100 /* 1101 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1102 * self-test results. 1103 */ 1104 int 1105 bge_chipinit(sc) 1106 struct bge_softc *sc; 1107 { 1108 u_int32_t cachesize; 1109 int i; 1110 u_int32_t dma_rw_ctl; 1111 struct pci_attach_args *pa = &(sc->bge_pa); 1112 1113 1114 /* Set endianness before we access any non-PCI registers. */ 1115 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1116 BGE_INIT); 1117 1118 /* Set power state to D0. */ 1119 bge_setpowerstate(sc, 0); 1120 1121 /* 1122 * Check the 'ROM failed' bit on the RX CPU to see if 1123 * self-tests passed. 1124 */ 1125 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1126 printf("%s: RX CPU self-diagnostics failed!\n", 1127 sc->bge_dev.dv_xname); 1128 return(ENODEV); 1129 } 1130 1131 /* Clear the MAC control register */ 1132 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1133 1134 /* 1135 * Clear the MAC statistics block in the NIC's 1136 * internal memory. 1137 */ 1138 for (i = BGE_STATS_BLOCK; 1139 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1140 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1141 1142 for (i = BGE_STATUS_BLOCK; 1143 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1144 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1145 1146 /* Set up the PCI DMA control register. */ 1147 if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1148 BGE_PCISTATE_PCI_BUSMODE) { 1149 /* Conventional PCI bus */ 1150 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1151 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1152 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1153 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1154 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1155 dma_rw_ctl |= 0x0F; 1156 } 1157 } else { 1158 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1159 /* PCI-X bus */ 1160 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1161 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1162 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1163 (0x0F); 1164 /* 1165 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1166 * for hardware bugs, which means we should also clear 1167 * the low-order MINDMA bits. In addition, the 5704 1168 * uses a different encoding of read/write watermarks. 1169 */ 1170 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 || 1171 sc->bge_chipid == BGE_CHIPID_BCM5704_A1 || 1172 sc->bge_chipid == BGE_CHIPID_BCM5704_A2 || 1173 sc->bge_chipid == BGE_CHIPID_BCM5704_A3) { 1174 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1175 /* should be 0x1f0000 */ 1176 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1177 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1178 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1179 } 1180 else if ((sc->bge_chipid >> 28) == 1181 (BGE_CHIPID_BCM5703_A0 >> 28)) { 1182 dma_rw_ctl &= 0xfffffff0; 1183 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1184 } 1185 } 1186 1187 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1188 1189 /* 1190 * Set up general mode register. 1191 */ 1192 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1193 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1194 BGE_MODECTL_TX_NO_PHDR_CSUM| BGE_MODECTL_RX_NO_PHDR_CSUM); 1195 1196 /* Get cache line size. */ 1197 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1198 1199 /* 1200 * Avoid violating PCI spec on certain chip revs. 1201 */ 1202 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1203 PCIM_CMD_MWIEN) { 1204 switch(cachesize) { 1205 case 1: 1206 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1207 BGE_PCI_WRITE_BNDRY_16BYTES); 1208 break; 1209 case 2: 1210 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1211 BGE_PCI_WRITE_BNDRY_32BYTES); 1212 break; 1213 case 4: 1214 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1215 BGE_PCI_WRITE_BNDRY_64BYTES); 1216 break; 1217 case 8: 1218 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1219 BGE_PCI_WRITE_BNDRY_128BYTES); 1220 break; 1221 case 16: 1222 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1223 BGE_PCI_WRITE_BNDRY_256BYTES); 1224 break; 1225 case 32: 1226 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1227 BGE_PCI_WRITE_BNDRY_512BYTES); 1228 break; 1229 case 64: 1230 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1231 BGE_PCI_WRITE_BNDRY_1024BYTES); 1232 break; 1233 default: 1234 /* Disable PCI memory write and invalidate. */ 1235 #if 0 1236 if (bootverbose) 1237 printf("%s: cache line size %d not " 1238 "supported; disabling PCI MWI\n", 1239 sc->bge_dev.dv_xname, cachesize); 1240 #endif 1241 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1242 PCIM_CMD_MWIEN); 1243 break; 1244 } 1245 } 1246 1247 /* 1248 * Disable memory write invalidate. Apparently it is not supported 1249 * properly by these devices. 1250 */ 1251 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1252 1253 1254 #ifdef __brokenalpha__ 1255 /* 1256 * Must insure that we do not cross an 8K (bytes) boundary 1257 * for DMA reads. Our highest limit is 1K bytes. This is a 1258 * restriction on some ALPHA platforms with early revision 1259 * 21174 PCI chipsets, such as the AlphaPC 164lx 1260 */ 1261 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1262 #endif 1263 1264 /* Set the timer prescaler (always 66MHz) */ 1265 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1266 1267 return(0); 1268 } 1269 1270 int 1271 bge_blockinit(sc) 1272 struct bge_softc *sc; 1273 { 1274 volatile struct bge_rcb *rcb; 1275 bus_size_t rcb_addr; 1276 int i; 1277 struct ifnet *ifp = &sc->ethercom.ec_if; 1278 bge_hostaddr taddr; 1279 1280 /* 1281 * Initialize the memory window pointer register so that 1282 * we can access the first 32K of internal NIC RAM. This will 1283 * allow us to set up the TX send ring RCBs and the RX return 1284 * ring RCBs, plus other things which live in NIC memory. 1285 */ 1286 1287 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1288 BGE_PCI_MEMWIN_BASEADDR, 0); 1289 1290 /* Configure mbuf memory pool */ 1291 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1292 if (sc->bge_extram) { 1293 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1294 BGE_EXT_SSRAM); 1295 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1296 } else { 1297 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1298 BGE_BUFFPOOL_1); 1299 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1300 } 1301 1302 /* Configure DMA resource pool */ 1303 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1304 BGE_DMA_DESCRIPTORS); 1305 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1306 } 1307 1308 /* Configure mbuf pool watermarks */ 1309 #ifdef ORIG_WPAUL_VALUES 1310 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1311 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1312 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1313 #else 1314 /* new broadcom docs strongly recommend these: */ 1315 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1316 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1317 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1318 } else { 1319 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1321 } 1322 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1323 #endif 1324 1325 /* Configure DMA resource watermarks */ 1326 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1327 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1328 1329 /* Enable buffer manager */ 1330 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1331 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1332 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1333 1334 /* Poll for buffer manager start indication */ 1335 for (i = 0; i < BGE_TIMEOUT; i++) { 1336 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1337 break; 1338 DELAY(10); 1339 } 1340 1341 if (i == BGE_TIMEOUT) { 1342 printf("%s: buffer manager failed to start\n", 1343 sc->bge_dev.dv_xname); 1344 return(ENXIO); 1345 } 1346 } 1347 1348 /* Enable flow-through queues */ 1349 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1350 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1351 1352 /* Wait until queue initialization is complete */ 1353 for (i = 0; i < BGE_TIMEOUT; i++) { 1354 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1355 break; 1356 DELAY(10); 1357 } 1358 1359 if (i == BGE_TIMEOUT) { 1360 printf("%s: flow-through queue init failed\n", 1361 sc->bge_dev.dv_xname); 1362 return(ENXIO); 1363 } 1364 1365 /* Initialize the standard RX ring control block */ 1366 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1367 bge_set_hostaddr(&rcb->bge_hostaddr, 1368 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1369 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1370 rcb->bge_maxlen_flags = 1371 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1372 } else { 1373 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1374 } 1375 if (sc->bge_extram) 1376 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1377 else 1378 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1379 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1380 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1381 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1382 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1383 1384 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1385 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1386 } else { 1387 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1388 } 1389 1390 /* 1391 * Initialize the jumbo RX ring control block 1392 * We set the 'ring disabled' bit in the flags 1393 * field until we're actually ready to start 1394 * using this ring (i.e. once we set the MTU 1395 * high enough to require it). 1396 */ 1397 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1398 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1399 bge_set_hostaddr(&rcb->bge_hostaddr, 1400 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1401 rcb->bge_maxlen_flags = 1402 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1403 BGE_RCB_FLAG_RING_DISABLED); 1404 if (sc->bge_extram) 1405 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1406 else 1407 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1408 1409 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1410 rcb->bge_hostaddr.bge_addr_hi); 1411 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1412 rcb->bge_hostaddr.bge_addr_lo); 1413 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1414 rcb->bge_maxlen_flags); 1415 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1416 1417 /* Set up dummy disabled mini ring RCB */ 1418 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1419 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1420 BGE_RCB_FLAG_RING_DISABLED); 1421 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1422 rcb->bge_maxlen_flags); 1423 1424 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1425 offsetof(struct bge_ring_data, bge_info), 1426 sizeof (struct bge_gib), 1427 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1428 } 1429 1430 /* 1431 * Set the BD ring replentish thresholds. The recommended 1432 * values are 1/8th the number of descriptors allocated to 1433 * each ring. 1434 */ 1435 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1436 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1437 1438 /* 1439 * Disable all unused send rings by setting the 'ring disabled' 1440 * bit in the flags field of all the TX send ring control blocks. 1441 * These are located in NIC memory. 1442 */ 1443 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1444 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1445 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1446 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1447 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1448 rcb_addr += sizeof(struct bge_rcb); 1449 } 1450 1451 /* Configure TX RCB 0 (we use only the first ring) */ 1452 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1453 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1454 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1455 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1456 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1457 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1458 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1459 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1460 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1461 } 1462 1463 /* Disable all unused RX return rings */ 1464 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1465 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1466 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1467 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1468 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1469 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1470 BGE_RCB_FLAG_RING_DISABLED)); 1471 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1472 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1473 (i * (sizeof(u_int64_t))), 0); 1474 rcb_addr += sizeof(struct bge_rcb); 1475 } 1476 1477 /* Initialize RX ring indexes */ 1478 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1479 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1480 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1481 1482 /* 1483 * Set up RX return ring 0 1484 * Note that the NIC address for RX return rings is 0x00000000. 1485 * The return rings live entirely within the host, so the 1486 * nicaddr field in the RCB isn't used. 1487 */ 1488 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1489 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1490 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1491 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1492 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1493 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1494 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1495 1496 /* Set random backoff seed for TX */ 1497 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1498 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1499 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1500 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1501 BGE_TX_BACKOFF_SEED_MASK); 1502 1503 /* Set inter-packet gap */ 1504 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1505 1506 /* 1507 * Specify which ring to use for packets that don't match 1508 * any RX rules. 1509 */ 1510 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1511 1512 /* 1513 * Configure number of RX lists. One interrupt distribution 1514 * list, sixteen active lists, one bad frames class. 1515 */ 1516 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1517 1518 /* Inialize RX list placement stats mask. */ 1519 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1520 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1521 1522 /* Disable host coalescing until we get it set up */ 1523 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1524 1525 /* Poll to make sure it's shut down. */ 1526 for (i = 0; i < BGE_TIMEOUT; i++) { 1527 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1528 break; 1529 DELAY(10); 1530 } 1531 1532 if (i == BGE_TIMEOUT) { 1533 printf("%s: host coalescing engine failed to idle\n", 1534 sc->bge_dev.dv_xname); 1535 return(ENXIO); 1536 } 1537 1538 /* Set up host coalescing defaults */ 1539 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1540 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1541 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1542 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1543 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1544 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1545 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1546 } 1547 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1548 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1549 1550 /* Set up address of statistics block */ 1551 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1552 bge_set_hostaddr(&taddr, 1553 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1554 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1555 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1556 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1557 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1558 } 1559 1560 /* Set up address of status block */ 1561 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1562 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1563 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1564 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1565 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1566 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1567 1568 /* Turn on host coalescing state machine */ 1569 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1570 1571 /* Turn on RX BD completion state machine and enable attentions */ 1572 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1573 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1574 1575 /* Turn on RX list placement state machine */ 1576 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1577 1578 /* Turn on RX list selector state machine. */ 1579 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1580 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1581 } 1582 1583 /* Turn on DMA, clear stats */ 1584 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1585 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1586 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1587 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1588 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1589 1590 /* Set misc. local control, enable interrupts on attentions */ 1591 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1592 1593 #ifdef notdef 1594 /* Assert GPIO pins for PHY reset */ 1595 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1596 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1597 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1598 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1599 #endif 1600 1601 #if defined(not_quite_yet) 1602 /* Linux driver enables enable gpio pin #1 on 5700s */ 1603 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1604 sc->bge_local_ctrl_reg |= 1605 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1606 } 1607 #endif 1608 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1609 1610 /* Turn on DMA completion state machine */ 1611 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1612 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1613 } 1614 1615 /* Turn on write DMA state machine */ 1616 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1617 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1618 1619 /* Turn on read DMA state machine */ 1620 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1621 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1622 1623 /* Turn on RX data completion state machine */ 1624 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1625 1626 /* Turn on RX BD initiator state machine */ 1627 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1628 1629 /* Turn on RX data and RX BD initiator state machine */ 1630 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1631 1632 /* Turn on Mbuf cluster free state machine */ 1633 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1634 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1635 } 1636 1637 /* Turn on send BD completion state machine */ 1638 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1639 1640 /* Turn on send data completion state machine */ 1641 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1642 1643 /* Turn on send data initiator state machine */ 1644 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1645 1646 /* Turn on send BD initiator state machine */ 1647 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1648 1649 /* Turn on send BD selector state machine */ 1650 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1651 1652 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1653 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1654 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1655 1656 /* ack/clear link change events */ 1657 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1658 BGE_MACSTAT_CFG_CHANGED); 1659 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1660 1661 /* Enable PHY auto polling (for MII/GMII only) */ 1662 if (sc->bge_tbi) { 1663 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1664 } else { 1665 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1666 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1667 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1668 BGE_EVTENB_MI_INTERRUPT); 1669 } 1670 1671 /* Enable link state change attentions. */ 1672 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1673 1674 return(0); 1675 } 1676 1677 static const struct bge_revision { 1678 uint32_t br_chipid; 1679 uint32_t br_quirks; 1680 const char *br_name; 1681 } bge_revisions[] = { 1682 { BGE_CHIPID_BCM5700_A0, 1683 BGE_QUIRK_LINK_STATE_BROKEN, 1684 "BCM5700 A0" }, 1685 1686 { BGE_CHIPID_BCM5700_A1, 1687 BGE_QUIRK_LINK_STATE_BROKEN, 1688 "BCM5700 A1" }, 1689 1690 { BGE_CHIPID_BCM5700_B0, 1691 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1692 "BCM5700 B0" }, 1693 1694 { BGE_CHIPID_BCM5700_B1, 1695 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1696 "BCM5700 B1" }, 1697 1698 { BGE_CHIPID_BCM5700_B2, 1699 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1700 "BCM5700 B2" }, 1701 1702 /* This is treated like a BCM5700 Bx */ 1703 { BGE_CHIPID_BCM5700_ALTIMA, 1704 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1705 "BCM5700 Altima" }, 1706 1707 { BGE_CHIPID_BCM5700_C0, 1708 0, 1709 "BCM5700 C0" }, 1710 1711 { BGE_CHIPID_BCM5701_A0, 1712 0, /*XXX really, just not known */ 1713 "BCM5701 A0" }, 1714 1715 { BGE_CHIPID_BCM5701_B0, 1716 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1717 "BCM5701 B0" }, 1718 1719 { BGE_CHIPID_BCM5701_B2, 1720 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1721 "BCM5701 B2" }, 1722 1723 { BGE_CHIPID_BCM5701_B5, 1724 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1725 "BCM5701 B5" }, 1726 1727 { BGE_CHIPID_BCM5703_A0, 1728 0, 1729 "BCM5703 A0" }, 1730 1731 { BGE_CHIPID_BCM5703_A1, 1732 0, 1733 "BCM5703 A1" }, 1734 1735 { BGE_CHIPID_BCM5703_A2, 1736 BGE_QUIRK_ONLY_PHY_1, 1737 "BCM5703 A2" }, 1738 1739 { BGE_CHIPID_BCM5704_A0, 1740 BGE_QUIRK_ONLY_PHY_1, 1741 "BCM5704 A0" }, 1742 1743 { BGE_CHIPID_BCM5704_A1, 1744 BGE_QUIRK_ONLY_PHY_1, 1745 "BCM5704 A1" }, 1746 1747 { BGE_CHIPID_BCM5704_A2, 1748 BGE_QUIRK_ONLY_PHY_1, 1749 "BCM5704 A2" }, 1750 1751 { BGE_CHIPID_BCM5704_A3, 1752 BGE_QUIRK_ONLY_PHY_1, 1753 "BCM5704 A3" }, 1754 1755 { BGE_CHIPID_BCM5705_A0, 1756 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1757 "BCM5705 A0" }, 1758 1759 { BGE_CHIPID_BCM5705_A1, 1760 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1761 "BCM5705 A1" }, 1762 1763 { BGE_CHIPID_BCM5705_A2, 1764 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1765 "BCM5705 A2" }, 1766 1767 { BGE_CHIPID_BCM5705_A3, 1768 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1769 "BCM5705 A3" }, 1770 1771 { 0, 0, NULL } 1772 }; 1773 1774 /* 1775 * Some defaults for major revisions, so that newer steppings 1776 * that we don't know about have a shot at working. 1777 */ 1778 static const struct bge_revision bge_majorrevs[] = { 1779 { BGE_ASICREV_BCM5700, 1780 BGE_QUIRK_LINK_STATE_BROKEN, 1781 "unknown BCM5700" }, 1782 1783 { BGE_ASICREV_BCM5701, 1784 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1785 "unknown BCM5701" }, 1786 1787 { BGE_ASICREV_BCM5703, 1788 0, 1789 "unknown BCM5703" }, 1790 1791 { BGE_ASICREV_BCM5704, 1792 BGE_QUIRK_ONLY_PHY_1, 1793 "unknown BCM5704" }, 1794 1795 { BGE_ASICREV_BCM5705, 1796 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1797 "unknown BCM5705" }, 1798 1799 { 0, 1800 0, 1801 NULL } 1802 }; 1803 1804 1805 static const struct bge_revision * 1806 bge_lookup_rev(uint32_t chipid) 1807 { 1808 const struct bge_revision *br; 1809 1810 for (br = bge_revisions; br->br_name != NULL; br++) { 1811 if (br->br_chipid == chipid) 1812 return (br); 1813 } 1814 1815 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1816 if (br->br_chipid == BGE_ASICREV(chipid)) 1817 return (br); 1818 } 1819 1820 return (NULL); 1821 } 1822 1823 static const struct bge_product { 1824 pci_vendor_id_t bp_vendor; 1825 pci_product_id_t bp_product; 1826 const char *bp_name; 1827 } bge_products[] = { 1828 /* 1829 * The BCM5700 documentation seems to indicate that the hardware 1830 * still has the Alteon vendor ID burned into it, though it 1831 * should always be overridden by the value in the EEPROM. We'll 1832 * check for it anyway. 1833 */ 1834 { PCI_VENDOR_ALTEON, 1835 PCI_PRODUCT_ALTEON_BCM5700, 1836 "Broadcom BCM5700 Gigabit Ethernet", 1837 }, 1838 { PCI_VENDOR_ALTEON, 1839 PCI_PRODUCT_ALTEON_BCM5701, 1840 "Broadcom BCM5701 Gigabit Ethernet", 1841 }, 1842 1843 { PCI_VENDOR_ALTIMA, 1844 PCI_PRODUCT_ALTIMA_AC1000, 1845 "Altima AC1000 Gigabit Ethernet", 1846 }, 1847 { PCI_VENDOR_ALTIMA, 1848 PCI_PRODUCT_ALTIMA_AC1001, 1849 "Altima AC1001 Gigabit Ethernet", 1850 }, 1851 { PCI_VENDOR_ALTIMA, 1852 PCI_PRODUCT_ALTIMA_AC9100, 1853 "Altima AC9100 Gigabit Ethernet", 1854 }, 1855 1856 { PCI_VENDOR_BROADCOM, 1857 PCI_PRODUCT_BROADCOM_BCM5700, 1858 "Broadcom BCM5700 Gigabit Ethernet", 1859 }, 1860 { PCI_VENDOR_BROADCOM, 1861 PCI_PRODUCT_BROADCOM_BCM5701, 1862 "Broadcom BCM5701 Gigabit Ethernet", 1863 }, 1864 { PCI_VENDOR_BROADCOM, 1865 PCI_PRODUCT_BROADCOM_BCM5702, 1866 "Broadcom BCM5702 Gigabit Ethernet", 1867 }, 1868 { PCI_VENDOR_BROADCOM, 1869 PCI_PRODUCT_BROADCOM_BCM5702X, 1870 "Broadcom BCM5702X Gigabit Ethernet" }, 1871 1872 { PCI_VENDOR_BROADCOM, 1873 PCI_PRODUCT_BROADCOM_BCM5703, 1874 "Broadcom BCM5703 Gigabit Ethernet", 1875 }, 1876 { PCI_VENDOR_BROADCOM, 1877 PCI_PRODUCT_BROADCOM_BCM5703X, 1878 "Broadcom BCM5703X Gigabit Ethernet", 1879 }, 1880 1881 { PCI_VENDOR_BROADCOM, 1882 PCI_PRODUCT_BROADCOM_BCM5704C, 1883 "Broadcom BCM5704C Dual Gigabit Ethernet", 1884 }, 1885 { PCI_VENDOR_BROADCOM, 1886 PCI_PRODUCT_BROADCOM_BCM5704S, 1887 "Broadcom BCM5704S Dual Gigabit Ethernet", 1888 }, 1889 1890 { PCI_VENDOR_BROADCOM, 1891 PCI_PRODUCT_BROADCOM_BCM5705, 1892 "Broadcom BCM5705 Gigabit Ethernet", 1893 }, 1894 { PCI_VENDOR_BROADCOM, 1895 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 1896 "Broadcom BCM5705 Gigabit Ethernet", 1897 }, 1898 { PCI_VENDOR_BROADCOM, 1899 PCI_PRODUCT_BROADCOM_BCM5705M, 1900 "Broadcom BCM5705M Gigabit Ethernet", 1901 }, 1902 1903 { PCI_VENDOR_BROADCOM, 1904 PCI_PRODUCT_BROADCOM_BCM5901, 1905 "Broadcom BCM5901 Fast Ethernet", 1906 }, 1907 { PCI_VENDOR_BROADCOM, 1908 PCI_PRODUCT_BROADCOM_BCM5901A2, 1909 "Broadcom BCM5901A2 Fast Ethernet", 1910 }, 1911 1912 { PCI_VENDOR_BROADCOM, 1913 PCI_PRODUCT_BROADCOM_BCM5782, 1914 "Broadcom BCM5782 Gigabit Ethernet", 1915 }, 1916 1917 { PCI_VENDOR_SCHNEIDERKOCH, 1918 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1919 "SysKonnect SK-9Dx1 Gigabit Ethernet", 1920 }, 1921 1922 { PCI_VENDOR_3COM, 1923 PCI_PRODUCT_3COM_3C996, 1924 "3Com 3c996 Gigabit Ethernet", 1925 }, 1926 1927 { 0, 1928 0, 1929 NULL }, 1930 }; 1931 1932 static const struct bge_product * 1933 bge_lookup(const struct pci_attach_args *pa) 1934 { 1935 const struct bge_product *bp; 1936 1937 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1938 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1939 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1940 return (bp); 1941 } 1942 1943 return (NULL); 1944 } 1945 1946 int 1947 bge_setpowerstate(sc, powerlevel) 1948 struct bge_softc *sc; 1949 int powerlevel; 1950 { 1951 #ifdef NOTYET 1952 u_int32_t pm_ctl = 0; 1953 1954 /* XXX FIXME: make sure indirect accesses enabled? */ 1955 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 1956 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 1957 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 1958 1959 /* clear the PME_assert bit and power state bits, enable PME */ 1960 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 1961 pm_ctl &= ~PCIM_PSTAT_DMASK; 1962 pm_ctl |= (1 << 8); 1963 1964 if (powerlevel == 0) { 1965 pm_ctl |= PCIM_PSTAT_D0; 1966 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 1967 pm_ctl, 2); 1968 DELAY(10000); 1969 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1970 DELAY(10000); 1971 1972 #ifdef NOTYET 1973 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 1974 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 1975 #endif 1976 DELAY(40); DELAY(40); DELAY(40); 1977 DELAY(10000); /* above not quite adequate on 5700 */ 1978 return 0; 1979 } 1980 1981 1982 /* 1983 * Entering ACPI power states D1-D3 is achieved by wiggling 1984 * GMII gpio pins. Example code assumes all hardware vendors 1985 * followed Broadom's sample pcb layout. Until we verify that 1986 * for all supported OEM cards, states D1-D3 are unsupported. 1987 */ 1988 printf("%s: power state %d unimplemented; check GPIO pins\n", 1989 sc->bge_dev.dv_xname, powerlevel); 1990 #endif 1991 return EOPNOTSUPP; 1992 } 1993 1994 1995 /* 1996 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1997 * against our list and return its name if we find a match. Note 1998 * that since the Broadcom controller contains VPD support, we 1999 * can get the device name string from the controller itself instead 2000 * of the compiled-in string. This is a little slow, but it guarantees 2001 * we'll always announce the right product name. 2002 */ 2003 int 2004 bge_probe(parent, match, aux) 2005 struct device *parent; 2006 struct cfdata *match; 2007 void *aux; 2008 { 2009 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2010 2011 if (bge_lookup(pa) != NULL) 2012 return (1); 2013 2014 return (0); 2015 } 2016 2017 void 2018 bge_attach(parent, self, aux) 2019 struct device *parent, *self; 2020 void *aux; 2021 { 2022 struct bge_softc *sc = (struct bge_softc *)self; 2023 struct pci_attach_args *pa = aux; 2024 const struct bge_product *bp; 2025 const struct bge_revision *br; 2026 pci_chipset_tag_t pc = pa->pa_pc; 2027 pci_intr_handle_t ih; 2028 const char *intrstr = NULL; 2029 bus_dma_segment_t seg; 2030 int rseg; 2031 u_int32_t hwcfg = 0; 2032 u_int32_t mac_addr = 0; 2033 u_int32_t command; 2034 struct ifnet *ifp; 2035 caddr_t kva; 2036 u_char eaddr[ETHER_ADDR_LEN]; 2037 pcireg_t memtype; 2038 bus_addr_t memaddr; 2039 bus_size_t memsize; 2040 u_int32_t pm_ctl; 2041 2042 bp = bge_lookup(pa); 2043 KASSERT(bp != NULL); 2044 2045 sc->bge_pa = *pa; 2046 2047 aprint_naive(": Ethernet controller\n"); 2048 aprint_normal(": %s\n", bp->bp_name); 2049 2050 /* 2051 * Map control/status registers. 2052 */ 2053 DPRINTFN(5, ("Map control/status regs\n")); 2054 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2055 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2056 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2057 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2058 2059 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2060 aprint_error("%s: failed to enable memory mapping!\n", 2061 sc->bge_dev.dv_xname); 2062 return; 2063 } 2064 2065 DPRINTFN(5, ("pci_mem_find\n")); 2066 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2067 switch (memtype) { 2068 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2069 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2070 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2071 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2072 &memaddr, &memsize) == 0) 2073 break; 2074 default: 2075 aprint_error("%s: can't find mem space\n", 2076 sc->bge_dev.dv_xname); 2077 return; 2078 } 2079 2080 DPRINTFN(5, ("pci_intr_map\n")); 2081 if (pci_intr_map(pa, &ih)) { 2082 aprint_error("%s: couldn't map interrupt\n", 2083 sc->bge_dev.dv_xname); 2084 return; 2085 } 2086 2087 DPRINTFN(5, ("pci_intr_string\n")); 2088 intrstr = pci_intr_string(pc, ih); 2089 2090 DPRINTFN(5, ("pci_intr_establish\n")); 2091 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2092 2093 if (sc->bge_intrhand == NULL) { 2094 aprint_error("%s: couldn't establish interrupt", 2095 sc->bge_dev.dv_xname); 2096 if (intrstr != NULL) 2097 aprint_normal(" at %s", intrstr); 2098 aprint_normal("\n"); 2099 return; 2100 } 2101 aprint_normal("%s: interrupting at %s\n", 2102 sc->bge_dev.dv_xname, intrstr); 2103 2104 /* 2105 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2106 * can clobber the chip's PCI config-space power control registers, 2107 * leaving the card in D3 powersave state. 2108 * We do not have memory-mapped registers in this state, 2109 * so force device into D0 state before starting initialization. 2110 */ 2111 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2112 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2113 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2114 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2115 DELAY(1000); /* 27 usec is allegedly sufficent */ 2116 2117 /* Try to reset the chip. */ 2118 DPRINTFN(5, ("bge_reset\n")); 2119 bge_reset(sc); 2120 2121 if (bge_chipinit(sc)) { 2122 aprint_error("%s: chip initialization failed\n", 2123 sc->bge_dev.dv_xname); 2124 bge_release_resources(sc); 2125 return; 2126 } 2127 2128 /* 2129 * Get station address from the EEPROM. 2130 */ 2131 mac_addr = bge_readmem_ind(sc, 0x0c14); 2132 if ((mac_addr >> 16) == 0x484b) { 2133 eaddr[0] = (u_char)(mac_addr >> 8); 2134 eaddr[1] = (u_char)(mac_addr >> 0); 2135 mac_addr = bge_readmem_ind(sc, 0x0c18); 2136 eaddr[2] = (u_char)(mac_addr >> 24); 2137 eaddr[3] = (u_char)(mac_addr >> 16); 2138 eaddr[4] = (u_char)(mac_addr >> 8); 2139 eaddr[5] = (u_char)(mac_addr >> 0); 2140 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2141 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2142 aprint_error("%s: failed to read station address\n", 2143 sc->bge_dev.dv_xname); 2144 bge_release_resources(sc); 2145 return; 2146 } 2147 2148 /* 2149 * Save ASIC rev. Look up any quirks associated with this 2150 * ASIC. 2151 */ 2152 sc->bge_chipid = 2153 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2154 BGE_PCIMISCCTL_ASICREV; 2155 br = bge_lookup_rev(sc->bge_chipid); 2156 2157 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2158 2159 if (br == NULL) { 2160 aprint_normal("unknown ASIC 0x%08x", sc->bge_chipid); 2161 } else { 2162 aprint_normal("ASIC %s", br->br_name); 2163 sc->bge_quirks |= br->br_quirks; 2164 } 2165 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2166 2167 /* Allocate the general information block and ring buffers. */ 2168 if (pci_dma64_available(pa)) 2169 sc->bge_dmatag = pa->pa_dmat64; 2170 else 2171 sc->bge_dmatag = pa->pa_dmat; 2172 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2173 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2174 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2175 aprint_error("%s: can't alloc rx buffers\n", 2176 sc->bge_dev.dv_xname); 2177 return; 2178 } 2179 DPRINTFN(5, ("bus_dmamem_map\n")); 2180 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2181 sizeof(struct bge_ring_data), &kva, 2182 BUS_DMA_NOWAIT)) { 2183 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2184 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2185 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2186 return; 2187 } 2188 DPRINTFN(5, ("bus_dmamem_create\n")); 2189 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2190 sizeof(struct bge_ring_data), 0, 2191 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2192 aprint_error("%s: can't create DMA map\n", 2193 sc->bge_dev.dv_xname); 2194 bus_dmamem_unmap(sc->bge_dmatag, kva, 2195 sizeof(struct bge_ring_data)); 2196 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2197 return; 2198 } 2199 DPRINTFN(5, ("bus_dmamem_load\n")); 2200 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2201 sizeof(struct bge_ring_data), NULL, 2202 BUS_DMA_NOWAIT)) { 2203 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2204 bus_dmamem_unmap(sc->bge_dmatag, kva, 2205 sizeof(struct bge_ring_data)); 2206 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2207 return; 2208 } 2209 2210 DPRINTFN(5, ("bzero\n")); 2211 sc->bge_rdata = (struct bge_ring_data *)kva; 2212 2213 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2214 2215 /* Try to allocate memory for jumbo buffers. */ 2216 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2217 if (bge_alloc_jumbo_mem(sc)) { 2218 aprint_error("%s: jumbo buffer allocation failed\n", 2219 sc->bge_dev.dv_xname); 2220 } else 2221 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2222 } 2223 2224 /* Set default tuneable values. */ 2225 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2226 sc->bge_rx_coal_ticks = 150; 2227 sc->bge_rx_max_coal_bds = 64; 2228 #ifdef ORIG_WPAUL_VALUES 2229 sc->bge_tx_coal_ticks = 150; 2230 sc->bge_tx_max_coal_bds = 128; 2231 #else 2232 sc->bge_tx_coal_ticks = 300; 2233 sc->bge_tx_max_coal_bds = 400; 2234 #endif 2235 2236 /* Set up ifnet structure */ 2237 ifp = &sc->ethercom.ec_if; 2238 ifp->if_softc = sc; 2239 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2240 ifp->if_ioctl = bge_ioctl; 2241 ifp->if_start = bge_start; 2242 ifp->if_init = bge_init; 2243 ifp->if_watchdog = bge_watchdog; 2244 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2245 IFQ_SET_READY(&ifp->if_snd); 2246 DPRINTFN(5, ("bcopy\n")); 2247 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2248 2249 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2250 sc->ethercom.ec_if.if_capabilities |= 2251 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 2252 sc->ethercom.ec_capabilities |= 2253 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2254 2255 /* 2256 * Do MII setup. 2257 */ 2258 DPRINTFN(5, ("mii setup\n")); 2259 sc->bge_mii.mii_ifp = ifp; 2260 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2261 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2262 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2263 2264 /* 2265 * Figure out what sort of media we have by checking the 2266 * hardware config word in the first 32k of NIC internal memory, 2267 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2268 * cards, this value appears to be unset. If that's the 2269 * case, we have to rely on identifying the NIC by its PCI 2270 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2271 */ 2272 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2273 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2274 } else { 2275 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2276 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2277 hwcfg = be32toh(hwcfg); 2278 } 2279 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2280 sc->bge_tbi = 1; 2281 2282 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2283 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2284 SK_SUBSYSID_9D41) 2285 sc->bge_tbi = 1; 2286 2287 if (sc->bge_tbi) { 2288 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2289 bge_ifmedia_sts); 2290 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2291 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2292 0, NULL); 2293 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2294 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2295 } else { 2296 /* 2297 * Do transceiver setup. 2298 */ 2299 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2300 bge_ifmedia_sts); 2301 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2302 MII_PHY_ANY, MII_OFFSET_ANY, 0); 2303 2304 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2305 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2306 ifmedia_add(&sc->bge_mii.mii_media, 2307 IFM_ETHER|IFM_MANUAL, 0, NULL); 2308 ifmedia_set(&sc->bge_mii.mii_media, 2309 IFM_ETHER|IFM_MANUAL); 2310 } else 2311 ifmedia_set(&sc->bge_mii.mii_media, 2312 IFM_ETHER|IFM_AUTO); 2313 } 2314 2315 /* 2316 * When using the BCM5701 in PCI-X mode, data corruption has 2317 * been observed in the first few bytes of some received packets. 2318 * Aligning the packet buffer in memory eliminates the corruption. 2319 * Unfortunately, this misaligns the packet payloads. On platforms 2320 * which do not support unaligned accesses, we will realign the 2321 * payloads by copying the received packets. 2322 */ 2323 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2324 /* If in PCI-X mode, work around the alignment bug. */ 2325 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2326 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2327 BGE_PCISTATE_PCI_BUSSPEED) 2328 sc->bge_rx_alignment_bug = 1; 2329 } 2330 2331 /* 2332 * Call MI attach routine. 2333 */ 2334 DPRINTFN(5, ("if_attach\n")); 2335 if_attach(ifp); 2336 DPRINTFN(5, ("ether_ifattach\n")); 2337 ether_ifattach(ifp, eaddr); 2338 DPRINTFN(5, ("callout_init\n")); 2339 callout_init(&sc->bge_timeout); 2340 } 2341 2342 void 2343 bge_release_resources(sc) 2344 struct bge_softc *sc; 2345 { 2346 if (sc->bge_vpd_prodname != NULL) 2347 free(sc->bge_vpd_prodname, M_DEVBUF); 2348 2349 if (sc->bge_vpd_readonly != NULL) 2350 free(sc->bge_vpd_readonly, M_DEVBUF); 2351 } 2352 2353 void 2354 bge_reset(sc) 2355 struct bge_softc *sc; 2356 { 2357 struct pci_attach_args *pa = &sc->bge_pa; 2358 u_int32_t cachesize, command, pcistate; 2359 int i, val = 0; 2360 2361 /* Save some important PCI state. */ 2362 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2363 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2364 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2365 2366 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2367 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2368 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2369 2370 /* Issue global reset */ 2371 bge_writereg_ind(sc, BGE_MISC_CFG, 2372 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2373 2374 DELAY(1000); 2375 2376 /* Reset some of the PCI state that got zapped by reset */ 2377 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2378 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2379 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2380 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2381 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2382 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2383 2384 /* Enable memory arbiter. */ 2385 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2386 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2387 } 2388 2389 /* 2390 * Prevent PXE restart: write a magic number to the 2391 * general communications memory at 0xB50. 2392 */ 2393 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2394 2395 /* 2396 * Poll the value location we just wrote until 2397 * we see the 1's complement of the magic number. 2398 * This indicates that the firmware initialization 2399 * is complete. 2400 */ 2401 for (i = 0; i < 750; i++) { 2402 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2403 if (val == ~BGE_MAGIC_NUMBER) 2404 break; 2405 DELAY(1000); 2406 } 2407 2408 if (i == 750) { 2409 printf("%s: firmware handshake timed out, val = %x\n", 2410 sc->bge_dev.dv_xname, val); 2411 return; 2412 } 2413 2414 /* 2415 * XXX Wait for the value of the PCISTATE register to 2416 * return to its original pre-reset state. This is a 2417 * fairly good indicator of reset completion. If we don't 2418 * wait for the reset to fully complete, trying to read 2419 * from the device's non-PCI registers may yield garbage 2420 * results. 2421 */ 2422 for (i = 0; i < BGE_TIMEOUT; i++) { 2423 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2424 pcistate) 2425 break; 2426 DELAY(10); 2427 } 2428 2429 /* Enable memory arbiter. */ 2430 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2431 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2432 } 2433 2434 /* Fix up byte swapping */ 2435 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2436 2437 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2438 2439 DELAY(10000); 2440 } 2441 2442 /* 2443 * Frame reception handling. This is called if there's a frame 2444 * on the receive return list. 2445 * 2446 * Note: we have to be able to handle two possibilities here: 2447 * 1) the frame is from the jumbo recieve ring 2448 * 2) the frame is from the standard receive ring 2449 */ 2450 2451 void 2452 bge_rxeof(sc) 2453 struct bge_softc *sc; 2454 { 2455 struct ifnet *ifp; 2456 int stdcnt = 0, jumbocnt = 0; 2457 int have_tag = 0; 2458 u_int16_t vlan_tag = 0; 2459 bus_dmamap_t dmamap; 2460 bus_addr_t offset, toff; 2461 bus_size_t tlen; 2462 int tosync; 2463 2464 ifp = &sc->ethercom.ec_if; 2465 2466 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2467 offsetof(struct bge_ring_data, bge_status_block), 2468 sizeof (struct bge_status_block), 2469 BUS_DMASYNC_POSTREAD); 2470 2471 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2472 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2473 sc->bge_rx_saved_considx; 2474 2475 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2476 2477 if (tosync < 0) { 2478 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2479 sizeof (struct bge_rx_bd); 2480 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2481 toff, tlen, BUS_DMASYNC_POSTREAD); 2482 tosync = -tosync; 2483 } 2484 2485 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2486 offset, tosync * sizeof (struct bge_rx_bd), 2487 BUS_DMASYNC_POSTREAD); 2488 2489 while(sc->bge_rx_saved_considx != 2490 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2491 struct bge_rx_bd *cur_rx; 2492 u_int32_t rxidx; 2493 struct mbuf *m = NULL; 2494 2495 cur_rx = &sc->bge_rdata-> 2496 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2497 2498 rxidx = cur_rx->bge_idx; 2499 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2500 2501 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2502 have_tag = 1; 2503 vlan_tag = cur_rx->bge_vlan_tag; 2504 } 2505 2506 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2507 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2508 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2509 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2510 jumbocnt++; 2511 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2512 ifp->if_ierrors++; 2513 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2514 continue; 2515 } 2516 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2517 NULL)== ENOBUFS) { 2518 ifp->if_ierrors++; 2519 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2520 continue; 2521 } 2522 } else { 2523 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2524 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2525 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2526 stdcnt++; 2527 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2528 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2529 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2530 ifp->if_ierrors++; 2531 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2532 continue; 2533 } 2534 if (bge_newbuf_std(sc, sc->bge_std, 2535 NULL, dmamap) == ENOBUFS) { 2536 ifp->if_ierrors++; 2537 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2538 continue; 2539 } 2540 } 2541 2542 ifp->if_ipackets++; 2543 #ifndef __NO_STRICT_ALIGNMENT 2544 /* 2545 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2546 * the Rx buffer has the layer-2 header unaligned. 2547 * If our CPU requires alignment, re-align by copying. 2548 */ 2549 if (sc->bge_rx_alignment_bug) { 2550 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2551 cur_rx->bge_len); 2552 m->m_data += ETHER_ALIGN; 2553 } 2554 #endif 2555 2556 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2557 m->m_pkthdr.rcvif = ifp; 2558 2559 #if NBPFILTER > 0 2560 /* 2561 * Handle BPF listeners. Let the BPF user see the packet. 2562 */ 2563 if (ifp->if_bpf) 2564 bpf_mtap(ifp->if_bpf, m); 2565 #endif 2566 2567 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2568 2569 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2570 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2571 /* 2572 * Rx transport checksum-offload may also 2573 * have bugs with packets which, when transmitted, 2574 * were `runts' requiring padding. 2575 */ 2576 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2577 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2578 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2579 m->m_pkthdr.csum_data = 2580 cur_rx->bge_tcp_udp_csum; 2581 m->m_pkthdr.csum_flags |= 2582 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2583 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2584 } 2585 2586 /* 2587 * If we received a packet with a vlan tag, pass it 2588 * to vlan_input() instead of ether_input(). 2589 */ 2590 if (have_tag) { 2591 struct m_tag *mtag; 2592 2593 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2594 M_NOWAIT); 2595 if (mtag != NULL) { 2596 *(u_int *)(mtag + 1) = vlan_tag; 2597 m_tag_prepend(m, mtag); 2598 have_tag = vlan_tag = 0; 2599 } else { 2600 printf("%s: no mbuf for tag\n", ifp->if_xname); 2601 m_freem(m); 2602 have_tag = vlan_tag = 0; 2603 continue; 2604 } 2605 } 2606 (*ifp->if_input)(ifp, m); 2607 } 2608 2609 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2610 if (stdcnt) 2611 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2612 if (jumbocnt) 2613 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2614 } 2615 2616 void 2617 bge_txeof(sc) 2618 struct bge_softc *sc; 2619 { 2620 struct bge_tx_bd *cur_tx = NULL; 2621 struct ifnet *ifp; 2622 struct txdmamap_pool_entry *dma; 2623 bus_addr_t offset, toff; 2624 bus_size_t tlen; 2625 int tosync; 2626 struct mbuf *m; 2627 2628 ifp = &sc->ethercom.ec_if; 2629 2630 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2631 offsetof(struct bge_ring_data, bge_status_block), 2632 sizeof (struct bge_status_block), 2633 BUS_DMASYNC_POSTREAD); 2634 2635 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2636 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2637 sc->bge_tx_saved_considx; 2638 2639 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2640 2641 if (tosync < 0) { 2642 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2643 sizeof (struct bge_tx_bd); 2644 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2645 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2646 tosync = -tosync; 2647 } 2648 2649 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2650 offset, tosync * sizeof (struct bge_tx_bd), 2651 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2652 2653 /* 2654 * Go through our tx ring and free mbufs for those 2655 * frames that have been sent. 2656 */ 2657 while (sc->bge_tx_saved_considx != 2658 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2659 u_int32_t idx = 0; 2660 2661 idx = sc->bge_tx_saved_considx; 2662 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2663 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2664 ifp->if_opackets++; 2665 m = sc->bge_cdata.bge_tx_chain[idx]; 2666 if (m != NULL) { 2667 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2668 dma = sc->txdma[idx]; 2669 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2670 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2671 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2672 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2673 sc->txdma[idx] = NULL; 2674 2675 m_freem(m); 2676 } 2677 sc->bge_txcnt--; 2678 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2679 ifp->if_timer = 0; 2680 } 2681 2682 if (cur_tx != NULL) 2683 ifp->if_flags &= ~IFF_OACTIVE; 2684 } 2685 2686 int 2687 bge_intr(xsc) 2688 void *xsc; 2689 { 2690 struct bge_softc *sc; 2691 struct ifnet *ifp; 2692 2693 sc = xsc; 2694 ifp = &sc->ethercom.ec_if; 2695 2696 #ifdef notdef 2697 /* Avoid this for now -- checking this register is expensive. */ 2698 /* Make sure this is really our interrupt. */ 2699 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2700 return (0); 2701 #endif 2702 /* Ack interrupt and stop others from occuring. */ 2703 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2704 2705 /* 2706 * Process link state changes. 2707 * Grrr. The link status word in the status block does 2708 * not work correctly on the BCM5700 rev AX and BX chips, 2709 * according to all avaibable information. Hence, we have 2710 * to enable MII interrupts in order to properly obtain 2711 * async link changes. Unfortunately, this also means that 2712 * we have to read the MAC status register to detect link 2713 * changes, thereby adding an additional register access to 2714 * the interrupt handler. 2715 */ 2716 2717 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2718 u_int32_t status; 2719 2720 status = CSR_READ_4(sc, BGE_MAC_STS); 2721 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2722 sc->bge_link = 0; 2723 callout_stop(&sc->bge_timeout); 2724 bge_tick(sc); 2725 /* Clear the interrupt */ 2726 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2727 BGE_EVTENB_MI_INTERRUPT); 2728 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2729 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2730 BRGPHY_INTRS); 2731 } 2732 } else { 2733 if (sc->bge_rdata->bge_status_block.bge_status & 2734 BGE_STATFLAG_LINKSTATE_CHANGED) { 2735 sc->bge_link = 0; 2736 callout_stop(&sc->bge_timeout); 2737 bge_tick(sc); 2738 /* Clear the interrupt */ 2739 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2740 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2741 BGE_MACSTAT_LINK_CHANGED); 2742 } 2743 } 2744 2745 if (ifp->if_flags & IFF_RUNNING) { 2746 /* Check RX return ring producer/consumer */ 2747 bge_rxeof(sc); 2748 2749 /* Check TX ring producer/consumer */ 2750 bge_txeof(sc); 2751 } 2752 2753 bge_handle_events(sc); 2754 2755 /* Re-enable interrupts. */ 2756 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2757 2758 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2759 bge_start(ifp); 2760 2761 return (1); 2762 } 2763 2764 void 2765 bge_tick(xsc) 2766 void *xsc; 2767 { 2768 struct bge_softc *sc = xsc; 2769 struct mii_data *mii = &sc->bge_mii; 2770 struct ifmedia *ifm = NULL; 2771 struct ifnet *ifp = &sc->ethercom.ec_if; 2772 int s; 2773 2774 s = splnet(); 2775 2776 bge_stats_update(sc); 2777 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2778 if (sc->bge_link) { 2779 splx(s); 2780 return; 2781 } 2782 2783 if (sc->bge_tbi) { 2784 ifm = &sc->bge_ifmedia; 2785 if (CSR_READ_4(sc, BGE_MAC_STS) & 2786 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2787 sc->bge_link++; 2788 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2789 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2790 bge_start(ifp); 2791 } 2792 splx(s); 2793 return; 2794 } 2795 2796 mii_tick(mii); 2797 2798 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2799 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2800 sc->bge_link++; 2801 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2802 bge_start(ifp); 2803 } 2804 2805 splx(s); 2806 } 2807 2808 void 2809 bge_stats_update(sc) 2810 struct bge_softc *sc; 2811 { 2812 struct ifnet *ifp = &sc->ethercom.ec_if; 2813 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2814 bus_size_t rstats = BGE_RX_STATS; 2815 2816 #define READ_RSTAT(sc, stats, stat) \ 2817 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 2818 2819 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2820 ifp->if_collisions += 2821 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 2822 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 2823 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 2824 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 2825 return; 2826 } 2827 2828 #undef READ_RSTAT 2829 #define READ_STAT(sc, stats, stat) \ 2830 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2831 2832 ifp->if_collisions += 2833 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2834 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2835 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2836 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2837 ifp->if_collisions; 2838 2839 #undef READ_STAT 2840 2841 #ifdef notdef 2842 ifp->if_collisions += 2843 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2844 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2845 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2846 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2847 ifp->if_collisions; 2848 #endif 2849 } 2850 2851 /* 2852 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2853 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2854 * but when such padded frames employ the bge IP/TCP checksum offload, 2855 * the hardware checksum assist gives incorrect results (possibly 2856 * from incorporating its own padding into the UDP/TCP checksum; who knows). 2857 * If we pad such runts with zeros, the onboard checksum comes out correct. 2858 */ 2859 static __inline int 2860 bge_cksum_pad(struct mbuf *pkt) 2861 { 2862 struct mbuf *last = NULL; 2863 int padlen; 2864 2865 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 2866 2867 /* if there's only the packet-header and we can pad there, use it. */ 2868 if (pkt->m_pkthdr.len == pkt->m_len && 2869 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 2870 last = pkt; 2871 } else { 2872 /* 2873 * Walk packet chain to find last mbuf. We will either 2874 * pad there, or append a new mbuf and pad it 2875 * (thus perhaps avoiding the bcm5700 dma-min bug). 2876 */ 2877 for (last = pkt; last->m_next != NULL; last = last->m_next) { 2878 (void) 0; /* do nothing*/ 2879 } 2880 2881 /* `last' now points to last in chain. */ 2882 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 2883 (void) 0; /* we can pad here, in-place. */ 2884 } else { 2885 /* Allocate new empty mbuf, pad it. Compact later. */ 2886 struct mbuf *n; 2887 MGET(n, M_DONTWAIT, MT_DATA); 2888 n->m_len = 0; 2889 last->m_next = n; 2890 last = n; 2891 } 2892 } 2893 2894 #ifdef DEBUG 2895 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 2896 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 2897 #endif 2898 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 2899 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 2900 last->m_len += padlen; 2901 pkt->m_pkthdr.len += padlen; 2902 return 0; 2903 } 2904 2905 /* 2906 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 2907 */ 2908 static __inline int 2909 bge_compact_dma_runt(struct mbuf *pkt) 2910 { 2911 struct mbuf *m, *prev; 2912 int totlen, prevlen; 2913 2914 prev = NULL; 2915 totlen = 0; 2916 prevlen = -1; 2917 2918 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 2919 int mlen = m->m_len; 2920 int shortfall = 8 - mlen ; 2921 2922 totlen += mlen; 2923 if (mlen == 0) { 2924 continue; 2925 } 2926 if (mlen >= 8) 2927 continue; 2928 2929 /* If we get here, mbuf data is too small for DMA engine. 2930 * Try to fix by shuffling data to prev or next in chain. 2931 * If that fails, do a compacting deep-copy of the whole chain. 2932 */ 2933 2934 /* Internal frag. If fits in prev, copy it there. */ 2935 if (prev && !M_READONLY(prev) && 2936 M_TRAILINGSPACE(prev) >= m->m_len) { 2937 bcopy(m->m_data, 2938 prev->m_data+prev->m_len, 2939 mlen); 2940 prev->m_len += mlen; 2941 m->m_len = 0; 2942 /* XXX stitch chain */ 2943 prev->m_next = m_free(m); 2944 m = prev; 2945 continue; 2946 } 2947 else if (m->m_next != NULL && !M_READONLY(m) && 2948 M_TRAILINGSPACE(m) >= shortfall && 2949 m->m_next->m_len >= (8 + shortfall)) { 2950 /* m is writable and have enough data in next, pull up. */ 2951 2952 bcopy(m->m_next->m_data, 2953 m->m_data+m->m_len, 2954 shortfall); 2955 m->m_len += shortfall; 2956 m->m_next->m_len -= shortfall; 2957 m->m_next->m_data += shortfall; 2958 } 2959 else if (m->m_next == NULL || 1) { 2960 /* Got a runt at the very end of the packet. 2961 * borrow data from the tail of the preceding mbuf and 2962 * update its length in-place. (The original data is still 2963 * valid, so we can do this even if prev is not writable.) 2964 */ 2965 2966 /* if we'd make prev a runt, just move all of its data. */ 2967 #ifdef DEBUG 2968 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 2969 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 2970 #endif 2971 if ((prev->m_len - shortfall) < 8) 2972 shortfall = prev->m_len; 2973 2974 #ifdef notyet /* just do the safe slow thing for now */ 2975 if (!M_READONLY(m)) { 2976 if (M_LEADINGSPACE(m) < shorfall) { 2977 void *m_dat; 2978 m_dat = (m->m_flags & M_PKTHDR) ? 2979 m->m_pktdat : m->dat; 2980 memmove(m_dat, mtod(m, void*), m->m_len); 2981 m->m_data = m_dat; 2982 } 2983 } else 2984 #endif /* just do the safe slow thing */ 2985 { 2986 struct mbuf * n = NULL; 2987 int newprevlen = prev->m_len - shortfall; 2988 2989 MGET(n, M_NOWAIT, MT_DATA); 2990 if (n == NULL) 2991 return ENOBUFS; 2992 KASSERT(m->m_len + shortfall < MLEN 2993 /*, 2994 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 2995 2996 /* first copy the data we're stealing from prev */ 2997 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 2998 2999 /* update prev->m_len accordingly */ 3000 prev->m_len -= shortfall; 3001 3002 /* copy data from runt m */ 3003 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3004 3005 /* n holds what we stole from prev, plus m */ 3006 n->m_len = shortfall + m->m_len; 3007 3008 /* stitch n into chain and free m */ 3009 n->m_next = m->m_next; 3010 prev->m_next = n; 3011 /* KASSERT(m->m_next == NULL); */ 3012 m->m_next = NULL; 3013 m_free(m); 3014 m = n; /* for continuing loop */ 3015 } 3016 } 3017 prevlen = m->m_len; 3018 } 3019 return 0; 3020 } 3021 3022 /* 3023 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3024 * pointers to descriptors. 3025 */ 3026 int 3027 bge_encap(sc, m_head, txidx) 3028 struct bge_softc *sc; 3029 struct mbuf *m_head; 3030 u_int32_t *txidx; 3031 { 3032 struct bge_tx_bd *f = NULL; 3033 u_int32_t frag, cur, cnt = 0; 3034 u_int16_t csum_flags = 0; 3035 struct txdmamap_pool_entry *dma; 3036 bus_dmamap_t dmamap; 3037 int i = 0; 3038 struct m_tag *mtag; 3039 3040 cur = frag = *txidx; 3041 3042 if (m_head->m_pkthdr.csum_flags) { 3043 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3044 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3045 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3046 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3047 } 3048 3049 /* 3050 * If we were asked to do an outboard checksum, and the NIC 3051 * has the bug where it sometimes adds in the Ethernet padding, 3052 * explicitly pad with zeros so the cksum will be correct either way. 3053 * (For now, do this for all chip versions, until newer 3054 * are confirmed to not require the workaround.) 3055 */ 3056 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3057 #ifdef notyet 3058 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3059 #endif 3060 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3061 goto check_dma_bug; 3062 3063 if (bge_cksum_pad(m_head) != 0) 3064 return ENOBUFS; 3065 3066 check_dma_bug: 3067 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3068 goto doit; 3069 /* 3070 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3071 * less than eight bytes. If we encounter a teeny mbuf 3072 * at the end of a chain, we can pad. Otherwise, copy. 3073 */ 3074 if (bge_compact_dma_runt(m_head) != 0) 3075 return ENOBUFS; 3076 3077 doit: 3078 dma = SLIST_FIRST(&sc->txdma_list); 3079 if (dma == NULL) 3080 return ENOBUFS; 3081 dmamap = dma->dmamap; 3082 3083 /* 3084 * Start packing the mbufs in this chain into 3085 * the fragment pointers. Stop when we run out 3086 * of fragments or hit the end of the mbuf chain. 3087 */ 3088 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3089 BUS_DMA_NOWAIT)) 3090 return(ENOBUFS); 3091 3092 mtag = sc->ethercom.ec_nvlans ? 3093 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3094 3095 for (i = 0; i < dmamap->dm_nsegs; i++) { 3096 f = &sc->bge_rdata->bge_tx_ring[frag]; 3097 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3098 break; 3099 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3100 f->bge_len = dmamap->dm_segs[i].ds_len; 3101 f->bge_flags = csum_flags; 3102 3103 if (mtag != NULL) { 3104 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3105 f->bge_vlan_tag = *(u_int *)(mtag + 1); 3106 } else { 3107 f->bge_vlan_tag = 0; 3108 } 3109 /* 3110 * Sanity check: avoid coming within 16 descriptors 3111 * of the end of the ring. 3112 */ 3113 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3114 return(ENOBUFS); 3115 cur = frag; 3116 BGE_INC(frag, BGE_TX_RING_CNT); 3117 cnt++; 3118 } 3119 3120 if (i < dmamap->dm_nsegs) 3121 return ENOBUFS; 3122 3123 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3124 BUS_DMASYNC_PREWRITE); 3125 3126 if (frag == sc->bge_tx_saved_considx) 3127 return(ENOBUFS); 3128 3129 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3130 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3131 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3132 sc->txdma[cur] = dma; 3133 sc->bge_txcnt += cnt; 3134 3135 *txidx = frag; 3136 3137 return(0); 3138 } 3139 3140 /* 3141 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3142 * to the mbuf data regions directly in the transmit descriptors. 3143 */ 3144 void 3145 bge_start(ifp) 3146 struct ifnet *ifp; 3147 { 3148 struct bge_softc *sc; 3149 struct mbuf *m_head = NULL; 3150 u_int32_t prodidx = 0; 3151 int pkts = 0; 3152 3153 sc = ifp->if_softc; 3154 3155 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3156 return; 3157 3158 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3159 3160 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3161 IFQ_POLL(&ifp->if_snd, m_head); 3162 if (m_head == NULL) 3163 break; 3164 3165 #if 0 3166 /* 3167 * XXX 3168 * safety overkill. If this is a fragmented packet chain 3169 * with delayed TCP/UDP checksums, then only encapsulate 3170 * it if we have enough descriptors to handle the entire 3171 * chain at once. 3172 * (paranoia -- may not actually be needed) 3173 */ 3174 if (m_head->m_flags & M_FIRSTFRAG && 3175 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3176 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3177 m_head->m_pkthdr.csum_data + 16) { 3178 ifp->if_flags |= IFF_OACTIVE; 3179 break; 3180 } 3181 } 3182 #endif 3183 3184 /* 3185 * Pack the data into the transmit ring. If we 3186 * don't have room, set the OACTIVE flag and wait 3187 * for the NIC to drain the ring. 3188 */ 3189 if (bge_encap(sc, m_head, &prodidx)) { 3190 ifp->if_flags |= IFF_OACTIVE; 3191 break; 3192 } 3193 3194 /* now we are committed to transmit the packet */ 3195 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3196 pkts++; 3197 3198 #if NBPFILTER > 0 3199 /* 3200 * If there's a BPF listener, bounce a copy of this frame 3201 * to him. 3202 */ 3203 if (ifp->if_bpf) 3204 bpf_mtap(ifp->if_bpf, m_head); 3205 #endif 3206 } 3207 if (pkts == 0) 3208 return; 3209 3210 /* Transmit */ 3211 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3212 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3213 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3214 3215 /* 3216 * Set a timeout in case the chip goes out to lunch. 3217 */ 3218 ifp->if_timer = 5; 3219 } 3220 3221 int 3222 bge_init(ifp) 3223 struct ifnet *ifp; 3224 { 3225 struct bge_softc *sc = ifp->if_softc; 3226 u_int16_t *m; 3227 int s, error; 3228 3229 s = splnet(); 3230 3231 ifp = &sc->ethercom.ec_if; 3232 3233 /* Cancel pending I/O and flush buffers. */ 3234 bge_stop(sc); 3235 bge_reset(sc); 3236 bge_chipinit(sc); 3237 3238 /* 3239 * Init the various state machines, ring 3240 * control blocks and firmware. 3241 */ 3242 error = bge_blockinit(sc); 3243 if (error != 0) { 3244 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3245 error); 3246 splx(s); 3247 return error; 3248 } 3249 3250 ifp = &sc->ethercom.ec_if; 3251 3252 /* Specify MTU. */ 3253 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3254 ETHER_HDR_LEN + ETHER_CRC_LEN); 3255 3256 /* Load our MAC address. */ 3257 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3258 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3259 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3260 3261 /* Enable or disable promiscuous mode as needed. */ 3262 if (ifp->if_flags & IFF_PROMISC) { 3263 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3264 } else { 3265 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3266 } 3267 3268 /* Program multicast filter. */ 3269 bge_setmulti(sc); 3270 3271 /* Init RX ring. */ 3272 bge_init_rx_ring_std(sc); 3273 3274 /* Init jumbo RX ring. */ 3275 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3276 bge_init_rx_ring_jumbo(sc); 3277 3278 /* Init our RX return ring index */ 3279 sc->bge_rx_saved_considx = 0; 3280 3281 /* Init TX ring. */ 3282 bge_init_tx_ring(sc); 3283 3284 /* Turn on transmitter */ 3285 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3286 3287 /* Turn on receiver */ 3288 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3289 3290 /* Tell firmware we're alive. */ 3291 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3292 3293 /* Enable host interrupts. */ 3294 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3295 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3296 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3297 3298 bge_ifmedia_upd(ifp); 3299 3300 ifp->if_flags |= IFF_RUNNING; 3301 ifp->if_flags &= ~IFF_OACTIVE; 3302 3303 splx(s); 3304 3305 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3306 3307 return 0; 3308 } 3309 3310 /* 3311 * Set media options. 3312 */ 3313 int 3314 bge_ifmedia_upd(ifp) 3315 struct ifnet *ifp; 3316 { 3317 struct bge_softc *sc = ifp->if_softc; 3318 struct mii_data *mii = &sc->bge_mii; 3319 struct ifmedia *ifm = &sc->bge_ifmedia; 3320 3321 /* If this is a 1000baseX NIC, enable the TBI port. */ 3322 if (sc->bge_tbi) { 3323 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3324 return(EINVAL); 3325 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3326 case IFM_AUTO: 3327 break; 3328 case IFM_1000_SX: 3329 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3330 BGE_CLRBIT(sc, BGE_MAC_MODE, 3331 BGE_MACMODE_HALF_DUPLEX); 3332 } else { 3333 BGE_SETBIT(sc, BGE_MAC_MODE, 3334 BGE_MACMODE_HALF_DUPLEX); 3335 } 3336 break; 3337 default: 3338 return(EINVAL); 3339 } 3340 return(0); 3341 } 3342 3343 sc->bge_link = 0; 3344 mii_mediachg(mii); 3345 3346 return(0); 3347 } 3348 3349 /* 3350 * Report current media status. 3351 */ 3352 void 3353 bge_ifmedia_sts(ifp, ifmr) 3354 struct ifnet *ifp; 3355 struct ifmediareq *ifmr; 3356 { 3357 struct bge_softc *sc = ifp->if_softc; 3358 struct mii_data *mii = &sc->bge_mii; 3359 3360 if (sc->bge_tbi) { 3361 ifmr->ifm_status = IFM_AVALID; 3362 ifmr->ifm_active = IFM_ETHER; 3363 if (CSR_READ_4(sc, BGE_MAC_STS) & 3364 BGE_MACSTAT_TBI_PCS_SYNCHED) 3365 ifmr->ifm_status |= IFM_ACTIVE; 3366 ifmr->ifm_active |= IFM_1000_SX; 3367 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3368 ifmr->ifm_active |= IFM_HDX; 3369 else 3370 ifmr->ifm_active |= IFM_FDX; 3371 return; 3372 } 3373 3374 mii_pollstat(mii); 3375 ifmr->ifm_active = mii->mii_media_active; 3376 ifmr->ifm_status = mii->mii_media_status; 3377 } 3378 3379 int 3380 bge_ioctl(ifp, command, data) 3381 struct ifnet *ifp; 3382 u_long command; 3383 caddr_t data; 3384 { 3385 struct bge_softc *sc = ifp->if_softc; 3386 struct ifreq *ifr = (struct ifreq *) data; 3387 int s, error = 0; 3388 struct mii_data *mii; 3389 3390 s = splnet(); 3391 3392 switch(command) { 3393 case SIOCSIFFLAGS: 3394 if (ifp->if_flags & IFF_UP) { 3395 /* 3396 * If only the state of the PROMISC flag changed, 3397 * then just use the 'set promisc mode' command 3398 * instead of reinitializing the entire NIC. Doing 3399 * a full re-init means reloading the firmware and 3400 * waiting for it to start up, which may take a 3401 * second or two. 3402 */ 3403 if (ifp->if_flags & IFF_RUNNING && 3404 ifp->if_flags & IFF_PROMISC && 3405 !(sc->bge_if_flags & IFF_PROMISC)) { 3406 BGE_SETBIT(sc, BGE_RX_MODE, 3407 BGE_RXMODE_RX_PROMISC); 3408 } else if (ifp->if_flags & IFF_RUNNING && 3409 !(ifp->if_flags & IFF_PROMISC) && 3410 sc->bge_if_flags & IFF_PROMISC) { 3411 BGE_CLRBIT(sc, BGE_RX_MODE, 3412 BGE_RXMODE_RX_PROMISC); 3413 } else 3414 bge_init(ifp); 3415 } else { 3416 if (ifp->if_flags & IFF_RUNNING) { 3417 bge_stop(sc); 3418 } 3419 } 3420 sc->bge_if_flags = ifp->if_flags; 3421 error = 0; 3422 break; 3423 case SIOCSIFMEDIA: 3424 case SIOCGIFMEDIA: 3425 if (sc->bge_tbi) { 3426 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3427 command); 3428 } else { 3429 mii = &sc->bge_mii; 3430 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3431 command); 3432 } 3433 error = 0; 3434 break; 3435 default: 3436 error = ether_ioctl(ifp, command, data); 3437 if (error == ENETRESET) { 3438 bge_setmulti(sc); 3439 error = 0; 3440 } 3441 break; 3442 } 3443 3444 splx(s); 3445 3446 return(error); 3447 } 3448 3449 void 3450 bge_watchdog(ifp) 3451 struct ifnet *ifp; 3452 { 3453 struct bge_softc *sc; 3454 3455 sc = ifp->if_softc; 3456 3457 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3458 3459 ifp->if_flags &= ~IFF_RUNNING; 3460 bge_init(ifp); 3461 3462 ifp->if_oerrors++; 3463 } 3464 3465 static void 3466 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3467 { 3468 int i; 3469 3470 BGE_CLRBIT(sc, reg, bit); 3471 3472 for (i = 0; i < BGE_TIMEOUT; i++) { 3473 if ((CSR_READ_4(sc, reg) & bit) == 0) 3474 return; 3475 delay(100); 3476 } 3477 3478 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3479 sc->bge_dev.dv_xname, (u_long) reg, bit); 3480 } 3481 3482 /* 3483 * Stop the adapter and free any mbufs allocated to the 3484 * RX and TX lists. 3485 */ 3486 void 3487 bge_stop(sc) 3488 struct bge_softc *sc; 3489 { 3490 struct ifnet *ifp = &sc->ethercom.ec_if; 3491 3492 callout_stop(&sc->bge_timeout); 3493 3494 /* 3495 * Disable all of the receiver blocks 3496 */ 3497 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3498 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3499 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3500 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3501 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3502 } 3503 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3504 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3505 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3506 3507 /* 3508 * Disable all of the transmit blocks 3509 */ 3510 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3511 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3512 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3513 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3514 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3515 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3516 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3517 } 3518 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3519 3520 /* 3521 * Shut down all of the memory managers and related 3522 * state machines. 3523 */ 3524 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3525 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3526 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3527 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3528 } 3529 3530 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3531 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3532 3533 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3534 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3535 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3536 } 3537 3538 /* Disable host interrupts. */ 3539 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3540 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3541 3542 /* 3543 * Tell firmware we're shutting down. 3544 */ 3545 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3546 3547 /* Free the RX lists. */ 3548 bge_free_rx_ring_std(sc); 3549 3550 /* Free jumbo RX list. */ 3551 bge_free_rx_ring_jumbo(sc); 3552 3553 /* Free TX buffers. */ 3554 bge_free_tx_ring(sc); 3555 3556 /* 3557 * Isolate/power down the PHY. 3558 */ 3559 if (!sc->bge_tbi) 3560 mii_down(&sc->bge_mii); 3561 3562 sc->bge_link = 0; 3563 3564 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3565 3566 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3567 } 3568 3569 /* 3570 * Stop all chip I/O so that the kernel's probe routines don't 3571 * get confused by errant DMAs when rebooting. 3572 */ 3573 void 3574 bge_shutdown(xsc) 3575 void *xsc; 3576 { 3577 struct bge_softc *sc = (struct bge_softc *)xsc; 3578 3579 bge_stop(sc); 3580 bge_reset(sc); 3581 } 3582
Indexes created Mon Sep 22 21:09:42 GMT 2025