if_bge.c revision 1.52
1 /* $NetBSD: if_bge.c,v 1.52 2003/10/23 20:36:36 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.52 2003/10/23 20:36:36 fvdl Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/miidevs.h> 120 #include <dev/mii/brgphyreg.h> 121 122 #include <dev/pci/if_bgereg.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 127 128 int bge_probe(struct device *, struct cfdata *, void *); 129 void bge_attach(struct device *, struct device *, void *); 130 void bge_release_resources(struct bge_softc *); 131 void bge_txeof(struct bge_softc *); 132 void bge_rxeof(struct bge_softc *); 133 134 void bge_tick(void *); 135 void bge_stats_update(struct bge_softc *); 136 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 137 static __inline int bge_cksum_pad(struct mbuf *pkt); 138 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 139 140 int bge_intr(void *); 141 void bge_start(struct ifnet *); 142 int bge_ioctl(struct ifnet *, u_long, caddr_t); 143 int bge_init(struct ifnet *); 144 void bge_stop(struct bge_softc *); 145 void bge_watchdog(struct ifnet *); 146 void bge_shutdown(void *); 147 int bge_ifmedia_upd(struct ifnet *); 148 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 149 150 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 151 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 152 153 void bge_setmulti(struct bge_softc *); 154 155 void bge_handle_events(struct bge_softc *); 156 int bge_alloc_jumbo_mem(struct bge_softc *); 157 void bge_free_jumbo_mem(struct bge_softc *); 158 void *bge_jalloc(struct bge_softc *); 159 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 160 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 161 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 162 int bge_init_rx_ring_std(struct bge_softc *); 163 void bge_free_rx_ring_std(struct bge_softc *); 164 int bge_init_rx_ring_jumbo(struct bge_softc *); 165 void bge_free_rx_ring_jumbo(struct bge_softc *); 166 void bge_free_tx_ring(struct bge_softc *); 167 int bge_init_tx_ring(struct bge_softc *); 168 169 int bge_chipinit(struct bge_softc *); 170 int bge_blockinit(struct bge_softc *); 171 int bge_setpowerstate(struct bge_softc *, int); 172 173 #ifdef notdef 174 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 175 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 176 void bge_vpd_read(struct bge_softc *); 177 #endif 178 179 u_int32_t bge_readmem_ind(struct bge_softc *, int); 180 void bge_writemem_ind(struct bge_softc *, int, int); 181 #ifdef notdef 182 u_int32_t bge_readreg_ind(struct bge_softc *, int); 183 #endif 184 void bge_writereg_ind(struct bge_softc *, int, int); 185 186 int bge_miibus_readreg(struct device *, int, int); 187 void bge_miibus_writereg(struct device *, int, int, int); 188 void bge_miibus_statchg(struct device *); 189 190 void bge_reset(struct bge_softc *); 191 192 void bge_dump_status(struct bge_softc *); 193 void bge_dump_rxbd(struct bge_rx_bd *); 194 195 #define BGE_DEBUG 196 #ifdef BGE_DEBUG 197 #define DPRINTF(x) if (bgedebug) printf x 198 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 199 int bgedebug = 0; 200 #else 201 #define DPRINTF(x) 202 #define DPRINTFN(n,x) 203 #endif 204 205 /* Various chip quirks. */ 206 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 207 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 208 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 209 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 210 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 211 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 212 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 213 #define BGE_QUIRK_5705_CORE 0x00000080 214 215 /* following bugs are common to bcm5700 rev B, all flavours */ 216 #define BGE_QUIRK_5700_COMMON \ 217 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 218 219 CFATTACH_DECL(bge, sizeof(struct bge_softc), 220 bge_probe, bge_attach, NULL, NULL); 221 222 u_int32_t 223 bge_readmem_ind(sc, off) 224 struct bge_softc *sc; 225 int off; 226 { 227 struct pci_attach_args *pa = &(sc->bge_pa); 228 pcireg_t val; 229 230 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 231 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 232 return val; 233 } 234 235 void 236 bge_writemem_ind(sc, off, val) 237 struct bge_softc *sc; 238 int off, val; 239 { 240 struct pci_attach_args *pa = &(sc->bge_pa); 241 242 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 243 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 244 } 245 246 #ifdef notdef 247 u_int32_t 248 bge_readreg_ind(sc, off) 249 struct bge_softc *sc; 250 int off; 251 { 252 struct pci_attach_args *pa = &(sc->bge_pa); 253 254 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 255 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 256 } 257 #endif 258 259 void 260 bge_writereg_ind(sc, off, val) 261 struct bge_softc *sc; 262 int off, val; 263 { 264 struct pci_attach_args *pa = &(sc->bge_pa); 265 266 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 267 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 268 } 269 270 #ifdef notdef 271 u_int8_t 272 bge_vpd_readbyte(sc, addr) 273 struct bge_softc *sc; 274 int addr; 275 { 276 int i; 277 u_int32_t val; 278 struct pci_attach_args *pa = &(sc->bge_pa); 279 280 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 281 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 282 DELAY(10); 283 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 284 BGE_VPD_FLAG) 285 break; 286 } 287 288 if (i == BGE_TIMEOUT) { 289 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 290 return(0); 291 } 292 293 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 294 295 return((val >> ((addr % 4) * 8)) & 0xFF); 296 } 297 298 void 299 bge_vpd_read_res(sc, res, addr) 300 struct bge_softc *sc; 301 struct vpd_res *res; 302 int addr; 303 { 304 int i; 305 u_int8_t *ptr; 306 307 ptr = (u_int8_t *)res; 308 for (i = 0; i < sizeof(struct vpd_res); i++) 309 ptr[i] = bge_vpd_readbyte(sc, i + addr); 310 } 311 312 void 313 bge_vpd_read(sc) 314 struct bge_softc *sc; 315 { 316 int pos = 0, i; 317 struct vpd_res res; 318 319 if (sc->bge_vpd_prodname != NULL) 320 free(sc->bge_vpd_prodname, M_DEVBUF); 321 if (sc->bge_vpd_readonly != NULL) 322 free(sc->bge_vpd_readonly, M_DEVBUF); 323 sc->bge_vpd_prodname = NULL; 324 sc->bge_vpd_readonly = NULL; 325 326 bge_vpd_read_res(sc, &res, pos); 327 328 if (res.vr_id != VPD_RES_ID) { 329 printf("%s: bad VPD resource id: expected %x got %x\n", 330 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 331 return; 332 } 333 334 pos += sizeof(res); 335 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 336 if (sc->bge_vpd_prodname == NULL) 337 panic("bge_vpd_read"); 338 for (i = 0; i < res.vr_len; i++) 339 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 340 sc->bge_vpd_prodname[i] = '\0'; 341 pos += i; 342 343 bge_vpd_read_res(sc, &res, pos); 344 345 if (res.vr_id != VPD_RES_READ) { 346 printf("%s: bad VPD resource id: expected %x got %x\n", 347 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 348 return; 349 } 350 351 pos += sizeof(res); 352 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 353 if (sc->bge_vpd_readonly == NULL) 354 panic("bge_vpd_read"); 355 for (i = 0; i < res.vr_len + 1; i++) 356 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 357 } 358 #endif 359 360 /* 361 * Read a byte of data stored in the EEPROM at address 'addr.' The 362 * BCM570x supports both the traditional bitbang interface and an 363 * auto access interface for reading the EEPROM. We use the auto 364 * access method. 365 */ 366 u_int8_t 367 bge_eeprom_getbyte(sc, addr, dest) 368 struct bge_softc *sc; 369 int addr; 370 u_int8_t *dest; 371 { 372 int i; 373 u_int32_t byte = 0; 374 375 /* 376 * Enable use of auto EEPROM access so we can avoid 377 * having to use the bitbang method. 378 */ 379 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 380 381 /* Reset the EEPROM, load the clock period. */ 382 CSR_WRITE_4(sc, BGE_EE_ADDR, 383 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 384 DELAY(20); 385 386 /* Issue the read EEPROM command. */ 387 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 388 389 /* Wait for completion */ 390 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 391 DELAY(10); 392 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 393 break; 394 } 395 396 if (i == BGE_TIMEOUT) { 397 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 398 return(0); 399 } 400 401 /* Get result. */ 402 byte = CSR_READ_4(sc, BGE_EE_DATA); 403 404 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 405 406 return(0); 407 } 408 409 /* 410 * Read a sequence of bytes from the EEPROM. 411 */ 412 int 413 bge_read_eeprom(sc, dest, off, cnt) 414 struct bge_softc *sc; 415 caddr_t dest; 416 int off; 417 int cnt; 418 { 419 int err = 0, i; 420 u_int8_t byte = 0; 421 422 for (i = 0; i < cnt; i++) { 423 err = bge_eeprom_getbyte(sc, off + i, &byte); 424 if (err) 425 break; 426 *(dest + i) = byte; 427 } 428 429 return(err ? 1 : 0); 430 } 431 432 int 433 bge_miibus_readreg(dev, phy, reg) 434 struct device *dev; 435 int phy, reg; 436 { 437 struct bge_softc *sc = (struct bge_softc *)dev; 438 struct ifnet *ifp; 439 u_int32_t val; 440 u_int32_t saved_autopoll; 441 int i; 442 443 ifp = &sc->ethercom.ec_if; 444 445 /* 446 * Several chips with builtin PHYs will incorrectly answer to 447 * other PHY instances than the builtin PHY at id 1. 448 */ 449 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 450 return(0); 451 452 /* Reading with autopolling on may trigger PCI errors */ 453 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 454 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 455 CSR_WRITE_4(sc, BGE_MI_MODE, 456 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 457 DELAY(40); 458 } 459 460 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 461 BGE_MIPHY(phy)|BGE_MIREG(reg)); 462 463 for (i = 0; i < BGE_TIMEOUT; i++) { 464 val = CSR_READ_4(sc, BGE_MI_COMM); 465 if (!(val & BGE_MICOMM_BUSY)) 466 break; 467 delay(10); 468 } 469 470 if (i == BGE_TIMEOUT) { 471 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 472 val = 0; 473 goto done; 474 } 475 476 val = CSR_READ_4(sc, BGE_MI_COMM); 477 478 done: 479 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 480 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 481 DELAY(40); 482 } 483 484 if (val & BGE_MICOMM_READFAIL) 485 return(0); 486 487 return(val & 0xFFFF); 488 } 489 490 void 491 bge_miibus_writereg(dev, phy, reg, val) 492 struct device *dev; 493 int phy, reg, val; 494 { 495 struct bge_softc *sc = (struct bge_softc *)dev; 496 u_int32_t saved_autopoll; 497 int i; 498 499 /* Touching the PHY while autopolling is on may trigger PCI errors */ 500 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 501 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 502 delay(40); 503 CSR_WRITE_4(sc, BGE_MI_MODE, 504 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 505 delay(10); /* 40 usec is supposed to be adequate */ 506 } 507 508 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 509 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 510 511 for (i = 0; i < BGE_TIMEOUT; i++) { 512 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 513 break; 514 delay(10); 515 } 516 517 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 518 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 519 delay(40); 520 } 521 522 if (i == BGE_TIMEOUT) { 523 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 524 } 525 } 526 527 void 528 bge_miibus_statchg(dev) 529 struct device *dev; 530 { 531 struct bge_softc *sc = (struct bge_softc *)dev; 532 struct mii_data *mii = &sc->bge_mii; 533 534 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 535 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 536 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 537 } else { 538 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 539 } 540 541 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 542 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 543 } else { 544 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 545 } 546 } 547 548 /* 549 * Handle events that have triggered interrupts. 550 */ 551 void 552 bge_handle_events(sc) 553 struct bge_softc *sc; 554 { 555 556 return; 557 } 558 559 /* 560 * Memory management for jumbo frames. 561 */ 562 563 int 564 bge_alloc_jumbo_mem(sc) 565 struct bge_softc *sc; 566 { 567 caddr_t ptr, kva; 568 bus_dma_segment_t seg; 569 int i, rseg, state, error; 570 struct bge_jpool_entry *entry; 571 572 state = error = 0; 573 574 /* Grab a big chunk o' storage. */ 575 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 576 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 577 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 578 return ENOBUFS; 579 } 580 581 state = 1; 582 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 583 BUS_DMA_NOWAIT)) { 584 printf("%s: can't map DMA buffers (%d bytes)\n", 585 sc->bge_dev.dv_xname, (int)BGE_JMEM); 586 error = ENOBUFS; 587 goto out; 588 } 589 590 state = 2; 591 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 592 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 593 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 594 error = ENOBUFS; 595 goto out; 596 } 597 598 state = 3; 599 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 600 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 601 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 602 error = ENOBUFS; 603 goto out; 604 } 605 606 state = 4; 607 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 608 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 609 610 SLIST_INIT(&sc->bge_jfree_listhead); 611 SLIST_INIT(&sc->bge_jinuse_listhead); 612 613 /* 614 * Now divide it up into 9K pieces and save the addresses 615 * in an array. 616 */ 617 ptr = sc->bge_cdata.bge_jumbo_buf; 618 for (i = 0; i < BGE_JSLOTS; i++) { 619 sc->bge_cdata.bge_jslots[i] = ptr; 620 ptr += BGE_JLEN; 621 entry = malloc(sizeof(struct bge_jpool_entry), 622 M_DEVBUF, M_NOWAIT); 623 if (entry == NULL) { 624 printf("%s: no memory for jumbo buffer queue!\n", 625 sc->bge_dev.dv_xname); 626 error = ENOBUFS; 627 goto out; 628 } 629 entry->slot = i; 630 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 631 entry, jpool_entries); 632 } 633 out: 634 if (error != 0) { 635 switch (state) { 636 case 4: 637 bus_dmamap_unload(sc->bge_dmatag, 638 sc->bge_cdata.bge_rx_jumbo_map); 639 case 3: 640 bus_dmamap_destroy(sc->bge_dmatag, 641 sc->bge_cdata.bge_rx_jumbo_map); 642 case 2: 643 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 644 case 1: 645 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 646 break; 647 default: 648 break; 649 } 650 } 651 652 return error; 653 } 654 655 /* 656 * Allocate a jumbo buffer. 657 */ 658 void * 659 bge_jalloc(sc) 660 struct bge_softc *sc; 661 { 662 struct bge_jpool_entry *entry; 663 664 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 665 666 if (entry == NULL) { 667 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 668 return(NULL); 669 } 670 671 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 672 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 673 return(sc->bge_cdata.bge_jslots[entry->slot]); 674 } 675 676 /* 677 * Release a jumbo buffer. 678 */ 679 void 680 bge_jfree(m, buf, size, arg) 681 struct mbuf *m; 682 caddr_t buf; 683 size_t size; 684 void *arg; 685 { 686 struct bge_jpool_entry *entry; 687 struct bge_softc *sc; 688 int i, s; 689 690 /* Extract the softc struct pointer. */ 691 sc = (struct bge_softc *)arg; 692 693 if (sc == NULL) 694 panic("bge_jfree: can't find softc pointer!"); 695 696 /* calculate the slot this buffer belongs to */ 697 698 i = ((caddr_t)buf 699 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 700 701 if ((i < 0) || (i >= BGE_JSLOTS)) 702 panic("bge_jfree: asked to free buffer that we don't manage!"); 703 704 s = splvm(); 705 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 706 if (entry == NULL) 707 panic("bge_jfree: buffer not in use!"); 708 entry->slot = i; 709 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 710 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 711 712 if (__predict_true(m != NULL)) 713 pool_cache_put(&mbpool_cache, m); 714 splx(s); 715 } 716 717 718 /* 719 * Intialize a standard receive ring descriptor. 720 */ 721 int 722 bge_newbuf_std(sc, i, m, dmamap) 723 struct bge_softc *sc; 724 int i; 725 struct mbuf *m; 726 bus_dmamap_t dmamap; 727 { 728 struct mbuf *m_new = NULL; 729 struct bge_rx_bd *r; 730 int error; 731 732 if (dmamap == NULL) { 733 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 734 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 735 if (error != 0) 736 return error; 737 } 738 739 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 740 741 if (m == NULL) { 742 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 743 if (m_new == NULL) { 744 return(ENOBUFS); 745 } 746 747 MCLGET(m_new, M_DONTWAIT); 748 if (!(m_new->m_flags & M_EXT)) { 749 m_freem(m_new); 750 return(ENOBUFS); 751 } 752 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 753 if (!sc->bge_rx_alignment_bug) 754 m_adj(m_new, ETHER_ALIGN); 755 756 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 757 BUS_DMA_READ|BUS_DMA_NOWAIT)) 758 return(ENOBUFS); 759 } else { 760 m_new = m; 761 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 762 m_new->m_data = m_new->m_ext.ext_buf; 763 if (!sc->bge_rx_alignment_bug) 764 m_adj(m_new, ETHER_ALIGN); 765 } 766 767 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 768 r = &sc->bge_rdata->bge_rx_std_ring[i]; 769 bge_set_hostaddr(&r->bge_addr, 770 dmamap->dm_segs[0].ds_addr); 771 r->bge_flags = BGE_RXBDFLAG_END; 772 r->bge_len = m_new->m_len; 773 r->bge_idx = i; 774 775 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 776 offsetof(struct bge_ring_data, bge_rx_std_ring) + 777 i * sizeof (struct bge_rx_bd), 778 sizeof (struct bge_rx_bd), 779 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 780 781 return(0); 782 } 783 784 /* 785 * Initialize a jumbo receive ring descriptor. This allocates 786 * a jumbo buffer from the pool managed internally by the driver. 787 */ 788 int 789 bge_newbuf_jumbo(sc, i, m) 790 struct bge_softc *sc; 791 int i; 792 struct mbuf *m; 793 { 794 struct mbuf *m_new = NULL; 795 struct bge_rx_bd *r; 796 797 if (m == NULL) { 798 caddr_t *buf = NULL; 799 800 /* Allocate the mbuf. */ 801 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 802 if (m_new == NULL) { 803 return(ENOBUFS); 804 } 805 806 /* Allocate the jumbo buffer */ 807 buf = bge_jalloc(sc); 808 if (buf == NULL) { 809 m_freem(m_new); 810 printf("%s: jumbo allocation failed " 811 "-- packet dropped!\n", sc->bge_dev.dv_xname); 812 return(ENOBUFS); 813 } 814 815 /* Attach the buffer to the mbuf. */ 816 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 817 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 818 bge_jfree, sc); 819 } else { 820 m_new = m; 821 m_new->m_data = m_new->m_ext.ext_buf; 822 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 823 } 824 825 if (!sc->bge_rx_alignment_bug) 826 m_adj(m_new, ETHER_ALIGN); 827 /* Set up the descriptor. */ 828 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 829 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 830 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 831 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 832 r->bge_len = m_new->m_len; 833 r->bge_idx = i; 834 835 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 836 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 837 i * sizeof (struct bge_rx_bd), 838 sizeof (struct bge_rx_bd), 839 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 840 841 return(0); 842 } 843 844 /* 845 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 846 * that's 1MB or memory, which is a lot. For now, we fill only the first 847 * 256 ring entries and hope that our CPU is fast enough to keep up with 848 * the NIC. 849 */ 850 int 851 bge_init_rx_ring_std(sc) 852 struct bge_softc *sc; 853 { 854 int i; 855 856 if (sc->bge_flags & BGE_RXRING_VALID) 857 return 0; 858 859 for (i = 0; i < BGE_SSLOTS; i++) { 860 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 861 return(ENOBUFS); 862 } 863 864 sc->bge_std = i - 1; 865 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 866 867 sc->bge_flags |= BGE_RXRING_VALID; 868 869 return(0); 870 } 871 872 void 873 bge_free_rx_ring_std(sc) 874 struct bge_softc *sc; 875 { 876 int i; 877 878 if (!(sc->bge_flags & BGE_RXRING_VALID)) 879 return; 880 881 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 882 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 883 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 884 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 885 bus_dmamap_destroy(sc->bge_dmatag, 886 sc->bge_cdata.bge_rx_std_map[i]); 887 } 888 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 889 sizeof(struct bge_rx_bd)); 890 } 891 892 sc->bge_flags &= ~BGE_RXRING_VALID; 893 } 894 895 int 896 bge_init_rx_ring_jumbo(sc) 897 struct bge_softc *sc; 898 { 899 int i; 900 volatile struct bge_rcb *rcb; 901 902 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 903 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 904 return(ENOBUFS); 905 }; 906 907 sc->bge_jumbo = i - 1; 908 909 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 910 rcb->bge_maxlen_flags = 0; 911 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 912 913 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 914 915 return(0); 916 } 917 918 void 919 bge_free_rx_ring_jumbo(sc) 920 struct bge_softc *sc; 921 { 922 int i; 923 924 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 925 return; 926 927 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 928 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 929 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 930 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 931 } 932 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 933 sizeof(struct bge_rx_bd)); 934 } 935 936 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 937 } 938 939 void 940 bge_free_tx_ring(sc) 941 struct bge_softc *sc; 942 { 943 int i, freed; 944 struct txdmamap_pool_entry *dma; 945 946 if (!(sc->bge_flags & BGE_TXRING_VALID)) 947 return; 948 949 freed = 0; 950 951 for (i = 0; i < BGE_TX_RING_CNT; i++) { 952 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 953 freed++; 954 m_freem(sc->bge_cdata.bge_tx_chain[i]); 955 sc->bge_cdata.bge_tx_chain[i] = NULL; 956 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 957 link); 958 sc->txdma[i] = 0; 959 } 960 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 961 sizeof(struct bge_tx_bd)); 962 } 963 964 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 965 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 966 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 967 free(dma, M_DEVBUF); 968 } 969 970 sc->bge_flags &= ~BGE_TXRING_VALID; 971 } 972 973 int 974 bge_init_tx_ring(sc) 975 struct bge_softc *sc; 976 { 977 int i; 978 bus_dmamap_t dmamap; 979 struct txdmamap_pool_entry *dma; 980 981 if (sc->bge_flags & BGE_TXRING_VALID) 982 return 0; 983 984 sc->bge_txcnt = 0; 985 sc->bge_tx_saved_considx = 0; 986 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 987 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 988 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 989 990 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 991 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 992 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 993 994 SLIST_INIT(&sc->txdma_list); 995 for (i = 0; i < BGE_RSLOTS; i++) { 996 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 997 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 998 &dmamap)) 999 return(ENOBUFS); 1000 if (dmamap == NULL) 1001 panic("dmamap NULL in bge_init_tx_ring"); 1002 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1003 if (dma == NULL) { 1004 printf("%s: can't alloc txdmamap_pool_entry\n", 1005 sc->bge_dev.dv_xname); 1006 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1007 return (ENOMEM); 1008 } 1009 dma->dmamap = dmamap; 1010 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1011 } 1012 1013 sc->bge_flags |= BGE_TXRING_VALID; 1014 1015 return(0); 1016 } 1017 1018 void 1019 bge_setmulti(sc) 1020 struct bge_softc *sc; 1021 { 1022 struct ethercom *ac = &sc->ethercom; 1023 struct ifnet *ifp = &ac->ec_if; 1024 struct ether_multi *enm; 1025 struct ether_multistep step; 1026 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1027 u_int32_t h; 1028 int i; 1029 1030 if (ifp->if_flags & IFF_PROMISC) 1031 goto allmulti; 1032 1033 /* Now program new ones. */ 1034 ETHER_FIRST_MULTI(step, ac, enm); 1035 while (enm != NULL) { 1036 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1037 /* 1038 * We must listen to a range of multicast addresses. 1039 * For now, just accept all multicasts, rather than 1040 * trying to set only those filter bits needed to match 1041 * the range. (At this time, the only use of address 1042 * ranges is for IP multicast routing, for which the 1043 * range is big enough to require all bits set.) 1044 */ 1045 goto allmulti; 1046 } 1047 1048 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1049 1050 /* Just want the 7 least-significant bits. */ 1051 h &= 0x7f; 1052 1053 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1054 ETHER_NEXT_MULTI(step, enm); 1055 } 1056 1057 ifp->if_flags &= ~IFF_ALLMULTI; 1058 goto setit; 1059 1060 allmulti: 1061 ifp->if_flags |= IFF_ALLMULTI; 1062 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1063 1064 setit: 1065 for (i = 0; i < 4; i++) 1066 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1067 } 1068 1069 const int bge_swapbits[] = { 1070 0, 1071 BGE_MODECTL_BYTESWAP_DATA, 1072 BGE_MODECTL_WORDSWAP_DATA, 1073 BGE_MODECTL_BYTESWAP_NONFRAME, 1074 BGE_MODECTL_WORDSWAP_NONFRAME, 1075 1076 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1077 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1078 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1079 1080 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1081 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1082 1083 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1084 1085 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1086 BGE_MODECTL_BYTESWAP_NONFRAME, 1087 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1088 BGE_MODECTL_WORDSWAP_NONFRAME, 1089 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1090 BGE_MODECTL_WORDSWAP_NONFRAME, 1091 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1092 BGE_MODECTL_WORDSWAP_NONFRAME, 1093 1094 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1095 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1096 }; 1097 1098 int bge_swapindex = 0; 1099 1100 /* 1101 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1102 * self-test results. 1103 */ 1104 int 1105 bge_chipinit(sc) 1106 struct bge_softc *sc; 1107 { 1108 u_int32_t cachesize; 1109 int i; 1110 u_int32_t dma_rw_ctl; 1111 struct pci_attach_args *pa = &(sc->bge_pa); 1112 1113 1114 /* Set endianness before we access any non-PCI registers. */ 1115 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1116 BGE_INIT); 1117 1118 /* Set power state to D0. */ 1119 bge_setpowerstate(sc, 0); 1120 1121 /* 1122 * Check the 'ROM failed' bit on the RX CPU to see if 1123 * self-tests passed. 1124 */ 1125 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1126 printf("%s: RX CPU self-diagnostics failed!\n", 1127 sc->bge_dev.dv_xname); 1128 return(ENODEV); 1129 } 1130 1131 /* Clear the MAC control register */ 1132 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1133 1134 /* 1135 * Clear the MAC statistics block in the NIC's 1136 * internal memory. 1137 */ 1138 for (i = BGE_STATS_BLOCK; 1139 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1140 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1141 1142 for (i = BGE_STATUS_BLOCK; 1143 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1144 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1145 1146 /* Set up the PCI DMA control register. */ 1147 if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1148 BGE_PCISTATE_PCI_BUSMODE) { 1149 /* Conventional PCI bus */ 1150 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1151 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1152 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1153 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1154 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1155 dma_rw_ctl |= 0x0F; 1156 } 1157 } else { 1158 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1159 /* PCI-X bus */ 1160 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1161 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1162 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1163 (0x0F); 1164 /* 1165 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1166 * for hardware bugs, which means we should also clear 1167 * the low-order MINDMA bits. In addition, the 5704 1168 * uses a different encoding of read/write watermarks. 1169 */ 1170 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 || 1171 sc->bge_chipid == BGE_CHIPID_BCM5704_A1 || 1172 sc->bge_chipid == BGE_CHIPID_BCM5704_A2 || 1173 sc->bge_chipid == BGE_CHIPID_BCM5704_A3) { 1174 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1175 /* should be 0x1f0000 */ 1176 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1177 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1178 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1179 } 1180 else if ((sc->bge_chipid >> 28) == 1181 (BGE_CHIPID_BCM5703_A0 >> 28)) { 1182 dma_rw_ctl &= 0xfffffff0; 1183 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1184 } 1185 } 1186 1187 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1188 1189 /* 1190 * Set up general mode register. 1191 */ 1192 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1193 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1194 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1195 BGE_MODECTL_RX_NO_PHDR_CSUM); 1196 1197 /* Get cache line size. */ 1198 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1199 1200 /* 1201 * Avoid violating PCI spec on certain chip revs. 1202 */ 1203 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1204 PCIM_CMD_MWIEN) { 1205 switch(cachesize) { 1206 case 1: 1207 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1208 BGE_PCI_WRITE_BNDRY_16BYTES); 1209 break; 1210 case 2: 1211 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1212 BGE_PCI_WRITE_BNDRY_32BYTES); 1213 break; 1214 case 4: 1215 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1216 BGE_PCI_WRITE_BNDRY_64BYTES); 1217 break; 1218 case 8: 1219 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1220 BGE_PCI_WRITE_BNDRY_128BYTES); 1221 break; 1222 case 16: 1223 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1224 BGE_PCI_WRITE_BNDRY_256BYTES); 1225 break; 1226 case 32: 1227 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1228 BGE_PCI_WRITE_BNDRY_512BYTES); 1229 break; 1230 case 64: 1231 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1232 BGE_PCI_WRITE_BNDRY_1024BYTES); 1233 break; 1234 default: 1235 /* Disable PCI memory write and invalidate. */ 1236 #if 0 1237 if (bootverbose) 1238 printf("%s: cache line size %d not " 1239 "supported; disabling PCI MWI\n", 1240 sc->bge_dev.dv_xname, cachesize); 1241 #endif 1242 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1243 PCIM_CMD_MWIEN); 1244 break; 1245 } 1246 } 1247 1248 /* 1249 * Disable memory write invalidate. Apparently it is not supported 1250 * properly by these devices. 1251 */ 1252 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1253 1254 1255 #ifdef __brokenalpha__ 1256 /* 1257 * Must insure that we do not cross an 8K (bytes) boundary 1258 * for DMA reads. Our highest limit is 1K bytes. This is a 1259 * restriction on some ALPHA platforms with early revision 1260 * 21174 PCI chipsets, such as the AlphaPC 164lx 1261 */ 1262 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1263 #endif 1264 1265 /* Set the timer prescaler (always 66MHz) */ 1266 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1267 1268 return(0); 1269 } 1270 1271 int 1272 bge_blockinit(sc) 1273 struct bge_softc *sc; 1274 { 1275 volatile struct bge_rcb *rcb; 1276 bus_size_t rcb_addr; 1277 int i; 1278 struct ifnet *ifp = &sc->ethercom.ec_if; 1279 bge_hostaddr taddr; 1280 1281 /* 1282 * Initialize the memory window pointer register so that 1283 * we can access the first 32K of internal NIC RAM. This will 1284 * allow us to set up the TX send ring RCBs and the RX return 1285 * ring RCBs, plus other things which live in NIC memory. 1286 */ 1287 1288 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1289 BGE_PCI_MEMWIN_BASEADDR, 0); 1290 1291 /* Configure mbuf memory pool */ 1292 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1293 if (sc->bge_extram) { 1294 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1295 BGE_EXT_SSRAM); 1296 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1297 } else { 1298 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1299 BGE_BUFFPOOL_1); 1300 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1301 } 1302 1303 /* Configure DMA resource pool */ 1304 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1305 BGE_DMA_DESCRIPTORS); 1306 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1307 } 1308 1309 /* Configure mbuf pool watermarks */ 1310 #ifdef ORIG_WPAUL_VALUES 1311 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1312 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1313 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1314 #else 1315 /* new broadcom docs strongly recommend these: */ 1316 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1317 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1318 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1319 } else { 1320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1321 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1322 } 1323 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1324 #endif 1325 1326 /* Configure DMA resource watermarks */ 1327 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1328 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1329 1330 /* Enable buffer manager */ 1331 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1332 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1333 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1334 1335 /* Poll for buffer manager start indication */ 1336 for (i = 0; i < BGE_TIMEOUT; i++) { 1337 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1338 break; 1339 DELAY(10); 1340 } 1341 1342 if (i == BGE_TIMEOUT) { 1343 printf("%s: buffer manager failed to start\n", 1344 sc->bge_dev.dv_xname); 1345 return(ENXIO); 1346 } 1347 } 1348 1349 /* Enable flow-through queues */ 1350 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1351 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1352 1353 /* Wait until queue initialization is complete */ 1354 for (i = 0; i < BGE_TIMEOUT; i++) { 1355 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1356 break; 1357 DELAY(10); 1358 } 1359 1360 if (i == BGE_TIMEOUT) { 1361 printf("%s: flow-through queue init failed\n", 1362 sc->bge_dev.dv_xname); 1363 return(ENXIO); 1364 } 1365 1366 /* Initialize the standard RX ring control block */ 1367 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1368 bge_set_hostaddr(&rcb->bge_hostaddr, 1369 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1370 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1371 rcb->bge_maxlen_flags = 1372 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1373 } else { 1374 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1375 } 1376 if (sc->bge_extram) 1377 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1378 else 1379 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1380 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1381 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1382 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1383 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1384 1385 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1386 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1387 } else { 1388 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1389 } 1390 1391 /* 1392 * Initialize the jumbo RX ring control block 1393 * We set the 'ring disabled' bit in the flags 1394 * field until we're actually ready to start 1395 * using this ring (i.e. once we set the MTU 1396 * high enough to require it). 1397 */ 1398 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1399 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1400 bge_set_hostaddr(&rcb->bge_hostaddr, 1401 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1402 rcb->bge_maxlen_flags = 1403 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1404 BGE_RCB_FLAG_RING_DISABLED); 1405 if (sc->bge_extram) 1406 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1407 else 1408 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1409 1410 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1411 rcb->bge_hostaddr.bge_addr_hi); 1412 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1413 rcb->bge_hostaddr.bge_addr_lo); 1414 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1415 rcb->bge_maxlen_flags); 1416 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1417 1418 /* Set up dummy disabled mini ring RCB */ 1419 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1420 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1421 BGE_RCB_FLAG_RING_DISABLED); 1422 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1423 rcb->bge_maxlen_flags); 1424 1425 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1426 offsetof(struct bge_ring_data, bge_info), 1427 sizeof (struct bge_gib), 1428 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1429 } 1430 1431 /* 1432 * Set the BD ring replentish thresholds. The recommended 1433 * values are 1/8th the number of descriptors allocated to 1434 * each ring. 1435 */ 1436 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1437 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1438 1439 /* 1440 * Disable all unused send rings by setting the 'ring disabled' 1441 * bit in the flags field of all the TX send ring control blocks. 1442 * These are located in NIC memory. 1443 */ 1444 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1445 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1446 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1447 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1448 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1449 rcb_addr += sizeof(struct bge_rcb); 1450 } 1451 1452 /* Configure TX RCB 0 (we use only the first ring) */ 1453 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1454 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1455 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1456 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1457 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1458 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1459 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1460 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1461 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1462 } 1463 1464 /* Disable all unused RX return rings */ 1465 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1466 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1467 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1468 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1469 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1470 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1471 BGE_RCB_FLAG_RING_DISABLED)); 1472 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1473 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1474 (i * (sizeof(u_int64_t))), 0); 1475 rcb_addr += sizeof(struct bge_rcb); 1476 } 1477 1478 /* Initialize RX ring indexes */ 1479 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1480 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1481 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1482 1483 /* 1484 * Set up RX return ring 0 1485 * Note that the NIC address for RX return rings is 0x00000000. 1486 * The return rings live entirely within the host, so the 1487 * nicaddr field in the RCB isn't used. 1488 */ 1489 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1490 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1491 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1492 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1493 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1494 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1495 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1496 1497 /* Set random backoff seed for TX */ 1498 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1499 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1500 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1501 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1502 BGE_TX_BACKOFF_SEED_MASK); 1503 1504 /* Set inter-packet gap */ 1505 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1506 1507 /* 1508 * Specify which ring to use for packets that don't match 1509 * any RX rules. 1510 */ 1511 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1512 1513 /* 1514 * Configure number of RX lists. One interrupt distribution 1515 * list, sixteen active lists, one bad frames class. 1516 */ 1517 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1518 1519 /* Inialize RX list placement stats mask. */ 1520 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1521 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1522 1523 /* Disable host coalescing until we get it set up */ 1524 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1525 1526 /* Poll to make sure it's shut down. */ 1527 for (i = 0; i < BGE_TIMEOUT; i++) { 1528 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1529 break; 1530 DELAY(10); 1531 } 1532 1533 if (i == BGE_TIMEOUT) { 1534 printf("%s: host coalescing engine failed to idle\n", 1535 sc->bge_dev.dv_xname); 1536 return(ENXIO); 1537 } 1538 1539 /* Set up host coalescing defaults */ 1540 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1541 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1542 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1543 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1544 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1545 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1546 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1547 } 1548 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1549 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1550 1551 /* Set up address of statistics block */ 1552 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1553 bge_set_hostaddr(&taddr, 1554 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1555 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1556 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1557 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1558 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1559 } 1560 1561 /* Set up address of status block */ 1562 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1563 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1564 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1565 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1566 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1567 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1568 1569 /* Turn on host coalescing state machine */ 1570 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1571 1572 /* Turn on RX BD completion state machine and enable attentions */ 1573 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1574 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1575 1576 /* Turn on RX list placement state machine */ 1577 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1578 1579 /* Turn on RX list selector state machine. */ 1580 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1581 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1582 } 1583 1584 /* Turn on DMA, clear stats */ 1585 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1586 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1587 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1588 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1589 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1590 1591 /* Set misc. local control, enable interrupts on attentions */ 1592 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1593 1594 #ifdef notdef 1595 /* Assert GPIO pins for PHY reset */ 1596 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1597 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1598 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1599 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1600 #endif 1601 1602 #if defined(not_quite_yet) 1603 /* Linux driver enables enable gpio pin #1 on 5700s */ 1604 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1605 sc->bge_local_ctrl_reg |= 1606 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1607 } 1608 #endif 1609 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1610 1611 /* Turn on DMA completion state machine */ 1612 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1613 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1614 } 1615 1616 /* Turn on write DMA state machine */ 1617 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1618 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1619 1620 /* Turn on read DMA state machine */ 1621 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1622 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1623 1624 /* Turn on RX data completion state machine */ 1625 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1626 1627 /* Turn on RX BD initiator state machine */ 1628 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1629 1630 /* Turn on RX data and RX BD initiator state machine */ 1631 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1632 1633 /* Turn on Mbuf cluster free state machine */ 1634 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1635 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1636 } 1637 1638 /* Turn on send BD completion state machine */ 1639 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1640 1641 /* Turn on send data completion state machine */ 1642 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1643 1644 /* Turn on send data initiator state machine */ 1645 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1646 1647 /* Turn on send BD initiator state machine */ 1648 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1649 1650 /* Turn on send BD selector state machine */ 1651 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1652 1653 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1654 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1655 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1656 1657 /* ack/clear link change events */ 1658 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1659 BGE_MACSTAT_CFG_CHANGED); 1660 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1661 1662 /* Enable PHY auto polling (for MII/GMII only) */ 1663 if (sc->bge_tbi) { 1664 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1665 } else { 1666 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1667 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1668 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1669 BGE_EVTENB_MI_INTERRUPT); 1670 } 1671 1672 /* Enable link state change attentions. */ 1673 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1674 1675 return(0); 1676 } 1677 1678 static const struct bge_revision { 1679 uint32_t br_chipid; 1680 uint32_t br_quirks; 1681 const char *br_name; 1682 } bge_revisions[] = { 1683 { BGE_CHIPID_BCM5700_A0, 1684 BGE_QUIRK_LINK_STATE_BROKEN, 1685 "BCM5700 A0" }, 1686 1687 { BGE_CHIPID_BCM5700_A1, 1688 BGE_QUIRK_LINK_STATE_BROKEN, 1689 "BCM5700 A1" }, 1690 1691 { BGE_CHIPID_BCM5700_B0, 1692 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1693 "BCM5700 B0" }, 1694 1695 { BGE_CHIPID_BCM5700_B1, 1696 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1697 "BCM5700 B1" }, 1698 1699 { BGE_CHIPID_BCM5700_B2, 1700 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1701 "BCM5700 B2" }, 1702 1703 /* This is treated like a BCM5700 Bx */ 1704 { BGE_CHIPID_BCM5700_ALTIMA, 1705 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1706 "BCM5700 Altima" }, 1707 1708 { BGE_CHIPID_BCM5700_C0, 1709 0, 1710 "BCM5700 C0" }, 1711 1712 { BGE_CHIPID_BCM5701_A0, 1713 0, /*XXX really, just not known */ 1714 "BCM5701 A0" }, 1715 1716 { BGE_CHIPID_BCM5701_B0, 1717 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1718 "BCM5701 B0" }, 1719 1720 { BGE_CHIPID_BCM5701_B2, 1721 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1722 "BCM5701 B2" }, 1723 1724 { BGE_CHIPID_BCM5701_B5, 1725 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1726 "BCM5701 B5" }, 1727 1728 { BGE_CHIPID_BCM5703_A0, 1729 0, 1730 "BCM5703 A0" }, 1731 1732 { BGE_CHIPID_BCM5703_A1, 1733 0, 1734 "BCM5703 A1" }, 1735 1736 { BGE_CHIPID_BCM5703_A2, 1737 BGE_QUIRK_ONLY_PHY_1, 1738 "BCM5703 A2" }, 1739 1740 { BGE_CHIPID_BCM5704_A0, 1741 BGE_QUIRK_ONLY_PHY_1, 1742 "BCM5704 A0" }, 1743 1744 { BGE_CHIPID_BCM5704_A1, 1745 BGE_QUIRK_ONLY_PHY_1, 1746 "BCM5704 A1" }, 1747 1748 { BGE_CHIPID_BCM5704_A2, 1749 BGE_QUIRK_ONLY_PHY_1, 1750 "BCM5704 A2" }, 1751 1752 { BGE_CHIPID_BCM5704_A3, 1753 BGE_QUIRK_ONLY_PHY_1, 1754 "BCM5704 A3" }, 1755 1756 { BGE_CHIPID_BCM5705_A0, 1757 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1758 "BCM5705 A0" }, 1759 1760 { BGE_CHIPID_BCM5705_A1, 1761 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1762 "BCM5705 A1" }, 1763 1764 { BGE_CHIPID_BCM5705_A2, 1765 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1766 "BCM5705 A2" }, 1767 1768 { BGE_CHIPID_BCM5705_A3, 1769 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1770 "BCM5705 A3" }, 1771 1772 { 0, 0, NULL } 1773 }; 1774 1775 /* 1776 * Some defaults for major revisions, so that newer steppings 1777 * that we don't know about have a shot at working. 1778 */ 1779 static const struct bge_revision bge_majorrevs[] = { 1780 { BGE_ASICREV_BCM5700, 1781 BGE_QUIRK_LINK_STATE_BROKEN, 1782 "unknown BCM5700" }, 1783 1784 { BGE_ASICREV_BCM5701, 1785 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1786 "unknown BCM5701" }, 1787 1788 { BGE_ASICREV_BCM5703, 1789 0, 1790 "unknown BCM5703" }, 1791 1792 { BGE_ASICREV_BCM5704, 1793 BGE_QUIRK_ONLY_PHY_1, 1794 "unknown BCM5704" }, 1795 1796 { BGE_ASICREV_BCM5705, 1797 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1798 "unknown BCM5705" }, 1799 1800 { 0, 1801 0, 1802 NULL } 1803 }; 1804 1805 1806 static const struct bge_revision * 1807 bge_lookup_rev(uint32_t chipid) 1808 { 1809 const struct bge_revision *br; 1810 1811 for (br = bge_revisions; br->br_name != NULL; br++) { 1812 if (br->br_chipid == chipid) 1813 return (br); 1814 } 1815 1816 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1817 if (br->br_chipid == BGE_ASICREV(chipid)) 1818 return (br); 1819 } 1820 1821 return (NULL); 1822 } 1823 1824 static const struct bge_product { 1825 pci_vendor_id_t bp_vendor; 1826 pci_product_id_t bp_product; 1827 const char *bp_name; 1828 } bge_products[] = { 1829 /* 1830 * The BCM5700 documentation seems to indicate that the hardware 1831 * still has the Alteon vendor ID burned into it, though it 1832 * should always be overridden by the value in the EEPROM. We'll 1833 * check for it anyway. 1834 */ 1835 { PCI_VENDOR_ALTEON, 1836 PCI_PRODUCT_ALTEON_BCM5700, 1837 "Broadcom BCM5700 Gigabit Ethernet", 1838 }, 1839 { PCI_VENDOR_ALTEON, 1840 PCI_PRODUCT_ALTEON_BCM5701, 1841 "Broadcom BCM5701 Gigabit Ethernet", 1842 }, 1843 1844 { PCI_VENDOR_ALTIMA, 1845 PCI_PRODUCT_ALTIMA_AC1000, 1846 "Altima AC1000 Gigabit Ethernet", 1847 }, 1848 { PCI_VENDOR_ALTIMA, 1849 PCI_PRODUCT_ALTIMA_AC1001, 1850 "Altima AC1001 Gigabit Ethernet", 1851 }, 1852 { PCI_VENDOR_ALTIMA, 1853 PCI_PRODUCT_ALTIMA_AC9100, 1854 "Altima AC9100 Gigabit Ethernet", 1855 }, 1856 1857 { PCI_VENDOR_BROADCOM, 1858 PCI_PRODUCT_BROADCOM_BCM5700, 1859 "Broadcom BCM5700 Gigabit Ethernet", 1860 }, 1861 { PCI_VENDOR_BROADCOM, 1862 PCI_PRODUCT_BROADCOM_BCM5701, 1863 "Broadcom BCM5701 Gigabit Ethernet", 1864 }, 1865 { PCI_VENDOR_BROADCOM, 1866 PCI_PRODUCT_BROADCOM_BCM5702, 1867 "Broadcom BCM5702 Gigabit Ethernet", 1868 }, 1869 { PCI_VENDOR_BROADCOM, 1870 PCI_PRODUCT_BROADCOM_BCM5702X, 1871 "Broadcom BCM5702X Gigabit Ethernet" }, 1872 1873 { PCI_VENDOR_BROADCOM, 1874 PCI_PRODUCT_BROADCOM_BCM5703, 1875 "Broadcom BCM5703 Gigabit Ethernet", 1876 }, 1877 { PCI_VENDOR_BROADCOM, 1878 PCI_PRODUCT_BROADCOM_BCM5703X, 1879 "Broadcom BCM5703X Gigabit Ethernet", 1880 }, 1881 1882 { PCI_VENDOR_BROADCOM, 1883 PCI_PRODUCT_BROADCOM_BCM5704C, 1884 "Broadcom BCM5704C Dual Gigabit Ethernet", 1885 }, 1886 { PCI_VENDOR_BROADCOM, 1887 PCI_PRODUCT_BROADCOM_BCM5704S, 1888 "Broadcom BCM5704S Dual Gigabit Ethernet", 1889 }, 1890 1891 { PCI_VENDOR_BROADCOM, 1892 PCI_PRODUCT_BROADCOM_BCM5705, 1893 "Broadcom BCM5705 Gigabit Ethernet", 1894 }, 1895 { PCI_VENDOR_BROADCOM, 1896 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 1897 "Broadcom BCM5705 Gigabit Ethernet", 1898 }, 1899 { PCI_VENDOR_BROADCOM, 1900 PCI_PRODUCT_BROADCOM_BCM5705M, 1901 "Broadcom BCM5705M Gigabit Ethernet", 1902 }, 1903 1904 { PCI_VENDOR_BROADCOM, 1905 PCI_PRODUCT_BROADCOM_BCM5901, 1906 "Broadcom BCM5901 Fast Ethernet", 1907 }, 1908 { PCI_VENDOR_BROADCOM, 1909 PCI_PRODUCT_BROADCOM_BCM5901A2, 1910 "Broadcom BCM5901A2 Fast Ethernet", 1911 }, 1912 1913 { PCI_VENDOR_BROADCOM, 1914 PCI_PRODUCT_BROADCOM_BCM5782, 1915 "Broadcom BCM5782 Gigabit Ethernet", 1916 }, 1917 1918 { PCI_VENDOR_SCHNEIDERKOCH, 1919 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1920 "SysKonnect SK-9Dx1 Gigabit Ethernet", 1921 }, 1922 1923 { PCI_VENDOR_3COM, 1924 PCI_PRODUCT_3COM_3C996, 1925 "3Com 3c996 Gigabit Ethernet", 1926 }, 1927 1928 { 0, 1929 0, 1930 NULL }, 1931 }; 1932 1933 static const struct bge_product * 1934 bge_lookup(const struct pci_attach_args *pa) 1935 { 1936 const struct bge_product *bp; 1937 1938 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1939 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1940 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1941 return (bp); 1942 } 1943 1944 return (NULL); 1945 } 1946 1947 int 1948 bge_setpowerstate(sc, powerlevel) 1949 struct bge_softc *sc; 1950 int powerlevel; 1951 { 1952 #ifdef NOTYET 1953 u_int32_t pm_ctl = 0; 1954 1955 /* XXX FIXME: make sure indirect accesses enabled? */ 1956 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 1957 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 1958 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 1959 1960 /* clear the PME_assert bit and power state bits, enable PME */ 1961 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 1962 pm_ctl &= ~PCIM_PSTAT_DMASK; 1963 pm_ctl |= (1 << 8); 1964 1965 if (powerlevel == 0) { 1966 pm_ctl |= PCIM_PSTAT_D0; 1967 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 1968 pm_ctl, 2); 1969 DELAY(10000); 1970 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1971 DELAY(10000); 1972 1973 #ifdef NOTYET 1974 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 1975 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 1976 #endif 1977 DELAY(40); DELAY(40); DELAY(40); 1978 DELAY(10000); /* above not quite adequate on 5700 */ 1979 return 0; 1980 } 1981 1982 1983 /* 1984 * Entering ACPI power states D1-D3 is achieved by wiggling 1985 * GMII gpio pins. Example code assumes all hardware vendors 1986 * followed Broadom's sample pcb layout. Until we verify that 1987 * for all supported OEM cards, states D1-D3 are unsupported. 1988 */ 1989 printf("%s: power state %d unimplemented; check GPIO pins\n", 1990 sc->bge_dev.dv_xname, powerlevel); 1991 #endif 1992 return EOPNOTSUPP; 1993 } 1994 1995 1996 /* 1997 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1998 * against our list and return its name if we find a match. Note 1999 * that since the Broadcom controller contains VPD support, we 2000 * can get the device name string from the controller itself instead 2001 * of the compiled-in string. This is a little slow, but it guarantees 2002 * we'll always announce the right product name. 2003 */ 2004 int 2005 bge_probe(parent, match, aux) 2006 struct device *parent; 2007 struct cfdata *match; 2008 void *aux; 2009 { 2010 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2011 2012 if (bge_lookup(pa) != NULL) 2013 return (1); 2014 2015 return (0); 2016 } 2017 2018 void 2019 bge_attach(parent, self, aux) 2020 struct device *parent, *self; 2021 void *aux; 2022 { 2023 struct bge_softc *sc = (struct bge_softc *)self; 2024 struct pci_attach_args *pa = aux; 2025 const struct bge_product *bp; 2026 const struct bge_revision *br; 2027 pci_chipset_tag_t pc = pa->pa_pc; 2028 pci_intr_handle_t ih; 2029 const char *intrstr = NULL; 2030 bus_dma_segment_t seg; 2031 int rseg; 2032 u_int32_t hwcfg = 0; 2033 u_int32_t mac_addr = 0; 2034 u_int32_t command; 2035 struct ifnet *ifp; 2036 caddr_t kva; 2037 u_char eaddr[ETHER_ADDR_LEN]; 2038 pcireg_t memtype; 2039 bus_addr_t memaddr; 2040 bus_size_t memsize; 2041 u_int32_t pm_ctl; 2042 2043 bp = bge_lookup(pa); 2044 KASSERT(bp != NULL); 2045 2046 sc->bge_pa = *pa; 2047 2048 aprint_naive(": Ethernet controller\n"); 2049 aprint_normal(": %s\n", bp->bp_name); 2050 2051 /* 2052 * Map control/status registers. 2053 */ 2054 DPRINTFN(5, ("Map control/status regs\n")); 2055 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2056 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2057 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2058 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2059 2060 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2061 aprint_error("%s: failed to enable memory mapping!\n", 2062 sc->bge_dev.dv_xname); 2063 return; 2064 } 2065 2066 DPRINTFN(5, ("pci_mem_find\n")); 2067 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2068 switch (memtype) { 2069 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2070 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2071 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2072 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2073 &memaddr, &memsize) == 0) 2074 break; 2075 default: 2076 aprint_error("%s: can't find mem space\n", 2077 sc->bge_dev.dv_xname); 2078 return; 2079 } 2080 2081 DPRINTFN(5, ("pci_intr_map\n")); 2082 if (pci_intr_map(pa, &ih)) { 2083 aprint_error("%s: couldn't map interrupt\n", 2084 sc->bge_dev.dv_xname); 2085 return; 2086 } 2087 2088 DPRINTFN(5, ("pci_intr_string\n")); 2089 intrstr = pci_intr_string(pc, ih); 2090 2091 DPRINTFN(5, ("pci_intr_establish\n")); 2092 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2093 2094 if (sc->bge_intrhand == NULL) { 2095 aprint_error("%s: couldn't establish interrupt", 2096 sc->bge_dev.dv_xname); 2097 if (intrstr != NULL) 2098 aprint_normal(" at %s", intrstr); 2099 aprint_normal("\n"); 2100 return; 2101 } 2102 aprint_normal("%s: interrupting at %s\n", 2103 sc->bge_dev.dv_xname, intrstr); 2104 2105 /* 2106 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2107 * can clobber the chip's PCI config-space power control registers, 2108 * leaving the card in D3 powersave state. 2109 * We do not have memory-mapped registers in this state, 2110 * so force device into D0 state before starting initialization. 2111 */ 2112 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2113 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2114 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2115 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2116 DELAY(1000); /* 27 usec is allegedly sufficent */ 2117 2118 /* Try to reset the chip. */ 2119 DPRINTFN(5, ("bge_reset\n")); 2120 bge_reset(sc); 2121 2122 if (bge_chipinit(sc)) { 2123 aprint_error("%s: chip initialization failed\n", 2124 sc->bge_dev.dv_xname); 2125 bge_release_resources(sc); 2126 return; 2127 } 2128 2129 /* 2130 * Get station address from the EEPROM. 2131 */ 2132 mac_addr = bge_readmem_ind(sc, 0x0c14); 2133 if ((mac_addr >> 16) == 0x484b) { 2134 eaddr[0] = (u_char)(mac_addr >> 8); 2135 eaddr[1] = (u_char)(mac_addr >> 0); 2136 mac_addr = bge_readmem_ind(sc, 0x0c18); 2137 eaddr[2] = (u_char)(mac_addr >> 24); 2138 eaddr[3] = (u_char)(mac_addr >> 16); 2139 eaddr[4] = (u_char)(mac_addr >> 8); 2140 eaddr[5] = (u_char)(mac_addr >> 0); 2141 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2142 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2143 aprint_error("%s: failed to read station address\n", 2144 sc->bge_dev.dv_xname); 2145 bge_release_resources(sc); 2146 return; 2147 } 2148 2149 /* 2150 * Save ASIC rev. Look up any quirks associated with this 2151 * ASIC. 2152 */ 2153 sc->bge_chipid = 2154 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2155 BGE_PCIMISCCTL_ASICREV; 2156 br = bge_lookup_rev(sc->bge_chipid); 2157 2158 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2159 2160 if (br == NULL) { 2161 aprint_normal("unknown ASIC 0x%08x", sc->bge_chipid); 2162 sc->bge_quirks = 0; 2163 } else { 2164 aprint_normal("ASIC %s", br->br_name); 2165 sc->bge_quirks |= br->br_quirks; 2166 } 2167 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2168 2169 /* Allocate the general information block and ring buffers. */ 2170 if (pci_dma64_available(pa)) 2171 sc->bge_dmatag = pa->pa_dmat64; 2172 else 2173 sc->bge_dmatag = pa->pa_dmat; 2174 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2175 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2176 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2177 aprint_error("%s: can't alloc rx buffers\n", 2178 sc->bge_dev.dv_xname); 2179 return; 2180 } 2181 DPRINTFN(5, ("bus_dmamem_map\n")); 2182 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2183 sizeof(struct bge_ring_data), &kva, 2184 BUS_DMA_NOWAIT)) { 2185 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2186 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2187 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2188 return; 2189 } 2190 DPRINTFN(5, ("bus_dmamem_create\n")); 2191 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2192 sizeof(struct bge_ring_data), 0, 2193 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2194 aprint_error("%s: can't create DMA map\n", 2195 sc->bge_dev.dv_xname); 2196 bus_dmamem_unmap(sc->bge_dmatag, kva, 2197 sizeof(struct bge_ring_data)); 2198 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2199 return; 2200 } 2201 DPRINTFN(5, ("bus_dmamem_load\n")); 2202 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2203 sizeof(struct bge_ring_data), NULL, 2204 BUS_DMA_NOWAIT)) { 2205 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2206 bus_dmamem_unmap(sc->bge_dmatag, kva, 2207 sizeof(struct bge_ring_data)); 2208 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2209 return; 2210 } 2211 2212 DPRINTFN(5, ("bzero\n")); 2213 sc->bge_rdata = (struct bge_ring_data *)kva; 2214 2215 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2216 2217 /* Try to allocate memory for jumbo buffers. */ 2218 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2219 if (bge_alloc_jumbo_mem(sc)) { 2220 aprint_error("%s: jumbo buffer allocation failed\n", 2221 sc->bge_dev.dv_xname); 2222 } else 2223 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2224 } 2225 2226 /* Set default tuneable values. */ 2227 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2228 sc->bge_rx_coal_ticks = 150; 2229 sc->bge_rx_max_coal_bds = 64; 2230 #ifdef ORIG_WPAUL_VALUES 2231 sc->bge_tx_coal_ticks = 150; 2232 sc->bge_tx_max_coal_bds = 128; 2233 #else 2234 sc->bge_tx_coal_ticks = 300; 2235 sc->bge_tx_max_coal_bds = 400; 2236 #endif 2237 2238 /* Set up ifnet structure */ 2239 ifp = &sc->ethercom.ec_if; 2240 ifp->if_softc = sc; 2241 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2242 ifp->if_ioctl = bge_ioctl; 2243 ifp->if_start = bge_start; 2244 ifp->if_init = bge_init; 2245 ifp->if_watchdog = bge_watchdog; 2246 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2247 IFQ_SET_READY(&ifp->if_snd); 2248 DPRINTFN(5, ("bcopy\n")); 2249 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2250 2251 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2252 sc->ethercom.ec_if.if_capabilities |= 2253 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 2254 sc->ethercom.ec_capabilities |= 2255 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2256 2257 /* 2258 * Do MII setup. 2259 */ 2260 DPRINTFN(5, ("mii setup\n")); 2261 sc->bge_mii.mii_ifp = ifp; 2262 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2263 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2264 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2265 2266 /* 2267 * Figure out what sort of media we have by checking the 2268 * hardware config word in the first 32k of NIC internal memory, 2269 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2270 * cards, this value appears to be unset. If that's the 2271 * case, we have to rely on identifying the NIC by its PCI 2272 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2273 */ 2274 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2275 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2276 } else { 2277 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2278 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2279 hwcfg = be32toh(hwcfg); 2280 } 2281 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2282 sc->bge_tbi = 1; 2283 2284 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2285 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2286 SK_SUBSYSID_9D41) 2287 sc->bge_tbi = 1; 2288 2289 if (sc->bge_tbi) { 2290 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2291 bge_ifmedia_sts); 2292 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2293 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2294 0, NULL); 2295 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2296 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2297 } else { 2298 /* 2299 * Do transceiver setup. 2300 */ 2301 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2302 bge_ifmedia_sts); 2303 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2304 MII_PHY_ANY, MII_OFFSET_ANY, 0); 2305 2306 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2307 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2308 ifmedia_add(&sc->bge_mii.mii_media, 2309 IFM_ETHER|IFM_MANUAL, 0, NULL); 2310 ifmedia_set(&sc->bge_mii.mii_media, 2311 IFM_ETHER|IFM_MANUAL); 2312 } else 2313 ifmedia_set(&sc->bge_mii.mii_media, 2314 IFM_ETHER|IFM_AUTO); 2315 } 2316 2317 /* 2318 * When using the BCM5701 in PCI-X mode, data corruption has 2319 * been observed in the first few bytes of some received packets. 2320 * Aligning the packet buffer in memory eliminates the corruption. 2321 * Unfortunately, this misaligns the packet payloads. On platforms 2322 * which do not support unaligned accesses, we will realign the 2323 * payloads by copying the received packets. 2324 */ 2325 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2326 /* If in PCI-X mode, work around the alignment bug. */ 2327 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2328 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2329 BGE_PCISTATE_PCI_BUSSPEED) 2330 sc->bge_rx_alignment_bug = 1; 2331 } 2332 2333 /* 2334 * Call MI attach routine. 2335 */ 2336 DPRINTFN(5, ("if_attach\n")); 2337 if_attach(ifp); 2338 DPRINTFN(5, ("ether_ifattach\n")); 2339 ether_ifattach(ifp, eaddr); 2340 DPRINTFN(5, ("callout_init\n")); 2341 callout_init(&sc->bge_timeout); 2342 } 2343 2344 void 2345 bge_release_resources(sc) 2346 struct bge_softc *sc; 2347 { 2348 if (sc->bge_vpd_prodname != NULL) 2349 free(sc->bge_vpd_prodname, M_DEVBUF); 2350 2351 if (sc->bge_vpd_readonly != NULL) 2352 free(sc->bge_vpd_readonly, M_DEVBUF); 2353 } 2354 2355 void 2356 bge_reset(sc) 2357 struct bge_softc *sc; 2358 { 2359 struct pci_attach_args *pa = &sc->bge_pa; 2360 u_int32_t cachesize, command, pcistate; 2361 int i, val = 0; 2362 2363 /* Save some important PCI state. */ 2364 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2365 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2366 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2367 2368 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2369 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2370 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2371 2372 /* Issue global reset */ 2373 bge_writereg_ind(sc, BGE_MISC_CFG, 2374 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2375 2376 DELAY(1000); 2377 2378 /* Reset some of the PCI state that got zapped by reset */ 2379 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2380 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2381 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2382 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2383 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2384 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2385 2386 /* Enable memory arbiter. */ 2387 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2388 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2389 } 2390 2391 /* 2392 * Prevent PXE restart: write a magic number to the 2393 * general communications memory at 0xB50. 2394 */ 2395 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2396 2397 /* 2398 * Poll the value location we just wrote until 2399 * we see the 1's complement of the magic number. 2400 * This indicates that the firmware initialization 2401 * is complete. 2402 */ 2403 for (i = 0; i < 750; i++) { 2404 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2405 if (val == ~BGE_MAGIC_NUMBER) 2406 break; 2407 DELAY(1000); 2408 } 2409 2410 if (i == 750) { 2411 printf("%s: firmware handshake timed out, val = %x\n", 2412 sc->bge_dev.dv_xname, val); 2413 return; 2414 } 2415 2416 /* 2417 * XXX Wait for the value of the PCISTATE register to 2418 * return to its original pre-reset state. This is a 2419 * fairly good indicator of reset completion. If we don't 2420 * wait for the reset to fully complete, trying to read 2421 * from the device's non-PCI registers may yield garbage 2422 * results. 2423 */ 2424 for (i = 0; i < BGE_TIMEOUT; i++) { 2425 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2426 pcistate) 2427 break; 2428 DELAY(10); 2429 } 2430 2431 /* Enable memory arbiter. */ 2432 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2433 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2434 } 2435 2436 /* Fix up byte swapping */ 2437 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2438 2439 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2440 2441 DELAY(10000); 2442 } 2443 2444 /* 2445 * Frame reception handling. This is called if there's a frame 2446 * on the receive return list. 2447 * 2448 * Note: we have to be able to handle two possibilities here: 2449 * 1) the frame is from the jumbo recieve ring 2450 * 2) the frame is from the standard receive ring 2451 */ 2452 2453 void 2454 bge_rxeof(sc) 2455 struct bge_softc *sc; 2456 { 2457 struct ifnet *ifp; 2458 int stdcnt = 0, jumbocnt = 0; 2459 int have_tag = 0; 2460 u_int16_t vlan_tag = 0; 2461 bus_dmamap_t dmamap; 2462 bus_addr_t offset, toff; 2463 bus_size_t tlen; 2464 int tosync; 2465 2466 ifp = &sc->ethercom.ec_if; 2467 2468 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2469 offsetof(struct bge_ring_data, bge_status_block), 2470 sizeof (struct bge_status_block), 2471 BUS_DMASYNC_POSTREAD); 2472 2473 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2474 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2475 sc->bge_rx_saved_considx; 2476 2477 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2478 2479 if (tosync < 0) { 2480 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2481 sizeof (struct bge_rx_bd); 2482 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2483 toff, tlen, BUS_DMASYNC_POSTREAD); 2484 tosync = -tosync; 2485 } 2486 2487 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2488 offset, tosync * sizeof (struct bge_rx_bd), 2489 BUS_DMASYNC_POSTREAD); 2490 2491 while(sc->bge_rx_saved_considx != 2492 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2493 struct bge_rx_bd *cur_rx; 2494 u_int32_t rxidx; 2495 struct mbuf *m = NULL; 2496 2497 cur_rx = &sc->bge_rdata-> 2498 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2499 2500 rxidx = cur_rx->bge_idx; 2501 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2502 2503 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2504 have_tag = 1; 2505 vlan_tag = cur_rx->bge_vlan_tag; 2506 } 2507 2508 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2509 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2510 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2511 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2512 jumbocnt++; 2513 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2514 ifp->if_ierrors++; 2515 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2516 continue; 2517 } 2518 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2519 NULL)== ENOBUFS) { 2520 ifp->if_ierrors++; 2521 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2522 continue; 2523 } 2524 } else { 2525 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2526 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2527 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2528 stdcnt++; 2529 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2530 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2531 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2532 ifp->if_ierrors++; 2533 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2534 continue; 2535 } 2536 if (bge_newbuf_std(sc, sc->bge_std, 2537 NULL, dmamap) == ENOBUFS) { 2538 ifp->if_ierrors++; 2539 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2540 continue; 2541 } 2542 } 2543 2544 ifp->if_ipackets++; 2545 #ifndef __NO_STRICT_ALIGNMENT 2546 /* 2547 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2548 * the Rx buffer has the layer-2 header unaligned. 2549 * If our CPU requires alignment, re-align by copying. 2550 */ 2551 if (sc->bge_rx_alignment_bug) { 2552 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2553 cur_rx->bge_len); 2554 m->m_data += ETHER_ALIGN; 2555 } 2556 #endif 2557 2558 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2559 m->m_pkthdr.rcvif = ifp; 2560 2561 #if NBPFILTER > 0 2562 /* 2563 * Handle BPF listeners. Let the BPF user see the packet. 2564 */ 2565 if (ifp->if_bpf) 2566 bpf_mtap(ifp->if_bpf, m); 2567 #endif 2568 2569 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2570 2571 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2572 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2573 /* 2574 * Rx transport checksum-offload may also 2575 * have bugs with packets which, when transmitted, 2576 * were `runts' requiring padding. 2577 */ 2578 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2579 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2580 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2581 m->m_pkthdr.csum_data = 2582 cur_rx->bge_tcp_udp_csum; 2583 m->m_pkthdr.csum_flags |= 2584 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2585 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2586 } 2587 2588 /* 2589 * If we received a packet with a vlan tag, pass it 2590 * to vlan_input() instead of ether_input(). 2591 */ 2592 if (have_tag) { 2593 struct m_tag *mtag; 2594 2595 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2596 M_NOWAIT); 2597 if (mtag != NULL) { 2598 *(u_int *)(mtag + 1) = vlan_tag; 2599 m_tag_prepend(m, mtag); 2600 have_tag = vlan_tag = 0; 2601 } else { 2602 printf("%s: no mbuf for tag\n", ifp->if_xname); 2603 m_freem(m); 2604 have_tag = vlan_tag = 0; 2605 continue; 2606 } 2607 } 2608 (*ifp->if_input)(ifp, m); 2609 } 2610 2611 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2612 if (stdcnt) 2613 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2614 if (jumbocnt) 2615 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2616 } 2617 2618 void 2619 bge_txeof(sc) 2620 struct bge_softc *sc; 2621 { 2622 struct bge_tx_bd *cur_tx = NULL; 2623 struct ifnet *ifp; 2624 struct txdmamap_pool_entry *dma; 2625 bus_addr_t offset, toff; 2626 bus_size_t tlen; 2627 int tosync; 2628 struct mbuf *m; 2629 2630 ifp = &sc->ethercom.ec_if; 2631 2632 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2633 offsetof(struct bge_ring_data, bge_status_block), 2634 sizeof (struct bge_status_block), 2635 BUS_DMASYNC_POSTREAD); 2636 2637 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2638 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2639 sc->bge_tx_saved_considx; 2640 2641 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2642 2643 if (tosync < 0) { 2644 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2645 sizeof (struct bge_tx_bd); 2646 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2647 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2648 tosync = -tosync; 2649 } 2650 2651 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2652 offset, tosync * sizeof (struct bge_tx_bd), 2653 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2654 2655 /* 2656 * Go through our tx ring and free mbufs for those 2657 * frames that have been sent. 2658 */ 2659 while (sc->bge_tx_saved_considx != 2660 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2661 u_int32_t idx = 0; 2662 2663 idx = sc->bge_tx_saved_considx; 2664 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2665 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2666 ifp->if_opackets++; 2667 m = sc->bge_cdata.bge_tx_chain[idx]; 2668 if (m != NULL) { 2669 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2670 dma = sc->txdma[idx]; 2671 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2672 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2673 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2674 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2675 sc->txdma[idx] = NULL; 2676 2677 m_freem(m); 2678 } 2679 sc->bge_txcnt--; 2680 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2681 ifp->if_timer = 0; 2682 } 2683 2684 if (cur_tx != NULL) 2685 ifp->if_flags &= ~IFF_OACTIVE; 2686 } 2687 2688 int 2689 bge_intr(xsc) 2690 void *xsc; 2691 { 2692 struct bge_softc *sc; 2693 struct ifnet *ifp; 2694 2695 sc = xsc; 2696 ifp = &sc->ethercom.ec_if; 2697 2698 #ifdef notdef 2699 /* Avoid this for now -- checking this register is expensive. */ 2700 /* Make sure this is really our interrupt. */ 2701 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2702 return (0); 2703 #endif 2704 /* Ack interrupt and stop others from occuring. */ 2705 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2706 2707 /* 2708 * Process link state changes. 2709 * Grrr. The link status word in the status block does 2710 * not work correctly on the BCM5700 rev AX and BX chips, 2711 * according to all avaibable information. Hence, we have 2712 * to enable MII interrupts in order to properly obtain 2713 * async link changes. Unfortunately, this also means that 2714 * we have to read the MAC status register to detect link 2715 * changes, thereby adding an additional register access to 2716 * the interrupt handler. 2717 */ 2718 2719 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2720 u_int32_t status; 2721 2722 status = CSR_READ_4(sc, BGE_MAC_STS); 2723 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2724 sc->bge_link = 0; 2725 callout_stop(&sc->bge_timeout); 2726 bge_tick(sc); 2727 /* Clear the interrupt */ 2728 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2729 BGE_EVTENB_MI_INTERRUPT); 2730 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2731 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2732 BRGPHY_INTRS); 2733 } 2734 } else { 2735 if (sc->bge_rdata->bge_status_block.bge_status & 2736 BGE_STATFLAG_LINKSTATE_CHANGED) { 2737 sc->bge_link = 0; 2738 callout_stop(&sc->bge_timeout); 2739 bge_tick(sc); 2740 /* Clear the interrupt */ 2741 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2742 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2743 BGE_MACSTAT_LINK_CHANGED); 2744 } 2745 } 2746 2747 if (ifp->if_flags & IFF_RUNNING) { 2748 /* Check RX return ring producer/consumer */ 2749 bge_rxeof(sc); 2750 2751 /* Check TX ring producer/consumer */ 2752 bge_txeof(sc); 2753 } 2754 2755 bge_handle_events(sc); 2756 2757 /* Re-enable interrupts. */ 2758 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2759 2760 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2761 bge_start(ifp); 2762 2763 return (1); 2764 } 2765 2766 void 2767 bge_tick(xsc) 2768 void *xsc; 2769 { 2770 struct bge_softc *sc = xsc; 2771 struct mii_data *mii = &sc->bge_mii; 2772 struct ifmedia *ifm = NULL; 2773 struct ifnet *ifp = &sc->ethercom.ec_if; 2774 int s; 2775 2776 s = splnet(); 2777 2778 bge_stats_update(sc); 2779 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2780 if (sc->bge_link) { 2781 splx(s); 2782 return; 2783 } 2784 2785 if (sc->bge_tbi) { 2786 ifm = &sc->bge_ifmedia; 2787 if (CSR_READ_4(sc, BGE_MAC_STS) & 2788 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2789 sc->bge_link++; 2790 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2791 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2792 bge_start(ifp); 2793 } 2794 splx(s); 2795 return; 2796 } 2797 2798 mii_tick(mii); 2799 2800 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2801 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2802 sc->bge_link++; 2803 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2804 bge_start(ifp); 2805 } 2806 2807 splx(s); 2808 } 2809 2810 void 2811 bge_stats_update(sc) 2812 struct bge_softc *sc; 2813 { 2814 struct ifnet *ifp = &sc->ethercom.ec_if; 2815 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2816 bus_size_t rstats = BGE_RX_STATS; 2817 2818 #define READ_RSTAT(sc, stats, stat) \ 2819 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 2820 2821 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2822 ifp->if_collisions += 2823 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 2824 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 2825 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 2826 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 2827 return; 2828 } 2829 2830 #undef READ_RSTAT 2831 #define READ_STAT(sc, stats, stat) \ 2832 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2833 2834 ifp->if_collisions += 2835 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2836 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2837 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2838 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2839 ifp->if_collisions; 2840 2841 #undef READ_STAT 2842 2843 #ifdef notdef 2844 ifp->if_collisions += 2845 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2846 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2847 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2848 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2849 ifp->if_collisions; 2850 #endif 2851 } 2852 2853 /* 2854 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2855 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2856 * but when such padded frames employ the bge IP/TCP checksum offload, 2857 * the hardware checksum assist gives incorrect results (possibly 2858 * from incorporating its own padding into the UDP/TCP checksum; who knows). 2859 * If we pad such runts with zeros, the onboard checksum comes out correct. 2860 */ 2861 static __inline int 2862 bge_cksum_pad(struct mbuf *pkt) 2863 { 2864 struct mbuf *last = NULL; 2865 int padlen; 2866 2867 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 2868 2869 /* if there's only the packet-header and we can pad there, use it. */ 2870 if (pkt->m_pkthdr.len == pkt->m_len && 2871 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 2872 last = pkt; 2873 } else { 2874 /* 2875 * Walk packet chain to find last mbuf. We will either 2876 * pad there, or append a new mbuf and pad it 2877 * (thus perhaps avoiding the bcm5700 dma-min bug). 2878 */ 2879 for (last = pkt; last->m_next != NULL; last = last->m_next) { 2880 (void) 0; /* do nothing*/ 2881 } 2882 2883 /* `last' now points to last in chain. */ 2884 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 2885 (void) 0; /* we can pad here, in-place. */ 2886 } else { 2887 /* Allocate new empty mbuf, pad it. Compact later. */ 2888 struct mbuf *n; 2889 MGET(n, M_DONTWAIT, MT_DATA); 2890 n->m_len = 0; 2891 last->m_next = n; 2892 last = n; 2893 } 2894 } 2895 2896 #ifdef DEBUG 2897 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 2898 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 2899 #endif 2900 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 2901 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 2902 last->m_len += padlen; 2903 pkt->m_pkthdr.len += padlen; 2904 return 0; 2905 } 2906 2907 /* 2908 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 2909 */ 2910 static __inline int 2911 bge_compact_dma_runt(struct mbuf *pkt) 2912 { 2913 struct mbuf *m, *prev; 2914 int totlen, prevlen; 2915 2916 prev = NULL; 2917 totlen = 0; 2918 prevlen = -1; 2919 2920 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 2921 int mlen = m->m_len; 2922 int shortfall = 8 - mlen ; 2923 2924 totlen += mlen; 2925 if (mlen == 0) { 2926 continue; 2927 } 2928 if (mlen >= 8) 2929 continue; 2930 2931 /* If we get here, mbuf data is too small for DMA engine. 2932 * Try to fix by shuffling data to prev or next in chain. 2933 * If that fails, do a compacting deep-copy of the whole chain. 2934 */ 2935 2936 /* Internal frag. If fits in prev, copy it there. */ 2937 if (prev && !M_READONLY(prev) && 2938 M_TRAILINGSPACE(prev) >= m->m_len) { 2939 bcopy(m->m_data, 2940 prev->m_data+prev->m_len, 2941 mlen); 2942 prev->m_len += mlen; 2943 m->m_len = 0; 2944 /* XXX stitch chain */ 2945 prev->m_next = m_free(m); 2946 m = prev; 2947 continue; 2948 } 2949 else if (m->m_next != NULL && !M_READONLY(m) && 2950 M_TRAILINGSPACE(m) >= shortfall && 2951 m->m_next->m_len >= (8 + shortfall)) { 2952 /* m is writable and have enough data in next, pull up. */ 2953 2954 bcopy(m->m_next->m_data, 2955 m->m_data+m->m_len, 2956 shortfall); 2957 m->m_len += shortfall; 2958 m->m_next->m_len -= shortfall; 2959 m->m_next->m_data += shortfall; 2960 } 2961 else if (m->m_next == NULL || 1) { 2962 /* Got a runt at the very end of the packet. 2963 * borrow data from the tail of the preceding mbuf and 2964 * update its length in-place. (The original data is still 2965 * valid, so we can do this even if prev is not writable.) 2966 */ 2967 2968 /* if we'd make prev a runt, just move all of its data. */ 2969 #ifdef DEBUG 2970 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 2971 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 2972 #endif 2973 if ((prev->m_len - shortfall) < 8) 2974 shortfall = prev->m_len; 2975 2976 #ifdef notyet /* just do the safe slow thing for now */ 2977 if (!M_READONLY(m)) { 2978 if (M_LEADINGSPACE(m) < shorfall) { 2979 void *m_dat; 2980 m_dat = (m->m_flags & M_PKTHDR) ? 2981 m->m_pktdat : m->dat; 2982 memmove(m_dat, mtod(m, void*), m->m_len); 2983 m->m_data = m_dat; 2984 } 2985 } else 2986 #endif /* just do the safe slow thing */ 2987 { 2988 struct mbuf * n = NULL; 2989 int newprevlen = prev->m_len - shortfall; 2990 2991 MGET(n, M_NOWAIT, MT_DATA); 2992 if (n == NULL) 2993 return ENOBUFS; 2994 KASSERT(m->m_len + shortfall < MLEN 2995 /*, 2996 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 2997 2998 /* first copy the data we're stealing from prev */ 2999 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3000 3001 /* update prev->m_len accordingly */ 3002 prev->m_len -= shortfall; 3003 3004 /* copy data from runt m */ 3005 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3006 3007 /* n holds what we stole from prev, plus m */ 3008 n->m_len = shortfall + m->m_len; 3009 3010 /* stitch n into chain and free m */ 3011 n->m_next = m->m_next; 3012 prev->m_next = n; 3013 /* KASSERT(m->m_next == NULL); */ 3014 m->m_next = NULL; 3015 m_free(m); 3016 m = n; /* for continuing loop */ 3017 } 3018 } 3019 prevlen = m->m_len; 3020 } 3021 return 0; 3022 } 3023 3024 /* 3025 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3026 * pointers to descriptors. 3027 */ 3028 int 3029 bge_encap(sc, m_head, txidx) 3030 struct bge_softc *sc; 3031 struct mbuf *m_head; 3032 u_int32_t *txidx; 3033 { 3034 struct bge_tx_bd *f = NULL; 3035 u_int32_t frag, cur, cnt = 0; 3036 u_int16_t csum_flags = 0; 3037 struct txdmamap_pool_entry *dma; 3038 bus_dmamap_t dmamap; 3039 int i = 0; 3040 struct m_tag *mtag; 3041 3042 cur = frag = *txidx; 3043 3044 if (m_head->m_pkthdr.csum_flags) { 3045 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3046 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3047 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3048 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3049 } 3050 3051 /* 3052 * If we were asked to do an outboard checksum, and the NIC 3053 * has the bug where it sometimes adds in the Ethernet padding, 3054 * explicitly pad with zeros so the cksum will be correct either way. 3055 * (For now, do this for all chip versions, until newer 3056 * are confirmed to not require the workaround.) 3057 */ 3058 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3059 #ifdef notyet 3060 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3061 #endif 3062 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3063 goto check_dma_bug; 3064 3065 if (bge_cksum_pad(m_head) != 0) 3066 return ENOBUFS; 3067 3068 check_dma_bug: 3069 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3070 goto doit; 3071 /* 3072 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3073 * less than eight bytes. If we encounter a teeny mbuf 3074 * at the end of a chain, we can pad. Otherwise, copy. 3075 */ 3076 if (bge_compact_dma_runt(m_head) != 0) 3077 return ENOBUFS; 3078 3079 doit: 3080 dma = SLIST_FIRST(&sc->txdma_list); 3081 if (dma == NULL) 3082 return ENOBUFS; 3083 dmamap = dma->dmamap; 3084 3085 /* 3086 * Start packing the mbufs in this chain into 3087 * the fragment pointers. Stop when we run out 3088 * of fragments or hit the end of the mbuf chain. 3089 */ 3090 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3091 BUS_DMA_NOWAIT)) 3092 return(ENOBUFS); 3093 3094 mtag = sc->ethercom.ec_nvlans ? 3095 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3096 3097 for (i = 0; i < dmamap->dm_nsegs; i++) { 3098 f = &sc->bge_rdata->bge_tx_ring[frag]; 3099 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3100 break; 3101 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3102 f->bge_len = dmamap->dm_segs[i].ds_len; 3103 f->bge_flags = csum_flags; 3104 3105 if (mtag != NULL) { 3106 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3107 f->bge_vlan_tag = *(u_int *)(mtag + 1); 3108 } else { 3109 f->bge_vlan_tag = 0; 3110 } 3111 /* 3112 * Sanity check: avoid coming within 16 descriptors 3113 * of the end of the ring. 3114 */ 3115 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3116 return(ENOBUFS); 3117 cur = frag; 3118 BGE_INC(frag, BGE_TX_RING_CNT); 3119 cnt++; 3120 } 3121 3122 if (i < dmamap->dm_nsegs) 3123 return ENOBUFS; 3124 3125 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3126 BUS_DMASYNC_PREWRITE); 3127 3128 if (frag == sc->bge_tx_saved_considx) 3129 return(ENOBUFS); 3130 3131 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3132 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3133 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3134 sc->txdma[cur] = dma; 3135 sc->bge_txcnt += cnt; 3136 3137 *txidx = frag; 3138 3139 return(0); 3140 } 3141 3142 /* 3143 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3144 * to the mbuf data regions directly in the transmit descriptors. 3145 */ 3146 void 3147 bge_start(ifp) 3148 struct ifnet *ifp; 3149 { 3150 struct bge_softc *sc; 3151 struct mbuf *m_head = NULL; 3152 u_int32_t prodidx = 0; 3153 int pkts = 0; 3154 3155 sc = ifp->if_softc; 3156 3157 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3158 return; 3159 3160 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3161 3162 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3163 IFQ_POLL(&ifp->if_snd, m_head); 3164 if (m_head == NULL) 3165 break; 3166 3167 #if 0 3168 /* 3169 * XXX 3170 * safety overkill. If this is a fragmented packet chain 3171 * with delayed TCP/UDP checksums, then only encapsulate 3172 * it if we have enough descriptors to handle the entire 3173 * chain at once. 3174 * (paranoia -- may not actually be needed) 3175 */ 3176 if (m_head->m_flags & M_FIRSTFRAG && 3177 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3178 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3179 m_head->m_pkthdr.csum_data + 16) { 3180 ifp->if_flags |= IFF_OACTIVE; 3181 break; 3182 } 3183 } 3184 #endif 3185 3186 /* 3187 * Pack the data into the transmit ring. If we 3188 * don't have room, set the OACTIVE flag and wait 3189 * for the NIC to drain the ring. 3190 */ 3191 if (bge_encap(sc, m_head, &prodidx)) { 3192 ifp->if_flags |= IFF_OACTIVE; 3193 break; 3194 } 3195 3196 /* now we are committed to transmit the packet */ 3197 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3198 pkts++; 3199 3200 #if NBPFILTER > 0 3201 /* 3202 * If there's a BPF listener, bounce a copy of this frame 3203 * to him. 3204 */ 3205 if (ifp->if_bpf) 3206 bpf_mtap(ifp->if_bpf, m_head); 3207 #endif 3208 } 3209 if (pkts == 0) 3210 return; 3211 3212 /* Transmit */ 3213 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3214 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3215 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3216 3217 /* 3218 * Set a timeout in case the chip goes out to lunch. 3219 */ 3220 ifp->if_timer = 5; 3221 } 3222 3223 int 3224 bge_init(ifp) 3225 struct ifnet *ifp; 3226 { 3227 struct bge_softc *sc = ifp->if_softc; 3228 u_int16_t *m; 3229 int s, error; 3230 3231 s = splnet(); 3232 3233 ifp = &sc->ethercom.ec_if; 3234 3235 /* Cancel pending I/O and flush buffers. */ 3236 bge_stop(sc); 3237 bge_reset(sc); 3238 bge_chipinit(sc); 3239 3240 /* 3241 * Init the various state machines, ring 3242 * control blocks and firmware. 3243 */ 3244 error = bge_blockinit(sc); 3245 if (error != 0) { 3246 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3247 error); 3248 splx(s); 3249 return error; 3250 } 3251 3252 ifp = &sc->ethercom.ec_if; 3253 3254 /* Specify MTU. */ 3255 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3256 ETHER_HDR_LEN + ETHER_CRC_LEN); 3257 3258 /* Load our MAC address. */ 3259 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3260 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3261 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3262 3263 /* Enable or disable promiscuous mode as needed. */ 3264 if (ifp->if_flags & IFF_PROMISC) { 3265 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3266 } else { 3267 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3268 } 3269 3270 /* Program multicast filter. */ 3271 bge_setmulti(sc); 3272 3273 /* Init RX ring. */ 3274 bge_init_rx_ring_std(sc); 3275 3276 /* Init jumbo RX ring. */ 3277 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3278 bge_init_rx_ring_jumbo(sc); 3279 3280 /* Init our RX return ring index */ 3281 sc->bge_rx_saved_considx = 0; 3282 3283 /* Init TX ring. */ 3284 bge_init_tx_ring(sc); 3285 3286 /* Turn on transmitter */ 3287 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3288 3289 /* Turn on receiver */ 3290 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3291 3292 /* Tell firmware we're alive. */ 3293 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3294 3295 /* Enable host interrupts. */ 3296 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3297 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3298 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3299 3300 bge_ifmedia_upd(ifp); 3301 3302 ifp->if_flags |= IFF_RUNNING; 3303 ifp->if_flags &= ~IFF_OACTIVE; 3304 3305 splx(s); 3306 3307 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3308 3309 return 0; 3310 } 3311 3312 /* 3313 * Set media options. 3314 */ 3315 int 3316 bge_ifmedia_upd(ifp) 3317 struct ifnet *ifp; 3318 { 3319 struct bge_softc *sc = ifp->if_softc; 3320 struct mii_data *mii = &sc->bge_mii; 3321 struct ifmedia *ifm = &sc->bge_ifmedia; 3322 3323 /* If this is a 1000baseX NIC, enable the TBI port. */ 3324 if (sc->bge_tbi) { 3325 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3326 return(EINVAL); 3327 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3328 case IFM_AUTO: 3329 break; 3330 case IFM_1000_SX: 3331 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3332 BGE_CLRBIT(sc, BGE_MAC_MODE, 3333 BGE_MACMODE_HALF_DUPLEX); 3334 } else { 3335 BGE_SETBIT(sc, BGE_MAC_MODE, 3336 BGE_MACMODE_HALF_DUPLEX); 3337 } 3338 break; 3339 default: 3340 return(EINVAL); 3341 } 3342 return(0); 3343 } 3344 3345 sc->bge_link = 0; 3346 mii_mediachg(mii); 3347 3348 return(0); 3349 } 3350 3351 /* 3352 * Report current media status. 3353 */ 3354 void 3355 bge_ifmedia_sts(ifp, ifmr) 3356 struct ifnet *ifp; 3357 struct ifmediareq *ifmr; 3358 { 3359 struct bge_softc *sc = ifp->if_softc; 3360 struct mii_data *mii = &sc->bge_mii; 3361 3362 if (sc->bge_tbi) { 3363 ifmr->ifm_status = IFM_AVALID; 3364 ifmr->ifm_active = IFM_ETHER; 3365 if (CSR_READ_4(sc, BGE_MAC_STS) & 3366 BGE_MACSTAT_TBI_PCS_SYNCHED) 3367 ifmr->ifm_status |= IFM_ACTIVE; 3368 ifmr->ifm_active |= IFM_1000_SX; 3369 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3370 ifmr->ifm_active |= IFM_HDX; 3371 else 3372 ifmr->ifm_active |= IFM_FDX; 3373 return; 3374 } 3375 3376 mii_pollstat(mii); 3377 ifmr->ifm_active = mii->mii_media_active; 3378 ifmr->ifm_status = mii->mii_media_status; 3379 } 3380 3381 int 3382 bge_ioctl(ifp, command, data) 3383 struct ifnet *ifp; 3384 u_long command; 3385 caddr_t data; 3386 { 3387 struct bge_softc *sc = ifp->if_softc; 3388 struct ifreq *ifr = (struct ifreq *) data; 3389 int s, error = 0; 3390 struct mii_data *mii; 3391 3392 s = splnet(); 3393 3394 switch(command) { 3395 case SIOCSIFFLAGS: 3396 if (ifp->if_flags & IFF_UP) { 3397 /* 3398 * If only the state of the PROMISC flag changed, 3399 * then just use the 'set promisc mode' command 3400 * instead of reinitializing the entire NIC. Doing 3401 * a full re-init means reloading the firmware and 3402 * waiting for it to start up, which may take a 3403 * second or two. 3404 */ 3405 if (ifp->if_flags & IFF_RUNNING && 3406 ifp->if_flags & IFF_PROMISC && 3407 !(sc->bge_if_flags & IFF_PROMISC)) { 3408 BGE_SETBIT(sc, BGE_RX_MODE, 3409 BGE_RXMODE_RX_PROMISC); 3410 } else if (ifp->if_flags & IFF_RUNNING && 3411 !(ifp->if_flags & IFF_PROMISC) && 3412 sc->bge_if_flags & IFF_PROMISC) { 3413 BGE_CLRBIT(sc, BGE_RX_MODE, 3414 BGE_RXMODE_RX_PROMISC); 3415 } else 3416 bge_init(ifp); 3417 } else { 3418 if (ifp->if_flags & IFF_RUNNING) { 3419 bge_stop(sc); 3420 } 3421 } 3422 sc->bge_if_flags = ifp->if_flags; 3423 error = 0; 3424 break; 3425 case SIOCSIFMEDIA: 3426 case SIOCGIFMEDIA: 3427 if (sc->bge_tbi) { 3428 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3429 command); 3430 } else { 3431 mii = &sc->bge_mii; 3432 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3433 command); 3434 } 3435 error = 0; 3436 break; 3437 default: 3438 error = ether_ioctl(ifp, command, data); 3439 if (error == ENETRESET) { 3440 bge_setmulti(sc); 3441 error = 0; 3442 } 3443 break; 3444 } 3445 3446 splx(s); 3447 3448 return(error); 3449 } 3450 3451 void 3452 bge_watchdog(ifp) 3453 struct ifnet *ifp; 3454 { 3455 struct bge_softc *sc; 3456 3457 sc = ifp->if_softc; 3458 3459 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3460 3461 ifp->if_flags &= ~IFF_RUNNING; 3462 bge_init(ifp); 3463 3464 ifp->if_oerrors++; 3465 } 3466 3467 static void 3468 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3469 { 3470 int i; 3471 3472 BGE_CLRBIT(sc, reg, bit); 3473 3474 for (i = 0; i < BGE_TIMEOUT; i++) { 3475 if ((CSR_READ_4(sc, reg) & bit) == 0) 3476 return; 3477 delay(100); 3478 } 3479 3480 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3481 sc->bge_dev.dv_xname, (u_long) reg, bit); 3482 } 3483 3484 /* 3485 * Stop the adapter and free any mbufs allocated to the 3486 * RX and TX lists. 3487 */ 3488 void 3489 bge_stop(sc) 3490 struct bge_softc *sc; 3491 { 3492 struct ifnet *ifp = &sc->ethercom.ec_if; 3493 3494 callout_stop(&sc->bge_timeout); 3495 3496 /* 3497 * Disable all of the receiver blocks 3498 */ 3499 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3500 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3501 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3502 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3503 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3504 } 3505 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3506 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3507 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3508 3509 /* 3510 * Disable all of the transmit blocks 3511 */ 3512 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3513 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3514 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3515 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3516 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3517 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3518 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3519 } 3520 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3521 3522 /* 3523 * Shut down all of the memory managers and related 3524 * state machines. 3525 */ 3526 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3527 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3528 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3529 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3530 } 3531 3532 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3533 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3534 3535 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3536 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3537 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3538 } 3539 3540 /* Disable host interrupts. */ 3541 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3542 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3543 3544 /* 3545 * Tell firmware we're shutting down. 3546 */ 3547 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3548 3549 /* Free the RX lists. */ 3550 bge_free_rx_ring_std(sc); 3551 3552 /* Free jumbo RX list. */ 3553 bge_free_rx_ring_jumbo(sc); 3554 3555 /* Free TX buffers. */ 3556 bge_free_tx_ring(sc); 3557 3558 /* 3559 * Isolate/power down the PHY. 3560 */ 3561 if (!sc->bge_tbi) 3562 mii_down(&sc->bge_mii); 3563 3564 sc->bge_link = 0; 3565 3566 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3567 3568 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3569 } 3570 3571 /* 3572 * Stop all chip I/O so that the kernel's probe routines don't 3573 * get confused by errant DMAs when rebooting. 3574 */ 3575 void 3576 bge_shutdown(xsc) 3577 void *xsc; 3578 { 3579 struct bge_softc *sc = (struct bge_softc *)xsc; 3580 3581 bge_stop(sc); 3582 bge_reset(sc); 3583 } 3584
Indexes created Wed Sep 24 05:09:52 GMT 2025