if_bge.c revision 1.56
1 /* $NetBSD: if_bge.c,v 1.56 2003/12/09 15:19:33 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.56 2003/12/09 15:19:33 pooka Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/miidevs.h> 120 #include <dev/mii/brgphyreg.h> 121 122 #include <dev/pci/if_bgereg.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 127 128 int bge_probe(struct device *, struct cfdata *, void *); 129 void bge_attach(struct device *, struct device *, void *); 130 void bge_release_resources(struct bge_softc *); 131 void bge_txeof(struct bge_softc *); 132 void bge_rxeof(struct bge_softc *); 133 134 void bge_tick(void *); 135 void bge_stats_update(struct bge_softc *); 136 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 137 static __inline int bge_cksum_pad(struct mbuf *pkt); 138 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 139 140 int bge_intr(void *); 141 void bge_start(struct ifnet *); 142 int bge_ioctl(struct ifnet *, u_long, caddr_t); 143 int bge_init(struct ifnet *); 144 void bge_stop(struct bge_softc *); 145 void bge_watchdog(struct ifnet *); 146 void bge_shutdown(void *); 147 int bge_ifmedia_upd(struct ifnet *); 148 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 149 150 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 151 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 152 153 void bge_setmulti(struct bge_softc *); 154 155 void bge_handle_events(struct bge_softc *); 156 int bge_alloc_jumbo_mem(struct bge_softc *); 157 void bge_free_jumbo_mem(struct bge_softc *); 158 void *bge_jalloc(struct bge_softc *); 159 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 160 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 161 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 162 int bge_init_rx_ring_std(struct bge_softc *); 163 void bge_free_rx_ring_std(struct bge_softc *); 164 int bge_init_rx_ring_jumbo(struct bge_softc *); 165 void bge_free_rx_ring_jumbo(struct bge_softc *); 166 void bge_free_tx_ring(struct bge_softc *); 167 int bge_init_tx_ring(struct bge_softc *); 168 169 int bge_chipinit(struct bge_softc *); 170 int bge_blockinit(struct bge_softc *); 171 int bge_setpowerstate(struct bge_softc *, int); 172 173 #ifdef notdef 174 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 175 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 176 void bge_vpd_read(struct bge_softc *); 177 #endif 178 179 u_int32_t bge_readmem_ind(struct bge_softc *, int); 180 void bge_writemem_ind(struct bge_softc *, int, int); 181 #ifdef notdef 182 u_int32_t bge_readreg_ind(struct bge_softc *, int); 183 #endif 184 void bge_writereg_ind(struct bge_softc *, int, int); 185 186 int bge_miibus_readreg(struct device *, int, int); 187 void bge_miibus_writereg(struct device *, int, int, int); 188 void bge_miibus_statchg(struct device *); 189 190 void bge_reset(struct bge_softc *); 191 192 void bge_dump_status(struct bge_softc *); 193 void bge_dump_rxbd(struct bge_rx_bd *); 194 195 #define BGE_DEBUG 196 #ifdef BGE_DEBUG 197 #define DPRINTF(x) if (bgedebug) printf x 198 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 199 int bgedebug = 0; 200 #else 201 #define DPRINTF(x) 202 #define DPRINTFN(n,x) 203 #endif 204 205 /* Various chip quirks. */ 206 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 207 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 208 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 209 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 210 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 211 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 212 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 213 #define BGE_QUIRK_5705_CORE 0x00000080 214 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 215 216 /* following bugs are common to bcm5700 rev B, all flavours */ 217 #define BGE_QUIRK_5700_COMMON \ 218 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 219 220 CFATTACH_DECL(bge, sizeof(struct bge_softc), 221 bge_probe, bge_attach, NULL, NULL); 222 223 u_int32_t 224 bge_readmem_ind(sc, off) 225 struct bge_softc *sc; 226 int off; 227 { 228 struct pci_attach_args *pa = &(sc->bge_pa); 229 pcireg_t val; 230 231 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 232 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 233 return val; 234 } 235 236 void 237 bge_writemem_ind(sc, off, val) 238 struct bge_softc *sc; 239 int off, val; 240 { 241 struct pci_attach_args *pa = &(sc->bge_pa); 242 243 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 244 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 245 } 246 247 #ifdef notdef 248 u_int32_t 249 bge_readreg_ind(sc, off) 250 struct bge_softc *sc; 251 int off; 252 { 253 struct pci_attach_args *pa = &(sc->bge_pa); 254 255 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 256 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 257 } 258 #endif 259 260 void 261 bge_writereg_ind(sc, off, val) 262 struct bge_softc *sc; 263 int off, val; 264 { 265 struct pci_attach_args *pa = &(sc->bge_pa); 266 267 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 268 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 269 } 270 271 #ifdef notdef 272 u_int8_t 273 bge_vpd_readbyte(sc, addr) 274 struct bge_softc *sc; 275 int addr; 276 { 277 int i; 278 u_int32_t val; 279 struct pci_attach_args *pa = &(sc->bge_pa); 280 281 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 282 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 283 DELAY(10); 284 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 285 BGE_VPD_FLAG) 286 break; 287 } 288 289 if (i == BGE_TIMEOUT) { 290 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 291 return(0); 292 } 293 294 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 295 296 return((val >> ((addr % 4) * 8)) & 0xFF); 297 } 298 299 void 300 bge_vpd_read_res(sc, res, addr) 301 struct bge_softc *sc; 302 struct vpd_res *res; 303 int addr; 304 { 305 int i; 306 u_int8_t *ptr; 307 308 ptr = (u_int8_t *)res; 309 for (i = 0; i < sizeof(struct vpd_res); i++) 310 ptr[i] = bge_vpd_readbyte(sc, i + addr); 311 } 312 313 void 314 bge_vpd_read(sc) 315 struct bge_softc *sc; 316 { 317 int pos = 0, i; 318 struct vpd_res res; 319 320 if (sc->bge_vpd_prodname != NULL) 321 free(sc->bge_vpd_prodname, M_DEVBUF); 322 if (sc->bge_vpd_readonly != NULL) 323 free(sc->bge_vpd_readonly, M_DEVBUF); 324 sc->bge_vpd_prodname = NULL; 325 sc->bge_vpd_readonly = NULL; 326 327 bge_vpd_read_res(sc, &res, pos); 328 329 if (res.vr_id != VPD_RES_ID) { 330 printf("%s: bad VPD resource id: expected %x got %x\n", 331 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 332 return; 333 } 334 335 pos += sizeof(res); 336 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 337 if (sc->bge_vpd_prodname == NULL) 338 panic("bge_vpd_read"); 339 for (i = 0; i < res.vr_len; i++) 340 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 341 sc->bge_vpd_prodname[i] = '\0'; 342 pos += i; 343 344 bge_vpd_read_res(sc, &res, pos); 345 346 if (res.vr_id != VPD_RES_READ) { 347 printf("%s: bad VPD resource id: expected %x got %x\n", 348 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 349 return; 350 } 351 352 pos += sizeof(res); 353 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 354 if (sc->bge_vpd_readonly == NULL) 355 panic("bge_vpd_read"); 356 for (i = 0; i < res.vr_len + 1; i++) 357 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 358 } 359 #endif 360 361 /* 362 * Read a byte of data stored in the EEPROM at address 'addr.' The 363 * BCM570x supports both the traditional bitbang interface and an 364 * auto access interface for reading the EEPROM. We use the auto 365 * access method. 366 */ 367 u_int8_t 368 bge_eeprom_getbyte(sc, addr, dest) 369 struct bge_softc *sc; 370 int addr; 371 u_int8_t *dest; 372 { 373 int i; 374 u_int32_t byte = 0; 375 376 /* 377 * Enable use of auto EEPROM access so we can avoid 378 * having to use the bitbang method. 379 */ 380 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 381 382 /* Reset the EEPROM, load the clock period. */ 383 CSR_WRITE_4(sc, BGE_EE_ADDR, 384 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 385 DELAY(20); 386 387 /* Issue the read EEPROM command. */ 388 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 389 390 /* Wait for completion */ 391 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 392 DELAY(10); 393 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 394 break; 395 } 396 397 if (i == BGE_TIMEOUT) { 398 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 399 return(0); 400 } 401 402 /* Get result. */ 403 byte = CSR_READ_4(sc, BGE_EE_DATA); 404 405 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 406 407 return(0); 408 } 409 410 /* 411 * Read a sequence of bytes from the EEPROM. 412 */ 413 int 414 bge_read_eeprom(sc, dest, off, cnt) 415 struct bge_softc *sc; 416 caddr_t dest; 417 int off; 418 int cnt; 419 { 420 int err = 0, i; 421 u_int8_t byte = 0; 422 423 for (i = 0; i < cnt; i++) { 424 err = bge_eeprom_getbyte(sc, off + i, &byte); 425 if (err) 426 break; 427 *(dest + i) = byte; 428 } 429 430 return(err ? 1 : 0); 431 } 432 433 int 434 bge_miibus_readreg(dev, phy, reg) 435 struct device *dev; 436 int phy, reg; 437 { 438 struct bge_softc *sc = (struct bge_softc *)dev; 439 u_int32_t val; 440 u_int32_t saved_autopoll; 441 int i; 442 443 /* 444 * Several chips with builtin PHYs will incorrectly answer to 445 * other PHY instances than the builtin PHY at id 1. 446 */ 447 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 448 return(0); 449 450 /* Reading with autopolling on may trigger PCI errors */ 451 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 452 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 453 CSR_WRITE_4(sc, BGE_MI_MODE, 454 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 455 DELAY(40); 456 } 457 458 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 459 BGE_MIPHY(phy)|BGE_MIREG(reg)); 460 461 for (i = 0; i < BGE_TIMEOUT; i++) { 462 val = CSR_READ_4(sc, BGE_MI_COMM); 463 if (!(val & BGE_MICOMM_BUSY)) 464 break; 465 delay(10); 466 } 467 468 if (i == BGE_TIMEOUT) { 469 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 470 val = 0; 471 goto done; 472 } 473 474 val = CSR_READ_4(sc, BGE_MI_COMM); 475 476 done: 477 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 478 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 479 DELAY(40); 480 } 481 482 if (val & BGE_MICOMM_READFAIL) 483 return(0); 484 485 return(val & 0xFFFF); 486 } 487 488 void 489 bge_miibus_writereg(dev, phy, reg, val) 490 struct device *dev; 491 int phy, reg, val; 492 { 493 struct bge_softc *sc = (struct bge_softc *)dev; 494 u_int32_t saved_autopoll; 495 int i; 496 497 /* Touching the PHY while autopolling is on may trigger PCI errors */ 498 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 499 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 500 delay(40); 501 CSR_WRITE_4(sc, BGE_MI_MODE, 502 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 503 delay(10); /* 40 usec is supposed to be adequate */ 504 } 505 506 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 507 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 508 509 for (i = 0; i < BGE_TIMEOUT; i++) { 510 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 511 break; 512 delay(10); 513 } 514 515 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 516 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 517 delay(40); 518 } 519 520 if (i == BGE_TIMEOUT) { 521 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 522 } 523 } 524 525 void 526 bge_miibus_statchg(dev) 527 struct device *dev; 528 { 529 struct bge_softc *sc = (struct bge_softc *)dev; 530 struct mii_data *mii = &sc->bge_mii; 531 532 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 533 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 534 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 535 } else { 536 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 537 } 538 539 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 540 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 541 } else { 542 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 543 } 544 } 545 546 /* 547 * Handle events that have triggered interrupts. 548 */ 549 void 550 bge_handle_events(sc) 551 struct bge_softc *sc; 552 { 553 554 return; 555 } 556 557 /* 558 * Memory management for jumbo frames. 559 */ 560 561 int 562 bge_alloc_jumbo_mem(sc) 563 struct bge_softc *sc; 564 { 565 caddr_t ptr, kva; 566 bus_dma_segment_t seg; 567 int i, rseg, state, error; 568 struct bge_jpool_entry *entry; 569 570 state = error = 0; 571 572 /* Grab a big chunk o' storage. */ 573 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 574 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 575 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 576 return ENOBUFS; 577 } 578 579 state = 1; 580 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 581 BUS_DMA_NOWAIT)) { 582 printf("%s: can't map DMA buffers (%d bytes)\n", 583 sc->bge_dev.dv_xname, (int)BGE_JMEM); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 2; 589 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 590 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 591 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 592 error = ENOBUFS; 593 goto out; 594 } 595 596 state = 3; 597 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 598 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 599 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 600 error = ENOBUFS; 601 goto out; 602 } 603 604 state = 4; 605 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 606 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 607 608 SLIST_INIT(&sc->bge_jfree_listhead); 609 SLIST_INIT(&sc->bge_jinuse_listhead); 610 611 /* 612 * Now divide it up into 9K pieces and save the addresses 613 * in an array. 614 */ 615 ptr = sc->bge_cdata.bge_jumbo_buf; 616 for (i = 0; i < BGE_JSLOTS; i++) { 617 sc->bge_cdata.bge_jslots[i] = ptr; 618 ptr += BGE_JLEN; 619 entry = malloc(sizeof(struct bge_jpool_entry), 620 M_DEVBUF, M_NOWAIT); 621 if (entry == NULL) { 622 printf("%s: no memory for jumbo buffer queue!\n", 623 sc->bge_dev.dv_xname); 624 error = ENOBUFS; 625 goto out; 626 } 627 entry->slot = i; 628 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 629 entry, jpool_entries); 630 } 631 out: 632 if (error != 0) { 633 switch (state) { 634 case 4: 635 bus_dmamap_unload(sc->bge_dmatag, 636 sc->bge_cdata.bge_rx_jumbo_map); 637 case 3: 638 bus_dmamap_destroy(sc->bge_dmatag, 639 sc->bge_cdata.bge_rx_jumbo_map); 640 case 2: 641 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 642 case 1: 643 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 644 break; 645 default: 646 break; 647 } 648 } 649 650 return error; 651 } 652 653 /* 654 * Allocate a jumbo buffer. 655 */ 656 void * 657 bge_jalloc(sc) 658 struct bge_softc *sc; 659 { 660 struct bge_jpool_entry *entry; 661 662 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 663 664 if (entry == NULL) { 665 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 666 return(NULL); 667 } 668 669 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 670 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 671 return(sc->bge_cdata.bge_jslots[entry->slot]); 672 } 673 674 /* 675 * Release a jumbo buffer. 676 */ 677 void 678 bge_jfree(m, buf, size, arg) 679 struct mbuf *m; 680 caddr_t buf; 681 size_t size; 682 void *arg; 683 { 684 struct bge_jpool_entry *entry; 685 struct bge_softc *sc; 686 int i, s; 687 688 /* Extract the softc struct pointer. */ 689 sc = (struct bge_softc *)arg; 690 691 if (sc == NULL) 692 panic("bge_jfree: can't find softc pointer!"); 693 694 /* calculate the slot this buffer belongs to */ 695 696 i = ((caddr_t)buf 697 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 698 699 if ((i < 0) || (i >= BGE_JSLOTS)) 700 panic("bge_jfree: asked to free buffer that we don't manage!"); 701 702 s = splvm(); 703 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 704 if (entry == NULL) 705 panic("bge_jfree: buffer not in use!"); 706 entry->slot = i; 707 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 708 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 709 710 if (__predict_true(m != NULL)) 711 pool_cache_put(&mbpool_cache, m); 712 splx(s); 713 } 714 715 716 /* 717 * Intialize a standard receive ring descriptor. 718 */ 719 int 720 bge_newbuf_std(sc, i, m, dmamap) 721 struct bge_softc *sc; 722 int i; 723 struct mbuf *m; 724 bus_dmamap_t dmamap; 725 { 726 struct mbuf *m_new = NULL; 727 struct bge_rx_bd *r; 728 int error; 729 730 if (dmamap == NULL) { 731 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 732 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 733 if (error != 0) 734 return error; 735 } 736 737 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 738 739 if (m == NULL) { 740 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 741 if (m_new == NULL) { 742 return(ENOBUFS); 743 } 744 745 MCLGET(m_new, M_DONTWAIT); 746 if (!(m_new->m_flags & M_EXT)) { 747 m_freem(m_new); 748 return(ENOBUFS); 749 } 750 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 751 if (!sc->bge_rx_alignment_bug) 752 m_adj(m_new, ETHER_ALIGN); 753 754 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 755 BUS_DMA_READ|BUS_DMA_NOWAIT)) 756 return(ENOBUFS); 757 } else { 758 m_new = m; 759 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 760 m_new->m_data = m_new->m_ext.ext_buf; 761 if (!sc->bge_rx_alignment_bug) 762 m_adj(m_new, ETHER_ALIGN); 763 } 764 765 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 766 r = &sc->bge_rdata->bge_rx_std_ring[i]; 767 bge_set_hostaddr(&r->bge_addr, 768 dmamap->dm_segs[0].ds_addr); 769 r->bge_flags = BGE_RXBDFLAG_END; 770 r->bge_len = m_new->m_len; 771 r->bge_idx = i; 772 773 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 774 offsetof(struct bge_ring_data, bge_rx_std_ring) + 775 i * sizeof (struct bge_rx_bd), 776 sizeof (struct bge_rx_bd), 777 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 778 779 return(0); 780 } 781 782 /* 783 * Initialize a jumbo receive ring descriptor. This allocates 784 * a jumbo buffer from the pool managed internally by the driver. 785 */ 786 int 787 bge_newbuf_jumbo(sc, i, m) 788 struct bge_softc *sc; 789 int i; 790 struct mbuf *m; 791 { 792 struct mbuf *m_new = NULL; 793 struct bge_rx_bd *r; 794 795 if (m == NULL) { 796 caddr_t *buf = NULL; 797 798 /* Allocate the mbuf. */ 799 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 800 if (m_new == NULL) { 801 return(ENOBUFS); 802 } 803 804 /* Allocate the jumbo buffer */ 805 buf = bge_jalloc(sc); 806 if (buf == NULL) { 807 m_freem(m_new); 808 printf("%s: jumbo allocation failed " 809 "-- packet dropped!\n", sc->bge_dev.dv_xname); 810 return(ENOBUFS); 811 } 812 813 /* Attach the buffer to the mbuf. */ 814 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 815 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 816 bge_jfree, sc); 817 } else { 818 m_new = m; 819 m_new->m_data = m_new->m_ext.ext_buf; 820 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 821 } 822 823 if (!sc->bge_rx_alignment_bug) 824 m_adj(m_new, ETHER_ALIGN); 825 /* Set up the descriptor. */ 826 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 827 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 828 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 829 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 830 r->bge_len = m_new->m_len; 831 r->bge_idx = i; 832 833 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 834 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 835 i * sizeof (struct bge_rx_bd), 836 sizeof (struct bge_rx_bd), 837 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 838 839 return(0); 840 } 841 842 /* 843 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 844 * that's 1MB or memory, which is a lot. For now, we fill only the first 845 * 256 ring entries and hope that our CPU is fast enough to keep up with 846 * the NIC. 847 */ 848 int 849 bge_init_rx_ring_std(sc) 850 struct bge_softc *sc; 851 { 852 int i; 853 854 if (sc->bge_flags & BGE_RXRING_VALID) 855 return 0; 856 857 for (i = 0; i < BGE_SSLOTS; i++) { 858 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 859 return(ENOBUFS); 860 } 861 862 sc->bge_std = i - 1; 863 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 864 865 sc->bge_flags |= BGE_RXRING_VALID; 866 867 return(0); 868 } 869 870 void 871 bge_free_rx_ring_std(sc) 872 struct bge_softc *sc; 873 { 874 int i; 875 876 if (!(sc->bge_flags & BGE_RXRING_VALID)) 877 return; 878 879 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 880 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 881 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 882 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 883 bus_dmamap_destroy(sc->bge_dmatag, 884 sc->bge_cdata.bge_rx_std_map[i]); 885 } 886 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 887 sizeof(struct bge_rx_bd)); 888 } 889 890 sc->bge_flags &= ~BGE_RXRING_VALID; 891 } 892 893 int 894 bge_init_rx_ring_jumbo(sc) 895 struct bge_softc *sc; 896 { 897 int i; 898 volatile struct bge_rcb *rcb; 899 900 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 901 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 902 return(ENOBUFS); 903 }; 904 905 sc->bge_jumbo = i - 1; 906 907 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 908 rcb->bge_maxlen_flags = 0; 909 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 910 911 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 912 913 return(0); 914 } 915 916 void 917 bge_free_rx_ring_jumbo(sc) 918 struct bge_softc *sc; 919 { 920 int i; 921 922 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 923 return; 924 925 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 926 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 927 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 928 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 929 } 930 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 931 sizeof(struct bge_rx_bd)); 932 } 933 934 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 935 } 936 937 void 938 bge_free_tx_ring(sc) 939 struct bge_softc *sc; 940 { 941 int i, freed; 942 struct txdmamap_pool_entry *dma; 943 944 if (!(sc->bge_flags & BGE_TXRING_VALID)) 945 return; 946 947 freed = 0; 948 949 for (i = 0; i < BGE_TX_RING_CNT; i++) { 950 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 951 freed++; 952 m_freem(sc->bge_cdata.bge_tx_chain[i]); 953 sc->bge_cdata.bge_tx_chain[i] = NULL; 954 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 955 link); 956 sc->txdma[i] = 0; 957 } 958 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 959 sizeof(struct bge_tx_bd)); 960 } 961 962 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 963 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 964 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 965 free(dma, M_DEVBUF); 966 } 967 968 sc->bge_flags &= ~BGE_TXRING_VALID; 969 } 970 971 int 972 bge_init_tx_ring(sc) 973 struct bge_softc *sc; 974 { 975 int i; 976 bus_dmamap_t dmamap; 977 struct txdmamap_pool_entry *dma; 978 979 if (sc->bge_flags & BGE_TXRING_VALID) 980 return 0; 981 982 sc->bge_txcnt = 0; 983 sc->bge_tx_saved_considx = 0; 984 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 985 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 986 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 987 988 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 989 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 990 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 991 992 SLIST_INIT(&sc->txdma_list); 993 for (i = 0; i < BGE_RSLOTS; i++) { 994 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 995 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 996 &dmamap)) 997 return(ENOBUFS); 998 if (dmamap == NULL) 999 panic("dmamap NULL in bge_init_tx_ring"); 1000 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1001 if (dma == NULL) { 1002 printf("%s: can't alloc txdmamap_pool_entry\n", 1003 sc->bge_dev.dv_xname); 1004 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1005 return (ENOMEM); 1006 } 1007 dma->dmamap = dmamap; 1008 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1009 } 1010 1011 sc->bge_flags |= BGE_TXRING_VALID; 1012 1013 return(0); 1014 } 1015 1016 void 1017 bge_setmulti(sc) 1018 struct bge_softc *sc; 1019 { 1020 struct ethercom *ac = &sc->ethercom; 1021 struct ifnet *ifp = &ac->ec_if; 1022 struct ether_multi *enm; 1023 struct ether_multistep step; 1024 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1025 u_int32_t h; 1026 int i; 1027 1028 if (ifp->if_flags & IFF_PROMISC) 1029 goto allmulti; 1030 1031 /* Now program new ones. */ 1032 ETHER_FIRST_MULTI(step, ac, enm); 1033 while (enm != NULL) { 1034 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1035 /* 1036 * We must listen to a range of multicast addresses. 1037 * For now, just accept all multicasts, rather than 1038 * trying to set only those filter bits needed to match 1039 * the range. (At this time, the only use of address 1040 * ranges is for IP multicast routing, for which the 1041 * range is big enough to require all bits set.) 1042 */ 1043 goto allmulti; 1044 } 1045 1046 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1047 1048 /* Just want the 7 least-significant bits. */ 1049 h &= 0x7f; 1050 1051 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1052 ETHER_NEXT_MULTI(step, enm); 1053 } 1054 1055 ifp->if_flags &= ~IFF_ALLMULTI; 1056 goto setit; 1057 1058 allmulti: 1059 ifp->if_flags |= IFF_ALLMULTI; 1060 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1061 1062 setit: 1063 for (i = 0; i < 4; i++) 1064 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1065 } 1066 1067 const int bge_swapbits[] = { 1068 0, 1069 BGE_MODECTL_BYTESWAP_DATA, 1070 BGE_MODECTL_WORDSWAP_DATA, 1071 BGE_MODECTL_BYTESWAP_NONFRAME, 1072 BGE_MODECTL_WORDSWAP_NONFRAME, 1073 1074 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1075 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1076 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1077 1078 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1079 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1080 1081 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1082 1083 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1084 BGE_MODECTL_BYTESWAP_NONFRAME, 1085 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1086 BGE_MODECTL_WORDSWAP_NONFRAME, 1087 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1088 BGE_MODECTL_WORDSWAP_NONFRAME, 1089 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1090 BGE_MODECTL_WORDSWAP_NONFRAME, 1091 1092 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1093 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1094 }; 1095 1096 int bge_swapindex = 0; 1097 1098 /* 1099 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1100 * self-test results. 1101 */ 1102 int 1103 bge_chipinit(sc) 1104 struct bge_softc *sc; 1105 { 1106 u_int32_t cachesize; 1107 int i; 1108 u_int32_t dma_rw_ctl; 1109 struct pci_attach_args *pa = &(sc->bge_pa); 1110 1111 1112 /* Set endianness before we access any non-PCI registers. */ 1113 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1114 BGE_INIT); 1115 1116 /* Set power state to D0. */ 1117 bge_setpowerstate(sc, 0); 1118 1119 /* 1120 * Check the 'ROM failed' bit on the RX CPU to see if 1121 * self-tests passed. 1122 */ 1123 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1124 printf("%s: RX CPU self-diagnostics failed!\n", 1125 sc->bge_dev.dv_xname); 1126 return(ENODEV); 1127 } 1128 1129 /* Clear the MAC control register */ 1130 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1131 1132 /* 1133 * Clear the MAC statistics block in the NIC's 1134 * internal memory. 1135 */ 1136 for (i = BGE_STATS_BLOCK; 1137 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1138 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1139 1140 for (i = BGE_STATUS_BLOCK; 1141 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1142 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1143 1144 /* Set up the PCI DMA control register. */ 1145 if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1146 BGE_PCISTATE_PCI_BUSMODE) { 1147 /* Conventional PCI bus */ 1148 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1149 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1150 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1151 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1152 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1153 dma_rw_ctl |= 0x0F; 1154 } 1155 } else { 1156 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1157 /* PCI-X bus */ 1158 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1159 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1160 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1161 (0x0F); 1162 /* 1163 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1164 * for hardware bugs, which means we should also clear 1165 * the low-order MINDMA bits. In addition, the 5704 1166 * uses a different encoding of read/write watermarks. 1167 */ 1168 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 || 1169 sc->bge_chipid == BGE_CHIPID_BCM5704_A1 || 1170 sc->bge_chipid == BGE_CHIPID_BCM5704_A2 || 1171 sc->bge_chipid == BGE_CHIPID_BCM5704_A3) { 1172 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1173 /* should be 0x1f0000 */ 1174 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1175 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1176 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1177 } 1178 else if ((sc->bge_chipid >> 28) == 1179 (BGE_CHIPID_BCM5703_A0 >> 28)) { 1180 dma_rw_ctl &= 0xfffffff0; 1181 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1182 } 1183 } 1184 1185 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1186 1187 /* 1188 * Set up general mode register. 1189 */ 1190 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1191 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1192 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1193 1194 /* Get cache line size. */ 1195 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1196 1197 /* 1198 * Avoid violating PCI spec on certain chip revs. 1199 */ 1200 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1201 PCIM_CMD_MWIEN) { 1202 switch(cachesize) { 1203 case 1: 1204 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1205 BGE_PCI_WRITE_BNDRY_16BYTES); 1206 break; 1207 case 2: 1208 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1209 BGE_PCI_WRITE_BNDRY_32BYTES); 1210 break; 1211 case 4: 1212 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1213 BGE_PCI_WRITE_BNDRY_64BYTES); 1214 break; 1215 case 8: 1216 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1217 BGE_PCI_WRITE_BNDRY_128BYTES); 1218 break; 1219 case 16: 1220 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1221 BGE_PCI_WRITE_BNDRY_256BYTES); 1222 break; 1223 case 32: 1224 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1225 BGE_PCI_WRITE_BNDRY_512BYTES); 1226 break; 1227 case 64: 1228 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1229 BGE_PCI_WRITE_BNDRY_1024BYTES); 1230 break; 1231 default: 1232 /* Disable PCI memory write and invalidate. */ 1233 #if 0 1234 if (bootverbose) 1235 printf("%s: cache line size %d not " 1236 "supported; disabling PCI MWI\n", 1237 sc->bge_dev.dv_xname, cachesize); 1238 #endif 1239 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1240 PCIM_CMD_MWIEN); 1241 break; 1242 } 1243 } 1244 1245 /* 1246 * Disable memory write invalidate. Apparently it is not supported 1247 * properly by these devices. 1248 */ 1249 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1250 1251 1252 #ifdef __brokenalpha__ 1253 /* 1254 * Must insure that we do not cross an 8K (bytes) boundary 1255 * for DMA reads. Our highest limit is 1K bytes. This is a 1256 * restriction on some ALPHA platforms with early revision 1257 * 21174 PCI chipsets, such as the AlphaPC 164lx 1258 */ 1259 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1260 #endif 1261 1262 /* Set the timer prescaler (always 66MHz) */ 1263 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1264 1265 return(0); 1266 } 1267 1268 int 1269 bge_blockinit(sc) 1270 struct bge_softc *sc; 1271 { 1272 volatile struct bge_rcb *rcb; 1273 bus_size_t rcb_addr; 1274 int i; 1275 struct ifnet *ifp = &sc->ethercom.ec_if; 1276 bge_hostaddr taddr; 1277 1278 /* 1279 * Initialize the memory window pointer register so that 1280 * we can access the first 32K of internal NIC RAM. This will 1281 * allow us to set up the TX send ring RCBs and the RX return 1282 * ring RCBs, plus other things which live in NIC memory. 1283 */ 1284 1285 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1286 BGE_PCI_MEMWIN_BASEADDR, 0); 1287 1288 /* Configure mbuf memory pool */ 1289 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1290 if (sc->bge_extram) { 1291 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1292 BGE_EXT_SSRAM); 1293 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1294 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1295 else 1296 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1297 } else { 1298 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1299 BGE_BUFFPOOL_1); 1300 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1301 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1302 else 1303 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1304 } 1305 1306 /* Configure DMA resource pool */ 1307 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1308 BGE_DMA_DESCRIPTORS); 1309 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1310 } 1311 1312 /* Configure mbuf pool watermarks */ 1313 #ifdef ORIG_WPAUL_VALUES 1314 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1315 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1316 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1317 #else 1318 /* new broadcom docs strongly recommend these: */ 1319 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1321 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1322 } else { 1323 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1324 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1325 } 1326 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1327 #endif 1328 1329 /* Configure DMA resource watermarks */ 1330 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1331 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1332 1333 /* Enable buffer manager */ 1334 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1335 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1336 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1337 1338 /* Poll for buffer manager start indication */ 1339 for (i = 0; i < BGE_TIMEOUT; i++) { 1340 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1341 break; 1342 DELAY(10); 1343 } 1344 1345 if (i == BGE_TIMEOUT) { 1346 printf("%s: buffer manager failed to start\n", 1347 sc->bge_dev.dv_xname); 1348 return(ENXIO); 1349 } 1350 } 1351 1352 /* Enable flow-through queues */ 1353 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1354 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1355 1356 /* Wait until queue initialization is complete */ 1357 for (i = 0; i < BGE_TIMEOUT; i++) { 1358 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1359 break; 1360 DELAY(10); 1361 } 1362 1363 if (i == BGE_TIMEOUT) { 1364 printf("%s: flow-through queue init failed\n", 1365 sc->bge_dev.dv_xname); 1366 return(ENXIO); 1367 } 1368 1369 /* Initialize the standard RX ring control block */ 1370 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1371 bge_set_hostaddr(&rcb->bge_hostaddr, 1372 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1373 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1374 rcb->bge_maxlen_flags = 1375 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1376 } else { 1377 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1378 } 1379 if (sc->bge_extram) 1380 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1381 else 1382 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1383 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1384 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1385 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1386 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1387 1388 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1389 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1390 } else { 1391 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1392 } 1393 1394 /* 1395 * Initialize the jumbo RX ring control block 1396 * We set the 'ring disabled' bit in the flags 1397 * field until we're actually ready to start 1398 * using this ring (i.e. once we set the MTU 1399 * high enough to require it). 1400 */ 1401 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1402 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1403 bge_set_hostaddr(&rcb->bge_hostaddr, 1404 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1405 rcb->bge_maxlen_flags = 1406 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1407 BGE_RCB_FLAG_RING_DISABLED); 1408 if (sc->bge_extram) 1409 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1410 else 1411 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1412 1413 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1414 rcb->bge_hostaddr.bge_addr_hi); 1415 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1416 rcb->bge_hostaddr.bge_addr_lo); 1417 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1418 rcb->bge_maxlen_flags); 1419 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1420 1421 /* Set up dummy disabled mini ring RCB */ 1422 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1423 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1424 BGE_RCB_FLAG_RING_DISABLED); 1425 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1426 rcb->bge_maxlen_flags); 1427 1428 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1429 offsetof(struct bge_ring_data, bge_info), 1430 sizeof (struct bge_gib), 1431 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1432 } 1433 1434 /* 1435 * Set the BD ring replentish thresholds. The recommended 1436 * values are 1/8th the number of descriptors allocated to 1437 * each ring. 1438 */ 1439 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1440 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1441 1442 /* 1443 * Disable all unused send rings by setting the 'ring disabled' 1444 * bit in the flags field of all the TX send ring control blocks. 1445 * These are located in NIC memory. 1446 */ 1447 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1448 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1449 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1450 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1451 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1452 rcb_addr += sizeof(struct bge_rcb); 1453 } 1454 1455 /* Configure TX RCB 0 (we use only the first ring) */ 1456 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1457 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1458 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1459 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1460 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1461 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1462 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1463 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1464 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1465 } 1466 1467 /* Disable all unused RX return rings */ 1468 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1469 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1470 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1471 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1472 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1473 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1474 BGE_RCB_FLAG_RING_DISABLED)); 1475 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1476 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1477 (i * (sizeof(u_int64_t))), 0); 1478 rcb_addr += sizeof(struct bge_rcb); 1479 } 1480 1481 /* Initialize RX ring indexes */ 1482 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1483 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1484 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1485 1486 /* 1487 * Set up RX return ring 0 1488 * Note that the NIC address for RX return rings is 0x00000000. 1489 * The return rings live entirely within the host, so the 1490 * nicaddr field in the RCB isn't used. 1491 */ 1492 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1493 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1494 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1495 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1496 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1497 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1498 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1499 1500 /* Set random backoff seed for TX */ 1501 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1502 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1503 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1504 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1505 BGE_TX_BACKOFF_SEED_MASK); 1506 1507 /* Set inter-packet gap */ 1508 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1509 1510 /* 1511 * Specify which ring to use for packets that don't match 1512 * any RX rules. 1513 */ 1514 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1515 1516 /* 1517 * Configure number of RX lists. One interrupt distribution 1518 * list, sixteen active lists, one bad frames class. 1519 */ 1520 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1521 1522 /* Inialize RX list placement stats mask. */ 1523 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1524 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1525 1526 /* Disable host coalescing until we get it set up */ 1527 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1528 1529 /* Poll to make sure it's shut down. */ 1530 for (i = 0; i < BGE_TIMEOUT; i++) { 1531 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1532 break; 1533 DELAY(10); 1534 } 1535 1536 if (i == BGE_TIMEOUT) { 1537 printf("%s: host coalescing engine failed to idle\n", 1538 sc->bge_dev.dv_xname); 1539 return(ENXIO); 1540 } 1541 1542 /* Set up host coalescing defaults */ 1543 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1544 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1545 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1546 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1547 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1548 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1549 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1550 } 1551 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1552 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1553 1554 /* Set up address of statistics block */ 1555 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1556 bge_set_hostaddr(&taddr, 1557 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1558 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1559 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1560 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1561 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1562 } 1563 1564 /* Set up address of status block */ 1565 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1566 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1567 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1568 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1569 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1570 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1571 1572 /* Turn on host coalescing state machine */ 1573 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1574 1575 /* Turn on RX BD completion state machine and enable attentions */ 1576 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1577 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1578 1579 /* Turn on RX list placement state machine */ 1580 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1581 1582 /* Turn on RX list selector state machine. */ 1583 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1584 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1585 } 1586 1587 /* Turn on DMA, clear stats */ 1588 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1589 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1590 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1591 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1592 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1593 1594 /* Set misc. local control, enable interrupts on attentions */ 1595 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1596 1597 #ifdef notdef 1598 /* Assert GPIO pins for PHY reset */ 1599 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1600 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1601 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1602 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1603 #endif 1604 1605 #if defined(not_quite_yet) 1606 /* Linux driver enables enable gpio pin #1 on 5700s */ 1607 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1608 sc->bge_local_ctrl_reg |= 1609 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1610 } 1611 #endif 1612 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1613 1614 /* Turn on DMA completion state machine */ 1615 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1616 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1617 } 1618 1619 /* Turn on write DMA state machine */ 1620 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1621 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1622 1623 /* Turn on read DMA state machine */ 1624 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1625 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1626 1627 /* Turn on RX data completion state machine */ 1628 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1629 1630 /* Turn on RX BD initiator state machine */ 1631 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1632 1633 /* Turn on RX data and RX BD initiator state machine */ 1634 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1635 1636 /* Turn on Mbuf cluster free state machine */ 1637 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1638 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1639 } 1640 1641 /* Turn on send BD completion state machine */ 1642 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1643 1644 /* Turn on send data completion state machine */ 1645 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1646 1647 /* Turn on send data initiator state machine */ 1648 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1649 1650 /* Turn on send BD initiator state machine */ 1651 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1652 1653 /* Turn on send BD selector state machine */ 1654 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1655 1656 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1657 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1658 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1659 1660 /* ack/clear link change events */ 1661 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1662 BGE_MACSTAT_CFG_CHANGED); 1663 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1664 1665 /* Enable PHY auto polling (for MII/GMII only) */ 1666 if (sc->bge_tbi) { 1667 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1668 } else { 1669 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1670 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1671 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1672 BGE_EVTENB_MI_INTERRUPT); 1673 } 1674 1675 /* Enable link state change attentions. */ 1676 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1677 1678 return(0); 1679 } 1680 1681 static const struct bge_revision { 1682 uint32_t br_chipid; 1683 uint32_t br_quirks; 1684 const char *br_name; 1685 } bge_revisions[] = { 1686 { BGE_CHIPID_BCM5700_A0, 1687 BGE_QUIRK_LINK_STATE_BROKEN, 1688 "BCM5700 A0" }, 1689 1690 { BGE_CHIPID_BCM5700_A1, 1691 BGE_QUIRK_LINK_STATE_BROKEN, 1692 "BCM5700 A1" }, 1693 1694 { BGE_CHIPID_BCM5700_B0, 1695 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1696 "BCM5700 B0" }, 1697 1698 { BGE_CHIPID_BCM5700_B1, 1699 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1700 "BCM5700 B1" }, 1701 1702 { BGE_CHIPID_BCM5700_B2, 1703 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1704 "BCM5700 B2" }, 1705 1706 /* This is treated like a BCM5700 Bx */ 1707 { BGE_CHIPID_BCM5700_ALTIMA, 1708 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1709 "BCM5700 Altima" }, 1710 1711 { BGE_CHIPID_BCM5700_C0, 1712 0, 1713 "BCM5700 C0" }, 1714 1715 { BGE_CHIPID_BCM5701_A0, 1716 0, /*XXX really, just not known */ 1717 "BCM5701 A0" }, 1718 1719 { BGE_CHIPID_BCM5701_B0, 1720 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1721 "BCM5701 B0" }, 1722 1723 { BGE_CHIPID_BCM5701_B2, 1724 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1725 "BCM5701 B2" }, 1726 1727 { BGE_CHIPID_BCM5701_B5, 1728 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1729 "BCM5701 B5" }, 1730 1731 { BGE_CHIPID_BCM5703_A0, 1732 0, 1733 "BCM5703 A0" }, 1734 1735 { BGE_CHIPID_BCM5703_A1, 1736 0, 1737 "BCM5703 A1" }, 1738 1739 { BGE_CHIPID_BCM5703_A2, 1740 BGE_QUIRK_ONLY_PHY_1, 1741 "BCM5703 A2" }, 1742 1743 { BGE_CHIPID_BCM5703_A3, 1744 BGE_QUIRK_ONLY_PHY_1, 1745 "BCM5703 A3" }, 1746 1747 { BGE_CHIPID_BCM5704_A0, 1748 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1749 "BCM5704 A0" }, 1750 1751 { BGE_CHIPID_BCM5704_A1, 1752 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1753 "BCM5704 A1" }, 1754 1755 { BGE_CHIPID_BCM5704_A2, 1756 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1757 "BCM5704 A2" }, 1758 1759 { BGE_CHIPID_BCM5704_A3, 1760 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1761 "BCM5704 A3" }, 1762 1763 { BGE_CHIPID_BCM5705_A0, 1764 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1765 "BCM5705 A0" }, 1766 1767 { BGE_CHIPID_BCM5705_A1, 1768 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1769 "BCM5705 A1" }, 1770 1771 { BGE_CHIPID_BCM5705_A2, 1772 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1773 "BCM5705 A2" }, 1774 1775 { BGE_CHIPID_BCM5705_A3, 1776 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1777 "BCM5705 A3" }, 1778 1779 { 0, 0, NULL } 1780 }; 1781 1782 /* 1783 * Some defaults for major revisions, so that newer steppings 1784 * that we don't know about have a shot at working. 1785 */ 1786 static const struct bge_revision bge_majorrevs[] = { 1787 { BGE_ASICREV_BCM5700, 1788 BGE_QUIRK_LINK_STATE_BROKEN, 1789 "unknown BCM5700" }, 1790 1791 { BGE_ASICREV_BCM5701, 1792 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1793 "unknown BCM5701" }, 1794 1795 { BGE_ASICREV_BCM5703, 1796 0, 1797 "unknown BCM5703" }, 1798 1799 { BGE_ASICREV_BCM5704, 1800 BGE_QUIRK_ONLY_PHY_1, 1801 "unknown BCM5704" }, 1802 1803 { BGE_ASICREV_BCM5705, 1804 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1805 "unknown BCM5705" }, 1806 1807 { 0, 1808 0, 1809 NULL } 1810 }; 1811 1812 1813 static const struct bge_revision * 1814 bge_lookup_rev(uint32_t chipid) 1815 { 1816 const struct bge_revision *br; 1817 1818 for (br = bge_revisions; br->br_name != NULL; br++) { 1819 if (br->br_chipid == chipid) 1820 return (br); 1821 } 1822 1823 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1824 if (br->br_chipid == BGE_ASICREV(chipid)) 1825 return (br); 1826 } 1827 1828 return (NULL); 1829 } 1830 1831 static const struct bge_product { 1832 pci_vendor_id_t bp_vendor; 1833 pci_product_id_t bp_product; 1834 const char *bp_name; 1835 } bge_products[] = { 1836 /* 1837 * The BCM5700 documentation seems to indicate that the hardware 1838 * still has the Alteon vendor ID burned into it, though it 1839 * should always be overridden by the value in the EEPROM. We'll 1840 * check for it anyway. 1841 */ 1842 { PCI_VENDOR_ALTEON, 1843 PCI_PRODUCT_ALTEON_BCM5700, 1844 "Broadcom BCM5700 Gigabit Ethernet", 1845 }, 1846 { PCI_VENDOR_ALTEON, 1847 PCI_PRODUCT_ALTEON_BCM5701, 1848 "Broadcom BCM5701 Gigabit Ethernet", 1849 }, 1850 1851 { PCI_VENDOR_ALTIMA, 1852 PCI_PRODUCT_ALTIMA_AC1000, 1853 "Altima AC1000 Gigabit Ethernet", 1854 }, 1855 { PCI_VENDOR_ALTIMA, 1856 PCI_PRODUCT_ALTIMA_AC1001, 1857 "Altima AC1001 Gigabit Ethernet", 1858 }, 1859 { PCI_VENDOR_ALTIMA, 1860 PCI_PRODUCT_ALTIMA_AC9100, 1861 "Altima AC9100 Gigabit Ethernet", 1862 }, 1863 1864 { PCI_VENDOR_BROADCOM, 1865 PCI_PRODUCT_BROADCOM_BCM5700, 1866 "Broadcom BCM5700 Gigabit Ethernet", 1867 }, 1868 { PCI_VENDOR_BROADCOM, 1869 PCI_PRODUCT_BROADCOM_BCM5701, 1870 "Broadcom BCM5701 Gigabit Ethernet", 1871 }, 1872 { PCI_VENDOR_BROADCOM, 1873 PCI_PRODUCT_BROADCOM_BCM5702, 1874 "Broadcom BCM5702 Gigabit Ethernet", 1875 }, 1876 { PCI_VENDOR_BROADCOM, 1877 PCI_PRODUCT_BROADCOM_BCM5702X, 1878 "Broadcom BCM5702X Gigabit Ethernet" }, 1879 1880 { PCI_VENDOR_BROADCOM, 1881 PCI_PRODUCT_BROADCOM_BCM5703, 1882 "Broadcom BCM5703 Gigabit Ethernet", 1883 }, 1884 { PCI_VENDOR_BROADCOM, 1885 PCI_PRODUCT_BROADCOM_BCM5703X, 1886 "Broadcom BCM5703X Gigabit Ethernet", 1887 }, 1888 { PCI_VENDOR_BROADCOM, 1889 PCI_PRODUCT_BROADCOM_BCM5703A3, 1890 "Broadcom BCM5703A3 Gigabit Ethernet", 1891 }, 1892 1893 { PCI_VENDOR_BROADCOM, 1894 PCI_PRODUCT_BROADCOM_BCM5704C, 1895 "Broadcom BCM5704C Dual Gigabit Ethernet", 1896 }, 1897 { PCI_VENDOR_BROADCOM, 1898 PCI_PRODUCT_BROADCOM_BCM5704S, 1899 "Broadcom BCM5704S Dual Gigabit Ethernet", 1900 }, 1901 1902 { PCI_VENDOR_BROADCOM, 1903 PCI_PRODUCT_BROADCOM_BCM5705, 1904 "Broadcom BCM5705 Gigabit Ethernet", 1905 }, 1906 { PCI_VENDOR_BROADCOM, 1907 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 1908 "Broadcom BCM5705 Gigabit Ethernet", 1909 }, 1910 { PCI_VENDOR_BROADCOM, 1911 PCI_PRODUCT_BROADCOM_BCM5705M, 1912 "Broadcom BCM5705M Gigabit Ethernet", 1913 }, 1914 1915 { PCI_VENDOR_BROADCOM, 1916 PCI_PRODUCT_BROADCOM_BCM5901, 1917 "Broadcom BCM5901 Fast Ethernet", 1918 }, 1919 { PCI_VENDOR_BROADCOM, 1920 PCI_PRODUCT_BROADCOM_BCM5901A2, 1921 "Broadcom BCM5901A2 Fast Ethernet", 1922 }, 1923 1924 { PCI_VENDOR_BROADCOM, 1925 PCI_PRODUCT_BROADCOM_BCM5782, 1926 "Broadcom BCM5782 Gigabit Ethernet", 1927 }, 1928 1929 { PCI_VENDOR_SCHNEIDERKOCH, 1930 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1931 "SysKonnect SK-9Dx1 Gigabit Ethernet", 1932 }, 1933 1934 { PCI_VENDOR_3COM, 1935 PCI_PRODUCT_3COM_3C996, 1936 "3Com 3c996 Gigabit Ethernet", 1937 }, 1938 1939 { 0, 1940 0, 1941 NULL }, 1942 }; 1943 1944 static const struct bge_product * 1945 bge_lookup(const struct pci_attach_args *pa) 1946 { 1947 const struct bge_product *bp; 1948 1949 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1950 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1951 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1952 return (bp); 1953 } 1954 1955 return (NULL); 1956 } 1957 1958 int 1959 bge_setpowerstate(sc, powerlevel) 1960 struct bge_softc *sc; 1961 int powerlevel; 1962 { 1963 #ifdef NOTYET 1964 u_int32_t pm_ctl = 0; 1965 1966 /* XXX FIXME: make sure indirect accesses enabled? */ 1967 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 1968 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 1969 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 1970 1971 /* clear the PME_assert bit and power state bits, enable PME */ 1972 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 1973 pm_ctl &= ~PCIM_PSTAT_DMASK; 1974 pm_ctl |= (1 << 8); 1975 1976 if (powerlevel == 0) { 1977 pm_ctl |= PCIM_PSTAT_D0; 1978 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 1979 pm_ctl, 2); 1980 DELAY(10000); 1981 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1982 DELAY(10000); 1983 1984 #ifdef NOTYET 1985 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 1986 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 1987 #endif 1988 DELAY(40); DELAY(40); DELAY(40); 1989 DELAY(10000); /* above not quite adequate on 5700 */ 1990 return 0; 1991 } 1992 1993 1994 /* 1995 * Entering ACPI power states D1-D3 is achieved by wiggling 1996 * GMII gpio pins. Example code assumes all hardware vendors 1997 * followed Broadom's sample pcb layout. Until we verify that 1998 * for all supported OEM cards, states D1-D3 are unsupported. 1999 */ 2000 printf("%s: power state %d unimplemented; check GPIO pins\n", 2001 sc->bge_dev.dv_xname, powerlevel); 2002 #endif 2003 return EOPNOTSUPP; 2004 } 2005 2006 2007 /* 2008 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2009 * against our list and return its name if we find a match. Note 2010 * that since the Broadcom controller contains VPD support, we 2011 * can get the device name string from the controller itself instead 2012 * of the compiled-in string. This is a little slow, but it guarantees 2013 * we'll always announce the right product name. 2014 */ 2015 int 2016 bge_probe(parent, match, aux) 2017 struct device *parent; 2018 struct cfdata *match; 2019 void *aux; 2020 { 2021 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2022 2023 if (bge_lookup(pa) != NULL) 2024 return (1); 2025 2026 return (0); 2027 } 2028 2029 void 2030 bge_attach(parent, self, aux) 2031 struct device *parent, *self; 2032 void *aux; 2033 { 2034 struct bge_softc *sc = (struct bge_softc *)self; 2035 struct pci_attach_args *pa = aux; 2036 const struct bge_product *bp; 2037 const struct bge_revision *br; 2038 pci_chipset_tag_t pc = pa->pa_pc; 2039 pci_intr_handle_t ih; 2040 const char *intrstr = NULL; 2041 bus_dma_segment_t seg; 2042 int rseg; 2043 u_int32_t hwcfg = 0; 2044 u_int32_t mac_addr = 0; 2045 u_int32_t command; 2046 struct ifnet *ifp; 2047 caddr_t kva; 2048 u_char eaddr[ETHER_ADDR_LEN]; 2049 pcireg_t memtype; 2050 bus_addr_t memaddr; 2051 bus_size_t memsize; 2052 u_int32_t pm_ctl; 2053 2054 bp = bge_lookup(pa); 2055 KASSERT(bp != NULL); 2056 2057 sc->bge_pa = *pa; 2058 2059 aprint_naive(": Ethernet controller\n"); 2060 aprint_normal(": %s\n", bp->bp_name); 2061 2062 /* 2063 * Map control/status registers. 2064 */ 2065 DPRINTFN(5, ("Map control/status regs\n")); 2066 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2067 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2068 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2069 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2070 2071 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2072 aprint_error("%s: failed to enable memory mapping!\n", 2073 sc->bge_dev.dv_xname); 2074 return; 2075 } 2076 2077 DPRINTFN(5, ("pci_mem_find\n")); 2078 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2079 switch (memtype) { 2080 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2081 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2082 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2083 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2084 &memaddr, &memsize) == 0) 2085 break; 2086 default: 2087 aprint_error("%s: can't find mem space\n", 2088 sc->bge_dev.dv_xname); 2089 return; 2090 } 2091 2092 DPRINTFN(5, ("pci_intr_map\n")); 2093 if (pci_intr_map(pa, &ih)) { 2094 aprint_error("%s: couldn't map interrupt\n", 2095 sc->bge_dev.dv_xname); 2096 return; 2097 } 2098 2099 DPRINTFN(5, ("pci_intr_string\n")); 2100 intrstr = pci_intr_string(pc, ih); 2101 2102 DPRINTFN(5, ("pci_intr_establish\n")); 2103 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2104 2105 if (sc->bge_intrhand == NULL) { 2106 aprint_error("%s: couldn't establish interrupt", 2107 sc->bge_dev.dv_xname); 2108 if (intrstr != NULL) 2109 aprint_normal(" at %s", intrstr); 2110 aprint_normal("\n"); 2111 return; 2112 } 2113 aprint_normal("%s: interrupting at %s\n", 2114 sc->bge_dev.dv_xname, intrstr); 2115 2116 /* 2117 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2118 * can clobber the chip's PCI config-space power control registers, 2119 * leaving the card in D3 powersave state. 2120 * We do not have memory-mapped registers in this state, 2121 * so force device into D0 state before starting initialization. 2122 */ 2123 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2124 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2125 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2126 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2127 DELAY(1000); /* 27 usec is allegedly sufficent */ 2128 2129 /* Try to reset the chip. */ 2130 DPRINTFN(5, ("bge_reset\n")); 2131 bge_reset(sc); 2132 2133 if (bge_chipinit(sc)) { 2134 aprint_error("%s: chip initialization failed\n", 2135 sc->bge_dev.dv_xname); 2136 bge_release_resources(sc); 2137 return; 2138 } 2139 2140 /* 2141 * Get station address from the EEPROM. 2142 */ 2143 mac_addr = bge_readmem_ind(sc, 0x0c14); 2144 if ((mac_addr >> 16) == 0x484b) { 2145 eaddr[0] = (u_char)(mac_addr >> 8); 2146 eaddr[1] = (u_char)(mac_addr >> 0); 2147 mac_addr = bge_readmem_ind(sc, 0x0c18); 2148 eaddr[2] = (u_char)(mac_addr >> 24); 2149 eaddr[3] = (u_char)(mac_addr >> 16); 2150 eaddr[4] = (u_char)(mac_addr >> 8); 2151 eaddr[5] = (u_char)(mac_addr >> 0); 2152 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2153 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2154 aprint_error("%s: failed to read station address\n", 2155 sc->bge_dev.dv_xname); 2156 bge_release_resources(sc); 2157 return; 2158 } 2159 2160 /* 2161 * Save ASIC rev. Look up any quirks associated with this 2162 * ASIC. 2163 */ 2164 sc->bge_chipid = 2165 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2166 BGE_PCIMISCCTL_ASICREV; 2167 br = bge_lookup_rev(sc->bge_chipid); 2168 2169 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2170 2171 if (br == NULL) { 2172 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2173 sc->bge_quirks = 0; 2174 } else { 2175 aprint_normal("ASIC %s (0x%04x)", 2176 br->br_name, sc->bge_chipid >> 16); 2177 sc->bge_quirks |= br->br_quirks; 2178 } 2179 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2180 2181 /* Allocate the general information block and ring buffers. */ 2182 if (pci_dma64_available(pa)) 2183 sc->bge_dmatag = pa->pa_dmat64; 2184 else 2185 sc->bge_dmatag = pa->pa_dmat; 2186 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2187 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2188 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2189 aprint_error("%s: can't alloc rx buffers\n", 2190 sc->bge_dev.dv_xname); 2191 return; 2192 } 2193 DPRINTFN(5, ("bus_dmamem_map\n")); 2194 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2195 sizeof(struct bge_ring_data), &kva, 2196 BUS_DMA_NOWAIT)) { 2197 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2198 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2199 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2200 return; 2201 } 2202 DPRINTFN(5, ("bus_dmamem_create\n")); 2203 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2204 sizeof(struct bge_ring_data), 0, 2205 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2206 aprint_error("%s: can't create DMA map\n", 2207 sc->bge_dev.dv_xname); 2208 bus_dmamem_unmap(sc->bge_dmatag, kva, 2209 sizeof(struct bge_ring_data)); 2210 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2211 return; 2212 } 2213 DPRINTFN(5, ("bus_dmamem_load\n")); 2214 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2215 sizeof(struct bge_ring_data), NULL, 2216 BUS_DMA_NOWAIT)) { 2217 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2218 bus_dmamem_unmap(sc->bge_dmatag, kva, 2219 sizeof(struct bge_ring_data)); 2220 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2221 return; 2222 } 2223 2224 DPRINTFN(5, ("bzero\n")); 2225 sc->bge_rdata = (struct bge_ring_data *)kva; 2226 2227 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2228 2229 /* Try to allocate memory for jumbo buffers. */ 2230 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2231 if (bge_alloc_jumbo_mem(sc)) { 2232 aprint_error("%s: jumbo buffer allocation failed\n", 2233 sc->bge_dev.dv_xname); 2234 } else 2235 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2236 } 2237 2238 /* Set default tuneable values. */ 2239 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2240 sc->bge_rx_coal_ticks = 150; 2241 sc->bge_rx_max_coal_bds = 64; 2242 #ifdef ORIG_WPAUL_VALUES 2243 sc->bge_tx_coal_ticks = 150; 2244 sc->bge_tx_max_coal_bds = 128; 2245 #else 2246 sc->bge_tx_coal_ticks = 300; 2247 sc->bge_tx_max_coal_bds = 400; 2248 #endif 2249 2250 /* Set up ifnet structure */ 2251 ifp = &sc->ethercom.ec_if; 2252 ifp->if_softc = sc; 2253 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2254 ifp->if_ioctl = bge_ioctl; 2255 ifp->if_start = bge_start; 2256 ifp->if_init = bge_init; 2257 ifp->if_watchdog = bge_watchdog; 2258 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2259 IFQ_SET_READY(&ifp->if_snd); 2260 DPRINTFN(5, ("bcopy\n")); 2261 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2262 2263 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2264 sc->ethercom.ec_if.if_capabilities |= 2265 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 2266 sc->ethercom.ec_capabilities |= 2267 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2268 2269 /* 2270 * Do MII setup. 2271 */ 2272 DPRINTFN(5, ("mii setup\n")); 2273 sc->bge_mii.mii_ifp = ifp; 2274 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2275 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2276 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2277 2278 /* 2279 * Figure out what sort of media we have by checking the 2280 * hardware config word in the first 32k of NIC internal memory, 2281 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2282 * cards, this value appears to be unset. If that's the 2283 * case, we have to rely on identifying the NIC by its PCI 2284 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2285 */ 2286 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2287 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2288 } else { 2289 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2290 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2291 hwcfg = be32toh(hwcfg); 2292 } 2293 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2294 sc->bge_tbi = 1; 2295 2296 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2297 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2298 SK_SUBSYSID_9D41) 2299 sc->bge_tbi = 1; 2300 2301 if (sc->bge_tbi) { 2302 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2303 bge_ifmedia_sts); 2304 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2305 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2306 0, NULL); 2307 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2308 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2309 } else { 2310 /* 2311 * Do transceiver setup. 2312 */ 2313 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2314 bge_ifmedia_sts); 2315 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2316 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 2317 2318 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2319 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2320 ifmedia_add(&sc->bge_mii.mii_media, 2321 IFM_ETHER|IFM_MANUAL, 0, NULL); 2322 ifmedia_set(&sc->bge_mii.mii_media, 2323 IFM_ETHER|IFM_MANUAL); 2324 } else 2325 ifmedia_set(&sc->bge_mii.mii_media, 2326 IFM_ETHER|IFM_AUTO); 2327 } 2328 2329 /* 2330 * When using the BCM5701 in PCI-X mode, data corruption has 2331 * been observed in the first few bytes of some received packets. 2332 * Aligning the packet buffer in memory eliminates the corruption. 2333 * Unfortunately, this misaligns the packet payloads. On platforms 2334 * which do not support unaligned accesses, we will realign the 2335 * payloads by copying the received packets. 2336 */ 2337 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2338 /* If in PCI-X mode, work around the alignment bug. */ 2339 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2340 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2341 BGE_PCISTATE_PCI_BUSSPEED) 2342 sc->bge_rx_alignment_bug = 1; 2343 } 2344 2345 /* 2346 * Call MI attach routine. 2347 */ 2348 DPRINTFN(5, ("if_attach\n")); 2349 if_attach(ifp); 2350 DPRINTFN(5, ("ether_ifattach\n")); 2351 ether_ifattach(ifp, eaddr); 2352 DPRINTFN(5, ("callout_init\n")); 2353 callout_init(&sc->bge_timeout); 2354 } 2355 2356 void 2357 bge_release_resources(sc) 2358 struct bge_softc *sc; 2359 { 2360 if (sc->bge_vpd_prodname != NULL) 2361 free(sc->bge_vpd_prodname, M_DEVBUF); 2362 2363 if (sc->bge_vpd_readonly != NULL) 2364 free(sc->bge_vpd_readonly, M_DEVBUF); 2365 } 2366 2367 void 2368 bge_reset(sc) 2369 struct bge_softc *sc; 2370 { 2371 struct pci_attach_args *pa = &sc->bge_pa; 2372 u_int32_t cachesize, command, pcistate; 2373 int i, val = 0; 2374 2375 /* Save some important PCI state. */ 2376 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2377 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2378 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2379 2380 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2381 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2382 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2383 2384 /* Issue global reset */ 2385 bge_writereg_ind(sc, BGE_MISC_CFG, 2386 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2387 2388 DELAY(1000); 2389 2390 /* Reset some of the PCI state that got zapped by reset */ 2391 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2392 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2393 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2394 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2395 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2396 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2397 2398 /* Enable memory arbiter. */ 2399 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2400 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2401 } 2402 2403 /* 2404 * Prevent PXE restart: write a magic number to the 2405 * general communications memory at 0xB50. 2406 */ 2407 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2408 2409 /* 2410 * Poll the value location we just wrote until 2411 * we see the 1's complement of the magic number. 2412 * This indicates that the firmware initialization 2413 * is complete. 2414 */ 2415 for (i = 0; i < 750; i++) { 2416 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2417 if (val == ~BGE_MAGIC_NUMBER) 2418 break; 2419 DELAY(1000); 2420 } 2421 2422 if (i == 750) { 2423 printf("%s: firmware handshake timed out, val = %x\n", 2424 sc->bge_dev.dv_xname, val); 2425 return; 2426 } 2427 2428 /* 2429 * XXX Wait for the value of the PCISTATE register to 2430 * return to its original pre-reset state. This is a 2431 * fairly good indicator of reset completion. If we don't 2432 * wait for the reset to fully complete, trying to read 2433 * from the device's non-PCI registers may yield garbage 2434 * results. 2435 */ 2436 for (i = 0; i < BGE_TIMEOUT; i++) { 2437 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2438 pcistate) 2439 break; 2440 DELAY(10); 2441 } 2442 2443 /* Enable memory arbiter. */ 2444 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2445 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2446 } 2447 2448 /* Fix up byte swapping */ 2449 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2450 2451 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2452 2453 DELAY(10000); 2454 } 2455 2456 /* 2457 * Frame reception handling. This is called if there's a frame 2458 * on the receive return list. 2459 * 2460 * Note: we have to be able to handle two possibilities here: 2461 * 1) the frame is from the jumbo recieve ring 2462 * 2) the frame is from the standard receive ring 2463 */ 2464 2465 void 2466 bge_rxeof(sc) 2467 struct bge_softc *sc; 2468 { 2469 struct ifnet *ifp; 2470 int stdcnt = 0, jumbocnt = 0; 2471 int have_tag = 0; 2472 u_int16_t vlan_tag = 0; 2473 bus_dmamap_t dmamap; 2474 bus_addr_t offset, toff; 2475 bus_size_t tlen; 2476 int tosync; 2477 2478 ifp = &sc->ethercom.ec_if; 2479 2480 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2481 offsetof(struct bge_ring_data, bge_status_block), 2482 sizeof (struct bge_status_block), 2483 BUS_DMASYNC_POSTREAD); 2484 2485 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2486 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2487 sc->bge_rx_saved_considx; 2488 2489 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2490 2491 if (tosync < 0) { 2492 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2493 sizeof (struct bge_rx_bd); 2494 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2495 toff, tlen, BUS_DMASYNC_POSTREAD); 2496 tosync = -tosync; 2497 } 2498 2499 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2500 offset, tosync * sizeof (struct bge_rx_bd), 2501 BUS_DMASYNC_POSTREAD); 2502 2503 while(sc->bge_rx_saved_considx != 2504 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2505 struct bge_rx_bd *cur_rx; 2506 u_int32_t rxidx; 2507 struct mbuf *m = NULL; 2508 2509 cur_rx = &sc->bge_rdata-> 2510 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2511 2512 rxidx = cur_rx->bge_idx; 2513 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2514 2515 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2516 have_tag = 1; 2517 vlan_tag = cur_rx->bge_vlan_tag; 2518 } 2519 2520 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2521 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2522 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2523 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2524 jumbocnt++; 2525 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2526 ifp->if_ierrors++; 2527 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2528 continue; 2529 } 2530 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2531 NULL)== ENOBUFS) { 2532 ifp->if_ierrors++; 2533 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2534 continue; 2535 } 2536 } else { 2537 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2538 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2539 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2540 stdcnt++; 2541 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2542 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2543 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2544 ifp->if_ierrors++; 2545 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2546 continue; 2547 } 2548 if (bge_newbuf_std(sc, sc->bge_std, 2549 NULL, dmamap) == ENOBUFS) { 2550 ifp->if_ierrors++; 2551 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2552 continue; 2553 } 2554 } 2555 2556 ifp->if_ipackets++; 2557 #ifndef __NO_STRICT_ALIGNMENT 2558 /* 2559 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2560 * the Rx buffer has the layer-2 header unaligned. 2561 * If our CPU requires alignment, re-align by copying. 2562 */ 2563 if (sc->bge_rx_alignment_bug) { 2564 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2565 cur_rx->bge_len); 2566 m->m_data += ETHER_ALIGN; 2567 } 2568 #endif 2569 2570 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2571 m->m_pkthdr.rcvif = ifp; 2572 2573 #if NBPFILTER > 0 2574 /* 2575 * Handle BPF listeners. Let the BPF user see the packet. 2576 */ 2577 if (ifp->if_bpf) 2578 bpf_mtap(ifp->if_bpf, m); 2579 #endif 2580 2581 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2582 2583 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2584 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2585 /* 2586 * Rx transport checksum-offload may also 2587 * have bugs with packets which, when transmitted, 2588 * were `runts' requiring padding. 2589 */ 2590 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2591 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2592 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2593 m->m_pkthdr.csum_data = 2594 cur_rx->bge_tcp_udp_csum; 2595 m->m_pkthdr.csum_flags |= 2596 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2597 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2598 } 2599 2600 /* 2601 * If we received a packet with a vlan tag, pass it 2602 * to vlan_input() instead of ether_input(). 2603 */ 2604 if (have_tag) { 2605 struct m_tag *mtag; 2606 2607 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2608 M_NOWAIT); 2609 if (mtag != NULL) { 2610 *(u_int *)(mtag + 1) = vlan_tag; 2611 m_tag_prepend(m, mtag); 2612 have_tag = vlan_tag = 0; 2613 } else { 2614 printf("%s: no mbuf for tag\n", ifp->if_xname); 2615 m_freem(m); 2616 have_tag = vlan_tag = 0; 2617 continue; 2618 } 2619 } 2620 (*ifp->if_input)(ifp, m); 2621 } 2622 2623 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2624 if (stdcnt) 2625 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2626 if (jumbocnt) 2627 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2628 } 2629 2630 void 2631 bge_txeof(sc) 2632 struct bge_softc *sc; 2633 { 2634 struct bge_tx_bd *cur_tx = NULL; 2635 struct ifnet *ifp; 2636 struct txdmamap_pool_entry *dma; 2637 bus_addr_t offset, toff; 2638 bus_size_t tlen; 2639 int tosync; 2640 struct mbuf *m; 2641 2642 ifp = &sc->ethercom.ec_if; 2643 2644 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2645 offsetof(struct bge_ring_data, bge_status_block), 2646 sizeof (struct bge_status_block), 2647 BUS_DMASYNC_POSTREAD); 2648 2649 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2650 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2651 sc->bge_tx_saved_considx; 2652 2653 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2654 2655 if (tosync < 0) { 2656 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2657 sizeof (struct bge_tx_bd); 2658 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2659 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2660 tosync = -tosync; 2661 } 2662 2663 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2664 offset, tosync * sizeof (struct bge_tx_bd), 2665 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2666 2667 /* 2668 * Go through our tx ring and free mbufs for those 2669 * frames that have been sent. 2670 */ 2671 while (sc->bge_tx_saved_considx != 2672 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2673 u_int32_t idx = 0; 2674 2675 idx = sc->bge_tx_saved_considx; 2676 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2677 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2678 ifp->if_opackets++; 2679 m = sc->bge_cdata.bge_tx_chain[idx]; 2680 if (m != NULL) { 2681 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2682 dma = sc->txdma[idx]; 2683 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2684 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2685 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2686 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2687 sc->txdma[idx] = NULL; 2688 2689 m_freem(m); 2690 } 2691 sc->bge_txcnt--; 2692 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2693 ifp->if_timer = 0; 2694 } 2695 2696 if (cur_tx != NULL) 2697 ifp->if_flags &= ~IFF_OACTIVE; 2698 } 2699 2700 int 2701 bge_intr(xsc) 2702 void *xsc; 2703 { 2704 struct bge_softc *sc; 2705 struct ifnet *ifp; 2706 2707 sc = xsc; 2708 ifp = &sc->ethercom.ec_if; 2709 2710 #ifdef notdef 2711 /* Avoid this for now -- checking this register is expensive. */ 2712 /* Make sure this is really our interrupt. */ 2713 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2714 return (0); 2715 #endif 2716 /* Ack interrupt and stop others from occuring. */ 2717 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2718 2719 /* 2720 * Process link state changes. 2721 * Grrr. The link status word in the status block does 2722 * not work correctly on the BCM5700 rev AX and BX chips, 2723 * according to all avaibable information. Hence, we have 2724 * to enable MII interrupts in order to properly obtain 2725 * async link changes. Unfortunately, this also means that 2726 * we have to read the MAC status register to detect link 2727 * changes, thereby adding an additional register access to 2728 * the interrupt handler. 2729 */ 2730 2731 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2732 u_int32_t status; 2733 2734 status = CSR_READ_4(sc, BGE_MAC_STS); 2735 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2736 sc->bge_link = 0; 2737 callout_stop(&sc->bge_timeout); 2738 bge_tick(sc); 2739 /* Clear the interrupt */ 2740 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2741 BGE_EVTENB_MI_INTERRUPT); 2742 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2743 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2744 BRGPHY_INTRS); 2745 } 2746 } else { 2747 if (sc->bge_rdata->bge_status_block.bge_status & 2748 BGE_STATFLAG_LINKSTATE_CHANGED) { 2749 sc->bge_link = 0; 2750 callout_stop(&sc->bge_timeout); 2751 bge_tick(sc); 2752 /* Clear the interrupt */ 2753 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2754 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2755 BGE_MACSTAT_LINK_CHANGED); 2756 } 2757 } 2758 2759 if (ifp->if_flags & IFF_RUNNING) { 2760 /* Check RX return ring producer/consumer */ 2761 bge_rxeof(sc); 2762 2763 /* Check TX ring producer/consumer */ 2764 bge_txeof(sc); 2765 } 2766 2767 bge_handle_events(sc); 2768 2769 /* Re-enable interrupts. */ 2770 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2771 2772 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2773 bge_start(ifp); 2774 2775 return (1); 2776 } 2777 2778 void 2779 bge_tick(xsc) 2780 void *xsc; 2781 { 2782 struct bge_softc *sc = xsc; 2783 struct mii_data *mii = &sc->bge_mii; 2784 struct ifmedia *ifm = NULL; 2785 struct ifnet *ifp = &sc->ethercom.ec_if; 2786 int s; 2787 2788 s = splnet(); 2789 2790 bge_stats_update(sc); 2791 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2792 if (sc->bge_link) { 2793 splx(s); 2794 return; 2795 } 2796 2797 if (sc->bge_tbi) { 2798 ifm = &sc->bge_ifmedia; 2799 if (CSR_READ_4(sc, BGE_MAC_STS) & 2800 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2801 sc->bge_link++; 2802 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2803 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2804 bge_start(ifp); 2805 } 2806 splx(s); 2807 return; 2808 } 2809 2810 mii_tick(mii); 2811 2812 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2813 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2814 sc->bge_link++; 2815 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2816 bge_start(ifp); 2817 } 2818 2819 splx(s); 2820 } 2821 2822 void 2823 bge_stats_update(sc) 2824 struct bge_softc *sc; 2825 { 2826 struct ifnet *ifp = &sc->ethercom.ec_if; 2827 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2828 bus_size_t rstats = BGE_RX_STATS; 2829 2830 #define READ_RSTAT(sc, stats, stat) \ 2831 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 2832 2833 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2834 ifp->if_collisions += 2835 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 2836 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 2837 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 2838 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 2839 return; 2840 } 2841 2842 #undef READ_RSTAT 2843 #define READ_STAT(sc, stats, stat) \ 2844 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2845 2846 ifp->if_collisions += 2847 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2848 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2849 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2850 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2851 ifp->if_collisions; 2852 2853 #undef READ_STAT 2854 2855 #ifdef notdef 2856 ifp->if_collisions += 2857 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2858 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2859 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2860 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2861 ifp->if_collisions; 2862 #endif 2863 } 2864 2865 /* 2866 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2867 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2868 * but when such padded frames employ the bge IP/TCP checksum offload, 2869 * the hardware checksum assist gives incorrect results (possibly 2870 * from incorporating its own padding into the UDP/TCP checksum; who knows). 2871 * If we pad such runts with zeros, the onboard checksum comes out correct. 2872 */ 2873 static __inline int 2874 bge_cksum_pad(struct mbuf *pkt) 2875 { 2876 struct mbuf *last = NULL; 2877 int padlen; 2878 2879 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 2880 2881 /* if there's only the packet-header and we can pad there, use it. */ 2882 if (pkt->m_pkthdr.len == pkt->m_len && 2883 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 2884 last = pkt; 2885 } else { 2886 /* 2887 * Walk packet chain to find last mbuf. We will either 2888 * pad there, or append a new mbuf and pad it 2889 * (thus perhaps avoiding the bcm5700 dma-min bug). 2890 */ 2891 for (last = pkt; last->m_next != NULL; last = last->m_next) { 2892 (void) 0; /* do nothing*/ 2893 } 2894 2895 /* `last' now points to last in chain. */ 2896 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 2897 (void) 0; /* we can pad here, in-place. */ 2898 } else { 2899 /* Allocate new empty mbuf, pad it. Compact later. */ 2900 struct mbuf *n; 2901 MGET(n, M_DONTWAIT, MT_DATA); 2902 n->m_len = 0; 2903 last->m_next = n; 2904 last = n; 2905 } 2906 } 2907 2908 #ifdef DEBUG 2909 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 2910 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 2911 #endif 2912 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 2913 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 2914 last->m_len += padlen; 2915 pkt->m_pkthdr.len += padlen; 2916 return 0; 2917 } 2918 2919 /* 2920 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 2921 */ 2922 static __inline int 2923 bge_compact_dma_runt(struct mbuf *pkt) 2924 { 2925 struct mbuf *m, *prev; 2926 int totlen, prevlen; 2927 2928 prev = NULL; 2929 totlen = 0; 2930 prevlen = -1; 2931 2932 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 2933 int mlen = m->m_len; 2934 int shortfall = 8 - mlen ; 2935 2936 totlen += mlen; 2937 if (mlen == 0) { 2938 continue; 2939 } 2940 if (mlen >= 8) 2941 continue; 2942 2943 /* If we get here, mbuf data is too small for DMA engine. 2944 * Try to fix by shuffling data to prev or next in chain. 2945 * If that fails, do a compacting deep-copy of the whole chain. 2946 */ 2947 2948 /* Internal frag. If fits in prev, copy it there. */ 2949 if (prev && !M_READONLY(prev) && 2950 M_TRAILINGSPACE(prev) >= m->m_len) { 2951 bcopy(m->m_data, 2952 prev->m_data+prev->m_len, 2953 mlen); 2954 prev->m_len += mlen; 2955 m->m_len = 0; 2956 /* XXX stitch chain */ 2957 prev->m_next = m_free(m); 2958 m = prev; 2959 continue; 2960 } 2961 else if (m->m_next != NULL && !M_READONLY(m) && 2962 M_TRAILINGSPACE(m) >= shortfall && 2963 m->m_next->m_len >= (8 + shortfall)) { 2964 /* m is writable and have enough data in next, pull up. */ 2965 2966 bcopy(m->m_next->m_data, 2967 m->m_data+m->m_len, 2968 shortfall); 2969 m->m_len += shortfall; 2970 m->m_next->m_len -= shortfall; 2971 m->m_next->m_data += shortfall; 2972 } 2973 else if (m->m_next == NULL || 1) { 2974 /* Got a runt at the very end of the packet. 2975 * borrow data from the tail of the preceding mbuf and 2976 * update its length in-place. (The original data is still 2977 * valid, so we can do this even if prev is not writable.) 2978 */ 2979 2980 /* if we'd make prev a runt, just move all of its data. */ 2981 #ifdef DEBUG 2982 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 2983 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 2984 #endif 2985 if ((prev->m_len - shortfall) < 8) 2986 shortfall = prev->m_len; 2987 2988 #ifdef notyet /* just do the safe slow thing for now */ 2989 if (!M_READONLY(m)) { 2990 if (M_LEADINGSPACE(m) < shorfall) { 2991 void *m_dat; 2992 m_dat = (m->m_flags & M_PKTHDR) ? 2993 m->m_pktdat : m->dat; 2994 memmove(m_dat, mtod(m, void*), m->m_len); 2995 m->m_data = m_dat; 2996 } 2997 } else 2998 #endif /* just do the safe slow thing */ 2999 { 3000 struct mbuf * n = NULL; 3001 int newprevlen = prev->m_len - shortfall; 3002 3003 MGET(n, M_NOWAIT, MT_DATA); 3004 if (n == NULL) 3005 return ENOBUFS; 3006 KASSERT(m->m_len + shortfall < MLEN 3007 /*, 3008 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3009 3010 /* first copy the data we're stealing from prev */ 3011 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3012 3013 /* update prev->m_len accordingly */ 3014 prev->m_len -= shortfall; 3015 3016 /* copy data from runt m */ 3017 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3018 3019 /* n holds what we stole from prev, plus m */ 3020 n->m_len = shortfall + m->m_len; 3021 3022 /* stitch n into chain and free m */ 3023 n->m_next = m->m_next; 3024 prev->m_next = n; 3025 /* KASSERT(m->m_next == NULL); */ 3026 m->m_next = NULL; 3027 m_free(m); 3028 m = n; /* for continuing loop */ 3029 } 3030 } 3031 prevlen = m->m_len; 3032 } 3033 return 0; 3034 } 3035 3036 /* 3037 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3038 * pointers to descriptors. 3039 */ 3040 int 3041 bge_encap(sc, m_head, txidx) 3042 struct bge_softc *sc; 3043 struct mbuf *m_head; 3044 u_int32_t *txidx; 3045 { 3046 struct bge_tx_bd *f = NULL; 3047 u_int32_t frag, cur, cnt = 0; 3048 u_int16_t csum_flags = 0; 3049 struct txdmamap_pool_entry *dma; 3050 bus_dmamap_t dmamap; 3051 int i = 0; 3052 struct m_tag *mtag; 3053 3054 cur = frag = *txidx; 3055 3056 if (m_head->m_pkthdr.csum_flags) { 3057 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3058 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3059 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3060 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3061 } 3062 3063 /* 3064 * If we were asked to do an outboard checksum, and the NIC 3065 * has the bug where it sometimes adds in the Ethernet padding, 3066 * explicitly pad with zeros so the cksum will be correct either way. 3067 * (For now, do this for all chip versions, until newer 3068 * are confirmed to not require the workaround.) 3069 */ 3070 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3071 #ifdef notyet 3072 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3073 #endif 3074 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3075 goto check_dma_bug; 3076 3077 if (bge_cksum_pad(m_head) != 0) 3078 return ENOBUFS; 3079 3080 check_dma_bug: 3081 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3082 goto doit; 3083 /* 3084 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3085 * less than eight bytes. If we encounter a teeny mbuf 3086 * at the end of a chain, we can pad. Otherwise, copy. 3087 */ 3088 if (bge_compact_dma_runt(m_head) != 0) 3089 return ENOBUFS; 3090 3091 doit: 3092 dma = SLIST_FIRST(&sc->txdma_list); 3093 if (dma == NULL) 3094 return ENOBUFS; 3095 dmamap = dma->dmamap; 3096 3097 /* 3098 * Start packing the mbufs in this chain into 3099 * the fragment pointers. Stop when we run out 3100 * of fragments or hit the end of the mbuf chain. 3101 */ 3102 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3103 BUS_DMA_NOWAIT)) 3104 return(ENOBUFS); 3105 3106 mtag = sc->ethercom.ec_nvlans ? 3107 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3108 3109 for (i = 0; i < dmamap->dm_nsegs; i++) { 3110 f = &sc->bge_rdata->bge_tx_ring[frag]; 3111 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3112 break; 3113 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3114 f->bge_len = dmamap->dm_segs[i].ds_len; 3115 f->bge_flags = csum_flags; 3116 3117 if (mtag != NULL) { 3118 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3119 f->bge_vlan_tag = *(u_int *)(mtag + 1); 3120 } else { 3121 f->bge_vlan_tag = 0; 3122 } 3123 /* 3124 * Sanity check: avoid coming within 16 descriptors 3125 * of the end of the ring. 3126 */ 3127 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3128 return(ENOBUFS); 3129 cur = frag; 3130 BGE_INC(frag, BGE_TX_RING_CNT); 3131 cnt++; 3132 } 3133 3134 if (i < dmamap->dm_nsegs) 3135 return ENOBUFS; 3136 3137 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3138 BUS_DMASYNC_PREWRITE); 3139 3140 if (frag == sc->bge_tx_saved_considx) 3141 return(ENOBUFS); 3142 3143 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3144 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3145 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3146 sc->txdma[cur] = dma; 3147 sc->bge_txcnt += cnt; 3148 3149 *txidx = frag; 3150 3151 return(0); 3152 } 3153 3154 /* 3155 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3156 * to the mbuf data regions directly in the transmit descriptors. 3157 */ 3158 void 3159 bge_start(ifp) 3160 struct ifnet *ifp; 3161 { 3162 struct bge_softc *sc; 3163 struct mbuf *m_head = NULL; 3164 u_int32_t prodidx = 0; 3165 int pkts = 0; 3166 3167 sc = ifp->if_softc; 3168 3169 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3170 return; 3171 3172 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3173 3174 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3175 IFQ_POLL(&ifp->if_snd, m_head); 3176 if (m_head == NULL) 3177 break; 3178 3179 #if 0 3180 /* 3181 * XXX 3182 * safety overkill. If this is a fragmented packet chain 3183 * with delayed TCP/UDP checksums, then only encapsulate 3184 * it if we have enough descriptors to handle the entire 3185 * chain at once. 3186 * (paranoia -- may not actually be needed) 3187 */ 3188 if (m_head->m_flags & M_FIRSTFRAG && 3189 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3190 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3191 m_head->m_pkthdr.csum_data + 16) { 3192 ifp->if_flags |= IFF_OACTIVE; 3193 break; 3194 } 3195 } 3196 #endif 3197 3198 /* 3199 * Pack the data into the transmit ring. If we 3200 * don't have room, set the OACTIVE flag and wait 3201 * for the NIC to drain the ring. 3202 */ 3203 if (bge_encap(sc, m_head, &prodidx)) { 3204 ifp->if_flags |= IFF_OACTIVE; 3205 break; 3206 } 3207 3208 /* now we are committed to transmit the packet */ 3209 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3210 pkts++; 3211 3212 #if NBPFILTER > 0 3213 /* 3214 * If there's a BPF listener, bounce a copy of this frame 3215 * to him. 3216 */ 3217 if (ifp->if_bpf) 3218 bpf_mtap(ifp->if_bpf, m_head); 3219 #endif 3220 } 3221 if (pkts == 0) 3222 return; 3223 3224 /* Transmit */ 3225 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3226 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3227 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3228 3229 /* 3230 * Set a timeout in case the chip goes out to lunch. 3231 */ 3232 ifp->if_timer = 5; 3233 } 3234 3235 int 3236 bge_init(ifp) 3237 struct ifnet *ifp; 3238 { 3239 struct bge_softc *sc = ifp->if_softc; 3240 u_int16_t *m; 3241 int s, error; 3242 3243 s = splnet(); 3244 3245 ifp = &sc->ethercom.ec_if; 3246 3247 /* Cancel pending I/O and flush buffers. */ 3248 bge_stop(sc); 3249 bge_reset(sc); 3250 bge_chipinit(sc); 3251 3252 /* 3253 * Init the various state machines, ring 3254 * control blocks and firmware. 3255 */ 3256 error = bge_blockinit(sc); 3257 if (error != 0) { 3258 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3259 error); 3260 splx(s); 3261 return error; 3262 } 3263 3264 ifp = &sc->ethercom.ec_if; 3265 3266 /* Specify MTU. */ 3267 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3268 ETHER_HDR_LEN + ETHER_CRC_LEN); 3269 3270 /* Load our MAC address. */ 3271 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3272 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3273 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3274 3275 /* Enable or disable promiscuous mode as needed. */ 3276 if (ifp->if_flags & IFF_PROMISC) { 3277 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3278 } else { 3279 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3280 } 3281 3282 /* Program multicast filter. */ 3283 bge_setmulti(sc); 3284 3285 /* Init RX ring. */ 3286 bge_init_rx_ring_std(sc); 3287 3288 /* Init jumbo RX ring. */ 3289 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3290 bge_init_rx_ring_jumbo(sc); 3291 3292 /* Init our RX return ring index */ 3293 sc->bge_rx_saved_considx = 0; 3294 3295 /* Init TX ring. */ 3296 bge_init_tx_ring(sc); 3297 3298 /* Turn on transmitter */ 3299 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3300 3301 /* Turn on receiver */ 3302 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3303 3304 /* Tell firmware we're alive. */ 3305 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3306 3307 /* Enable host interrupts. */ 3308 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3309 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3310 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3311 3312 bge_ifmedia_upd(ifp); 3313 3314 ifp->if_flags |= IFF_RUNNING; 3315 ifp->if_flags &= ~IFF_OACTIVE; 3316 3317 splx(s); 3318 3319 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3320 3321 return 0; 3322 } 3323 3324 /* 3325 * Set media options. 3326 */ 3327 int 3328 bge_ifmedia_upd(ifp) 3329 struct ifnet *ifp; 3330 { 3331 struct bge_softc *sc = ifp->if_softc; 3332 struct mii_data *mii = &sc->bge_mii; 3333 struct ifmedia *ifm = &sc->bge_ifmedia; 3334 3335 /* If this is a 1000baseX NIC, enable the TBI port. */ 3336 if (sc->bge_tbi) { 3337 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3338 return(EINVAL); 3339 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3340 case IFM_AUTO: 3341 break; 3342 case IFM_1000_SX: 3343 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3344 BGE_CLRBIT(sc, BGE_MAC_MODE, 3345 BGE_MACMODE_HALF_DUPLEX); 3346 } else { 3347 BGE_SETBIT(sc, BGE_MAC_MODE, 3348 BGE_MACMODE_HALF_DUPLEX); 3349 } 3350 break; 3351 default: 3352 return(EINVAL); 3353 } 3354 return(0); 3355 } 3356 3357 sc->bge_link = 0; 3358 mii_mediachg(mii); 3359 3360 return(0); 3361 } 3362 3363 /* 3364 * Report current media status. 3365 */ 3366 void 3367 bge_ifmedia_sts(ifp, ifmr) 3368 struct ifnet *ifp; 3369 struct ifmediareq *ifmr; 3370 { 3371 struct bge_softc *sc = ifp->if_softc; 3372 struct mii_data *mii = &sc->bge_mii; 3373 3374 if (sc->bge_tbi) { 3375 ifmr->ifm_status = IFM_AVALID; 3376 ifmr->ifm_active = IFM_ETHER; 3377 if (CSR_READ_4(sc, BGE_MAC_STS) & 3378 BGE_MACSTAT_TBI_PCS_SYNCHED) 3379 ifmr->ifm_status |= IFM_ACTIVE; 3380 ifmr->ifm_active |= IFM_1000_SX; 3381 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3382 ifmr->ifm_active |= IFM_HDX; 3383 else 3384 ifmr->ifm_active |= IFM_FDX; 3385 return; 3386 } 3387 3388 mii_pollstat(mii); 3389 ifmr->ifm_active = mii->mii_media_active; 3390 ifmr->ifm_status = mii->mii_media_status; 3391 } 3392 3393 int 3394 bge_ioctl(ifp, command, data) 3395 struct ifnet *ifp; 3396 u_long command; 3397 caddr_t data; 3398 { 3399 struct bge_softc *sc = ifp->if_softc; 3400 struct ifreq *ifr = (struct ifreq *) data; 3401 int s, error = 0; 3402 struct mii_data *mii; 3403 3404 s = splnet(); 3405 3406 switch(command) { 3407 case SIOCSIFFLAGS: 3408 if (ifp->if_flags & IFF_UP) { 3409 /* 3410 * If only the state of the PROMISC flag changed, 3411 * then just use the 'set promisc mode' command 3412 * instead of reinitializing the entire NIC. Doing 3413 * a full re-init means reloading the firmware and 3414 * waiting for it to start up, which may take a 3415 * second or two. 3416 */ 3417 if (ifp->if_flags & IFF_RUNNING && 3418 ifp->if_flags & IFF_PROMISC && 3419 !(sc->bge_if_flags & IFF_PROMISC)) { 3420 BGE_SETBIT(sc, BGE_RX_MODE, 3421 BGE_RXMODE_RX_PROMISC); 3422 } else if (ifp->if_flags & IFF_RUNNING && 3423 !(ifp->if_flags & IFF_PROMISC) && 3424 sc->bge_if_flags & IFF_PROMISC) { 3425 BGE_CLRBIT(sc, BGE_RX_MODE, 3426 BGE_RXMODE_RX_PROMISC); 3427 } else 3428 bge_init(ifp); 3429 } else { 3430 if (ifp->if_flags & IFF_RUNNING) { 3431 bge_stop(sc); 3432 } 3433 } 3434 sc->bge_if_flags = ifp->if_flags; 3435 error = 0; 3436 break; 3437 case SIOCSIFMEDIA: 3438 case SIOCGIFMEDIA: 3439 if (sc->bge_tbi) { 3440 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3441 command); 3442 } else { 3443 mii = &sc->bge_mii; 3444 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3445 command); 3446 } 3447 error = 0; 3448 break; 3449 default: 3450 error = ether_ioctl(ifp, command, data); 3451 if (error == ENETRESET) { 3452 bge_setmulti(sc); 3453 error = 0; 3454 } 3455 break; 3456 } 3457 3458 splx(s); 3459 3460 return(error); 3461 } 3462 3463 void 3464 bge_watchdog(ifp) 3465 struct ifnet *ifp; 3466 { 3467 struct bge_softc *sc; 3468 3469 sc = ifp->if_softc; 3470 3471 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3472 3473 ifp->if_flags &= ~IFF_RUNNING; 3474 bge_init(ifp); 3475 3476 ifp->if_oerrors++; 3477 } 3478 3479 static void 3480 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3481 { 3482 int i; 3483 3484 BGE_CLRBIT(sc, reg, bit); 3485 3486 for (i = 0; i < BGE_TIMEOUT; i++) { 3487 if ((CSR_READ_4(sc, reg) & bit) == 0) 3488 return; 3489 delay(100); 3490 } 3491 3492 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3493 sc->bge_dev.dv_xname, (u_long) reg, bit); 3494 } 3495 3496 /* 3497 * Stop the adapter and free any mbufs allocated to the 3498 * RX and TX lists. 3499 */ 3500 void 3501 bge_stop(sc) 3502 struct bge_softc *sc; 3503 { 3504 struct ifnet *ifp = &sc->ethercom.ec_if; 3505 3506 callout_stop(&sc->bge_timeout); 3507 3508 /* 3509 * Disable all of the receiver blocks 3510 */ 3511 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3512 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3513 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3514 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3515 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3516 } 3517 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3518 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3519 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3520 3521 /* 3522 * Disable all of the transmit blocks 3523 */ 3524 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3525 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3526 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3527 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3528 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3529 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3530 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3531 } 3532 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3533 3534 /* 3535 * Shut down all of the memory managers and related 3536 * state machines. 3537 */ 3538 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3539 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3540 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3541 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3542 } 3543 3544 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3545 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3546 3547 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3548 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3549 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3550 } 3551 3552 /* Disable host interrupts. */ 3553 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3554 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3555 3556 /* 3557 * Tell firmware we're shutting down. 3558 */ 3559 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3560 3561 /* Free the RX lists. */ 3562 bge_free_rx_ring_std(sc); 3563 3564 /* Free jumbo RX list. */ 3565 bge_free_rx_ring_jumbo(sc); 3566 3567 /* Free TX buffers. */ 3568 bge_free_tx_ring(sc); 3569 3570 /* 3571 * Isolate/power down the PHY. 3572 */ 3573 if (!sc->bge_tbi) 3574 mii_down(&sc->bge_mii); 3575 3576 sc->bge_link = 0; 3577 3578 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3579 3580 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3581 } 3582 3583 /* 3584 * Stop all chip I/O so that the kernel's probe routines don't 3585 * get confused by errant DMAs when rebooting. 3586 */ 3587 void 3588 bge_shutdown(xsc) 3589 void *xsc; 3590 { 3591 struct bge_softc *sc = (struct bge_softc *)xsc; 3592 3593 bge_stop(sc); 3594 bge_reset(sc); 3595 } 3596
Indexes created Mon Sep 22 13:09:51 GMT 2025