if_bge.c revision 1.58
1 /* $NetBSD: if_bge.c,v 1.58 2004/01/22 02:29:46 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.58 2004/01/22 02:29:46 jonathan Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/miidevs.h> 120 #include <dev/mii/brgphyreg.h> 121 122 #include <dev/pci/if_bgereg.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 127 128 int bge_probe(struct device *, struct cfdata *, void *); 129 void bge_attach(struct device *, struct device *, void *); 130 void bge_release_resources(struct bge_softc *); 131 void bge_txeof(struct bge_softc *); 132 void bge_rxeof(struct bge_softc *); 133 134 void bge_tick(void *); 135 void bge_stats_update(struct bge_softc *); 136 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 137 static __inline int bge_cksum_pad(struct mbuf *pkt); 138 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 139 140 int bge_intr(void *); 141 void bge_start(struct ifnet *); 142 int bge_ioctl(struct ifnet *, u_long, caddr_t); 143 int bge_init(struct ifnet *); 144 void bge_stop(struct bge_softc *); 145 void bge_watchdog(struct ifnet *); 146 void bge_shutdown(void *); 147 int bge_ifmedia_upd(struct ifnet *); 148 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 149 150 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 151 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 152 153 void bge_setmulti(struct bge_softc *); 154 155 void bge_handle_events(struct bge_softc *); 156 int bge_alloc_jumbo_mem(struct bge_softc *); 157 void bge_free_jumbo_mem(struct bge_softc *); 158 void *bge_jalloc(struct bge_softc *); 159 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 160 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 161 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 162 int bge_init_rx_ring_std(struct bge_softc *); 163 void bge_free_rx_ring_std(struct bge_softc *); 164 int bge_init_rx_ring_jumbo(struct bge_softc *); 165 void bge_free_rx_ring_jumbo(struct bge_softc *); 166 void bge_free_tx_ring(struct bge_softc *); 167 int bge_init_tx_ring(struct bge_softc *); 168 169 int bge_chipinit(struct bge_softc *); 170 int bge_blockinit(struct bge_softc *); 171 int bge_setpowerstate(struct bge_softc *, int); 172 173 #ifdef notdef 174 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 175 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 176 void bge_vpd_read(struct bge_softc *); 177 #endif 178 179 u_int32_t bge_readmem_ind(struct bge_softc *, int); 180 void bge_writemem_ind(struct bge_softc *, int, int); 181 #ifdef notdef 182 u_int32_t bge_readreg_ind(struct bge_softc *, int); 183 #endif 184 void bge_writereg_ind(struct bge_softc *, int, int); 185 186 int bge_miibus_readreg(struct device *, int, int); 187 void bge_miibus_writereg(struct device *, int, int, int); 188 void bge_miibus_statchg(struct device *); 189 190 void bge_reset(struct bge_softc *); 191 192 void bge_dump_status(struct bge_softc *); 193 void bge_dump_rxbd(struct bge_rx_bd *); 194 195 #define BGE_DEBUG 196 #ifdef BGE_DEBUG 197 #define DPRINTF(x) if (bgedebug) printf x 198 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 199 int bgedebug = 0; 200 #else 201 #define DPRINTF(x) 202 #define DPRINTFN(n,x) 203 #endif 204 205 /* Various chip quirks. */ 206 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 207 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 208 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 209 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 210 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 211 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 212 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 213 #define BGE_QUIRK_5705_CORE 0x00000080 214 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 215 216 /* following bugs are common to bcm5700 rev B, all flavours */ 217 #define BGE_QUIRK_5700_COMMON \ 218 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 219 220 CFATTACH_DECL(bge, sizeof(struct bge_softc), 221 bge_probe, bge_attach, NULL, NULL); 222 223 u_int32_t 224 bge_readmem_ind(sc, off) 225 struct bge_softc *sc; 226 int off; 227 { 228 struct pci_attach_args *pa = &(sc->bge_pa); 229 pcireg_t val; 230 231 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 232 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 233 return val; 234 } 235 236 void 237 bge_writemem_ind(sc, off, val) 238 struct bge_softc *sc; 239 int off, val; 240 { 241 struct pci_attach_args *pa = &(sc->bge_pa); 242 243 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 244 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 245 } 246 247 #ifdef notdef 248 u_int32_t 249 bge_readreg_ind(sc, off) 250 struct bge_softc *sc; 251 int off; 252 { 253 struct pci_attach_args *pa = &(sc->bge_pa); 254 255 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 256 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 257 } 258 #endif 259 260 void 261 bge_writereg_ind(sc, off, val) 262 struct bge_softc *sc; 263 int off, val; 264 { 265 struct pci_attach_args *pa = &(sc->bge_pa); 266 267 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 268 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 269 } 270 271 #ifdef notdef 272 u_int8_t 273 bge_vpd_readbyte(sc, addr) 274 struct bge_softc *sc; 275 int addr; 276 { 277 int i; 278 u_int32_t val; 279 struct pci_attach_args *pa = &(sc->bge_pa); 280 281 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 282 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 283 DELAY(10); 284 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 285 BGE_VPD_FLAG) 286 break; 287 } 288 289 if (i == BGE_TIMEOUT) { 290 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 291 return(0); 292 } 293 294 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 295 296 return((val >> ((addr % 4) * 8)) & 0xFF); 297 } 298 299 void 300 bge_vpd_read_res(sc, res, addr) 301 struct bge_softc *sc; 302 struct vpd_res *res; 303 int addr; 304 { 305 int i; 306 u_int8_t *ptr; 307 308 ptr = (u_int8_t *)res; 309 for (i = 0; i < sizeof(struct vpd_res); i++) 310 ptr[i] = bge_vpd_readbyte(sc, i + addr); 311 } 312 313 void 314 bge_vpd_read(sc) 315 struct bge_softc *sc; 316 { 317 int pos = 0, i; 318 struct vpd_res res; 319 320 if (sc->bge_vpd_prodname != NULL) 321 free(sc->bge_vpd_prodname, M_DEVBUF); 322 if (sc->bge_vpd_readonly != NULL) 323 free(sc->bge_vpd_readonly, M_DEVBUF); 324 sc->bge_vpd_prodname = NULL; 325 sc->bge_vpd_readonly = NULL; 326 327 bge_vpd_read_res(sc, &res, pos); 328 329 if (res.vr_id != VPD_RES_ID) { 330 printf("%s: bad VPD resource id: expected %x got %x\n", 331 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 332 return; 333 } 334 335 pos += sizeof(res); 336 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 337 if (sc->bge_vpd_prodname == NULL) 338 panic("bge_vpd_read"); 339 for (i = 0; i < res.vr_len; i++) 340 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 341 sc->bge_vpd_prodname[i] = '\0'; 342 pos += i; 343 344 bge_vpd_read_res(sc, &res, pos); 345 346 if (res.vr_id != VPD_RES_READ) { 347 printf("%s: bad VPD resource id: expected %x got %x\n", 348 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 349 return; 350 } 351 352 pos += sizeof(res); 353 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 354 if (sc->bge_vpd_readonly == NULL) 355 panic("bge_vpd_read"); 356 for (i = 0; i < res.vr_len + 1; i++) 357 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 358 } 359 #endif 360 361 /* 362 * Read a byte of data stored in the EEPROM at address 'addr.' The 363 * BCM570x supports both the traditional bitbang interface and an 364 * auto access interface for reading the EEPROM. We use the auto 365 * access method. 366 */ 367 u_int8_t 368 bge_eeprom_getbyte(sc, addr, dest) 369 struct bge_softc *sc; 370 int addr; 371 u_int8_t *dest; 372 { 373 int i; 374 u_int32_t byte = 0; 375 376 /* 377 * Enable use of auto EEPROM access so we can avoid 378 * having to use the bitbang method. 379 */ 380 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 381 382 /* Reset the EEPROM, load the clock period. */ 383 CSR_WRITE_4(sc, BGE_EE_ADDR, 384 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 385 DELAY(20); 386 387 /* Issue the read EEPROM command. */ 388 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 389 390 /* Wait for completion */ 391 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 392 DELAY(10); 393 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 394 break; 395 } 396 397 if (i == BGE_TIMEOUT) { 398 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 399 return(0); 400 } 401 402 /* Get result. */ 403 byte = CSR_READ_4(sc, BGE_EE_DATA); 404 405 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 406 407 return(0); 408 } 409 410 /* 411 * Read a sequence of bytes from the EEPROM. 412 */ 413 int 414 bge_read_eeprom(sc, dest, off, cnt) 415 struct bge_softc *sc; 416 caddr_t dest; 417 int off; 418 int cnt; 419 { 420 int err = 0, i; 421 u_int8_t byte = 0; 422 423 for (i = 0; i < cnt; i++) { 424 err = bge_eeprom_getbyte(sc, off + i, &byte); 425 if (err) 426 break; 427 *(dest + i) = byte; 428 } 429 430 return(err ? 1 : 0); 431 } 432 433 int 434 bge_miibus_readreg(dev, phy, reg) 435 struct device *dev; 436 int phy, reg; 437 { 438 struct bge_softc *sc = (struct bge_softc *)dev; 439 u_int32_t val; 440 u_int32_t saved_autopoll; 441 int i; 442 443 /* 444 * Several chips with builtin PHYs will incorrectly answer to 445 * other PHY instances than the builtin PHY at id 1. 446 */ 447 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 448 return(0); 449 450 /* Reading with autopolling on may trigger PCI errors */ 451 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 452 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 453 CSR_WRITE_4(sc, BGE_MI_MODE, 454 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 455 DELAY(40); 456 } 457 458 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 459 BGE_MIPHY(phy)|BGE_MIREG(reg)); 460 461 for (i = 0; i < BGE_TIMEOUT; i++) { 462 val = CSR_READ_4(sc, BGE_MI_COMM); 463 if (!(val & BGE_MICOMM_BUSY)) 464 break; 465 delay(10); 466 } 467 468 if (i == BGE_TIMEOUT) { 469 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 470 val = 0; 471 goto done; 472 } 473 474 val = CSR_READ_4(sc, BGE_MI_COMM); 475 476 done: 477 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 478 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 479 DELAY(40); 480 } 481 482 if (val & BGE_MICOMM_READFAIL) 483 return(0); 484 485 return(val & 0xFFFF); 486 } 487 488 void 489 bge_miibus_writereg(dev, phy, reg, val) 490 struct device *dev; 491 int phy, reg, val; 492 { 493 struct bge_softc *sc = (struct bge_softc *)dev; 494 u_int32_t saved_autopoll; 495 int i; 496 497 /* Touching the PHY while autopolling is on may trigger PCI errors */ 498 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 499 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 500 delay(40); 501 CSR_WRITE_4(sc, BGE_MI_MODE, 502 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 503 delay(10); /* 40 usec is supposed to be adequate */ 504 } 505 506 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 507 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 508 509 for (i = 0; i < BGE_TIMEOUT; i++) { 510 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 511 break; 512 delay(10); 513 } 514 515 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 516 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 517 delay(40); 518 } 519 520 if (i == BGE_TIMEOUT) { 521 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 522 } 523 } 524 525 void 526 bge_miibus_statchg(dev) 527 struct device *dev; 528 { 529 struct bge_softc *sc = (struct bge_softc *)dev; 530 struct mii_data *mii = &sc->bge_mii; 531 532 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 533 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 534 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 535 } else { 536 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 537 } 538 539 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 540 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 541 } else { 542 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 543 } 544 } 545 546 /* 547 * Handle events that have triggered interrupts. 548 */ 549 void 550 bge_handle_events(sc) 551 struct bge_softc *sc; 552 { 553 554 return; 555 } 556 557 /* 558 * Memory management for jumbo frames. 559 */ 560 561 int 562 bge_alloc_jumbo_mem(sc) 563 struct bge_softc *sc; 564 { 565 caddr_t ptr, kva; 566 bus_dma_segment_t seg; 567 int i, rseg, state, error; 568 struct bge_jpool_entry *entry; 569 570 state = error = 0; 571 572 /* Grab a big chunk o' storage. */ 573 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 574 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 575 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 576 return ENOBUFS; 577 } 578 579 state = 1; 580 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 581 BUS_DMA_NOWAIT)) { 582 printf("%s: can't map DMA buffers (%d bytes)\n", 583 sc->bge_dev.dv_xname, (int)BGE_JMEM); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 2; 589 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 590 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 591 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 592 error = ENOBUFS; 593 goto out; 594 } 595 596 state = 3; 597 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 598 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 599 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 600 error = ENOBUFS; 601 goto out; 602 } 603 604 state = 4; 605 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 606 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 607 608 SLIST_INIT(&sc->bge_jfree_listhead); 609 SLIST_INIT(&sc->bge_jinuse_listhead); 610 611 /* 612 * Now divide it up into 9K pieces and save the addresses 613 * in an array. 614 */ 615 ptr = sc->bge_cdata.bge_jumbo_buf; 616 for (i = 0; i < BGE_JSLOTS; i++) { 617 sc->bge_cdata.bge_jslots[i] = ptr; 618 ptr += BGE_JLEN; 619 entry = malloc(sizeof(struct bge_jpool_entry), 620 M_DEVBUF, M_NOWAIT); 621 if (entry == NULL) { 622 printf("%s: no memory for jumbo buffer queue!\n", 623 sc->bge_dev.dv_xname); 624 error = ENOBUFS; 625 goto out; 626 } 627 entry->slot = i; 628 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 629 entry, jpool_entries); 630 } 631 out: 632 if (error != 0) { 633 switch (state) { 634 case 4: 635 bus_dmamap_unload(sc->bge_dmatag, 636 sc->bge_cdata.bge_rx_jumbo_map); 637 case 3: 638 bus_dmamap_destroy(sc->bge_dmatag, 639 sc->bge_cdata.bge_rx_jumbo_map); 640 case 2: 641 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 642 case 1: 643 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 644 break; 645 default: 646 break; 647 } 648 } 649 650 return error; 651 } 652 653 /* 654 * Allocate a jumbo buffer. 655 */ 656 void * 657 bge_jalloc(sc) 658 struct bge_softc *sc; 659 { 660 struct bge_jpool_entry *entry; 661 662 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 663 664 if (entry == NULL) { 665 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 666 return(NULL); 667 } 668 669 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 670 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 671 return(sc->bge_cdata.bge_jslots[entry->slot]); 672 } 673 674 /* 675 * Release a jumbo buffer. 676 */ 677 void 678 bge_jfree(m, buf, size, arg) 679 struct mbuf *m; 680 caddr_t buf; 681 size_t size; 682 void *arg; 683 { 684 struct bge_jpool_entry *entry; 685 struct bge_softc *sc; 686 int i, s; 687 688 /* Extract the softc struct pointer. */ 689 sc = (struct bge_softc *)arg; 690 691 if (sc == NULL) 692 panic("bge_jfree: can't find softc pointer!"); 693 694 /* calculate the slot this buffer belongs to */ 695 696 i = ((caddr_t)buf 697 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 698 699 if ((i < 0) || (i >= BGE_JSLOTS)) 700 panic("bge_jfree: asked to free buffer that we don't manage!"); 701 702 s = splvm(); 703 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 704 if (entry == NULL) 705 panic("bge_jfree: buffer not in use!"); 706 entry->slot = i; 707 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 708 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 709 710 if (__predict_true(m != NULL)) 711 pool_cache_put(&mbpool_cache, m); 712 splx(s); 713 } 714 715 716 /* 717 * Intialize a standard receive ring descriptor. 718 */ 719 int 720 bge_newbuf_std(sc, i, m, dmamap) 721 struct bge_softc *sc; 722 int i; 723 struct mbuf *m; 724 bus_dmamap_t dmamap; 725 { 726 struct mbuf *m_new = NULL; 727 struct bge_rx_bd *r; 728 int error; 729 730 if (dmamap == NULL) { 731 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 732 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 733 if (error != 0) 734 return error; 735 } 736 737 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 738 739 if (m == NULL) { 740 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 741 if (m_new == NULL) { 742 return(ENOBUFS); 743 } 744 745 MCLGET(m_new, M_DONTWAIT); 746 if (!(m_new->m_flags & M_EXT)) { 747 m_freem(m_new); 748 return(ENOBUFS); 749 } 750 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 751 if (!sc->bge_rx_alignment_bug) 752 m_adj(m_new, ETHER_ALIGN); 753 754 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 755 BUS_DMA_READ|BUS_DMA_NOWAIT)) 756 return(ENOBUFS); 757 } else { 758 m_new = m; 759 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 760 m_new->m_data = m_new->m_ext.ext_buf; 761 if (!sc->bge_rx_alignment_bug) 762 m_adj(m_new, ETHER_ALIGN); 763 } 764 765 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 766 r = &sc->bge_rdata->bge_rx_std_ring[i]; 767 bge_set_hostaddr(&r->bge_addr, 768 dmamap->dm_segs[0].ds_addr); 769 r->bge_flags = BGE_RXBDFLAG_END; 770 r->bge_len = m_new->m_len; 771 r->bge_idx = i; 772 773 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 774 offsetof(struct bge_ring_data, bge_rx_std_ring) + 775 i * sizeof (struct bge_rx_bd), 776 sizeof (struct bge_rx_bd), 777 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 778 779 return(0); 780 } 781 782 /* 783 * Initialize a jumbo receive ring descriptor. This allocates 784 * a jumbo buffer from the pool managed internally by the driver. 785 */ 786 int 787 bge_newbuf_jumbo(sc, i, m) 788 struct bge_softc *sc; 789 int i; 790 struct mbuf *m; 791 { 792 struct mbuf *m_new = NULL; 793 struct bge_rx_bd *r; 794 795 if (m == NULL) { 796 caddr_t *buf = NULL; 797 798 /* Allocate the mbuf. */ 799 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 800 if (m_new == NULL) { 801 return(ENOBUFS); 802 } 803 804 /* Allocate the jumbo buffer */ 805 buf = bge_jalloc(sc); 806 if (buf == NULL) { 807 m_freem(m_new); 808 printf("%s: jumbo allocation failed " 809 "-- packet dropped!\n", sc->bge_dev.dv_xname); 810 return(ENOBUFS); 811 } 812 813 /* Attach the buffer to the mbuf. */ 814 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 815 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 816 bge_jfree, sc); 817 } else { 818 m_new = m; 819 m_new->m_data = m_new->m_ext.ext_buf; 820 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 821 } 822 823 if (!sc->bge_rx_alignment_bug) 824 m_adj(m_new, ETHER_ALIGN); 825 /* Set up the descriptor. */ 826 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 827 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 828 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 829 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 830 r->bge_len = m_new->m_len; 831 r->bge_idx = i; 832 833 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 834 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 835 i * sizeof (struct bge_rx_bd), 836 sizeof (struct bge_rx_bd), 837 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 838 839 return(0); 840 } 841 842 /* 843 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 844 * that's 1MB or memory, which is a lot. For now, we fill only the first 845 * 256 ring entries and hope that our CPU is fast enough to keep up with 846 * the NIC. 847 */ 848 int 849 bge_init_rx_ring_std(sc) 850 struct bge_softc *sc; 851 { 852 int i; 853 854 if (sc->bge_flags & BGE_RXRING_VALID) 855 return 0; 856 857 for (i = 0; i < BGE_SSLOTS; i++) { 858 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 859 return(ENOBUFS); 860 } 861 862 sc->bge_std = i - 1; 863 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 864 865 sc->bge_flags |= BGE_RXRING_VALID; 866 867 return(0); 868 } 869 870 void 871 bge_free_rx_ring_std(sc) 872 struct bge_softc *sc; 873 { 874 int i; 875 876 if (!(sc->bge_flags & BGE_RXRING_VALID)) 877 return; 878 879 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 880 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 881 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 882 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 883 bus_dmamap_destroy(sc->bge_dmatag, 884 sc->bge_cdata.bge_rx_std_map[i]); 885 } 886 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 887 sizeof(struct bge_rx_bd)); 888 } 889 890 sc->bge_flags &= ~BGE_RXRING_VALID; 891 } 892 893 int 894 bge_init_rx_ring_jumbo(sc) 895 struct bge_softc *sc; 896 { 897 int i; 898 volatile struct bge_rcb *rcb; 899 900 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 901 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 902 return(ENOBUFS); 903 }; 904 905 sc->bge_jumbo = i - 1; 906 907 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 908 rcb->bge_maxlen_flags = 0; 909 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 910 911 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 912 913 return(0); 914 } 915 916 void 917 bge_free_rx_ring_jumbo(sc) 918 struct bge_softc *sc; 919 { 920 int i; 921 922 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 923 return; 924 925 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 926 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 927 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 928 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 929 } 930 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 931 sizeof(struct bge_rx_bd)); 932 } 933 934 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 935 } 936 937 void 938 bge_free_tx_ring(sc) 939 struct bge_softc *sc; 940 { 941 int i, freed; 942 struct txdmamap_pool_entry *dma; 943 944 if (!(sc->bge_flags & BGE_TXRING_VALID)) 945 return; 946 947 freed = 0; 948 949 for (i = 0; i < BGE_TX_RING_CNT; i++) { 950 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 951 freed++; 952 m_freem(sc->bge_cdata.bge_tx_chain[i]); 953 sc->bge_cdata.bge_tx_chain[i] = NULL; 954 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 955 link); 956 sc->txdma[i] = 0; 957 } 958 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 959 sizeof(struct bge_tx_bd)); 960 } 961 962 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 963 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 964 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 965 free(dma, M_DEVBUF); 966 } 967 968 sc->bge_flags &= ~BGE_TXRING_VALID; 969 } 970 971 int 972 bge_init_tx_ring(sc) 973 struct bge_softc *sc; 974 { 975 int i; 976 bus_dmamap_t dmamap; 977 struct txdmamap_pool_entry *dma; 978 979 if (sc->bge_flags & BGE_TXRING_VALID) 980 return 0; 981 982 sc->bge_txcnt = 0; 983 sc->bge_tx_saved_considx = 0; 984 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 985 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 986 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 987 988 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 989 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 990 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 991 992 SLIST_INIT(&sc->txdma_list); 993 for (i = 0; i < BGE_RSLOTS; i++) { 994 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 995 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 996 &dmamap)) 997 return(ENOBUFS); 998 if (dmamap == NULL) 999 panic("dmamap NULL in bge_init_tx_ring"); 1000 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1001 if (dma == NULL) { 1002 printf("%s: can't alloc txdmamap_pool_entry\n", 1003 sc->bge_dev.dv_xname); 1004 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1005 return (ENOMEM); 1006 } 1007 dma->dmamap = dmamap; 1008 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1009 } 1010 1011 sc->bge_flags |= BGE_TXRING_VALID; 1012 1013 return(0); 1014 } 1015 1016 void 1017 bge_setmulti(sc) 1018 struct bge_softc *sc; 1019 { 1020 struct ethercom *ac = &sc->ethercom; 1021 struct ifnet *ifp = &ac->ec_if; 1022 struct ether_multi *enm; 1023 struct ether_multistep step; 1024 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1025 u_int32_t h; 1026 int i; 1027 1028 if (ifp->if_flags & IFF_PROMISC) 1029 goto allmulti; 1030 1031 /* Now program new ones. */ 1032 ETHER_FIRST_MULTI(step, ac, enm); 1033 while (enm != NULL) { 1034 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1035 /* 1036 * We must listen to a range of multicast addresses. 1037 * For now, just accept all multicasts, rather than 1038 * trying to set only those filter bits needed to match 1039 * the range. (At this time, the only use of address 1040 * ranges is for IP multicast routing, for which the 1041 * range is big enough to require all bits set.) 1042 */ 1043 goto allmulti; 1044 } 1045 1046 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1047 1048 /* Just want the 7 least-significant bits. */ 1049 h &= 0x7f; 1050 1051 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1052 ETHER_NEXT_MULTI(step, enm); 1053 } 1054 1055 ifp->if_flags &= ~IFF_ALLMULTI; 1056 goto setit; 1057 1058 allmulti: 1059 ifp->if_flags |= IFF_ALLMULTI; 1060 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1061 1062 setit: 1063 for (i = 0; i < 4; i++) 1064 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1065 } 1066 1067 const int bge_swapbits[] = { 1068 0, 1069 BGE_MODECTL_BYTESWAP_DATA, 1070 BGE_MODECTL_WORDSWAP_DATA, 1071 BGE_MODECTL_BYTESWAP_NONFRAME, 1072 BGE_MODECTL_WORDSWAP_NONFRAME, 1073 1074 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1075 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1076 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1077 1078 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1079 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1080 1081 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1082 1083 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1084 BGE_MODECTL_BYTESWAP_NONFRAME, 1085 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1086 BGE_MODECTL_WORDSWAP_NONFRAME, 1087 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1088 BGE_MODECTL_WORDSWAP_NONFRAME, 1089 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1090 BGE_MODECTL_WORDSWAP_NONFRAME, 1091 1092 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1093 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1094 }; 1095 1096 int bge_swapindex = 0; 1097 1098 /* 1099 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1100 * self-test results. 1101 */ 1102 int 1103 bge_chipinit(sc) 1104 struct bge_softc *sc; 1105 { 1106 u_int32_t cachesize; 1107 int i; 1108 u_int32_t dma_rw_ctl; 1109 struct pci_attach_args *pa = &(sc->bge_pa); 1110 1111 1112 /* Set endianness before we access any non-PCI registers. */ 1113 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1114 BGE_INIT); 1115 1116 /* Set power state to D0. */ 1117 bge_setpowerstate(sc, 0); 1118 1119 /* 1120 * Check the 'ROM failed' bit on the RX CPU to see if 1121 * self-tests passed. 1122 */ 1123 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1124 printf("%s: RX CPU self-diagnostics failed!\n", 1125 sc->bge_dev.dv_xname); 1126 return(ENODEV); 1127 } 1128 1129 /* Clear the MAC control register */ 1130 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1131 1132 /* 1133 * Clear the MAC statistics block in the NIC's 1134 * internal memory. 1135 */ 1136 for (i = BGE_STATS_BLOCK; 1137 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1138 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1139 1140 for (i = BGE_STATUS_BLOCK; 1141 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1142 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1143 1144 /* Set up the PCI DMA control register. */ 1145 if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1146 BGE_PCISTATE_PCI_BUSMODE) { 1147 /* Conventional PCI bus */ 1148 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1149 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1150 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1151 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1152 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1153 dma_rw_ctl |= 0x0F; 1154 } 1155 } else { 1156 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1157 /* PCI-X bus */ 1158 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1159 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1160 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1161 (0x0F); 1162 /* 1163 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1164 * for hardware bugs, which means we should also clear 1165 * the low-order MINDMA bits. In addition, the 5704 1166 * uses a different encoding of read/write watermarks. 1167 */ 1168 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1169 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1170 /* should be 0x1f0000 */ 1171 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1172 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1173 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1174 } 1175 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1176 dma_rw_ctl &= 0xfffffff0; 1177 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1178 } 1179 } 1180 1181 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1182 1183 /* 1184 * Set up general mode register. 1185 */ 1186 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1187 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1188 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1189 1190 /* Get cache line size. */ 1191 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1192 1193 /* 1194 * Avoid violating PCI spec on certain chip revs. 1195 */ 1196 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1197 PCIM_CMD_MWIEN) { 1198 switch(cachesize) { 1199 case 1: 1200 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1201 BGE_PCI_WRITE_BNDRY_16BYTES); 1202 break; 1203 case 2: 1204 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1205 BGE_PCI_WRITE_BNDRY_32BYTES); 1206 break; 1207 case 4: 1208 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1209 BGE_PCI_WRITE_BNDRY_64BYTES); 1210 break; 1211 case 8: 1212 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1213 BGE_PCI_WRITE_BNDRY_128BYTES); 1214 break; 1215 case 16: 1216 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1217 BGE_PCI_WRITE_BNDRY_256BYTES); 1218 break; 1219 case 32: 1220 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1221 BGE_PCI_WRITE_BNDRY_512BYTES); 1222 break; 1223 case 64: 1224 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1225 BGE_PCI_WRITE_BNDRY_1024BYTES); 1226 break; 1227 default: 1228 /* Disable PCI memory write and invalidate. */ 1229 #if 0 1230 if (bootverbose) 1231 printf("%s: cache line size %d not " 1232 "supported; disabling PCI MWI\n", 1233 sc->bge_dev.dv_xname, cachesize); 1234 #endif 1235 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1236 PCIM_CMD_MWIEN); 1237 break; 1238 } 1239 } 1240 1241 /* 1242 * Disable memory write invalidate. Apparently it is not supported 1243 * properly by these devices. 1244 */ 1245 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1246 1247 1248 #ifdef __brokenalpha__ 1249 /* 1250 * Must insure that we do not cross an 8K (bytes) boundary 1251 * for DMA reads. Our highest limit is 1K bytes. This is a 1252 * restriction on some ALPHA platforms with early revision 1253 * 21174 PCI chipsets, such as the AlphaPC 164lx 1254 */ 1255 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1256 #endif 1257 1258 /* Set the timer prescaler (always 66MHz) */ 1259 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1260 1261 return(0); 1262 } 1263 1264 int 1265 bge_blockinit(sc) 1266 struct bge_softc *sc; 1267 { 1268 volatile struct bge_rcb *rcb; 1269 bus_size_t rcb_addr; 1270 int i; 1271 struct ifnet *ifp = &sc->ethercom.ec_if; 1272 bge_hostaddr taddr; 1273 1274 /* 1275 * Initialize the memory window pointer register so that 1276 * we can access the first 32K of internal NIC RAM. This will 1277 * allow us to set up the TX send ring RCBs and the RX return 1278 * ring RCBs, plus other things which live in NIC memory. 1279 */ 1280 1281 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1282 BGE_PCI_MEMWIN_BASEADDR, 0); 1283 1284 /* Configure mbuf memory pool */ 1285 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1286 if (sc->bge_extram) { 1287 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1288 BGE_EXT_SSRAM); 1289 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1290 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1291 else 1292 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1293 } else { 1294 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1295 BGE_BUFFPOOL_1); 1296 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1297 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1298 else 1299 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1300 } 1301 1302 /* Configure DMA resource pool */ 1303 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1304 BGE_DMA_DESCRIPTORS); 1305 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1306 } 1307 1308 /* Configure mbuf pool watermarks */ 1309 #ifdef ORIG_WPAUL_VALUES 1310 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1311 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1312 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1313 #else 1314 /* new broadcom docs strongly recommend these: */ 1315 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1316 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1317 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1318 } else { 1319 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1320 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1321 } 1322 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1323 #endif 1324 1325 /* Configure DMA resource watermarks */ 1326 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1327 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1328 1329 /* Enable buffer manager */ 1330 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1331 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1332 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1333 1334 /* Poll for buffer manager start indication */ 1335 for (i = 0; i < BGE_TIMEOUT; i++) { 1336 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1337 break; 1338 DELAY(10); 1339 } 1340 1341 if (i == BGE_TIMEOUT) { 1342 printf("%s: buffer manager failed to start\n", 1343 sc->bge_dev.dv_xname); 1344 return(ENXIO); 1345 } 1346 } 1347 1348 /* Enable flow-through queues */ 1349 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1350 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1351 1352 /* Wait until queue initialization is complete */ 1353 for (i = 0; i < BGE_TIMEOUT; i++) { 1354 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1355 break; 1356 DELAY(10); 1357 } 1358 1359 if (i == BGE_TIMEOUT) { 1360 printf("%s: flow-through queue init failed\n", 1361 sc->bge_dev.dv_xname); 1362 return(ENXIO); 1363 } 1364 1365 /* Initialize the standard RX ring control block */ 1366 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1367 bge_set_hostaddr(&rcb->bge_hostaddr, 1368 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1369 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1370 rcb->bge_maxlen_flags = 1371 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1372 } else { 1373 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1374 } 1375 if (sc->bge_extram) 1376 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1377 else 1378 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1379 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1380 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1381 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1382 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1383 1384 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1385 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1386 } else { 1387 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1388 } 1389 1390 /* 1391 * Initialize the jumbo RX ring control block 1392 * We set the 'ring disabled' bit in the flags 1393 * field until we're actually ready to start 1394 * using this ring (i.e. once we set the MTU 1395 * high enough to require it). 1396 */ 1397 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1398 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1399 bge_set_hostaddr(&rcb->bge_hostaddr, 1400 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1401 rcb->bge_maxlen_flags = 1402 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1403 BGE_RCB_FLAG_RING_DISABLED); 1404 if (sc->bge_extram) 1405 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1406 else 1407 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1408 1409 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1410 rcb->bge_hostaddr.bge_addr_hi); 1411 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1412 rcb->bge_hostaddr.bge_addr_lo); 1413 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1414 rcb->bge_maxlen_flags); 1415 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1416 1417 /* Set up dummy disabled mini ring RCB */ 1418 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1419 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1420 BGE_RCB_FLAG_RING_DISABLED); 1421 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1422 rcb->bge_maxlen_flags); 1423 1424 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1425 offsetof(struct bge_ring_data, bge_info), 1426 sizeof (struct bge_gib), 1427 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1428 } 1429 1430 /* 1431 * Set the BD ring replentish thresholds. The recommended 1432 * values are 1/8th the number of descriptors allocated to 1433 * each ring. 1434 */ 1435 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1436 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1437 1438 /* 1439 * Disable all unused send rings by setting the 'ring disabled' 1440 * bit in the flags field of all the TX send ring control blocks. 1441 * These are located in NIC memory. 1442 */ 1443 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1444 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1445 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1446 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1447 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1448 rcb_addr += sizeof(struct bge_rcb); 1449 } 1450 1451 /* Configure TX RCB 0 (we use only the first ring) */ 1452 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1453 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1454 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1455 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1456 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1457 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1458 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1459 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1460 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1461 } 1462 1463 /* Disable all unused RX return rings */ 1464 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1465 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1466 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1467 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1468 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1469 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1470 BGE_RCB_FLAG_RING_DISABLED)); 1471 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1472 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1473 (i * (sizeof(u_int64_t))), 0); 1474 rcb_addr += sizeof(struct bge_rcb); 1475 } 1476 1477 /* Initialize RX ring indexes */ 1478 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1479 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1480 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1481 1482 /* 1483 * Set up RX return ring 0 1484 * Note that the NIC address for RX return rings is 0x00000000. 1485 * The return rings live entirely within the host, so the 1486 * nicaddr field in the RCB isn't used. 1487 */ 1488 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1489 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1490 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1491 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1492 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1493 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1494 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1495 1496 /* Set random backoff seed for TX */ 1497 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1498 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1499 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1500 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1501 BGE_TX_BACKOFF_SEED_MASK); 1502 1503 /* Set inter-packet gap */ 1504 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1505 1506 /* 1507 * Specify which ring to use for packets that don't match 1508 * any RX rules. 1509 */ 1510 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1511 1512 /* 1513 * Configure number of RX lists. One interrupt distribution 1514 * list, sixteen active lists, one bad frames class. 1515 */ 1516 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1517 1518 /* Inialize RX list placement stats mask. */ 1519 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1520 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1521 1522 /* Disable host coalescing until we get it set up */ 1523 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1524 1525 /* Poll to make sure it's shut down. */ 1526 for (i = 0; i < BGE_TIMEOUT; i++) { 1527 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1528 break; 1529 DELAY(10); 1530 } 1531 1532 if (i == BGE_TIMEOUT) { 1533 printf("%s: host coalescing engine failed to idle\n", 1534 sc->bge_dev.dv_xname); 1535 return(ENXIO); 1536 } 1537 1538 /* Set up host coalescing defaults */ 1539 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1540 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1541 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1542 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1543 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1544 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1545 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1546 } 1547 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1548 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1549 1550 /* Set up address of statistics block */ 1551 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1552 bge_set_hostaddr(&taddr, 1553 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1554 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1555 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1556 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1557 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1558 } 1559 1560 /* Set up address of status block */ 1561 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1562 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1563 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1564 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1565 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1566 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1567 1568 /* Turn on host coalescing state machine */ 1569 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1570 1571 /* Turn on RX BD completion state machine and enable attentions */ 1572 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1573 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1574 1575 /* Turn on RX list placement state machine */ 1576 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1577 1578 /* Turn on RX list selector state machine. */ 1579 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1580 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1581 } 1582 1583 /* Turn on DMA, clear stats */ 1584 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1585 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1586 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1587 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1588 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1589 1590 /* Set misc. local control, enable interrupts on attentions */ 1591 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1592 1593 #ifdef notdef 1594 /* Assert GPIO pins for PHY reset */ 1595 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1596 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1597 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1598 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1599 #endif 1600 1601 #if defined(not_quite_yet) 1602 /* Linux driver enables enable gpio pin #1 on 5700s */ 1603 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1604 sc->bge_local_ctrl_reg |= 1605 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1606 } 1607 #endif 1608 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1609 1610 /* Turn on DMA completion state machine */ 1611 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1612 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1613 } 1614 1615 /* Turn on write DMA state machine */ 1616 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1617 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1618 1619 /* Turn on read DMA state machine */ 1620 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1621 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1622 1623 /* Turn on RX data completion state machine */ 1624 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1625 1626 /* Turn on RX BD initiator state machine */ 1627 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1628 1629 /* Turn on RX data and RX BD initiator state machine */ 1630 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1631 1632 /* Turn on Mbuf cluster free state machine */ 1633 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1634 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1635 } 1636 1637 /* Turn on send BD completion state machine */ 1638 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1639 1640 /* Turn on send data completion state machine */ 1641 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1642 1643 /* Turn on send data initiator state machine */ 1644 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1645 1646 /* Turn on send BD initiator state machine */ 1647 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1648 1649 /* Turn on send BD selector state machine */ 1650 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1651 1652 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1653 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1654 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1655 1656 /* ack/clear link change events */ 1657 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1658 BGE_MACSTAT_CFG_CHANGED); 1659 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1660 1661 /* Enable PHY auto polling (for MII/GMII only) */ 1662 if (sc->bge_tbi) { 1663 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1664 } else { 1665 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1666 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1667 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1668 BGE_EVTENB_MI_INTERRUPT); 1669 } 1670 1671 /* Enable link state change attentions. */ 1672 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1673 1674 return(0); 1675 } 1676 1677 static const struct bge_revision { 1678 uint32_t br_chipid; 1679 uint32_t br_quirks; 1680 const char *br_name; 1681 } bge_revisions[] = { 1682 { BGE_CHIPID_BCM5700_A0, 1683 BGE_QUIRK_LINK_STATE_BROKEN, 1684 "BCM5700 A0" }, 1685 1686 { BGE_CHIPID_BCM5700_A1, 1687 BGE_QUIRK_LINK_STATE_BROKEN, 1688 "BCM5700 A1" }, 1689 1690 { BGE_CHIPID_BCM5700_B0, 1691 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1692 "BCM5700 B0" }, 1693 1694 { BGE_CHIPID_BCM5700_B1, 1695 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1696 "BCM5700 B1" }, 1697 1698 { BGE_CHIPID_BCM5700_B2, 1699 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1700 "BCM5700 B2" }, 1701 1702 /* This is treated like a BCM5700 Bx */ 1703 { BGE_CHIPID_BCM5700_ALTIMA, 1704 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1705 "BCM5700 Altima" }, 1706 1707 { BGE_CHIPID_BCM5700_C0, 1708 0, 1709 "BCM5700 C0" }, 1710 1711 { BGE_CHIPID_BCM5701_A0, 1712 0, /*XXX really, just not known */ 1713 "BCM5701 A0" }, 1714 1715 { BGE_CHIPID_BCM5701_B0, 1716 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1717 "BCM5701 B0" }, 1718 1719 { BGE_CHIPID_BCM5701_B2, 1720 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1721 "BCM5701 B2" }, 1722 1723 { BGE_CHIPID_BCM5701_B5, 1724 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1725 "BCM5701 B5" }, 1726 1727 { BGE_CHIPID_BCM5703_A0, 1728 0, 1729 "BCM5703 A0" }, 1730 1731 { BGE_CHIPID_BCM5703_A1, 1732 0, 1733 "BCM5703 A1" }, 1734 1735 { BGE_CHIPID_BCM5703_A2, 1736 BGE_QUIRK_ONLY_PHY_1, 1737 "BCM5703 A2" }, 1738 1739 { BGE_CHIPID_BCM5703_A3, 1740 BGE_QUIRK_ONLY_PHY_1, 1741 "BCM5703 A3" }, 1742 1743 { BGE_CHIPID_BCM5704_A0, 1744 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1745 "BCM5704 A0" }, 1746 1747 { BGE_CHIPID_BCM5704_A1, 1748 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1749 "BCM5704 A1" }, 1750 1751 { BGE_CHIPID_BCM5704_A2, 1752 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1753 "BCM5704 A2" }, 1754 1755 { BGE_CHIPID_BCM5704_A3, 1756 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1757 "BCM5704 A3" }, 1758 1759 { BGE_CHIPID_BCM5705_A0, 1760 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1761 "BCM5705 A0" }, 1762 1763 { BGE_CHIPID_BCM5705_A1, 1764 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1765 "BCM5705 A1" }, 1766 1767 { BGE_CHIPID_BCM5705_A2, 1768 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1769 "BCM5705 A2" }, 1770 1771 { BGE_CHIPID_BCM5705_A3, 1772 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1773 "BCM5705 A3" }, 1774 1775 { 0, 0, NULL } 1776 }; 1777 1778 /* 1779 * Some defaults for major revisions, so that newer steppings 1780 * that we don't know about have a shot at working. 1781 */ 1782 static const struct bge_revision bge_majorrevs[] = { 1783 { BGE_ASICREV_BCM5700, 1784 BGE_QUIRK_LINK_STATE_BROKEN, 1785 "unknown BCM5700" }, 1786 1787 { BGE_ASICREV_BCM5701, 1788 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1789 "unknown BCM5701" }, 1790 1791 { BGE_ASICREV_BCM5703, 1792 0, 1793 "unknown BCM5703" }, 1794 1795 { BGE_ASICREV_BCM5704, 1796 BGE_QUIRK_ONLY_PHY_1, 1797 "unknown BCM5704" }, 1798 1799 { BGE_ASICREV_BCM5705, 1800 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1801 "unknown BCM5705" }, 1802 1803 { 0, 1804 0, 1805 NULL } 1806 }; 1807 1808 1809 static const struct bge_revision * 1810 bge_lookup_rev(uint32_t chipid) 1811 { 1812 const struct bge_revision *br; 1813 1814 for (br = bge_revisions; br->br_name != NULL; br++) { 1815 if (br->br_chipid == chipid) 1816 return (br); 1817 } 1818 1819 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1820 if (br->br_chipid == BGE_ASICREV(chipid)) 1821 return (br); 1822 } 1823 1824 return (NULL); 1825 } 1826 1827 static const struct bge_product { 1828 pci_vendor_id_t bp_vendor; 1829 pci_product_id_t bp_product; 1830 const char *bp_name; 1831 } bge_products[] = { 1832 /* 1833 * The BCM5700 documentation seems to indicate that the hardware 1834 * still has the Alteon vendor ID burned into it, though it 1835 * should always be overridden by the value in the EEPROM. We'll 1836 * check for it anyway. 1837 */ 1838 { PCI_VENDOR_ALTEON, 1839 PCI_PRODUCT_ALTEON_BCM5700, 1840 "Broadcom BCM5700 Gigabit Ethernet", 1841 }, 1842 { PCI_VENDOR_ALTEON, 1843 PCI_PRODUCT_ALTEON_BCM5701, 1844 "Broadcom BCM5701 Gigabit Ethernet", 1845 }, 1846 1847 { PCI_VENDOR_ALTIMA, 1848 PCI_PRODUCT_ALTIMA_AC1000, 1849 "Altima AC1000 Gigabit Ethernet", 1850 }, 1851 { PCI_VENDOR_ALTIMA, 1852 PCI_PRODUCT_ALTIMA_AC1001, 1853 "Altima AC1001 Gigabit Ethernet", 1854 }, 1855 { PCI_VENDOR_ALTIMA, 1856 PCI_PRODUCT_ALTIMA_AC9100, 1857 "Altima AC9100 Gigabit Ethernet", 1858 }, 1859 1860 { PCI_VENDOR_BROADCOM, 1861 PCI_PRODUCT_BROADCOM_BCM5700, 1862 "Broadcom BCM5700 Gigabit Ethernet", 1863 }, 1864 { PCI_VENDOR_BROADCOM, 1865 PCI_PRODUCT_BROADCOM_BCM5701, 1866 "Broadcom BCM5701 Gigabit Ethernet", 1867 }, 1868 { PCI_VENDOR_BROADCOM, 1869 PCI_PRODUCT_BROADCOM_BCM5702, 1870 "Broadcom BCM5702 Gigabit Ethernet", 1871 }, 1872 { PCI_VENDOR_BROADCOM, 1873 PCI_PRODUCT_BROADCOM_BCM5702X, 1874 "Broadcom BCM5702X Gigabit Ethernet" }, 1875 1876 { PCI_VENDOR_BROADCOM, 1877 PCI_PRODUCT_BROADCOM_BCM5703, 1878 "Broadcom BCM5703 Gigabit Ethernet", 1879 }, 1880 { PCI_VENDOR_BROADCOM, 1881 PCI_PRODUCT_BROADCOM_BCM5703X, 1882 "Broadcom BCM5703X Gigabit Ethernet", 1883 }, 1884 { PCI_VENDOR_BROADCOM, 1885 PCI_PRODUCT_BROADCOM_BCM5703A3, 1886 "Broadcom BCM5703A3 Gigabit Ethernet", 1887 }, 1888 1889 { PCI_VENDOR_BROADCOM, 1890 PCI_PRODUCT_BROADCOM_BCM5704C, 1891 "Broadcom BCM5704C Dual Gigabit Ethernet", 1892 }, 1893 { PCI_VENDOR_BROADCOM, 1894 PCI_PRODUCT_BROADCOM_BCM5704S, 1895 "Broadcom BCM5704S Dual Gigabit Ethernet", 1896 }, 1897 1898 { PCI_VENDOR_BROADCOM, 1899 PCI_PRODUCT_BROADCOM_BCM5705, 1900 "Broadcom BCM5705 Gigabit Ethernet", 1901 }, 1902 { PCI_VENDOR_BROADCOM, 1903 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 1904 "Broadcom BCM5705 Gigabit Ethernet", 1905 }, 1906 { PCI_VENDOR_BROADCOM, 1907 PCI_PRODUCT_BROADCOM_BCM5705M, 1908 "Broadcom BCM5705M Gigabit Ethernet", 1909 }, 1910 1911 { PCI_VENDOR_BROADCOM, 1912 PCI_PRODUCT_BROADCOM_BCM5901, 1913 "Broadcom BCM5901 Fast Ethernet", 1914 }, 1915 { PCI_VENDOR_BROADCOM, 1916 PCI_PRODUCT_BROADCOM_BCM5901A2, 1917 "Broadcom BCM5901A2 Fast Ethernet", 1918 }, 1919 1920 { PCI_VENDOR_BROADCOM, 1921 PCI_PRODUCT_BROADCOM_BCM5782, 1922 "Broadcom BCM5782 Gigabit Ethernet", 1923 }, 1924 1925 { PCI_VENDOR_SCHNEIDERKOCH, 1926 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1927 "SysKonnect SK-9Dx1 Gigabit Ethernet", 1928 }, 1929 1930 { PCI_VENDOR_3COM, 1931 PCI_PRODUCT_3COM_3C996, 1932 "3Com 3c996 Gigabit Ethernet", 1933 }, 1934 1935 { 0, 1936 0, 1937 NULL }, 1938 }; 1939 1940 static const struct bge_product * 1941 bge_lookup(const struct pci_attach_args *pa) 1942 { 1943 const struct bge_product *bp; 1944 1945 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1946 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1947 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1948 return (bp); 1949 } 1950 1951 return (NULL); 1952 } 1953 1954 int 1955 bge_setpowerstate(sc, powerlevel) 1956 struct bge_softc *sc; 1957 int powerlevel; 1958 { 1959 #ifdef NOTYET 1960 u_int32_t pm_ctl = 0; 1961 1962 /* XXX FIXME: make sure indirect accesses enabled? */ 1963 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 1964 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 1965 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 1966 1967 /* clear the PME_assert bit and power state bits, enable PME */ 1968 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 1969 pm_ctl &= ~PCIM_PSTAT_DMASK; 1970 pm_ctl |= (1 << 8); 1971 1972 if (powerlevel == 0) { 1973 pm_ctl |= PCIM_PSTAT_D0; 1974 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 1975 pm_ctl, 2); 1976 DELAY(10000); 1977 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1978 DELAY(10000); 1979 1980 #ifdef NOTYET 1981 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 1982 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 1983 #endif 1984 DELAY(40); DELAY(40); DELAY(40); 1985 DELAY(10000); /* above not quite adequate on 5700 */ 1986 return 0; 1987 } 1988 1989 1990 /* 1991 * Entering ACPI power states D1-D3 is achieved by wiggling 1992 * GMII gpio pins. Example code assumes all hardware vendors 1993 * followed Broadom's sample pcb layout. Until we verify that 1994 * for all supported OEM cards, states D1-D3 are unsupported. 1995 */ 1996 printf("%s: power state %d unimplemented; check GPIO pins\n", 1997 sc->bge_dev.dv_xname, powerlevel); 1998 #endif 1999 return EOPNOTSUPP; 2000 } 2001 2002 2003 /* 2004 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2005 * against our list and return its name if we find a match. Note 2006 * that since the Broadcom controller contains VPD support, we 2007 * can get the device name string from the controller itself instead 2008 * of the compiled-in string. This is a little slow, but it guarantees 2009 * we'll always announce the right product name. 2010 */ 2011 int 2012 bge_probe(parent, match, aux) 2013 struct device *parent; 2014 struct cfdata *match; 2015 void *aux; 2016 { 2017 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2018 2019 if (bge_lookup(pa) != NULL) 2020 return (1); 2021 2022 return (0); 2023 } 2024 2025 void 2026 bge_attach(parent, self, aux) 2027 struct device *parent, *self; 2028 void *aux; 2029 { 2030 struct bge_softc *sc = (struct bge_softc *)self; 2031 struct pci_attach_args *pa = aux; 2032 const struct bge_product *bp; 2033 const struct bge_revision *br; 2034 pci_chipset_tag_t pc = pa->pa_pc; 2035 pci_intr_handle_t ih; 2036 const char *intrstr = NULL; 2037 bus_dma_segment_t seg; 2038 int rseg; 2039 u_int32_t hwcfg = 0; 2040 u_int32_t mac_addr = 0; 2041 u_int32_t command; 2042 struct ifnet *ifp; 2043 caddr_t kva; 2044 u_char eaddr[ETHER_ADDR_LEN]; 2045 pcireg_t memtype; 2046 bus_addr_t memaddr; 2047 bus_size_t memsize; 2048 u_int32_t pm_ctl; 2049 2050 bp = bge_lookup(pa); 2051 KASSERT(bp != NULL); 2052 2053 sc->bge_pa = *pa; 2054 2055 aprint_naive(": Ethernet controller\n"); 2056 aprint_normal(": %s\n", bp->bp_name); 2057 2058 /* 2059 * Map control/status registers. 2060 */ 2061 DPRINTFN(5, ("Map control/status regs\n")); 2062 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2063 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2064 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2065 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2066 2067 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2068 aprint_error("%s: failed to enable memory mapping!\n", 2069 sc->bge_dev.dv_xname); 2070 return; 2071 } 2072 2073 DPRINTFN(5, ("pci_mem_find\n")); 2074 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2075 switch (memtype) { 2076 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2077 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2078 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2079 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2080 &memaddr, &memsize) == 0) 2081 break; 2082 default: 2083 aprint_error("%s: can't find mem space\n", 2084 sc->bge_dev.dv_xname); 2085 return; 2086 } 2087 2088 DPRINTFN(5, ("pci_intr_map\n")); 2089 if (pci_intr_map(pa, &ih)) { 2090 aprint_error("%s: couldn't map interrupt\n", 2091 sc->bge_dev.dv_xname); 2092 return; 2093 } 2094 2095 DPRINTFN(5, ("pci_intr_string\n")); 2096 intrstr = pci_intr_string(pc, ih); 2097 2098 DPRINTFN(5, ("pci_intr_establish\n")); 2099 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2100 2101 if (sc->bge_intrhand == NULL) { 2102 aprint_error("%s: couldn't establish interrupt", 2103 sc->bge_dev.dv_xname); 2104 if (intrstr != NULL) 2105 aprint_normal(" at %s", intrstr); 2106 aprint_normal("\n"); 2107 return; 2108 } 2109 aprint_normal("%s: interrupting at %s\n", 2110 sc->bge_dev.dv_xname, intrstr); 2111 2112 /* 2113 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2114 * can clobber the chip's PCI config-space power control registers, 2115 * leaving the card in D3 powersave state. 2116 * We do not have memory-mapped registers in this state, 2117 * so force device into D0 state before starting initialization. 2118 */ 2119 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2120 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2121 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2122 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2123 DELAY(1000); /* 27 usec is allegedly sufficent */ 2124 2125 /* Try to reset the chip. */ 2126 DPRINTFN(5, ("bge_reset\n")); 2127 bge_reset(sc); 2128 2129 if (bge_chipinit(sc)) { 2130 aprint_error("%s: chip initialization failed\n", 2131 sc->bge_dev.dv_xname); 2132 bge_release_resources(sc); 2133 return; 2134 } 2135 2136 /* 2137 * Get station address from the EEPROM. 2138 */ 2139 mac_addr = bge_readmem_ind(sc, 0x0c14); 2140 if ((mac_addr >> 16) == 0x484b) { 2141 eaddr[0] = (u_char)(mac_addr >> 8); 2142 eaddr[1] = (u_char)(mac_addr >> 0); 2143 mac_addr = bge_readmem_ind(sc, 0x0c18); 2144 eaddr[2] = (u_char)(mac_addr >> 24); 2145 eaddr[3] = (u_char)(mac_addr >> 16); 2146 eaddr[4] = (u_char)(mac_addr >> 8); 2147 eaddr[5] = (u_char)(mac_addr >> 0); 2148 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2149 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2150 aprint_error("%s: failed to read station address\n", 2151 sc->bge_dev.dv_xname); 2152 bge_release_resources(sc); 2153 return; 2154 } 2155 2156 /* 2157 * Save ASIC rev. Look up any quirks associated with this 2158 * ASIC. 2159 */ 2160 sc->bge_chipid = 2161 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2162 BGE_PCIMISCCTL_ASICREV; 2163 br = bge_lookup_rev(sc->bge_chipid); 2164 2165 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2166 2167 if (br == NULL) { 2168 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2169 sc->bge_quirks = 0; 2170 } else { 2171 aprint_normal("ASIC %s (0x%04x)", 2172 br->br_name, sc->bge_chipid >> 16); 2173 sc->bge_quirks |= br->br_quirks; 2174 } 2175 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2176 2177 /* Allocate the general information block and ring buffers. */ 2178 if (pci_dma64_available(pa)) 2179 sc->bge_dmatag = pa->pa_dmat64; 2180 else 2181 sc->bge_dmatag = pa->pa_dmat; 2182 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2183 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2184 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2185 aprint_error("%s: can't alloc rx buffers\n", 2186 sc->bge_dev.dv_xname); 2187 return; 2188 } 2189 DPRINTFN(5, ("bus_dmamem_map\n")); 2190 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2191 sizeof(struct bge_ring_data), &kva, 2192 BUS_DMA_NOWAIT)) { 2193 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2194 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2195 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2196 return; 2197 } 2198 DPRINTFN(5, ("bus_dmamem_create\n")); 2199 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2200 sizeof(struct bge_ring_data), 0, 2201 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2202 aprint_error("%s: can't create DMA map\n", 2203 sc->bge_dev.dv_xname); 2204 bus_dmamem_unmap(sc->bge_dmatag, kva, 2205 sizeof(struct bge_ring_data)); 2206 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2207 return; 2208 } 2209 DPRINTFN(5, ("bus_dmamem_load\n")); 2210 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2211 sizeof(struct bge_ring_data), NULL, 2212 BUS_DMA_NOWAIT)) { 2213 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2214 bus_dmamem_unmap(sc->bge_dmatag, kva, 2215 sizeof(struct bge_ring_data)); 2216 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2217 return; 2218 } 2219 2220 DPRINTFN(5, ("bzero\n")); 2221 sc->bge_rdata = (struct bge_ring_data *)kva; 2222 2223 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2224 2225 /* Try to allocate memory for jumbo buffers. */ 2226 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2227 if (bge_alloc_jumbo_mem(sc)) { 2228 aprint_error("%s: jumbo buffer allocation failed\n", 2229 sc->bge_dev.dv_xname); 2230 } else 2231 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2232 } 2233 2234 /* Set default tuneable values. */ 2235 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2236 sc->bge_rx_coal_ticks = 150; 2237 sc->bge_rx_max_coal_bds = 64; 2238 #ifdef ORIG_WPAUL_VALUES 2239 sc->bge_tx_coal_ticks = 150; 2240 sc->bge_tx_max_coal_bds = 128; 2241 #else 2242 sc->bge_tx_coal_ticks = 300; 2243 sc->bge_tx_max_coal_bds = 400; 2244 #endif 2245 2246 /* Set up ifnet structure */ 2247 ifp = &sc->ethercom.ec_if; 2248 ifp->if_softc = sc; 2249 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2250 ifp->if_ioctl = bge_ioctl; 2251 ifp->if_start = bge_start; 2252 ifp->if_init = bge_init; 2253 ifp->if_watchdog = bge_watchdog; 2254 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2255 IFQ_SET_READY(&ifp->if_snd); 2256 DPRINTFN(5, ("bcopy\n")); 2257 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2258 2259 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2260 sc->ethercom.ec_if.if_capabilities |= 2261 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 2262 sc->ethercom.ec_capabilities |= 2263 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2264 2265 /* 2266 * Do MII setup. 2267 */ 2268 DPRINTFN(5, ("mii setup\n")); 2269 sc->bge_mii.mii_ifp = ifp; 2270 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2271 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2272 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2273 2274 /* 2275 * Figure out what sort of media we have by checking the 2276 * hardware config word in the first 32k of NIC internal memory, 2277 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2278 * cards, this value appears to be unset. If that's the 2279 * case, we have to rely on identifying the NIC by its PCI 2280 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2281 */ 2282 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2283 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2284 } else { 2285 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2286 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2287 hwcfg = be32toh(hwcfg); 2288 } 2289 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2290 sc->bge_tbi = 1; 2291 2292 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2293 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2294 SK_SUBSYSID_9D41) 2295 sc->bge_tbi = 1; 2296 2297 if (sc->bge_tbi) { 2298 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2299 bge_ifmedia_sts); 2300 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2301 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2302 0, NULL); 2303 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2304 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2305 } else { 2306 /* 2307 * Do transceiver setup. 2308 */ 2309 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2310 bge_ifmedia_sts); 2311 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2312 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 2313 2314 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2315 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2316 ifmedia_add(&sc->bge_mii.mii_media, 2317 IFM_ETHER|IFM_MANUAL, 0, NULL); 2318 ifmedia_set(&sc->bge_mii.mii_media, 2319 IFM_ETHER|IFM_MANUAL); 2320 } else 2321 ifmedia_set(&sc->bge_mii.mii_media, 2322 IFM_ETHER|IFM_AUTO); 2323 } 2324 2325 /* 2326 * When using the BCM5701 in PCI-X mode, data corruption has 2327 * been observed in the first few bytes of some received packets. 2328 * Aligning the packet buffer in memory eliminates the corruption. 2329 * Unfortunately, this misaligns the packet payloads. On platforms 2330 * which do not support unaligned accesses, we will realign the 2331 * payloads by copying the received packets. 2332 */ 2333 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2334 /* If in PCI-X mode, work around the alignment bug. */ 2335 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2336 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2337 BGE_PCISTATE_PCI_BUSSPEED) 2338 sc->bge_rx_alignment_bug = 1; 2339 } 2340 2341 /* 2342 * Call MI attach routine. 2343 */ 2344 DPRINTFN(5, ("if_attach\n")); 2345 if_attach(ifp); 2346 DPRINTFN(5, ("ether_ifattach\n")); 2347 ether_ifattach(ifp, eaddr); 2348 DPRINTFN(5, ("callout_init\n")); 2349 callout_init(&sc->bge_timeout); 2350 } 2351 2352 void 2353 bge_release_resources(sc) 2354 struct bge_softc *sc; 2355 { 2356 if (sc->bge_vpd_prodname != NULL) 2357 free(sc->bge_vpd_prodname, M_DEVBUF); 2358 2359 if (sc->bge_vpd_readonly != NULL) 2360 free(sc->bge_vpd_readonly, M_DEVBUF); 2361 } 2362 2363 void 2364 bge_reset(sc) 2365 struct bge_softc *sc; 2366 { 2367 struct pci_attach_args *pa = &sc->bge_pa; 2368 u_int32_t cachesize, command, pcistate; 2369 int i, val = 0; 2370 2371 /* Save some important PCI state. */ 2372 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2373 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2374 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2375 2376 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2377 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2378 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2379 2380 /* Issue global reset */ 2381 bge_writereg_ind(sc, BGE_MISC_CFG, 2382 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2383 2384 DELAY(1000); 2385 2386 /* Reset some of the PCI state that got zapped by reset */ 2387 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2388 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2389 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2390 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2391 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2392 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2393 2394 /* Enable memory arbiter. */ 2395 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2396 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2397 } 2398 2399 /* 2400 * Prevent PXE restart: write a magic number to the 2401 * general communications memory at 0xB50. 2402 */ 2403 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2404 2405 /* 2406 * Poll the value location we just wrote until 2407 * we see the 1's complement of the magic number. 2408 * This indicates that the firmware initialization 2409 * is complete. 2410 */ 2411 for (i = 0; i < 750; i++) { 2412 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2413 if (val == ~BGE_MAGIC_NUMBER) 2414 break; 2415 DELAY(1000); 2416 } 2417 2418 if (i == 750) { 2419 printf("%s: firmware handshake timed out, val = %x\n", 2420 sc->bge_dev.dv_xname, val); 2421 return; 2422 } 2423 2424 /* 2425 * XXX Wait for the value of the PCISTATE register to 2426 * return to its original pre-reset state. This is a 2427 * fairly good indicator of reset completion. If we don't 2428 * wait for the reset to fully complete, trying to read 2429 * from the device's non-PCI registers may yield garbage 2430 * results. 2431 */ 2432 for (i = 0; i < BGE_TIMEOUT; i++) { 2433 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 2434 pcistate) 2435 break; 2436 DELAY(10); 2437 } 2438 2439 /* Enable memory arbiter. */ 2440 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2441 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2442 } 2443 2444 /* Fix up byte swapping */ 2445 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2446 2447 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2448 2449 DELAY(10000); 2450 } 2451 2452 /* 2453 * Frame reception handling. This is called if there's a frame 2454 * on the receive return list. 2455 * 2456 * Note: we have to be able to handle two possibilities here: 2457 * 1) the frame is from the jumbo recieve ring 2458 * 2) the frame is from the standard receive ring 2459 */ 2460 2461 void 2462 bge_rxeof(sc) 2463 struct bge_softc *sc; 2464 { 2465 struct ifnet *ifp; 2466 int stdcnt = 0, jumbocnt = 0; 2467 int have_tag = 0; 2468 u_int16_t vlan_tag = 0; 2469 bus_dmamap_t dmamap; 2470 bus_addr_t offset, toff; 2471 bus_size_t tlen; 2472 int tosync; 2473 2474 ifp = &sc->ethercom.ec_if; 2475 2476 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2477 offsetof(struct bge_ring_data, bge_status_block), 2478 sizeof (struct bge_status_block), 2479 BUS_DMASYNC_POSTREAD); 2480 2481 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2482 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2483 sc->bge_rx_saved_considx; 2484 2485 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2486 2487 if (tosync < 0) { 2488 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2489 sizeof (struct bge_rx_bd); 2490 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2491 toff, tlen, BUS_DMASYNC_POSTREAD); 2492 tosync = -tosync; 2493 } 2494 2495 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2496 offset, tosync * sizeof (struct bge_rx_bd), 2497 BUS_DMASYNC_POSTREAD); 2498 2499 while(sc->bge_rx_saved_considx != 2500 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2501 struct bge_rx_bd *cur_rx; 2502 u_int32_t rxidx; 2503 struct mbuf *m = NULL; 2504 2505 cur_rx = &sc->bge_rdata-> 2506 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2507 2508 rxidx = cur_rx->bge_idx; 2509 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2510 2511 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2512 have_tag = 1; 2513 vlan_tag = cur_rx->bge_vlan_tag; 2514 } 2515 2516 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2517 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2518 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2519 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2520 jumbocnt++; 2521 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2522 ifp->if_ierrors++; 2523 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2524 continue; 2525 } 2526 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2527 NULL)== ENOBUFS) { 2528 ifp->if_ierrors++; 2529 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2530 continue; 2531 } 2532 } else { 2533 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2534 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2535 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2536 stdcnt++; 2537 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2538 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2539 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2540 ifp->if_ierrors++; 2541 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2542 continue; 2543 } 2544 if (bge_newbuf_std(sc, sc->bge_std, 2545 NULL, dmamap) == ENOBUFS) { 2546 ifp->if_ierrors++; 2547 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2548 continue; 2549 } 2550 } 2551 2552 ifp->if_ipackets++; 2553 #ifndef __NO_STRICT_ALIGNMENT 2554 /* 2555 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2556 * the Rx buffer has the layer-2 header unaligned. 2557 * If our CPU requires alignment, re-align by copying. 2558 */ 2559 if (sc->bge_rx_alignment_bug) { 2560 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2561 cur_rx->bge_len); 2562 m->m_data += ETHER_ALIGN; 2563 } 2564 #endif 2565 2566 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2567 m->m_pkthdr.rcvif = ifp; 2568 2569 #if NBPFILTER > 0 2570 /* 2571 * Handle BPF listeners. Let the BPF user see the packet. 2572 */ 2573 if (ifp->if_bpf) 2574 bpf_mtap(ifp->if_bpf, m); 2575 #endif 2576 2577 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2578 2579 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2580 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2581 /* 2582 * Rx transport checksum-offload may also 2583 * have bugs with packets which, when transmitted, 2584 * were `runts' requiring padding. 2585 */ 2586 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2587 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2588 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2589 m->m_pkthdr.csum_data = 2590 cur_rx->bge_tcp_udp_csum; 2591 m->m_pkthdr.csum_flags |= 2592 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2593 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2594 } 2595 2596 /* 2597 * If we received a packet with a vlan tag, pass it 2598 * to vlan_input() instead of ether_input(). 2599 */ 2600 if (have_tag) { 2601 struct m_tag *mtag; 2602 2603 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2604 M_NOWAIT); 2605 if (mtag != NULL) { 2606 *(u_int *)(mtag + 1) = vlan_tag; 2607 m_tag_prepend(m, mtag); 2608 have_tag = vlan_tag = 0; 2609 } else { 2610 printf("%s: no mbuf for tag\n", ifp->if_xname); 2611 m_freem(m); 2612 have_tag = vlan_tag = 0; 2613 continue; 2614 } 2615 } 2616 (*ifp->if_input)(ifp, m); 2617 } 2618 2619 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2620 if (stdcnt) 2621 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2622 if (jumbocnt) 2623 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2624 } 2625 2626 void 2627 bge_txeof(sc) 2628 struct bge_softc *sc; 2629 { 2630 struct bge_tx_bd *cur_tx = NULL; 2631 struct ifnet *ifp; 2632 struct txdmamap_pool_entry *dma; 2633 bus_addr_t offset, toff; 2634 bus_size_t tlen; 2635 int tosync; 2636 struct mbuf *m; 2637 2638 ifp = &sc->ethercom.ec_if; 2639 2640 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2641 offsetof(struct bge_ring_data, bge_status_block), 2642 sizeof (struct bge_status_block), 2643 BUS_DMASYNC_POSTREAD); 2644 2645 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2646 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2647 sc->bge_tx_saved_considx; 2648 2649 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2650 2651 if (tosync < 0) { 2652 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2653 sizeof (struct bge_tx_bd); 2654 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2655 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2656 tosync = -tosync; 2657 } 2658 2659 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2660 offset, tosync * sizeof (struct bge_tx_bd), 2661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2662 2663 /* 2664 * Go through our tx ring and free mbufs for those 2665 * frames that have been sent. 2666 */ 2667 while (sc->bge_tx_saved_considx != 2668 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2669 u_int32_t idx = 0; 2670 2671 idx = sc->bge_tx_saved_considx; 2672 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2673 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2674 ifp->if_opackets++; 2675 m = sc->bge_cdata.bge_tx_chain[idx]; 2676 if (m != NULL) { 2677 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2678 dma = sc->txdma[idx]; 2679 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2680 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2681 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2682 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2683 sc->txdma[idx] = NULL; 2684 2685 m_freem(m); 2686 } 2687 sc->bge_txcnt--; 2688 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2689 ifp->if_timer = 0; 2690 } 2691 2692 if (cur_tx != NULL) 2693 ifp->if_flags &= ~IFF_OACTIVE; 2694 } 2695 2696 int 2697 bge_intr(xsc) 2698 void *xsc; 2699 { 2700 struct bge_softc *sc; 2701 struct ifnet *ifp; 2702 2703 sc = xsc; 2704 ifp = &sc->ethercom.ec_if; 2705 2706 #ifdef notdef 2707 /* Avoid this for now -- checking this register is expensive. */ 2708 /* Make sure this is really our interrupt. */ 2709 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2710 return (0); 2711 #endif 2712 /* Ack interrupt and stop others from occuring. */ 2713 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2714 2715 /* 2716 * Process link state changes. 2717 * Grrr. The link status word in the status block does 2718 * not work correctly on the BCM5700 rev AX and BX chips, 2719 * according to all avaibable information. Hence, we have 2720 * to enable MII interrupts in order to properly obtain 2721 * async link changes. Unfortunately, this also means that 2722 * we have to read the MAC status register to detect link 2723 * changes, thereby adding an additional register access to 2724 * the interrupt handler. 2725 */ 2726 2727 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2728 u_int32_t status; 2729 2730 status = CSR_READ_4(sc, BGE_MAC_STS); 2731 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2732 sc->bge_link = 0; 2733 callout_stop(&sc->bge_timeout); 2734 bge_tick(sc); 2735 /* Clear the interrupt */ 2736 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2737 BGE_EVTENB_MI_INTERRUPT); 2738 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2739 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2740 BRGPHY_INTRS); 2741 } 2742 } else { 2743 if (sc->bge_rdata->bge_status_block.bge_status & 2744 BGE_STATFLAG_LINKSTATE_CHANGED) { 2745 sc->bge_link = 0; 2746 callout_stop(&sc->bge_timeout); 2747 bge_tick(sc); 2748 /* Clear the interrupt */ 2749 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2750 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2751 BGE_MACSTAT_LINK_CHANGED); 2752 } 2753 } 2754 2755 if (ifp->if_flags & IFF_RUNNING) { 2756 /* Check RX return ring producer/consumer */ 2757 bge_rxeof(sc); 2758 2759 /* Check TX ring producer/consumer */ 2760 bge_txeof(sc); 2761 } 2762 2763 if (sc->bge_pending_rxintr_change) { 2764 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 2765 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 2766 uint32_t junk; 2767 2768 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 2769 DELAY(10); 2770 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 2771 2772 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 2773 DELAY(10); 2774 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 2775 2776 sc->bge_pending_rxintr_change = 0; 2777 } 2778 bge_handle_events(sc); 2779 2780 /* Re-enable interrupts. */ 2781 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2782 2783 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2784 bge_start(ifp); 2785 2786 return (1); 2787 } 2788 2789 void 2790 bge_tick(xsc) 2791 void *xsc; 2792 { 2793 struct bge_softc *sc = xsc; 2794 struct mii_data *mii = &sc->bge_mii; 2795 struct ifmedia *ifm = NULL; 2796 struct ifnet *ifp = &sc->ethercom.ec_if; 2797 int s; 2798 2799 s = splnet(); 2800 2801 bge_stats_update(sc); 2802 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2803 if (sc->bge_link) { 2804 splx(s); 2805 return; 2806 } 2807 2808 if (sc->bge_tbi) { 2809 ifm = &sc->bge_ifmedia; 2810 if (CSR_READ_4(sc, BGE_MAC_STS) & 2811 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2812 sc->bge_link++; 2813 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2814 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2815 bge_start(ifp); 2816 } 2817 splx(s); 2818 return; 2819 } 2820 2821 mii_tick(mii); 2822 2823 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2824 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2825 sc->bge_link++; 2826 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2827 bge_start(ifp); 2828 } 2829 2830 splx(s); 2831 } 2832 2833 void 2834 bge_stats_update(sc) 2835 struct bge_softc *sc; 2836 { 2837 struct ifnet *ifp = &sc->ethercom.ec_if; 2838 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2839 bus_size_t rstats = BGE_RX_STATS; 2840 2841 #define READ_RSTAT(sc, stats, stat) \ 2842 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 2843 2844 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2845 ifp->if_collisions += 2846 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 2847 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 2848 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 2849 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 2850 return; 2851 } 2852 2853 #undef READ_RSTAT 2854 #define READ_STAT(sc, stats, stat) \ 2855 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2856 2857 ifp->if_collisions += 2858 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2859 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2860 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2861 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2862 ifp->if_collisions; 2863 2864 #undef READ_STAT 2865 2866 #ifdef notdef 2867 ifp->if_collisions += 2868 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2869 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2870 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2871 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2872 ifp->if_collisions; 2873 #endif 2874 } 2875 2876 /* 2877 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2878 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2879 * but when such padded frames employ the bge IP/TCP checksum offload, 2880 * the hardware checksum assist gives incorrect results (possibly 2881 * from incorporating its own padding into the UDP/TCP checksum; who knows). 2882 * If we pad such runts with zeros, the onboard checksum comes out correct. 2883 */ 2884 static __inline int 2885 bge_cksum_pad(struct mbuf *pkt) 2886 { 2887 struct mbuf *last = NULL; 2888 int padlen; 2889 2890 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 2891 2892 /* if there's only the packet-header and we can pad there, use it. */ 2893 if (pkt->m_pkthdr.len == pkt->m_len && 2894 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 2895 last = pkt; 2896 } else { 2897 /* 2898 * Walk packet chain to find last mbuf. We will either 2899 * pad there, or append a new mbuf and pad it 2900 * (thus perhaps avoiding the bcm5700 dma-min bug). 2901 */ 2902 for (last = pkt; last->m_next != NULL; last = last->m_next) { 2903 (void) 0; /* do nothing*/ 2904 } 2905 2906 /* `last' now points to last in chain. */ 2907 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 2908 (void) 0; /* we can pad here, in-place. */ 2909 } else { 2910 /* Allocate new empty mbuf, pad it. Compact later. */ 2911 struct mbuf *n; 2912 MGET(n, M_DONTWAIT, MT_DATA); 2913 n->m_len = 0; 2914 last->m_next = n; 2915 last = n; 2916 } 2917 } 2918 2919 #ifdef DEBUG 2920 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 2921 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 2922 #endif 2923 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 2924 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 2925 last->m_len += padlen; 2926 pkt->m_pkthdr.len += padlen; 2927 return 0; 2928 } 2929 2930 /* 2931 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 2932 */ 2933 static __inline int 2934 bge_compact_dma_runt(struct mbuf *pkt) 2935 { 2936 struct mbuf *m, *prev; 2937 int totlen, prevlen; 2938 2939 prev = NULL; 2940 totlen = 0; 2941 prevlen = -1; 2942 2943 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 2944 int mlen = m->m_len; 2945 int shortfall = 8 - mlen ; 2946 2947 totlen += mlen; 2948 if (mlen == 0) { 2949 continue; 2950 } 2951 if (mlen >= 8) 2952 continue; 2953 2954 /* If we get here, mbuf data is too small for DMA engine. 2955 * Try to fix by shuffling data to prev or next in chain. 2956 * If that fails, do a compacting deep-copy of the whole chain. 2957 */ 2958 2959 /* Internal frag. If fits in prev, copy it there. */ 2960 if (prev && !M_READONLY(prev) && 2961 M_TRAILINGSPACE(prev) >= m->m_len) { 2962 bcopy(m->m_data, 2963 prev->m_data+prev->m_len, 2964 mlen); 2965 prev->m_len += mlen; 2966 m->m_len = 0; 2967 /* XXX stitch chain */ 2968 prev->m_next = m_free(m); 2969 m = prev; 2970 continue; 2971 } 2972 else if (m->m_next != NULL && !M_READONLY(m) && 2973 M_TRAILINGSPACE(m) >= shortfall && 2974 m->m_next->m_len >= (8 + shortfall)) { 2975 /* m is writable and have enough data in next, pull up. */ 2976 2977 bcopy(m->m_next->m_data, 2978 m->m_data+m->m_len, 2979 shortfall); 2980 m->m_len += shortfall; 2981 m->m_next->m_len -= shortfall; 2982 m->m_next->m_data += shortfall; 2983 } 2984 else if (m->m_next == NULL || 1) { 2985 /* Got a runt at the very end of the packet. 2986 * borrow data from the tail of the preceding mbuf and 2987 * update its length in-place. (The original data is still 2988 * valid, so we can do this even if prev is not writable.) 2989 */ 2990 2991 /* if we'd make prev a runt, just move all of its data. */ 2992 #ifdef DEBUG 2993 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 2994 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 2995 #endif 2996 if ((prev->m_len - shortfall) < 8) 2997 shortfall = prev->m_len; 2998 2999 #ifdef notyet /* just do the safe slow thing for now */ 3000 if (!M_READONLY(m)) { 3001 if (M_LEADINGSPACE(m) < shorfall) { 3002 void *m_dat; 3003 m_dat = (m->m_flags & M_PKTHDR) ? 3004 m->m_pktdat : m->dat; 3005 memmove(m_dat, mtod(m, void*), m->m_len); 3006 m->m_data = m_dat; 3007 } 3008 } else 3009 #endif /* just do the safe slow thing */ 3010 { 3011 struct mbuf * n = NULL; 3012 int newprevlen = prev->m_len - shortfall; 3013 3014 MGET(n, M_NOWAIT, MT_DATA); 3015 if (n == NULL) 3016 return ENOBUFS; 3017 KASSERT(m->m_len + shortfall < MLEN 3018 /*, 3019 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3020 3021 /* first copy the data we're stealing from prev */ 3022 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3023 3024 /* update prev->m_len accordingly */ 3025 prev->m_len -= shortfall; 3026 3027 /* copy data from runt m */ 3028 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3029 3030 /* n holds what we stole from prev, plus m */ 3031 n->m_len = shortfall + m->m_len; 3032 3033 /* stitch n into chain and free m */ 3034 n->m_next = m->m_next; 3035 prev->m_next = n; 3036 /* KASSERT(m->m_next == NULL); */ 3037 m->m_next = NULL; 3038 m_free(m); 3039 m = n; /* for continuing loop */ 3040 } 3041 } 3042 prevlen = m->m_len; 3043 } 3044 return 0; 3045 } 3046 3047 /* 3048 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3049 * pointers to descriptors. 3050 */ 3051 int 3052 bge_encap(sc, m_head, txidx) 3053 struct bge_softc *sc; 3054 struct mbuf *m_head; 3055 u_int32_t *txidx; 3056 { 3057 struct bge_tx_bd *f = NULL; 3058 u_int32_t frag, cur, cnt = 0; 3059 u_int16_t csum_flags = 0; 3060 struct txdmamap_pool_entry *dma; 3061 bus_dmamap_t dmamap; 3062 int i = 0; 3063 struct m_tag *mtag; 3064 3065 cur = frag = *txidx; 3066 3067 if (m_head->m_pkthdr.csum_flags) { 3068 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3069 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3070 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3071 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3072 } 3073 3074 /* 3075 * If we were asked to do an outboard checksum, and the NIC 3076 * has the bug where it sometimes adds in the Ethernet padding, 3077 * explicitly pad with zeros so the cksum will be correct either way. 3078 * (For now, do this for all chip versions, until newer 3079 * are confirmed to not require the workaround.) 3080 */ 3081 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3082 #ifdef notyet 3083 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3084 #endif 3085 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3086 goto check_dma_bug; 3087 3088 if (bge_cksum_pad(m_head) != 0) 3089 return ENOBUFS; 3090 3091 check_dma_bug: 3092 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3093 goto doit; 3094 /* 3095 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3096 * less than eight bytes. If we encounter a teeny mbuf 3097 * at the end of a chain, we can pad. Otherwise, copy. 3098 */ 3099 if (bge_compact_dma_runt(m_head) != 0) 3100 return ENOBUFS; 3101 3102 doit: 3103 dma = SLIST_FIRST(&sc->txdma_list); 3104 if (dma == NULL) 3105 return ENOBUFS; 3106 dmamap = dma->dmamap; 3107 3108 /* 3109 * Start packing the mbufs in this chain into 3110 * the fragment pointers. Stop when we run out 3111 * of fragments or hit the end of the mbuf chain. 3112 */ 3113 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3114 BUS_DMA_NOWAIT)) 3115 return(ENOBUFS); 3116 3117 mtag = sc->ethercom.ec_nvlans ? 3118 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3119 3120 for (i = 0; i < dmamap->dm_nsegs; i++) { 3121 f = &sc->bge_rdata->bge_tx_ring[frag]; 3122 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3123 break; 3124 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3125 f->bge_len = dmamap->dm_segs[i].ds_len; 3126 f->bge_flags = csum_flags; 3127 3128 if (mtag != NULL) { 3129 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3130 f->bge_vlan_tag = *(u_int *)(mtag + 1); 3131 } else { 3132 f->bge_vlan_tag = 0; 3133 } 3134 /* 3135 * Sanity check: avoid coming within 16 descriptors 3136 * of the end of the ring. 3137 */ 3138 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3139 return(ENOBUFS); 3140 cur = frag; 3141 BGE_INC(frag, BGE_TX_RING_CNT); 3142 cnt++; 3143 } 3144 3145 if (i < dmamap->dm_nsegs) 3146 return ENOBUFS; 3147 3148 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3149 BUS_DMASYNC_PREWRITE); 3150 3151 if (frag == sc->bge_tx_saved_considx) 3152 return(ENOBUFS); 3153 3154 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3155 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3156 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3157 sc->txdma[cur] = dma; 3158 sc->bge_txcnt += cnt; 3159 3160 *txidx = frag; 3161 3162 return(0); 3163 } 3164 3165 /* 3166 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3167 * to the mbuf data regions directly in the transmit descriptors. 3168 */ 3169 void 3170 bge_start(ifp) 3171 struct ifnet *ifp; 3172 { 3173 struct bge_softc *sc; 3174 struct mbuf *m_head = NULL; 3175 u_int32_t prodidx = 0; 3176 int pkts = 0; 3177 3178 sc = ifp->if_softc; 3179 3180 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3181 return; 3182 3183 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3184 3185 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3186 IFQ_POLL(&ifp->if_snd, m_head); 3187 if (m_head == NULL) 3188 break; 3189 3190 #if 0 3191 /* 3192 * XXX 3193 * safety overkill. If this is a fragmented packet chain 3194 * with delayed TCP/UDP checksums, then only encapsulate 3195 * it if we have enough descriptors to handle the entire 3196 * chain at once. 3197 * (paranoia -- may not actually be needed) 3198 */ 3199 if (m_head->m_flags & M_FIRSTFRAG && 3200 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3201 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3202 m_head->m_pkthdr.csum_data + 16) { 3203 ifp->if_flags |= IFF_OACTIVE; 3204 break; 3205 } 3206 } 3207 #endif 3208 3209 /* 3210 * Pack the data into the transmit ring. If we 3211 * don't have room, set the OACTIVE flag and wait 3212 * for the NIC to drain the ring. 3213 */ 3214 if (bge_encap(sc, m_head, &prodidx)) { 3215 ifp->if_flags |= IFF_OACTIVE; 3216 break; 3217 } 3218 3219 /* now we are committed to transmit the packet */ 3220 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3221 pkts++; 3222 3223 #if NBPFILTER > 0 3224 /* 3225 * If there's a BPF listener, bounce a copy of this frame 3226 * to him. 3227 */ 3228 if (ifp->if_bpf) 3229 bpf_mtap(ifp->if_bpf, m_head); 3230 #endif 3231 } 3232 if (pkts == 0) 3233 return; 3234 3235 /* Transmit */ 3236 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3237 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3238 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3239 3240 /* 3241 * Set a timeout in case the chip goes out to lunch. 3242 */ 3243 ifp->if_timer = 5; 3244 } 3245 3246 int 3247 bge_init(ifp) 3248 struct ifnet *ifp; 3249 { 3250 struct bge_softc *sc = ifp->if_softc; 3251 u_int16_t *m; 3252 int s, error; 3253 3254 s = splnet(); 3255 3256 ifp = &sc->ethercom.ec_if; 3257 3258 /* Cancel pending I/O and flush buffers. */ 3259 bge_stop(sc); 3260 bge_reset(sc); 3261 bge_chipinit(sc); 3262 3263 /* 3264 * Init the various state machines, ring 3265 * control blocks and firmware. 3266 */ 3267 error = bge_blockinit(sc); 3268 if (error != 0) { 3269 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3270 error); 3271 splx(s); 3272 return error; 3273 } 3274 3275 ifp = &sc->ethercom.ec_if; 3276 3277 /* Specify MTU. */ 3278 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3279 ETHER_HDR_LEN + ETHER_CRC_LEN); 3280 3281 /* Load our MAC address. */ 3282 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3283 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3284 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3285 3286 /* Enable or disable promiscuous mode as needed. */ 3287 if (ifp->if_flags & IFF_PROMISC) { 3288 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3289 } else { 3290 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3291 } 3292 3293 /* Program multicast filter. */ 3294 bge_setmulti(sc); 3295 3296 /* Init RX ring. */ 3297 bge_init_rx_ring_std(sc); 3298 3299 /* Init jumbo RX ring. */ 3300 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3301 bge_init_rx_ring_jumbo(sc); 3302 3303 /* Init our RX return ring index */ 3304 sc->bge_rx_saved_considx = 0; 3305 3306 /* Init TX ring. */ 3307 bge_init_tx_ring(sc); 3308 3309 /* Turn on transmitter */ 3310 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3311 3312 /* Turn on receiver */ 3313 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3314 3315 /* Tell firmware we're alive. */ 3316 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3317 3318 /* Enable host interrupts. */ 3319 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3320 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3321 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3322 3323 bge_ifmedia_upd(ifp); 3324 3325 ifp->if_flags |= IFF_RUNNING; 3326 ifp->if_flags &= ~IFF_OACTIVE; 3327 3328 splx(s); 3329 3330 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3331 3332 return 0; 3333 } 3334 3335 /* 3336 * Set media options. 3337 */ 3338 int 3339 bge_ifmedia_upd(ifp) 3340 struct ifnet *ifp; 3341 { 3342 struct bge_softc *sc = ifp->if_softc; 3343 struct mii_data *mii = &sc->bge_mii; 3344 struct ifmedia *ifm = &sc->bge_ifmedia; 3345 3346 /* If this is a 1000baseX NIC, enable the TBI port. */ 3347 if (sc->bge_tbi) { 3348 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3349 return(EINVAL); 3350 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3351 case IFM_AUTO: 3352 break; 3353 case IFM_1000_SX: 3354 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3355 BGE_CLRBIT(sc, BGE_MAC_MODE, 3356 BGE_MACMODE_HALF_DUPLEX); 3357 } else { 3358 BGE_SETBIT(sc, BGE_MAC_MODE, 3359 BGE_MACMODE_HALF_DUPLEX); 3360 } 3361 break; 3362 default: 3363 return(EINVAL); 3364 } 3365 return(0); 3366 } 3367 3368 sc->bge_link = 0; 3369 mii_mediachg(mii); 3370 3371 return(0); 3372 } 3373 3374 /* 3375 * Report current media status. 3376 */ 3377 void 3378 bge_ifmedia_sts(ifp, ifmr) 3379 struct ifnet *ifp; 3380 struct ifmediareq *ifmr; 3381 { 3382 struct bge_softc *sc = ifp->if_softc; 3383 struct mii_data *mii = &sc->bge_mii; 3384 3385 if (sc->bge_tbi) { 3386 ifmr->ifm_status = IFM_AVALID; 3387 ifmr->ifm_active = IFM_ETHER; 3388 if (CSR_READ_4(sc, BGE_MAC_STS) & 3389 BGE_MACSTAT_TBI_PCS_SYNCHED) 3390 ifmr->ifm_status |= IFM_ACTIVE; 3391 ifmr->ifm_active |= IFM_1000_SX; 3392 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3393 ifmr->ifm_active |= IFM_HDX; 3394 else 3395 ifmr->ifm_active |= IFM_FDX; 3396 return; 3397 } 3398 3399 mii_pollstat(mii); 3400 ifmr->ifm_active = mii->mii_media_active; 3401 ifmr->ifm_status = mii->mii_media_status; 3402 } 3403 3404 int 3405 bge_ioctl(ifp, command, data) 3406 struct ifnet *ifp; 3407 u_long command; 3408 caddr_t data; 3409 { 3410 struct bge_softc *sc = ifp->if_softc; 3411 struct ifreq *ifr = (struct ifreq *) data; 3412 int s, error = 0; 3413 struct mii_data *mii; 3414 3415 s = splnet(); 3416 3417 switch(command) { 3418 case SIOCSIFFLAGS: 3419 if (ifp->if_flags & IFF_UP) { 3420 /* 3421 * If only the state of the PROMISC flag changed, 3422 * then just use the 'set promisc mode' command 3423 * instead of reinitializing the entire NIC. Doing 3424 * a full re-init means reloading the firmware and 3425 * waiting for it to start up, which may take a 3426 * second or two. 3427 */ 3428 if (ifp->if_flags & IFF_RUNNING && 3429 ifp->if_flags & IFF_PROMISC && 3430 !(sc->bge_if_flags & IFF_PROMISC)) { 3431 BGE_SETBIT(sc, BGE_RX_MODE, 3432 BGE_RXMODE_RX_PROMISC); 3433 } else if (ifp->if_flags & IFF_RUNNING && 3434 !(ifp->if_flags & IFF_PROMISC) && 3435 sc->bge_if_flags & IFF_PROMISC) { 3436 BGE_CLRBIT(sc, BGE_RX_MODE, 3437 BGE_RXMODE_RX_PROMISC); 3438 } else 3439 bge_init(ifp); 3440 } else { 3441 if (ifp->if_flags & IFF_RUNNING) { 3442 bge_stop(sc); 3443 } 3444 } 3445 sc->bge_if_flags = ifp->if_flags; 3446 error = 0; 3447 break; 3448 case SIOCSIFMEDIA: 3449 case SIOCGIFMEDIA: 3450 if (sc->bge_tbi) { 3451 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3452 command); 3453 } else { 3454 mii = &sc->bge_mii; 3455 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3456 command); 3457 } 3458 error = 0; 3459 break; 3460 default: 3461 error = ether_ioctl(ifp, command, data); 3462 if (error == ENETRESET) { 3463 bge_setmulti(sc); 3464 error = 0; 3465 } 3466 break; 3467 } 3468 3469 splx(s); 3470 3471 return(error); 3472 } 3473 3474 void 3475 bge_watchdog(ifp) 3476 struct ifnet *ifp; 3477 { 3478 struct bge_softc *sc; 3479 3480 sc = ifp->if_softc; 3481 3482 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3483 3484 ifp->if_flags &= ~IFF_RUNNING; 3485 bge_init(ifp); 3486 3487 ifp->if_oerrors++; 3488 } 3489 3490 static void 3491 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3492 { 3493 int i; 3494 3495 BGE_CLRBIT(sc, reg, bit); 3496 3497 for (i = 0; i < BGE_TIMEOUT; i++) { 3498 if ((CSR_READ_4(sc, reg) & bit) == 0) 3499 return; 3500 delay(100); 3501 } 3502 3503 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3504 sc->bge_dev.dv_xname, (u_long) reg, bit); 3505 } 3506 3507 /* 3508 * Stop the adapter and free any mbufs allocated to the 3509 * RX and TX lists. 3510 */ 3511 void 3512 bge_stop(sc) 3513 struct bge_softc *sc; 3514 { 3515 struct ifnet *ifp = &sc->ethercom.ec_if; 3516 3517 callout_stop(&sc->bge_timeout); 3518 3519 /* 3520 * Disable all of the receiver blocks 3521 */ 3522 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3523 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3524 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3525 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3526 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3527 } 3528 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3529 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3530 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3531 3532 /* 3533 * Disable all of the transmit blocks 3534 */ 3535 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3536 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3537 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3538 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3539 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3540 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3541 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3542 } 3543 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3544 3545 /* 3546 * Shut down all of the memory managers and related 3547 * state machines. 3548 */ 3549 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3550 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3551 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3552 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3553 } 3554 3555 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3556 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3557 3558 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3559 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3560 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3561 } 3562 3563 /* Disable host interrupts. */ 3564 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3565 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3566 3567 /* 3568 * Tell firmware we're shutting down. 3569 */ 3570 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3571 3572 /* Free the RX lists. */ 3573 bge_free_rx_ring_std(sc); 3574 3575 /* Free jumbo RX list. */ 3576 bge_free_rx_ring_jumbo(sc); 3577 3578 /* Free TX buffers. */ 3579 bge_free_tx_ring(sc); 3580 3581 /* 3582 * Isolate/power down the PHY. 3583 */ 3584 if (!sc->bge_tbi) 3585 mii_down(&sc->bge_mii); 3586 3587 sc->bge_link = 0; 3588 3589 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3590 3591 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3592 } 3593 3594 /* 3595 * Stop all chip I/O so that the kernel's probe routines don't 3596 * get confused by errant DMAs when rebooting. 3597 */ 3598 void 3599 bge_shutdown(xsc) 3600 void *xsc; 3601 { 3602 struct bge_softc *sc = (struct bge_softc *)xsc; 3603 3604 bge_stop(sc); 3605 bge_reset(sc); 3606 } 3607
Indexes created Thu Sep 25 02:09:54 GMT 2025