if_bge.c revision 1.63
1 /* $NetBSD: if_bge.c,v 1.63 2004/03/20 02:04:07 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.63 2004/03/20 02:04:07 jonathan Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/miidevs.h> 120 #include <dev/mii/brgphyreg.h> 121 122 #include <dev/pci/if_bgereg.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 127 128 129 /* 130 * Tunable thresholds for rx-side bge interrupt mitigation. 131 */ 132 133 /* 134 * The pairs of values below were obtained from empirical measurement 135 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 136 * interrupt for every N packets received, where N is, approximately, 137 * the second value (rx_max_bds) in each pair. The values are chosen 138 * such that moving from one pair to the succeeding pair was observed 139 * to roughly halve interrupt rate under sustained input packet load. 140 * The values were empirically chosen to avoid overflowing internal 141 * limits on the bcm5700: inreasing rx_ticks much beyond 600 142 * results in internal wrapping and higher interrupt rates. 143 * The limit of 46 frames was chosen to match NFS workloads. 144 * 145 * These values also work well on bcm5701, bcm5704C, and (less 146 * tested) bcm5703. On other chipsets, (including the Altima chip 147 * family), the larger values may overflow internal chip limits, 148 * leading to increasing interrupt rates rather than lower interrupt 149 * rates. 150 * 151 * Applications using heavy interrupt mitigation (interrupting every 152 * 32 or 46 frames) in both directions may need to increase the TCP 153 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 154 * full link bandwidth, due to ACKs and window updates lingering 155 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 156 */ 157 struct bge_load_rx_thresh { 158 int rx_ticks; 159 int rx_max_bds; } 160 bge_rx_threshes[] = { 161 { 32, 2 }, 162 { 50, 4 }, 163 { 100, 8 }, 164 { 192, 16 }, 165 { 416, 32 }, 166 { 598, 46 } 167 }; 168 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 169 170 /* XXX patchable; should be sysctl'able */ 171 int bge_auto_thresh = 0; 172 173 int bge_probe(struct device *, struct cfdata *, void *); 174 void bge_attach(struct device *, struct device *, void *); 175 void bge_release_resources(struct bge_softc *); 176 void bge_txeof(struct bge_softc *); 177 void bge_rxeof(struct bge_softc *); 178 179 void bge_tick(void *); 180 void bge_stats_update(struct bge_softc *); 181 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 182 static __inline int bge_cksum_pad(struct mbuf *pkt); 183 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 184 185 int bge_intr(void *); 186 void bge_start(struct ifnet *); 187 int bge_ioctl(struct ifnet *, u_long, caddr_t); 188 int bge_init(struct ifnet *); 189 void bge_stop(struct bge_softc *); 190 void bge_watchdog(struct ifnet *); 191 void bge_shutdown(void *); 192 int bge_ifmedia_upd(struct ifnet *); 193 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 194 195 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 196 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 197 198 void bge_setmulti(struct bge_softc *); 199 200 void bge_handle_events(struct bge_softc *); 201 int bge_alloc_jumbo_mem(struct bge_softc *); 202 void bge_free_jumbo_mem(struct bge_softc *); 203 void *bge_jalloc(struct bge_softc *); 204 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 205 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 206 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 207 int bge_init_rx_ring_std(struct bge_softc *); 208 void bge_free_rx_ring_std(struct bge_softc *); 209 int bge_init_rx_ring_jumbo(struct bge_softc *); 210 void bge_free_rx_ring_jumbo(struct bge_softc *); 211 void bge_free_tx_ring(struct bge_softc *); 212 int bge_init_tx_ring(struct bge_softc *); 213 214 int bge_chipinit(struct bge_softc *); 215 int bge_blockinit(struct bge_softc *); 216 int bge_setpowerstate(struct bge_softc *, int); 217 218 #ifdef notdef 219 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 220 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 221 void bge_vpd_read(struct bge_softc *); 222 #endif 223 224 u_int32_t bge_readmem_ind(struct bge_softc *, int); 225 void bge_writemem_ind(struct bge_softc *, int, int); 226 #ifdef notdef 227 u_int32_t bge_readreg_ind(struct bge_softc *, int); 228 #endif 229 void bge_writereg_ind(struct bge_softc *, int, int); 230 231 int bge_miibus_readreg(struct device *, int, int); 232 void bge_miibus_writereg(struct device *, int, int, int); 233 void bge_miibus_statchg(struct device *); 234 235 void bge_reset(struct bge_softc *); 236 237 void bge_set_thresh(struct ifnet * /*ifp*/, int /*lvl*/); 238 void bge_update_all_threshes(int /*lvl*/); 239 240 void bge_dump_status(struct bge_softc *); 241 void bge_dump_rxbd(struct bge_rx_bd *); 242 243 #define BGE_DEBUG 244 #ifdef BGE_DEBUG 245 #define DPRINTF(x) if (bgedebug) printf x 246 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 247 int bgedebug = 0; 248 #else 249 #define DPRINTF(x) 250 #define DPRINTFN(n,x) 251 #endif 252 253 /* Various chip quirks. */ 254 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 255 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 256 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 257 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 258 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 259 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 260 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 261 #define BGE_QUIRK_5705_CORE 0x00000080 262 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 263 264 /* following bugs are common to bcm5700 rev B, all flavours */ 265 #define BGE_QUIRK_5700_COMMON \ 266 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 267 268 CFATTACH_DECL(bge, sizeof(struct bge_softc), 269 bge_probe, bge_attach, NULL, NULL); 270 271 u_int32_t 272 bge_readmem_ind(sc, off) 273 struct bge_softc *sc; 274 int off; 275 { 276 struct pci_attach_args *pa = &(sc->bge_pa); 277 pcireg_t val; 278 279 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 280 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 281 return val; 282 } 283 284 void 285 bge_writemem_ind(sc, off, val) 286 struct bge_softc *sc; 287 int off, val; 288 { 289 struct pci_attach_args *pa = &(sc->bge_pa); 290 291 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 292 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 293 } 294 295 #ifdef notdef 296 u_int32_t 297 bge_readreg_ind(sc, off) 298 struct bge_softc *sc; 299 int off; 300 { 301 struct pci_attach_args *pa = &(sc->bge_pa); 302 303 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 304 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 305 } 306 #endif 307 308 void 309 bge_writereg_ind(sc, off, val) 310 struct bge_softc *sc; 311 int off, val; 312 { 313 struct pci_attach_args *pa = &(sc->bge_pa); 314 315 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 316 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 317 } 318 319 #ifdef notdef 320 u_int8_t 321 bge_vpd_readbyte(sc, addr) 322 struct bge_softc *sc; 323 int addr; 324 { 325 int i; 326 u_int32_t val; 327 struct pci_attach_args *pa = &(sc->bge_pa); 328 329 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 330 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 331 DELAY(10); 332 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 333 BGE_VPD_FLAG) 334 break; 335 } 336 337 if (i == BGE_TIMEOUT) { 338 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 339 return(0); 340 } 341 342 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 343 344 return((val >> ((addr % 4) * 8)) & 0xFF); 345 } 346 347 void 348 bge_vpd_read_res(sc, res, addr) 349 struct bge_softc *sc; 350 struct vpd_res *res; 351 int addr; 352 { 353 int i; 354 u_int8_t *ptr; 355 356 ptr = (u_int8_t *)res; 357 for (i = 0; i < sizeof(struct vpd_res); i++) 358 ptr[i] = bge_vpd_readbyte(sc, i + addr); 359 } 360 361 void 362 bge_vpd_read(sc) 363 struct bge_softc *sc; 364 { 365 int pos = 0, i; 366 struct vpd_res res; 367 368 if (sc->bge_vpd_prodname != NULL) 369 free(sc->bge_vpd_prodname, M_DEVBUF); 370 if (sc->bge_vpd_readonly != NULL) 371 free(sc->bge_vpd_readonly, M_DEVBUF); 372 sc->bge_vpd_prodname = NULL; 373 sc->bge_vpd_readonly = NULL; 374 375 bge_vpd_read_res(sc, &res, pos); 376 377 if (res.vr_id != VPD_RES_ID) { 378 printf("%s: bad VPD resource id: expected %x got %x\n", 379 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 380 return; 381 } 382 383 pos += sizeof(res); 384 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 385 if (sc->bge_vpd_prodname == NULL) 386 panic("bge_vpd_read"); 387 for (i = 0; i < res.vr_len; i++) 388 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 389 sc->bge_vpd_prodname[i] = '\0'; 390 pos += i; 391 392 bge_vpd_read_res(sc, &res, pos); 393 394 if (res.vr_id != VPD_RES_READ) { 395 printf("%s: bad VPD resource id: expected %x got %x\n", 396 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 402 if (sc->bge_vpd_readonly == NULL) 403 panic("bge_vpd_read"); 404 for (i = 0; i < res.vr_len + 1; i++) 405 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 406 } 407 #endif 408 409 /* 410 * Read a byte of data stored in the EEPROM at address 'addr.' The 411 * BCM570x supports both the traditional bitbang interface and an 412 * auto access interface for reading the EEPROM. We use the auto 413 * access method. 414 */ 415 u_int8_t 416 bge_eeprom_getbyte(sc, addr, dest) 417 struct bge_softc *sc; 418 int addr; 419 u_int8_t *dest; 420 { 421 int i; 422 u_int32_t byte = 0; 423 424 /* 425 * Enable use of auto EEPROM access so we can avoid 426 * having to use the bitbang method. 427 */ 428 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 429 430 /* Reset the EEPROM, load the clock period. */ 431 CSR_WRITE_4(sc, BGE_EE_ADDR, 432 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 433 DELAY(20); 434 435 /* Issue the read EEPROM command. */ 436 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 437 438 /* Wait for completion */ 439 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 440 DELAY(10); 441 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 442 break; 443 } 444 445 if (i == BGE_TIMEOUT) { 446 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 447 return(0); 448 } 449 450 /* Get result. */ 451 byte = CSR_READ_4(sc, BGE_EE_DATA); 452 453 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 454 455 return(0); 456 } 457 458 /* 459 * Read a sequence of bytes from the EEPROM. 460 */ 461 int 462 bge_read_eeprom(sc, dest, off, cnt) 463 struct bge_softc *sc; 464 caddr_t dest; 465 int off; 466 int cnt; 467 { 468 int err = 0, i; 469 u_int8_t byte = 0; 470 471 for (i = 0; i < cnt; i++) { 472 err = bge_eeprom_getbyte(sc, off + i, &byte); 473 if (err) 474 break; 475 *(dest + i) = byte; 476 } 477 478 return(err ? 1 : 0); 479 } 480 481 int 482 bge_miibus_readreg(dev, phy, reg) 483 struct device *dev; 484 int phy, reg; 485 { 486 struct bge_softc *sc = (struct bge_softc *)dev; 487 u_int32_t val; 488 u_int32_t saved_autopoll; 489 int i; 490 491 /* 492 * Several chips with builtin PHYs will incorrectly answer to 493 * other PHY instances than the builtin PHY at id 1. 494 */ 495 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 496 return(0); 497 498 /* Reading with autopolling on may trigger PCI errors */ 499 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 500 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 501 CSR_WRITE_4(sc, BGE_MI_MODE, 502 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 503 DELAY(40); 504 } 505 506 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 507 BGE_MIPHY(phy)|BGE_MIREG(reg)); 508 509 for (i = 0; i < BGE_TIMEOUT; i++) { 510 val = CSR_READ_4(sc, BGE_MI_COMM); 511 if (!(val & BGE_MICOMM_BUSY)) 512 break; 513 delay(10); 514 } 515 516 if (i == BGE_TIMEOUT) { 517 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 518 val = 0; 519 goto done; 520 } 521 522 val = CSR_READ_4(sc, BGE_MI_COMM); 523 524 done: 525 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 526 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 527 DELAY(40); 528 } 529 530 if (val & BGE_MICOMM_READFAIL) 531 return(0); 532 533 return(val & 0xFFFF); 534 } 535 536 void 537 bge_miibus_writereg(dev, phy, reg, val) 538 struct device *dev; 539 int phy, reg, val; 540 { 541 struct bge_softc *sc = (struct bge_softc *)dev; 542 u_int32_t saved_autopoll; 543 int i; 544 545 /* Touching the PHY while autopolling is on may trigger PCI errors */ 546 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 547 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 548 delay(40); 549 CSR_WRITE_4(sc, BGE_MI_MODE, 550 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 551 delay(10); /* 40 usec is supposed to be adequate */ 552 } 553 554 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 555 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 556 557 for (i = 0; i < BGE_TIMEOUT; i++) { 558 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 559 break; 560 delay(10); 561 } 562 563 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 564 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 565 delay(40); 566 } 567 568 if (i == BGE_TIMEOUT) { 569 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 570 } 571 } 572 573 void 574 bge_miibus_statchg(dev) 575 struct device *dev; 576 { 577 struct bge_softc *sc = (struct bge_softc *)dev; 578 struct mii_data *mii = &sc->bge_mii; 579 580 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 581 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 582 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 583 } else { 584 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 585 } 586 587 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 588 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 589 } else { 590 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 591 } 592 } 593 594 /* 595 * Update rx threshold levels to values in a particular slot 596 * of the interrupt-mitigation table bge_rx_threshes. 597 */ 598 void 599 bge_set_thresh(struct ifnet *ifp, int lvl) 600 { 601 struct bge_softc *sc = ifp->if_softc; 602 int s; 603 604 /* For now, just save the new Rx-intr thresholds and record 605 * that a threshold update is pending. Updating the hardware 606 * registers here (even at splhigh()) is observed to 607 * occasionaly cause glitches where Rx-interrupts are not 608 * honoured for up to 10 seconds. jonathan (at) netbsd.org, 2003-04-05 609 */ 610 s = splnet(); 611 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 612 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 613 sc->bge_pending_rxintr_change = 1; 614 splx(s); 615 616 return; 617 } 618 619 620 /* 621 * Update Rx thresholds of all bge devices 622 */ 623 void 624 bge_update_all_threshes(int lvl) 625 { 626 struct ifnet *ifp; 627 const char * const namebuf = "bge"; 628 int namelen; 629 630 if (lvl < 0) 631 lvl = 0; 632 else if( lvl >= NBGE_RX_THRESH) 633 lvl = NBGE_RX_THRESH - 1; 634 635 namelen = strlen(namebuf); 636 /* 637 * Now search all the interfaces for this name/number 638 */ 639 TAILQ_FOREACH(ifp, &ifnet, if_list) { 640 if (strncmp(ifp->if_xname, namebuf, namelen) != 0 ) 641 continue; 642 /* We got a match: update if doing auto-threshold-tuning */ 643 if (bge_auto_thresh) 644 bge_set_thresh(ifp->if_softc, lvl); 645 } 646 } 647 648 /* 649 * Handle events that have triggered interrupts. 650 */ 651 void 652 bge_handle_events(sc) 653 struct bge_softc *sc; 654 { 655 656 return; 657 } 658 659 /* 660 * Memory management for jumbo frames. 661 */ 662 663 int 664 bge_alloc_jumbo_mem(sc) 665 struct bge_softc *sc; 666 { 667 caddr_t ptr, kva; 668 bus_dma_segment_t seg; 669 int i, rseg, state, error; 670 struct bge_jpool_entry *entry; 671 672 state = error = 0; 673 674 /* Grab a big chunk o' storage. */ 675 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 676 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 677 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 678 return ENOBUFS; 679 } 680 681 state = 1; 682 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 683 BUS_DMA_NOWAIT)) { 684 printf("%s: can't map DMA buffers (%d bytes)\n", 685 sc->bge_dev.dv_xname, (int)BGE_JMEM); 686 error = ENOBUFS; 687 goto out; 688 } 689 690 state = 2; 691 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 692 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 693 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 694 error = ENOBUFS; 695 goto out; 696 } 697 698 state = 3; 699 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 700 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 701 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 702 error = ENOBUFS; 703 goto out; 704 } 705 706 state = 4; 707 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 708 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 709 710 SLIST_INIT(&sc->bge_jfree_listhead); 711 SLIST_INIT(&sc->bge_jinuse_listhead); 712 713 /* 714 * Now divide it up into 9K pieces and save the addresses 715 * in an array. 716 */ 717 ptr = sc->bge_cdata.bge_jumbo_buf; 718 for (i = 0; i < BGE_JSLOTS; i++) { 719 sc->bge_cdata.bge_jslots[i] = ptr; 720 ptr += BGE_JLEN; 721 entry = malloc(sizeof(struct bge_jpool_entry), 722 M_DEVBUF, M_NOWAIT); 723 if (entry == NULL) { 724 printf("%s: no memory for jumbo buffer queue!\n", 725 sc->bge_dev.dv_xname); 726 error = ENOBUFS; 727 goto out; 728 } 729 entry->slot = i; 730 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 731 entry, jpool_entries); 732 } 733 out: 734 if (error != 0) { 735 switch (state) { 736 case 4: 737 bus_dmamap_unload(sc->bge_dmatag, 738 sc->bge_cdata.bge_rx_jumbo_map); 739 case 3: 740 bus_dmamap_destroy(sc->bge_dmatag, 741 sc->bge_cdata.bge_rx_jumbo_map); 742 case 2: 743 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 744 case 1: 745 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 746 break; 747 default: 748 break; 749 } 750 } 751 752 return error; 753 } 754 755 /* 756 * Allocate a jumbo buffer. 757 */ 758 void * 759 bge_jalloc(sc) 760 struct bge_softc *sc; 761 { 762 struct bge_jpool_entry *entry; 763 764 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 765 766 if (entry == NULL) { 767 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 768 return(NULL); 769 } 770 771 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 772 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 773 return(sc->bge_cdata.bge_jslots[entry->slot]); 774 } 775 776 /* 777 * Release a jumbo buffer. 778 */ 779 void 780 bge_jfree(m, buf, size, arg) 781 struct mbuf *m; 782 caddr_t buf; 783 size_t size; 784 void *arg; 785 { 786 struct bge_jpool_entry *entry; 787 struct bge_softc *sc; 788 int i, s; 789 790 /* Extract the softc struct pointer. */ 791 sc = (struct bge_softc *)arg; 792 793 if (sc == NULL) 794 panic("bge_jfree: can't find softc pointer!"); 795 796 /* calculate the slot this buffer belongs to */ 797 798 i = ((caddr_t)buf 799 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 800 801 if ((i < 0) || (i >= BGE_JSLOTS)) 802 panic("bge_jfree: asked to free buffer that we don't manage!"); 803 804 s = splvm(); 805 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 806 if (entry == NULL) 807 panic("bge_jfree: buffer not in use!"); 808 entry->slot = i; 809 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 810 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 811 812 if (__predict_true(m != NULL)) 813 pool_cache_put(&mbpool_cache, m); 814 splx(s); 815 } 816 817 818 /* 819 * Intialize a standard receive ring descriptor. 820 */ 821 int 822 bge_newbuf_std(sc, i, m, dmamap) 823 struct bge_softc *sc; 824 int i; 825 struct mbuf *m; 826 bus_dmamap_t dmamap; 827 { 828 struct mbuf *m_new = NULL; 829 struct bge_rx_bd *r; 830 int error; 831 832 if (dmamap == NULL) { 833 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 834 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 835 if (error != 0) 836 return error; 837 } 838 839 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 840 841 if (m == NULL) { 842 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 843 if (m_new == NULL) { 844 return(ENOBUFS); 845 } 846 847 MCLGET(m_new, M_DONTWAIT); 848 if (!(m_new->m_flags & M_EXT)) { 849 m_freem(m_new); 850 return(ENOBUFS); 851 } 852 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 853 if (!sc->bge_rx_alignment_bug) 854 m_adj(m_new, ETHER_ALIGN); 855 856 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 857 BUS_DMA_READ|BUS_DMA_NOWAIT)) 858 return(ENOBUFS); 859 } else { 860 m_new = m; 861 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 862 m_new->m_data = m_new->m_ext.ext_buf; 863 if (!sc->bge_rx_alignment_bug) 864 m_adj(m_new, ETHER_ALIGN); 865 } 866 867 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 868 r = &sc->bge_rdata->bge_rx_std_ring[i]; 869 bge_set_hostaddr(&r->bge_addr, 870 dmamap->dm_segs[0].ds_addr); 871 r->bge_flags = BGE_RXBDFLAG_END; 872 r->bge_len = m_new->m_len; 873 r->bge_idx = i; 874 875 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 876 offsetof(struct bge_ring_data, bge_rx_std_ring) + 877 i * sizeof (struct bge_rx_bd), 878 sizeof (struct bge_rx_bd), 879 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 880 881 return(0); 882 } 883 884 /* 885 * Initialize a jumbo receive ring descriptor. This allocates 886 * a jumbo buffer from the pool managed internally by the driver. 887 */ 888 int 889 bge_newbuf_jumbo(sc, i, m) 890 struct bge_softc *sc; 891 int i; 892 struct mbuf *m; 893 { 894 struct mbuf *m_new = NULL; 895 struct bge_rx_bd *r; 896 897 if (m == NULL) { 898 caddr_t *buf = NULL; 899 900 /* Allocate the mbuf. */ 901 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 902 if (m_new == NULL) { 903 return(ENOBUFS); 904 } 905 906 /* Allocate the jumbo buffer */ 907 buf = bge_jalloc(sc); 908 if (buf == NULL) { 909 m_freem(m_new); 910 printf("%s: jumbo allocation failed " 911 "-- packet dropped!\n", sc->bge_dev.dv_xname); 912 return(ENOBUFS); 913 } 914 915 /* Attach the buffer to the mbuf. */ 916 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 917 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 918 bge_jfree, sc); 919 } else { 920 m_new = m; 921 m_new->m_data = m_new->m_ext.ext_buf; 922 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 923 } 924 925 if (!sc->bge_rx_alignment_bug) 926 m_adj(m_new, ETHER_ALIGN); 927 /* Set up the descriptor. */ 928 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 929 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 930 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 931 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 932 r->bge_len = m_new->m_len; 933 r->bge_idx = i; 934 935 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 936 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 937 i * sizeof (struct bge_rx_bd), 938 sizeof (struct bge_rx_bd), 939 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 940 941 return(0); 942 } 943 944 /* 945 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 946 * that's 1MB or memory, which is a lot. For now, we fill only the first 947 * 256 ring entries and hope that our CPU is fast enough to keep up with 948 * the NIC. 949 */ 950 int 951 bge_init_rx_ring_std(sc) 952 struct bge_softc *sc; 953 { 954 int i; 955 956 if (sc->bge_flags & BGE_RXRING_VALID) 957 return 0; 958 959 for (i = 0; i < BGE_SSLOTS; i++) { 960 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 961 return(ENOBUFS); 962 } 963 964 sc->bge_std = i - 1; 965 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 966 967 sc->bge_flags |= BGE_RXRING_VALID; 968 969 return(0); 970 } 971 972 void 973 bge_free_rx_ring_std(sc) 974 struct bge_softc *sc; 975 { 976 int i; 977 978 if (!(sc->bge_flags & BGE_RXRING_VALID)) 979 return; 980 981 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 982 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 983 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 984 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 985 bus_dmamap_destroy(sc->bge_dmatag, 986 sc->bge_cdata.bge_rx_std_map[i]); 987 } 988 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 989 sizeof(struct bge_rx_bd)); 990 } 991 992 sc->bge_flags &= ~BGE_RXRING_VALID; 993 } 994 995 int 996 bge_init_rx_ring_jumbo(sc) 997 struct bge_softc *sc; 998 { 999 int i; 1000 volatile struct bge_rcb *rcb; 1001 1002 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1003 return 0; 1004 1005 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1006 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1007 return(ENOBUFS); 1008 }; 1009 1010 sc->bge_jumbo = i - 1; 1011 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1012 1013 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1014 rcb->bge_maxlen_flags = 0; 1015 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1016 1017 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1018 1019 return(0); 1020 } 1021 1022 void 1023 bge_free_rx_ring_jumbo(sc) 1024 struct bge_softc *sc; 1025 { 1026 int i; 1027 1028 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1029 return; 1030 1031 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1032 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1033 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1034 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1035 } 1036 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1037 sizeof(struct bge_rx_bd)); 1038 } 1039 1040 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1041 } 1042 1043 void 1044 bge_free_tx_ring(sc) 1045 struct bge_softc *sc; 1046 { 1047 int i, freed; 1048 struct txdmamap_pool_entry *dma; 1049 1050 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1051 return; 1052 1053 freed = 0; 1054 1055 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1056 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1057 freed++; 1058 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1059 sc->bge_cdata.bge_tx_chain[i] = NULL; 1060 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1061 link); 1062 sc->txdma[i] = 0; 1063 } 1064 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1065 sizeof(struct bge_tx_bd)); 1066 } 1067 1068 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1069 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1070 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1071 free(dma, M_DEVBUF); 1072 } 1073 1074 sc->bge_flags &= ~BGE_TXRING_VALID; 1075 } 1076 1077 int 1078 bge_init_tx_ring(sc) 1079 struct bge_softc *sc; 1080 { 1081 int i; 1082 bus_dmamap_t dmamap; 1083 struct txdmamap_pool_entry *dma; 1084 1085 if (sc->bge_flags & BGE_TXRING_VALID) 1086 return 0; 1087 1088 sc->bge_txcnt = 0; 1089 sc->bge_tx_saved_considx = 0; 1090 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1091 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1092 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1093 1094 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1095 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1096 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1097 1098 SLIST_INIT(&sc->txdma_list); 1099 for (i = 0; i < BGE_RSLOTS; i++) { 1100 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 1101 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1102 &dmamap)) 1103 return(ENOBUFS); 1104 if (dmamap == NULL) 1105 panic("dmamap NULL in bge_init_tx_ring"); 1106 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1107 if (dma == NULL) { 1108 printf("%s: can't alloc txdmamap_pool_entry\n", 1109 sc->bge_dev.dv_xname); 1110 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1111 return (ENOMEM); 1112 } 1113 dma->dmamap = dmamap; 1114 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1115 } 1116 1117 sc->bge_flags |= BGE_TXRING_VALID; 1118 1119 return(0); 1120 } 1121 1122 void 1123 bge_setmulti(sc) 1124 struct bge_softc *sc; 1125 { 1126 struct ethercom *ac = &sc->ethercom; 1127 struct ifnet *ifp = &ac->ec_if; 1128 struct ether_multi *enm; 1129 struct ether_multistep step; 1130 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1131 u_int32_t h; 1132 int i; 1133 1134 if (ifp->if_flags & IFF_PROMISC) 1135 goto allmulti; 1136 1137 /* Now program new ones. */ 1138 ETHER_FIRST_MULTI(step, ac, enm); 1139 while (enm != NULL) { 1140 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1141 /* 1142 * We must listen to a range of multicast addresses. 1143 * For now, just accept all multicasts, rather than 1144 * trying to set only those filter bits needed to match 1145 * the range. (At this time, the only use of address 1146 * ranges is for IP multicast routing, for which the 1147 * range is big enough to require all bits set.) 1148 */ 1149 goto allmulti; 1150 } 1151 1152 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1153 1154 /* Just want the 7 least-significant bits. */ 1155 h &= 0x7f; 1156 1157 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1158 ETHER_NEXT_MULTI(step, enm); 1159 } 1160 1161 ifp->if_flags &= ~IFF_ALLMULTI; 1162 goto setit; 1163 1164 allmulti: 1165 ifp->if_flags |= IFF_ALLMULTI; 1166 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1167 1168 setit: 1169 for (i = 0; i < 4; i++) 1170 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1171 } 1172 1173 const int bge_swapbits[] = { 1174 0, 1175 BGE_MODECTL_BYTESWAP_DATA, 1176 BGE_MODECTL_WORDSWAP_DATA, 1177 BGE_MODECTL_BYTESWAP_NONFRAME, 1178 BGE_MODECTL_WORDSWAP_NONFRAME, 1179 1180 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1181 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1182 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1183 1184 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1185 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1186 1187 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1188 1189 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1190 BGE_MODECTL_BYTESWAP_NONFRAME, 1191 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1192 BGE_MODECTL_WORDSWAP_NONFRAME, 1193 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1194 BGE_MODECTL_WORDSWAP_NONFRAME, 1195 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1196 BGE_MODECTL_WORDSWAP_NONFRAME, 1197 1198 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1199 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1200 }; 1201 1202 int bge_swapindex = 0; 1203 1204 /* 1205 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1206 * self-test results. 1207 */ 1208 int 1209 bge_chipinit(sc) 1210 struct bge_softc *sc; 1211 { 1212 u_int32_t cachesize; 1213 int i; 1214 u_int32_t dma_rw_ctl; 1215 struct pci_attach_args *pa = &(sc->bge_pa); 1216 1217 1218 /* Set endianness before we access any non-PCI registers. */ 1219 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1220 BGE_INIT); 1221 1222 /* Set power state to D0. */ 1223 bge_setpowerstate(sc, 0); 1224 1225 /* 1226 * Check the 'ROM failed' bit on the RX CPU to see if 1227 * self-tests passed. 1228 */ 1229 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1230 printf("%s: RX CPU self-diagnostics failed!\n", 1231 sc->bge_dev.dv_xname); 1232 return(ENODEV); 1233 } 1234 1235 /* Clear the MAC control register */ 1236 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1237 1238 /* 1239 * Clear the MAC statistics block in the NIC's 1240 * internal memory. 1241 */ 1242 for (i = BGE_STATS_BLOCK; 1243 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1244 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1245 1246 for (i = BGE_STATUS_BLOCK; 1247 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1248 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1249 1250 /* Set up the PCI DMA control register. */ 1251 if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1252 BGE_PCISTATE_PCI_BUSMODE) { 1253 /* Conventional PCI bus */ 1254 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1255 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1256 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1257 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1258 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1259 dma_rw_ctl |= 0x0F; 1260 } 1261 } else { 1262 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1263 /* PCI-X bus */ 1264 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1265 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1266 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1267 (0x0F); 1268 /* 1269 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1270 * for hardware bugs, which means we should also clear 1271 * the low-order MINDMA bits. In addition, the 5704 1272 * uses a different encoding of read/write watermarks. 1273 */ 1274 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1275 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1276 /* should be 0x1f0000 */ 1277 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1278 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1279 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1280 } 1281 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1282 dma_rw_ctl &= 0xfffffff0; 1283 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1284 } 1285 } 1286 1287 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1288 1289 /* 1290 * Set up general mode register. 1291 */ 1292 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1293 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1294 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1295 1296 /* Get cache line size. */ 1297 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1298 1299 /* 1300 * Avoid violating PCI spec on certain chip revs. 1301 */ 1302 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1303 PCIM_CMD_MWIEN) { 1304 switch(cachesize) { 1305 case 1: 1306 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1307 BGE_PCI_WRITE_BNDRY_16BYTES); 1308 break; 1309 case 2: 1310 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1311 BGE_PCI_WRITE_BNDRY_32BYTES); 1312 break; 1313 case 4: 1314 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1315 BGE_PCI_WRITE_BNDRY_64BYTES); 1316 break; 1317 case 8: 1318 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1319 BGE_PCI_WRITE_BNDRY_128BYTES); 1320 break; 1321 case 16: 1322 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1323 BGE_PCI_WRITE_BNDRY_256BYTES); 1324 break; 1325 case 32: 1326 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1327 BGE_PCI_WRITE_BNDRY_512BYTES); 1328 break; 1329 case 64: 1330 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1331 BGE_PCI_WRITE_BNDRY_1024BYTES); 1332 break; 1333 default: 1334 /* Disable PCI memory write and invalidate. */ 1335 #if 0 1336 if (bootverbose) 1337 printf("%s: cache line size %d not " 1338 "supported; disabling PCI MWI\n", 1339 sc->bge_dev.dv_xname, cachesize); 1340 #endif 1341 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1342 PCIM_CMD_MWIEN); 1343 break; 1344 } 1345 } 1346 1347 /* 1348 * Disable memory write invalidate. Apparently it is not supported 1349 * properly by these devices. 1350 */ 1351 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1352 1353 1354 #ifdef __brokenalpha__ 1355 /* 1356 * Must insure that we do not cross an 8K (bytes) boundary 1357 * for DMA reads. Our highest limit is 1K bytes. This is a 1358 * restriction on some ALPHA platforms with early revision 1359 * 21174 PCI chipsets, such as the AlphaPC 164lx 1360 */ 1361 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1362 #endif 1363 1364 /* Set the timer prescaler (always 66MHz) */ 1365 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1366 1367 return(0); 1368 } 1369 1370 int 1371 bge_blockinit(sc) 1372 struct bge_softc *sc; 1373 { 1374 volatile struct bge_rcb *rcb; 1375 bus_size_t rcb_addr; 1376 int i; 1377 struct ifnet *ifp = &sc->ethercom.ec_if; 1378 bge_hostaddr taddr; 1379 1380 /* 1381 * Initialize the memory window pointer register so that 1382 * we can access the first 32K of internal NIC RAM. This will 1383 * allow us to set up the TX send ring RCBs and the RX return 1384 * ring RCBs, plus other things which live in NIC memory. 1385 */ 1386 1387 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1388 BGE_PCI_MEMWIN_BASEADDR, 0); 1389 1390 /* Configure mbuf memory pool */ 1391 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1392 if (sc->bge_extram) { 1393 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1394 BGE_EXT_SSRAM); 1395 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1396 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1397 else 1398 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1399 } else { 1400 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1401 BGE_BUFFPOOL_1); 1402 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1403 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1404 else 1405 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1406 } 1407 1408 /* Configure DMA resource pool */ 1409 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1410 BGE_DMA_DESCRIPTORS); 1411 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1412 } 1413 1414 /* Configure mbuf pool watermarks */ 1415 #ifdef ORIG_WPAUL_VALUES 1416 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1417 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1418 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1419 #else 1420 /* new broadcom docs strongly recommend these: */ 1421 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1422 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1423 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1424 } else { 1425 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1426 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1427 } 1428 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1429 #endif 1430 1431 /* Configure DMA resource watermarks */ 1432 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1433 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1434 1435 /* Enable buffer manager */ 1436 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1437 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1438 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1439 1440 /* Poll for buffer manager start indication */ 1441 for (i = 0; i < BGE_TIMEOUT; i++) { 1442 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1443 break; 1444 DELAY(10); 1445 } 1446 1447 if (i == BGE_TIMEOUT) { 1448 printf("%s: buffer manager failed to start\n", 1449 sc->bge_dev.dv_xname); 1450 return(ENXIO); 1451 } 1452 } 1453 1454 /* Enable flow-through queues */ 1455 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1456 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1457 1458 /* Wait until queue initialization is complete */ 1459 for (i = 0; i < BGE_TIMEOUT; i++) { 1460 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1461 break; 1462 DELAY(10); 1463 } 1464 1465 if (i == BGE_TIMEOUT) { 1466 printf("%s: flow-through queue init failed\n", 1467 sc->bge_dev.dv_xname); 1468 return(ENXIO); 1469 } 1470 1471 /* Initialize the standard RX ring control block */ 1472 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1473 bge_set_hostaddr(&rcb->bge_hostaddr, 1474 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1475 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1476 rcb->bge_maxlen_flags = 1477 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1478 } else { 1479 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1480 } 1481 if (sc->bge_extram) 1482 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1483 else 1484 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1485 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1486 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1487 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1488 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1489 1490 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1491 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1492 } else { 1493 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1494 } 1495 1496 /* 1497 * Initialize the jumbo RX ring control block 1498 * We set the 'ring disabled' bit in the flags 1499 * field until we're actually ready to start 1500 * using this ring (i.e. once we set the MTU 1501 * high enough to require it). 1502 */ 1503 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1504 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1505 bge_set_hostaddr(&rcb->bge_hostaddr, 1506 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1507 rcb->bge_maxlen_flags = 1508 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1509 BGE_RCB_FLAG_RING_DISABLED); 1510 if (sc->bge_extram) 1511 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1512 else 1513 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1514 1515 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1516 rcb->bge_hostaddr.bge_addr_hi); 1517 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1518 rcb->bge_hostaddr.bge_addr_lo); 1519 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1520 rcb->bge_maxlen_flags); 1521 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1522 1523 /* Set up dummy disabled mini ring RCB */ 1524 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1525 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1526 BGE_RCB_FLAG_RING_DISABLED); 1527 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1528 rcb->bge_maxlen_flags); 1529 1530 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1531 offsetof(struct bge_ring_data, bge_info), 1532 sizeof (struct bge_gib), 1533 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1534 } 1535 1536 /* 1537 * Set the BD ring replentish thresholds. The recommended 1538 * values are 1/8th the number of descriptors allocated to 1539 * each ring. 1540 */ 1541 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1542 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1543 1544 /* 1545 * Disable all unused send rings by setting the 'ring disabled' 1546 * bit in the flags field of all the TX send ring control blocks. 1547 * These are located in NIC memory. 1548 */ 1549 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1550 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1551 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1552 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1553 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1554 rcb_addr += sizeof(struct bge_rcb); 1555 } 1556 1557 /* Configure TX RCB 0 (we use only the first ring) */ 1558 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1559 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1560 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1561 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1562 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1563 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1564 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1565 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1566 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1567 } 1568 1569 /* Disable all unused RX return rings */ 1570 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1571 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1572 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1573 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1574 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1575 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1576 BGE_RCB_FLAG_RING_DISABLED)); 1577 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1578 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1579 (i * (sizeof(u_int64_t))), 0); 1580 rcb_addr += sizeof(struct bge_rcb); 1581 } 1582 1583 /* Initialize RX ring indexes */ 1584 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1585 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1586 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1587 1588 /* 1589 * Set up RX return ring 0 1590 * Note that the NIC address for RX return rings is 0x00000000. 1591 * The return rings live entirely within the host, so the 1592 * nicaddr field in the RCB isn't used. 1593 */ 1594 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1595 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1596 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1597 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1598 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1599 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1600 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1601 1602 /* Set random backoff seed for TX */ 1603 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1604 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1605 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1606 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1607 BGE_TX_BACKOFF_SEED_MASK); 1608 1609 /* Set inter-packet gap */ 1610 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1611 1612 /* 1613 * Specify which ring to use for packets that don't match 1614 * any RX rules. 1615 */ 1616 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1617 1618 /* 1619 * Configure number of RX lists. One interrupt distribution 1620 * list, sixteen active lists, one bad frames class. 1621 */ 1622 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1623 1624 /* Inialize RX list placement stats mask. */ 1625 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1626 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1627 1628 /* Disable host coalescing until we get it set up */ 1629 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1630 1631 /* Poll to make sure it's shut down. */ 1632 for (i = 0; i < BGE_TIMEOUT; i++) { 1633 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1634 break; 1635 DELAY(10); 1636 } 1637 1638 if (i == BGE_TIMEOUT) { 1639 printf("%s: host coalescing engine failed to idle\n", 1640 sc->bge_dev.dv_xname); 1641 return(ENXIO); 1642 } 1643 1644 /* Set up host coalescing defaults */ 1645 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1646 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1647 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1648 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1649 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1650 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1651 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1652 } 1653 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1654 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1655 1656 /* Set up address of statistics block */ 1657 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1658 bge_set_hostaddr(&taddr, 1659 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1660 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1661 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1662 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1663 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1664 } 1665 1666 /* Set up address of status block */ 1667 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1668 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1669 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1670 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1671 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1672 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1673 1674 /* Turn on host coalescing state machine */ 1675 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1676 1677 /* Turn on RX BD completion state machine and enable attentions */ 1678 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1679 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1680 1681 /* Turn on RX list placement state machine */ 1682 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1683 1684 /* Turn on RX list selector state machine. */ 1685 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1686 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1687 } 1688 1689 /* Turn on DMA, clear stats */ 1690 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1691 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1692 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1693 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1694 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1695 1696 /* Set misc. local control, enable interrupts on attentions */ 1697 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1698 1699 #ifdef notdef 1700 /* Assert GPIO pins for PHY reset */ 1701 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1702 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1703 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1704 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1705 #endif 1706 1707 #if defined(not_quite_yet) 1708 /* Linux driver enables enable gpio pin #1 on 5700s */ 1709 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1710 sc->bge_local_ctrl_reg |= 1711 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1712 } 1713 #endif 1714 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1715 1716 /* Turn on DMA completion state machine */ 1717 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1718 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1719 } 1720 1721 /* Turn on write DMA state machine */ 1722 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1723 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1724 1725 /* Turn on read DMA state machine */ 1726 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1727 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1728 1729 /* Turn on RX data completion state machine */ 1730 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1731 1732 /* Turn on RX BD initiator state machine */ 1733 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1734 1735 /* Turn on RX data and RX BD initiator state machine */ 1736 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1737 1738 /* Turn on Mbuf cluster free state machine */ 1739 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1740 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1741 } 1742 1743 /* Turn on send BD completion state machine */ 1744 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1745 1746 /* Turn on send data completion state machine */ 1747 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1748 1749 /* Turn on send data initiator state machine */ 1750 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1751 1752 /* Turn on send BD initiator state machine */ 1753 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1754 1755 /* Turn on send BD selector state machine */ 1756 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1757 1758 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1759 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1760 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1761 1762 /* ack/clear link change events */ 1763 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1764 BGE_MACSTAT_CFG_CHANGED); 1765 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1766 1767 /* Enable PHY auto polling (for MII/GMII only) */ 1768 if (sc->bge_tbi) { 1769 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1770 } else { 1771 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1772 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1773 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1774 BGE_EVTENB_MI_INTERRUPT); 1775 } 1776 1777 /* Enable link state change attentions. */ 1778 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1779 1780 return(0); 1781 } 1782 1783 static const struct bge_revision { 1784 uint32_t br_chipid; 1785 uint32_t br_quirks; 1786 const char *br_name; 1787 } bge_revisions[] = { 1788 { BGE_CHIPID_BCM5700_A0, 1789 BGE_QUIRK_LINK_STATE_BROKEN, 1790 "BCM5700 A0" }, 1791 1792 { BGE_CHIPID_BCM5700_A1, 1793 BGE_QUIRK_LINK_STATE_BROKEN, 1794 "BCM5700 A1" }, 1795 1796 { BGE_CHIPID_BCM5700_B0, 1797 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1798 "BCM5700 B0" }, 1799 1800 { BGE_CHIPID_BCM5700_B1, 1801 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1802 "BCM5700 B1" }, 1803 1804 { BGE_CHIPID_BCM5700_B2, 1805 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1806 "BCM5700 B2" }, 1807 1808 /* This is treated like a BCM5700 Bx */ 1809 { BGE_CHIPID_BCM5700_ALTIMA, 1810 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1811 "BCM5700 Altima" }, 1812 1813 { BGE_CHIPID_BCM5700_C0, 1814 0, 1815 "BCM5700 C0" }, 1816 1817 { BGE_CHIPID_BCM5701_A0, 1818 0, /*XXX really, just not known */ 1819 "BCM5701 A0" }, 1820 1821 { BGE_CHIPID_BCM5701_B0, 1822 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1823 "BCM5701 B0" }, 1824 1825 { BGE_CHIPID_BCM5701_B2, 1826 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1827 "BCM5701 B2" }, 1828 1829 { BGE_CHIPID_BCM5701_B5, 1830 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1831 "BCM5701 B5" }, 1832 1833 { BGE_CHIPID_BCM5703_A0, 1834 0, 1835 "BCM5703 A0" }, 1836 1837 { BGE_CHIPID_BCM5703_A1, 1838 0, 1839 "BCM5703 A1" }, 1840 1841 { BGE_CHIPID_BCM5703_A2, 1842 BGE_QUIRK_ONLY_PHY_1, 1843 "BCM5703 A2" }, 1844 1845 { BGE_CHIPID_BCM5703_A3, 1846 BGE_QUIRK_ONLY_PHY_1, 1847 "BCM5703 A3" }, 1848 1849 { BGE_CHIPID_BCM5704_A0, 1850 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1851 "BCM5704 A0" }, 1852 1853 { BGE_CHIPID_BCM5704_A1, 1854 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1855 "BCM5704 A1" }, 1856 1857 { BGE_CHIPID_BCM5704_A2, 1858 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1859 "BCM5704 A2" }, 1860 1861 { BGE_CHIPID_BCM5704_A3, 1862 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1863 "BCM5704 A3" }, 1864 1865 { BGE_CHIPID_BCM5705_A0, 1866 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1867 "BCM5705 A0" }, 1868 1869 { BGE_CHIPID_BCM5705_A1, 1870 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1871 "BCM5705 A1" }, 1872 1873 { BGE_CHIPID_BCM5705_A2, 1874 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1875 "BCM5705 A2" }, 1876 1877 { BGE_CHIPID_BCM5705_A3, 1878 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1879 "BCM5705 A3" }, 1880 1881 { 0, 0, NULL } 1882 }; 1883 1884 /* 1885 * Some defaults for major revisions, so that newer steppings 1886 * that we don't know about have a shot at working. 1887 */ 1888 static const struct bge_revision bge_majorrevs[] = { 1889 { BGE_ASICREV_BCM5700, 1890 BGE_QUIRK_LINK_STATE_BROKEN, 1891 "unknown BCM5700" }, 1892 1893 { BGE_ASICREV_BCM5701, 1894 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1895 "unknown BCM5701" }, 1896 1897 { BGE_ASICREV_BCM5703, 1898 0, 1899 "unknown BCM5703" }, 1900 1901 { BGE_ASICREV_BCM5704, 1902 BGE_QUIRK_ONLY_PHY_1, 1903 "unknown BCM5704" }, 1904 1905 { BGE_ASICREV_BCM5705, 1906 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1907 "unknown BCM5705" }, 1908 1909 { 0, 1910 0, 1911 NULL } 1912 }; 1913 1914 1915 static const struct bge_revision * 1916 bge_lookup_rev(uint32_t chipid) 1917 { 1918 const struct bge_revision *br; 1919 1920 for (br = bge_revisions; br->br_name != NULL; br++) { 1921 if (br->br_chipid == chipid) 1922 return (br); 1923 } 1924 1925 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1926 if (br->br_chipid == BGE_ASICREV(chipid)) 1927 return (br); 1928 } 1929 1930 return (NULL); 1931 } 1932 1933 static const struct bge_product { 1934 pci_vendor_id_t bp_vendor; 1935 pci_product_id_t bp_product; 1936 const char *bp_name; 1937 } bge_products[] = { 1938 /* 1939 * The BCM5700 documentation seems to indicate that the hardware 1940 * still has the Alteon vendor ID burned into it, though it 1941 * should always be overridden by the value in the EEPROM. We'll 1942 * check for it anyway. 1943 */ 1944 { PCI_VENDOR_ALTEON, 1945 PCI_PRODUCT_ALTEON_BCM5700, 1946 "Broadcom BCM5700 Gigabit Ethernet", 1947 }, 1948 { PCI_VENDOR_ALTEON, 1949 PCI_PRODUCT_ALTEON_BCM5701, 1950 "Broadcom BCM5701 Gigabit Ethernet", 1951 }, 1952 1953 { PCI_VENDOR_ALTIMA, 1954 PCI_PRODUCT_ALTIMA_AC1000, 1955 "Altima AC1000 Gigabit Ethernet", 1956 }, 1957 { PCI_VENDOR_ALTIMA, 1958 PCI_PRODUCT_ALTIMA_AC1001, 1959 "Altima AC1001 Gigabit Ethernet", 1960 }, 1961 { PCI_VENDOR_ALTIMA, 1962 PCI_PRODUCT_ALTIMA_AC9100, 1963 "Altima AC9100 Gigabit Ethernet", 1964 }, 1965 1966 { PCI_VENDOR_BROADCOM, 1967 PCI_PRODUCT_BROADCOM_BCM5700, 1968 "Broadcom BCM5700 Gigabit Ethernet", 1969 }, 1970 { PCI_VENDOR_BROADCOM, 1971 PCI_PRODUCT_BROADCOM_BCM5701, 1972 "Broadcom BCM5701 Gigabit Ethernet", 1973 }, 1974 { PCI_VENDOR_BROADCOM, 1975 PCI_PRODUCT_BROADCOM_BCM5702, 1976 "Broadcom BCM5702 Gigabit Ethernet", 1977 }, 1978 { PCI_VENDOR_BROADCOM, 1979 PCI_PRODUCT_BROADCOM_BCM5702X, 1980 "Broadcom BCM5702X Gigabit Ethernet" }, 1981 1982 { PCI_VENDOR_BROADCOM, 1983 PCI_PRODUCT_BROADCOM_BCM5703, 1984 "Broadcom BCM5703 Gigabit Ethernet", 1985 }, 1986 { PCI_VENDOR_BROADCOM, 1987 PCI_PRODUCT_BROADCOM_BCM5703X, 1988 "Broadcom BCM5703X Gigabit Ethernet", 1989 }, 1990 { PCI_VENDOR_BROADCOM, 1991 PCI_PRODUCT_BROADCOM_BCM5703A3, 1992 "Broadcom BCM5703A3 Gigabit Ethernet", 1993 }, 1994 1995 { PCI_VENDOR_BROADCOM, 1996 PCI_PRODUCT_BROADCOM_BCM5704C, 1997 "Broadcom BCM5704C Dual Gigabit Ethernet", 1998 }, 1999 { PCI_VENDOR_BROADCOM, 2000 PCI_PRODUCT_BROADCOM_BCM5704S, 2001 "Broadcom BCM5704S Dual Gigabit Ethernet", 2002 }, 2003 2004 { PCI_VENDOR_BROADCOM, 2005 PCI_PRODUCT_BROADCOM_BCM5705, 2006 "Broadcom BCM5705 Gigabit Ethernet", 2007 }, 2008 { PCI_VENDOR_BROADCOM, 2009 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 2010 "Broadcom BCM5705 Gigabit Ethernet", 2011 }, 2012 { PCI_VENDOR_BROADCOM, 2013 PCI_PRODUCT_BROADCOM_BCM5705M, 2014 "Broadcom BCM5705M Gigabit Ethernet", 2015 }, 2016 2017 { PCI_VENDOR_BROADCOM, 2018 PCI_PRODUCT_BROADCOM_BCM5901, 2019 "Broadcom BCM5901 Fast Ethernet", 2020 }, 2021 { PCI_VENDOR_BROADCOM, 2022 PCI_PRODUCT_BROADCOM_BCM5901A2, 2023 "Broadcom BCM5901A2 Fast Ethernet", 2024 }, 2025 2026 { PCI_VENDOR_BROADCOM, 2027 PCI_PRODUCT_BROADCOM_BCM5782, 2028 "Broadcom BCM5782 Gigabit Ethernet", 2029 }, 2030 2031 { PCI_VENDOR_SCHNEIDERKOCH, 2032 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2033 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2034 }, 2035 2036 { PCI_VENDOR_3COM, 2037 PCI_PRODUCT_3COM_3C996, 2038 "3Com 3c996 Gigabit Ethernet", 2039 }, 2040 2041 { 0, 2042 0, 2043 NULL }, 2044 }; 2045 2046 static const struct bge_product * 2047 bge_lookup(const struct pci_attach_args *pa) 2048 { 2049 const struct bge_product *bp; 2050 2051 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2052 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2053 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2054 return (bp); 2055 } 2056 2057 return (NULL); 2058 } 2059 2060 int 2061 bge_setpowerstate(sc, powerlevel) 2062 struct bge_softc *sc; 2063 int powerlevel; 2064 { 2065 #ifdef NOTYET 2066 u_int32_t pm_ctl = 0; 2067 2068 /* XXX FIXME: make sure indirect accesses enabled? */ 2069 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2070 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2071 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2072 2073 /* clear the PME_assert bit and power state bits, enable PME */ 2074 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2075 pm_ctl &= ~PCIM_PSTAT_DMASK; 2076 pm_ctl |= (1 << 8); 2077 2078 if (powerlevel == 0) { 2079 pm_ctl |= PCIM_PSTAT_D0; 2080 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2081 pm_ctl, 2); 2082 DELAY(10000); 2083 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2084 DELAY(10000); 2085 2086 #ifdef NOTYET 2087 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2088 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2089 #endif 2090 DELAY(40); DELAY(40); DELAY(40); 2091 DELAY(10000); /* above not quite adequate on 5700 */ 2092 return 0; 2093 } 2094 2095 2096 /* 2097 * Entering ACPI power states D1-D3 is achieved by wiggling 2098 * GMII gpio pins. Example code assumes all hardware vendors 2099 * followed Broadom's sample pcb layout. Until we verify that 2100 * for all supported OEM cards, states D1-D3 are unsupported. 2101 */ 2102 printf("%s: power state %d unimplemented; check GPIO pins\n", 2103 sc->bge_dev.dv_xname, powerlevel); 2104 #endif 2105 return EOPNOTSUPP; 2106 } 2107 2108 2109 /* 2110 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2111 * against our list and return its name if we find a match. Note 2112 * that since the Broadcom controller contains VPD support, we 2113 * can get the device name string from the controller itself instead 2114 * of the compiled-in string. This is a little slow, but it guarantees 2115 * we'll always announce the right product name. 2116 */ 2117 int 2118 bge_probe(parent, match, aux) 2119 struct device *parent; 2120 struct cfdata *match; 2121 void *aux; 2122 { 2123 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2124 2125 if (bge_lookup(pa) != NULL) 2126 return (1); 2127 2128 return (0); 2129 } 2130 2131 void 2132 bge_attach(parent, self, aux) 2133 struct device *parent, *self; 2134 void *aux; 2135 { 2136 struct bge_softc *sc = (struct bge_softc *)self; 2137 struct pci_attach_args *pa = aux; 2138 const struct bge_product *bp; 2139 const struct bge_revision *br; 2140 pci_chipset_tag_t pc = pa->pa_pc; 2141 pci_intr_handle_t ih; 2142 const char *intrstr = NULL; 2143 bus_dma_segment_t seg; 2144 int rseg; 2145 u_int32_t hwcfg = 0; 2146 u_int32_t mac_addr = 0; 2147 u_int32_t command; 2148 struct ifnet *ifp; 2149 caddr_t kva; 2150 u_char eaddr[ETHER_ADDR_LEN]; 2151 pcireg_t memtype; 2152 bus_addr_t memaddr; 2153 bus_size_t memsize; 2154 u_int32_t pm_ctl; 2155 2156 bp = bge_lookup(pa); 2157 KASSERT(bp != NULL); 2158 2159 sc->bge_pa = *pa; 2160 2161 aprint_naive(": Ethernet controller\n"); 2162 aprint_normal(": %s\n", bp->bp_name); 2163 2164 /* 2165 * Map control/status registers. 2166 */ 2167 DPRINTFN(5, ("Map control/status regs\n")); 2168 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2169 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2170 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2171 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2172 2173 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2174 aprint_error("%s: failed to enable memory mapping!\n", 2175 sc->bge_dev.dv_xname); 2176 return; 2177 } 2178 2179 DPRINTFN(5, ("pci_mem_find\n")); 2180 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2181 switch (memtype) { 2182 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2183 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2184 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2185 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2186 &memaddr, &memsize) == 0) 2187 break; 2188 default: 2189 aprint_error("%s: can't find mem space\n", 2190 sc->bge_dev.dv_xname); 2191 return; 2192 } 2193 2194 DPRINTFN(5, ("pci_intr_map\n")); 2195 if (pci_intr_map(pa, &ih)) { 2196 aprint_error("%s: couldn't map interrupt\n", 2197 sc->bge_dev.dv_xname); 2198 return; 2199 } 2200 2201 DPRINTFN(5, ("pci_intr_string\n")); 2202 intrstr = pci_intr_string(pc, ih); 2203 2204 DPRINTFN(5, ("pci_intr_establish\n")); 2205 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2206 2207 if (sc->bge_intrhand == NULL) { 2208 aprint_error("%s: couldn't establish interrupt", 2209 sc->bge_dev.dv_xname); 2210 if (intrstr != NULL) 2211 aprint_normal(" at %s", intrstr); 2212 aprint_normal("\n"); 2213 return; 2214 } 2215 aprint_normal("%s: interrupting at %s\n", 2216 sc->bge_dev.dv_xname, intrstr); 2217 2218 /* 2219 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2220 * can clobber the chip's PCI config-space power control registers, 2221 * leaving the card in D3 powersave state. 2222 * We do not have memory-mapped registers in this state, 2223 * so force device into D0 state before starting initialization. 2224 */ 2225 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2226 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2227 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2228 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2229 DELAY(1000); /* 27 usec is allegedly sufficent */ 2230 2231 /* Try to reset the chip. */ 2232 DPRINTFN(5, ("bge_reset\n")); 2233 bge_reset(sc); 2234 2235 if (bge_chipinit(sc)) { 2236 aprint_error("%s: chip initialization failed\n", 2237 sc->bge_dev.dv_xname); 2238 bge_release_resources(sc); 2239 return; 2240 } 2241 2242 /* 2243 * Get station address from the EEPROM. 2244 */ 2245 mac_addr = bge_readmem_ind(sc, 0x0c14); 2246 if ((mac_addr >> 16) == 0x484b) { 2247 eaddr[0] = (u_char)(mac_addr >> 8); 2248 eaddr[1] = (u_char)(mac_addr >> 0); 2249 mac_addr = bge_readmem_ind(sc, 0x0c18); 2250 eaddr[2] = (u_char)(mac_addr >> 24); 2251 eaddr[3] = (u_char)(mac_addr >> 16); 2252 eaddr[4] = (u_char)(mac_addr >> 8); 2253 eaddr[5] = (u_char)(mac_addr >> 0); 2254 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2255 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2256 aprint_error("%s: failed to read station address\n", 2257 sc->bge_dev.dv_xname); 2258 bge_release_resources(sc); 2259 return; 2260 } 2261 2262 /* 2263 * Save ASIC rev. Look up any quirks associated with this 2264 * ASIC. 2265 */ 2266 sc->bge_chipid = 2267 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2268 BGE_PCIMISCCTL_ASICREV; 2269 br = bge_lookup_rev(sc->bge_chipid); 2270 2271 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2272 2273 if (br == NULL) { 2274 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2275 sc->bge_quirks = 0; 2276 } else { 2277 aprint_normal("ASIC %s (0x%04x)", 2278 br->br_name, sc->bge_chipid >> 16); 2279 sc->bge_quirks |= br->br_quirks; 2280 } 2281 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2282 2283 /* Allocate the general information block and ring buffers. */ 2284 if (pci_dma64_available(pa)) 2285 sc->bge_dmatag = pa->pa_dmat64; 2286 else 2287 sc->bge_dmatag = pa->pa_dmat; 2288 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2289 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2290 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2291 aprint_error("%s: can't alloc rx buffers\n", 2292 sc->bge_dev.dv_xname); 2293 return; 2294 } 2295 DPRINTFN(5, ("bus_dmamem_map\n")); 2296 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2297 sizeof(struct bge_ring_data), &kva, 2298 BUS_DMA_NOWAIT)) { 2299 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2300 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2301 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2302 return; 2303 } 2304 DPRINTFN(5, ("bus_dmamem_create\n")); 2305 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2306 sizeof(struct bge_ring_data), 0, 2307 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2308 aprint_error("%s: can't create DMA map\n", 2309 sc->bge_dev.dv_xname); 2310 bus_dmamem_unmap(sc->bge_dmatag, kva, 2311 sizeof(struct bge_ring_data)); 2312 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2313 return; 2314 } 2315 DPRINTFN(5, ("bus_dmamem_load\n")); 2316 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2317 sizeof(struct bge_ring_data), NULL, 2318 BUS_DMA_NOWAIT)) { 2319 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2320 bus_dmamem_unmap(sc->bge_dmatag, kva, 2321 sizeof(struct bge_ring_data)); 2322 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2323 return; 2324 } 2325 2326 DPRINTFN(5, ("bzero\n")); 2327 sc->bge_rdata = (struct bge_ring_data *)kva; 2328 2329 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2330 2331 /* Try to allocate memory for jumbo buffers. */ 2332 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2333 if (bge_alloc_jumbo_mem(sc)) { 2334 aprint_error("%s: jumbo buffer allocation failed\n", 2335 sc->bge_dev.dv_xname); 2336 } else 2337 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2338 } 2339 2340 /* Set default tuneable values. */ 2341 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2342 sc->bge_rx_coal_ticks = 150; 2343 sc->bge_rx_max_coal_bds = 64; 2344 #ifdef ORIG_WPAUL_VALUES 2345 sc->bge_tx_coal_ticks = 150; 2346 sc->bge_tx_max_coal_bds = 128; 2347 #else 2348 sc->bge_tx_coal_ticks = 300; 2349 sc->bge_tx_max_coal_bds = 400; 2350 #endif 2351 2352 /* Set up ifnet structure */ 2353 ifp = &sc->ethercom.ec_if; 2354 ifp->if_softc = sc; 2355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2356 ifp->if_ioctl = bge_ioctl; 2357 ifp->if_start = bge_start; 2358 ifp->if_init = bge_init; 2359 ifp->if_watchdog = bge_watchdog; 2360 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2361 IFQ_SET_READY(&ifp->if_snd); 2362 DPRINTFN(5, ("bcopy\n")); 2363 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2364 2365 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2366 sc->ethercom.ec_if.if_capabilities |= 2367 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 2368 sc->ethercom.ec_capabilities |= 2369 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2370 2371 /* 2372 * Do MII setup. 2373 */ 2374 DPRINTFN(5, ("mii setup\n")); 2375 sc->bge_mii.mii_ifp = ifp; 2376 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2377 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2378 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2379 2380 /* 2381 * Figure out what sort of media we have by checking the 2382 * hardware config word in the first 32k of NIC internal memory, 2383 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2384 * cards, this value appears to be unset. If that's the 2385 * case, we have to rely on identifying the NIC by its PCI 2386 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2387 */ 2388 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2389 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2390 } else { 2391 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2392 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2393 hwcfg = be32toh(hwcfg); 2394 } 2395 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2396 sc->bge_tbi = 1; 2397 2398 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2399 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2400 SK_SUBSYSID_9D41) 2401 sc->bge_tbi = 1; 2402 2403 if (sc->bge_tbi) { 2404 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2405 bge_ifmedia_sts); 2406 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2407 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2408 0, NULL); 2409 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2410 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2411 } else { 2412 /* 2413 * Do transceiver setup. 2414 */ 2415 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2416 bge_ifmedia_sts); 2417 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2418 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 2419 2420 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2421 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2422 ifmedia_add(&sc->bge_mii.mii_media, 2423 IFM_ETHER|IFM_MANUAL, 0, NULL); 2424 ifmedia_set(&sc->bge_mii.mii_media, 2425 IFM_ETHER|IFM_MANUAL); 2426 } else 2427 ifmedia_set(&sc->bge_mii.mii_media, 2428 IFM_ETHER|IFM_AUTO); 2429 } 2430 2431 /* 2432 * When using the BCM5701 in PCI-X mode, data corruption has 2433 * been observed in the first few bytes of some received packets. 2434 * Aligning the packet buffer in memory eliminates the corruption. 2435 * Unfortunately, this misaligns the packet payloads. On platforms 2436 * which do not support unaligned accesses, we will realign the 2437 * payloads by copying the received packets. 2438 */ 2439 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2440 /* If in PCI-X mode, work around the alignment bug. */ 2441 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2442 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2443 BGE_PCISTATE_PCI_BUSSPEED) 2444 sc->bge_rx_alignment_bug = 1; 2445 } 2446 2447 /* 2448 * Call MI attach routine. 2449 */ 2450 DPRINTFN(5, ("if_attach\n")); 2451 if_attach(ifp); 2452 DPRINTFN(5, ("ether_ifattach\n")); 2453 ether_ifattach(ifp, eaddr); 2454 DPRINTFN(5, ("callout_init\n")); 2455 callout_init(&sc->bge_timeout); 2456 } 2457 2458 void 2459 bge_release_resources(sc) 2460 struct bge_softc *sc; 2461 { 2462 if (sc->bge_vpd_prodname != NULL) 2463 free(sc->bge_vpd_prodname, M_DEVBUF); 2464 2465 if (sc->bge_vpd_readonly != NULL) 2466 free(sc->bge_vpd_readonly, M_DEVBUF); 2467 } 2468 2469 void 2470 bge_reset(sc) 2471 struct bge_softc *sc; 2472 { 2473 struct pci_attach_args *pa = &sc->bge_pa; 2474 u_int32_t cachesize, command, pcistate, new_pcistate; 2475 int i, val = 0; 2476 2477 /* Save some important PCI state. */ 2478 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2479 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2480 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2481 2482 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2483 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2484 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2485 2486 /* Issue global reset */ 2487 bge_writereg_ind(sc, BGE_MISC_CFG, 2488 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2489 2490 DELAY(1000); 2491 2492 /* Reset some of the PCI state that got zapped by reset */ 2493 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2494 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2495 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2496 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2497 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2498 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2499 2500 /* Enable memory arbiter. */ 2501 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2502 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2503 } 2504 2505 /* 2506 * Prevent PXE restart: write a magic number to the 2507 * general communications memory at 0xB50. 2508 */ 2509 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2510 2511 /* 2512 * Poll the value location we just wrote until 2513 * we see the 1's complement of the magic number. 2514 * This indicates that the firmware initialization 2515 * is complete. 2516 */ 2517 for (i = 0; i < 750; i++) { 2518 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2519 if (val == ~BGE_MAGIC_NUMBER) 2520 break; 2521 DELAY(1000); 2522 } 2523 2524 if (i == 750) { 2525 printf("%s: firmware handshake timed out, val = %x\n", 2526 sc->bge_dev.dv_xname, val); 2527 return; 2528 } 2529 2530 /* 2531 * XXX Wait for the value of the PCISTATE register to 2532 * return to its original pre-reset state. This is a 2533 * fairly good indicator of reset completion. If we don't 2534 * wait for the reset to fully complete, trying to read 2535 * from the device's non-PCI registers may yield garbage 2536 * results. 2537 */ 2538 for (i = 0; i < BGE_TIMEOUT; i++) { 2539 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2540 BGE_PCI_PCISTATE); 2541 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2542 (pcistate & ~BGE_PCISTATE_RESERVED)) 2543 break; 2544 DELAY(10); 2545 } 2546 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2547 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2548 printf("%s: pcistate failed to revert\n", 2549 sc->bge_dev.dv_xname); 2550 } 2551 2552 /* Enable memory arbiter. */ 2553 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2554 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2555 } 2556 2557 /* Fix up byte swapping */ 2558 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2559 2560 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2561 2562 DELAY(10000); 2563 } 2564 2565 /* 2566 * Frame reception handling. This is called if there's a frame 2567 * on the receive return list. 2568 * 2569 * Note: we have to be able to handle two possibilities here: 2570 * 1) the frame is from the jumbo recieve ring 2571 * 2) the frame is from the standard receive ring 2572 */ 2573 2574 void 2575 bge_rxeof(sc) 2576 struct bge_softc *sc; 2577 { 2578 struct ifnet *ifp; 2579 int stdcnt = 0, jumbocnt = 0; 2580 int have_tag = 0; 2581 u_int16_t vlan_tag = 0; 2582 bus_dmamap_t dmamap; 2583 bus_addr_t offset, toff; 2584 bus_size_t tlen; 2585 int tosync; 2586 2587 ifp = &sc->ethercom.ec_if; 2588 2589 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2590 offsetof(struct bge_ring_data, bge_status_block), 2591 sizeof (struct bge_status_block), 2592 BUS_DMASYNC_POSTREAD); 2593 2594 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2595 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2596 sc->bge_rx_saved_considx; 2597 2598 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2599 2600 if (tosync < 0) { 2601 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2602 sizeof (struct bge_rx_bd); 2603 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2604 toff, tlen, BUS_DMASYNC_POSTREAD); 2605 tosync = -tosync; 2606 } 2607 2608 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2609 offset, tosync * sizeof (struct bge_rx_bd), 2610 BUS_DMASYNC_POSTREAD); 2611 2612 while(sc->bge_rx_saved_considx != 2613 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2614 struct bge_rx_bd *cur_rx; 2615 u_int32_t rxidx; 2616 struct mbuf *m = NULL; 2617 2618 cur_rx = &sc->bge_rdata-> 2619 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2620 2621 rxidx = cur_rx->bge_idx; 2622 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2623 2624 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2625 have_tag = 1; 2626 vlan_tag = cur_rx->bge_vlan_tag; 2627 } 2628 2629 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2630 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2631 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2632 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2633 jumbocnt++; 2634 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2635 ifp->if_ierrors++; 2636 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2637 continue; 2638 } 2639 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2640 NULL)== ENOBUFS) { 2641 ifp->if_ierrors++; 2642 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2643 continue; 2644 } 2645 } else { 2646 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2647 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2648 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2649 stdcnt++; 2650 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2651 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2652 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2653 ifp->if_ierrors++; 2654 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2655 continue; 2656 } 2657 if (bge_newbuf_std(sc, sc->bge_std, 2658 NULL, dmamap) == ENOBUFS) { 2659 ifp->if_ierrors++; 2660 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2661 continue; 2662 } 2663 } 2664 2665 ifp->if_ipackets++; 2666 #ifndef __NO_STRICT_ALIGNMENT 2667 /* 2668 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2669 * the Rx buffer has the layer-2 header unaligned. 2670 * If our CPU requires alignment, re-align by copying. 2671 */ 2672 if (sc->bge_rx_alignment_bug) { 2673 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2674 cur_rx->bge_len); 2675 m->m_data += ETHER_ALIGN; 2676 } 2677 #endif 2678 2679 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2680 m->m_pkthdr.rcvif = ifp; 2681 2682 #if NBPFILTER > 0 2683 /* 2684 * Handle BPF listeners. Let the BPF user see the packet. 2685 */ 2686 if (ifp->if_bpf) 2687 bpf_mtap(ifp->if_bpf, m); 2688 #endif 2689 2690 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 2691 2692 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2693 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2694 /* 2695 * Rx transport checksum-offload may also 2696 * have bugs with packets which, when transmitted, 2697 * were `runts' requiring padding. 2698 */ 2699 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2700 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2701 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2702 m->m_pkthdr.csum_data = 2703 cur_rx->bge_tcp_udp_csum; 2704 m->m_pkthdr.csum_flags |= 2705 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2706 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2707 } 2708 2709 /* 2710 * If we received a packet with a vlan tag, pass it 2711 * to vlan_input() instead of ether_input(). 2712 */ 2713 if (have_tag) { 2714 struct m_tag *mtag; 2715 2716 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2717 M_NOWAIT); 2718 if (mtag != NULL) { 2719 *(u_int *)(mtag + 1) = vlan_tag; 2720 m_tag_prepend(m, mtag); 2721 have_tag = vlan_tag = 0; 2722 } else { 2723 printf("%s: no mbuf for tag\n", ifp->if_xname); 2724 m_freem(m); 2725 have_tag = vlan_tag = 0; 2726 continue; 2727 } 2728 } 2729 (*ifp->if_input)(ifp, m); 2730 } 2731 2732 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2733 if (stdcnt) 2734 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2735 if (jumbocnt) 2736 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2737 } 2738 2739 void 2740 bge_txeof(sc) 2741 struct bge_softc *sc; 2742 { 2743 struct bge_tx_bd *cur_tx = NULL; 2744 struct ifnet *ifp; 2745 struct txdmamap_pool_entry *dma; 2746 bus_addr_t offset, toff; 2747 bus_size_t tlen; 2748 int tosync; 2749 struct mbuf *m; 2750 2751 ifp = &sc->ethercom.ec_if; 2752 2753 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2754 offsetof(struct bge_ring_data, bge_status_block), 2755 sizeof (struct bge_status_block), 2756 BUS_DMASYNC_POSTREAD); 2757 2758 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2759 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2760 sc->bge_tx_saved_considx; 2761 2762 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2763 2764 if (tosync < 0) { 2765 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2766 sizeof (struct bge_tx_bd); 2767 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2768 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2769 tosync = -tosync; 2770 } 2771 2772 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2773 offset, tosync * sizeof (struct bge_tx_bd), 2774 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2775 2776 /* 2777 * Go through our tx ring and free mbufs for those 2778 * frames that have been sent. 2779 */ 2780 while (sc->bge_tx_saved_considx != 2781 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2782 u_int32_t idx = 0; 2783 2784 idx = sc->bge_tx_saved_considx; 2785 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2786 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2787 ifp->if_opackets++; 2788 m = sc->bge_cdata.bge_tx_chain[idx]; 2789 if (m != NULL) { 2790 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2791 dma = sc->txdma[idx]; 2792 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2793 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2794 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2795 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2796 sc->txdma[idx] = NULL; 2797 2798 m_freem(m); 2799 } 2800 sc->bge_txcnt--; 2801 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2802 ifp->if_timer = 0; 2803 } 2804 2805 if (cur_tx != NULL) 2806 ifp->if_flags &= ~IFF_OACTIVE; 2807 } 2808 2809 int 2810 bge_intr(xsc) 2811 void *xsc; 2812 { 2813 struct bge_softc *sc; 2814 struct ifnet *ifp; 2815 2816 sc = xsc; 2817 ifp = &sc->ethercom.ec_if; 2818 2819 #ifdef notdef 2820 /* Avoid this for now -- checking this register is expensive. */ 2821 /* Make sure this is really our interrupt. */ 2822 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2823 return (0); 2824 #endif 2825 /* Ack interrupt and stop others from occuring. */ 2826 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2827 2828 /* 2829 * Process link state changes. 2830 * Grrr. The link status word in the status block does 2831 * not work correctly on the BCM5700 rev AX and BX chips, 2832 * according to all avaibable information. Hence, we have 2833 * to enable MII interrupts in order to properly obtain 2834 * async link changes. Unfortunately, this also means that 2835 * we have to read the MAC status register to detect link 2836 * changes, thereby adding an additional register access to 2837 * the interrupt handler. 2838 */ 2839 2840 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2841 u_int32_t status; 2842 2843 status = CSR_READ_4(sc, BGE_MAC_STS); 2844 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2845 sc->bge_link = 0; 2846 callout_stop(&sc->bge_timeout); 2847 bge_tick(sc); 2848 /* Clear the interrupt */ 2849 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2850 BGE_EVTENB_MI_INTERRUPT); 2851 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2852 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2853 BRGPHY_INTRS); 2854 } 2855 } else { 2856 if (sc->bge_rdata->bge_status_block.bge_status & 2857 BGE_STATFLAG_LINKSTATE_CHANGED) { 2858 sc->bge_link = 0; 2859 callout_stop(&sc->bge_timeout); 2860 bge_tick(sc); 2861 /* Clear the interrupt */ 2862 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2863 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2864 BGE_MACSTAT_LINK_CHANGED); 2865 } 2866 } 2867 2868 if (ifp->if_flags & IFF_RUNNING) { 2869 /* Check RX return ring producer/consumer */ 2870 bge_rxeof(sc); 2871 2872 /* Check TX ring producer/consumer */ 2873 bge_txeof(sc); 2874 } 2875 2876 if (sc->bge_pending_rxintr_change) { 2877 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 2878 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 2879 uint32_t junk; 2880 2881 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 2882 DELAY(10); 2883 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 2884 2885 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 2886 DELAY(10); 2887 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 2888 2889 sc->bge_pending_rxintr_change = 0; 2890 } 2891 bge_handle_events(sc); 2892 2893 /* Re-enable interrupts. */ 2894 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2895 2896 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2897 bge_start(ifp); 2898 2899 return (1); 2900 } 2901 2902 void 2903 bge_tick(xsc) 2904 void *xsc; 2905 { 2906 struct bge_softc *sc = xsc; 2907 struct mii_data *mii = &sc->bge_mii; 2908 struct ifmedia *ifm = NULL; 2909 struct ifnet *ifp = &sc->ethercom.ec_if; 2910 int s; 2911 2912 s = splnet(); 2913 2914 bge_stats_update(sc); 2915 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2916 if (sc->bge_link) { 2917 splx(s); 2918 return; 2919 } 2920 2921 if (sc->bge_tbi) { 2922 ifm = &sc->bge_ifmedia; 2923 if (CSR_READ_4(sc, BGE_MAC_STS) & 2924 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2925 sc->bge_link++; 2926 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2927 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2928 bge_start(ifp); 2929 } 2930 splx(s); 2931 return; 2932 } 2933 2934 mii_tick(mii); 2935 2936 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2937 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2938 sc->bge_link++; 2939 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2940 bge_start(ifp); 2941 } 2942 2943 splx(s); 2944 } 2945 2946 void 2947 bge_stats_update(sc) 2948 struct bge_softc *sc; 2949 { 2950 struct ifnet *ifp = &sc->ethercom.ec_if; 2951 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2952 bus_size_t rstats = BGE_RX_STATS; 2953 2954 #define READ_RSTAT(sc, stats, stat) \ 2955 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 2956 2957 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2958 ifp->if_collisions += 2959 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 2960 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 2961 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 2962 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 2963 return; 2964 } 2965 2966 #undef READ_RSTAT 2967 #define READ_STAT(sc, stats, stat) \ 2968 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2969 2970 ifp->if_collisions += 2971 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2972 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2973 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2974 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2975 ifp->if_collisions; 2976 2977 #undef READ_STAT 2978 2979 #ifdef notdef 2980 ifp->if_collisions += 2981 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2982 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2983 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2984 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2985 ifp->if_collisions; 2986 #endif 2987 } 2988 2989 /* 2990 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2991 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2992 * but when such padded frames employ the bge IP/TCP checksum offload, 2993 * the hardware checksum assist gives incorrect results (possibly 2994 * from incorporating its own padding into the UDP/TCP checksum; who knows). 2995 * If we pad such runts with zeros, the onboard checksum comes out correct. 2996 */ 2997 static __inline int 2998 bge_cksum_pad(struct mbuf *pkt) 2999 { 3000 struct mbuf *last = NULL; 3001 int padlen; 3002 3003 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3004 3005 /* if there's only the packet-header and we can pad there, use it. */ 3006 if (pkt->m_pkthdr.len == pkt->m_len && 3007 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 3008 last = pkt; 3009 } else { 3010 /* 3011 * Walk packet chain to find last mbuf. We will either 3012 * pad there, or append a new mbuf and pad it 3013 * (thus perhaps avoiding the bcm5700 dma-min bug). 3014 */ 3015 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3016 (void) 0; /* do nothing*/ 3017 } 3018 3019 /* `last' now points to last in chain. */ 3020 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 3021 (void) 0; /* we can pad here, in-place. */ 3022 } else { 3023 /* Allocate new empty mbuf, pad it. Compact later. */ 3024 struct mbuf *n; 3025 MGET(n, M_DONTWAIT, MT_DATA); 3026 n->m_len = 0; 3027 last->m_next = n; 3028 last = n; 3029 } 3030 } 3031 3032 #ifdef DEBUG 3033 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 3034 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 3035 #endif 3036 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3037 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3038 last->m_len += padlen; 3039 pkt->m_pkthdr.len += padlen; 3040 return 0; 3041 } 3042 3043 /* 3044 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3045 */ 3046 static __inline int 3047 bge_compact_dma_runt(struct mbuf *pkt) 3048 { 3049 struct mbuf *m, *prev; 3050 int totlen, prevlen; 3051 3052 prev = NULL; 3053 totlen = 0; 3054 prevlen = -1; 3055 3056 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3057 int mlen = m->m_len; 3058 int shortfall = 8 - mlen ; 3059 3060 totlen += mlen; 3061 if (mlen == 0) { 3062 continue; 3063 } 3064 if (mlen >= 8) 3065 continue; 3066 3067 /* If we get here, mbuf data is too small for DMA engine. 3068 * Try to fix by shuffling data to prev or next in chain. 3069 * If that fails, do a compacting deep-copy of the whole chain. 3070 */ 3071 3072 /* Internal frag. If fits in prev, copy it there. */ 3073 if (prev && !M_READONLY(prev) && 3074 M_TRAILINGSPACE(prev) >= m->m_len) { 3075 bcopy(m->m_data, 3076 prev->m_data+prev->m_len, 3077 mlen); 3078 prev->m_len += mlen; 3079 m->m_len = 0; 3080 /* XXX stitch chain */ 3081 prev->m_next = m_free(m); 3082 m = prev; 3083 continue; 3084 } 3085 else if (m->m_next != NULL && !M_READONLY(m) && 3086 M_TRAILINGSPACE(m) >= shortfall && 3087 m->m_next->m_len >= (8 + shortfall)) { 3088 /* m is writable and have enough data in next, pull up. */ 3089 3090 bcopy(m->m_next->m_data, 3091 m->m_data+m->m_len, 3092 shortfall); 3093 m->m_len += shortfall; 3094 m->m_next->m_len -= shortfall; 3095 m->m_next->m_data += shortfall; 3096 } 3097 else if (m->m_next == NULL || 1) { 3098 /* Got a runt at the very end of the packet. 3099 * borrow data from the tail of the preceding mbuf and 3100 * update its length in-place. (The original data is still 3101 * valid, so we can do this even if prev is not writable.) 3102 */ 3103 3104 /* if we'd make prev a runt, just move all of its data. */ 3105 #ifdef DEBUG 3106 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3107 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3108 #endif 3109 if ((prev->m_len - shortfall) < 8) 3110 shortfall = prev->m_len; 3111 3112 #ifdef notyet /* just do the safe slow thing for now */ 3113 if (!M_READONLY(m)) { 3114 if (M_LEADINGSPACE(m) < shorfall) { 3115 void *m_dat; 3116 m_dat = (m->m_flags & M_PKTHDR) ? 3117 m->m_pktdat : m->dat; 3118 memmove(m_dat, mtod(m, void*), m->m_len); 3119 m->m_data = m_dat; 3120 } 3121 } else 3122 #endif /* just do the safe slow thing */ 3123 { 3124 struct mbuf * n = NULL; 3125 int newprevlen = prev->m_len - shortfall; 3126 3127 MGET(n, M_NOWAIT, MT_DATA); 3128 if (n == NULL) 3129 return ENOBUFS; 3130 KASSERT(m->m_len + shortfall < MLEN 3131 /*, 3132 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3133 3134 /* first copy the data we're stealing from prev */ 3135 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3136 3137 /* update prev->m_len accordingly */ 3138 prev->m_len -= shortfall; 3139 3140 /* copy data from runt m */ 3141 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3142 3143 /* n holds what we stole from prev, plus m */ 3144 n->m_len = shortfall + m->m_len; 3145 3146 /* stitch n into chain and free m */ 3147 n->m_next = m->m_next; 3148 prev->m_next = n; 3149 /* KASSERT(m->m_next == NULL); */ 3150 m->m_next = NULL; 3151 m_free(m); 3152 m = n; /* for continuing loop */ 3153 } 3154 } 3155 prevlen = m->m_len; 3156 } 3157 return 0; 3158 } 3159 3160 /* 3161 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3162 * pointers to descriptors. 3163 */ 3164 int 3165 bge_encap(sc, m_head, txidx) 3166 struct bge_softc *sc; 3167 struct mbuf *m_head; 3168 u_int32_t *txidx; 3169 { 3170 struct bge_tx_bd *f = NULL; 3171 u_int32_t frag, cur, cnt = 0; 3172 u_int16_t csum_flags = 0; 3173 struct txdmamap_pool_entry *dma; 3174 bus_dmamap_t dmamap; 3175 int i = 0; 3176 struct m_tag *mtag; 3177 3178 cur = frag = *txidx; 3179 3180 if (m_head->m_pkthdr.csum_flags) { 3181 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3182 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3183 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3184 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3185 } 3186 3187 /* 3188 * If we were asked to do an outboard checksum, and the NIC 3189 * has the bug where it sometimes adds in the Ethernet padding, 3190 * explicitly pad with zeros so the cksum will be correct either way. 3191 * (For now, do this for all chip versions, until newer 3192 * are confirmed to not require the workaround.) 3193 */ 3194 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3195 #ifdef notyet 3196 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3197 #endif 3198 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3199 goto check_dma_bug; 3200 3201 if (bge_cksum_pad(m_head) != 0) 3202 return ENOBUFS; 3203 3204 check_dma_bug: 3205 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3206 goto doit; 3207 /* 3208 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3209 * less than eight bytes. If we encounter a teeny mbuf 3210 * at the end of a chain, we can pad. Otherwise, copy. 3211 */ 3212 if (bge_compact_dma_runt(m_head) != 0) 3213 return ENOBUFS; 3214 3215 doit: 3216 dma = SLIST_FIRST(&sc->txdma_list); 3217 if (dma == NULL) 3218 return ENOBUFS; 3219 dmamap = dma->dmamap; 3220 3221 /* 3222 * Start packing the mbufs in this chain into 3223 * the fragment pointers. Stop when we run out 3224 * of fragments or hit the end of the mbuf chain. 3225 */ 3226 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3227 BUS_DMA_NOWAIT)) 3228 return(ENOBUFS); 3229 3230 mtag = sc->ethercom.ec_nvlans ? 3231 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3232 3233 for (i = 0; i < dmamap->dm_nsegs; i++) { 3234 f = &sc->bge_rdata->bge_tx_ring[frag]; 3235 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3236 break; 3237 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3238 f->bge_len = dmamap->dm_segs[i].ds_len; 3239 f->bge_flags = csum_flags; 3240 3241 if (mtag != NULL) { 3242 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3243 f->bge_vlan_tag = *(u_int *)(mtag + 1); 3244 } else { 3245 f->bge_vlan_tag = 0; 3246 } 3247 /* 3248 * Sanity check: avoid coming within 16 descriptors 3249 * of the end of the ring. 3250 */ 3251 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3252 return(ENOBUFS); 3253 cur = frag; 3254 BGE_INC(frag, BGE_TX_RING_CNT); 3255 cnt++; 3256 } 3257 3258 if (i < dmamap->dm_nsegs) 3259 return ENOBUFS; 3260 3261 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3262 BUS_DMASYNC_PREWRITE); 3263 3264 if (frag == sc->bge_tx_saved_considx) 3265 return(ENOBUFS); 3266 3267 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3268 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3269 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3270 sc->txdma[cur] = dma; 3271 sc->bge_txcnt += cnt; 3272 3273 *txidx = frag; 3274 3275 return(0); 3276 } 3277 3278 /* 3279 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3280 * to the mbuf data regions directly in the transmit descriptors. 3281 */ 3282 void 3283 bge_start(ifp) 3284 struct ifnet *ifp; 3285 { 3286 struct bge_softc *sc; 3287 struct mbuf *m_head = NULL; 3288 u_int32_t prodidx = 0; 3289 int pkts = 0; 3290 3291 sc = ifp->if_softc; 3292 3293 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3294 return; 3295 3296 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3297 3298 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3299 IFQ_POLL(&ifp->if_snd, m_head); 3300 if (m_head == NULL) 3301 break; 3302 3303 #if 0 3304 /* 3305 * XXX 3306 * safety overkill. If this is a fragmented packet chain 3307 * with delayed TCP/UDP checksums, then only encapsulate 3308 * it if we have enough descriptors to handle the entire 3309 * chain at once. 3310 * (paranoia -- may not actually be needed) 3311 */ 3312 if (m_head->m_flags & M_FIRSTFRAG && 3313 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3314 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3315 m_head->m_pkthdr.csum_data + 16) { 3316 ifp->if_flags |= IFF_OACTIVE; 3317 break; 3318 } 3319 } 3320 #endif 3321 3322 /* 3323 * Pack the data into the transmit ring. If we 3324 * don't have room, set the OACTIVE flag and wait 3325 * for the NIC to drain the ring. 3326 */ 3327 if (bge_encap(sc, m_head, &prodidx)) { 3328 ifp->if_flags |= IFF_OACTIVE; 3329 break; 3330 } 3331 3332 /* now we are committed to transmit the packet */ 3333 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3334 pkts++; 3335 3336 #if NBPFILTER > 0 3337 /* 3338 * If there's a BPF listener, bounce a copy of this frame 3339 * to him. 3340 */ 3341 if (ifp->if_bpf) 3342 bpf_mtap(ifp->if_bpf, m_head); 3343 #endif 3344 } 3345 if (pkts == 0) 3346 return; 3347 3348 /* Transmit */ 3349 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3350 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3351 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3352 3353 /* 3354 * Set a timeout in case the chip goes out to lunch. 3355 */ 3356 ifp->if_timer = 5; 3357 } 3358 3359 int 3360 bge_init(ifp) 3361 struct ifnet *ifp; 3362 { 3363 struct bge_softc *sc = ifp->if_softc; 3364 u_int16_t *m; 3365 int s, error; 3366 3367 s = splnet(); 3368 3369 ifp = &sc->ethercom.ec_if; 3370 3371 /* Cancel pending I/O and flush buffers. */ 3372 bge_stop(sc); 3373 bge_reset(sc); 3374 bge_chipinit(sc); 3375 3376 /* 3377 * Init the various state machines, ring 3378 * control blocks and firmware. 3379 */ 3380 error = bge_blockinit(sc); 3381 if (error != 0) { 3382 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3383 error); 3384 splx(s); 3385 return error; 3386 } 3387 3388 ifp = &sc->ethercom.ec_if; 3389 3390 /* Specify MTU. */ 3391 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3392 ETHER_HDR_LEN + ETHER_CRC_LEN); 3393 3394 /* Load our MAC address. */ 3395 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3396 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3397 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3398 3399 /* Enable or disable promiscuous mode as needed. */ 3400 if (ifp->if_flags & IFF_PROMISC) { 3401 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3402 } else { 3403 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3404 } 3405 3406 /* Program multicast filter. */ 3407 bge_setmulti(sc); 3408 3409 /* Init RX ring. */ 3410 bge_init_rx_ring_std(sc); 3411 3412 /* Init jumbo RX ring. */ 3413 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3414 bge_init_rx_ring_jumbo(sc); 3415 3416 /* Init our RX return ring index */ 3417 sc->bge_rx_saved_considx = 0; 3418 3419 /* Init TX ring. */ 3420 bge_init_tx_ring(sc); 3421 3422 /* Turn on transmitter */ 3423 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3424 3425 /* Turn on receiver */ 3426 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3427 3428 /* Tell firmware we're alive. */ 3429 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3430 3431 /* Enable host interrupts. */ 3432 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3433 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3434 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3435 3436 bge_ifmedia_upd(ifp); 3437 3438 ifp->if_flags |= IFF_RUNNING; 3439 ifp->if_flags &= ~IFF_OACTIVE; 3440 3441 splx(s); 3442 3443 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3444 3445 return 0; 3446 } 3447 3448 /* 3449 * Set media options. 3450 */ 3451 int 3452 bge_ifmedia_upd(ifp) 3453 struct ifnet *ifp; 3454 { 3455 struct bge_softc *sc = ifp->if_softc; 3456 struct mii_data *mii = &sc->bge_mii; 3457 struct ifmedia *ifm = &sc->bge_ifmedia; 3458 3459 /* If this is a 1000baseX NIC, enable the TBI port. */ 3460 if (sc->bge_tbi) { 3461 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3462 return(EINVAL); 3463 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3464 case IFM_AUTO: 3465 break; 3466 case IFM_1000_SX: 3467 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3468 BGE_CLRBIT(sc, BGE_MAC_MODE, 3469 BGE_MACMODE_HALF_DUPLEX); 3470 } else { 3471 BGE_SETBIT(sc, BGE_MAC_MODE, 3472 BGE_MACMODE_HALF_DUPLEX); 3473 } 3474 break; 3475 default: 3476 return(EINVAL); 3477 } 3478 return(0); 3479 } 3480 3481 sc->bge_link = 0; 3482 mii_mediachg(mii); 3483 3484 return(0); 3485 } 3486 3487 /* 3488 * Report current media status. 3489 */ 3490 void 3491 bge_ifmedia_sts(ifp, ifmr) 3492 struct ifnet *ifp; 3493 struct ifmediareq *ifmr; 3494 { 3495 struct bge_softc *sc = ifp->if_softc; 3496 struct mii_data *mii = &sc->bge_mii; 3497 3498 if (sc->bge_tbi) { 3499 ifmr->ifm_status = IFM_AVALID; 3500 ifmr->ifm_active = IFM_ETHER; 3501 if (CSR_READ_4(sc, BGE_MAC_STS) & 3502 BGE_MACSTAT_TBI_PCS_SYNCHED) 3503 ifmr->ifm_status |= IFM_ACTIVE; 3504 ifmr->ifm_active |= IFM_1000_SX; 3505 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3506 ifmr->ifm_active |= IFM_HDX; 3507 else 3508 ifmr->ifm_active |= IFM_FDX; 3509 return; 3510 } 3511 3512 mii_pollstat(mii); 3513 ifmr->ifm_active = mii->mii_media_active; 3514 ifmr->ifm_status = mii->mii_media_status; 3515 } 3516 3517 int 3518 bge_ioctl(ifp, command, data) 3519 struct ifnet *ifp; 3520 u_long command; 3521 caddr_t data; 3522 { 3523 struct bge_softc *sc = ifp->if_softc; 3524 struct ifreq *ifr = (struct ifreq *) data; 3525 int s, error = 0; 3526 struct mii_data *mii; 3527 3528 s = splnet(); 3529 3530 switch(command) { 3531 case SIOCSIFFLAGS: 3532 if (ifp->if_flags & IFF_UP) { 3533 /* 3534 * If only the state of the PROMISC flag changed, 3535 * then just use the 'set promisc mode' command 3536 * instead of reinitializing the entire NIC. Doing 3537 * a full re-init means reloading the firmware and 3538 * waiting for it to start up, which may take a 3539 * second or two. 3540 */ 3541 if (ifp->if_flags & IFF_RUNNING && 3542 ifp->if_flags & IFF_PROMISC && 3543 !(sc->bge_if_flags & IFF_PROMISC)) { 3544 BGE_SETBIT(sc, BGE_RX_MODE, 3545 BGE_RXMODE_RX_PROMISC); 3546 } else if (ifp->if_flags & IFF_RUNNING && 3547 !(ifp->if_flags & IFF_PROMISC) && 3548 sc->bge_if_flags & IFF_PROMISC) { 3549 BGE_CLRBIT(sc, BGE_RX_MODE, 3550 BGE_RXMODE_RX_PROMISC); 3551 } else 3552 bge_init(ifp); 3553 } else { 3554 if (ifp->if_flags & IFF_RUNNING) { 3555 bge_stop(sc); 3556 } 3557 } 3558 sc->bge_if_flags = ifp->if_flags; 3559 error = 0; 3560 break; 3561 case SIOCSIFMEDIA: 3562 case SIOCGIFMEDIA: 3563 if (sc->bge_tbi) { 3564 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3565 command); 3566 } else { 3567 mii = &sc->bge_mii; 3568 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3569 command); 3570 } 3571 error = 0; 3572 break; 3573 default: 3574 error = ether_ioctl(ifp, command, data); 3575 if (error == ENETRESET) { 3576 bge_setmulti(sc); 3577 error = 0; 3578 } 3579 break; 3580 } 3581 3582 splx(s); 3583 3584 return(error); 3585 } 3586 3587 void 3588 bge_watchdog(ifp) 3589 struct ifnet *ifp; 3590 { 3591 struct bge_softc *sc; 3592 3593 sc = ifp->if_softc; 3594 3595 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3596 3597 ifp->if_flags &= ~IFF_RUNNING; 3598 bge_init(ifp); 3599 3600 ifp->if_oerrors++; 3601 } 3602 3603 static void 3604 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3605 { 3606 int i; 3607 3608 BGE_CLRBIT(sc, reg, bit); 3609 3610 for (i = 0; i < BGE_TIMEOUT; i++) { 3611 if ((CSR_READ_4(sc, reg) & bit) == 0) 3612 return; 3613 delay(100); 3614 } 3615 3616 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3617 sc->bge_dev.dv_xname, (u_long) reg, bit); 3618 } 3619 3620 /* 3621 * Stop the adapter and free any mbufs allocated to the 3622 * RX and TX lists. 3623 */ 3624 void 3625 bge_stop(sc) 3626 struct bge_softc *sc; 3627 { 3628 struct ifnet *ifp = &sc->ethercom.ec_if; 3629 3630 callout_stop(&sc->bge_timeout); 3631 3632 /* 3633 * Disable all of the receiver blocks 3634 */ 3635 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3636 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3637 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3638 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3639 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3640 } 3641 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3642 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3643 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3644 3645 /* 3646 * Disable all of the transmit blocks 3647 */ 3648 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3649 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3650 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3651 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3652 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3653 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3654 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3655 } 3656 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3657 3658 /* 3659 * Shut down all of the memory managers and related 3660 * state machines. 3661 */ 3662 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3663 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3664 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3665 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3666 } 3667 3668 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3669 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3670 3671 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3672 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3673 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3674 } 3675 3676 /* Disable host interrupts. */ 3677 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3678 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3679 3680 /* 3681 * Tell firmware we're shutting down. 3682 */ 3683 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3684 3685 /* Free the RX lists. */ 3686 bge_free_rx_ring_std(sc); 3687 3688 /* Free jumbo RX list. */ 3689 bge_free_rx_ring_jumbo(sc); 3690 3691 /* Free TX buffers. */ 3692 bge_free_tx_ring(sc); 3693 3694 /* 3695 * Isolate/power down the PHY. 3696 */ 3697 if (!sc->bge_tbi) 3698 mii_down(&sc->bge_mii); 3699 3700 sc->bge_link = 0; 3701 3702 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3703 3704 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3705 } 3706 3707 /* 3708 * Stop all chip I/O so that the kernel's probe routines don't 3709 * get confused by errant DMAs when rebooting. 3710 */ 3711 void 3712 bge_shutdown(xsc) 3713 void *xsc; 3714 { 3715 struct bge_softc *sc = (struct bge_softc *)xsc; 3716 3717 bge_stop(sc); 3718 bge_reset(sc); 3719 } 3720
Indexes created Tue Sep 23 07:09:52 GMT 2025