if_bge.c revision 1.9
1 /* $NetBSD: if_bge.c,v 1.9 2002/06/28 01:10:06 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 40 * 41 * Written by Bill Paul <wpaul (at) windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include "bpfilter.h" 76 #include "vlan.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/sockio.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/device.h> 86 #include <sys/socket.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 #include <net/if_ether.h> 92 93 #ifdef INET 94 #include <netinet/in.h> 95 #include <netinet/in_systm.h> 96 #include <netinet/in_var.h> 97 #include <netinet/ip.h> 98 #endif 99 100 #if NBPFILTER > 0 101 #include <net/bpf.h> 102 #endif 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 #include <dev/mii/miidevs.h> 111 #include <dev/mii/brgphyreg.h> 112 113 #include <dev/pci/if_bgereg.h> 114 115 #include <uvm/uvm_extern.h> 116 117 /* #define BGE_CHECKSUM */ 118 119 int bge_probe(struct device *, struct cfdata *, void *); 120 void bge_attach(struct device *, struct device *, void *); 121 void bge_release_resources(struct bge_softc *); 122 void bge_txeof(struct bge_softc *); 123 void bge_rxeof(struct bge_softc *); 124 125 void bge_tick(void *); 126 void bge_stats_update(struct bge_softc *); 127 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 128 129 int bge_intr(void *); 130 void bge_start(struct ifnet *); 131 int bge_ioctl(struct ifnet *, u_long, caddr_t); 132 int bge_init(struct ifnet *); 133 void bge_stop(struct bge_softc *); 134 void bge_watchdog(struct ifnet *); 135 void bge_shutdown(void *); 136 int bge_ifmedia_upd(struct ifnet *); 137 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 138 139 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 140 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 141 142 u_int32_t bge_crc(struct bge_softc *, caddr_t); 143 void bge_setmulti(struct bge_softc *); 144 145 void bge_handle_events(struct bge_softc *); 146 int bge_alloc_jumbo_mem(struct bge_softc *); 147 void bge_free_jumbo_mem(struct bge_softc *); 148 void *bge_jalloc(struct bge_softc *); 149 void bge_jfree(struct mbuf *, caddr_t, u_int, void *); 150 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 151 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 152 int bge_init_rx_ring_std(struct bge_softc *); 153 void bge_free_rx_ring_std(struct bge_softc *); 154 int bge_init_rx_ring_jumbo(struct bge_softc *); 155 void bge_free_rx_ring_jumbo(struct bge_softc *); 156 void bge_free_tx_ring(struct bge_softc *); 157 int bge_init_tx_ring(struct bge_softc *); 158 159 int bge_chipinit(struct bge_softc *); 160 int bge_blockinit(struct bge_softc *); 161 162 #ifdef notdef 163 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 164 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 165 void bge_vpd_read(struct bge_softc *); 166 #endif 167 168 u_int32_t bge_readmem_ind(struct bge_softc *, int); 169 void bge_writemem_ind(struct bge_softc *, int, int); 170 #ifdef notdef 171 u_int32_t bge_readreg_ind(struct bge_softc *, int); 172 #endif 173 void bge_writereg_ind(struct bge_softc *, int, int); 174 175 int bge_miibus_readreg(struct device *, int, int); 176 void bge_miibus_writereg(struct device *, int, int, int); 177 void bge_miibus_statchg(struct device *); 178 179 void bge_reset(struct bge_softc *); 180 void bge_phy_hack(struct bge_softc *); 181 182 void bge_dump_status(struct bge_softc *); 183 void bge_dump_rxbd(struct bge_rx_bd *); 184 185 #define BGE_DEBUG 186 #ifdef BGE_DEBUG 187 #define DPRINTF(x) if (bgedebug) printf x 188 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 189 int bgedebug = 0; 190 #else 191 #define DPRINTF(x) 192 #define DPRINTFN(n,x) 193 #endif 194 195 struct cfattach bge_ca = { 196 sizeof(struct bge_softc), bge_probe, bge_attach 197 }; 198 199 u_int32_t 200 bge_readmem_ind(sc, off) 201 struct bge_softc *sc; 202 int off; 203 { 204 struct pci_attach_args *pa = &(sc->bge_pa); 205 pcireg_t val; 206 207 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 208 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 209 return val; 210 } 211 212 void 213 bge_writemem_ind(sc, off, val) 214 struct bge_softc *sc; 215 int off, val; 216 { 217 struct pci_attach_args *pa = &(sc->bge_pa); 218 219 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 220 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 221 } 222 223 #ifdef notdef 224 u_int32_t 225 bge_readreg_ind(sc, off) 226 struct bge_softc *sc; 227 int off; 228 { 229 struct pci_attach_args *pa = &(sc->bge_pa); 230 231 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 232 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 233 } 234 #endif 235 236 void 237 bge_writereg_ind(sc, off, val) 238 struct bge_softc *sc; 239 int off, val; 240 { 241 struct pci_attach_args *pa = &(sc->bge_pa); 242 243 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 244 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 245 } 246 247 #ifdef notdef 248 u_int8_t 249 bge_vpd_readbyte(sc, addr) 250 struct bge_softc *sc; 251 int addr; 252 { 253 int i; 254 u_int32_t val; 255 struct pci_attach_args *pa = &(sc->bge_pa); 256 257 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 258 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 259 DELAY(10); 260 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 261 BGE_VPD_FLAG) 262 break; 263 } 264 265 if (i == BGE_TIMEOUT) { 266 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 267 return(0); 268 } 269 270 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 271 272 return((val >> ((addr % 4) * 8)) & 0xFF); 273 } 274 275 void 276 bge_vpd_read_res(sc, res, addr) 277 struct bge_softc *sc; 278 struct vpd_res *res; 279 int addr; 280 { 281 int i; 282 u_int8_t *ptr; 283 284 ptr = (u_int8_t *)res; 285 for (i = 0; i < sizeof(struct vpd_res); i++) 286 ptr[i] = bge_vpd_readbyte(sc, i + addr); 287 } 288 289 void 290 bge_vpd_read(sc) 291 struct bge_softc *sc; 292 { 293 int pos = 0, i; 294 struct vpd_res res; 295 296 if (sc->bge_vpd_prodname != NULL) 297 free(sc->bge_vpd_prodname, M_DEVBUF); 298 if (sc->bge_vpd_readonly != NULL) 299 free(sc->bge_vpd_readonly, M_DEVBUF); 300 sc->bge_vpd_prodname = NULL; 301 sc->bge_vpd_readonly = NULL; 302 303 bge_vpd_read_res(sc, &res, pos); 304 305 if (res.vr_id != VPD_RES_ID) { 306 printf("%s: bad VPD resource id: expected %x got %x\n", 307 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 308 return; 309 } 310 311 pos += sizeof(res); 312 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 313 if (sc->bge_vpd_prodname == NULL) 314 panic("bge_vpd_read"); 315 for (i = 0; i < res.vr_len; i++) 316 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 317 sc->bge_vpd_prodname[i] = '\0'; 318 pos += i; 319 320 bge_vpd_read_res(sc, &res, pos); 321 322 if (res.vr_id != VPD_RES_READ) { 323 printf("%s: bad VPD resource id: expected %x got %x\n", 324 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 325 return; 326 } 327 328 pos += sizeof(res); 329 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 330 if (sc->bge_vpd_readonly == NULL) 331 panic("bge_vpd_read"); 332 for (i = 0; i < res.vr_len + 1; i++) 333 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 334 } 335 #endif 336 337 /* 338 * Read a byte of data stored in the EEPROM at address 'addr.' The 339 * BCM570x supports both the traditional bitbang interface and an 340 * auto access interface for reading the EEPROM. We use the auto 341 * access method. 342 */ 343 u_int8_t 344 bge_eeprom_getbyte(sc, addr, dest) 345 struct bge_softc *sc; 346 int addr; 347 u_int8_t *dest; 348 { 349 int i; 350 u_int32_t byte = 0; 351 352 /* 353 * Enable use of auto EEPROM access so we can avoid 354 * having to use the bitbang method. 355 */ 356 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 357 358 /* Reset the EEPROM, load the clock period. */ 359 CSR_WRITE_4(sc, BGE_EE_ADDR, 360 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 361 DELAY(20); 362 363 /* Issue the read EEPROM command. */ 364 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 365 366 /* Wait for completion */ 367 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 368 DELAY(10); 369 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 370 break; 371 } 372 373 if (i == BGE_TIMEOUT) { 374 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 375 return(0); 376 } 377 378 /* Get result. */ 379 byte = CSR_READ_4(sc, BGE_EE_DATA); 380 381 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 382 383 return(0); 384 } 385 386 /* 387 * Read a sequence of bytes from the EEPROM. 388 */ 389 int 390 bge_read_eeprom(sc, dest, off, cnt) 391 struct bge_softc *sc; 392 caddr_t dest; 393 int off; 394 int cnt; 395 { 396 int err = 0, i; 397 u_int8_t byte = 0; 398 399 for (i = 0; i < cnt; i++) { 400 err = bge_eeprom_getbyte(sc, off + i, &byte); 401 if (err) 402 break; 403 *(dest + i) = byte; 404 } 405 406 return(err ? 1 : 0); 407 } 408 409 int 410 bge_miibus_readreg(dev, phy, reg) 411 struct device *dev; 412 int phy, reg; 413 { 414 struct bge_softc *sc = (struct bge_softc *)dev; 415 struct ifnet *ifp; 416 u_int32_t val; 417 int i; 418 419 ifp = &sc->ethercom.ec_if; 420 421 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 422 return(0); 423 424 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 425 BGE_MIPHY(phy)|BGE_MIREG(reg)); 426 427 for (i = 0; i < BGE_TIMEOUT; i++) { 428 val = CSR_READ_4(sc, BGE_MI_COMM); 429 if (!(val & BGE_MICOMM_BUSY)) 430 break; 431 delay(10); 432 } 433 434 if (i == BGE_TIMEOUT) { 435 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 436 return(0); 437 } 438 439 val = CSR_READ_4(sc, BGE_MI_COMM); 440 441 if (val & BGE_MICOMM_READFAIL) 442 return(0); 443 444 return(val & 0xFFFF); 445 } 446 447 void 448 bge_miibus_writereg(dev, phy, reg, val) 449 struct device *dev; 450 int phy, reg, val; 451 { 452 struct bge_softc *sc = (struct bge_softc *)dev; 453 int i; 454 455 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 456 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 457 458 for (i = 0; i < BGE_TIMEOUT; i++) { 459 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 460 break; 461 delay(10); 462 } 463 464 if (i == BGE_TIMEOUT) { 465 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 466 } 467 } 468 469 void 470 bge_miibus_statchg(dev) 471 struct device *dev; 472 { 473 struct bge_softc *sc = (struct bge_softc *)dev; 474 struct mii_data *mii = &sc->bge_mii; 475 476 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 477 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 478 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 479 } else { 480 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 481 } 482 483 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 484 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 485 } else { 486 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 487 } 488 489 bge_phy_hack(sc); 490 } 491 492 /* 493 * Handle events that have triggered interrupts. 494 */ 495 void 496 bge_handle_events(sc) 497 struct bge_softc *sc; 498 { 499 500 return; 501 } 502 503 /* 504 * Memory management for jumbo frames. 505 */ 506 507 int 508 bge_alloc_jumbo_mem(sc) 509 struct bge_softc *sc; 510 { 511 caddr_t ptr, kva; 512 bus_dma_segment_t seg; 513 int i, rseg, state, error; 514 struct bge_jpool_entry *entry; 515 516 state = error = 0; 517 518 /* Grab a big chunk o' storage. */ 519 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 520 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 521 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 522 return ENOBUFS; 523 } 524 525 state = 1; 526 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 527 BUS_DMA_NOWAIT)) { 528 printf("%s: can't map dma buffers (%d bytes)\n", 529 sc->bge_dev.dv_xname, (int)BGE_JMEM); 530 error = ENOBUFS; 531 goto out; 532 } 533 534 state = 2; 535 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 536 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 537 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 538 error = ENOBUFS; 539 goto out; 540 } 541 542 state = 3; 543 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 544 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 545 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 546 error = ENOBUFS; 547 goto out; 548 } 549 550 state = 4; 551 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 552 DPRINTFN(1,("bge_jumbo_buf = 0x%p\n", sc->bge_cdata.bge_jumbo_buf)); 553 554 SLIST_INIT(&sc->bge_jfree_listhead); 555 SLIST_INIT(&sc->bge_jinuse_listhead); 556 557 /* 558 * Now divide it up into 9K pieces and save the addresses 559 * in an array. 560 */ 561 ptr = sc->bge_cdata.bge_jumbo_buf; 562 for (i = 0; i < BGE_JSLOTS; i++) { 563 sc->bge_cdata.bge_jslots[i] = ptr; 564 ptr += BGE_JLEN; 565 entry = malloc(sizeof(struct bge_jpool_entry), 566 M_DEVBUF, M_NOWAIT); 567 if (entry == NULL) { 568 printf("%s: no memory for jumbo buffer queue!\n", 569 sc->bge_dev.dv_xname); 570 error = ENOBUFS; 571 goto out; 572 } 573 entry->slot = i; 574 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 575 entry, jpool_entries); 576 } 577 out: 578 if (error != 0) { 579 switch (state) { 580 case 4: 581 bus_dmamap_unload(sc->bge_dmatag, 582 sc->bge_cdata.bge_rx_jumbo_map); 583 case 3: 584 bus_dmamap_destroy(sc->bge_dmatag, 585 sc->bge_cdata.bge_rx_jumbo_map); 586 case 2: 587 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 588 case 1: 589 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 590 break; 591 default: 592 break; 593 } 594 } 595 596 return error; 597 } 598 599 /* 600 * Allocate a jumbo buffer. 601 */ 602 void * 603 bge_jalloc(sc) 604 struct bge_softc *sc; 605 { 606 struct bge_jpool_entry *entry; 607 608 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 609 610 if (entry == NULL) { 611 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 612 return(NULL); 613 } 614 615 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 616 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 617 return(sc->bge_cdata.bge_jslots[entry->slot]); 618 } 619 620 /* 621 * Release a jumbo buffer. 622 */ 623 void 624 bge_jfree(m, buf, size, arg) 625 struct mbuf *m; 626 caddr_t buf; 627 u_int size; 628 void *arg; 629 { 630 struct bge_jpool_entry *entry; 631 struct bge_softc *sc; 632 int i, s; 633 634 /* Extract the softc struct pointer. */ 635 sc = (struct bge_softc *)arg; 636 637 if (sc == NULL) 638 panic("bge_jfree: can't find softc pointer!"); 639 640 /* calculate the slot this buffer belongs to */ 641 642 i = ((caddr_t)buf 643 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 644 645 if ((i < 0) || (i >= BGE_JSLOTS)) 646 panic("bge_jfree: asked to free buffer that we don't manage!"); 647 648 s = splvm(); 649 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 650 if (entry == NULL) 651 panic("bge_jfree: buffer not in use!"); 652 entry->slot = i; 653 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 654 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 655 656 if (__predict_true(m != NULL)) 657 pool_cache_put(&mbpool_cache, m); 658 splx(s); 659 } 660 661 662 /* 663 * Intialize a standard receive ring descriptor. 664 */ 665 int 666 bge_newbuf_std(sc, i, m, dmamap) 667 struct bge_softc *sc; 668 int i; 669 struct mbuf *m; 670 bus_dmamap_t dmamap; 671 { 672 struct mbuf *m_new = NULL; 673 struct bge_rx_bd *r; 674 int error; 675 676 if (dmamap == NULL) { 677 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 678 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 679 if (error != 0) 680 return error; 681 } 682 683 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 684 685 if (m == NULL) { 686 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 687 if (m_new == NULL) { 688 return(ENOBUFS); 689 } 690 691 MCLGET(m_new, M_DONTWAIT); 692 if (!(m_new->m_flags & M_EXT)) { 693 m_freem(m_new); 694 return(ENOBUFS); 695 } 696 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 697 698 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 699 BUS_DMA_READ|BUS_DMA_NOWAIT)) 700 return(ENOBUFS); 701 } else { 702 m_new = m; 703 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 704 m_new->m_data = m_new->m_ext.ext_buf; 705 } 706 707 m_adj(m_new, ETHER_ALIGN); 708 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 709 r = &sc->bge_rdata->bge_rx_std_ring[i]; 710 bge_set_hostaddr(&r->bge_addr, 711 dmamap->dm_segs[0].ds_addr + ETHER_ALIGN); 712 r->bge_flags = BGE_RXBDFLAG_END; 713 r->bge_len = m_new->m_len; 714 r->bge_idx = i; 715 716 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 717 offsetof(struct bge_ring_data, bge_rx_std_ring) + 718 i * sizeof (struct bge_rx_bd), 719 sizeof (struct bge_rx_bd), 720 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 721 722 return(0); 723 } 724 725 /* 726 * Initialize a jumbo receive ring descriptor. This allocates 727 * a jumbo buffer from the pool managed internally by the driver. 728 */ 729 int 730 bge_newbuf_jumbo(sc, i, m) 731 struct bge_softc *sc; 732 int i; 733 struct mbuf *m; 734 { 735 struct mbuf *m_new = NULL; 736 struct bge_rx_bd *r; 737 738 if (m == NULL) { 739 caddr_t *buf = NULL; 740 741 /* Allocate the mbuf. */ 742 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 743 if (m_new == NULL) { 744 return(ENOBUFS); 745 } 746 747 /* Allocate the jumbo buffer */ 748 buf = bge_jalloc(sc); 749 if (buf == NULL) { 750 m_freem(m_new); 751 printf("%s: jumbo allocation failed " 752 "-- packet dropped!\n", sc->bge_dev.dv_xname); 753 return(ENOBUFS); 754 } 755 756 /* Attach the buffer to the mbuf. */ 757 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 758 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 759 bge_jfree, sc); 760 } else { 761 m_new = m; 762 m_new->m_data = m_new->m_ext.ext_buf; 763 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 764 } 765 766 m_adj(m_new, ETHER_ALIGN); 767 /* Set up the descriptor. */ 768 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 769 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 770 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 771 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 772 r->bge_len = m_new->m_len; 773 r->bge_idx = i; 774 775 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 776 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 777 i * sizeof (struct bge_rx_bd), 778 sizeof (struct bge_rx_bd), 779 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 780 781 return(0); 782 } 783 784 /* 785 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 786 * that's 1MB or memory, which is a lot. For now, we fill only the first 787 * 256 ring entries and hope that our CPU is fast enough to keep up with 788 * the NIC. 789 */ 790 int 791 bge_init_rx_ring_std(sc) 792 struct bge_softc *sc; 793 { 794 int i; 795 796 if (sc->bge_flags & BGE_RXRING_VALID) 797 return 0; 798 799 for (i = 0; i < BGE_SSLOTS; i++) { 800 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 801 return(ENOBUFS); 802 } 803 804 sc->bge_std = i - 1; 805 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 806 807 sc->bge_flags |= BGE_RXRING_VALID; 808 809 return(0); 810 } 811 812 void 813 bge_free_rx_ring_std(sc) 814 struct bge_softc *sc; 815 { 816 int i; 817 818 if (!(sc->bge_flags & BGE_RXRING_VALID)) 819 return; 820 821 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 822 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 823 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 824 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 825 bus_dmamap_destroy(sc->bge_dmatag, 826 sc->bge_cdata.bge_rx_std_map[i]); 827 } 828 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 829 sizeof(struct bge_rx_bd)); 830 } 831 832 sc->bge_flags &= ~BGE_RXRING_VALID; 833 } 834 835 int 836 bge_init_rx_ring_jumbo(sc) 837 struct bge_softc *sc; 838 { 839 int i; 840 struct bge_rcb *rcb; 841 struct bge_rcb_opaque *rcbo; 842 843 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 844 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 845 return(ENOBUFS); 846 }; 847 848 sc->bge_jumbo = i - 1; 849 850 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 851 rcbo = (struct bge_rcb_opaque *)rcb; 852 rcb->bge_flags = 0; 853 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 854 855 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 856 857 return(0); 858 } 859 860 void 861 bge_free_rx_ring_jumbo(sc) 862 struct bge_softc *sc; 863 { 864 int i; 865 866 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 867 return; 868 869 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 870 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 871 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 872 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 873 } 874 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 875 sizeof(struct bge_rx_bd)); 876 } 877 878 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 879 } 880 881 void 882 bge_free_tx_ring(sc) 883 struct bge_softc *sc; 884 { 885 int i, freed; 886 struct txdmamap_pool_entry *dma; 887 888 if (!(sc->bge_flags & BGE_TXRING_VALID)) 889 return; 890 891 freed = 0; 892 893 for (i = 0; i < BGE_TX_RING_CNT; i++) { 894 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 895 freed++; 896 m_freem(sc->bge_cdata.bge_tx_chain[i]); 897 sc->bge_cdata.bge_tx_chain[i] = NULL; 898 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 899 link); 900 sc->txdma[i] = 0; 901 } 902 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 903 sizeof(struct bge_tx_bd)); 904 } 905 906 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 907 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 908 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 909 free(dma, M_DEVBUF); 910 } 911 912 sc->bge_flags &= ~BGE_TXRING_VALID; 913 } 914 915 int 916 bge_init_tx_ring(sc) 917 struct bge_softc *sc; 918 { 919 int i; 920 bus_dmamap_t dmamap; 921 struct txdmamap_pool_entry *dma; 922 923 if (sc->bge_flags & BGE_TXRING_VALID) 924 return 0; 925 926 sc->bge_txcnt = 0; 927 sc->bge_tx_saved_considx = 0; 928 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 929 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 930 931 SLIST_INIT(&sc->txdma_list); 932 for (i = 0; i < BGE_RSLOTS; i++) { 933 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 934 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 935 &dmamap)) 936 return(ENOBUFS); 937 if (dmamap == NULL) 938 panic("dmamap NULL in bge_init_tx_ring"); 939 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 940 if (dma == NULL) { 941 printf("%s: can't alloc txdmamap_pool_entry\n", 942 sc->bge_dev.dv_xname); 943 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 944 return (ENOMEM); 945 } 946 dma->dmamap = dmamap; 947 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 948 } 949 950 sc->bge_flags |= BGE_TXRING_VALID; 951 952 return(0); 953 } 954 955 #define BGE_POLY 0xEDB88320 956 957 u_int32_t 958 bge_crc(sc, addr) 959 struct bge_softc *sc; 960 caddr_t addr; 961 { 962 u_int32_t idx, bit, data, crc; 963 964 /* Compute CRC for the address value. */ 965 crc = 0xFFFFFFFF; /* initial value */ 966 967 for (idx = 0; idx < 6; idx++) { 968 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 969 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 970 } 971 972 return(crc & 0x7F); 973 } 974 975 void 976 bge_setmulti(sc) 977 struct bge_softc *sc; 978 { 979 struct ethercom *ac = &sc->ethercom; 980 struct ifnet *ifp = &ac->ec_if; 981 struct ether_multi *enm; 982 struct ether_multistep step; 983 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 984 u_int32_t h; 985 int i; 986 987 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 988 for (i = 0; i < 4; i++) 989 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 990 return; 991 } 992 993 /* First, zot all the existing filters. */ 994 for (i = 0; i < 4; i++) 995 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 996 997 /* Now program new ones. */ 998 ETHER_FIRST_MULTI(step, ac, enm); 999 while (enm != NULL) { 1000 h = bge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 1001 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1002 ETHER_NEXT_MULTI(step, enm); 1003 } 1004 1005 for (i = 0; i < 4; i++) 1006 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1007 } 1008 1009 int bge_swapbits[] = { 1010 0, 1011 BGE_MODECTL_BYTESWAP_DATA, 1012 BGE_MODECTL_WORDSWAP_DATA, 1013 BGE_MODECTL_BYTESWAP_NONFRAME, 1014 BGE_MODECTL_WORDSWAP_NONFRAME, 1015 1016 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1017 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1018 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1019 1020 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1021 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1022 1023 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1024 1025 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1026 BGE_MODECTL_BYTESWAP_NONFRAME, 1027 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1028 BGE_MODECTL_WORDSWAP_NONFRAME, 1029 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1030 BGE_MODECTL_WORDSWAP_NONFRAME, 1031 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1032 BGE_MODECTL_WORDSWAP_NONFRAME, 1033 1034 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1035 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1036 }; 1037 1038 int bge_swapindex = 0; 1039 1040 /* 1041 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1042 * self-test results. 1043 */ 1044 int 1045 bge_chipinit(sc) 1046 struct bge_softc *sc; 1047 { 1048 u_int32_t cachesize; 1049 int i; 1050 struct pci_attach_args *pa = &(sc->bge_pa); 1051 1052 1053 /* Set endianness before we access any non-PCI registers. */ 1054 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1055 BGE_INIT); 1056 1057 /* 1058 * Check the 'ROM failed' bit on the RX CPU to see if 1059 * self-tests passed. 1060 */ 1061 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1062 printf("%s: RX CPU self-diagnostics failed!\n", 1063 sc->bge_dev.dv_xname); 1064 return(ENODEV); 1065 } 1066 1067 /* Clear the MAC control register */ 1068 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1069 1070 /* 1071 * Clear the MAC statistics block in the NIC's 1072 * internal memory. 1073 */ 1074 for (i = BGE_STATS_BLOCK; 1075 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1076 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1077 1078 for (i = BGE_STATUS_BLOCK; 1079 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1080 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1081 1082 /* Set up the PCI DMA control register. */ 1083 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1084 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 1085 1086 /* 1087 * Set up general mode register. 1088 */ 1089 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1090 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1091 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1092 BGE_MODECTL_RX_NO_PHDR_CSUM); 1093 1094 /* Get cache line size. */ 1095 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1096 1097 /* 1098 * Avoid violating PCI spec on certain chip revs. 1099 */ 1100 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1101 PCIM_CMD_MWIEN) { 1102 switch(cachesize) { 1103 case 1: 1104 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1105 BGE_PCI_WRITE_BNDRY_16BYTES); 1106 break; 1107 case 2: 1108 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1109 BGE_PCI_WRITE_BNDRY_32BYTES); 1110 break; 1111 case 4: 1112 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1113 BGE_PCI_WRITE_BNDRY_64BYTES); 1114 break; 1115 case 8: 1116 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1117 BGE_PCI_WRITE_BNDRY_128BYTES); 1118 break; 1119 case 16: 1120 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1121 BGE_PCI_WRITE_BNDRY_256BYTES); 1122 break; 1123 case 32: 1124 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1125 BGE_PCI_WRITE_BNDRY_512BYTES); 1126 break; 1127 case 64: 1128 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1129 BGE_PCI_WRITE_BNDRY_1024BYTES); 1130 break; 1131 default: 1132 /* Disable PCI memory write and invalidate. */ 1133 #if 0 1134 if (bootverbose) 1135 printf("%s: cache line size %d not " 1136 "supported; disabling PCI MWI\n", 1137 sc->bge_dev.dv_xname, cachesize); 1138 #endif 1139 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1140 PCIM_CMD_MWIEN); 1141 break; 1142 } 1143 } 1144 1145 #ifdef __brokenalpha__ 1146 /* 1147 * Must insure that we do not cross an 8K (bytes) boundary 1148 * for DMA reads. Our highest limit is 1K bytes. This is a 1149 * restriction on some ALPHA platforms with early revision 1150 * 21174 PCI chipsets, such as the AlphaPC 164lx 1151 */ 1152 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1153 #endif 1154 1155 /* Set the timer prescaler (always 66Mhz) */ 1156 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1157 1158 return(0); 1159 } 1160 1161 int 1162 bge_blockinit(sc) 1163 struct bge_softc *sc; 1164 { 1165 struct bge_rcb *rcb; 1166 struct bge_rcb_opaque *rcbo; 1167 bus_size_t rcb_addr; 1168 int i; 1169 struct ifnet *ifp = &sc->ethercom.ec_if; 1170 bge_hostaddr taddr; 1171 1172 /* 1173 * Initialize the memory window pointer register so that 1174 * we can access the first 32K of internal NIC RAM. This will 1175 * allow us to set up the TX send ring RCBs and the RX return 1176 * ring RCBs, plus other things which live in NIC memory. 1177 */ 1178 1179 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1180 BGE_PCI_MEMWIN_BASEADDR, 0); 1181 1182 /* Configure mbuf memory pool */ 1183 if (sc->bge_extram) { 1184 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1185 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1186 } else { 1187 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1188 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1189 } 1190 1191 /* Configure DMA resource pool */ 1192 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1193 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1194 1195 /* Configure mbuf pool watermarks */ 1196 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1197 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1198 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1199 1200 /* Configure DMA resource watermarks */ 1201 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1202 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1203 1204 /* Enable buffer manager */ 1205 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1206 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1207 1208 /* Poll for buffer manager start indication */ 1209 for (i = 0; i < BGE_TIMEOUT; i++) { 1210 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1211 break; 1212 DELAY(10); 1213 } 1214 1215 if (i == BGE_TIMEOUT) { 1216 printf("%s: buffer manager failed to start\n", 1217 sc->bge_dev.dv_xname); 1218 return(ENXIO); 1219 } 1220 1221 /* Enable flow-through queues */ 1222 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1223 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1224 1225 /* Wait until queue initialization is complete */ 1226 for (i = 0; i < BGE_TIMEOUT; i++) { 1227 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1228 break; 1229 DELAY(10); 1230 } 1231 1232 if (i == BGE_TIMEOUT) { 1233 printf("%s: flow-through queue init failed\n", 1234 sc->bge_dev.dv_xname); 1235 return(ENXIO); 1236 } 1237 1238 /* Initialize the standard RX ring control block */ 1239 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1240 bge_set_hostaddr(&rcb->bge_hostaddr, 1241 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1242 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1243 if (sc->bge_extram) 1244 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1245 else 1246 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1247 rcb->bge_flags = 0; 1248 rcbo = (struct bge_rcb_opaque *)rcb; 1249 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1250 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1251 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1252 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1253 1254 /* 1255 * Initialize the jumbo RX ring control block 1256 * We set the 'ring disabled' bit in the flags 1257 * field until we're actually ready to start 1258 * using this ring (i.e. once we set the MTU 1259 * high enough to require it). 1260 */ 1261 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1262 bge_set_hostaddr(&rcb->bge_hostaddr, 1263 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1264 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1265 if (sc->bge_extram) 1266 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1267 else 1268 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1269 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1270 1271 rcbo = (struct bge_rcb_opaque *)rcb; 1272 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1273 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1274 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1275 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1276 1277 /* Set up dummy disabled mini ring RCB */ 1278 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1279 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1280 rcbo = (struct bge_rcb_opaque *)rcb; 1281 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1282 1283 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1284 offsetof(struct bge_ring_data, bge_info), sizeof (struct bge_gib), 1285 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1286 1287 /* 1288 * Set the BD ring replentish thresholds. The recommended 1289 * values are 1/8th the number of descriptors allocated to 1290 * each ring. 1291 */ 1292 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1293 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1294 1295 /* 1296 * Disable all unused send rings by setting the 'ring disabled' 1297 * bit in the flags field of all the TX send ring control blocks. 1298 * These are located in NIC memory. 1299 */ 1300 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1301 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1302 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1303 BGE_RCB_FLAG_RING_DISABLED); 1304 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1305 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1306 rcb_addr += sizeof(struct bge_rcb); 1307 } 1308 1309 /* Configure TX RCB 0 (we use only the first ring) */ 1310 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1311 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1312 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1313 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1314 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1315 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1316 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1317 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1318 1319 /* Disable all unused RX return rings */ 1320 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1321 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1322 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1323 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1324 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1325 BGE_RCB_FLAG_RING_DISABLED); 1326 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1327 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1328 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1329 (i * (sizeof(u_int64_t))), 0); 1330 rcb_addr += sizeof(struct bge_rcb); 1331 } 1332 1333 /* Initialize RX ring indexes */ 1334 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1335 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1336 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1337 1338 /* 1339 * Set up RX return ring 0 1340 * Note that the NIC address for RX return rings is 0x00000000. 1341 * The return rings live entirely within the host, so the 1342 * nicaddr field in the RCB isn't used. 1343 */ 1344 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1345 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1346 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1347 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1348 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1349 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1350 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1351 1352 /* Set random backoff seed for TX */ 1353 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1354 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1355 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1356 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1357 BGE_TX_BACKOFF_SEED_MASK); 1358 1359 /* Set inter-packet gap */ 1360 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1361 1362 /* 1363 * Specify which ring to use for packets that don't match 1364 * any RX rules. 1365 */ 1366 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1367 1368 /* 1369 * Configure number of RX lists. One interrupt distribution 1370 * list, sixteen active lists, one bad frames class. 1371 */ 1372 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1373 1374 /* Inialize RX list placement stats mask. */ 1375 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1376 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1377 1378 /* Disable host coalescing until we get it set up */ 1379 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1380 1381 /* Poll to make sure it's shut down. */ 1382 for (i = 0; i < BGE_TIMEOUT; i++) { 1383 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1384 break; 1385 DELAY(10); 1386 } 1387 1388 if (i == BGE_TIMEOUT) { 1389 printf("%s: host coalescing engine failed to idle\n", 1390 sc->bge_dev.dv_xname); 1391 return(ENXIO); 1392 } 1393 1394 /* Set up host coalescing defaults */ 1395 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1396 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1397 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1398 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1399 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1400 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1401 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1402 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1403 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1404 1405 /* Set up address of statistics block */ 1406 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1407 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1408 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1409 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1410 1411 /* Set up address of status block */ 1412 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1413 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1414 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1415 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1416 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1417 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1418 1419 /* Turn on host coalescing state machine */ 1420 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1421 1422 /* Turn on RX BD completion state machine and enable attentions */ 1423 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1424 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1425 1426 /* Turn on RX list placement state machine */ 1427 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1428 1429 /* Turn on RX list selector state machine. */ 1430 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1431 1432 /* Turn on DMA, clear stats */ 1433 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1434 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1435 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1436 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1437 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1438 1439 /* Set misc. local control, enable interrupts on attentions */ 1440 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1441 1442 #ifdef notdef 1443 /* Assert GPIO pins for PHY reset */ 1444 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1445 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1446 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1447 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1448 #endif 1449 1450 /* Turn on DMA completion state machine */ 1451 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1452 1453 /* Turn on write DMA state machine */ 1454 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1455 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1456 1457 /* Turn on read DMA state machine */ 1458 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1459 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1460 1461 /* Turn on RX data completion state machine */ 1462 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1463 1464 /* Turn on RX BD initiator state machine */ 1465 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1466 1467 /* Turn on RX data and RX BD initiator state machine */ 1468 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1469 1470 /* Turn on Mbuf cluster free state machine */ 1471 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1472 1473 /* Turn on send BD completion state machine */ 1474 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1475 1476 /* Turn on send data completion state machine */ 1477 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1478 1479 /* Turn on send data initiator state machine */ 1480 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1481 1482 /* Turn on send BD initiator state machine */ 1483 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1484 1485 /* Turn on send BD selector state machine */ 1486 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1487 1488 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1489 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1490 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1491 1492 /* init LED register */ 1493 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1494 1495 /* ack/clear link change events */ 1496 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1497 BGE_MACSTAT_CFG_CHANGED); 1498 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1499 1500 /* Enable PHY auto polling (for MII/GMII only) */ 1501 if (sc->bge_tbi) { 1502 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1503 } else { 1504 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1505 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) 1506 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1507 BGE_EVTENB_MI_INTERRUPT); 1508 } 1509 1510 /* Enable link state change attentions. */ 1511 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1512 1513 return(0); 1514 } 1515 1516 static const struct bge_product { 1517 pci_vendor_id_t bp_vendor; 1518 pci_product_id_t bp_product; 1519 const char *bp_name; 1520 } bge_products[] = { 1521 /* 1522 * The BCM5700 documentation seems to indicate that the hardware 1523 * still has the Alteon vendor ID burned into it, though it 1524 * should always be overridden by the value in the EEPROM. We'll 1525 * check for it anyway. 1526 */ 1527 { PCI_VENDOR_ALTEON, 1528 PCI_PRODUCT_ALTEON_BCM5700, 1529 "Broadcom BCM5700 Gigabit Ethernet" }, 1530 { PCI_VENDOR_ALTEON, 1531 PCI_PRODUCT_ALTEON_BCM5701, 1532 "Broadcom BCM5701 Gigabit Ethernet" }, 1533 1534 { PCI_VENDOR_ALTIMA, 1535 PCI_PRODUCT_ALTIMA_AC1000, 1536 "Altima AC1000 Gigabit Ethernet" }, 1537 { PCI_VENDOR_ALTIMA, 1538 PCI_PRODUCT_ALTIMA_AC9100, 1539 "Altima AC9100 Gigabit Ethernet" }, 1540 1541 { PCI_VENDOR_BROADCOM, 1542 PCI_PRODUCT_BROADCOM_BCM5700, 1543 "Broadcom BCM5700 Gigabit Ethernet" }, 1544 { PCI_VENDOR_BROADCOM, 1545 PCI_PRODUCT_BROADCOM_BCM5701, 1546 "Broadcom BCM5700 Gigabit Ethernet" }, 1547 1548 { PCI_VENDOR_SCHNEIDERKOCH, 1549 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 1550 "SysKonnect SK-9Dx1 Gigabit Ethernet" }, 1551 1552 { PCI_VENDOR_3COM, 1553 PCI_PRODUCT_3COM_3C996, 1554 "3Com 3c996 Gigabit Ethernet" }, 1555 1556 { 0, 1557 0, 1558 NULL }, 1559 }; 1560 1561 static const struct bge_product * 1562 bge_lookup(const struct pci_attach_args *pa) 1563 { 1564 const struct bge_product *bp; 1565 1566 for (bp = bge_products; bp->bp_name != NULL; bp++) { 1567 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 1568 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 1569 return (bp); 1570 } 1571 1572 return (NULL); 1573 } 1574 1575 /* 1576 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1577 * against our list and return its name if we find a match. Note 1578 * that since the Broadcom controller contains VPD support, we 1579 * can get the device name string from the controller itself instead 1580 * of the compiled-in string. This is a little slow, but it guarantees 1581 * we'll always announce the right product name. 1582 */ 1583 int 1584 bge_probe(parent, match, aux) 1585 struct device *parent; 1586 struct cfdata *match; 1587 void *aux; 1588 { 1589 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1590 1591 if (bge_lookup(pa) != NULL) 1592 return (1); 1593 1594 return (0); 1595 } 1596 1597 void 1598 bge_attach(parent, self, aux) 1599 struct device *parent, *self; 1600 void *aux; 1601 { 1602 struct bge_softc *sc = (struct bge_softc *)self; 1603 struct pci_attach_args *pa = aux; 1604 const struct bge_product *bp; 1605 pci_chipset_tag_t pc = pa->pa_pc; 1606 pci_intr_handle_t ih; 1607 const char *intrstr = NULL; 1608 bus_dma_segment_t seg; 1609 int rseg; 1610 u_int32_t hwcfg = 0; 1611 u_int32_t command; 1612 struct ifnet *ifp; 1613 int unit; 1614 caddr_t kva; 1615 u_char eaddr[ETHER_ADDR_LEN]; 1616 pcireg_t memtype; 1617 bus_addr_t memaddr; 1618 bus_size_t memsize; 1619 1620 bp = bge_lookup(pa); 1621 KASSERT(bp != NULL); 1622 1623 sc->bge_pa = *pa; 1624 1625 printf(": %s, rev. 0x%02x\n", bp->bp_name, PCI_REVISION(pa->pa_class)); 1626 1627 /* 1628 * Map control/status registers. 1629 */ 1630 DPRINTFN(5, ("Map control/status regs\n")); 1631 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1632 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1633 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1634 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1635 1636 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1637 printf("%s: failed to enable memory mapping!\n", 1638 sc->bge_dev.dv_xname); 1639 return; 1640 } 1641 1642 DPRINTFN(5, ("pci_mem_find\n")); 1643 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1644 switch (memtype) { 1645 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1646 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1647 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 1648 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 1649 &memaddr, &memsize) == 0) 1650 break; 1651 default: 1652 printf("%s: can't find mem space\n", 1653 sc->bge_dev.dv_xname); 1654 return; 1655 } 1656 1657 DPRINTFN(5, ("pci_intr_map\n")); 1658 if (pci_intr_map(pa, &ih)) { 1659 printf("%s: couldn't map interrupt\n", 1660 sc->bge_dev.dv_xname); 1661 return; 1662 } 1663 1664 DPRINTFN(5, ("pci_intr_string\n")); 1665 intrstr = pci_intr_string(pc, ih); 1666 1667 DPRINTFN(5, ("pci_intr_establish\n")); 1668 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 1669 1670 if (sc->bge_intrhand == NULL) { 1671 printf("%s: couldn't establish interrupt", 1672 sc->bge_dev.dv_xname); 1673 if (intrstr != NULL) 1674 printf(" at %s", intrstr); 1675 printf("\n"); 1676 return; 1677 } 1678 printf("%s: interrupting at %s\n", sc->bge_dev.dv_xname, intrstr); 1679 1680 /* Try to reset the chip. */ 1681 DPRINTFN(5, ("bge_reset\n")); 1682 bge_reset(sc); 1683 1684 if (bge_chipinit(sc)) { 1685 printf("%s: chip initializatino failed\n", 1686 sc->bge_dev.dv_xname); 1687 bge_release_resources(sc); 1688 return; 1689 } 1690 1691 /* 1692 * Get station address from the EEPROM. 1693 */ 1694 if (bge_read_eeprom(sc, (caddr_t)eaddr, 1695 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1696 printf("bge%d: failed to read station address\n", unit); 1697 bge_release_resources(sc); 1698 return; 1699 } 1700 1701 /* 1702 * A Broadcom chip was detected. Inform the world. 1703 */ 1704 printf("%s: Ethernet address %s\n", sc->bge_dev.dv_xname, 1705 ether_sprintf(eaddr)); 1706 1707 /* Allocate the general information block and ring buffers. */ 1708 sc->bge_dmatag = pa->pa_dmat; 1709 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1710 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1711 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1712 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1713 return; 1714 } 1715 DPRINTFN(5, ("bus_dmamem_map\n")); 1716 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1717 sizeof(struct bge_ring_data), &kva, 1718 BUS_DMA_NOWAIT)) { 1719 printf("%s: can't map dma buffers (%d bytes)\n", 1720 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 1721 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1722 return; 1723 } 1724 DPRINTFN(5, ("bus_dmamem_create\n")); 1725 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1726 sizeof(struct bge_ring_data), 0, 1727 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1728 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1729 bus_dmamem_unmap(sc->bge_dmatag, kva, 1730 sizeof(struct bge_ring_data)); 1731 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1732 return; 1733 } 1734 DPRINTFN(5, ("bus_dmamem_load\n")); 1735 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1736 sizeof(struct bge_ring_data), NULL, 1737 BUS_DMA_NOWAIT)) { 1738 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1739 bus_dmamem_unmap(sc->bge_dmatag, kva, 1740 sizeof(struct bge_ring_data)); 1741 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1742 return; 1743 } 1744 1745 DPRINTFN(5, ("bzero\n")); 1746 sc->bge_rdata = (struct bge_ring_data *)kva; 1747 1748 memset(sc->bge_rdata, sizeof(struct bge_ring_data), 0); 1749 1750 /* Try to allocate memory for jumbo buffers. */ 1751 if (bge_alloc_jumbo_mem(sc)) { 1752 printf("%s: jumbo buffer allocation failed\n", 1753 sc->bge_dev.dv_xname); 1754 } else 1755 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1756 1757 /* Set default tuneable values. */ 1758 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1759 sc->bge_rx_coal_ticks = 150; 1760 sc->bge_tx_coal_ticks = 150; 1761 sc->bge_rx_max_coal_bds = 64; 1762 sc->bge_tx_max_coal_bds = 128; 1763 1764 /* Set up ifnet structure */ 1765 ifp = &sc->ethercom.ec_if; 1766 ifp->if_softc = sc; 1767 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1768 ifp->if_ioctl = bge_ioctl; 1769 ifp->if_start = bge_start; 1770 ifp->if_init = bge_init; 1771 ifp->if_watchdog = bge_watchdog; 1772 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1773 IFQ_SET_READY(&ifp->if_snd); 1774 DPRINTFN(5, ("bcopy\n")); 1775 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 1776 1777 sc->ethercom.ec_if.if_capabilities |= 1778 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1779 sc->ethercom.ec_capabilities |= 1780 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 1781 1782 /* 1783 * Do MII setup. 1784 */ 1785 DPRINTFN(5, ("mii setup\n")); 1786 sc->bge_mii.mii_ifp = ifp; 1787 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1788 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1789 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1790 1791 /* Save ASIC rev. */ 1792 1793 sc->bge_asicrev = 1794 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 1795 BGE_PCIMISCCTL_ASICREV; 1796 1797 /* 1798 * Figure out what sort of media we have by checking the 1799 * hardware config word in the EEPROM. Note: on some BCM5700 1800 * cards, this value appears to be unset. If that's the 1801 * case, we have to rely on identifying the NIC by its PCI 1802 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1803 */ 1804 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1805 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1806 if ((be32toh(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1807 sc->bge_tbi = 1; 1808 1809 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1810 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1811 SK_SUBSYSID_9D41) 1812 sc->bge_tbi = 1; 1813 1814 if (sc->bge_tbi) { 1815 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 1816 bge_ifmedia_sts); 1817 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1818 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 1819 0, NULL); 1820 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1821 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1822 } else { 1823 /* 1824 * Do transceiver setup. 1825 */ 1826 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1827 bge_ifmedia_sts); 1828 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1829 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1830 1831 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1832 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1833 ifmedia_add(&sc->bge_mii.mii_media, 1834 IFM_ETHER|IFM_MANUAL, 0, NULL); 1835 ifmedia_set(&sc->bge_mii.mii_media, 1836 IFM_ETHER|IFM_MANUAL); 1837 } else 1838 ifmedia_set(&sc->bge_mii.mii_media, 1839 IFM_ETHER|IFM_AUTO); 1840 } 1841 1842 /* 1843 * Call MI attach routine. 1844 */ 1845 DPRINTFN(5, ("if_attach\n")); 1846 if_attach(ifp); 1847 DPRINTFN(5, ("ether_ifattach\n")); 1848 ether_ifattach(ifp, eaddr); 1849 DPRINTFN(5, ("callout_init\n")); 1850 callout_init(&sc->bge_timeout); 1851 } 1852 1853 void 1854 bge_release_resources(sc) 1855 struct bge_softc *sc; 1856 { 1857 if (sc->bge_vpd_prodname != NULL) 1858 free(sc->bge_vpd_prodname, M_DEVBUF); 1859 1860 if (sc->bge_vpd_readonly != NULL) 1861 free(sc->bge_vpd_readonly, M_DEVBUF); 1862 } 1863 1864 void 1865 bge_reset(sc) 1866 struct bge_softc *sc; 1867 { 1868 struct pci_attach_args *pa = &sc->bge_pa; 1869 u_int32_t cachesize, command, pcistate; 1870 int i, val = 0; 1871 1872 /* Save some important PCI state. */ 1873 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1874 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1875 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1876 1877 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1878 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1879 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1880 1881 /* Issue global reset */ 1882 bge_writereg_ind(sc, BGE_MISC_CFG, 1883 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1884 1885 DELAY(1000); 1886 1887 /* Reset some of the PCI state that got zapped by reset */ 1888 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1889 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1890 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 1891 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1892 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1893 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1894 1895 /* Enable memory arbiter. */ 1896 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1897 1898 /* 1899 * Prevent PXE restart: write a magic number to the 1900 * general communications memory at 0xB50. 1901 */ 1902 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1903 1904 /* 1905 * Poll the value location we just wrote until 1906 * we see the 1's complement of the magic number. 1907 * This indicates that the firmware initialization 1908 * is complete. 1909 */ 1910 for (i = 0; i < 750; i++) { 1911 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1912 if (val == ~BGE_MAGIC_NUMBER) 1913 break; 1914 DELAY(1000); 1915 } 1916 1917 if (i == 750) { 1918 printf("%s: firmware handshake timed out, val = %x\n", 1919 sc->bge_dev.dv_xname, val); 1920 return; 1921 } 1922 1923 /* 1924 * XXX Wait for the value of the PCISTATE register to 1925 * return to its original pre-reset state. This is a 1926 * fairly good indicator of reset completion. If we don't 1927 * wait for the reset to fully complete, trying to read 1928 * from the device's non-PCI registers may yield garbage 1929 * results. 1930 */ 1931 for (i = 0; i < BGE_TIMEOUT; i++) { 1932 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 1933 pcistate) 1934 break; 1935 DELAY(10); 1936 } 1937 1938 /* Enable memory arbiter. */ 1939 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1940 1941 /* Fix up byte swapping */ 1942 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 1943 1944 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1945 1946 DELAY(10000); 1947 } 1948 1949 /* 1950 * Frame reception handling. This is called if there's a frame 1951 * on the receive return list. 1952 * 1953 * Note: we have to be able to handle two possibilities here: 1954 * 1) the frame is from the jumbo recieve ring 1955 * 2) the frame is from the standard receive ring 1956 */ 1957 1958 void 1959 bge_rxeof(sc) 1960 struct bge_softc *sc; 1961 { 1962 struct ifnet *ifp; 1963 int stdcnt = 0, jumbocnt = 0; 1964 int have_tag = 0; 1965 u_int16_t vlan_tag = 0; 1966 bus_dmamap_t dmamap; 1967 bus_addr_t offset, toff; 1968 bus_size_t tlen; 1969 int tosync; 1970 1971 ifp = &sc->ethercom.ec_if; 1972 1973 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1974 offsetof(struct bge_ring_data, bge_status_block), 1975 sizeof (struct bge_status_block), 1976 BUS_DMASYNC_POSTREAD); 1977 1978 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 1979 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 1980 sc->bge_rx_saved_considx; 1981 1982 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 1983 1984 if (tosync < 0) { 1985 tlen = (BGE_RETURN_RING_CNT - sc->bge_rx_saved_considx) * 1986 sizeof (struct bge_rx_bd); 1987 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1988 toff, tlen, BUS_DMASYNC_POSTREAD); 1989 tosync = -tosync; 1990 } 1991 1992 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1993 offset, tosync * sizeof (struct bge_rx_bd), 1994 BUS_DMASYNC_POSTREAD); 1995 1996 while(sc->bge_rx_saved_considx != 1997 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1998 struct bge_rx_bd *cur_rx; 1999 u_int32_t rxidx; 2000 struct mbuf *m = NULL; 2001 2002 cur_rx = &sc->bge_rdata-> 2003 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2004 2005 rxidx = cur_rx->bge_idx; 2006 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 2007 2008 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2009 have_tag = 1; 2010 vlan_tag = cur_rx->bge_vlan_tag; 2011 } 2012 2013 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2014 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2015 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2016 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2017 jumbocnt++; 2018 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2019 ifp->if_ierrors++; 2020 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2021 continue; 2022 } 2023 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2024 NULL)== ENOBUFS) { 2025 ifp->if_ierrors++; 2026 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2027 continue; 2028 } 2029 } else { 2030 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2031 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2032 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2033 stdcnt++; 2034 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2035 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2036 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2037 ifp->if_ierrors++; 2038 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2039 continue; 2040 } 2041 if (bge_newbuf_std(sc, sc->bge_std, 2042 NULL, dmamap) == ENOBUFS) { 2043 ifp->if_ierrors++; 2044 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2045 continue; 2046 } 2047 } 2048 2049 ifp->if_ipackets++; 2050 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2051 m->m_pkthdr.rcvif = ifp; 2052 2053 #if NBPFILTER > 0 2054 /* 2055 * Handle BPF listeners. Let the BPF user see the packet. 2056 */ 2057 if (ifp->if_bpf) 2058 bpf_mtap(ifp->if_bpf, m); 2059 #endif 2060 2061 if (sc->bge_asicrev != BGE_ASICREV_BCM5700_B0) { 2062 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2063 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2064 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2065 #if 0 /* XXX appears to be broken */ 2066 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2067 m->m_pkthdr.csum_data = 2068 cur_rx->bge_tcp_udp_csum; 2069 m->m_pkthdr.csum_flags |= 2070 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_DATA); 2071 } 2072 #endif 2073 } 2074 2075 /* 2076 * If we received a packet with a vlan tag, pass it 2077 * to vlan_input() instead of ether_input(). 2078 */ 2079 if (have_tag) { 2080 struct mbuf *n; 2081 2082 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2083 if (n != NULL) { 2084 *mtod(n, int *) = vlan_tag; 2085 n->m_len = sizeof(int); 2086 have_tag = vlan_tag = 0; 2087 } else { 2088 printf("%s: no mbuf for tag\n", ifp->if_xname); 2089 m_freem(m); 2090 have_tag = vlan_tag = 0; 2091 continue; 2092 } 2093 } 2094 (*ifp->if_input)(ifp, m); 2095 } 2096 2097 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2098 if (stdcnt) 2099 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2100 if (jumbocnt) 2101 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2102 } 2103 2104 void 2105 bge_txeof(sc) 2106 struct bge_softc *sc; 2107 { 2108 struct bge_tx_bd *cur_tx = NULL; 2109 struct ifnet *ifp; 2110 struct txdmamap_pool_entry *dma; 2111 bus_addr_t offset, toff; 2112 bus_size_t tlen; 2113 int tosync; 2114 struct mbuf *m; 2115 2116 ifp = &sc->ethercom.ec_if; 2117 2118 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2119 offsetof(struct bge_ring_data, bge_status_block), 2120 sizeof (struct bge_status_block), 2121 BUS_DMASYNC_POSTREAD); 2122 2123 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2124 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2125 sc->bge_tx_saved_considx; 2126 2127 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2128 2129 if (tosync < 0) { 2130 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2131 sizeof (struct bge_tx_bd); 2132 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2133 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2134 tosync = -tosync; 2135 } 2136 2137 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2138 offset, tosync * sizeof (struct bge_tx_bd), 2139 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2140 2141 /* 2142 * Go through our tx ring and free mbufs for those 2143 * frames that have been sent. 2144 */ 2145 while (sc->bge_tx_saved_considx != 2146 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2147 u_int32_t idx = 0; 2148 2149 idx = sc->bge_tx_saved_considx; 2150 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2151 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2152 ifp->if_opackets++; 2153 m = sc->bge_cdata.bge_tx_chain[idx]; 2154 if (m != NULL) { 2155 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2156 dma = sc->txdma[idx]; 2157 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2158 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2159 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2160 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2161 sc->txdma[idx] = NULL; 2162 2163 m_freem(m); 2164 } 2165 sc->bge_txcnt--; 2166 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2167 ifp->if_timer = 0; 2168 } 2169 2170 if (cur_tx != NULL) 2171 ifp->if_flags &= ~IFF_OACTIVE; 2172 } 2173 2174 int 2175 bge_intr(xsc) 2176 void *xsc; 2177 { 2178 struct bge_softc *sc; 2179 struct ifnet *ifp; 2180 2181 sc = xsc; 2182 ifp = &sc->ethercom.ec_if; 2183 2184 #ifdef notdef 2185 /* Avoid this for now -- checking this register is expensive. */ 2186 /* Make sure this is really our interrupt. */ 2187 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2188 return (0); 2189 #endif 2190 /* Ack interrupt and stop others from occuring. */ 2191 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2192 2193 /* 2194 * Process link state changes. 2195 * Grrr. The link status word in the status block does 2196 * not work correctly on the BCM5700 rev AX and BX chips, 2197 * according to all avaibable information. Hence, we have 2198 * to enable MII interrupts in order to properly obtain 2199 * async link changes. Unfortunately, this also means that 2200 * we have to read the MAC status register to detect link 2201 * changes, thereby adding an additional register access to 2202 * the interrupt handler. 2203 */ 2204 2205 if (BGE_IS_5700_Ax_Bx(sc->bge_asicrev)) { 2206 u_int32_t status; 2207 2208 status = CSR_READ_4(sc, BGE_MAC_STS); 2209 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2210 sc->bge_link = 0; 2211 callout_stop(&sc->bge_timeout); 2212 bge_tick(sc); 2213 /* Clear the interrupt */ 2214 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2215 BGE_EVTENB_MI_INTERRUPT); 2216 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 2217 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 2218 BRGPHY_INTRS); 2219 } 2220 } else { 2221 if (sc->bge_rdata->bge_status_block.bge_status & 2222 BGE_STATFLAG_LINKSTATE_CHANGED) { 2223 sc->bge_link = 0; 2224 callout_stop(&sc->bge_timeout); 2225 bge_tick(sc); 2226 /* Clear the interrupt */ 2227 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2228 BGE_MACSTAT_CFG_CHANGED); 2229 } 2230 } 2231 2232 if (ifp->if_flags & IFF_RUNNING) { 2233 /* Check RX return ring producer/consumer */ 2234 bge_rxeof(sc); 2235 2236 /* Check TX ring producer/consumer */ 2237 bge_txeof(sc); 2238 } 2239 2240 bge_handle_events(sc); 2241 2242 /* Re-enable interrupts. */ 2243 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2244 2245 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 2246 bge_start(ifp); 2247 2248 return (1); 2249 } 2250 2251 void 2252 bge_tick(xsc) 2253 void *xsc; 2254 { 2255 struct bge_softc *sc = xsc; 2256 struct mii_data *mii = &sc->bge_mii; 2257 struct ifmedia *ifm = NULL; 2258 struct ifnet *ifp = &sc->ethercom.ec_if; 2259 int s; 2260 2261 s = splnet(); 2262 2263 bge_stats_update(sc); 2264 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2265 if (sc->bge_link) { 2266 splx(s); 2267 return; 2268 } 2269 2270 if (sc->bge_tbi) { 2271 ifm = &sc->bge_ifmedia; 2272 if (CSR_READ_4(sc, BGE_MAC_STS) & 2273 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2274 sc->bge_link++; 2275 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2276 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2277 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2278 bge_start(ifp); 2279 } 2280 splx(s); 2281 return; 2282 } 2283 2284 mii_tick(mii); 2285 2286 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2287 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2288 sc->bge_link++; 2289 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2290 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2291 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2292 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2293 bge_start(ifp); 2294 } 2295 2296 splx(s); 2297 } 2298 2299 void 2300 bge_stats_update(sc) 2301 struct bge_softc *sc; 2302 { 2303 struct ifnet *ifp = &sc->ethercom.ec_if; 2304 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2305 2306 #define READ_STAT(sc, stats, stat) \ 2307 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2308 2309 ifp->if_collisions += 2310 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2311 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2312 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2313 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2314 ifp->if_collisions; 2315 2316 #undef READ_STAT 2317 2318 #ifdef notdef 2319 ifp->if_collisions += 2320 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2321 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2322 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2323 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2324 ifp->if_collisions; 2325 #endif 2326 } 2327 2328 /* 2329 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2330 * pointers to descriptors. 2331 */ 2332 int 2333 bge_encap(sc, m_head, txidx) 2334 struct bge_softc *sc; 2335 struct mbuf *m_head; 2336 u_int32_t *txidx; 2337 { 2338 struct bge_tx_bd *f = NULL; 2339 u_int32_t frag, cur, cnt = 0; 2340 u_int16_t csum_flags = 0; 2341 struct txdmamap_pool_entry *dma; 2342 bus_dmamap_t dmamap; 2343 int i = 0; 2344 struct mbuf *n; 2345 2346 cur = frag = *txidx; 2347 2348 if (m_head->m_pkthdr.csum_flags) { 2349 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 2350 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2351 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2352 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2353 } 2354 2355 dma = SLIST_FIRST(&sc->txdma_list); 2356 if (dma == NULL) 2357 return ENOBUFS; 2358 dmamap = dma->dmamap; 2359 2360 /* 2361 * Start packing the mbufs in this chain into 2362 * the fragment pointers. Stop when we run out 2363 * of fragments or hit the end of the mbuf chain. 2364 */ 2365 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 2366 BUS_DMA_NOWAIT)) 2367 return(ENOBUFS); 2368 2369 n = sc->ethercom.ec_nvlans ? 2370 m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN) : NULL; 2371 2372 for (i = 0; i < dmamap->dm_nsegs; i++) { 2373 f = &sc->bge_rdata->bge_tx_ring[frag]; 2374 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2375 break; 2376 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 2377 f->bge_len = dmamap->dm_segs[i].ds_len; 2378 f->bge_flags = csum_flags; 2379 2380 if (n != NULL) { 2381 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2382 f->bge_vlan_tag = *mtod(n, int *); 2383 } else { 2384 f->bge_vlan_tag = 0; 2385 } 2386 /* 2387 * Sanity check: avoid coming within 16 descriptors 2388 * of the end of the ring. 2389 */ 2390 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2391 return(ENOBUFS); 2392 cur = frag; 2393 BGE_INC(frag, BGE_TX_RING_CNT); 2394 cnt++; 2395 } 2396 2397 if (i < dmamap->dm_nsegs) 2398 return ENOBUFS; 2399 2400 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 2401 BUS_DMASYNC_PREWRITE); 2402 2403 if (frag == sc->bge_tx_saved_considx) 2404 return(ENOBUFS); 2405 2406 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2407 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2408 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 2409 sc->txdma[cur] = dma; 2410 sc->bge_txcnt += cnt; 2411 2412 *txidx = frag; 2413 2414 return(0); 2415 } 2416 2417 /* 2418 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2419 * to the mbuf data regions directly in the transmit descriptors. 2420 */ 2421 void 2422 bge_start(ifp) 2423 struct ifnet *ifp; 2424 { 2425 struct bge_softc *sc; 2426 struct mbuf *m_head = NULL; 2427 u_int32_t prodidx = 0; 2428 int pkts = 0; 2429 2430 sc = ifp->if_softc; 2431 2432 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2433 return; 2434 2435 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2436 2437 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2438 IFQ_POLL(&ifp->if_snd, m_head); 2439 if (m_head == NULL) 2440 break; 2441 2442 #if 0 2443 /* 2444 * XXX 2445 * safety overkill. If this is a fragmented packet chain 2446 * with delayed TCP/UDP checksums, then only encapsulate 2447 * it if we have enough descriptors to handle the entire 2448 * chain at once. 2449 * (paranoia -- may not actually be needed) 2450 */ 2451 if (m_head->m_flags & M_FIRSTFRAG && 2452 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2453 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2454 m_head->m_pkthdr.csum_data + 16) { 2455 ifp->if_flags |= IFF_OACTIVE; 2456 break; 2457 } 2458 } 2459 #endif 2460 2461 /* 2462 * Pack the data into the transmit ring. If we 2463 * don't have room, set the OACTIVE flag and wait 2464 * for the NIC to drain the ring. 2465 */ 2466 if (bge_encap(sc, m_head, &prodidx)) { 2467 ifp->if_flags |= IFF_OACTIVE; 2468 break; 2469 } 2470 2471 /* now we are committed to transmit the packet */ 2472 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2473 pkts++; 2474 2475 #if NBPFILTER > 0 2476 /* 2477 * If there's a BPF listener, bounce a copy of this frame 2478 * to him. 2479 */ 2480 if (ifp->if_bpf) 2481 bpf_mtap(ifp->if_bpf, m_head); 2482 #endif 2483 } 2484 if (pkts == 0) 2485 return; 2486 2487 /* Transmit */ 2488 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2489 2490 /* 2491 * Set a timeout in case the chip goes out to lunch. 2492 */ 2493 ifp->if_timer = 5; 2494 } 2495 2496 /* 2497 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2498 * program its internal DSP. Failing to do this can result in 2499 * massive packet loss at 1Gb speeds. 2500 */ 2501 void 2502 bge_phy_hack(sc) 2503 struct bge_softc *sc; 2504 { 2505 struct bge_bcom_hack bhack[] = { 2506 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2507 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2508 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2509 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2510 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2511 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2512 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2513 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2514 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2515 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2516 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2517 { 0, 0 } }; 2518 u_int16_t vid, did; 2519 int i; 2520 2521 vid = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR1); 2522 did = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR2); 2523 2524 if (MII_OUI(vid, did) == MII_OUI_BROADCOM && 2525 (MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5400 || 2526 MII_MODEL(did) == MII_MODEL_BROADCOM_BCM5401)) { 2527 i = 0; 2528 while (bhack[i].reg) { 2529 bge_miibus_writereg(&sc->bge_dev, 1, bhack[i].reg, 2530 bhack[i].val); 2531 i++; 2532 } 2533 } 2534 } 2535 2536 int 2537 bge_init(ifp) 2538 struct ifnet *ifp; 2539 { 2540 struct bge_softc *sc = ifp->if_softc; 2541 u_int16_t *m; 2542 int s, error; 2543 2544 s = splnet(); 2545 2546 ifp = &sc->ethercom.ec_if; 2547 2548 /* Cancel pending I/O and flush buffers. */ 2549 bge_stop(sc); 2550 bge_reset(sc); 2551 bge_chipinit(sc); 2552 2553 /* 2554 * Init the various state machines, ring 2555 * control blocks and firmware. 2556 */ 2557 error = bge_blockinit(sc); 2558 if (error != 0) { 2559 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 2560 error); 2561 splx(s); 2562 return error; 2563 } 2564 2565 ifp = &sc->ethercom.ec_if; 2566 2567 /* Specify MTU. */ 2568 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2569 ETHER_HDR_LEN + ETHER_CRC_LEN); 2570 2571 /* Load our MAC address. */ 2572 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 2573 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2574 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2575 2576 /* Enable or disable promiscuous mode as needed. */ 2577 if (ifp->if_flags & IFF_PROMISC) { 2578 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2579 } else { 2580 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2581 } 2582 2583 /* Program multicast filter. */ 2584 bge_setmulti(sc); 2585 2586 /* Init RX ring. */ 2587 bge_init_rx_ring_std(sc); 2588 2589 /* Init jumbo RX ring. */ 2590 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2591 bge_init_rx_ring_jumbo(sc); 2592 2593 /* Init our RX return ring index */ 2594 sc->bge_rx_saved_considx = 0; 2595 2596 /* Init TX ring. */ 2597 bge_init_tx_ring(sc); 2598 2599 /* Turn on transmitter */ 2600 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2601 2602 /* Turn on receiver */ 2603 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2604 2605 /* Tell firmware we're alive. */ 2606 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2607 2608 /* Enable host interrupts. */ 2609 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2610 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2611 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2612 2613 bge_ifmedia_upd(ifp); 2614 2615 ifp->if_flags |= IFF_RUNNING; 2616 ifp->if_flags &= ~IFF_OACTIVE; 2617 2618 splx(s); 2619 2620 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 2621 2622 return 0; 2623 } 2624 2625 /* 2626 * Set media options. 2627 */ 2628 int 2629 bge_ifmedia_upd(ifp) 2630 struct ifnet *ifp; 2631 { 2632 struct bge_softc *sc = ifp->if_softc; 2633 struct mii_data *mii = &sc->bge_mii; 2634 struct ifmedia *ifm = &sc->bge_ifmedia; 2635 2636 /* If this is a 1000baseX NIC, enable the TBI port. */ 2637 if (sc->bge_tbi) { 2638 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2639 return(EINVAL); 2640 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2641 case IFM_AUTO: 2642 break; 2643 case IFM_1000_SX: 2644 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2645 BGE_CLRBIT(sc, BGE_MAC_MODE, 2646 BGE_MACMODE_HALF_DUPLEX); 2647 } else { 2648 BGE_SETBIT(sc, BGE_MAC_MODE, 2649 BGE_MACMODE_HALF_DUPLEX); 2650 } 2651 break; 2652 default: 2653 return(EINVAL); 2654 } 2655 return(0); 2656 } 2657 2658 sc->bge_link = 0; 2659 if (mii->mii_instance) { 2660 struct mii_softc *miisc; 2661 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2662 miisc = LIST_NEXT(miisc, mii_list)) 2663 mii_phy_reset(miisc); 2664 } 2665 bge_phy_hack(sc); 2666 mii_mediachg(mii); 2667 2668 return(0); 2669 } 2670 2671 /* 2672 * Report current media status. 2673 */ 2674 void 2675 bge_ifmedia_sts(ifp, ifmr) 2676 struct ifnet *ifp; 2677 struct ifmediareq *ifmr; 2678 { 2679 struct bge_softc *sc = ifp->if_softc; 2680 struct mii_data *mii = &sc->bge_mii; 2681 2682 if (sc->bge_tbi) { 2683 ifmr->ifm_status = IFM_AVALID; 2684 ifmr->ifm_active = IFM_ETHER; 2685 if (CSR_READ_4(sc, BGE_MAC_STS) & 2686 BGE_MACSTAT_TBI_PCS_SYNCHED) 2687 ifmr->ifm_status |= IFM_ACTIVE; 2688 ifmr->ifm_active |= IFM_1000_SX; 2689 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2690 ifmr->ifm_active |= IFM_HDX; 2691 else 2692 ifmr->ifm_active |= IFM_FDX; 2693 return; 2694 } 2695 2696 mii_pollstat(mii); 2697 ifmr->ifm_active = mii->mii_media_active; 2698 ifmr->ifm_status = mii->mii_media_status; 2699 } 2700 2701 int 2702 bge_ioctl(ifp, command, data) 2703 struct ifnet *ifp; 2704 u_long command; 2705 caddr_t data; 2706 { 2707 struct bge_softc *sc = ifp->if_softc; 2708 struct ifreq *ifr = (struct ifreq *) data; 2709 int s, error = 0; 2710 struct mii_data *mii; 2711 2712 s = splnet(); 2713 2714 switch(command) { 2715 case SIOCSIFFLAGS: 2716 if (ifp->if_flags & IFF_UP) { 2717 /* 2718 * If only the state of the PROMISC flag changed, 2719 * then just use the 'set promisc mode' command 2720 * instead of reinitializing the entire NIC. Doing 2721 * a full re-init means reloading the firmware and 2722 * waiting for it to start up, which may take a 2723 * second or two. 2724 */ 2725 if (ifp->if_flags & IFF_RUNNING && 2726 ifp->if_flags & IFF_PROMISC && 2727 !(sc->bge_if_flags & IFF_PROMISC)) { 2728 BGE_SETBIT(sc, BGE_RX_MODE, 2729 BGE_RXMODE_RX_PROMISC); 2730 } else if (ifp->if_flags & IFF_RUNNING && 2731 !(ifp->if_flags & IFF_PROMISC) && 2732 sc->bge_if_flags & IFF_PROMISC) { 2733 BGE_CLRBIT(sc, BGE_RX_MODE, 2734 BGE_RXMODE_RX_PROMISC); 2735 } else 2736 bge_init(ifp); 2737 } else { 2738 if (ifp->if_flags & IFF_RUNNING) { 2739 bge_stop(sc); 2740 } 2741 } 2742 sc->bge_if_flags = ifp->if_flags; 2743 error = 0; 2744 break; 2745 case SIOCSIFMEDIA: 2746 case SIOCGIFMEDIA: 2747 if (sc->bge_tbi) { 2748 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2749 command); 2750 } else { 2751 mii = &sc->bge_mii; 2752 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2753 command); 2754 } 2755 error = 0; 2756 break; 2757 default: 2758 error = ether_ioctl(ifp, command, data); 2759 if (error == ENETRESET) { 2760 bge_setmulti(sc); 2761 error = 0; 2762 } 2763 break; 2764 } 2765 2766 splx(s); 2767 2768 return(error); 2769 } 2770 2771 void 2772 bge_watchdog(ifp) 2773 struct ifnet *ifp; 2774 { 2775 struct bge_softc *sc; 2776 2777 sc = ifp->if_softc; 2778 2779 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2780 2781 ifp->if_flags &= ~IFF_RUNNING; 2782 bge_init(ifp); 2783 2784 ifp->if_oerrors++; 2785 } 2786 2787 /* 2788 * Stop the adapter and free any mbufs allocated to the 2789 * RX and TX lists. 2790 */ 2791 void 2792 bge_stop(sc) 2793 struct bge_softc *sc; 2794 { 2795 struct ifnet *ifp = &sc->ethercom.ec_if; 2796 2797 callout_stop(&sc->bge_timeout); 2798 2799 /* 2800 * Disable all of the receiver blocks 2801 */ 2802 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2803 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2804 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2805 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2806 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2807 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2808 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2809 2810 /* 2811 * Disable all of the transmit blocks 2812 */ 2813 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2814 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2815 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2816 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2817 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2818 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2819 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2820 2821 /* 2822 * Shut down all of the memory managers and related 2823 * state machines. 2824 */ 2825 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2826 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2827 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2828 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2829 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2830 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2831 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2832 2833 /* Disable host interrupts. */ 2834 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2835 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2836 2837 /* 2838 * Tell firmware we're shutting down. 2839 */ 2840 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2841 2842 /* Free the RX lists. */ 2843 bge_free_rx_ring_std(sc); 2844 2845 /* Free jumbo RX list. */ 2846 bge_free_rx_ring_jumbo(sc); 2847 2848 /* Free TX buffers. */ 2849 bge_free_tx_ring(sc); 2850 2851 /* 2852 * Isolate/power down the PHY. 2853 */ 2854 if (!sc->bge_tbi) 2855 mii_down(&sc->bge_mii); 2856 2857 sc->bge_link = 0; 2858 2859 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2860 2861 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2862 } 2863 2864 /* 2865 * Stop all chip I/O so that the kernel's probe routines don't 2866 * get confused by errant DMAs when rebooting. 2867 */ 2868 void 2869 bge_shutdown(xsc) 2870 void *xsc; 2871 { 2872 struct bge_softc *sc = (struct bge_softc *)xsc; 2873 2874 bge_stop(sc); 2875 bge_reset(sc); 2876 } 2877
Indexes created Tue Sep 23 07:09:52 GMT 2025