if_bge.c revision 1.94
1 /* $NetBSD: if_bge.c,v 1.94 2005/11/15 06:05:44 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.94 2005/11/15 06:05:44 jonathan Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 #if NBPFILTER > 0 111 #include <net/bpf.h> 112 #endif 113 114 #include <dev/pci/pcireg.h> 115 #include <dev/pci/pcivar.h> 116 #include <dev/pci/pcidevs.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 #include <dev/mii/miidevs.h> 121 #include <dev/mii/brgphyreg.h> 122 123 #include <dev/pci/if_bgereg.h> 124 125 #include <uvm/uvm_extern.h> 126 127 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 128 129 130 /* 131 * Tunable thresholds for rx-side bge interrupt mitigation. 132 */ 133 134 /* 135 * The pairs of values below were obtained from empirical measurement 136 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 137 * interrupt for every N packets received, where N is, approximately, 138 * the second value (rx_max_bds) in each pair. The values are chosen 139 * such that moving from one pair to the succeeding pair was observed 140 * to roughly halve interrupt rate under sustained input packet load. 141 * The values were empirically chosen to avoid overflowing internal 142 * limits on the bcm5700: inreasing rx_ticks much beyond 600 143 * results in internal wrapping and higher interrupt rates. 144 * The limit of 46 frames was chosen to match NFS workloads. 145 * 146 * These values also work well on bcm5701, bcm5704C, and (less 147 * tested) bcm5703. On other chipsets, (including the Altima chip 148 * family), the larger values may overflow internal chip limits, 149 * leading to increasing interrupt rates rather than lower interrupt 150 * rates. 151 * 152 * Applications using heavy interrupt mitigation (interrupting every 153 * 32 or 46 frames) in both directions may need to increase the TCP 154 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 155 * full link bandwidth, due to ACKs and window updates lingering 156 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 157 */ 158 struct bge_load_rx_thresh { 159 int rx_ticks; 160 int rx_max_bds; } 161 bge_rx_threshes[] = { 162 { 32, 2 }, 163 { 50, 4 }, 164 { 100, 8 }, 165 { 192, 16 }, 166 { 416, 32 }, 167 { 598, 46 } 168 }; 169 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 170 171 /* XXX patchable; should be sysctl'able */ 172 static int bge_auto_thresh = 1; 173 static int bge_rx_thresh_lvl; 174 175 #ifdef __NetBSD__ 176 static int bge_rxthresh_nodenum; 177 #endif /* __NetBSD__ */ 178 179 int bge_probe(struct device *, struct cfdata *, void *); 180 void bge_attach(struct device *, struct device *, void *); 181 void bge_powerhook(int, void *); 182 void bge_release_resources(struct bge_softc *); 183 void bge_txeof(struct bge_softc *); 184 void bge_rxeof(struct bge_softc *); 185 186 void bge_tick(void *); 187 void bge_stats_update(struct bge_softc *); 188 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 189 static __inline int bge_cksum_pad(struct mbuf *pkt); 190 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 191 192 int bge_intr(void *); 193 void bge_start(struct ifnet *); 194 int bge_ioctl(struct ifnet *, u_long, caddr_t); 195 int bge_init(struct ifnet *); 196 void bge_stop(struct bge_softc *); 197 void bge_watchdog(struct ifnet *); 198 void bge_shutdown(void *); 199 int bge_ifmedia_upd(struct ifnet *); 200 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 201 202 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 203 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 204 205 void bge_setmulti(struct bge_softc *); 206 207 void bge_handle_events(struct bge_softc *); 208 int bge_alloc_jumbo_mem(struct bge_softc *); 209 void bge_free_jumbo_mem(struct bge_softc *); 210 void *bge_jalloc(struct bge_softc *); 211 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 212 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 213 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 214 int bge_init_rx_ring_std(struct bge_softc *); 215 void bge_free_rx_ring_std(struct bge_softc *); 216 int bge_init_rx_ring_jumbo(struct bge_softc *); 217 void bge_free_rx_ring_jumbo(struct bge_softc *); 218 void bge_free_tx_ring(struct bge_softc *); 219 int bge_init_tx_ring(struct bge_softc *); 220 221 int bge_chipinit(struct bge_softc *); 222 int bge_blockinit(struct bge_softc *); 223 int bge_setpowerstate(struct bge_softc *, int); 224 225 #ifdef notdef 226 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 227 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 228 void bge_vpd_read(struct bge_softc *); 229 #endif 230 231 u_int32_t bge_readmem_ind(struct bge_softc *, int); 232 void bge_writemem_ind(struct bge_softc *, int, int); 233 #ifdef notdef 234 u_int32_t bge_readreg_ind(struct bge_softc *, int); 235 #endif 236 void bge_writereg_ind(struct bge_softc *, int, int); 237 238 int bge_miibus_readreg(struct device *, int, int); 239 void bge_miibus_writereg(struct device *, int, int, int); 240 void bge_miibus_statchg(struct device *); 241 242 void bge_reset(struct bge_softc *); 243 244 void bge_set_thresh(struct ifnet * /*ifp*/, int /*lvl*/); 245 void bge_update_all_threshes(int /*lvl*/); 246 247 void bge_dump_status(struct bge_softc *); 248 void bge_dump_rxbd(struct bge_rx_bd *); 249 250 #define BGE_DEBUG 251 #ifdef BGE_DEBUG 252 #define DPRINTF(x) if (bgedebug) printf x 253 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 254 int bgedebug = 0; 255 #else 256 #define DPRINTF(x) 257 #define DPRINTFN(n,x) 258 #endif 259 260 #ifdef BGE_EVENT_COUNTERS 261 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 262 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 263 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 264 #else 265 #define BGE_EVCNT_INCR(ev) /* nothing */ 266 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 267 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 268 #endif 269 270 /* Various chip quirks. */ 271 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 272 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 273 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 274 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 275 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 276 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 277 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 278 #define BGE_QUIRK_5705_CORE 0x00000080 279 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 280 281 /* following bugs are common to bcm5700 rev B, all flavours */ 282 #define BGE_QUIRK_5700_COMMON \ 283 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 284 285 CFATTACH_DECL(bge, sizeof(struct bge_softc), 286 bge_probe, bge_attach, NULL, NULL); 287 288 u_int32_t 289 bge_readmem_ind(sc, off) 290 struct bge_softc *sc; 291 int off; 292 { 293 struct pci_attach_args *pa = &(sc->bge_pa); 294 pcireg_t val; 295 296 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 297 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 298 return val; 299 } 300 301 void 302 bge_writemem_ind(sc, off, val) 303 struct bge_softc *sc; 304 int off, val; 305 { 306 struct pci_attach_args *pa = &(sc->bge_pa); 307 308 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 309 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 310 } 311 312 #ifdef notdef 313 u_int32_t 314 bge_readreg_ind(sc, off) 315 struct bge_softc *sc; 316 int off; 317 { 318 struct pci_attach_args *pa = &(sc->bge_pa); 319 320 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 321 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 322 } 323 #endif 324 325 void 326 bge_writereg_ind(sc, off, val) 327 struct bge_softc *sc; 328 int off, val; 329 { 330 struct pci_attach_args *pa = &(sc->bge_pa); 331 332 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 333 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 334 } 335 336 #ifdef notdef 337 u_int8_t 338 bge_vpd_readbyte(sc, addr) 339 struct bge_softc *sc; 340 int addr; 341 { 342 int i; 343 u_int32_t val; 344 struct pci_attach_args *pa = &(sc->bge_pa); 345 346 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 347 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 348 DELAY(10); 349 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 350 BGE_VPD_FLAG) 351 break; 352 } 353 354 if (i == BGE_TIMEOUT) { 355 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 356 return(0); 357 } 358 359 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 360 361 return((val >> ((addr % 4) * 8)) & 0xFF); 362 } 363 364 void 365 bge_vpd_read_res(sc, res, addr) 366 struct bge_softc *sc; 367 struct vpd_res *res; 368 int addr; 369 { 370 int i; 371 u_int8_t *ptr; 372 373 ptr = (u_int8_t *)res; 374 for (i = 0; i < sizeof(struct vpd_res); i++) 375 ptr[i] = bge_vpd_readbyte(sc, i + addr); 376 } 377 378 void 379 bge_vpd_read(sc) 380 struct bge_softc *sc; 381 { 382 int pos = 0, i; 383 struct vpd_res res; 384 385 if (sc->bge_vpd_prodname != NULL) 386 free(sc->bge_vpd_prodname, M_DEVBUF); 387 if (sc->bge_vpd_readonly != NULL) 388 free(sc->bge_vpd_readonly, M_DEVBUF); 389 sc->bge_vpd_prodname = NULL; 390 sc->bge_vpd_readonly = NULL; 391 392 bge_vpd_read_res(sc, &res, pos); 393 394 if (res.vr_id != VPD_RES_ID) { 395 printf("%s: bad VPD resource id: expected %x got %x\n", 396 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 402 if (sc->bge_vpd_prodname == NULL) 403 panic("bge_vpd_read"); 404 for (i = 0; i < res.vr_len; i++) 405 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 406 sc->bge_vpd_prodname[i] = '\0'; 407 pos += i; 408 409 bge_vpd_read_res(sc, &res, pos); 410 411 if (res.vr_id != VPD_RES_READ) { 412 printf("%s: bad VPD resource id: expected %x got %x\n", 413 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 414 return; 415 } 416 417 pos += sizeof(res); 418 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 419 if (sc->bge_vpd_readonly == NULL) 420 panic("bge_vpd_read"); 421 for (i = 0; i < res.vr_len + 1; i++) 422 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 423 } 424 #endif 425 426 /* 427 * Read a byte of data stored in the EEPROM at address 'addr.' The 428 * BCM570x supports both the traditional bitbang interface and an 429 * auto access interface for reading the EEPROM. We use the auto 430 * access method. 431 */ 432 u_int8_t 433 bge_eeprom_getbyte(sc, addr, dest) 434 struct bge_softc *sc; 435 int addr; 436 u_int8_t *dest; 437 { 438 int i; 439 u_int32_t byte = 0; 440 441 /* 442 * Enable use of auto EEPROM access so we can avoid 443 * having to use the bitbang method. 444 */ 445 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 446 447 /* Reset the EEPROM, load the clock period. */ 448 CSR_WRITE_4(sc, BGE_EE_ADDR, 449 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 450 DELAY(20); 451 452 /* Issue the read EEPROM command. */ 453 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 454 455 /* Wait for completion */ 456 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 457 DELAY(10); 458 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 459 break; 460 } 461 462 if (i == BGE_TIMEOUT) { 463 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 464 return(0); 465 } 466 467 /* Get result. */ 468 byte = CSR_READ_4(sc, BGE_EE_DATA); 469 470 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 471 472 return(0); 473 } 474 475 /* 476 * Read a sequence of bytes from the EEPROM. 477 */ 478 int 479 bge_read_eeprom(sc, dest, off, cnt) 480 struct bge_softc *sc; 481 caddr_t dest; 482 int off; 483 int cnt; 484 { 485 int err = 0, i; 486 u_int8_t byte = 0; 487 488 for (i = 0; i < cnt; i++) { 489 err = bge_eeprom_getbyte(sc, off + i, &byte); 490 if (err) 491 break; 492 *(dest + i) = byte; 493 } 494 495 return(err ? 1 : 0); 496 } 497 498 int 499 bge_miibus_readreg(dev, phy, reg) 500 struct device *dev; 501 int phy, reg; 502 { 503 struct bge_softc *sc = (struct bge_softc *)dev; 504 u_int32_t val; 505 u_int32_t saved_autopoll; 506 int i; 507 508 /* 509 * Several chips with builtin PHYs will incorrectly answer to 510 * other PHY instances than the builtin PHY at id 1. 511 */ 512 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 513 return(0); 514 515 /* Reading with autopolling on may trigger PCI errors */ 516 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 517 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 518 CSR_WRITE_4(sc, BGE_MI_MODE, 519 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 520 DELAY(40); 521 } 522 523 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 524 BGE_MIPHY(phy)|BGE_MIREG(reg)); 525 526 for (i = 0; i < BGE_TIMEOUT; i++) { 527 val = CSR_READ_4(sc, BGE_MI_COMM); 528 if (!(val & BGE_MICOMM_BUSY)) 529 break; 530 delay(10); 531 } 532 533 if (i == BGE_TIMEOUT) { 534 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 535 val = 0; 536 goto done; 537 } 538 539 val = CSR_READ_4(sc, BGE_MI_COMM); 540 541 done: 542 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 543 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 544 DELAY(40); 545 } 546 547 if (val & BGE_MICOMM_READFAIL) 548 return(0); 549 550 return(val & 0xFFFF); 551 } 552 553 void 554 bge_miibus_writereg(dev, phy, reg, val) 555 struct device *dev; 556 int phy, reg, val; 557 { 558 struct bge_softc *sc = (struct bge_softc *)dev; 559 u_int32_t saved_autopoll; 560 int i; 561 562 /* Touching the PHY while autopolling is on may trigger PCI errors */ 563 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 564 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 565 delay(40); 566 CSR_WRITE_4(sc, BGE_MI_MODE, 567 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 568 delay(10); /* 40 usec is supposed to be adequate */ 569 } 570 571 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 572 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 573 574 for (i = 0; i < BGE_TIMEOUT; i++) { 575 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 576 break; 577 delay(10); 578 } 579 580 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 581 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 582 delay(40); 583 } 584 585 if (i == BGE_TIMEOUT) { 586 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 587 } 588 } 589 590 void 591 bge_miibus_statchg(dev) 592 struct device *dev; 593 { 594 struct bge_softc *sc = (struct bge_softc *)dev; 595 struct mii_data *mii = &sc->bge_mii; 596 597 /* 598 * Get flow control negotiation result. 599 */ 600 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 601 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 602 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 603 mii->mii_media_active &= ~IFM_ETH_FMASK; 604 } 605 606 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 607 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 608 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 609 } else { 610 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 611 } 612 613 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 614 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 615 } else { 616 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 617 } 618 619 /* 620 * 802.3x flow control 621 */ 622 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 623 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 624 } else { 625 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 626 } 627 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 628 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 629 } else { 630 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 631 } 632 } 633 634 /* 635 * Update rx threshold levels to values in a particular slot 636 * of the interrupt-mitigation table bge_rx_threshes. 637 */ 638 void 639 bge_set_thresh(struct ifnet *ifp, int lvl) 640 { 641 struct bge_softc *sc = ifp->if_softc; 642 int s; 643 644 /* For now, just save the new Rx-intr thresholds and record 645 * that a threshold update is pending. Updating the hardware 646 * registers here (even at splhigh()) is observed to 647 * occasionaly cause glitches where Rx-interrupts are not 648 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 649 */ 650 s = splnet(); 651 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 652 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 653 sc->bge_pending_rxintr_change = 1; 654 splx(s); 655 656 return; 657 } 658 659 660 /* 661 * Update Rx thresholds of all bge devices 662 */ 663 void 664 bge_update_all_threshes(int lvl) 665 { 666 struct ifnet *ifp; 667 const char * const namebuf = "bge"; 668 int namelen; 669 670 if (lvl < 0) 671 lvl = 0; 672 else if( lvl >= NBGE_RX_THRESH) 673 lvl = NBGE_RX_THRESH - 1; 674 675 namelen = strlen(namebuf); 676 /* 677 * Now search all the interfaces for this name/number 678 */ 679 IFNET_FOREACH(ifp) { 680 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 681 continue; 682 /* We got a match: update if doing auto-threshold-tuning */ 683 if (bge_auto_thresh) 684 bge_set_thresh(ifp, lvl); 685 } 686 } 687 688 /* 689 * Handle events that have triggered interrupts. 690 */ 691 void 692 bge_handle_events(sc) 693 struct bge_softc *sc; 694 { 695 696 return; 697 } 698 699 /* 700 * Memory management for jumbo frames. 701 */ 702 703 int 704 bge_alloc_jumbo_mem(sc) 705 struct bge_softc *sc; 706 { 707 caddr_t ptr, kva; 708 bus_dma_segment_t seg; 709 int i, rseg, state, error; 710 struct bge_jpool_entry *entry; 711 712 state = error = 0; 713 714 /* Grab a big chunk o' storage. */ 715 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 716 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 717 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 718 return ENOBUFS; 719 } 720 721 state = 1; 722 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 723 BUS_DMA_NOWAIT)) { 724 printf("%s: can't map DMA buffers (%d bytes)\n", 725 sc->bge_dev.dv_xname, (int)BGE_JMEM); 726 error = ENOBUFS; 727 goto out; 728 } 729 730 state = 2; 731 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 732 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 733 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 734 error = ENOBUFS; 735 goto out; 736 } 737 738 state = 3; 739 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 740 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 741 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 742 error = ENOBUFS; 743 goto out; 744 } 745 746 state = 4; 747 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 748 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 749 750 SLIST_INIT(&sc->bge_jfree_listhead); 751 SLIST_INIT(&sc->bge_jinuse_listhead); 752 753 /* 754 * Now divide it up into 9K pieces and save the addresses 755 * in an array. 756 */ 757 ptr = sc->bge_cdata.bge_jumbo_buf; 758 for (i = 0; i < BGE_JSLOTS; i++) { 759 sc->bge_cdata.bge_jslots[i] = ptr; 760 ptr += BGE_JLEN; 761 entry = malloc(sizeof(struct bge_jpool_entry), 762 M_DEVBUF, M_NOWAIT); 763 if (entry == NULL) { 764 printf("%s: no memory for jumbo buffer queue!\n", 765 sc->bge_dev.dv_xname); 766 error = ENOBUFS; 767 goto out; 768 } 769 entry->slot = i; 770 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 771 entry, jpool_entries); 772 } 773 out: 774 if (error != 0) { 775 switch (state) { 776 case 4: 777 bus_dmamap_unload(sc->bge_dmatag, 778 sc->bge_cdata.bge_rx_jumbo_map); 779 case 3: 780 bus_dmamap_destroy(sc->bge_dmatag, 781 sc->bge_cdata.bge_rx_jumbo_map); 782 case 2: 783 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 784 case 1: 785 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 786 break; 787 default: 788 break; 789 } 790 } 791 792 return error; 793 } 794 795 /* 796 * Allocate a jumbo buffer. 797 */ 798 void * 799 bge_jalloc(sc) 800 struct bge_softc *sc; 801 { 802 struct bge_jpool_entry *entry; 803 804 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 805 806 if (entry == NULL) { 807 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 808 return(NULL); 809 } 810 811 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 812 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 813 return(sc->bge_cdata.bge_jslots[entry->slot]); 814 } 815 816 /* 817 * Release a jumbo buffer. 818 */ 819 void 820 bge_jfree(m, buf, size, arg) 821 struct mbuf *m; 822 caddr_t buf; 823 size_t size; 824 void *arg; 825 { 826 struct bge_jpool_entry *entry; 827 struct bge_softc *sc; 828 int i, s; 829 830 /* Extract the softc struct pointer. */ 831 sc = (struct bge_softc *)arg; 832 833 if (sc == NULL) 834 panic("bge_jfree: can't find softc pointer!"); 835 836 /* calculate the slot this buffer belongs to */ 837 838 i = ((caddr_t)buf 839 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 840 841 if ((i < 0) || (i >= BGE_JSLOTS)) 842 panic("bge_jfree: asked to free buffer that we don't manage!"); 843 844 s = splvm(); 845 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 846 if (entry == NULL) 847 panic("bge_jfree: buffer not in use!"); 848 entry->slot = i; 849 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 850 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 851 852 if (__predict_true(m != NULL)) 853 pool_cache_put(&mbpool_cache, m); 854 splx(s); 855 } 856 857 858 /* 859 * Intialize a standard receive ring descriptor. 860 */ 861 int 862 bge_newbuf_std(sc, i, m, dmamap) 863 struct bge_softc *sc; 864 int i; 865 struct mbuf *m; 866 bus_dmamap_t dmamap; 867 { 868 struct mbuf *m_new = NULL; 869 struct bge_rx_bd *r; 870 int error; 871 872 if (dmamap == NULL) { 873 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 874 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 875 if (error != 0) 876 return error; 877 } 878 879 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 880 881 if (m == NULL) { 882 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 883 if (m_new == NULL) { 884 return(ENOBUFS); 885 } 886 887 MCLGET(m_new, M_DONTWAIT); 888 if (!(m_new->m_flags & M_EXT)) { 889 m_freem(m_new); 890 return(ENOBUFS); 891 } 892 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 893 if (!sc->bge_rx_alignment_bug) 894 m_adj(m_new, ETHER_ALIGN); 895 896 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 897 BUS_DMA_READ|BUS_DMA_NOWAIT)) 898 return(ENOBUFS); 899 } else { 900 m_new = m; 901 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 902 m_new->m_data = m_new->m_ext.ext_buf; 903 if (!sc->bge_rx_alignment_bug) 904 m_adj(m_new, ETHER_ALIGN); 905 } 906 907 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 908 r = &sc->bge_rdata->bge_rx_std_ring[i]; 909 bge_set_hostaddr(&r->bge_addr, 910 dmamap->dm_segs[0].ds_addr); 911 r->bge_flags = BGE_RXBDFLAG_END; 912 r->bge_len = m_new->m_len; 913 r->bge_idx = i; 914 915 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 916 offsetof(struct bge_ring_data, bge_rx_std_ring) + 917 i * sizeof (struct bge_rx_bd), 918 sizeof (struct bge_rx_bd), 919 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 920 921 return(0); 922 } 923 924 /* 925 * Initialize a jumbo receive ring descriptor. This allocates 926 * a jumbo buffer from the pool managed internally by the driver. 927 */ 928 int 929 bge_newbuf_jumbo(sc, i, m) 930 struct bge_softc *sc; 931 int i; 932 struct mbuf *m; 933 { 934 struct mbuf *m_new = NULL; 935 struct bge_rx_bd *r; 936 937 if (m == NULL) { 938 caddr_t buf = NULL; 939 940 /* Allocate the mbuf. */ 941 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 942 if (m_new == NULL) { 943 return(ENOBUFS); 944 } 945 946 /* Allocate the jumbo buffer */ 947 buf = bge_jalloc(sc); 948 if (buf == NULL) { 949 m_freem(m_new); 950 printf("%s: jumbo allocation failed " 951 "-- packet dropped!\n", sc->bge_dev.dv_xname); 952 return(ENOBUFS); 953 } 954 955 /* Attach the buffer to the mbuf. */ 956 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 957 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 958 bge_jfree, sc); 959 m_new->m_flags |= M_EXT_RW; 960 } else { 961 m_new = m; 962 m_new->m_data = m_new->m_ext.ext_buf; 963 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 964 } 965 966 if (!sc->bge_rx_alignment_bug) 967 m_adj(m_new, ETHER_ALIGN); 968 /* Set up the descriptor. */ 969 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 970 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 971 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 972 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 973 r->bge_len = m_new->m_len; 974 r->bge_idx = i; 975 976 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 977 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 978 i * sizeof (struct bge_rx_bd), 979 sizeof (struct bge_rx_bd), 980 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 981 982 return(0); 983 } 984 985 /* 986 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 987 * that's 1MB or memory, which is a lot. For now, we fill only the first 988 * 256 ring entries and hope that our CPU is fast enough to keep up with 989 * the NIC. 990 */ 991 int 992 bge_init_rx_ring_std(sc) 993 struct bge_softc *sc; 994 { 995 int i; 996 997 if (sc->bge_flags & BGE_RXRING_VALID) 998 return 0; 999 1000 for (i = 0; i < BGE_SSLOTS; i++) { 1001 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1002 return(ENOBUFS); 1003 } 1004 1005 sc->bge_std = i - 1; 1006 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1007 1008 sc->bge_flags |= BGE_RXRING_VALID; 1009 1010 return(0); 1011 } 1012 1013 void 1014 bge_free_rx_ring_std(sc) 1015 struct bge_softc *sc; 1016 { 1017 int i; 1018 1019 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1020 return; 1021 1022 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1023 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1024 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1025 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1026 bus_dmamap_destroy(sc->bge_dmatag, 1027 sc->bge_cdata.bge_rx_std_map[i]); 1028 } 1029 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1030 sizeof(struct bge_rx_bd)); 1031 } 1032 1033 sc->bge_flags &= ~BGE_RXRING_VALID; 1034 } 1035 1036 int 1037 bge_init_rx_ring_jumbo(sc) 1038 struct bge_softc *sc; 1039 { 1040 int i; 1041 volatile struct bge_rcb *rcb; 1042 1043 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1044 return 0; 1045 1046 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1047 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1048 return(ENOBUFS); 1049 }; 1050 1051 sc->bge_jumbo = i - 1; 1052 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1053 1054 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1055 rcb->bge_maxlen_flags = 0; 1056 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1057 1058 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1059 1060 return(0); 1061 } 1062 1063 void 1064 bge_free_rx_ring_jumbo(sc) 1065 struct bge_softc *sc; 1066 { 1067 int i; 1068 1069 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1070 return; 1071 1072 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1073 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1074 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1075 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1076 } 1077 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1078 sizeof(struct bge_rx_bd)); 1079 } 1080 1081 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1082 } 1083 1084 void 1085 bge_free_tx_ring(sc) 1086 struct bge_softc *sc; 1087 { 1088 int i, freed; 1089 struct txdmamap_pool_entry *dma; 1090 1091 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1092 return; 1093 1094 freed = 0; 1095 1096 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1097 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1098 freed++; 1099 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1100 sc->bge_cdata.bge_tx_chain[i] = NULL; 1101 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1102 link); 1103 sc->txdma[i] = 0; 1104 } 1105 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1106 sizeof(struct bge_tx_bd)); 1107 } 1108 1109 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1110 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1111 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1112 free(dma, M_DEVBUF); 1113 } 1114 1115 sc->bge_flags &= ~BGE_TXRING_VALID; 1116 } 1117 1118 int 1119 bge_init_tx_ring(sc) 1120 struct bge_softc *sc; 1121 { 1122 int i; 1123 bus_dmamap_t dmamap; 1124 struct txdmamap_pool_entry *dma; 1125 1126 if (sc->bge_flags & BGE_TXRING_VALID) 1127 return 0; 1128 1129 sc->bge_txcnt = 0; 1130 sc->bge_tx_saved_considx = 0; 1131 1132 /* Initialize transmit producer index for host-memory send ring. */ 1133 sc->bge_tx_prodidx = 0; 1134 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1135 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1136 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1137 1138 /* NIC-memory send ring not used; initialize to zero. */ 1139 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1140 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1141 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1142 1143 SLIST_INIT(&sc->txdma_list); 1144 for (i = 0; i < BGE_RSLOTS; i++) { 1145 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 1146 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1147 &dmamap)) 1148 return(ENOBUFS); 1149 if (dmamap == NULL) 1150 panic("dmamap NULL in bge_init_tx_ring"); 1151 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1152 if (dma == NULL) { 1153 printf("%s: can't alloc txdmamap_pool_entry\n", 1154 sc->bge_dev.dv_xname); 1155 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1156 return (ENOMEM); 1157 } 1158 dma->dmamap = dmamap; 1159 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1160 } 1161 1162 sc->bge_flags |= BGE_TXRING_VALID; 1163 1164 return(0); 1165 } 1166 1167 void 1168 bge_setmulti(sc) 1169 struct bge_softc *sc; 1170 { 1171 struct ethercom *ac = &sc->ethercom; 1172 struct ifnet *ifp = &ac->ec_if; 1173 struct ether_multi *enm; 1174 struct ether_multistep step; 1175 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1176 u_int32_t h; 1177 int i; 1178 1179 if (ifp->if_flags & IFF_PROMISC) 1180 goto allmulti; 1181 1182 /* Now program new ones. */ 1183 ETHER_FIRST_MULTI(step, ac, enm); 1184 while (enm != NULL) { 1185 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1186 /* 1187 * We must listen to a range of multicast addresses. 1188 * For now, just accept all multicasts, rather than 1189 * trying to set only those filter bits needed to match 1190 * the range. (At this time, the only use of address 1191 * ranges is for IP multicast routing, for which the 1192 * range is big enough to require all bits set.) 1193 */ 1194 goto allmulti; 1195 } 1196 1197 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1198 1199 /* Just want the 7 least-significant bits. */ 1200 h &= 0x7f; 1201 1202 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1203 ETHER_NEXT_MULTI(step, enm); 1204 } 1205 1206 ifp->if_flags &= ~IFF_ALLMULTI; 1207 goto setit; 1208 1209 allmulti: 1210 ifp->if_flags |= IFF_ALLMULTI; 1211 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1212 1213 setit: 1214 for (i = 0; i < 4; i++) 1215 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1216 } 1217 1218 const int bge_swapbits[] = { 1219 0, 1220 BGE_MODECTL_BYTESWAP_DATA, 1221 BGE_MODECTL_WORDSWAP_DATA, 1222 BGE_MODECTL_BYTESWAP_NONFRAME, 1223 BGE_MODECTL_WORDSWAP_NONFRAME, 1224 1225 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1226 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1227 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1228 1229 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1230 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1231 1232 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1233 1234 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1235 BGE_MODECTL_BYTESWAP_NONFRAME, 1236 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1237 BGE_MODECTL_WORDSWAP_NONFRAME, 1238 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1239 BGE_MODECTL_WORDSWAP_NONFRAME, 1240 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1241 BGE_MODECTL_WORDSWAP_NONFRAME, 1242 1243 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1244 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1245 }; 1246 1247 int bge_swapindex = 0; 1248 1249 /* 1250 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1251 * self-test results. 1252 */ 1253 int 1254 bge_chipinit(sc) 1255 struct bge_softc *sc; 1256 { 1257 u_int32_t cachesize; 1258 int i; 1259 u_int32_t dma_rw_ctl; 1260 struct pci_attach_args *pa = &(sc->bge_pa); 1261 1262 1263 /* Set endianness before we access any non-PCI registers. */ 1264 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1265 BGE_INIT); 1266 1267 /* Set power state to D0. */ 1268 bge_setpowerstate(sc, 0); 1269 1270 /* 1271 * Check the 'ROM failed' bit on the RX CPU to see if 1272 * self-tests passed. 1273 */ 1274 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1275 printf("%s: RX CPU self-diagnostics failed!\n", 1276 sc->bge_dev.dv_xname); 1277 return(ENODEV); 1278 } 1279 1280 /* Clear the MAC control register */ 1281 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1282 1283 /* 1284 * Clear the MAC statistics block in the NIC's 1285 * internal memory. 1286 */ 1287 for (i = BGE_STATS_BLOCK; 1288 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1289 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1290 1291 for (i = BGE_STATUS_BLOCK; 1292 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1293 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1294 1295 /* Set up the PCI DMA control register. */ 1296 if (sc->bge_pcie) { 1297 /* From FreeBSD */ 1298 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1299 sc->bge_dev.dv_xname)); 1300 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1301 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1302 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1303 } else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1304 BGE_PCISTATE_PCI_BUSMODE) { 1305 /* Conventional PCI bus */ 1306 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1307 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1308 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1309 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1310 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1311 dma_rw_ctl |= 0x0F; 1312 } 1313 } else { 1314 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1315 /* PCI-X bus */ 1316 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1317 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1318 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1319 (0x0F); 1320 /* 1321 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1322 * for hardware bugs, which means we should also clear 1323 * the low-order MINDMA bits. In addition, the 5704 1324 * uses a different encoding of read/write watermarks. 1325 */ 1326 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1327 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1328 /* should be 0x1f0000 */ 1329 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1330 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1331 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1332 } 1333 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1334 dma_rw_ctl &= 0xfffffff0; 1335 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1336 } 1337 } 1338 1339 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1340 1341 /* 1342 * Set up general mode register. 1343 */ 1344 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1345 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1346 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1347 1348 /* Get cache line size. */ 1349 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1350 1351 /* 1352 * Avoid violating PCI spec on certain chip revs. 1353 */ 1354 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1355 PCIM_CMD_MWIEN) { 1356 switch(cachesize) { 1357 case 1: 1358 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1359 BGE_PCI_WRITE_BNDRY_16BYTES); 1360 break; 1361 case 2: 1362 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1363 BGE_PCI_WRITE_BNDRY_32BYTES); 1364 break; 1365 case 4: 1366 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1367 BGE_PCI_WRITE_BNDRY_64BYTES); 1368 break; 1369 case 8: 1370 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1371 BGE_PCI_WRITE_BNDRY_128BYTES); 1372 break; 1373 case 16: 1374 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1375 BGE_PCI_WRITE_BNDRY_256BYTES); 1376 break; 1377 case 32: 1378 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1379 BGE_PCI_WRITE_BNDRY_512BYTES); 1380 break; 1381 case 64: 1382 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1383 BGE_PCI_WRITE_BNDRY_1024BYTES); 1384 break; 1385 default: 1386 /* Disable PCI memory write and invalidate. */ 1387 #if 0 1388 if (bootverbose) 1389 printf("%s: cache line size %d not " 1390 "supported; disabling PCI MWI\n", 1391 sc->bge_dev.dv_xname, cachesize); 1392 #endif 1393 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1394 PCIM_CMD_MWIEN); 1395 break; 1396 } 1397 } 1398 1399 /* 1400 * Disable memory write invalidate. Apparently it is not supported 1401 * properly by these devices. 1402 */ 1403 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1404 1405 1406 #ifdef __brokenalpha__ 1407 /* 1408 * Must insure that we do not cross an 8K (bytes) boundary 1409 * for DMA reads. Our highest limit is 1K bytes. This is a 1410 * restriction on some ALPHA platforms with early revision 1411 * 21174 PCI chipsets, such as the AlphaPC 164lx 1412 */ 1413 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1414 #endif 1415 1416 /* Set the timer prescaler (always 66MHz) */ 1417 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1418 1419 return(0); 1420 } 1421 1422 int 1423 bge_blockinit(sc) 1424 struct bge_softc *sc; 1425 { 1426 volatile struct bge_rcb *rcb; 1427 bus_size_t rcb_addr; 1428 int i; 1429 struct ifnet *ifp = &sc->ethercom.ec_if; 1430 bge_hostaddr taddr; 1431 1432 /* 1433 * Initialize the memory window pointer register so that 1434 * we can access the first 32K of internal NIC RAM. This will 1435 * allow us to set up the TX send ring RCBs and the RX return 1436 * ring RCBs, plus other things which live in NIC memory. 1437 */ 1438 1439 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1440 BGE_PCI_MEMWIN_BASEADDR, 0); 1441 1442 /* Configure mbuf memory pool */ 1443 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1444 if (sc->bge_extram) { 1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1446 BGE_EXT_SSRAM); 1447 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1448 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1449 else 1450 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1451 } else { 1452 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1453 BGE_BUFFPOOL_1); 1454 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1455 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1456 else 1457 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1458 } 1459 1460 /* Configure DMA resource pool */ 1461 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1462 BGE_DMA_DESCRIPTORS); 1463 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1464 } 1465 1466 /* Configure mbuf pool watermarks */ 1467 #ifdef ORIG_WPAUL_VALUES 1468 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1469 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1470 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1471 #else 1472 /* new broadcom docs strongly recommend these: */ 1473 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1474 if (ifp->if_mtu > ETHER_MAX_LEN) { 1475 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1476 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1477 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1478 } else { 1479 /* Values from Linux driver... */ 1480 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1481 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1482 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1483 } 1484 } else { 1485 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1486 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1487 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1488 } 1489 #endif 1490 1491 /* Configure DMA resource watermarks */ 1492 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1493 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1494 1495 /* Enable buffer manager */ 1496 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1497 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1498 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1499 1500 /* Poll for buffer manager start indication */ 1501 for (i = 0; i < BGE_TIMEOUT; i++) { 1502 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1503 break; 1504 DELAY(10); 1505 } 1506 1507 if (i == BGE_TIMEOUT) { 1508 printf("%s: buffer manager failed to start\n", 1509 sc->bge_dev.dv_xname); 1510 return(ENXIO); 1511 } 1512 } 1513 1514 /* Enable flow-through queues */ 1515 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1516 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1517 1518 /* Wait until queue initialization is complete */ 1519 for (i = 0; i < BGE_TIMEOUT; i++) { 1520 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1521 break; 1522 DELAY(10); 1523 } 1524 1525 if (i == BGE_TIMEOUT) { 1526 printf("%s: flow-through queue init failed\n", 1527 sc->bge_dev.dv_xname); 1528 return(ENXIO); 1529 } 1530 1531 /* Initialize the standard RX ring control block */ 1532 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1533 bge_set_hostaddr(&rcb->bge_hostaddr, 1534 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1535 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1536 rcb->bge_maxlen_flags = 1537 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1538 } else { 1539 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1540 } 1541 if (sc->bge_extram) 1542 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1543 else 1544 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1545 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1546 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1547 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1548 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1549 1550 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1551 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1552 } else { 1553 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1554 } 1555 1556 /* 1557 * Initialize the jumbo RX ring control block 1558 * We set the 'ring disabled' bit in the flags 1559 * field until we're actually ready to start 1560 * using this ring (i.e. once we set the MTU 1561 * high enough to require it). 1562 */ 1563 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1564 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1565 bge_set_hostaddr(&rcb->bge_hostaddr, 1566 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1567 rcb->bge_maxlen_flags = 1568 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1569 BGE_RCB_FLAG_RING_DISABLED); 1570 if (sc->bge_extram) 1571 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1572 else 1573 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1574 1575 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1576 rcb->bge_hostaddr.bge_addr_hi); 1577 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1578 rcb->bge_hostaddr.bge_addr_lo); 1579 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1580 rcb->bge_maxlen_flags); 1581 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1582 1583 /* Set up dummy disabled mini ring RCB */ 1584 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1585 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1586 BGE_RCB_FLAG_RING_DISABLED); 1587 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1588 rcb->bge_maxlen_flags); 1589 1590 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1591 offsetof(struct bge_ring_data, bge_info), 1592 sizeof (struct bge_gib), 1593 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1594 } 1595 1596 /* 1597 * Set the BD ring replentish thresholds. The recommended 1598 * values are 1/8th the number of descriptors allocated to 1599 * each ring. 1600 */ 1601 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1602 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1603 1604 /* 1605 * Disable all unused send rings by setting the 'ring disabled' 1606 * bit in the flags field of all the TX send ring control blocks. 1607 * These are located in NIC memory. 1608 */ 1609 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1610 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1611 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1612 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1613 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1614 rcb_addr += sizeof(struct bge_rcb); 1615 } 1616 1617 /* Configure TX RCB 0 (we use only the first ring) */ 1618 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1619 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1620 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1621 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1622 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1623 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1624 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1625 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1626 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1627 } 1628 1629 /* Disable all unused RX return rings */ 1630 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1631 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1632 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1633 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1634 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1635 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1636 BGE_RCB_FLAG_RING_DISABLED)); 1637 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1638 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1639 (i * (sizeof(u_int64_t))), 0); 1640 rcb_addr += sizeof(struct bge_rcb); 1641 } 1642 1643 /* Initialize RX ring indexes */ 1644 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1645 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1646 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1647 1648 /* 1649 * Set up RX return ring 0 1650 * Note that the NIC address for RX return rings is 0x00000000. 1651 * The return rings live entirely within the host, so the 1652 * nicaddr field in the RCB isn't used. 1653 */ 1654 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1655 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1656 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1657 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1658 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1659 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1660 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1661 1662 /* Set random backoff seed for TX */ 1663 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1664 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1665 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1666 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1667 BGE_TX_BACKOFF_SEED_MASK); 1668 1669 /* Set inter-packet gap */ 1670 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1671 1672 /* 1673 * Specify which ring to use for packets that don't match 1674 * any RX rules. 1675 */ 1676 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1677 1678 /* 1679 * Configure number of RX lists. One interrupt distribution 1680 * list, sixteen active lists, one bad frames class. 1681 */ 1682 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1683 1684 /* Inialize RX list placement stats mask. */ 1685 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1686 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1687 1688 /* Disable host coalescing until we get it set up */ 1689 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1690 1691 /* Poll to make sure it's shut down. */ 1692 for (i = 0; i < BGE_TIMEOUT; i++) { 1693 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1694 break; 1695 DELAY(10); 1696 } 1697 1698 if (i == BGE_TIMEOUT) { 1699 printf("%s: host coalescing engine failed to idle\n", 1700 sc->bge_dev.dv_xname); 1701 return(ENXIO); 1702 } 1703 1704 /* Set up host coalescing defaults */ 1705 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1706 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1707 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1708 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1709 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1710 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1711 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1712 } 1713 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1714 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1715 1716 /* Set up address of statistics block */ 1717 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1718 bge_set_hostaddr(&taddr, 1719 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1720 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1721 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1722 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1723 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1724 } 1725 1726 /* Set up address of status block */ 1727 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1728 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1729 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1730 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1731 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1732 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1733 1734 /* Turn on host coalescing state machine */ 1735 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1736 1737 /* Turn on RX BD completion state machine and enable attentions */ 1738 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1739 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1740 1741 /* Turn on RX list placement state machine */ 1742 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1743 1744 /* Turn on RX list selector state machine. */ 1745 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1746 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1747 } 1748 1749 /* Turn on DMA, clear stats */ 1750 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1751 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1752 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1753 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1754 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1755 1756 /* Set misc. local control, enable interrupts on attentions */ 1757 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1758 1759 #ifdef notdef 1760 /* Assert GPIO pins for PHY reset */ 1761 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1762 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1763 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1764 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1765 #endif 1766 1767 #if defined(not_quite_yet) 1768 /* Linux driver enables enable gpio pin #1 on 5700s */ 1769 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1770 sc->bge_local_ctrl_reg |= 1771 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1772 } 1773 #endif 1774 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1775 1776 /* Turn on DMA completion state machine */ 1777 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1778 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1779 } 1780 1781 /* Turn on write DMA state machine */ 1782 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1783 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1784 1785 /* Turn on read DMA state machine */ 1786 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1787 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1788 1789 /* Turn on RX data completion state machine */ 1790 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1791 1792 /* Turn on RX BD initiator state machine */ 1793 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1794 1795 /* Turn on RX data and RX BD initiator state machine */ 1796 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1797 1798 /* Turn on Mbuf cluster free state machine */ 1799 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1800 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1801 } 1802 1803 /* Turn on send BD completion state machine */ 1804 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1805 1806 /* Turn on send data completion state machine */ 1807 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1808 1809 /* Turn on send data initiator state machine */ 1810 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1811 1812 /* Turn on send BD initiator state machine */ 1813 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1814 1815 /* Turn on send BD selector state machine */ 1816 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1817 1818 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1819 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1820 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1821 1822 /* ack/clear link change events */ 1823 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1824 BGE_MACSTAT_CFG_CHANGED); 1825 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1826 1827 /* Enable PHY auto polling (for MII/GMII only) */ 1828 if (sc->bge_tbi) { 1829 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1830 } else { 1831 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1832 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1833 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1834 BGE_EVTENB_MI_INTERRUPT); 1835 } 1836 1837 /* Enable link state change attentions. */ 1838 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1839 1840 return(0); 1841 } 1842 1843 static const struct bge_revision { 1844 uint32_t br_chipid; 1845 uint32_t br_quirks; 1846 const char *br_name; 1847 } bge_revisions[] = { 1848 { BGE_CHIPID_BCM5700_A0, 1849 BGE_QUIRK_LINK_STATE_BROKEN, 1850 "BCM5700 A0" }, 1851 1852 { BGE_CHIPID_BCM5700_A1, 1853 BGE_QUIRK_LINK_STATE_BROKEN, 1854 "BCM5700 A1" }, 1855 1856 { BGE_CHIPID_BCM5700_B0, 1857 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1858 "BCM5700 B0" }, 1859 1860 { BGE_CHIPID_BCM5700_B1, 1861 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1862 "BCM5700 B1" }, 1863 1864 { BGE_CHIPID_BCM5700_B2, 1865 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1866 "BCM5700 B2" }, 1867 1868 /* This is treated like a BCM5700 Bx */ 1869 { BGE_CHIPID_BCM5700_ALTIMA, 1870 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1871 "BCM5700 Altima" }, 1872 1873 { BGE_CHIPID_BCM5700_C0, 1874 0, 1875 "BCM5700 C0" }, 1876 1877 { BGE_CHIPID_BCM5701_A0, 1878 0, /*XXX really, just not known */ 1879 "BCM5701 A0" }, 1880 1881 { BGE_CHIPID_BCM5701_B0, 1882 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1883 "BCM5701 B0" }, 1884 1885 { BGE_CHIPID_BCM5701_B2, 1886 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1887 "BCM5701 B2" }, 1888 1889 { BGE_CHIPID_BCM5701_B5, 1890 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1891 "BCM5701 B5" }, 1892 1893 { BGE_CHIPID_BCM5703_A0, 1894 0, 1895 "BCM5703 A0" }, 1896 1897 { BGE_CHIPID_BCM5703_A1, 1898 0, 1899 "BCM5703 A1" }, 1900 1901 { BGE_CHIPID_BCM5703_A2, 1902 BGE_QUIRK_ONLY_PHY_1, 1903 "BCM5703 A2" }, 1904 1905 { BGE_CHIPID_BCM5703_A3, 1906 BGE_QUIRK_ONLY_PHY_1, 1907 "BCM5703 A3" }, 1908 1909 { BGE_CHIPID_BCM5704_A0, 1910 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1911 "BCM5704 A0" }, 1912 1913 { BGE_CHIPID_BCM5704_A1, 1914 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1915 "BCM5704 A1" }, 1916 1917 { BGE_CHIPID_BCM5704_A2, 1918 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1919 "BCM5704 A2" }, 1920 1921 { BGE_CHIPID_BCM5704_A3, 1922 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1923 "BCM5704 A3" }, 1924 1925 { BGE_CHIPID_BCM5705_A0, 1926 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1927 "BCM5705 A0" }, 1928 1929 { BGE_CHIPID_BCM5705_A1, 1930 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1931 "BCM5705 A1" }, 1932 1933 { BGE_CHIPID_BCM5705_A2, 1934 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1935 "BCM5705 A2" }, 1936 1937 { BGE_CHIPID_BCM5705_A3, 1938 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1939 "BCM5705 A3" }, 1940 1941 { BGE_CHIPID_BCM5750_A0, 1942 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1943 "BCM5750 A1" }, 1944 1945 { BGE_CHIPID_BCM5750_A1, 1946 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1947 "BCM5750 A1" }, 1948 1949 { BGE_CHIPID_BCM5751_A1, 1950 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1951 "BCM5751 A1" }, 1952 1953 { 0, 0, NULL } 1954 }; 1955 1956 /* 1957 * Some defaults for major revisions, so that newer steppings 1958 * that we don't know about have a shot at working. 1959 */ 1960 static const struct bge_revision bge_majorrevs[] = { 1961 { BGE_ASICREV_BCM5700, 1962 BGE_QUIRK_LINK_STATE_BROKEN, 1963 "unknown BCM5700" }, 1964 1965 { BGE_ASICREV_BCM5701, 1966 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1967 "unknown BCM5701" }, 1968 1969 { BGE_ASICREV_BCM5703, 1970 0, 1971 "unknown BCM5703" }, 1972 1973 { BGE_ASICREV_BCM5704, 1974 BGE_QUIRK_ONLY_PHY_1, 1975 "unknown BCM5704" }, 1976 1977 { BGE_ASICREV_BCM5705, 1978 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1979 "unknown BCM5705" }, 1980 1981 { BGE_ASICREV_BCM5750, 1982 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1983 "unknown BCM5750" }, 1984 1985 { 0, 1986 0, 1987 NULL } 1988 }; 1989 1990 1991 static const struct bge_revision * 1992 bge_lookup_rev(uint32_t chipid) 1993 { 1994 const struct bge_revision *br; 1995 1996 for (br = bge_revisions; br->br_name != NULL; br++) { 1997 if (br->br_chipid == chipid) 1998 return (br); 1999 } 2000 2001 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2002 if (br->br_chipid == BGE_ASICREV(chipid)) 2003 return (br); 2004 } 2005 2006 return (NULL); 2007 } 2008 2009 static const struct bge_product { 2010 pci_vendor_id_t bp_vendor; 2011 pci_product_id_t bp_product; 2012 const char *bp_name; 2013 } bge_products[] = { 2014 /* 2015 * The BCM5700 documentation seems to indicate that the hardware 2016 * still has the Alteon vendor ID burned into it, though it 2017 * should always be overridden by the value in the EEPROM. We'll 2018 * check for it anyway. 2019 */ 2020 { PCI_VENDOR_ALTEON, 2021 PCI_PRODUCT_ALTEON_BCM5700, 2022 "Broadcom BCM5700 Gigabit Ethernet", 2023 }, 2024 { PCI_VENDOR_ALTEON, 2025 PCI_PRODUCT_ALTEON_BCM5701, 2026 "Broadcom BCM5701 Gigabit Ethernet", 2027 }, 2028 2029 { PCI_VENDOR_ALTIMA, 2030 PCI_PRODUCT_ALTIMA_AC1000, 2031 "Altima AC1000 Gigabit Ethernet", 2032 }, 2033 { PCI_VENDOR_ALTIMA, 2034 PCI_PRODUCT_ALTIMA_AC1001, 2035 "Altima AC1001 Gigabit Ethernet", 2036 }, 2037 { PCI_VENDOR_ALTIMA, 2038 PCI_PRODUCT_ALTIMA_AC9100, 2039 "Altima AC9100 Gigabit Ethernet", 2040 }, 2041 2042 { PCI_VENDOR_BROADCOM, 2043 PCI_PRODUCT_BROADCOM_BCM5700, 2044 "Broadcom BCM5700 Gigabit Ethernet", 2045 }, 2046 { PCI_VENDOR_BROADCOM, 2047 PCI_PRODUCT_BROADCOM_BCM5701, 2048 "Broadcom BCM5701 Gigabit Ethernet", 2049 }, 2050 { PCI_VENDOR_BROADCOM, 2051 PCI_PRODUCT_BROADCOM_BCM5702, 2052 "Broadcom BCM5702 Gigabit Ethernet", 2053 }, 2054 { PCI_VENDOR_BROADCOM, 2055 PCI_PRODUCT_BROADCOM_BCM5702X, 2056 "Broadcom BCM5702X Gigabit Ethernet" }, 2057 2058 { PCI_VENDOR_BROADCOM, 2059 PCI_PRODUCT_BROADCOM_BCM5703, 2060 "Broadcom BCM5703 Gigabit Ethernet", 2061 }, 2062 { PCI_VENDOR_BROADCOM, 2063 PCI_PRODUCT_BROADCOM_BCM5703X, 2064 "Broadcom BCM5703X Gigabit Ethernet", 2065 }, 2066 { PCI_VENDOR_BROADCOM, 2067 PCI_PRODUCT_BROADCOM_BCM5703A3, 2068 "Broadcom BCM5703A3 Gigabit Ethernet", 2069 }, 2070 2071 { PCI_VENDOR_BROADCOM, 2072 PCI_PRODUCT_BROADCOM_BCM5704C, 2073 "Broadcom BCM5704C Dual Gigabit Ethernet", 2074 }, 2075 { PCI_VENDOR_BROADCOM, 2076 PCI_PRODUCT_BROADCOM_BCM5704S, 2077 "Broadcom BCM5704S Dual Gigabit Ethernet", 2078 }, 2079 2080 { PCI_VENDOR_BROADCOM, 2081 PCI_PRODUCT_BROADCOM_BCM5705, 2082 "Broadcom BCM5705 Gigabit Ethernet", 2083 }, 2084 { PCI_VENDOR_BROADCOM, 2085 PCI_PRODUCT_BROADCOM_BCM5705K, 2086 "Broadcom BCM5705K Gigabit Ethernet", 2087 }, 2088 { PCI_VENDOR_BROADCOM, 2089 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 2090 "Broadcom BCM5705 Gigabit Ethernet", 2091 }, 2092 { PCI_VENDOR_BROADCOM, 2093 PCI_PRODUCT_BROADCOM_BCM5705M, 2094 "Broadcom BCM5705M Gigabit Ethernet", 2095 }, 2096 2097 { PCI_VENDOR_BROADCOM, 2098 PCI_PRODUCT_BROADCOM_BCM5721, 2099 "Broadcom BCM5721 Gigabit Ethernet", 2100 }, 2101 2102 { PCI_VENDOR_BROADCOM, 2103 PCI_PRODUCT_BROADCOM_BCM5750, 2104 "Broadcom BCM5750 Gigabit Ethernet", 2105 }, 2106 2107 { PCI_VENDOR_BROADCOM, 2108 PCI_PRODUCT_BROADCOM_BCM5750M, 2109 "Broadcom BCM5750M Gigabit Ethernet", 2110 }, 2111 2112 { PCI_VENDOR_BROADCOM, 2113 PCI_PRODUCT_BROADCOM_BCM5751, 2114 "Broadcom BCM5751 Gigabit Ethernet", 2115 }, 2116 2117 { PCI_VENDOR_BROADCOM, 2118 PCI_PRODUCT_BROADCOM_BCM5751M, 2119 "Broadcom BCM5751M Gigabit Ethernet", 2120 }, 2121 2122 { PCI_VENDOR_BROADCOM, 2123 PCI_PRODUCT_BROADCOM_BCM5782, 2124 "Broadcom BCM5782 Gigabit Ethernet", 2125 }, 2126 { PCI_VENDOR_BROADCOM, 2127 PCI_PRODUCT_BROADCOM_BCM5788, 2128 "Broadcom BCM5788 Gigabit Ethernet", 2129 }, 2130 2131 { PCI_VENDOR_BROADCOM, 2132 PCI_PRODUCT_BROADCOM_BCM5901, 2133 "Broadcom BCM5901 Fast Ethernet", 2134 }, 2135 { PCI_VENDOR_BROADCOM, 2136 PCI_PRODUCT_BROADCOM_BCM5901A2, 2137 "Broadcom BCM5901A2 Fast Ethernet", 2138 }, 2139 2140 { PCI_VENDOR_SCHNEIDERKOCH, 2141 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2142 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2143 }, 2144 2145 { PCI_VENDOR_3COM, 2146 PCI_PRODUCT_3COM_3C996, 2147 "3Com 3c996 Gigabit Ethernet", 2148 }, 2149 2150 { 0, 2151 0, 2152 NULL }, 2153 }; 2154 2155 static const struct bge_product * 2156 bge_lookup(const struct pci_attach_args *pa) 2157 { 2158 const struct bge_product *bp; 2159 2160 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2161 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2162 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2163 return (bp); 2164 } 2165 2166 return (NULL); 2167 } 2168 2169 int 2170 bge_setpowerstate(sc, powerlevel) 2171 struct bge_softc *sc; 2172 int powerlevel; 2173 { 2174 #ifdef NOTYET 2175 u_int32_t pm_ctl = 0; 2176 2177 /* XXX FIXME: make sure indirect accesses enabled? */ 2178 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2179 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2180 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2181 2182 /* clear the PME_assert bit and power state bits, enable PME */ 2183 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2184 pm_ctl &= ~PCIM_PSTAT_DMASK; 2185 pm_ctl |= (1 << 8); 2186 2187 if (powerlevel == 0) { 2188 pm_ctl |= PCIM_PSTAT_D0; 2189 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2190 pm_ctl, 2); 2191 DELAY(10000); 2192 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2193 DELAY(10000); 2194 2195 #ifdef NOTYET 2196 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2197 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2198 #endif 2199 DELAY(40); DELAY(40); DELAY(40); 2200 DELAY(10000); /* above not quite adequate on 5700 */ 2201 return 0; 2202 } 2203 2204 2205 /* 2206 * Entering ACPI power states D1-D3 is achieved by wiggling 2207 * GMII gpio pins. Example code assumes all hardware vendors 2208 * followed Broadom's sample pcb layout. Until we verify that 2209 * for all supported OEM cards, states D1-D3 are unsupported. 2210 */ 2211 printf("%s: power state %d unimplemented; check GPIO pins\n", 2212 sc->bge_dev.dv_xname, powerlevel); 2213 #endif 2214 return EOPNOTSUPP; 2215 } 2216 2217 2218 /* 2219 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2220 * against our list and return its name if we find a match. Note 2221 * that since the Broadcom controller contains VPD support, we 2222 * can get the device name string from the controller itself instead 2223 * of the compiled-in string. This is a little slow, but it guarantees 2224 * we'll always announce the right product name. 2225 */ 2226 int 2227 bge_probe(parent, match, aux) 2228 struct device *parent; 2229 struct cfdata *match; 2230 void *aux; 2231 { 2232 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2233 2234 if (bge_lookup(pa) != NULL) 2235 return (1); 2236 2237 return (0); 2238 } 2239 2240 void 2241 bge_attach(parent, self, aux) 2242 struct device *parent, *self; 2243 void *aux; 2244 { 2245 struct bge_softc *sc = (struct bge_softc *)self; 2246 struct pci_attach_args *pa = aux; 2247 const struct bge_product *bp; 2248 const struct bge_revision *br; 2249 pci_chipset_tag_t pc = pa->pa_pc; 2250 pci_intr_handle_t ih; 2251 const char *intrstr = NULL; 2252 bus_dma_segment_t seg; 2253 int rseg; 2254 u_int32_t hwcfg = 0; 2255 u_int32_t mac_addr = 0; 2256 u_int32_t command; 2257 struct ifnet *ifp; 2258 caddr_t kva; 2259 u_char eaddr[ETHER_ADDR_LEN]; 2260 pcireg_t memtype; 2261 bus_addr_t memaddr; 2262 bus_size_t memsize; 2263 u_int32_t pm_ctl; 2264 2265 bp = bge_lookup(pa); 2266 KASSERT(bp != NULL); 2267 2268 sc->bge_pa = *pa; 2269 2270 aprint_naive(": Ethernet controller\n"); 2271 aprint_normal(": %s\n", bp->bp_name); 2272 2273 /* 2274 * Map control/status registers. 2275 */ 2276 DPRINTFN(5, ("Map control/status regs\n")); 2277 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2278 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2279 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2280 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2281 2282 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2283 aprint_error("%s: failed to enable memory mapping!\n", 2284 sc->bge_dev.dv_xname); 2285 return; 2286 } 2287 2288 DPRINTFN(5, ("pci_mem_find\n")); 2289 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2290 switch (memtype) { 2291 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2292 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2293 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2294 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2295 &memaddr, &memsize) == 0) 2296 break; 2297 default: 2298 aprint_error("%s: can't find mem space\n", 2299 sc->bge_dev.dv_xname); 2300 return; 2301 } 2302 2303 DPRINTFN(5, ("pci_intr_map\n")); 2304 if (pci_intr_map(pa, &ih)) { 2305 aprint_error("%s: couldn't map interrupt\n", 2306 sc->bge_dev.dv_xname); 2307 return; 2308 } 2309 2310 DPRINTFN(5, ("pci_intr_string\n")); 2311 intrstr = pci_intr_string(pc, ih); 2312 2313 DPRINTFN(5, ("pci_intr_establish\n")); 2314 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2315 2316 if (sc->bge_intrhand == NULL) { 2317 aprint_error("%s: couldn't establish interrupt", 2318 sc->bge_dev.dv_xname); 2319 if (intrstr != NULL) 2320 aprint_normal(" at %s", intrstr); 2321 aprint_normal("\n"); 2322 return; 2323 } 2324 aprint_normal("%s: interrupting at %s\n", 2325 sc->bge_dev.dv_xname, intrstr); 2326 2327 /* 2328 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2329 * can clobber the chip's PCI config-space power control registers, 2330 * leaving the card in D3 powersave state. 2331 * We do not have memory-mapped registers in this state, 2332 * so force device into D0 state before starting initialization. 2333 */ 2334 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2335 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2336 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2337 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2338 DELAY(1000); /* 27 usec is allegedly sufficent */ 2339 2340 /* 2341 * Save ASIC rev. Look up any quirks associated with this 2342 * ASIC. 2343 */ 2344 sc->bge_chipid = 2345 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2346 BGE_PCIMISCCTL_ASICREV; 2347 2348 /* 2349 * Detect PCI-Express devices 2350 * XXX: guessed from Linux/FreeBSD; no documentation 2351 */ 2352 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 && 2353 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 2354 NULL, NULL) != 0) 2355 sc->bge_pcie = 1; 2356 else 2357 sc->bge_pcie = 0; 2358 2359 /* Try to reset the chip. */ 2360 DPRINTFN(5, ("bge_reset\n")); 2361 bge_reset(sc); 2362 2363 if (bge_chipinit(sc)) { 2364 aprint_error("%s: chip initialization failed\n", 2365 sc->bge_dev.dv_xname); 2366 bge_release_resources(sc); 2367 return; 2368 } 2369 2370 /* 2371 * Get station address from the EEPROM. 2372 */ 2373 mac_addr = bge_readmem_ind(sc, 0x0c14); 2374 if ((mac_addr >> 16) == 0x484b) { 2375 eaddr[0] = (u_char)(mac_addr >> 8); 2376 eaddr[1] = (u_char)(mac_addr >> 0); 2377 mac_addr = bge_readmem_ind(sc, 0x0c18); 2378 eaddr[2] = (u_char)(mac_addr >> 24); 2379 eaddr[3] = (u_char)(mac_addr >> 16); 2380 eaddr[4] = (u_char)(mac_addr >> 8); 2381 eaddr[5] = (u_char)(mac_addr >> 0); 2382 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2383 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2384 aprint_error("%s: failed to read station address\n", 2385 sc->bge_dev.dv_xname); 2386 bge_release_resources(sc); 2387 return; 2388 } 2389 2390 br = bge_lookup_rev(sc->bge_chipid); 2391 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2392 2393 if (br == NULL) { 2394 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2395 sc->bge_quirks = 0; 2396 } else { 2397 aprint_normal("ASIC %s (0x%04x)", 2398 br->br_name, sc->bge_chipid >> 16); 2399 sc->bge_quirks |= br->br_quirks; 2400 } 2401 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2402 2403 /* Allocate the general information block and ring buffers. */ 2404 if (pci_dma64_available(pa)) 2405 sc->bge_dmatag = pa->pa_dmat64; 2406 else 2407 sc->bge_dmatag = pa->pa_dmat; 2408 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2409 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2410 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2411 aprint_error("%s: can't alloc rx buffers\n", 2412 sc->bge_dev.dv_xname); 2413 return; 2414 } 2415 DPRINTFN(5, ("bus_dmamem_map\n")); 2416 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2417 sizeof(struct bge_ring_data), &kva, 2418 BUS_DMA_NOWAIT)) { 2419 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2420 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2421 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2422 return; 2423 } 2424 DPRINTFN(5, ("bus_dmamem_create\n")); 2425 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2426 sizeof(struct bge_ring_data), 0, 2427 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2428 aprint_error("%s: can't create DMA map\n", 2429 sc->bge_dev.dv_xname); 2430 bus_dmamem_unmap(sc->bge_dmatag, kva, 2431 sizeof(struct bge_ring_data)); 2432 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2433 return; 2434 } 2435 DPRINTFN(5, ("bus_dmamem_load\n")); 2436 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2437 sizeof(struct bge_ring_data), NULL, 2438 BUS_DMA_NOWAIT)) { 2439 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2440 bus_dmamem_unmap(sc->bge_dmatag, kva, 2441 sizeof(struct bge_ring_data)); 2442 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2443 return; 2444 } 2445 2446 DPRINTFN(5, ("bzero\n")); 2447 sc->bge_rdata = (struct bge_ring_data *)kva; 2448 2449 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2450 2451 /* Try to allocate memory for jumbo buffers. */ 2452 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2453 if (bge_alloc_jumbo_mem(sc)) { 2454 aprint_error("%s: jumbo buffer allocation failed\n", 2455 sc->bge_dev.dv_xname); 2456 } else 2457 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2458 } 2459 2460 /* Set default tuneable values. */ 2461 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2462 sc->bge_rx_coal_ticks = 150; 2463 sc->bge_rx_max_coal_bds = 64; 2464 #ifdef ORIG_WPAUL_VALUES 2465 sc->bge_tx_coal_ticks = 150; 2466 sc->bge_tx_max_coal_bds = 128; 2467 #else 2468 sc->bge_tx_coal_ticks = 300; 2469 sc->bge_tx_max_coal_bds = 400; 2470 #endif 2471 2472 /* Set up ifnet structure */ 2473 ifp = &sc->ethercom.ec_if; 2474 ifp->if_softc = sc; 2475 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2476 ifp->if_ioctl = bge_ioctl; 2477 ifp->if_start = bge_start; 2478 ifp->if_init = bge_init; 2479 ifp->if_watchdog = bge_watchdog; 2480 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2481 IFQ_SET_READY(&ifp->if_snd); 2482 DPRINTFN(5, ("bcopy\n")); 2483 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2484 2485 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2486 sc->ethercom.ec_if.if_capabilities |= 2487 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2488 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2489 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2490 sc->ethercom.ec_capabilities |= 2491 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2492 2493 /* 2494 * Do MII setup. 2495 */ 2496 DPRINTFN(5, ("mii setup\n")); 2497 sc->bge_mii.mii_ifp = ifp; 2498 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2499 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2500 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2501 2502 /* 2503 * Figure out what sort of media we have by checking the 2504 * hardware config word in the first 32k of NIC internal memory, 2505 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2506 * cards, this value appears to be unset. If that's the 2507 * case, we have to rely on identifying the NIC by its PCI 2508 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2509 */ 2510 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2511 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2512 } else { 2513 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2514 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2515 hwcfg = be32toh(hwcfg); 2516 } 2517 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2518 sc->bge_tbi = 1; 2519 2520 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2521 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2522 SK_SUBSYSID_9D41) 2523 sc->bge_tbi = 1; 2524 2525 if (sc->bge_tbi) { 2526 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2527 bge_ifmedia_sts); 2528 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2529 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2530 0, NULL); 2531 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2532 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2533 } else { 2534 /* 2535 * Do transceiver setup. 2536 */ 2537 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2538 bge_ifmedia_sts); 2539 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2540 MII_PHY_ANY, MII_OFFSET_ANY, 2541 MIIF_FORCEANEG|MIIF_DOPAUSE); 2542 2543 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2544 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2545 ifmedia_add(&sc->bge_mii.mii_media, 2546 IFM_ETHER|IFM_MANUAL, 0, NULL); 2547 ifmedia_set(&sc->bge_mii.mii_media, 2548 IFM_ETHER|IFM_MANUAL); 2549 } else 2550 ifmedia_set(&sc->bge_mii.mii_media, 2551 IFM_ETHER|IFM_AUTO); 2552 } 2553 2554 /* 2555 * When using the BCM5701 in PCI-X mode, data corruption has 2556 * been observed in the first few bytes of some received packets. 2557 * Aligning the packet buffer in memory eliminates the corruption. 2558 * Unfortunately, this misaligns the packet payloads. On platforms 2559 * which do not support unaligned accesses, we will realign the 2560 * payloads by copying the received packets. 2561 */ 2562 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2563 /* If in PCI-X mode, work around the alignment bug. */ 2564 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2565 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2566 BGE_PCISTATE_PCI_BUSSPEED) 2567 sc->bge_rx_alignment_bug = 1; 2568 } 2569 2570 /* 2571 * Call MI attach routine. 2572 */ 2573 DPRINTFN(5, ("if_attach\n")); 2574 if_attach(ifp); 2575 DPRINTFN(5, ("ether_ifattach\n")); 2576 ether_ifattach(ifp, eaddr); 2577 #ifdef BGE_EVENT_COUNTERS 2578 /* 2579 * Attach event counters. 2580 */ 2581 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2582 NULL, sc->bge_dev.dv_xname, "intr"); 2583 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2584 NULL, sc->bge_dev.dv_xname, "tx_xoff"); 2585 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2586 NULL, sc->bge_dev.dv_xname, "tx_xon"); 2587 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2588 NULL, sc->bge_dev.dv_xname, "rx_xoff"); 2589 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2590 NULL, sc->bge_dev.dv_xname, "rx_xon"); 2591 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2592 NULL, sc->bge_dev.dv_xname, "rx_macctl"); 2593 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2594 NULL, sc->bge_dev.dv_xname, "xoffentered"); 2595 #endif /* BGE_EVENT_COUNTERS */ 2596 DPRINTFN(5, ("callout_init\n")); 2597 callout_init(&sc->bge_timeout); 2598 2599 sc->bge_powerhook = powerhook_establish(bge_powerhook, sc); 2600 if (sc->bge_powerhook == NULL) 2601 printf("%s: WARNING: unable to establish PCI power hook\n", 2602 sc->bge_dev.dv_xname); 2603 } 2604 2605 void 2606 bge_release_resources(sc) 2607 struct bge_softc *sc; 2608 { 2609 if (sc->bge_vpd_prodname != NULL) 2610 free(sc->bge_vpd_prodname, M_DEVBUF); 2611 2612 if (sc->bge_vpd_readonly != NULL) 2613 free(sc->bge_vpd_readonly, M_DEVBUF); 2614 } 2615 2616 void 2617 bge_reset(sc) 2618 struct bge_softc *sc; 2619 { 2620 struct pci_attach_args *pa = &sc->bge_pa; 2621 u_int32_t cachesize, command, pcistate, new_pcistate; 2622 int i, val; 2623 2624 /* Save some important PCI state. */ 2625 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2626 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2627 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2628 2629 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2630 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2631 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2632 2633 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2634 /* 2635 * XXX: from FreeBSD/Linux; no documentation 2636 */ 2637 if (sc->bge_pcie) { 2638 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2639 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2640 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2641 /* No idea what that actually means */ 2642 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2643 val |= (1<<29); 2644 } 2645 } 2646 2647 /* Issue global reset */ 2648 bge_writereg_ind(sc, BGE_MISC_CFG, val); 2649 2650 DELAY(1000); 2651 2652 /* 2653 * XXX: from FreeBSD/Linux; no documentation 2654 */ 2655 if (sc->bge_pcie) { 2656 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2657 pcireg_t reg; 2658 2659 DELAY(500000); 2660 /* XXX: Magic Numbers */ 2661 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0); 2662 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0, 2663 reg | (1 << 15)); 2664 } 2665 /* XXX: Magic Numbers */ 2666 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN1, 0xf5000); 2667 } 2668 2669 /* Reset some of the PCI state that got zapped by reset */ 2670 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2671 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2672 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2673 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2674 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2675 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2676 2677 /* Enable memory arbiter. */ 2678 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2679 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2680 } 2681 2682 /* 2683 * Prevent PXE restart: write a magic number to the 2684 * general communications memory at 0xB50. 2685 */ 2686 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2687 2688 /* 2689 * Poll the value location we just wrote until 2690 * we see the 1's complement of the magic number. 2691 * This indicates that the firmware initialization 2692 * is complete. 2693 */ 2694 for (i = 0; i < 750; i++) { 2695 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2696 if (val == ~BGE_MAGIC_NUMBER) 2697 break; 2698 DELAY(1000); 2699 } 2700 2701 if (i == 750) { 2702 printf("%s: firmware handshake timed out, val = %x\n", 2703 sc->bge_dev.dv_xname, val); 2704 return; 2705 } 2706 2707 /* 2708 * XXX Wait for the value of the PCISTATE register to 2709 * return to its original pre-reset state. This is a 2710 * fairly good indicator of reset completion. If we don't 2711 * wait for the reset to fully complete, trying to read 2712 * from the device's non-PCI registers may yield garbage 2713 * results. 2714 */ 2715 for (i = 0; i < BGE_TIMEOUT; i++) { 2716 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2717 BGE_PCI_PCISTATE); 2718 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2719 (pcistate & ~BGE_PCISTATE_RESERVED)) 2720 break; 2721 DELAY(10); 2722 } 2723 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2724 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2725 printf("%s: pcistate failed to revert\n", 2726 sc->bge_dev.dv_xname); 2727 } 2728 2729 /* XXX: from FreeBSD/Linux; no documentation */ 2730 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2731 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2732 2733 /* Enable memory arbiter. */ 2734 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2735 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2736 } 2737 2738 /* Fix up byte swapping */ 2739 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2740 2741 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2742 2743 DELAY(10000); 2744 } 2745 2746 /* 2747 * Frame reception handling. This is called if there's a frame 2748 * on the receive return list. 2749 * 2750 * Note: we have to be able to handle two possibilities here: 2751 * 1) the frame is from the jumbo recieve ring 2752 * 2) the frame is from the standard receive ring 2753 */ 2754 2755 void 2756 bge_rxeof(sc) 2757 struct bge_softc *sc; 2758 { 2759 struct ifnet *ifp; 2760 int stdcnt = 0, jumbocnt = 0; 2761 bus_dmamap_t dmamap; 2762 bus_addr_t offset, toff; 2763 bus_size_t tlen; 2764 int tosync; 2765 2766 ifp = &sc->ethercom.ec_if; 2767 2768 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2769 offsetof(struct bge_ring_data, bge_status_block), 2770 sizeof (struct bge_status_block), 2771 BUS_DMASYNC_POSTREAD); 2772 2773 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2774 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2775 sc->bge_rx_saved_considx; 2776 2777 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2778 2779 if (tosync < 0) { 2780 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2781 sizeof (struct bge_rx_bd); 2782 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2783 toff, tlen, BUS_DMASYNC_POSTREAD); 2784 tosync = -tosync; 2785 } 2786 2787 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2788 offset, tosync * sizeof (struct bge_rx_bd), 2789 BUS_DMASYNC_POSTREAD); 2790 2791 while(sc->bge_rx_saved_considx != 2792 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2793 struct bge_rx_bd *cur_rx; 2794 u_int32_t rxidx; 2795 struct mbuf *m = NULL; 2796 2797 cur_rx = &sc->bge_rdata-> 2798 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2799 2800 rxidx = cur_rx->bge_idx; 2801 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2802 2803 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2804 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2805 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2806 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2807 jumbocnt++; 2808 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2809 ifp->if_ierrors++; 2810 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2811 continue; 2812 } 2813 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2814 NULL)== ENOBUFS) { 2815 ifp->if_ierrors++; 2816 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2817 continue; 2818 } 2819 } else { 2820 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2821 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2822 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2823 stdcnt++; 2824 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2825 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2826 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2827 ifp->if_ierrors++; 2828 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2829 continue; 2830 } 2831 if (bge_newbuf_std(sc, sc->bge_std, 2832 NULL, dmamap) == ENOBUFS) { 2833 ifp->if_ierrors++; 2834 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2835 continue; 2836 } 2837 } 2838 2839 ifp->if_ipackets++; 2840 #ifndef __NO_STRICT_ALIGNMENT 2841 /* 2842 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2843 * the Rx buffer has the layer-2 header unaligned. 2844 * If our CPU requires alignment, re-align by copying. 2845 */ 2846 if (sc->bge_rx_alignment_bug) { 2847 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2848 cur_rx->bge_len); 2849 m->m_data += ETHER_ALIGN; 2850 } 2851 #endif 2852 2853 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2854 m->m_pkthdr.rcvif = ifp; 2855 2856 #if NBPFILTER > 0 2857 /* 2858 * Handle BPF listeners. Let the BPF user see the packet. 2859 */ 2860 if (ifp->if_bpf) 2861 bpf_mtap(ifp->if_bpf, m); 2862 #endif 2863 2864 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 2865 2866 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2867 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2868 /* 2869 * Rx transport checksum-offload may also 2870 * have bugs with packets which, when transmitted, 2871 * were `runts' requiring padding. 2872 */ 2873 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2874 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2875 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2876 m->m_pkthdr.csum_data = 2877 cur_rx->bge_tcp_udp_csum; 2878 m->m_pkthdr.csum_flags |= 2879 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2880 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2881 } 2882 2883 /* 2884 * If we received a packet with a vlan tag, pass it 2885 * to vlan_input() instead of ether_input(). 2886 */ 2887 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 2888 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 2889 2890 (*ifp->if_input)(ifp, m); 2891 } 2892 2893 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2894 if (stdcnt) 2895 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2896 if (jumbocnt) 2897 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2898 } 2899 2900 void 2901 bge_txeof(sc) 2902 struct bge_softc *sc; 2903 { 2904 struct bge_tx_bd *cur_tx = NULL; 2905 struct ifnet *ifp; 2906 struct txdmamap_pool_entry *dma; 2907 bus_addr_t offset, toff; 2908 bus_size_t tlen; 2909 int tosync; 2910 struct mbuf *m; 2911 2912 ifp = &sc->ethercom.ec_if; 2913 2914 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2915 offsetof(struct bge_ring_data, bge_status_block), 2916 sizeof (struct bge_status_block), 2917 BUS_DMASYNC_POSTREAD); 2918 2919 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2920 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2921 sc->bge_tx_saved_considx; 2922 2923 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2924 2925 if (tosync < 0) { 2926 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2927 sizeof (struct bge_tx_bd); 2928 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2929 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2930 tosync = -tosync; 2931 } 2932 2933 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2934 offset, tosync * sizeof (struct bge_tx_bd), 2935 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2936 2937 /* 2938 * Go through our tx ring and free mbufs for those 2939 * frames that have been sent. 2940 */ 2941 while (sc->bge_tx_saved_considx != 2942 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2943 u_int32_t idx = 0; 2944 2945 idx = sc->bge_tx_saved_considx; 2946 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2947 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2948 ifp->if_opackets++; 2949 m = sc->bge_cdata.bge_tx_chain[idx]; 2950 if (m != NULL) { 2951 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2952 dma = sc->txdma[idx]; 2953 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2954 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2955 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2956 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2957 sc->txdma[idx] = NULL; 2958 2959 m_freem(m); 2960 } 2961 sc->bge_txcnt--; 2962 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2963 ifp->if_timer = 0; 2964 } 2965 2966 if (cur_tx != NULL) 2967 ifp->if_flags &= ~IFF_OACTIVE; 2968 } 2969 2970 int 2971 bge_intr(xsc) 2972 void *xsc; 2973 { 2974 struct bge_softc *sc; 2975 struct ifnet *ifp; 2976 2977 sc = xsc; 2978 ifp = &sc->ethercom.ec_if; 2979 2980 #ifdef notdef 2981 /* Avoid this for now -- checking this register is expensive. */ 2982 /* Make sure this is really our interrupt. */ 2983 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2984 return (0); 2985 #endif 2986 /* Ack interrupt and stop others from occuring. */ 2987 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2988 2989 BGE_EVCNT_INCR(sc->bge_ev_intr); 2990 2991 /* 2992 * Process link state changes. 2993 * Grrr. The link status word in the status block does 2994 * not work correctly on the BCM5700 rev AX and BX chips, 2995 * according to all avaibable information. Hence, we have 2996 * to enable MII interrupts in order to properly obtain 2997 * async link changes. Unfortunately, this also means that 2998 * we have to read the MAC status register to detect link 2999 * changes, thereby adding an additional register access to 3000 * the interrupt handler. 3001 */ 3002 3003 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 3004 u_int32_t status; 3005 3006 status = CSR_READ_4(sc, BGE_MAC_STS); 3007 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3008 sc->bge_link = 0; 3009 callout_stop(&sc->bge_timeout); 3010 bge_tick(sc); 3011 /* Clear the interrupt */ 3012 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3013 BGE_EVTENB_MI_INTERRUPT); 3014 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 3015 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 3016 BRGPHY_INTRS); 3017 } 3018 } else { 3019 if (sc->bge_rdata->bge_status_block.bge_status & 3020 BGE_STATFLAG_LINKSTATE_CHANGED) { 3021 sc->bge_link = 0; 3022 callout_stop(&sc->bge_timeout); 3023 bge_tick(sc); 3024 /* Clear the interrupt */ 3025 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3026 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3027 BGE_MACSTAT_LINK_CHANGED); 3028 } 3029 } 3030 3031 if (ifp->if_flags & IFF_RUNNING) { 3032 /* Check RX return ring producer/consumer */ 3033 bge_rxeof(sc); 3034 3035 /* Check TX ring producer/consumer */ 3036 bge_txeof(sc); 3037 } 3038 3039 if (sc->bge_pending_rxintr_change) { 3040 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3041 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3042 uint32_t junk; 3043 3044 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3045 DELAY(10); 3046 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3047 3048 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3049 DELAY(10); 3050 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3051 3052 sc->bge_pending_rxintr_change = 0; 3053 } 3054 bge_handle_events(sc); 3055 3056 /* Re-enable interrupts. */ 3057 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3058 3059 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3060 bge_start(ifp); 3061 3062 return (1); 3063 } 3064 3065 void 3066 bge_tick(xsc) 3067 void *xsc; 3068 { 3069 struct bge_softc *sc = xsc; 3070 struct mii_data *mii = &sc->bge_mii; 3071 struct ifmedia *ifm = NULL; 3072 struct ifnet *ifp = &sc->ethercom.ec_if; 3073 int s; 3074 3075 s = splnet(); 3076 3077 bge_stats_update(sc); 3078 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3079 if (sc->bge_link) { 3080 splx(s); 3081 return; 3082 } 3083 3084 if (sc->bge_tbi) { 3085 ifm = &sc->bge_ifmedia; 3086 if (CSR_READ_4(sc, BGE_MAC_STS) & 3087 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3088 sc->bge_link++; 3089 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3090 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3091 bge_start(ifp); 3092 } 3093 splx(s); 3094 return; 3095 } 3096 3097 mii_tick(mii); 3098 3099 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 3100 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3101 sc->bge_link++; 3102 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3103 bge_start(ifp); 3104 } 3105 3106 splx(s); 3107 } 3108 3109 void 3110 bge_stats_update(sc) 3111 struct bge_softc *sc; 3112 { 3113 struct ifnet *ifp = &sc->ethercom.ec_if; 3114 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3115 bus_size_t rstats = BGE_RX_STATS; 3116 3117 #define READ_RSTAT(sc, stats, stat) \ 3118 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3119 3120 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3121 ifp->if_collisions += 3122 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3123 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3124 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3125 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3126 3127 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3128 READ_RSTAT(sc, rstats, outXoffSent)); 3129 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3130 READ_RSTAT(sc, rstats, outXonSent)); 3131 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3132 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3133 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3134 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3135 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3136 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3137 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3138 READ_RSTAT(sc, rstats, xoffStateEntered)); 3139 return; 3140 } 3141 3142 #undef READ_RSTAT 3143 #define READ_STAT(sc, stats, stat) \ 3144 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3145 3146 ifp->if_collisions += 3147 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3148 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3149 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3150 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3151 ifp->if_collisions; 3152 3153 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3154 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3155 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3156 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3157 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3158 READ_STAT(sc, stats, 3159 xoffPauseFramesReceived.bge_addr_lo)); 3160 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3161 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3162 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3163 READ_STAT(sc, stats, 3164 macControlFramesReceived.bge_addr_lo)); 3165 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3166 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3167 3168 #undef READ_STAT 3169 3170 #ifdef notdef 3171 ifp->if_collisions += 3172 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3173 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3174 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3175 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3176 ifp->if_collisions; 3177 #endif 3178 } 3179 3180 /* 3181 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3182 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3183 * but when such padded frames employ the bge IP/TCP checksum offload, 3184 * the hardware checksum assist gives incorrect results (possibly 3185 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3186 * If we pad such runts with zeros, the onboard checksum comes out correct. 3187 */ 3188 static __inline int 3189 bge_cksum_pad(struct mbuf *pkt) 3190 { 3191 struct mbuf *last = NULL; 3192 int padlen; 3193 3194 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3195 3196 /* if there's only the packet-header and we can pad there, use it. */ 3197 if (pkt->m_pkthdr.len == pkt->m_len && 3198 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 3199 last = pkt; 3200 } else { 3201 /* 3202 * Walk packet chain to find last mbuf. We will either 3203 * pad there, or append a new mbuf and pad it 3204 * (thus perhaps avoiding the bcm5700 dma-min bug). 3205 */ 3206 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3207 (void) 0; /* do nothing*/ 3208 } 3209 3210 /* `last' now points to last in chain. */ 3211 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 3212 (void) 0; /* we can pad here, in-place. */ 3213 } else { 3214 /* Allocate new empty mbuf, pad it. Compact later. */ 3215 struct mbuf *n; 3216 MGET(n, M_DONTWAIT, MT_DATA); 3217 n->m_len = 0; 3218 last->m_next = n; 3219 last = n; 3220 } 3221 } 3222 3223 #ifdef DEBUG 3224 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 3225 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 3226 #endif 3227 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3228 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3229 last->m_len += padlen; 3230 pkt->m_pkthdr.len += padlen; 3231 return 0; 3232 } 3233 3234 /* 3235 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3236 */ 3237 static __inline int 3238 bge_compact_dma_runt(struct mbuf *pkt) 3239 { 3240 struct mbuf *m, *prev; 3241 int totlen, prevlen; 3242 3243 prev = NULL; 3244 totlen = 0; 3245 prevlen = -1; 3246 3247 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3248 int mlen = m->m_len; 3249 int shortfall = 8 - mlen ; 3250 3251 totlen += mlen; 3252 if (mlen == 0) { 3253 continue; 3254 } 3255 if (mlen >= 8) 3256 continue; 3257 3258 /* If we get here, mbuf data is too small for DMA engine. 3259 * Try to fix by shuffling data to prev or next in chain. 3260 * If that fails, do a compacting deep-copy of the whole chain. 3261 */ 3262 3263 /* Internal frag. If fits in prev, copy it there. */ 3264 if (prev && !M_READONLY(prev) && 3265 M_TRAILINGSPACE(prev) >= m->m_len) { 3266 bcopy(m->m_data, 3267 prev->m_data+prev->m_len, 3268 mlen); 3269 prev->m_len += mlen; 3270 m->m_len = 0; 3271 /* XXX stitch chain */ 3272 prev->m_next = m_free(m); 3273 m = prev; 3274 continue; 3275 } 3276 else if (m->m_next != NULL && !M_READONLY(m) && 3277 M_TRAILINGSPACE(m) >= shortfall && 3278 m->m_next->m_len >= (8 + shortfall)) { 3279 /* m is writable and have enough data in next, pull up. */ 3280 3281 bcopy(m->m_next->m_data, 3282 m->m_data+m->m_len, 3283 shortfall); 3284 m->m_len += shortfall; 3285 m->m_next->m_len -= shortfall; 3286 m->m_next->m_data += shortfall; 3287 } 3288 else if (m->m_next == NULL || 1) { 3289 /* Got a runt at the very end of the packet. 3290 * borrow data from the tail of the preceding mbuf and 3291 * update its length in-place. (The original data is still 3292 * valid, so we can do this even if prev is not writable.) 3293 */ 3294 3295 /* if we'd make prev a runt, just move all of its data. */ 3296 #ifdef DEBUG 3297 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3298 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3299 #endif 3300 if ((prev->m_len - shortfall) < 8) 3301 shortfall = prev->m_len; 3302 3303 #ifdef notyet /* just do the safe slow thing for now */ 3304 if (!M_READONLY(m)) { 3305 if (M_LEADINGSPACE(m) < shorfall) { 3306 void *m_dat; 3307 m_dat = (m->m_flags & M_PKTHDR) ? 3308 m->m_pktdat : m->dat; 3309 memmove(m_dat, mtod(m, void*), m->m_len); 3310 m->m_data = m_dat; 3311 } 3312 } else 3313 #endif /* just do the safe slow thing */ 3314 { 3315 struct mbuf * n = NULL; 3316 int newprevlen = prev->m_len - shortfall; 3317 3318 MGET(n, M_NOWAIT, MT_DATA); 3319 if (n == NULL) 3320 return ENOBUFS; 3321 KASSERT(m->m_len + shortfall < MLEN 3322 /*, 3323 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3324 3325 /* first copy the data we're stealing from prev */ 3326 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3327 3328 /* update prev->m_len accordingly */ 3329 prev->m_len -= shortfall; 3330 3331 /* copy data from runt m */ 3332 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3333 3334 /* n holds what we stole from prev, plus m */ 3335 n->m_len = shortfall + m->m_len; 3336 3337 /* stitch n into chain and free m */ 3338 n->m_next = m->m_next; 3339 prev->m_next = n; 3340 /* KASSERT(m->m_next == NULL); */ 3341 m->m_next = NULL; 3342 m_free(m); 3343 m = n; /* for continuing loop */ 3344 } 3345 } 3346 prevlen = m->m_len; 3347 } 3348 return 0; 3349 } 3350 3351 /* 3352 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3353 * pointers to descriptors. 3354 */ 3355 int 3356 bge_encap(sc, m_head, txidx) 3357 struct bge_softc *sc; 3358 struct mbuf *m_head; 3359 u_int32_t *txidx; 3360 { 3361 struct bge_tx_bd *f = NULL; 3362 u_int32_t frag, cur, cnt = 0; 3363 u_int16_t csum_flags = 0; 3364 struct txdmamap_pool_entry *dma; 3365 bus_dmamap_t dmamap; 3366 int i = 0; 3367 struct m_tag *mtag; 3368 3369 cur = frag = *txidx; 3370 3371 if (m_head->m_pkthdr.csum_flags) { 3372 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3373 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3374 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3375 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3376 } 3377 3378 /* 3379 * If we were asked to do an outboard checksum, and the NIC 3380 * has the bug where it sometimes adds in the Ethernet padding, 3381 * explicitly pad with zeros so the cksum will be correct either way. 3382 * (For now, do this for all chip versions, until newer 3383 * are confirmed to not require the workaround.) 3384 */ 3385 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3386 #ifdef notyet 3387 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3388 #endif 3389 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3390 goto check_dma_bug; 3391 3392 if (bge_cksum_pad(m_head) != 0) 3393 return ENOBUFS; 3394 3395 check_dma_bug: 3396 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3397 goto doit; 3398 /* 3399 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3400 * less than eight bytes. If we encounter a teeny mbuf 3401 * at the end of a chain, we can pad. Otherwise, copy. 3402 */ 3403 if (bge_compact_dma_runt(m_head) != 0) 3404 return ENOBUFS; 3405 3406 doit: 3407 dma = SLIST_FIRST(&sc->txdma_list); 3408 if (dma == NULL) 3409 return ENOBUFS; 3410 dmamap = dma->dmamap; 3411 3412 /* 3413 * Start packing the mbufs in this chain into 3414 * the fragment pointers. Stop when we run out 3415 * of fragments or hit the end of the mbuf chain. 3416 */ 3417 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3418 BUS_DMA_NOWAIT)) 3419 return(ENOBUFS); 3420 3421 mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head); 3422 3423 for (i = 0; i < dmamap->dm_nsegs; i++) { 3424 f = &sc->bge_rdata->bge_tx_ring[frag]; 3425 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3426 break; 3427 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3428 f->bge_len = dmamap->dm_segs[i].ds_len; 3429 f->bge_flags = csum_flags; 3430 3431 if (mtag != NULL) { 3432 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3433 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3434 } else { 3435 f->bge_vlan_tag = 0; 3436 } 3437 /* 3438 * Sanity check: avoid coming within 16 descriptors 3439 * of the end of the ring. 3440 */ 3441 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3442 return(ENOBUFS); 3443 cur = frag; 3444 BGE_INC(frag, BGE_TX_RING_CNT); 3445 cnt++; 3446 } 3447 3448 if (i < dmamap->dm_nsegs) 3449 return ENOBUFS; 3450 3451 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3452 BUS_DMASYNC_PREWRITE); 3453 3454 if (frag == sc->bge_tx_saved_considx) 3455 return(ENOBUFS); 3456 3457 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3458 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3459 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3460 sc->txdma[cur] = dma; 3461 sc->bge_txcnt += cnt; 3462 3463 *txidx = frag; 3464 3465 return(0); 3466 } 3467 3468 /* 3469 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3470 * to the mbuf data regions directly in the transmit descriptors. 3471 */ 3472 void 3473 bge_start(ifp) 3474 struct ifnet *ifp; 3475 { 3476 struct bge_softc *sc; 3477 struct mbuf *m_head = NULL; 3478 u_int32_t prodidx; 3479 int pkts = 0; 3480 3481 sc = ifp->if_softc; 3482 3483 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3484 return; 3485 3486 prodidx = sc->bge_tx_prodidx; 3487 3488 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3489 IFQ_POLL(&ifp->if_snd, m_head); 3490 if (m_head == NULL) 3491 break; 3492 3493 #if 0 3494 /* 3495 * XXX 3496 * safety overkill. If this is a fragmented packet chain 3497 * with delayed TCP/UDP checksums, then only encapsulate 3498 * it if we have enough descriptors to handle the entire 3499 * chain at once. 3500 * (paranoia -- may not actually be needed) 3501 */ 3502 if (m_head->m_flags & M_FIRSTFRAG && 3503 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3504 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3505 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3506 ifp->if_flags |= IFF_OACTIVE; 3507 break; 3508 } 3509 } 3510 #endif 3511 3512 /* 3513 * Pack the data into the transmit ring. If we 3514 * don't have room, set the OACTIVE flag and wait 3515 * for the NIC to drain the ring. 3516 */ 3517 if (bge_encap(sc, m_head, &prodidx)) { 3518 ifp->if_flags |= IFF_OACTIVE; 3519 break; 3520 } 3521 3522 /* now we are committed to transmit the packet */ 3523 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3524 pkts++; 3525 3526 #if NBPFILTER > 0 3527 /* 3528 * If there's a BPF listener, bounce a copy of this frame 3529 * to him. 3530 */ 3531 if (ifp->if_bpf) 3532 bpf_mtap(ifp->if_bpf, m_head); 3533 #endif 3534 } 3535 if (pkts == 0) 3536 return; 3537 3538 /* Transmit */ 3539 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3540 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3541 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3542 3543 sc->bge_tx_prodidx = prodidx; 3544 3545 /* 3546 * Set a timeout in case the chip goes out to lunch. 3547 */ 3548 ifp->if_timer = 5; 3549 } 3550 3551 int 3552 bge_init(ifp) 3553 struct ifnet *ifp; 3554 { 3555 struct bge_softc *sc = ifp->if_softc; 3556 u_int16_t *m; 3557 int s, error; 3558 3559 s = splnet(); 3560 3561 ifp = &sc->ethercom.ec_if; 3562 3563 /* Cancel pending I/O and flush buffers. */ 3564 bge_stop(sc); 3565 bge_reset(sc); 3566 bge_chipinit(sc); 3567 3568 /* 3569 * Init the various state machines, ring 3570 * control blocks and firmware. 3571 */ 3572 error = bge_blockinit(sc); 3573 if (error != 0) { 3574 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3575 error); 3576 splx(s); 3577 return error; 3578 } 3579 3580 ifp = &sc->ethercom.ec_if; 3581 3582 /* Specify MTU. */ 3583 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3584 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3585 3586 /* Load our MAC address. */ 3587 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3588 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3589 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3590 3591 /* Enable or disable promiscuous mode as needed. */ 3592 if (ifp->if_flags & IFF_PROMISC) { 3593 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3594 } else { 3595 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3596 } 3597 3598 /* Program multicast filter. */ 3599 bge_setmulti(sc); 3600 3601 /* Init RX ring. */ 3602 bge_init_rx_ring_std(sc); 3603 3604 /* Init jumbo RX ring. */ 3605 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3606 bge_init_rx_ring_jumbo(sc); 3607 3608 /* Init our RX return ring index */ 3609 sc->bge_rx_saved_considx = 0; 3610 3611 /* Init TX ring. */ 3612 bge_init_tx_ring(sc); 3613 3614 /* Turn on transmitter */ 3615 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3616 3617 /* Turn on receiver */ 3618 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3619 3620 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3621 3622 /* Tell firmware we're alive. */ 3623 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3624 3625 /* Enable host interrupts. */ 3626 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3627 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3628 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3629 3630 bge_ifmedia_upd(ifp); 3631 3632 ifp->if_flags |= IFF_RUNNING; 3633 ifp->if_flags &= ~IFF_OACTIVE; 3634 3635 splx(s); 3636 3637 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3638 3639 return 0; 3640 } 3641 3642 /* 3643 * Set media options. 3644 */ 3645 int 3646 bge_ifmedia_upd(ifp) 3647 struct ifnet *ifp; 3648 { 3649 struct bge_softc *sc = ifp->if_softc; 3650 struct mii_data *mii = &sc->bge_mii; 3651 struct ifmedia *ifm = &sc->bge_ifmedia; 3652 3653 /* If this is a 1000baseX NIC, enable the TBI port. */ 3654 if (sc->bge_tbi) { 3655 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3656 return(EINVAL); 3657 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3658 case IFM_AUTO: 3659 break; 3660 case IFM_1000_SX: 3661 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3662 BGE_CLRBIT(sc, BGE_MAC_MODE, 3663 BGE_MACMODE_HALF_DUPLEX); 3664 } else { 3665 BGE_SETBIT(sc, BGE_MAC_MODE, 3666 BGE_MACMODE_HALF_DUPLEX); 3667 } 3668 break; 3669 default: 3670 return(EINVAL); 3671 } 3672 /* XXX 802.3x flow control for 1000BASE-SX */ 3673 return(0); 3674 } 3675 3676 sc->bge_link = 0; 3677 mii_mediachg(mii); 3678 3679 return(0); 3680 } 3681 3682 /* 3683 * Report current media status. 3684 */ 3685 void 3686 bge_ifmedia_sts(ifp, ifmr) 3687 struct ifnet *ifp; 3688 struct ifmediareq *ifmr; 3689 { 3690 struct bge_softc *sc = ifp->if_softc; 3691 struct mii_data *mii = &sc->bge_mii; 3692 3693 if (sc->bge_tbi) { 3694 ifmr->ifm_status = IFM_AVALID; 3695 ifmr->ifm_active = IFM_ETHER; 3696 if (CSR_READ_4(sc, BGE_MAC_STS) & 3697 BGE_MACSTAT_TBI_PCS_SYNCHED) 3698 ifmr->ifm_status |= IFM_ACTIVE; 3699 ifmr->ifm_active |= IFM_1000_SX; 3700 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3701 ifmr->ifm_active |= IFM_HDX; 3702 else 3703 ifmr->ifm_active |= IFM_FDX; 3704 return; 3705 } 3706 3707 mii_pollstat(mii); 3708 ifmr->ifm_status = mii->mii_media_status; 3709 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 3710 sc->bge_flowflags; 3711 } 3712 3713 int 3714 bge_ioctl(ifp, command, data) 3715 struct ifnet *ifp; 3716 u_long command; 3717 caddr_t data; 3718 { 3719 struct bge_softc *sc = ifp->if_softc; 3720 struct ifreq *ifr = (struct ifreq *) data; 3721 int s, error = 0; 3722 struct mii_data *mii; 3723 3724 s = splnet(); 3725 3726 switch(command) { 3727 case SIOCSIFFLAGS: 3728 if (ifp->if_flags & IFF_UP) { 3729 /* 3730 * If only the state of the PROMISC flag changed, 3731 * then just use the 'set promisc mode' command 3732 * instead of reinitializing the entire NIC. Doing 3733 * a full re-init means reloading the firmware and 3734 * waiting for it to start up, which may take a 3735 * second or two. 3736 */ 3737 if (ifp->if_flags & IFF_RUNNING && 3738 ifp->if_flags & IFF_PROMISC && 3739 !(sc->bge_if_flags & IFF_PROMISC)) { 3740 BGE_SETBIT(sc, BGE_RX_MODE, 3741 BGE_RXMODE_RX_PROMISC); 3742 } else if (ifp->if_flags & IFF_RUNNING && 3743 !(ifp->if_flags & IFF_PROMISC) && 3744 sc->bge_if_flags & IFF_PROMISC) { 3745 BGE_CLRBIT(sc, BGE_RX_MODE, 3746 BGE_RXMODE_RX_PROMISC); 3747 } else 3748 bge_init(ifp); 3749 } else { 3750 if (ifp->if_flags & IFF_RUNNING) { 3751 bge_stop(sc); 3752 } 3753 } 3754 sc->bge_if_flags = ifp->if_flags; 3755 error = 0; 3756 break; 3757 case SIOCSIFMEDIA: 3758 /* XXX Flow control is not supported for 1000BASE-SX */ 3759 if (sc->bge_tbi) { 3760 ifr->ifr_media &= ~IFM_ETH_FMASK; 3761 sc->bge_flowflags = 0; 3762 } 3763 3764 /* Flow control requires full-duplex mode. */ 3765 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 3766 (ifr->ifr_media & IFM_FDX) == 0) { 3767 ifr->ifr_media &= ~IFM_ETH_FMASK; 3768 } 3769 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 3770 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 3771 /* We an do both TXPAUSE and RXPAUSE. */ 3772 ifr->ifr_media |= 3773 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 3774 } 3775 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 3776 } 3777 /* FALLTHROUGH */ 3778 case SIOCGIFMEDIA: 3779 if (sc->bge_tbi) { 3780 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3781 command); 3782 } else { 3783 mii = &sc->bge_mii; 3784 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3785 command); 3786 } 3787 break; 3788 default: 3789 error = ether_ioctl(ifp, command, data); 3790 if (error == ENETRESET) { 3791 if (ifp->if_flags & IFF_RUNNING) 3792 bge_setmulti(sc); 3793 error = 0; 3794 } 3795 break; 3796 } 3797 3798 splx(s); 3799 3800 return(error); 3801 } 3802 3803 void 3804 bge_watchdog(ifp) 3805 struct ifnet *ifp; 3806 { 3807 struct bge_softc *sc; 3808 3809 sc = ifp->if_softc; 3810 3811 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3812 3813 ifp->if_flags &= ~IFF_RUNNING; 3814 bge_init(ifp); 3815 3816 ifp->if_oerrors++; 3817 } 3818 3819 static void 3820 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3821 { 3822 int i; 3823 3824 BGE_CLRBIT(sc, reg, bit); 3825 3826 for (i = 0; i < BGE_TIMEOUT; i++) { 3827 if ((CSR_READ_4(sc, reg) & bit) == 0) 3828 return; 3829 delay(100); 3830 } 3831 3832 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3833 sc->bge_dev.dv_xname, (u_long) reg, bit); 3834 } 3835 3836 /* 3837 * Stop the adapter and free any mbufs allocated to the 3838 * RX and TX lists. 3839 */ 3840 void 3841 bge_stop(sc) 3842 struct bge_softc *sc; 3843 { 3844 struct ifnet *ifp = &sc->ethercom.ec_if; 3845 3846 callout_stop(&sc->bge_timeout); 3847 3848 /* 3849 * Disable all of the receiver blocks 3850 */ 3851 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3852 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3853 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3854 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3855 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3856 } 3857 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3858 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3859 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3860 3861 /* 3862 * Disable all of the transmit blocks 3863 */ 3864 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3865 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3866 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3867 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3868 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3869 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3870 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3871 } 3872 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3873 3874 /* 3875 * Shut down all of the memory managers and related 3876 * state machines. 3877 */ 3878 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3879 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3880 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3881 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3882 } 3883 3884 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3885 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3886 3887 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3888 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3889 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3890 } 3891 3892 /* Disable host interrupts. */ 3893 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3894 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3895 3896 /* 3897 * Tell firmware we're shutting down. 3898 */ 3899 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3900 3901 /* Free the RX lists. */ 3902 bge_free_rx_ring_std(sc); 3903 3904 /* Free jumbo RX list. */ 3905 bge_free_rx_ring_jumbo(sc); 3906 3907 /* Free TX buffers. */ 3908 bge_free_tx_ring(sc); 3909 3910 /* 3911 * Isolate/power down the PHY. 3912 */ 3913 if (!sc->bge_tbi) 3914 mii_down(&sc->bge_mii); 3915 3916 sc->bge_link = 0; 3917 3918 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3919 3920 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3921 } 3922 3923 /* 3924 * Stop all chip I/O so that the kernel's probe routines don't 3925 * get confused by errant DMAs when rebooting. 3926 */ 3927 void 3928 bge_shutdown(xsc) 3929 void *xsc; 3930 { 3931 struct bge_softc *sc = (struct bge_softc *)xsc; 3932 3933 bge_stop(sc); 3934 bge_reset(sc); 3935 } 3936 3937 3938 static int 3939 sysctl_bge_verify(SYSCTLFN_ARGS) 3940 { 3941 int error, t; 3942 struct sysctlnode node; 3943 3944 node = *rnode; 3945 t = *(int*)rnode->sysctl_data; 3946 node.sysctl_data = &t; 3947 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3948 if (error || newp == NULL) 3949 return (error); 3950 3951 #if 0 3952 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 3953 node.sysctl_num, rnode->sysctl_num)); 3954 #endif 3955 3956 if (node.sysctl_num == bge_rxthresh_nodenum) { 3957 if (t < 0 || t >= NBGE_RX_THRESH) 3958 return (EINVAL); 3959 bge_update_all_threshes(t); 3960 } else 3961 return (EINVAL); 3962 3963 *(int*)rnode->sysctl_data = t; 3964 3965 return (0); 3966 } 3967 3968 /* 3969 * Set up sysctl(3) MIB, hw.bge.*. 3970 * 3971 * TBD condition SYSCTL_PERMANENT on being an LKM or not 3972 */ 3973 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 3974 { 3975 int rc, bge_root_num; 3976 const struct sysctlnode *node; 3977 3978 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3979 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 3980 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3981 goto err; 3982 } 3983 3984 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3985 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 3986 SYSCTL_DESCR("BGE interface controls"), 3987 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3988 goto err; 3989 } 3990 3991 bge_root_num = node->sysctl_num; 3992 3993 /* BGE Rx interrupt mitigation level */ 3994 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3995 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 3996 CTLTYPE_INT, "rx_lvl", 3997 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 3998 sysctl_bge_verify, 0, 3999 &bge_rx_thresh_lvl, 4000 0, CTL_HW, bge_root_num, CTL_CREATE, 4001 CTL_EOL)) != 0) { 4002 goto err; 4003 } 4004 4005 bge_rxthresh_nodenum = node->sysctl_num; 4006 4007 return; 4008 4009 err: 4010 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4011 } 4012 4013 void 4014 bge_powerhook(int why, void *hdl) 4015 { 4016 struct bge_softc *sc = (struct bge_softc *)hdl; 4017 struct ifnet *ifp = &sc->ethercom.ec_if; 4018 struct pci_attach_args *pa = &(sc->bge_pa); 4019 pci_chipset_tag_t pc = pa->pa_pc; 4020 pcitag_t tag = pa->pa_tag; 4021 4022 switch (why) { 4023 case PWR_SOFTSUSPEND: 4024 case PWR_SOFTSTANDBY: 4025 bge_shutdown(sc); 4026 break; 4027 case PWR_SOFTRESUME: 4028 if (ifp->if_flags & IFF_UP) { 4029 ifp->if_flags &= ~IFF_RUNNING; 4030 bge_init(ifp); 4031 } 4032 break; 4033 case PWR_SUSPEND: 4034 case PWR_STANDBY: 4035 pci_conf_capture(pc, tag, &sc->bge_pciconf); 4036 break; 4037 case PWR_RESUME: 4038 pci_conf_restore(pc, tag, &sc->bge_pciconf); 4039 break; 4040 } 4041 4042 return; 4043 } 4044
Indexes created Wed Sep 24 05:09:52 GMT 2025