if_bge.c revision 1.95
1 /* $NetBSD: if_bge.c,v 1.95 2005/11/24 03:27:59 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl (at) wasabisystems.com> 44 * Jason Thorpe <thorpej (at) wasabisystems.com> 45 * Jonathan Stone <jonathan (at) dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul (at) windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.95 2005/11/24 03:27:59 jonathan Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 /* Headers for TCP Segmentation Offload (TSO) */ 111 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 112 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 113 #include <netinet/ip.h> /* for struct ip */ 114 #include <netinet/tcp.h> /* for struct tcphdr */ 115 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/miivar.h> 127 #include <dev/mii/miidevs.h> 128 #include <dev/mii/brgphyreg.h> 129 130 #include <dev/pci/if_bgereg.h> 131 132 #include <uvm/uvm_extern.h> 133 134 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 135 136 137 /* 138 * Tunable thresholds for rx-side bge interrupt mitigation. 139 */ 140 141 /* 142 * The pairs of values below were obtained from empirical measurement 143 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 144 * interrupt for every N packets received, where N is, approximately, 145 * the second value (rx_max_bds) in each pair. The values are chosen 146 * such that moving from one pair to the succeeding pair was observed 147 * to roughly halve interrupt rate under sustained input packet load. 148 * The values were empirically chosen to avoid overflowing internal 149 * limits on the bcm5700: inreasing rx_ticks much beyond 600 150 * results in internal wrapping and higher interrupt rates. 151 * The limit of 46 frames was chosen to match NFS workloads. 152 * 153 * These values also work well on bcm5701, bcm5704C, and (less 154 * tested) bcm5703. On other chipsets, (including the Altima chip 155 * family), the larger values may overflow internal chip limits, 156 * leading to increasing interrupt rates rather than lower interrupt 157 * rates. 158 * 159 * Applications using heavy interrupt mitigation (interrupting every 160 * 32 or 46 frames) in both directions may need to increase the TCP 161 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 162 * full link bandwidth, due to ACKs and window updates lingering 163 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 164 */ 165 struct bge_load_rx_thresh { 166 int rx_ticks; 167 int rx_max_bds; } 168 bge_rx_threshes[] = { 169 { 32, 2 }, 170 { 50, 4 }, 171 { 100, 8 }, 172 { 192, 16 }, 173 { 416, 32 }, 174 { 598, 46 } 175 }; 176 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 177 178 /* XXX patchable; should be sysctl'able */ 179 static int bge_auto_thresh = 1; 180 static int bge_rx_thresh_lvl; 181 182 #ifdef __NetBSD__ 183 static int bge_rxthresh_nodenum; 184 #endif /* __NetBSD__ */ 185 186 int bge_probe(struct device *, struct cfdata *, void *); 187 void bge_attach(struct device *, struct device *, void *); 188 void bge_powerhook(int, void *); 189 void bge_release_resources(struct bge_softc *); 190 void bge_txeof(struct bge_softc *); 191 void bge_rxeof(struct bge_softc *); 192 193 void bge_tick(void *); 194 void bge_stats_update(struct bge_softc *); 195 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 196 static __inline int bge_cksum_pad(struct mbuf *pkt); 197 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 198 199 int bge_intr(void *); 200 void bge_start(struct ifnet *); 201 int bge_ioctl(struct ifnet *, u_long, caddr_t); 202 int bge_init(struct ifnet *); 203 void bge_stop(struct bge_softc *); 204 void bge_watchdog(struct ifnet *); 205 void bge_shutdown(void *); 206 int bge_ifmedia_upd(struct ifnet *); 207 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 208 209 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 210 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 211 212 void bge_setmulti(struct bge_softc *); 213 214 void bge_handle_events(struct bge_softc *); 215 int bge_alloc_jumbo_mem(struct bge_softc *); 216 void bge_free_jumbo_mem(struct bge_softc *); 217 void *bge_jalloc(struct bge_softc *); 218 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 219 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 220 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 221 int bge_init_rx_ring_std(struct bge_softc *); 222 void bge_free_rx_ring_std(struct bge_softc *); 223 int bge_init_rx_ring_jumbo(struct bge_softc *); 224 void bge_free_rx_ring_jumbo(struct bge_softc *); 225 void bge_free_tx_ring(struct bge_softc *); 226 int bge_init_tx_ring(struct bge_softc *); 227 228 int bge_chipinit(struct bge_softc *); 229 int bge_blockinit(struct bge_softc *); 230 int bge_setpowerstate(struct bge_softc *, int); 231 232 #ifdef notdef 233 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 234 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 235 void bge_vpd_read(struct bge_softc *); 236 #endif 237 238 u_int32_t bge_readmem_ind(struct bge_softc *, int); 239 void bge_writemem_ind(struct bge_softc *, int, int); 240 #ifdef notdef 241 u_int32_t bge_readreg_ind(struct bge_softc *, int); 242 #endif 243 void bge_writereg_ind(struct bge_softc *, int, int); 244 245 int bge_miibus_readreg(struct device *, int, int); 246 void bge_miibus_writereg(struct device *, int, int, int); 247 void bge_miibus_statchg(struct device *); 248 249 void bge_reset(struct bge_softc *); 250 251 void bge_set_thresh(struct ifnet * /*ifp*/, int /*lvl*/); 252 void bge_update_all_threshes(int /*lvl*/); 253 254 void bge_dump_status(struct bge_softc *); 255 void bge_dump_rxbd(struct bge_rx_bd *); 256 257 258 #define BGE_DEBUG 259 #ifdef BGE_DEBUG 260 #define DPRINTF(x) if (bgedebug) printf x 261 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 262 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 263 int bgedebug = 0; 264 int bge_tso_debug = 0; 265 #else 266 #define DPRINTF(x) 267 #define DPRINTFN(n,x) 268 #define BGE_TSO_PRINTF(x) 269 #endif 270 271 #ifdef BGE_EVENT_COUNTERS 272 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 273 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 274 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 275 #else 276 #define BGE_EVCNT_INCR(ev) /* nothing */ 277 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 278 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 279 #endif 280 281 /* Various chip quirks. */ 282 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 283 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 284 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 285 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 286 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 287 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 288 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 289 #define BGE_QUIRK_5705_CORE 0x00000080 290 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 291 292 /* 293 * XXX: how to handle variants based on 5750 and derivatives: 294 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 295 * in general behave like a 5705, except with additional quirks. 296 * This driver's current handling of the 5721 is wrong; 297 * how we map ASIC revision to "quirks" needs more thought. 298 * (defined here until the thought is done). 299 */ 300 #define BGE_IS_5750_OR_BEYOND(sc) \ 301 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 302 303 #define BGE_IS_5705_OR_BEYOND(sc) \ 304 ( ((sc)->bge_quirks & BGE_QUIRK_5705_CORE) || \ 305 BGE_IS_5750_OR_BEYOND(sc) ) 306 307 308 /* following bugs are common to bcm5700 rev B, all flavours */ 309 #define BGE_QUIRK_5700_COMMON \ 310 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 311 312 CFATTACH_DECL(bge, sizeof(struct bge_softc), 313 bge_probe, bge_attach, NULL, NULL); 314 315 u_int32_t 316 bge_readmem_ind(sc, off) 317 struct bge_softc *sc; 318 int off; 319 { 320 struct pci_attach_args *pa = &(sc->bge_pa); 321 pcireg_t val; 322 323 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 324 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 325 return val; 326 } 327 328 void 329 bge_writemem_ind(sc, off, val) 330 struct bge_softc *sc; 331 int off, val; 332 { 333 struct pci_attach_args *pa = &(sc->bge_pa); 334 335 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 336 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 337 } 338 339 #ifdef notdef 340 u_int32_t 341 bge_readreg_ind(sc, off) 342 struct bge_softc *sc; 343 int off; 344 { 345 struct pci_attach_args *pa = &(sc->bge_pa); 346 347 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 348 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 349 } 350 #endif 351 352 void 353 bge_writereg_ind(sc, off, val) 354 struct bge_softc *sc; 355 int off, val; 356 { 357 struct pci_attach_args *pa = &(sc->bge_pa); 358 359 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 360 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 361 } 362 363 #ifdef notdef 364 u_int8_t 365 bge_vpd_readbyte(sc, addr) 366 struct bge_softc *sc; 367 int addr; 368 { 369 int i; 370 u_int32_t val; 371 struct pci_attach_args *pa = &(sc->bge_pa); 372 373 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 374 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 375 DELAY(10); 376 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 377 BGE_VPD_FLAG) 378 break; 379 } 380 381 if (i == BGE_TIMEOUT) { 382 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 383 return(0); 384 } 385 386 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 387 388 return((val >> ((addr % 4) * 8)) & 0xFF); 389 } 390 391 void 392 bge_vpd_read_res(sc, res, addr) 393 struct bge_softc *sc; 394 struct vpd_res *res; 395 int addr; 396 { 397 int i; 398 u_int8_t *ptr; 399 400 ptr = (u_int8_t *)res; 401 for (i = 0; i < sizeof(struct vpd_res); i++) 402 ptr[i] = bge_vpd_readbyte(sc, i + addr); 403 } 404 405 void 406 bge_vpd_read(sc) 407 struct bge_softc *sc; 408 { 409 int pos = 0, i; 410 struct vpd_res res; 411 412 if (sc->bge_vpd_prodname != NULL) 413 free(sc->bge_vpd_prodname, M_DEVBUF); 414 if (sc->bge_vpd_readonly != NULL) 415 free(sc->bge_vpd_readonly, M_DEVBUF); 416 sc->bge_vpd_prodname = NULL; 417 sc->bge_vpd_readonly = NULL; 418 419 bge_vpd_read_res(sc, &res, pos); 420 421 if (res.vr_id != VPD_RES_ID) { 422 printf("%s: bad VPD resource id: expected %x got %x\n", 423 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 424 return; 425 } 426 427 pos += sizeof(res); 428 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 429 if (sc->bge_vpd_prodname == NULL) 430 panic("bge_vpd_read"); 431 for (i = 0; i < res.vr_len; i++) 432 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 433 sc->bge_vpd_prodname[i] = '\0'; 434 pos += i; 435 436 bge_vpd_read_res(sc, &res, pos); 437 438 if (res.vr_id != VPD_RES_READ) { 439 printf("%s: bad VPD resource id: expected %x got %x\n", 440 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 441 return; 442 } 443 444 pos += sizeof(res); 445 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 446 if (sc->bge_vpd_readonly == NULL) 447 panic("bge_vpd_read"); 448 for (i = 0; i < res.vr_len + 1; i++) 449 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 450 } 451 #endif 452 453 /* 454 * Read a byte of data stored in the EEPROM at address 'addr.' The 455 * BCM570x supports both the traditional bitbang interface and an 456 * auto access interface for reading the EEPROM. We use the auto 457 * access method. 458 */ 459 u_int8_t 460 bge_eeprom_getbyte(sc, addr, dest) 461 struct bge_softc *sc; 462 int addr; 463 u_int8_t *dest; 464 { 465 int i; 466 u_int32_t byte = 0; 467 468 /* 469 * Enable use of auto EEPROM access so we can avoid 470 * having to use the bitbang method. 471 */ 472 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 473 474 /* Reset the EEPROM, load the clock period. */ 475 CSR_WRITE_4(sc, BGE_EE_ADDR, 476 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 477 DELAY(20); 478 479 /* Issue the read EEPROM command. */ 480 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 481 482 /* Wait for completion */ 483 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 484 DELAY(10); 485 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 486 break; 487 } 488 489 if (i == BGE_TIMEOUT) { 490 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 491 return(0); 492 } 493 494 /* Get result. */ 495 byte = CSR_READ_4(sc, BGE_EE_DATA); 496 497 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 498 499 return(0); 500 } 501 502 /* 503 * Read a sequence of bytes from the EEPROM. 504 */ 505 int 506 bge_read_eeprom(sc, dest, off, cnt) 507 struct bge_softc *sc; 508 caddr_t dest; 509 int off; 510 int cnt; 511 { 512 int err = 0, i; 513 u_int8_t byte = 0; 514 515 for (i = 0; i < cnt; i++) { 516 err = bge_eeprom_getbyte(sc, off + i, &byte); 517 if (err) 518 break; 519 *(dest + i) = byte; 520 } 521 522 return(err ? 1 : 0); 523 } 524 525 int 526 bge_miibus_readreg(dev, phy, reg) 527 struct device *dev; 528 int phy, reg; 529 { 530 struct bge_softc *sc = (struct bge_softc *)dev; 531 u_int32_t val; 532 u_int32_t saved_autopoll; 533 int i; 534 535 /* 536 * Several chips with builtin PHYs will incorrectly answer to 537 * other PHY instances than the builtin PHY at id 1. 538 */ 539 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 540 return(0); 541 542 /* Reading with autopolling on may trigger PCI errors */ 543 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 544 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 545 CSR_WRITE_4(sc, BGE_MI_MODE, 546 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 547 DELAY(40); 548 } 549 550 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 551 BGE_MIPHY(phy)|BGE_MIREG(reg)); 552 553 for (i = 0; i < BGE_TIMEOUT; i++) { 554 val = CSR_READ_4(sc, BGE_MI_COMM); 555 if (!(val & BGE_MICOMM_BUSY)) 556 break; 557 delay(10); 558 } 559 560 if (i == BGE_TIMEOUT) { 561 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 562 val = 0; 563 goto done; 564 } 565 566 val = CSR_READ_4(sc, BGE_MI_COMM); 567 568 done: 569 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 570 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 571 DELAY(40); 572 } 573 574 if (val & BGE_MICOMM_READFAIL) 575 return(0); 576 577 return(val & 0xFFFF); 578 } 579 580 void 581 bge_miibus_writereg(dev, phy, reg, val) 582 struct device *dev; 583 int phy, reg, val; 584 { 585 struct bge_softc *sc = (struct bge_softc *)dev; 586 u_int32_t saved_autopoll; 587 int i; 588 589 /* Touching the PHY while autopolling is on may trigger PCI errors */ 590 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 591 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 592 delay(40); 593 CSR_WRITE_4(sc, BGE_MI_MODE, 594 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 595 delay(10); /* 40 usec is supposed to be adequate */ 596 } 597 598 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 599 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 600 601 for (i = 0; i < BGE_TIMEOUT; i++) { 602 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 603 break; 604 delay(10); 605 } 606 607 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 608 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 609 delay(40); 610 } 611 612 if (i == BGE_TIMEOUT) { 613 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 614 } 615 } 616 617 void 618 bge_miibus_statchg(dev) 619 struct device *dev; 620 { 621 struct bge_softc *sc = (struct bge_softc *)dev; 622 struct mii_data *mii = &sc->bge_mii; 623 624 /* 625 * Get flow control negotiation result. 626 */ 627 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 628 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 629 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 630 mii->mii_media_active &= ~IFM_ETH_FMASK; 631 } 632 633 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 634 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 635 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 636 } else { 637 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 638 } 639 640 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 641 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 642 } else { 643 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 644 } 645 646 /* 647 * 802.3x flow control 648 */ 649 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 650 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 651 } else { 652 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 653 } 654 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 655 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 656 } else { 657 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 658 } 659 } 660 661 /* 662 * Update rx threshold levels to values in a particular slot 663 * of the interrupt-mitigation table bge_rx_threshes. 664 */ 665 void 666 bge_set_thresh(struct ifnet *ifp, int lvl) 667 { 668 struct bge_softc *sc = ifp->if_softc; 669 int s; 670 671 /* For now, just save the new Rx-intr thresholds and record 672 * that a threshold update is pending. Updating the hardware 673 * registers here (even at splhigh()) is observed to 674 * occasionaly cause glitches where Rx-interrupts are not 675 * honoured for up to 10 seconds. jonathan (at) NetBSD.org, 2003-04-05 676 */ 677 s = splnet(); 678 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 679 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 680 sc->bge_pending_rxintr_change = 1; 681 splx(s); 682 683 return; 684 } 685 686 687 /* 688 * Update Rx thresholds of all bge devices 689 */ 690 void 691 bge_update_all_threshes(int lvl) 692 { 693 struct ifnet *ifp; 694 const char * const namebuf = "bge"; 695 int namelen; 696 697 if (lvl < 0) 698 lvl = 0; 699 else if( lvl >= NBGE_RX_THRESH) 700 lvl = NBGE_RX_THRESH - 1; 701 702 namelen = strlen(namebuf); 703 /* 704 * Now search all the interfaces for this name/number 705 */ 706 IFNET_FOREACH(ifp) { 707 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 708 continue; 709 /* We got a match: update if doing auto-threshold-tuning */ 710 if (bge_auto_thresh) 711 bge_set_thresh(ifp, lvl); 712 } 713 } 714 715 /* 716 * Handle events that have triggered interrupts. 717 */ 718 void 719 bge_handle_events(sc) 720 struct bge_softc *sc; 721 { 722 723 return; 724 } 725 726 /* 727 * Memory management for jumbo frames. 728 */ 729 730 int 731 bge_alloc_jumbo_mem(sc) 732 struct bge_softc *sc; 733 { 734 caddr_t ptr, kva; 735 bus_dma_segment_t seg; 736 int i, rseg, state, error; 737 struct bge_jpool_entry *entry; 738 739 state = error = 0; 740 741 /* Grab a big chunk o' storage. */ 742 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 743 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 744 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 745 return ENOBUFS; 746 } 747 748 state = 1; 749 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 750 BUS_DMA_NOWAIT)) { 751 printf("%s: can't map DMA buffers (%d bytes)\n", 752 sc->bge_dev.dv_xname, (int)BGE_JMEM); 753 error = ENOBUFS; 754 goto out; 755 } 756 757 state = 2; 758 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 759 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 760 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 761 error = ENOBUFS; 762 goto out; 763 } 764 765 state = 3; 766 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 767 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 768 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 769 error = ENOBUFS; 770 goto out; 771 } 772 773 state = 4; 774 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 775 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 776 777 SLIST_INIT(&sc->bge_jfree_listhead); 778 SLIST_INIT(&sc->bge_jinuse_listhead); 779 780 /* 781 * Now divide it up into 9K pieces and save the addresses 782 * in an array. 783 */ 784 ptr = sc->bge_cdata.bge_jumbo_buf; 785 for (i = 0; i < BGE_JSLOTS; i++) { 786 sc->bge_cdata.bge_jslots[i] = ptr; 787 ptr += BGE_JLEN; 788 entry = malloc(sizeof(struct bge_jpool_entry), 789 M_DEVBUF, M_NOWAIT); 790 if (entry == NULL) { 791 printf("%s: no memory for jumbo buffer queue!\n", 792 sc->bge_dev.dv_xname); 793 error = ENOBUFS; 794 goto out; 795 } 796 entry->slot = i; 797 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 798 entry, jpool_entries); 799 } 800 out: 801 if (error != 0) { 802 switch (state) { 803 case 4: 804 bus_dmamap_unload(sc->bge_dmatag, 805 sc->bge_cdata.bge_rx_jumbo_map); 806 case 3: 807 bus_dmamap_destroy(sc->bge_dmatag, 808 sc->bge_cdata.bge_rx_jumbo_map); 809 case 2: 810 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 811 case 1: 812 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 813 break; 814 default: 815 break; 816 } 817 } 818 819 return error; 820 } 821 822 /* 823 * Allocate a jumbo buffer. 824 */ 825 void * 826 bge_jalloc(sc) 827 struct bge_softc *sc; 828 { 829 struct bge_jpool_entry *entry; 830 831 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 832 833 if (entry == NULL) { 834 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 835 return(NULL); 836 } 837 838 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 839 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 840 return(sc->bge_cdata.bge_jslots[entry->slot]); 841 } 842 843 /* 844 * Release a jumbo buffer. 845 */ 846 void 847 bge_jfree(m, buf, size, arg) 848 struct mbuf *m; 849 caddr_t buf; 850 size_t size; 851 void *arg; 852 { 853 struct bge_jpool_entry *entry; 854 struct bge_softc *sc; 855 int i, s; 856 857 /* Extract the softc struct pointer. */ 858 sc = (struct bge_softc *)arg; 859 860 if (sc == NULL) 861 panic("bge_jfree: can't find softc pointer!"); 862 863 /* calculate the slot this buffer belongs to */ 864 865 i = ((caddr_t)buf 866 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 867 868 if ((i < 0) || (i >= BGE_JSLOTS)) 869 panic("bge_jfree: asked to free buffer that we don't manage!"); 870 871 s = splvm(); 872 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 873 if (entry == NULL) 874 panic("bge_jfree: buffer not in use!"); 875 entry->slot = i; 876 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 877 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 878 879 if (__predict_true(m != NULL)) 880 pool_cache_put(&mbpool_cache, m); 881 splx(s); 882 } 883 884 885 /* 886 * Intialize a standard receive ring descriptor. 887 */ 888 int 889 bge_newbuf_std(sc, i, m, dmamap) 890 struct bge_softc *sc; 891 int i; 892 struct mbuf *m; 893 bus_dmamap_t dmamap; 894 { 895 struct mbuf *m_new = NULL; 896 struct bge_rx_bd *r; 897 int error; 898 899 if (dmamap == NULL) { 900 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 901 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 902 if (error != 0) 903 return error; 904 } 905 906 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 907 908 if (m == NULL) { 909 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 910 if (m_new == NULL) { 911 return(ENOBUFS); 912 } 913 914 MCLGET(m_new, M_DONTWAIT); 915 if (!(m_new->m_flags & M_EXT)) { 916 m_freem(m_new); 917 return(ENOBUFS); 918 } 919 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 920 if (!sc->bge_rx_alignment_bug) 921 m_adj(m_new, ETHER_ALIGN); 922 923 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 924 BUS_DMA_READ|BUS_DMA_NOWAIT)) 925 return(ENOBUFS); 926 } else { 927 m_new = m; 928 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 929 m_new->m_data = m_new->m_ext.ext_buf; 930 if (!sc->bge_rx_alignment_bug) 931 m_adj(m_new, ETHER_ALIGN); 932 } 933 934 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 935 r = &sc->bge_rdata->bge_rx_std_ring[i]; 936 bge_set_hostaddr(&r->bge_addr, 937 dmamap->dm_segs[0].ds_addr); 938 r->bge_flags = BGE_RXBDFLAG_END; 939 r->bge_len = m_new->m_len; 940 r->bge_idx = i; 941 942 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 943 offsetof(struct bge_ring_data, bge_rx_std_ring) + 944 i * sizeof (struct bge_rx_bd), 945 sizeof (struct bge_rx_bd), 946 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 947 948 return(0); 949 } 950 951 /* 952 * Initialize a jumbo receive ring descriptor. This allocates 953 * a jumbo buffer from the pool managed internally by the driver. 954 */ 955 int 956 bge_newbuf_jumbo(sc, i, m) 957 struct bge_softc *sc; 958 int i; 959 struct mbuf *m; 960 { 961 struct mbuf *m_new = NULL; 962 struct bge_rx_bd *r; 963 964 if (m == NULL) { 965 caddr_t buf = NULL; 966 967 /* Allocate the mbuf. */ 968 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 969 if (m_new == NULL) { 970 return(ENOBUFS); 971 } 972 973 /* Allocate the jumbo buffer */ 974 buf = bge_jalloc(sc); 975 if (buf == NULL) { 976 m_freem(m_new); 977 printf("%s: jumbo allocation failed " 978 "-- packet dropped!\n", sc->bge_dev.dv_xname); 979 return(ENOBUFS); 980 } 981 982 /* Attach the buffer to the mbuf. */ 983 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 984 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 985 bge_jfree, sc); 986 m_new->m_flags |= M_EXT_RW; 987 } else { 988 m_new = m; 989 m_new->m_data = m_new->m_ext.ext_buf; 990 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 991 } 992 993 if (!sc->bge_rx_alignment_bug) 994 m_adj(m_new, ETHER_ALIGN); 995 /* Set up the descriptor. */ 996 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 997 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 998 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 999 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1000 r->bge_len = m_new->m_len; 1001 r->bge_idx = i; 1002 1003 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1004 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1005 i * sizeof (struct bge_rx_bd), 1006 sizeof (struct bge_rx_bd), 1007 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1008 1009 return(0); 1010 } 1011 1012 /* 1013 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1014 * that's 1MB or memory, which is a lot. For now, we fill only the first 1015 * 256 ring entries and hope that our CPU is fast enough to keep up with 1016 * the NIC. 1017 */ 1018 int 1019 bge_init_rx_ring_std(sc) 1020 struct bge_softc *sc; 1021 { 1022 int i; 1023 1024 if (sc->bge_flags & BGE_RXRING_VALID) 1025 return 0; 1026 1027 for (i = 0; i < BGE_SSLOTS; i++) { 1028 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1029 return(ENOBUFS); 1030 } 1031 1032 sc->bge_std = i - 1; 1033 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1034 1035 sc->bge_flags |= BGE_RXRING_VALID; 1036 1037 return(0); 1038 } 1039 1040 void 1041 bge_free_rx_ring_std(sc) 1042 struct bge_softc *sc; 1043 { 1044 int i; 1045 1046 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1047 return; 1048 1049 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1050 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1051 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1052 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1053 bus_dmamap_destroy(sc->bge_dmatag, 1054 sc->bge_cdata.bge_rx_std_map[i]); 1055 } 1056 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1057 sizeof(struct bge_rx_bd)); 1058 } 1059 1060 sc->bge_flags &= ~BGE_RXRING_VALID; 1061 } 1062 1063 int 1064 bge_init_rx_ring_jumbo(sc) 1065 struct bge_softc *sc; 1066 { 1067 int i; 1068 volatile struct bge_rcb *rcb; 1069 1070 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1071 return 0; 1072 1073 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1074 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1075 return(ENOBUFS); 1076 }; 1077 1078 sc->bge_jumbo = i - 1; 1079 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1080 1081 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1082 rcb->bge_maxlen_flags = 0; 1083 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1084 1085 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1086 1087 return(0); 1088 } 1089 1090 void 1091 bge_free_rx_ring_jumbo(sc) 1092 struct bge_softc *sc; 1093 { 1094 int i; 1095 1096 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1097 return; 1098 1099 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1100 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1101 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1102 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1103 } 1104 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1105 sizeof(struct bge_rx_bd)); 1106 } 1107 1108 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1109 } 1110 1111 void 1112 bge_free_tx_ring(sc) 1113 struct bge_softc *sc; 1114 { 1115 int i, freed; 1116 struct txdmamap_pool_entry *dma; 1117 1118 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1119 return; 1120 1121 freed = 0; 1122 1123 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1124 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1125 freed++; 1126 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1127 sc->bge_cdata.bge_tx_chain[i] = NULL; 1128 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1129 link); 1130 sc->txdma[i] = 0; 1131 } 1132 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1133 sizeof(struct bge_tx_bd)); 1134 } 1135 1136 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1137 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1138 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1139 free(dma, M_DEVBUF); 1140 } 1141 1142 sc->bge_flags &= ~BGE_TXRING_VALID; 1143 } 1144 1145 int 1146 bge_init_tx_ring(sc) 1147 struct bge_softc *sc; 1148 { 1149 int i; 1150 bus_dmamap_t dmamap; 1151 struct txdmamap_pool_entry *dma; 1152 1153 if (sc->bge_flags & BGE_TXRING_VALID) 1154 return 0; 1155 1156 sc->bge_txcnt = 0; 1157 sc->bge_tx_saved_considx = 0; 1158 1159 /* Initialize transmit producer index for host-memory send ring. */ 1160 sc->bge_tx_prodidx = 0; 1161 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1162 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1163 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1164 1165 /* NIC-memory send ring not used; initialize to zero. */ 1166 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1167 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1168 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1169 1170 SLIST_INIT(&sc->txdma_list); 1171 for (i = 0; i < BGE_RSLOTS; i++) { 1172 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1173 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1174 &dmamap)) 1175 return(ENOBUFS); 1176 if (dmamap == NULL) 1177 panic("dmamap NULL in bge_init_tx_ring"); 1178 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1179 if (dma == NULL) { 1180 printf("%s: can't alloc txdmamap_pool_entry\n", 1181 sc->bge_dev.dv_xname); 1182 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1183 return (ENOMEM); 1184 } 1185 dma->dmamap = dmamap; 1186 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1187 } 1188 1189 sc->bge_flags |= BGE_TXRING_VALID; 1190 1191 return(0); 1192 } 1193 1194 void 1195 bge_setmulti(sc) 1196 struct bge_softc *sc; 1197 { 1198 struct ethercom *ac = &sc->ethercom; 1199 struct ifnet *ifp = &ac->ec_if; 1200 struct ether_multi *enm; 1201 struct ether_multistep step; 1202 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1203 u_int32_t h; 1204 int i; 1205 1206 if (ifp->if_flags & IFF_PROMISC) 1207 goto allmulti; 1208 1209 /* Now program new ones. */ 1210 ETHER_FIRST_MULTI(step, ac, enm); 1211 while (enm != NULL) { 1212 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1213 /* 1214 * We must listen to a range of multicast addresses. 1215 * For now, just accept all multicasts, rather than 1216 * trying to set only those filter bits needed to match 1217 * the range. (At this time, the only use of address 1218 * ranges is for IP multicast routing, for which the 1219 * range is big enough to require all bits set.) 1220 */ 1221 goto allmulti; 1222 } 1223 1224 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1225 1226 /* Just want the 7 least-significant bits. */ 1227 h &= 0x7f; 1228 1229 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1230 ETHER_NEXT_MULTI(step, enm); 1231 } 1232 1233 ifp->if_flags &= ~IFF_ALLMULTI; 1234 goto setit; 1235 1236 allmulti: 1237 ifp->if_flags |= IFF_ALLMULTI; 1238 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1239 1240 setit: 1241 for (i = 0; i < 4; i++) 1242 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1243 } 1244 1245 const int bge_swapbits[] = { 1246 0, 1247 BGE_MODECTL_BYTESWAP_DATA, 1248 BGE_MODECTL_WORDSWAP_DATA, 1249 BGE_MODECTL_BYTESWAP_NONFRAME, 1250 BGE_MODECTL_WORDSWAP_NONFRAME, 1251 1252 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1253 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1254 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1255 1256 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1257 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1258 1259 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1260 1261 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1262 BGE_MODECTL_BYTESWAP_NONFRAME, 1263 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1264 BGE_MODECTL_WORDSWAP_NONFRAME, 1265 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1266 BGE_MODECTL_WORDSWAP_NONFRAME, 1267 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1268 BGE_MODECTL_WORDSWAP_NONFRAME, 1269 1270 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1271 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1272 }; 1273 1274 int bge_swapindex = 0; 1275 1276 /* 1277 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1278 * self-test results. 1279 */ 1280 int 1281 bge_chipinit(sc) 1282 struct bge_softc *sc; 1283 { 1284 u_int32_t cachesize; 1285 int i; 1286 u_int32_t dma_rw_ctl; 1287 struct pci_attach_args *pa = &(sc->bge_pa); 1288 1289 1290 /* Set endianness before we access any non-PCI registers. */ 1291 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1292 BGE_INIT); 1293 1294 /* Set power state to D0. */ 1295 bge_setpowerstate(sc, 0); 1296 1297 /* 1298 * Check the 'ROM failed' bit on the RX CPU to see if 1299 * self-tests passed. 1300 */ 1301 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1302 printf("%s: RX CPU self-diagnostics failed!\n", 1303 sc->bge_dev.dv_xname); 1304 return(ENODEV); 1305 } 1306 1307 /* Clear the MAC control register */ 1308 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1309 1310 /* 1311 * Clear the MAC statistics block in the NIC's 1312 * internal memory. 1313 */ 1314 for (i = BGE_STATS_BLOCK; 1315 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1316 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1317 1318 for (i = BGE_STATUS_BLOCK; 1319 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1320 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1321 1322 /* Set up the PCI DMA control register. */ 1323 if (sc->bge_pcie) { 1324 u_int32_t device_ctl; 1325 1326 /* From FreeBSD */ 1327 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1328 sc->bge_dev.dv_xname)); 1329 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1330 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1331 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1332 1333 /* jonathan: alternative from Linux driver */ 1334 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1335 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1336 1337 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1338 device_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 1339 BGE_PCI_CONF_DEV_CTRL); 1340 printf("%s: pcie mode=0x%x\n", sc->bge_dev.dv_xname, device_ctl); 1341 1342 if ((device_ctl & 0x00e0) && 0) { 1343 /* 1344 * XXX jonathan (at) NetBSD.org: 1345 * This clause is exactly what the Broadcom-supplied 1346 * Linux does; but given overall register programming 1347 * by if_bge(4), this larger DMA-write watermark 1348 * value causes bcm5721 chips to totally wedge. 1349 */ 1350 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1351 } else { 1352 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1353 } 1354 } else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1355 BGE_PCISTATE_PCI_BUSMODE) { 1356 /* Conventional PCI bus */ 1357 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1358 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1359 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1360 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1361 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1362 dma_rw_ctl |= 0x0F; 1363 } 1364 } else { 1365 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1366 /* PCI-X bus */ 1367 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1368 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1369 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1370 (0x0F); 1371 /* 1372 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1373 * for hardware bugs, which means we should also clear 1374 * the low-order MINDMA bits. In addition, the 5704 1375 * uses a different encoding of read/write watermarks. 1376 */ 1377 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1378 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1379 /* should be 0x1f0000 */ 1380 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1381 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1382 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1383 } 1384 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1385 dma_rw_ctl &= 0xfffffff0; 1386 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1387 } 1388 } 1389 1390 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1391 1392 /* 1393 * Set up general mode register. 1394 */ 1395 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1396 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1397 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1398 1399 /* Get cache line size. */ 1400 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1401 1402 /* 1403 * Avoid violating PCI spec on certain chip revs. 1404 */ 1405 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1406 PCIM_CMD_MWIEN) { 1407 switch(cachesize) { 1408 case 1: 1409 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1410 BGE_PCI_WRITE_BNDRY_16BYTES); 1411 break; 1412 case 2: 1413 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1414 BGE_PCI_WRITE_BNDRY_32BYTES); 1415 break; 1416 case 4: 1417 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1418 BGE_PCI_WRITE_BNDRY_64BYTES); 1419 break; 1420 case 8: 1421 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1422 BGE_PCI_WRITE_BNDRY_128BYTES); 1423 break; 1424 case 16: 1425 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1426 BGE_PCI_WRITE_BNDRY_256BYTES); 1427 break; 1428 case 32: 1429 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1430 BGE_PCI_WRITE_BNDRY_512BYTES); 1431 break; 1432 case 64: 1433 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1434 BGE_PCI_WRITE_BNDRY_1024BYTES); 1435 break; 1436 default: 1437 /* Disable PCI memory write and invalidate. */ 1438 #if 0 1439 if (bootverbose) 1440 printf("%s: cache line size %d not " 1441 "supported; disabling PCI MWI\n", 1442 sc->bge_dev.dv_xname, cachesize); 1443 #endif 1444 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1445 PCIM_CMD_MWIEN); 1446 break; 1447 } 1448 } 1449 1450 /* 1451 * Disable memory write invalidate. Apparently it is not supported 1452 * properly by these devices. 1453 */ 1454 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1455 1456 1457 #ifdef __brokenalpha__ 1458 /* 1459 * Must insure that we do not cross an 8K (bytes) boundary 1460 * for DMA reads. Our highest limit is 1K bytes. This is a 1461 * restriction on some ALPHA platforms with early revision 1462 * 21174 PCI chipsets, such as the AlphaPC 164lx 1463 */ 1464 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1465 #endif 1466 1467 /* Set the timer prescaler (always 66MHz) */ 1468 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1469 1470 return(0); 1471 } 1472 1473 int 1474 bge_blockinit(sc) 1475 struct bge_softc *sc; 1476 { 1477 volatile struct bge_rcb *rcb; 1478 bus_size_t rcb_addr; 1479 int i; 1480 struct ifnet *ifp = &sc->ethercom.ec_if; 1481 bge_hostaddr taddr; 1482 1483 /* 1484 * Initialize the memory window pointer register so that 1485 * we can access the first 32K of internal NIC RAM. This will 1486 * allow us to set up the TX send ring RCBs and the RX return 1487 * ring RCBs, plus other things which live in NIC memory. 1488 */ 1489 1490 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1491 BGE_PCI_MEMWIN_BASEADDR, 0); 1492 1493 /* Configure mbuf memory pool */ 1494 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1495 if (sc->bge_extram) { 1496 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1497 BGE_EXT_SSRAM); 1498 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1499 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1500 else 1501 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1502 } else { 1503 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1504 BGE_BUFFPOOL_1); 1505 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1507 else 1508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1509 } 1510 1511 /* Configure DMA resource pool */ 1512 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1513 BGE_DMA_DESCRIPTORS); 1514 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1515 } 1516 1517 /* Configure mbuf pool watermarks */ 1518 #ifdef ORIG_WPAUL_VALUES 1519 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1521 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1522 #else 1523 /* new broadcom docs strongly recommend these: */ 1524 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1525 if (ifp->if_mtu > ETHER_MAX_LEN) { 1526 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1527 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1528 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1529 } else { 1530 /* Values from Linux driver... */ 1531 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1532 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1534 } 1535 } else { 1536 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1537 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1538 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1539 } 1540 #endif 1541 1542 /* Configure DMA resource watermarks */ 1543 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1544 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1545 1546 /* Enable buffer manager */ 1547 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1548 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1549 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1550 1551 /* Poll for buffer manager start indication */ 1552 for (i = 0; i < BGE_TIMEOUT; i++) { 1553 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1554 break; 1555 DELAY(10); 1556 } 1557 1558 if (i == BGE_TIMEOUT) { 1559 printf("%s: buffer manager failed to start\n", 1560 sc->bge_dev.dv_xname); 1561 return(ENXIO); 1562 } 1563 } 1564 1565 /* Enable flow-through queues */ 1566 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1567 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1568 1569 /* Wait until queue initialization is complete */ 1570 for (i = 0; i < BGE_TIMEOUT; i++) { 1571 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1572 break; 1573 DELAY(10); 1574 } 1575 1576 if (i == BGE_TIMEOUT) { 1577 printf("%s: flow-through queue init failed\n", 1578 sc->bge_dev.dv_xname); 1579 return(ENXIO); 1580 } 1581 1582 /* Initialize the standard RX ring control block */ 1583 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1584 bge_set_hostaddr(&rcb->bge_hostaddr, 1585 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1586 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1587 rcb->bge_maxlen_flags = 1588 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1589 } else { 1590 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1591 } 1592 if (sc->bge_extram) 1593 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1594 else 1595 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1596 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1597 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1598 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1599 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1600 1601 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1602 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1603 } else { 1604 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1605 } 1606 1607 /* 1608 * Initialize the jumbo RX ring control block 1609 * We set the 'ring disabled' bit in the flags 1610 * field until we're actually ready to start 1611 * using this ring (i.e. once we set the MTU 1612 * high enough to require it). 1613 */ 1614 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1615 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1616 bge_set_hostaddr(&rcb->bge_hostaddr, 1617 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1618 rcb->bge_maxlen_flags = 1619 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1620 BGE_RCB_FLAG_RING_DISABLED); 1621 if (sc->bge_extram) 1622 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1623 else 1624 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1625 1626 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1627 rcb->bge_hostaddr.bge_addr_hi); 1628 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1629 rcb->bge_hostaddr.bge_addr_lo); 1630 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1631 rcb->bge_maxlen_flags); 1632 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1633 1634 /* Set up dummy disabled mini ring RCB */ 1635 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1636 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1637 BGE_RCB_FLAG_RING_DISABLED); 1638 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1639 rcb->bge_maxlen_flags); 1640 1641 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1642 offsetof(struct bge_ring_data, bge_info), 1643 sizeof (struct bge_gib), 1644 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1645 } 1646 1647 /* 1648 * Set the BD ring replentish thresholds. The recommended 1649 * values are 1/8th the number of descriptors allocated to 1650 * each ring. 1651 */ 1652 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1653 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1654 1655 /* 1656 * Disable all unused send rings by setting the 'ring disabled' 1657 * bit in the flags field of all the TX send ring control blocks. 1658 * These are located in NIC memory. 1659 */ 1660 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1661 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1662 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1663 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1664 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1665 rcb_addr += sizeof(struct bge_rcb); 1666 } 1667 1668 /* Configure TX RCB 0 (we use only the first ring) */ 1669 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1670 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1671 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1672 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1673 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1674 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1675 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1676 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1677 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1678 } 1679 1680 /* Disable all unused RX return rings */ 1681 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1682 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1683 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1684 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1685 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1686 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1687 BGE_RCB_FLAG_RING_DISABLED)); 1688 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1689 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1690 (i * (sizeof(u_int64_t))), 0); 1691 rcb_addr += sizeof(struct bge_rcb); 1692 } 1693 1694 /* Initialize RX ring indexes */ 1695 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1696 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1697 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1698 1699 /* 1700 * Set up RX return ring 0 1701 * Note that the NIC address for RX return rings is 0x00000000. 1702 * The return rings live entirely within the host, so the 1703 * nicaddr field in the RCB isn't used. 1704 */ 1705 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1706 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1707 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1708 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1709 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1710 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1711 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1712 1713 /* Set random backoff seed for TX */ 1714 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1715 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1716 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1717 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1718 BGE_TX_BACKOFF_SEED_MASK); 1719 1720 /* Set inter-packet gap */ 1721 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1722 1723 /* 1724 * Specify which ring to use for packets that don't match 1725 * any RX rules. 1726 */ 1727 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1728 1729 /* 1730 * Configure number of RX lists. One interrupt distribution 1731 * list, sixteen active lists, one bad frames class. 1732 */ 1733 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1734 1735 /* Inialize RX list placement stats mask. */ 1736 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1737 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1738 1739 /* Disable host coalescing until we get it set up */ 1740 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1741 1742 /* Poll to make sure it's shut down. */ 1743 for (i = 0; i < BGE_TIMEOUT; i++) { 1744 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1745 break; 1746 DELAY(10); 1747 } 1748 1749 if (i == BGE_TIMEOUT) { 1750 printf("%s: host coalescing engine failed to idle\n", 1751 sc->bge_dev.dv_xname); 1752 return(ENXIO); 1753 } 1754 1755 /* Set up host coalescing defaults */ 1756 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1757 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1758 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1759 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1760 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1761 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1762 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1763 } 1764 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1765 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1766 1767 /* Set up address of statistics block */ 1768 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1769 bge_set_hostaddr(&taddr, 1770 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1771 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1772 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1773 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1774 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1775 } 1776 1777 /* Set up address of status block */ 1778 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1779 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1780 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1781 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1782 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1783 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1784 1785 /* Turn on host coalescing state machine */ 1786 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1787 1788 /* Turn on RX BD completion state machine and enable attentions */ 1789 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1790 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1791 1792 /* Turn on RX list placement state machine */ 1793 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1794 1795 /* Turn on RX list selector state machine. */ 1796 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1797 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1798 } 1799 1800 /* Turn on DMA, clear stats */ 1801 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1802 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1803 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1804 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1805 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1806 1807 /* Set misc. local control, enable interrupts on attentions */ 1808 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1809 1810 #ifdef notdef 1811 /* Assert GPIO pins for PHY reset */ 1812 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1813 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1814 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1815 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1816 #endif 1817 1818 #if defined(not_quite_yet) 1819 /* Linux driver enables enable gpio pin #1 on 5700s */ 1820 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1821 sc->bge_local_ctrl_reg |= 1822 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1823 } 1824 #endif 1825 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1826 1827 /* Turn on DMA completion state machine */ 1828 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1829 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1830 } 1831 1832 /* Turn on write DMA state machine */ 1833 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1834 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1835 1836 /* Turn on read DMA state machine */ 1837 { 1838 uint32_t dma_read_modebits; 1839 1840 dma_read_modebits = 1841 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1842 1843 if (sc->bge_pcie && 0) { 1844 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 1845 } else if ((sc->bge_quirks & BGE_QUIRK_5705_CORE)) { 1846 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 1847 } 1848 1849 /* XXX broadcom-supplied linux driver; undocumented */ 1850 if (BGE_IS_5750_OR_BEYOND(sc)) { 1851 /* 1852 * XXX: magic values. 1853 * From Broadcom-supplied Linux driver; apparently 1854 * required to workaround a DMA bug affecting TSO 1855 * on bcm575x/bcm5721? 1856 */ 1857 dma_read_modebits |= (1 << 27); 1858 } 1859 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 1860 } 1861 1862 /* Turn on RX data completion state machine */ 1863 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1864 1865 /* Turn on RX BD initiator state machine */ 1866 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1867 1868 /* Turn on RX data and RX BD initiator state machine */ 1869 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1870 1871 /* Turn on Mbuf cluster free state machine */ 1872 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1873 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1874 } 1875 1876 /* Turn on send BD completion state machine */ 1877 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1878 1879 /* Turn on send data completion state machine */ 1880 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1881 1882 /* Turn on send data initiator state machine */ 1883 if (BGE_IS_5750_OR_BEYOND(sc)) { 1884 /* XXX: magic value from Linux driver */ 1885 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1886 } else { 1887 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1888 } 1889 1890 /* Turn on send BD initiator state machine */ 1891 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1892 1893 /* Turn on send BD selector state machine */ 1894 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1895 1896 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1897 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1898 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1899 1900 /* ack/clear link change events */ 1901 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1902 BGE_MACSTAT_CFG_CHANGED); 1903 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1904 1905 /* Enable PHY auto polling (for MII/GMII only) */ 1906 if (sc->bge_tbi) { 1907 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1908 } else { 1909 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1910 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1911 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1912 BGE_EVTENB_MI_INTERRUPT); 1913 } 1914 1915 /* Enable link state change attentions. */ 1916 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1917 1918 return(0); 1919 } 1920 1921 static const struct bge_revision { 1922 uint32_t br_chipid; 1923 uint32_t br_quirks; 1924 const char *br_name; 1925 } bge_revisions[] = { 1926 { BGE_CHIPID_BCM5700_A0, 1927 BGE_QUIRK_LINK_STATE_BROKEN, 1928 "BCM5700 A0" }, 1929 1930 { BGE_CHIPID_BCM5700_A1, 1931 BGE_QUIRK_LINK_STATE_BROKEN, 1932 "BCM5700 A1" }, 1933 1934 { BGE_CHIPID_BCM5700_B0, 1935 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1936 "BCM5700 B0" }, 1937 1938 { BGE_CHIPID_BCM5700_B1, 1939 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1940 "BCM5700 B1" }, 1941 1942 { BGE_CHIPID_BCM5700_B2, 1943 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1944 "BCM5700 B2" }, 1945 1946 /* This is treated like a BCM5700 Bx */ 1947 { BGE_CHIPID_BCM5700_ALTIMA, 1948 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1949 "BCM5700 Altima" }, 1950 1951 { BGE_CHIPID_BCM5700_C0, 1952 0, 1953 "BCM5700 C0" }, 1954 1955 { BGE_CHIPID_BCM5701_A0, 1956 0, /*XXX really, just not known */ 1957 "BCM5701 A0" }, 1958 1959 { BGE_CHIPID_BCM5701_B0, 1960 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1961 "BCM5701 B0" }, 1962 1963 { BGE_CHIPID_BCM5701_B2, 1964 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1965 "BCM5701 B2" }, 1966 1967 { BGE_CHIPID_BCM5701_B5, 1968 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1969 "BCM5701 B5" }, 1970 1971 { BGE_CHIPID_BCM5703_A0, 1972 0, 1973 "BCM5703 A0" }, 1974 1975 { BGE_CHIPID_BCM5703_A1, 1976 0, 1977 "BCM5703 A1" }, 1978 1979 { BGE_CHIPID_BCM5703_A2, 1980 BGE_QUIRK_ONLY_PHY_1, 1981 "BCM5703 A2" }, 1982 1983 { BGE_CHIPID_BCM5703_A3, 1984 BGE_QUIRK_ONLY_PHY_1, 1985 "BCM5703 A3" }, 1986 1987 { BGE_CHIPID_BCM5704_A0, 1988 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1989 "BCM5704 A0" }, 1990 1991 { BGE_CHIPID_BCM5704_A1, 1992 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1993 "BCM5704 A1" }, 1994 1995 { BGE_CHIPID_BCM5704_A2, 1996 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1997 "BCM5704 A2" }, 1998 1999 { BGE_CHIPID_BCM5704_A3, 2000 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 2001 "BCM5704 A3" }, 2002 2003 { BGE_CHIPID_BCM5705_A0, 2004 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2005 "BCM5705 A0" }, 2006 2007 { BGE_CHIPID_BCM5705_A1, 2008 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2009 "BCM5705 A1" }, 2010 2011 { BGE_CHIPID_BCM5705_A2, 2012 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2013 "BCM5705 A2" }, 2014 2015 { BGE_CHIPID_BCM5705_A3, 2016 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2017 "BCM5705 A3" }, 2018 2019 { BGE_CHIPID_BCM5750_A0, 2020 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2021 "BCM5750 A1" }, 2022 2023 { BGE_CHIPID_BCM5750_A1, 2024 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2025 "BCM5750 A1" }, 2026 2027 { BGE_CHIPID_BCM5751_A1, 2028 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2029 "BCM5751 A1" }, 2030 2031 { 0, 0, NULL } 2032 }; 2033 2034 /* 2035 * Some defaults for major revisions, so that newer steppings 2036 * that we don't know about have a shot at working. 2037 */ 2038 static const struct bge_revision bge_majorrevs[] = { 2039 { BGE_ASICREV_BCM5700, 2040 BGE_QUIRK_LINK_STATE_BROKEN, 2041 "unknown BCM5700" }, 2042 2043 { BGE_ASICREV_BCM5701, 2044 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 2045 "unknown BCM5701" }, 2046 2047 { BGE_ASICREV_BCM5703, 2048 0, 2049 "unknown BCM5703" }, 2050 2051 { BGE_ASICREV_BCM5704, 2052 BGE_QUIRK_ONLY_PHY_1, 2053 "unknown BCM5704" }, 2054 2055 { BGE_ASICREV_BCM5705, 2056 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2057 "unknown BCM5705" }, 2058 2059 { BGE_ASICREV_BCM5750, 2060 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 2061 "unknown BCM5750" }, 2062 2063 { 0, 2064 0, 2065 NULL } 2066 }; 2067 2068 2069 static const struct bge_revision * 2070 bge_lookup_rev(uint32_t chipid) 2071 { 2072 const struct bge_revision *br; 2073 2074 for (br = bge_revisions; br->br_name != NULL; br++) { 2075 if (br->br_chipid == chipid) 2076 return (br); 2077 } 2078 2079 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2080 if (br->br_chipid == BGE_ASICREV(chipid)) 2081 return (br); 2082 } 2083 2084 return (NULL); 2085 } 2086 2087 static const struct bge_product { 2088 pci_vendor_id_t bp_vendor; 2089 pci_product_id_t bp_product; 2090 const char *bp_name; 2091 } bge_products[] = { 2092 /* 2093 * The BCM5700 documentation seems to indicate that the hardware 2094 * still has the Alteon vendor ID burned into it, though it 2095 * should always be overridden by the value in the EEPROM. We'll 2096 * check for it anyway. 2097 */ 2098 { PCI_VENDOR_ALTEON, 2099 PCI_PRODUCT_ALTEON_BCM5700, 2100 "Broadcom BCM5700 Gigabit Ethernet", 2101 }, 2102 { PCI_VENDOR_ALTEON, 2103 PCI_PRODUCT_ALTEON_BCM5701, 2104 "Broadcom BCM5701 Gigabit Ethernet", 2105 }, 2106 2107 { PCI_VENDOR_ALTIMA, 2108 PCI_PRODUCT_ALTIMA_AC1000, 2109 "Altima AC1000 Gigabit Ethernet", 2110 }, 2111 { PCI_VENDOR_ALTIMA, 2112 PCI_PRODUCT_ALTIMA_AC1001, 2113 "Altima AC1001 Gigabit Ethernet", 2114 }, 2115 { PCI_VENDOR_ALTIMA, 2116 PCI_PRODUCT_ALTIMA_AC9100, 2117 "Altima AC9100 Gigabit Ethernet", 2118 }, 2119 2120 { PCI_VENDOR_BROADCOM, 2121 PCI_PRODUCT_BROADCOM_BCM5700, 2122 "Broadcom BCM5700 Gigabit Ethernet", 2123 }, 2124 { PCI_VENDOR_BROADCOM, 2125 PCI_PRODUCT_BROADCOM_BCM5701, 2126 "Broadcom BCM5701 Gigabit Ethernet", 2127 }, 2128 { PCI_VENDOR_BROADCOM, 2129 PCI_PRODUCT_BROADCOM_BCM5702, 2130 "Broadcom BCM5702 Gigabit Ethernet", 2131 }, 2132 { PCI_VENDOR_BROADCOM, 2133 PCI_PRODUCT_BROADCOM_BCM5702X, 2134 "Broadcom BCM5702X Gigabit Ethernet" }, 2135 2136 { PCI_VENDOR_BROADCOM, 2137 PCI_PRODUCT_BROADCOM_BCM5703, 2138 "Broadcom BCM5703 Gigabit Ethernet", 2139 }, 2140 { PCI_VENDOR_BROADCOM, 2141 PCI_PRODUCT_BROADCOM_BCM5703X, 2142 "Broadcom BCM5703X Gigabit Ethernet", 2143 }, 2144 { PCI_VENDOR_BROADCOM, 2145 PCI_PRODUCT_BROADCOM_BCM5703A3, 2146 "Broadcom BCM5703A3 Gigabit Ethernet", 2147 }, 2148 2149 { PCI_VENDOR_BROADCOM, 2150 PCI_PRODUCT_BROADCOM_BCM5704C, 2151 "Broadcom BCM5704C Dual Gigabit Ethernet", 2152 }, 2153 { PCI_VENDOR_BROADCOM, 2154 PCI_PRODUCT_BROADCOM_BCM5704S, 2155 "Broadcom BCM5704S Dual Gigabit Ethernet", 2156 }, 2157 2158 { PCI_VENDOR_BROADCOM, 2159 PCI_PRODUCT_BROADCOM_BCM5705, 2160 "Broadcom BCM5705 Gigabit Ethernet", 2161 }, 2162 { PCI_VENDOR_BROADCOM, 2163 PCI_PRODUCT_BROADCOM_BCM5705K, 2164 "Broadcom BCM5705K Gigabit Ethernet", 2165 }, 2166 { PCI_VENDOR_BROADCOM, 2167 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 2168 "Broadcom BCM5705 Gigabit Ethernet", 2169 }, 2170 { PCI_VENDOR_BROADCOM, 2171 PCI_PRODUCT_BROADCOM_BCM5705M, 2172 "Broadcom BCM5705M Gigabit Ethernet", 2173 }, 2174 2175 { PCI_VENDOR_BROADCOM, 2176 PCI_PRODUCT_BROADCOM_BCM5721, 2177 "Broadcom BCM5721 Gigabit Ethernet", 2178 }, 2179 2180 { PCI_VENDOR_BROADCOM, 2181 PCI_PRODUCT_BROADCOM_BCM5750, 2182 "Broadcom BCM5750 Gigabit Ethernet", 2183 }, 2184 2185 { PCI_VENDOR_BROADCOM, 2186 PCI_PRODUCT_BROADCOM_BCM5750M, 2187 "Broadcom BCM5750M Gigabit Ethernet", 2188 }, 2189 2190 { PCI_VENDOR_BROADCOM, 2191 PCI_PRODUCT_BROADCOM_BCM5751, 2192 "Broadcom BCM5751 Gigabit Ethernet", 2193 }, 2194 2195 { PCI_VENDOR_BROADCOM, 2196 PCI_PRODUCT_BROADCOM_BCM5751M, 2197 "Broadcom BCM5751M Gigabit Ethernet", 2198 }, 2199 2200 { PCI_VENDOR_BROADCOM, 2201 PCI_PRODUCT_BROADCOM_BCM5782, 2202 "Broadcom BCM5782 Gigabit Ethernet", 2203 }, 2204 { PCI_VENDOR_BROADCOM, 2205 PCI_PRODUCT_BROADCOM_BCM5788, 2206 "Broadcom BCM5788 Gigabit Ethernet", 2207 }, 2208 2209 { PCI_VENDOR_BROADCOM, 2210 PCI_PRODUCT_BROADCOM_BCM5901, 2211 "Broadcom BCM5901 Fast Ethernet", 2212 }, 2213 { PCI_VENDOR_BROADCOM, 2214 PCI_PRODUCT_BROADCOM_BCM5901A2, 2215 "Broadcom BCM5901A2 Fast Ethernet", 2216 }, 2217 2218 { PCI_VENDOR_SCHNEIDERKOCH, 2219 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2220 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2221 }, 2222 2223 { PCI_VENDOR_3COM, 2224 PCI_PRODUCT_3COM_3C996, 2225 "3Com 3c996 Gigabit Ethernet", 2226 }, 2227 2228 { 0, 2229 0, 2230 NULL }, 2231 }; 2232 2233 static const struct bge_product * 2234 bge_lookup(const struct pci_attach_args *pa) 2235 { 2236 const struct bge_product *bp; 2237 2238 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2239 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2240 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2241 return (bp); 2242 } 2243 2244 return (NULL); 2245 } 2246 2247 int 2248 bge_setpowerstate(sc, powerlevel) 2249 struct bge_softc *sc; 2250 int powerlevel; 2251 { 2252 #ifdef NOTYET 2253 u_int32_t pm_ctl = 0; 2254 2255 /* XXX FIXME: make sure indirect accesses enabled? */ 2256 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2257 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2258 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2259 2260 /* clear the PME_assert bit and power state bits, enable PME */ 2261 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2262 pm_ctl &= ~PCIM_PSTAT_DMASK; 2263 pm_ctl |= (1 << 8); 2264 2265 if (powerlevel == 0) { 2266 pm_ctl |= PCIM_PSTAT_D0; 2267 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2268 pm_ctl, 2); 2269 DELAY(10000); 2270 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2271 DELAY(10000); 2272 2273 #ifdef NOTYET 2274 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2275 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2276 #endif 2277 DELAY(40); DELAY(40); DELAY(40); 2278 DELAY(10000); /* above not quite adequate on 5700 */ 2279 return 0; 2280 } 2281 2282 2283 /* 2284 * Entering ACPI power states D1-D3 is achieved by wiggling 2285 * GMII gpio pins. Example code assumes all hardware vendors 2286 * followed Broadom's sample pcb layout. Until we verify that 2287 * for all supported OEM cards, states D1-D3 are unsupported. 2288 */ 2289 printf("%s: power state %d unimplemented; check GPIO pins\n", 2290 sc->bge_dev.dv_xname, powerlevel); 2291 #endif 2292 return EOPNOTSUPP; 2293 } 2294 2295 2296 /* 2297 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2298 * against our list and return its name if we find a match. Note 2299 * that since the Broadcom controller contains VPD support, we 2300 * can get the device name string from the controller itself instead 2301 * of the compiled-in string. This is a little slow, but it guarantees 2302 * we'll always announce the right product name. 2303 */ 2304 int 2305 bge_probe(parent, match, aux) 2306 struct device *parent; 2307 struct cfdata *match; 2308 void *aux; 2309 { 2310 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2311 2312 if (bge_lookup(pa) != NULL) 2313 return (1); 2314 2315 return (0); 2316 } 2317 2318 void 2319 bge_attach(parent, self, aux) 2320 struct device *parent, *self; 2321 void *aux; 2322 { 2323 struct bge_softc *sc = (struct bge_softc *)self; 2324 struct pci_attach_args *pa = aux; 2325 const struct bge_product *bp; 2326 const struct bge_revision *br; 2327 pci_chipset_tag_t pc = pa->pa_pc; 2328 pci_intr_handle_t ih; 2329 const char *intrstr = NULL; 2330 bus_dma_segment_t seg; 2331 int rseg; 2332 u_int32_t hwcfg = 0; 2333 u_int32_t mac_addr = 0; 2334 u_int32_t command; 2335 struct ifnet *ifp; 2336 caddr_t kva; 2337 u_char eaddr[ETHER_ADDR_LEN]; 2338 pcireg_t memtype; 2339 bus_addr_t memaddr; 2340 bus_size_t memsize; 2341 u_int32_t pm_ctl; 2342 2343 bp = bge_lookup(pa); 2344 KASSERT(bp != NULL); 2345 2346 sc->bge_pa = *pa; 2347 2348 aprint_naive(": Ethernet controller\n"); 2349 aprint_normal(": %s\n", bp->bp_name); 2350 2351 /* 2352 * Map control/status registers. 2353 */ 2354 DPRINTFN(5, ("Map control/status regs\n")); 2355 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2356 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2357 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2358 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2359 2360 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2361 aprint_error("%s: failed to enable memory mapping!\n", 2362 sc->bge_dev.dv_xname); 2363 return; 2364 } 2365 2366 DPRINTFN(5, ("pci_mem_find\n")); 2367 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2368 switch (memtype) { 2369 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2370 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2371 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2372 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2373 &memaddr, &memsize) == 0) 2374 break; 2375 default: 2376 aprint_error("%s: can't find mem space\n", 2377 sc->bge_dev.dv_xname); 2378 return; 2379 } 2380 2381 DPRINTFN(5, ("pci_intr_map\n")); 2382 if (pci_intr_map(pa, &ih)) { 2383 aprint_error("%s: couldn't map interrupt\n", 2384 sc->bge_dev.dv_xname); 2385 return; 2386 } 2387 2388 DPRINTFN(5, ("pci_intr_string\n")); 2389 intrstr = pci_intr_string(pc, ih); 2390 2391 DPRINTFN(5, ("pci_intr_establish\n")); 2392 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2393 2394 if (sc->bge_intrhand == NULL) { 2395 aprint_error("%s: couldn't establish interrupt", 2396 sc->bge_dev.dv_xname); 2397 if (intrstr != NULL) 2398 aprint_normal(" at %s", intrstr); 2399 aprint_normal("\n"); 2400 return; 2401 } 2402 aprint_normal("%s: interrupting at %s\n", 2403 sc->bge_dev.dv_xname, intrstr); 2404 2405 /* 2406 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2407 * can clobber the chip's PCI config-space power control registers, 2408 * leaving the card in D3 powersave state. 2409 * We do not have memory-mapped registers in this state, 2410 * so force device into D0 state before starting initialization. 2411 */ 2412 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2413 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2414 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2415 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2416 DELAY(1000); /* 27 usec is allegedly sufficent */ 2417 2418 /* 2419 * Save ASIC rev. Look up any quirks associated with this 2420 * ASIC. 2421 */ 2422 sc->bge_chipid = 2423 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2424 BGE_PCIMISCCTL_ASICREV; 2425 2426 /* 2427 * Detect PCI-Express devices 2428 * XXX: guessed from Linux/FreeBSD; no documentation 2429 */ 2430 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 && 2431 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 2432 NULL, NULL) != 0) 2433 sc->bge_pcie = 1; 2434 else 2435 sc->bge_pcie = 0; 2436 2437 /* Try to reset the chip. */ 2438 DPRINTFN(5, ("bge_reset\n")); 2439 bge_reset(sc); 2440 2441 if (bge_chipinit(sc)) { 2442 aprint_error("%s: chip initialization failed\n", 2443 sc->bge_dev.dv_xname); 2444 bge_release_resources(sc); 2445 return; 2446 } 2447 2448 /* 2449 * Get station address from the EEPROM. 2450 */ 2451 mac_addr = bge_readmem_ind(sc, 0x0c14); 2452 if ((mac_addr >> 16) == 0x484b) { 2453 eaddr[0] = (u_char)(mac_addr >> 8); 2454 eaddr[1] = (u_char)(mac_addr >> 0); 2455 mac_addr = bge_readmem_ind(sc, 0x0c18); 2456 eaddr[2] = (u_char)(mac_addr >> 24); 2457 eaddr[3] = (u_char)(mac_addr >> 16); 2458 eaddr[4] = (u_char)(mac_addr >> 8); 2459 eaddr[5] = (u_char)(mac_addr >> 0); 2460 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2461 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2462 aprint_error("%s: failed to read station address\n", 2463 sc->bge_dev.dv_xname); 2464 bge_release_resources(sc); 2465 return; 2466 } 2467 2468 br = bge_lookup_rev(sc->bge_chipid); 2469 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2470 2471 if (br == NULL) { 2472 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2473 sc->bge_quirks = 0; 2474 } else { 2475 aprint_normal("ASIC %s (0x%04x)", 2476 br->br_name, sc->bge_chipid >> 16); 2477 sc->bge_quirks |= br->br_quirks; 2478 } 2479 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2480 2481 /* Allocate the general information block and ring buffers. */ 2482 if (pci_dma64_available(pa)) 2483 sc->bge_dmatag = pa->pa_dmat64; 2484 else 2485 sc->bge_dmatag = pa->pa_dmat; 2486 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2487 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2488 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2489 aprint_error("%s: can't alloc rx buffers\n", 2490 sc->bge_dev.dv_xname); 2491 return; 2492 } 2493 DPRINTFN(5, ("bus_dmamem_map\n")); 2494 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2495 sizeof(struct bge_ring_data), &kva, 2496 BUS_DMA_NOWAIT)) { 2497 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2498 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2499 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2500 return; 2501 } 2502 DPRINTFN(5, ("bus_dmamem_create\n")); 2503 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2504 sizeof(struct bge_ring_data), 0, 2505 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2506 aprint_error("%s: can't create DMA map\n", 2507 sc->bge_dev.dv_xname); 2508 bus_dmamem_unmap(sc->bge_dmatag, kva, 2509 sizeof(struct bge_ring_data)); 2510 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2511 return; 2512 } 2513 DPRINTFN(5, ("bus_dmamem_load\n")); 2514 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2515 sizeof(struct bge_ring_data), NULL, 2516 BUS_DMA_NOWAIT)) { 2517 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2518 bus_dmamem_unmap(sc->bge_dmatag, kva, 2519 sizeof(struct bge_ring_data)); 2520 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2521 return; 2522 } 2523 2524 DPRINTFN(5, ("bzero\n")); 2525 sc->bge_rdata = (struct bge_ring_data *)kva; 2526 2527 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2528 2529 /* Try to allocate memory for jumbo buffers. */ 2530 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2531 if (bge_alloc_jumbo_mem(sc)) { 2532 aprint_error("%s: jumbo buffer allocation failed\n", 2533 sc->bge_dev.dv_xname); 2534 } else 2535 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2536 } 2537 2538 /* Set default tuneable values. */ 2539 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2540 sc->bge_rx_coal_ticks = 150; 2541 sc->bge_rx_max_coal_bds = 64; 2542 #ifdef ORIG_WPAUL_VALUES 2543 sc->bge_tx_coal_ticks = 150; 2544 sc->bge_tx_max_coal_bds = 128; 2545 #else 2546 sc->bge_tx_coal_ticks = 300; 2547 sc->bge_tx_max_coal_bds = 400; 2548 #endif 2549 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 2550 sc->bge_tx_coal_ticks = (12 * 5); 2551 sc->bge_rx_max_coal_bds = (12 * 5); 2552 aprint_error("%s: setting short Tx thresholds\n", 2553 sc->bge_dev.dv_xname); 2554 } 2555 2556 /* Set up ifnet structure */ 2557 ifp = &sc->ethercom.ec_if; 2558 ifp->if_softc = sc; 2559 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2560 ifp->if_ioctl = bge_ioctl; 2561 ifp->if_start = bge_start; 2562 ifp->if_init = bge_init; 2563 ifp->if_watchdog = bge_watchdog; 2564 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2565 IFQ_SET_READY(&ifp->if_snd); 2566 DPRINTFN(5, ("bcopy\n")); 2567 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2568 2569 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2570 sc->ethercom.ec_if.if_capabilities |= 2571 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2572 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2573 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2574 sc->ethercom.ec_capabilities |= 2575 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2576 2577 if (sc->bge_pcie) 2578 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2579 2580 /* 2581 * Do MII setup. 2582 */ 2583 DPRINTFN(5, ("mii setup\n")); 2584 sc->bge_mii.mii_ifp = ifp; 2585 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2586 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2587 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2588 2589 /* 2590 * Figure out what sort of media we have by checking the 2591 * hardware config word in the first 32k of NIC internal memory, 2592 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2593 * cards, this value appears to be unset. If that's the 2594 * case, we have to rely on identifying the NIC by its PCI 2595 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2596 */ 2597 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2598 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2599 } else { 2600 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2601 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2602 hwcfg = be32toh(hwcfg); 2603 } 2604 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2605 sc->bge_tbi = 1; 2606 2607 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2608 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2609 SK_SUBSYSID_9D41) 2610 sc->bge_tbi = 1; 2611 2612 if (sc->bge_tbi) { 2613 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2614 bge_ifmedia_sts); 2615 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2616 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2617 0, NULL); 2618 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2619 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2620 } else { 2621 /* 2622 * Do transceiver setup. 2623 */ 2624 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2625 bge_ifmedia_sts); 2626 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2627 MII_PHY_ANY, MII_OFFSET_ANY, 2628 MIIF_FORCEANEG|MIIF_DOPAUSE); 2629 2630 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2631 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2632 ifmedia_add(&sc->bge_mii.mii_media, 2633 IFM_ETHER|IFM_MANUAL, 0, NULL); 2634 ifmedia_set(&sc->bge_mii.mii_media, 2635 IFM_ETHER|IFM_MANUAL); 2636 } else 2637 ifmedia_set(&sc->bge_mii.mii_media, 2638 IFM_ETHER|IFM_AUTO); 2639 } 2640 2641 /* 2642 * When using the BCM5701 in PCI-X mode, data corruption has 2643 * been observed in the first few bytes of some received packets. 2644 * Aligning the packet buffer in memory eliminates the corruption. 2645 * Unfortunately, this misaligns the packet payloads. On platforms 2646 * which do not support unaligned accesses, we will realign the 2647 * payloads by copying the received packets. 2648 */ 2649 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2650 /* If in PCI-X mode, work around the alignment bug. */ 2651 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2652 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2653 BGE_PCISTATE_PCI_BUSSPEED) 2654 sc->bge_rx_alignment_bug = 1; 2655 } 2656 2657 /* 2658 * Call MI attach routine. 2659 */ 2660 DPRINTFN(5, ("if_attach\n")); 2661 if_attach(ifp); 2662 DPRINTFN(5, ("ether_ifattach\n")); 2663 ether_ifattach(ifp, eaddr); 2664 #ifdef BGE_EVENT_COUNTERS 2665 /* 2666 * Attach event counters. 2667 */ 2668 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2669 NULL, sc->bge_dev.dv_xname, "intr"); 2670 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2671 NULL, sc->bge_dev.dv_xname, "tx_xoff"); 2672 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2673 NULL, sc->bge_dev.dv_xname, "tx_xon"); 2674 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2675 NULL, sc->bge_dev.dv_xname, "rx_xoff"); 2676 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2677 NULL, sc->bge_dev.dv_xname, "rx_xon"); 2678 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2679 NULL, sc->bge_dev.dv_xname, "rx_macctl"); 2680 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2681 NULL, sc->bge_dev.dv_xname, "xoffentered"); 2682 #endif /* BGE_EVENT_COUNTERS */ 2683 DPRINTFN(5, ("callout_init\n")); 2684 callout_init(&sc->bge_timeout); 2685 2686 sc->bge_powerhook = powerhook_establish(bge_powerhook, sc); 2687 if (sc->bge_powerhook == NULL) 2688 printf("%s: WARNING: unable to establish PCI power hook\n", 2689 sc->bge_dev.dv_xname); 2690 } 2691 2692 void 2693 bge_release_resources(sc) 2694 struct bge_softc *sc; 2695 { 2696 if (sc->bge_vpd_prodname != NULL) 2697 free(sc->bge_vpd_prodname, M_DEVBUF); 2698 2699 if (sc->bge_vpd_readonly != NULL) 2700 free(sc->bge_vpd_readonly, M_DEVBUF); 2701 } 2702 2703 void 2704 bge_reset(sc) 2705 struct bge_softc *sc; 2706 { 2707 struct pci_attach_args *pa = &sc->bge_pa; 2708 u_int32_t cachesize, command, pcistate, new_pcistate; 2709 int i, val; 2710 2711 /* Save some important PCI state. */ 2712 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2713 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2714 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2715 2716 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2717 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2718 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2719 2720 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2721 /* 2722 * XXX: from FreeBSD/Linux; no documentation 2723 */ 2724 if (sc->bge_pcie) { 2725 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2726 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2727 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2728 /* No idea what that actually means */ 2729 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2730 val |= (1<<29); 2731 } 2732 } 2733 2734 /* Issue global reset */ 2735 bge_writereg_ind(sc, BGE_MISC_CFG, val); 2736 2737 DELAY(1000); 2738 2739 /* 2740 * XXX: from FreeBSD/Linux; no documentation 2741 */ 2742 if (sc->bge_pcie) { 2743 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2744 pcireg_t reg; 2745 2746 DELAY(500000); 2747 /* XXX: Magic Numbers */ 2748 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0); 2749 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0, 2750 reg | (1 << 15)); 2751 } 2752 /* 2753 * XXX: Magic Numbers. 2754 * Sets maximal PCI-e payload and clears any PCI-e errors. 2755 * Should be replaced with references to PCI config-space 2756 * capability block for PCI-Express. 2757 */ 2758 pci_conf_write(pa->pa_pc, pa->pa_tag, 2759 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2760 2761 } 2762 2763 /* Reset some of the PCI state that got zapped by reset */ 2764 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2765 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2766 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2767 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2768 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2769 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2770 2771 /* Enable memory arbiter. */ 2772 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2773 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2774 } 2775 2776 /* 2777 * Prevent PXE restart: write a magic number to the 2778 * general communications memory at 0xB50. 2779 */ 2780 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2781 2782 /* 2783 * Poll the value location we just wrote until 2784 * we see the 1's complement of the magic number. 2785 * This indicates that the firmware initialization 2786 * is complete. 2787 */ 2788 for (i = 0; i < BGE_TIMEOUT; i++) { 2789 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2790 if (val == ~BGE_MAGIC_NUMBER) 2791 break; 2792 DELAY(1000); 2793 } 2794 2795 if (i >= BGE_TIMEOUT) { 2796 printf("%s: firmware handshake timed out, val = %x\n", 2797 sc->bge_dev.dv_xname, val); 2798 /* 2799 * XXX: occasionally fired on bcm5721, but without 2800 * apparent harm. For now, keep going if we timeout 2801 * against PCI-E devices. 2802 */ 2803 if (!sc->bge_pcie) 2804 return; 2805 } 2806 2807 /* 2808 * XXX Wait for the value of the PCISTATE register to 2809 * return to its original pre-reset state. This is a 2810 * fairly good indicator of reset completion. If we don't 2811 * wait for the reset to fully complete, trying to read 2812 * from the device's non-PCI registers may yield garbage 2813 * results. 2814 */ 2815 for (i = 0; i < BGE_TIMEOUT; i++) { 2816 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2817 BGE_PCI_PCISTATE); 2818 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2819 (pcistate & ~BGE_PCISTATE_RESERVED)) 2820 break; 2821 DELAY(10); 2822 } 2823 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2824 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2825 printf("%s: pcistate failed to revert\n", 2826 sc->bge_dev.dv_xname); 2827 } 2828 2829 /* XXX: from FreeBSD/Linux; no documentation */ 2830 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2831 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2832 2833 /* Enable memory arbiter. */ 2834 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2835 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2836 } 2837 2838 /* Fix up byte swapping */ 2839 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2840 2841 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2842 2843 DELAY(10000); 2844 } 2845 2846 /* 2847 * Frame reception handling. This is called if there's a frame 2848 * on the receive return list. 2849 * 2850 * Note: we have to be able to handle two possibilities here: 2851 * 1) the frame is from the jumbo recieve ring 2852 * 2) the frame is from the standard receive ring 2853 */ 2854 2855 void 2856 bge_rxeof(sc) 2857 struct bge_softc *sc; 2858 { 2859 struct ifnet *ifp; 2860 int stdcnt = 0, jumbocnt = 0; 2861 bus_dmamap_t dmamap; 2862 bus_addr_t offset, toff; 2863 bus_size_t tlen; 2864 int tosync; 2865 2866 ifp = &sc->ethercom.ec_if; 2867 2868 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2869 offsetof(struct bge_ring_data, bge_status_block), 2870 sizeof (struct bge_status_block), 2871 BUS_DMASYNC_POSTREAD); 2872 2873 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2874 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2875 sc->bge_rx_saved_considx; 2876 2877 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2878 2879 if (tosync < 0) { 2880 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2881 sizeof (struct bge_rx_bd); 2882 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2883 toff, tlen, BUS_DMASYNC_POSTREAD); 2884 tosync = -tosync; 2885 } 2886 2887 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2888 offset, tosync * sizeof (struct bge_rx_bd), 2889 BUS_DMASYNC_POSTREAD); 2890 2891 while(sc->bge_rx_saved_considx != 2892 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2893 struct bge_rx_bd *cur_rx; 2894 u_int32_t rxidx; 2895 struct mbuf *m = NULL; 2896 2897 cur_rx = &sc->bge_rdata-> 2898 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2899 2900 rxidx = cur_rx->bge_idx; 2901 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2902 2903 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2904 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2905 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2906 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2907 jumbocnt++; 2908 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2909 ifp->if_ierrors++; 2910 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2911 continue; 2912 } 2913 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2914 NULL)== ENOBUFS) { 2915 ifp->if_ierrors++; 2916 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2917 continue; 2918 } 2919 } else { 2920 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2921 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2922 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2923 stdcnt++; 2924 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2925 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2926 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2927 ifp->if_ierrors++; 2928 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2929 continue; 2930 } 2931 if (bge_newbuf_std(sc, sc->bge_std, 2932 NULL, dmamap) == ENOBUFS) { 2933 ifp->if_ierrors++; 2934 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2935 continue; 2936 } 2937 } 2938 2939 ifp->if_ipackets++; 2940 #ifndef __NO_STRICT_ALIGNMENT 2941 /* 2942 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2943 * the Rx buffer has the layer-2 header unaligned. 2944 * If our CPU requires alignment, re-align by copying. 2945 */ 2946 if (sc->bge_rx_alignment_bug) { 2947 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2948 cur_rx->bge_len); 2949 m->m_data += ETHER_ALIGN; 2950 } 2951 #endif 2952 2953 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2954 m->m_pkthdr.rcvif = ifp; 2955 2956 #if NBPFILTER > 0 2957 /* 2958 * Handle BPF listeners. Let the BPF user see the packet. 2959 */ 2960 if (ifp->if_bpf) 2961 bpf_mtap(ifp->if_bpf, m); 2962 #endif 2963 2964 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 2965 2966 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2967 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2968 /* 2969 * Rx transport checksum-offload may also 2970 * have bugs with packets which, when transmitted, 2971 * were `runts' requiring padding. 2972 */ 2973 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2974 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2975 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2976 m->m_pkthdr.csum_data = 2977 cur_rx->bge_tcp_udp_csum; 2978 m->m_pkthdr.csum_flags |= 2979 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2980 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2981 } 2982 2983 /* 2984 * If we received a packet with a vlan tag, pass it 2985 * to vlan_input() instead of ether_input(). 2986 */ 2987 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 2988 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 2989 2990 (*ifp->if_input)(ifp, m); 2991 } 2992 2993 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2994 if (stdcnt) 2995 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2996 if (jumbocnt) 2997 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2998 } 2999 3000 void 3001 bge_txeof(sc) 3002 struct bge_softc *sc; 3003 { 3004 struct bge_tx_bd *cur_tx = NULL; 3005 struct ifnet *ifp; 3006 struct txdmamap_pool_entry *dma; 3007 bus_addr_t offset, toff; 3008 bus_size_t tlen; 3009 int tosync; 3010 struct mbuf *m; 3011 3012 ifp = &sc->ethercom.ec_if; 3013 3014 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3015 offsetof(struct bge_ring_data, bge_status_block), 3016 sizeof (struct bge_status_block), 3017 BUS_DMASYNC_POSTREAD); 3018 3019 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3020 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3021 sc->bge_tx_saved_considx; 3022 3023 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3024 3025 if (tosync < 0) { 3026 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3027 sizeof (struct bge_tx_bd); 3028 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3029 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3030 tosync = -tosync; 3031 } 3032 3033 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3034 offset, tosync * sizeof (struct bge_tx_bd), 3035 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3036 3037 /* 3038 * Go through our tx ring and free mbufs for those 3039 * frames that have been sent. 3040 */ 3041 while (sc->bge_tx_saved_considx != 3042 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3043 u_int32_t idx = 0; 3044 3045 idx = sc->bge_tx_saved_considx; 3046 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3047 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3048 ifp->if_opackets++; 3049 m = sc->bge_cdata.bge_tx_chain[idx]; 3050 if (m != NULL) { 3051 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3052 dma = sc->txdma[idx]; 3053 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3054 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3055 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3056 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3057 sc->txdma[idx] = NULL; 3058 3059 m_freem(m); 3060 } 3061 sc->bge_txcnt--; 3062 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3063 ifp->if_timer = 0; 3064 } 3065 3066 if (cur_tx != NULL) 3067 ifp->if_flags &= ~IFF_OACTIVE; 3068 } 3069 3070 int 3071 bge_intr(xsc) 3072 void *xsc; 3073 { 3074 struct bge_softc *sc; 3075 struct ifnet *ifp; 3076 3077 sc = xsc; 3078 ifp = &sc->ethercom.ec_if; 3079 3080 #ifdef notdef 3081 /* Avoid this for now -- checking this register is expensive. */ 3082 /* Make sure this is really our interrupt. */ 3083 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 3084 return (0); 3085 #endif 3086 /* Ack interrupt and stop others from occuring. */ 3087 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3088 3089 BGE_EVCNT_INCR(sc->bge_ev_intr); 3090 3091 /* 3092 * Process link state changes. 3093 * Grrr. The link status word in the status block does 3094 * not work correctly on the BCM5700 rev AX and BX chips, 3095 * according to all avaibable information. Hence, we have 3096 * to enable MII interrupts in order to properly obtain 3097 * async link changes. Unfortunately, this also means that 3098 * we have to read the MAC status register to detect link 3099 * changes, thereby adding an additional register access to 3100 * the interrupt handler. 3101 */ 3102 3103 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 3104 u_int32_t status; 3105 3106 status = CSR_READ_4(sc, BGE_MAC_STS); 3107 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3108 sc->bge_link = 0; 3109 callout_stop(&sc->bge_timeout); 3110 bge_tick(sc); 3111 /* Clear the interrupt */ 3112 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3113 BGE_EVTENB_MI_INTERRUPT); 3114 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 3115 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 3116 BRGPHY_INTRS); 3117 } 3118 } else { 3119 if (sc->bge_rdata->bge_status_block.bge_status & 3120 BGE_STATFLAG_LINKSTATE_CHANGED) { 3121 sc->bge_link = 0; 3122 callout_stop(&sc->bge_timeout); 3123 bge_tick(sc); 3124 /* Clear the interrupt */ 3125 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3126 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3127 BGE_MACSTAT_LINK_CHANGED); 3128 } 3129 } 3130 3131 if (ifp->if_flags & IFF_RUNNING) { 3132 /* Check RX return ring producer/consumer */ 3133 bge_rxeof(sc); 3134 3135 /* Check TX ring producer/consumer */ 3136 bge_txeof(sc); 3137 } 3138 3139 if (sc->bge_pending_rxintr_change) { 3140 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3141 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3142 uint32_t junk; 3143 3144 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3145 DELAY(10); 3146 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3147 3148 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3149 DELAY(10); 3150 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3151 3152 sc->bge_pending_rxintr_change = 0; 3153 } 3154 bge_handle_events(sc); 3155 3156 /* Re-enable interrupts. */ 3157 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3158 3159 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3160 bge_start(ifp); 3161 3162 return (1); 3163 } 3164 3165 void 3166 bge_tick(xsc) 3167 void *xsc; 3168 { 3169 struct bge_softc *sc = xsc; 3170 struct mii_data *mii = &sc->bge_mii; 3171 struct ifmedia *ifm = NULL; 3172 struct ifnet *ifp = &sc->ethercom.ec_if; 3173 int s; 3174 3175 s = splnet(); 3176 3177 bge_stats_update(sc); 3178 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3179 if (sc->bge_link) { 3180 splx(s); 3181 return; 3182 } 3183 3184 if (sc->bge_tbi) { 3185 ifm = &sc->bge_ifmedia; 3186 if (CSR_READ_4(sc, BGE_MAC_STS) & 3187 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3188 sc->bge_link++; 3189 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3190 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3191 bge_start(ifp); 3192 } 3193 splx(s); 3194 return; 3195 } 3196 3197 mii_tick(mii); 3198 3199 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 3200 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3201 sc->bge_link++; 3202 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3203 bge_start(ifp); 3204 } 3205 3206 splx(s); 3207 } 3208 3209 void 3210 bge_stats_update(sc) 3211 struct bge_softc *sc; 3212 { 3213 struct ifnet *ifp = &sc->ethercom.ec_if; 3214 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3215 bus_size_t rstats = BGE_RX_STATS; 3216 3217 #define READ_RSTAT(sc, stats, stat) \ 3218 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3219 3220 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3221 ifp->if_collisions += 3222 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3223 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3224 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3225 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3226 3227 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3228 READ_RSTAT(sc, rstats, outXoffSent)); 3229 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3230 READ_RSTAT(sc, rstats, outXonSent)); 3231 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3232 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3233 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3234 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3235 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3236 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3237 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3238 READ_RSTAT(sc, rstats, xoffStateEntered)); 3239 return; 3240 } 3241 3242 #undef READ_RSTAT 3243 #define READ_STAT(sc, stats, stat) \ 3244 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3245 3246 ifp->if_collisions += 3247 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3248 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3249 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3250 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3251 ifp->if_collisions; 3252 3253 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3254 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3255 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3256 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3257 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3258 READ_STAT(sc, stats, 3259 xoffPauseFramesReceived.bge_addr_lo)); 3260 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3261 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3262 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3263 READ_STAT(sc, stats, 3264 macControlFramesReceived.bge_addr_lo)); 3265 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3266 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3267 3268 #undef READ_STAT 3269 3270 #ifdef notdef 3271 ifp->if_collisions += 3272 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3273 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3274 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3275 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3276 ifp->if_collisions; 3277 #endif 3278 } 3279 3280 /* 3281 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3282 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3283 * but when such padded frames employ the bge IP/TCP checksum offload, 3284 * the hardware checksum assist gives incorrect results (possibly 3285 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3286 * If we pad such runts with zeros, the onboard checksum comes out correct. 3287 */ 3288 static __inline int 3289 bge_cksum_pad(struct mbuf *pkt) 3290 { 3291 struct mbuf *last = NULL; 3292 int padlen; 3293 3294 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3295 3296 /* if there's only the packet-header and we can pad there, use it. */ 3297 if (pkt->m_pkthdr.len == pkt->m_len && 3298 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 3299 last = pkt; 3300 } else { 3301 /* 3302 * Walk packet chain to find last mbuf. We will either 3303 * pad there, or append a new mbuf and pad it 3304 * (thus perhaps avoiding the bcm5700 dma-min bug). 3305 */ 3306 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3307 (void) 0; /* do nothing*/ 3308 } 3309 3310 /* `last' now points to last in chain. */ 3311 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 3312 (void) 0; /* we can pad here, in-place. */ 3313 } else { 3314 /* Allocate new empty mbuf, pad it. Compact later. */ 3315 struct mbuf *n; 3316 MGET(n, M_DONTWAIT, MT_DATA); 3317 n->m_len = 0; 3318 last->m_next = n; 3319 last = n; 3320 } 3321 } 3322 3323 #ifdef DEBUG 3324 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 3325 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 3326 #endif 3327 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3328 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3329 last->m_len += padlen; 3330 pkt->m_pkthdr.len += padlen; 3331 return 0; 3332 } 3333 3334 /* 3335 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3336 */ 3337 static __inline int 3338 bge_compact_dma_runt(struct mbuf *pkt) 3339 { 3340 struct mbuf *m, *prev; 3341 int totlen, prevlen; 3342 3343 prev = NULL; 3344 totlen = 0; 3345 prevlen = -1; 3346 3347 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3348 int mlen = m->m_len; 3349 int shortfall = 8 - mlen ; 3350 3351 totlen += mlen; 3352 if (mlen == 0) { 3353 continue; 3354 } 3355 if (mlen >= 8) 3356 continue; 3357 3358 /* If we get here, mbuf data is too small for DMA engine. 3359 * Try to fix by shuffling data to prev or next in chain. 3360 * If that fails, do a compacting deep-copy of the whole chain. 3361 */ 3362 3363 /* Internal frag. If fits in prev, copy it there. */ 3364 if (prev && !M_READONLY(prev) && 3365 M_TRAILINGSPACE(prev) >= m->m_len) { 3366 bcopy(m->m_data, 3367 prev->m_data+prev->m_len, 3368 mlen); 3369 prev->m_len += mlen; 3370 m->m_len = 0; 3371 /* XXX stitch chain */ 3372 prev->m_next = m_free(m); 3373 m = prev; 3374 continue; 3375 } 3376 else if (m->m_next != NULL && !M_READONLY(m) && 3377 M_TRAILINGSPACE(m) >= shortfall && 3378 m->m_next->m_len >= (8 + shortfall)) { 3379 /* m is writable and have enough data in next, pull up. */ 3380 3381 bcopy(m->m_next->m_data, 3382 m->m_data+m->m_len, 3383 shortfall); 3384 m->m_len += shortfall; 3385 m->m_next->m_len -= shortfall; 3386 m->m_next->m_data += shortfall; 3387 } 3388 else if (m->m_next == NULL || 1) { 3389 /* Got a runt at the very end of the packet. 3390 * borrow data from the tail of the preceding mbuf and 3391 * update its length in-place. (The original data is still 3392 * valid, so we can do this even if prev is not writable.) 3393 */ 3394 3395 /* if we'd make prev a runt, just move all of its data. */ 3396 #ifdef DEBUG 3397 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3398 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3399 #endif 3400 if ((prev->m_len - shortfall) < 8) 3401 shortfall = prev->m_len; 3402 3403 #ifdef notyet /* just do the safe slow thing for now */ 3404 if (!M_READONLY(m)) { 3405 if (M_LEADINGSPACE(m) < shorfall) { 3406 void *m_dat; 3407 m_dat = (m->m_flags & M_PKTHDR) ? 3408 m->m_pktdat : m->dat; 3409 memmove(m_dat, mtod(m, void*), m->m_len); 3410 m->m_data = m_dat; 3411 } 3412 } else 3413 #endif /* just do the safe slow thing */ 3414 { 3415 struct mbuf * n = NULL; 3416 int newprevlen = prev->m_len - shortfall; 3417 3418 MGET(n, M_NOWAIT, MT_DATA); 3419 if (n == NULL) 3420 return ENOBUFS; 3421 KASSERT(m->m_len + shortfall < MLEN 3422 /*, 3423 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3424 3425 /* first copy the data we're stealing from prev */ 3426 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3427 3428 /* update prev->m_len accordingly */ 3429 prev->m_len -= shortfall; 3430 3431 /* copy data from runt m */ 3432 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3433 3434 /* n holds what we stole from prev, plus m */ 3435 n->m_len = shortfall + m->m_len; 3436 3437 /* stitch n into chain and free m */ 3438 n->m_next = m->m_next; 3439 prev->m_next = n; 3440 /* KASSERT(m->m_next == NULL); */ 3441 m->m_next = NULL; 3442 m_free(m); 3443 m = n; /* for continuing loop */ 3444 } 3445 } 3446 prevlen = m->m_len; 3447 } 3448 return 0; 3449 } 3450 3451 /* 3452 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3453 * pointers to descriptors. 3454 */ 3455 int 3456 bge_encap(sc, m_head, txidx) 3457 struct bge_softc *sc; 3458 struct mbuf *m_head; 3459 u_int32_t *txidx; 3460 { 3461 struct bge_tx_bd *f = NULL; 3462 u_int32_t frag, cur, cnt = 0; 3463 u_int16_t csum_flags = 0; 3464 u_int16_t txbd_tso_flags = 0; 3465 struct txdmamap_pool_entry *dma; 3466 bus_dmamap_t dmamap; 3467 int i = 0; 3468 struct m_tag *mtag; 3469 int use_tso, maxsegsize, error; 3470 3471 cur = frag = *txidx; 3472 3473 if (m_head->m_pkthdr.csum_flags) { 3474 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3475 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3476 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3477 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3478 } 3479 3480 /* 3481 * If we were asked to do an outboard checksum, and the NIC 3482 * has the bug where it sometimes adds in the Ethernet padding, 3483 * explicitly pad with zeros so the cksum will be correct either way. 3484 * (For now, do this for all chip versions, until newer 3485 * are confirmed to not require the workaround.) 3486 */ 3487 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3488 #ifdef notyet 3489 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3490 #endif 3491 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3492 goto check_dma_bug; 3493 3494 if (bge_cksum_pad(m_head) != 0) { 3495 return ENOBUFS; 3496 } 3497 3498 check_dma_bug: 3499 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3500 goto doit; 3501 /* 3502 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3503 * less than eight bytes. If we encounter a teeny mbuf 3504 * at the end of a chain, we can pad. Otherwise, copy. 3505 */ 3506 if (bge_compact_dma_runt(m_head) != 0) 3507 return ENOBUFS; 3508 3509 doit: 3510 dma = SLIST_FIRST(&sc->txdma_list); 3511 if (dma == NULL) 3512 return ENOBUFS; 3513 dmamap = dma->dmamap; 3514 3515 /* 3516 * Set up any necessary TSO state before we start packing... 3517 */ 3518 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3519 if (!use_tso) { 3520 maxsegsize = 0; 3521 } else { /* TSO setup */ 3522 unsigned mss; 3523 struct ether_header *eh; 3524 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3525 struct mbuf * m0 = m_head; 3526 struct ip *ip; 3527 struct tcphdr *th; 3528 int iphl, hlen; 3529 3530 /* 3531 * XXX It would be nice if the mbuf pkthdr had offset 3532 * fields for the protocol headers. 3533 */ 3534 3535 eh = mtod(m0, struct ether_header *); 3536 switch (htons(eh->ether_type)) { 3537 case ETHERTYPE_IP: 3538 offset = ETHER_HDR_LEN; 3539 break; 3540 3541 case ETHERTYPE_VLAN: 3542 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3543 break; 3544 3545 default: 3546 /* 3547 * Don't support this protocol or encapsulation. 3548 */ 3549 return (ENOBUFS); 3550 } 3551 3552 /* 3553 * TCP/IP headers are in the first mbuf; we can do 3554 * this the easy way. 3555 */ 3556 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3557 hlen = iphl + offset; 3558 if (__predict_false(m0->m_len < 3559 (hlen + sizeof(struct tcphdr)))) { 3560 3561 printf("TSO: hard case m0->m_len == %d <" 3562 " ip/tcp hlen%d, not handled yet\n", 3563 m0->m_len, hlen+ sizeof(struct tcphdr)); 3564 #ifdef NOTYET 3565 /* 3566 * XXX jonathan (at) NetBSD.org: untested. 3567 * how to force this branch to be taken? 3568 */ 3569 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3570 3571 m_copydata(m0, offset, sizeof(ip), &ip); 3572 m_copydata(m0, hlen, sizeof(th), &th); 3573 3574 ip.ip_len = 0; 3575 3576 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3577 sizeof(ip.ip_len), &ip.ip_len); 3578 3579 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3580 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3581 3582 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3583 sizeof(th.th_sum), &th.th_sum); 3584 3585 hlen += th.th_off << 2; 3586 iptcp_opt_words = hlen; 3587 #else 3588 /* 3589 * if_wm "hard" case not yet supported, can we not 3590 * mandate it out of existence? 3591 */ 3592 (void) ip; (void)th; (void) ip_tcp_hlen; 3593 3594 return ENOBUFS; 3595 #endif 3596 } else { 3597 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 3598 th = (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 3599 ip_tcp_hlen = iphl + (th->th_off << 2); 3600 3601 /* Total IP/TCP options, in 32-bit words */ 3602 iptcp_opt_words = (ip_tcp_hlen 3603 - sizeof(struct tcphdr) 3604 - sizeof(struct ip)) >> 2; 3605 } 3606 if (BGE_IS_5750_OR_BEYOND(sc)) { 3607 th->th_sum = 0; 3608 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3609 } else { 3610 /* 3611 * XXX jonathan (at) NetBSD.org: 5705 untested. 3612 * Requires TSO firmware patch for 5701/5703/5704. 3613 */ 3614 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3615 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3616 } 3617 3618 mss = m_head->m_pkthdr.segsz; 3619 txbd_tso_flags |= 3620 BGE_TXBDFLAG_CPU_PRE_DMA | 3621 BGE_TXBDFLAG_CPU_POST_DMA; 3622 3623 /* 3624 * Our NIC TSO-assist assumes TSO has standard, optionless 3625 * IPv4 and TCP headers, which total 40 bytes. By default, 3626 * the NIC copies 40 bytes of IP/TCP header from the 3627 * supplied header into the IP/TCP header portion of 3628 * each post-TSO-segment. If the supplied packet has IP or 3629 * TCP options, we need to tell the NIC to copy those extra 3630 * bytes into each post-TSO header, in addition to the normal 3631 * 40-byte IP/TCP header (and to leave space accordingly). 3632 * Unfortunately, the driver encoding of option length 3633 * varies across different ASIC families. 3634 */ 3635 tcp_seg_flags = 0; 3636 if (iptcp_opt_words) { 3637 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3638 tcp_seg_flags = 3639 iptcp_opt_words << 11; 3640 } else { 3641 txbd_tso_flags |= 3642 iptcp_opt_words << 12; 3643 } 3644 } 3645 maxsegsize = mss | tcp_seg_flags; 3646 ip->ip_len = htons(mss + ip_tcp_hlen); 3647 3648 } /* TSO setup */ 3649 3650 /* 3651 * Start packing the mbufs in this chain into 3652 * the fragment pointers. Stop when we run out 3653 * of fragments or hit the end of the mbuf chain. 3654 */ 3655 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3656 BUS_DMA_NOWAIT); 3657 if (error) { 3658 return(ENOBUFS); 3659 } 3660 3661 mtag = sc->ethercom.ec_nvlans ? 3662 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3663 3664 3665 /* Iterate over dmap-map fragments. */ 3666 for (i = 0; i < dmamap->dm_nsegs; i++) { 3667 f = &sc->bge_rdata->bge_tx_ring[frag]; 3668 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3669 break; 3670 3671 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3672 f->bge_len = dmamap->dm_segs[i].ds_len; 3673 3674 /* 3675 * For 5751 and follow-ons, for TSO we must turn 3676 * off checksum-assist flag in the tx-descr, and 3677 * supply the ASIC-revision-specific encoding 3678 * of TSO flags and segsize. 3679 */ 3680 if (use_tso) { 3681 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3682 f->bge_rsvd = maxsegsize; 3683 f->bge_flags = csum_flags | txbd_tso_flags; 3684 } else { 3685 f->bge_rsvd = 0; 3686 f->bge_flags = 3687 (csum_flags | txbd_tso_flags) & 0x0fff; 3688 } 3689 } else { 3690 f->bge_rsvd = 0; 3691 f->bge_flags = csum_flags; 3692 } 3693 3694 if (mtag != NULL) { 3695 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3696 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3697 } else { 3698 f->bge_vlan_tag = 0; 3699 } 3700 /* 3701 * Sanity check: avoid coming within 16 descriptors 3702 * of the end of the ring. 3703 */ 3704 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) { 3705 BGE_TSO_PRINTF(("%s: " 3706 " dmamap_load_mbuf too close to ring wrap\n", 3707 sc->bge_dev.dv_xname)); 3708 return(ENOBUFS); 3709 } 3710 cur = frag; 3711 BGE_INC(frag, BGE_TX_RING_CNT); 3712 cnt++; 3713 } 3714 3715 if (i < dmamap->dm_nsegs) { 3716 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3717 sc->bge_dev.dv_xname, i, dmamap->dm_nsegs)); 3718 return ENOBUFS; 3719 } 3720 3721 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3722 BUS_DMASYNC_PREWRITE); 3723 3724 if (frag == sc->bge_tx_saved_considx) { 3725 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3726 sc->bge_dev.dv_xname, frag, sc->bge_tx_saved_considx)); 3727 3728 return(ENOBUFS); 3729 } 3730 3731 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3732 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3733 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3734 sc->txdma[cur] = dma; 3735 sc->bge_txcnt += cnt; 3736 3737 *txidx = frag; 3738 3739 return(0); 3740 } 3741 3742 /* 3743 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3744 * to the mbuf data regions directly in the transmit descriptors. 3745 */ 3746 void 3747 bge_start(ifp) 3748 struct ifnet *ifp; 3749 { 3750 struct bge_softc *sc; 3751 struct mbuf *m_head = NULL; 3752 u_int32_t prodidx; 3753 int pkts = 0; 3754 3755 sc = ifp->if_softc; 3756 3757 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3758 return; 3759 3760 prodidx = sc->bge_tx_prodidx; 3761 3762 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3763 IFQ_POLL(&ifp->if_snd, m_head); 3764 if (m_head == NULL) 3765 break; 3766 3767 #if 0 3768 /* 3769 * XXX 3770 * safety overkill. If this is a fragmented packet chain 3771 * with delayed TCP/UDP checksums, then only encapsulate 3772 * it if we have enough descriptors to handle the entire 3773 * chain at once. 3774 * (paranoia -- may not actually be needed) 3775 */ 3776 if (m_head->m_flags & M_FIRSTFRAG && 3777 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3778 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3779 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3780 ifp->if_flags |= IFF_OACTIVE; 3781 break; 3782 } 3783 } 3784 #endif 3785 3786 /* 3787 * Pack the data into the transmit ring. If we 3788 * don't have room, set the OACTIVE flag and wait 3789 * for the NIC to drain the ring. 3790 */ 3791 if (bge_encap(sc, m_head, &prodidx)) { 3792 printf("bge: failed on len %d?\n", m_head->m_pkthdr.len); 3793 ifp->if_flags |= IFF_OACTIVE; 3794 break; 3795 } 3796 3797 /* now we are committed to transmit the packet */ 3798 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3799 pkts++; 3800 3801 #if NBPFILTER > 0 3802 /* 3803 * If there's a BPF listener, bounce a copy of this frame 3804 * to him. 3805 */ 3806 if (ifp->if_bpf) 3807 bpf_mtap(ifp->if_bpf, m_head); 3808 #endif 3809 } 3810 if (pkts == 0) 3811 return; 3812 3813 /* Transmit */ 3814 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3815 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3816 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3817 3818 sc->bge_tx_prodidx = prodidx; 3819 3820 /* 3821 * Set a timeout in case the chip goes out to lunch. 3822 */ 3823 ifp->if_timer = 5; 3824 } 3825 3826 int 3827 bge_init(ifp) 3828 struct ifnet *ifp; 3829 { 3830 struct bge_softc *sc = ifp->if_softc; 3831 u_int16_t *m; 3832 int s, error; 3833 3834 s = splnet(); 3835 3836 ifp = &sc->ethercom.ec_if; 3837 3838 /* Cancel pending I/O and flush buffers. */ 3839 bge_stop(sc); 3840 bge_reset(sc); 3841 bge_chipinit(sc); 3842 3843 /* 3844 * Init the various state machines, ring 3845 * control blocks and firmware. 3846 */ 3847 error = bge_blockinit(sc); 3848 if (error != 0) { 3849 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3850 error); 3851 splx(s); 3852 return error; 3853 } 3854 3855 ifp = &sc->ethercom.ec_if; 3856 3857 /* Specify MTU. */ 3858 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3859 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3860 3861 /* Load our MAC address. */ 3862 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3863 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3864 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3865 3866 /* Enable or disable promiscuous mode as needed. */ 3867 if (ifp->if_flags & IFF_PROMISC) { 3868 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3869 } else { 3870 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3871 } 3872 3873 /* Program multicast filter. */ 3874 bge_setmulti(sc); 3875 3876 /* Init RX ring. */ 3877 bge_init_rx_ring_std(sc); 3878 3879 /* Init jumbo RX ring. */ 3880 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3881 bge_init_rx_ring_jumbo(sc); 3882 3883 /* Init our RX return ring index */ 3884 sc->bge_rx_saved_considx = 0; 3885 3886 /* Init TX ring. */ 3887 bge_init_tx_ring(sc); 3888 3889 /* Turn on transmitter */ 3890 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3891 3892 /* Turn on receiver */ 3893 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3894 3895 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3896 3897 /* Tell firmware we're alive. */ 3898 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3899 3900 /* Enable host interrupts. */ 3901 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3902 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3903 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3904 3905 bge_ifmedia_upd(ifp); 3906 3907 ifp->if_flags |= IFF_RUNNING; 3908 ifp->if_flags &= ~IFF_OACTIVE; 3909 3910 splx(s); 3911 3912 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3913 3914 return 0; 3915 } 3916 3917 /* 3918 * Set media options. 3919 */ 3920 int 3921 bge_ifmedia_upd(ifp) 3922 struct ifnet *ifp; 3923 { 3924 struct bge_softc *sc = ifp->if_softc; 3925 struct mii_data *mii = &sc->bge_mii; 3926 struct ifmedia *ifm = &sc->bge_ifmedia; 3927 3928 /* If this is a 1000baseX NIC, enable the TBI port. */ 3929 if (sc->bge_tbi) { 3930 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3931 return(EINVAL); 3932 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3933 case IFM_AUTO: 3934 break; 3935 case IFM_1000_SX: 3936 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3937 BGE_CLRBIT(sc, BGE_MAC_MODE, 3938 BGE_MACMODE_HALF_DUPLEX); 3939 } else { 3940 BGE_SETBIT(sc, BGE_MAC_MODE, 3941 BGE_MACMODE_HALF_DUPLEX); 3942 } 3943 break; 3944 default: 3945 return(EINVAL); 3946 } 3947 /* XXX 802.3x flow control for 1000BASE-SX */ 3948 return(0); 3949 } 3950 3951 sc->bge_link = 0; 3952 mii_mediachg(mii); 3953 3954 return(0); 3955 } 3956 3957 /* 3958 * Report current media status. 3959 */ 3960 void 3961 bge_ifmedia_sts(ifp, ifmr) 3962 struct ifnet *ifp; 3963 struct ifmediareq *ifmr; 3964 { 3965 struct bge_softc *sc = ifp->if_softc; 3966 struct mii_data *mii = &sc->bge_mii; 3967 3968 if (sc->bge_tbi) { 3969 ifmr->ifm_status = IFM_AVALID; 3970 ifmr->ifm_active = IFM_ETHER; 3971 if (CSR_READ_4(sc, BGE_MAC_STS) & 3972 BGE_MACSTAT_TBI_PCS_SYNCHED) 3973 ifmr->ifm_status |= IFM_ACTIVE; 3974 ifmr->ifm_active |= IFM_1000_SX; 3975 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3976 ifmr->ifm_active |= IFM_HDX; 3977 else 3978 ifmr->ifm_active |= IFM_FDX; 3979 return; 3980 } 3981 3982 mii_pollstat(mii); 3983 ifmr->ifm_status = mii->mii_media_status; 3984 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 3985 sc->bge_flowflags; 3986 } 3987 3988 int 3989 bge_ioctl(ifp, command, data) 3990 struct ifnet *ifp; 3991 u_long command; 3992 caddr_t data; 3993 { 3994 struct bge_softc *sc = ifp->if_softc; 3995 struct ifreq *ifr = (struct ifreq *) data; 3996 int s, error = 0; 3997 struct mii_data *mii; 3998 3999 s = splnet(); 4000 4001 switch(command) { 4002 case SIOCSIFFLAGS: 4003 if (ifp->if_flags & IFF_UP) { 4004 /* 4005 * If only the state of the PROMISC flag changed, 4006 * then just use the 'set promisc mode' command 4007 * instead of reinitializing the entire NIC. Doing 4008 * a full re-init means reloading the firmware and 4009 * waiting for it to start up, which may take a 4010 * second or two. 4011 */ 4012 if (ifp->if_flags & IFF_RUNNING && 4013 ifp->if_flags & IFF_PROMISC && 4014 !(sc->bge_if_flags & IFF_PROMISC)) { 4015 BGE_SETBIT(sc, BGE_RX_MODE, 4016 BGE_RXMODE_RX_PROMISC); 4017 } else if (ifp->if_flags & IFF_RUNNING && 4018 !(ifp->if_flags & IFF_PROMISC) && 4019 sc->bge_if_flags & IFF_PROMISC) { 4020 BGE_CLRBIT(sc, BGE_RX_MODE, 4021 BGE_RXMODE_RX_PROMISC); 4022 } else 4023 bge_init(ifp); 4024 } else { 4025 if (ifp->if_flags & IFF_RUNNING) { 4026 bge_stop(sc); 4027 } 4028 } 4029 sc->bge_if_flags = ifp->if_flags; 4030 error = 0; 4031 break; 4032 case SIOCSIFMEDIA: 4033 /* XXX Flow control is not supported for 1000BASE-SX */ 4034 if (sc->bge_tbi) { 4035 ifr->ifr_media &= ~IFM_ETH_FMASK; 4036 sc->bge_flowflags = 0; 4037 } 4038 4039 /* Flow control requires full-duplex mode. */ 4040 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4041 (ifr->ifr_media & IFM_FDX) == 0) { 4042 ifr->ifr_media &= ~IFM_ETH_FMASK; 4043 } 4044 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4045 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4046 /* We an do both TXPAUSE and RXPAUSE. */ 4047 ifr->ifr_media |= 4048 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4049 } 4050 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4051 } 4052 /* FALLTHROUGH */ 4053 case SIOCGIFMEDIA: 4054 if (sc->bge_tbi) { 4055 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4056 command); 4057 } else { 4058 mii = &sc->bge_mii; 4059 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4060 command); 4061 } 4062 break; 4063 default: 4064 error = ether_ioctl(ifp, command, data); 4065 if (error == ENETRESET) { 4066 if (ifp->if_flags & IFF_RUNNING) 4067 bge_setmulti(sc); 4068 error = 0; 4069 } 4070 break; 4071 } 4072 4073 splx(s); 4074 4075 return(error); 4076 } 4077 4078 void 4079 bge_watchdog(ifp) 4080 struct ifnet *ifp; 4081 { 4082 struct bge_softc *sc; 4083 4084 sc = ifp->if_softc; 4085 4086 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 4087 4088 ifp->if_flags &= ~IFF_RUNNING; 4089 bge_init(ifp); 4090 4091 ifp->if_oerrors++; 4092 } 4093 4094 static void 4095 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4096 { 4097 int i; 4098 4099 BGE_CLRBIT(sc, reg, bit); 4100 4101 for (i = 0; i < BGE_TIMEOUT; i++) { 4102 if ((CSR_READ_4(sc, reg) & bit) == 0) 4103 return; 4104 delay(100); 4105 if (sc->bge_pcie) 4106 DELAY(1000); 4107 } 4108 4109 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 4110 sc->bge_dev.dv_xname, (u_long) reg, bit); 4111 } 4112 4113 /* 4114 * Stop the adapter and free any mbufs allocated to the 4115 * RX and TX lists. 4116 */ 4117 void 4118 bge_stop(sc) 4119 struct bge_softc *sc; 4120 { 4121 struct ifnet *ifp = &sc->ethercom.ec_if; 4122 4123 callout_stop(&sc->bge_timeout); 4124 4125 /* 4126 * Disable all of the receiver blocks 4127 */ 4128 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4129 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4130 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4131 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4132 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4133 } 4134 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4135 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4136 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4137 4138 /* 4139 * Disable all of the transmit blocks 4140 */ 4141 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4142 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4143 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4144 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4145 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4146 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4147 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4148 } 4149 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4150 4151 /* 4152 * Shut down all of the memory managers and related 4153 * state machines. 4154 */ 4155 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4156 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4157 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4158 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4159 } 4160 4161 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4162 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4163 4164 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 4165 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4166 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4167 } 4168 4169 /* Disable host interrupts. */ 4170 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4171 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 4172 4173 /* 4174 * Tell firmware we're shutting down. 4175 */ 4176 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4177 4178 /* Free the RX lists. */ 4179 bge_free_rx_ring_std(sc); 4180 4181 /* Free jumbo RX list. */ 4182 bge_free_rx_ring_jumbo(sc); 4183 4184 /* Free TX buffers. */ 4185 bge_free_tx_ring(sc); 4186 4187 /* 4188 * Isolate/power down the PHY. 4189 */ 4190 if (!sc->bge_tbi) 4191 mii_down(&sc->bge_mii); 4192 4193 sc->bge_link = 0; 4194 4195 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4196 4197 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4198 } 4199 4200 /* 4201 * Stop all chip I/O so that the kernel's probe routines don't 4202 * get confused by errant DMAs when rebooting. 4203 */ 4204 void 4205 bge_shutdown(xsc) 4206 void *xsc; 4207 { 4208 struct bge_softc *sc = (struct bge_softc *)xsc; 4209 4210 bge_stop(sc); 4211 bge_reset(sc); 4212 } 4213 4214 4215 static int 4216 sysctl_bge_verify(SYSCTLFN_ARGS) 4217 { 4218 int error, t; 4219 struct sysctlnode node; 4220 4221 node = *rnode; 4222 t = *(int*)rnode->sysctl_data; 4223 node.sysctl_data = &t; 4224 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4225 if (error || newp == NULL) 4226 return (error); 4227 4228 #if 0 4229 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4230 node.sysctl_num, rnode->sysctl_num)); 4231 #endif 4232 4233 if (node.sysctl_num == bge_rxthresh_nodenum) { 4234 if (t < 0 || t >= NBGE_RX_THRESH) 4235 return (EINVAL); 4236 bge_update_all_threshes(t); 4237 } else 4238 return (EINVAL); 4239 4240 *(int*)rnode->sysctl_data = t; 4241 4242 return (0); 4243 } 4244 4245 /* 4246 * Set up sysctl(3) MIB, hw.bge.*. 4247 * 4248 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4249 */ 4250 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4251 { 4252 int rc, bge_root_num; 4253 const struct sysctlnode *node; 4254 4255 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4256 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4257 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4258 goto err; 4259 } 4260 4261 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4262 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4263 SYSCTL_DESCR("BGE interface controls"), 4264 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4265 goto err; 4266 } 4267 4268 bge_root_num = node->sysctl_num; 4269 4270 /* BGE Rx interrupt mitigation level */ 4271 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4272 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4273 CTLTYPE_INT, "rx_lvl", 4274 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4275 sysctl_bge_verify, 0, 4276 &bge_rx_thresh_lvl, 4277 0, CTL_HW, bge_root_num, CTL_CREATE, 4278 CTL_EOL)) != 0) { 4279 goto err; 4280 } 4281 4282 bge_rxthresh_nodenum = node->sysctl_num; 4283 4284 return; 4285 4286 err: 4287 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4288 } 4289 4290 void 4291 bge_powerhook(int why, void *hdl) 4292 { 4293 struct bge_softc *sc = (struct bge_softc *)hdl; 4294 struct ifnet *ifp = &sc->ethercom.ec_if; 4295 struct pci_attach_args *pa = &(sc->bge_pa); 4296 pci_chipset_tag_t pc = pa->pa_pc; 4297 pcitag_t tag = pa->pa_tag; 4298 4299 switch (why) { 4300 case PWR_SOFTSUSPEND: 4301 case PWR_SOFTSTANDBY: 4302 bge_shutdown(sc); 4303 break; 4304 case PWR_SOFTRESUME: 4305 if (ifp->if_flags & IFF_UP) { 4306 ifp->if_flags &= ~IFF_RUNNING; 4307 bge_init(ifp); 4308 } 4309 break; 4310 case PWR_SUSPEND: 4311 case PWR_STANDBY: 4312 pci_conf_capture(pc, tag, &sc->bge_pciconf); 4313 break; 4314 case PWR_RESUME: 4315 pci_conf_restore(pc, tag, &sc->bge_pciconf); 4316 break; 4317 } 4318 4319 return; 4320 } 4321
Indexes created Tue Sep 23 14:10:03 GMT 2025