if_bgereg.h revision 1.21
1 /* $NetBSD: if_bgereg.h,v 1.21 2004/05/15 22:19:27 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79 #define BGE_UNMAPPED 0x00001000 80 #define BGE_UNMAPPED_END 0x00001FFF 81 #define BGE_DMA_DESCRIPTORS 0x00002000 82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83 #define BGE_SEND_RING_1_TO_4 0x00004000 84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86 /* Mappings for internal memory configuration */ 87 #define BGE_STD_RX_RINGS 0x00006000 88 #define BGE_STD_RX_RINGS_END 0x00006FFF 89 #define BGE_JUMBO_RX_RINGS 0x00007000 90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91 #define BGE_BUFFPOOL_1 0x00008000 92 #define BGE_BUFFPOOL_1_END 0x0000FFFF 93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_2_END 0x00017FFF 95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96 #define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98 /* Mappings for external SSRAM configurations */ 99 #define BGE_SEND_RING_5_TO_6 0x00006000 100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101 #define BGE_SEND_RING_7_TO_8 0x00007000 102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103 #define BGE_SEND_RING_9_TO_16 0x00008000 104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105 #define BGE_EXT_STD_RX_RINGS 0x0000C000 106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109 #define BGE_MINI_RX_RINGS 0x0000E000 110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION1_END 0x00017FFF 113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114 #define BGE_AVAIL_REGION2_END 0x0001FFFF 115 #define BGE_EXT_SSRAM 0x00020000 116 #define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119 /* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129 /* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132 #define BGE_PCI_VID 0x00 133 #define BGE_PCI_DID 0x02 134 #define BGE_PCI_CMD 0x04 135 #define BGE_PCI_STS 0x06 136 #define BGE_PCI_REV 0x08 137 #define BGE_PCI_CLASS 0x09 138 #define BGE_PCI_CACHESZ 0x0C 139 #define BGE_PCI_LATTIMER 0x0D 140 #define BGE_PCI_HDRTYPE 0x0E 141 #define BGE_PCI_BIST 0x0F 142 #define BGE_PCI_BAR0 0x10 143 #define BGE_PCI_BAR1 0x14 144 #define BGE_PCI_SUBSYS 0x2C 145 #define BGE_PCI_SUBVID 0x2E 146 #define BGE_PCI_ROMBASE 0x30 147 #define BGE_PCI_CAPPTR 0x34 148 #define BGE_PCI_INTLINE 0x3C 149 #define BGE_PCI_INTPIN 0x3D 150 #define BGE_PCI_MINGNT 0x3E 151 #define BGE_PCI_MAXLAT 0x3F 152 #define BGE_PCI_PCIXCAP 0x40 153 #define BGE_PCI_NEXTPTR_PM 0x41 154 #define BGE_PCI_PCIX_CMD 0x42 155 #define BGE_PCI_PCIX_STS 0x44 156 #define BGE_PCI_PWRMGMT_CAPID 0x48 157 #define BGE_PCI_NEXTPTR_VPD 0x49 158 #define BGE_PCI_PWRMGMT_CAPS 0x4A 159 #define BGE_PCI_PWRMGMT_CMD 0x4C 160 #define BGE_PCI_PWRMGMT_STS 0x4D 161 #define BGE_PCI_PWRMGMT_DATA 0x4F 162 #define BGE_PCI_VPD_CAPID 0x50 163 #define BGE_PCI_NEXTPTR_MSI 0x51 164 #define BGE_PCI_VPD_ADDR 0x52 165 #define BGE_PCI_VPD_DATA 0x54 166 #define BGE_PCI_MSI_CAPID 0x58 167 #define BGE_PCI_NEXTPTR_NONE 0x59 168 #define BGE_PCI_MSI_CTL 0x5A 169 #define BGE_PCI_MSI_ADDR_HI 0x5C 170 #define BGE_PCI_MSI_ADDR_LO 0x60 171 #define BGE_PCI_MSI_DATA 0x64 172 173 /* 174 * PCI registers specific to the BCM570x family. 175 */ 176 #define BGE_PCI_MISC_CTL 0x68 177 #define BGE_PCI_DMA_RW_CTL 0x6C 178 #define BGE_PCI_PCISTATE 0x70 179 #define BGE_PCI_CLKCTL 0x74 180 #define BGE_PCI_REG_BASEADDR 0x78 181 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 182 #define BGE_PCI_REG_DATA 0x80 183 #define BGE_PCI_MEMWIN_DATA 0x84 184 #define BGE_PCI_MODECTL 0x88 185 #define BGE_PCI_MISC_CFG 0x8C 186 #define BGE_PCI_MISC_LOCALCTL 0x90 187 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 188 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 189 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 190 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 191 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 192 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 193 #define BGE_PCI_ISR_MBX_HI 0xB0 194 #define BGE_PCI_ISR_MBX_LO 0xB4 195 196 /* PCI Misc. Host control register */ 197 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 198 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 199 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 200 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 201 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 202 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 203 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 204 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 205 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 206 207 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 208 #if BYTE_ORDER == LITTLE_ENDIAN 209 #define BGE_DMA_SWAP_OPTIONS \ 210 BGE_MODECTL_WORDSWAP_NONFRAME| \ 211 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 212 #else 213 #define BGE_DMA_SWAP_OPTIONS \ 214 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 215 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 216 #endif 217 218 #define BGE_INIT \ 219 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 220 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 221 222 #define BGE_CHIPID_TIGON_I 0x40000000 223 #define BGE_CHIPID_TIGON_II 0x60000000 224 #define BGE_CHIPID_BCM5700_A0 0x70000000 225 #define BGE_CHIPID_BCM5700_A1 0x70010000 226 #define BGE_CHIPID_BCM5700_B0 0x71000000 227 #define BGE_CHIPID_BCM5700_B1 0x71020000 228 #define BGE_CHIPID_BCM5700_B2 0x71030000 229 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 230 #define BGE_CHIPID_BCM5700_C0 0x72000000 231 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 232 #define BGE_CHIPID_BCM5701_B0 0x01000000 233 #define BGE_CHIPID_BCM5701_B2 0x01020000 234 #define BGE_CHIPID_BCM5701_B5 0x01050000 235 #define BGE_CHIPID_BCM5703_A0 0x10000000 236 #define BGE_CHIPID_BCM5703_A1 0x10010000 237 #define BGE_CHIPID_BCM5703_A2 0x10020000 238 #define BGE_CHIPID_BCM5703_A3 0x11000000 239 #define BGE_CHIPID_BCM5704_A0 0x20000000 240 #define BGE_CHIPID_BCM5704_A1 0x20010000 241 #define BGE_CHIPID_BCM5704_A2 0x20020000 242 #define BGE_CHIPID_BCM5704_A3 0x20030000 243 #define BGE_CHIPID_BCM5705_A0 0x30000000 244 #define BGE_CHIPID_BCM5705_A1 0x30010000 245 #define BGE_CHIPID_BCM5705_A2 0x30020000 246 #define BGE_CHIPID_BCM5705_A3 0x30030000 247 248 /* shorthand one */ 249 #define BGE_ASICREV(x) ((x) >> 28) 250 #define BGE_ASICREV_BCM5700 0x07 251 #define BGE_ASICREV_BCM5701 0x00 252 #define BGE_ASICREV_BCM5703 0x01 253 #define BGE_ASICREV_BCM5704 0x02 254 #define BGE_ASICREV_BCM5705 0x03 255 256 /* chip revisions */ 257 #define BGE_CHIPREV(x) ((x) >> 24) 258 #define BGE_CHIPREV_5700_AX 0x70 259 #define BGE_CHIPREV_5700_BX 0x71 260 #define BGE_CHIPREV_5700_CX 0x72 261 #define BGE_CHIPREV_5701_AX 0x00 262 263 /* PCI DMA Read/Write Control register */ 264 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 265 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 266 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 267 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 268 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 269 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 270 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 271 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 272 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 273 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 274 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 275 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 276 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 277 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 278 279 280 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 281 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 282 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 283 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 284 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 285 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 286 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 287 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 288 289 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 290 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 291 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 292 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 293 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 294 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 295 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 296 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 297 298 /* 299 * PCI state register -- note, this register is read only 300 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 301 * register is set. 302 */ 303 #define BGE_PCISTATE_FORCE_RESET 0x00000001 304 #define BGE_PCISTATE_INTR_STATE 0x00000002 305 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 306 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 307 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 308 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 309 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 310 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 311 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 312 313 /* 314 * The following bits in PCI state register are reserved. 315 * If we check that the register values reverts on reset, 316 * do not check these bits. On some 5704C (rev A3) and some 317 * Altima chips, these bits do not revert until much later 318 * in the bge driver's bge_reset() chip-reset state machine. 319 */ 320 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 321 322 /* 323 * PCI Clock Control register -- note, this register is read only 324 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 325 * register is set. 326 */ 327 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 328 #define BGE_PCICLOCKCTL_M66EN 0x00000080 329 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 330 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 331 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 332 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 333 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 334 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 335 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 336 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 337 338 339 #ifndef PCIM_CMD_MWIEN 340 #define PCIM_CMD_MWIEN 0x0010 341 #endif 342 343 /* 344 * High priority mailbox registers 345 * Each mailbox is 64-bits wide, though we only use the 346 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 347 * first. The NIC will load the mailbox after the lower 32 bit word 348 * has been updated. 349 */ 350 #define BGE_MBX_IRQ0_HI 0x0200 351 #define BGE_MBX_IRQ0_LO 0x0204 352 #define BGE_MBX_IRQ1_HI 0x0208 353 #define BGE_MBX_IRQ1_LO 0x020C 354 #define BGE_MBX_IRQ2_HI 0x0210 355 #define BGE_MBX_IRQ2_LO 0x0214 356 #define BGE_MBX_IRQ3_HI 0x0218 357 #define BGE_MBX_IRQ3_LO 0x021C 358 #define BGE_MBX_GEN0_HI 0x0220 359 #define BGE_MBX_GEN0_LO 0x0224 360 #define BGE_MBX_GEN1_HI 0x0228 361 #define BGE_MBX_GEN1_LO 0x022C 362 #define BGE_MBX_GEN2_HI 0x0230 363 #define BGE_MBX_GEN2_LO 0x0234 364 #define BGE_MBX_GEN3_HI 0x0228 365 #define BGE_MBX_GEN3_LO 0x022C 366 #define BGE_MBX_GEN4_HI 0x0240 367 #define BGE_MBX_GEN4_LO 0x0244 368 #define BGE_MBX_GEN5_HI 0x0248 369 #define BGE_MBX_GEN5_LO 0x024C 370 #define BGE_MBX_GEN6_HI 0x0250 371 #define BGE_MBX_GEN6_LO 0x0254 372 #define BGE_MBX_GEN7_HI 0x0258 373 #define BGE_MBX_GEN7_LO 0x025C 374 #define BGE_MBX_RELOAD_STATS_HI 0x0260 375 #define BGE_MBX_RELOAD_STATS_LO 0x0264 376 #define BGE_MBX_RX_STD_PROD_HI 0x0268 377 #define BGE_MBX_RX_STD_PROD_LO 0x026C 378 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 379 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 380 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 381 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 382 #define BGE_MBX_RX_CONS0_HI 0x0280 383 #define BGE_MBX_RX_CONS0_LO 0x0284 384 #define BGE_MBX_RX_CONS1_HI 0x0288 385 #define BGE_MBX_RX_CONS1_LO 0x028C 386 #define BGE_MBX_RX_CONS2_HI 0x0290 387 #define BGE_MBX_RX_CONS2_LO 0x0294 388 #define BGE_MBX_RX_CONS3_HI 0x0298 389 #define BGE_MBX_RX_CONS3_LO 0x029C 390 #define BGE_MBX_RX_CONS4_HI 0x02A0 391 #define BGE_MBX_RX_CONS4_LO 0x02A4 392 #define BGE_MBX_RX_CONS5_HI 0x02A8 393 #define BGE_MBX_RX_CONS5_LO 0x02AC 394 #define BGE_MBX_RX_CONS6_HI 0x02B0 395 #define BGE_MBX_RX_CONS6_LO 0x02B4 396 #define BGE_MBX_RX_CONS7_HI 0x02B8 397 #define BGE_MBX_RX_CONS7_LO 0x02BC 398 #define BGE_MBX_RX_CONS8_HI 0x02C0 399 #define BGE_MBX_RX_CONS8_LO 0x02C4 400 #define BGE_MBX_RX_CONS9_HI 0x02C8 401 #define BGE_MBX_RX_CONS9_LO 0x02CC 402 #define BGE_MBX_RX_CONS10_HI 0x02D0 403 #define BGE_MBX_RX_CONS10_LO 0x02D4 404 #define BGE_MBX_RX_CONS11_HI 0x02D8 405 #define BGE_MBX_RX_CONS11_LO 0x02DC 406 #define BGE_MBX_RX_CONS12_HI 0x02E0 407 #define BGE_MBX_RX_CONS12_LO 0x02E4 408 #define BGE_MBX_RX_CONS13_HI 0x02E8 409 #define BGE_MBX_RX_CONS13_LO 0x02EC 410 #define BGE_MBX_RX_CONS14_HI 0x02F0 411 #define BGE_MBX_RX_CONS14_LO 0x02F4 412 #define BGE_MBX_RX_CONS15_HI 0x02F8 413 #define BGE_MBX_RX_CONS15_LO 0x02FC 414 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 415 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 416 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 417 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 418 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 419 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 420 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 421 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 422 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 423 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 424 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 425 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 426 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 427 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 428 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 429 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 430 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 431 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 432 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 433 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 434 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 435 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 436 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 437 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 438 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 439 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 440 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 441 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 442 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 443 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 444 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 445 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 446 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 447 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 448 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 449 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 450 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 451 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 452 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 453 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 454 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 455 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 456 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 457 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 458 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 459 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 460 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 461 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 462 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 463 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 464 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 465 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 466 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 467 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 468 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 469 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 470 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 471 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 472 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 473 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 474 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 475 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 476 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 477 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 478 479 #define BGE_TX_RINGS_MAX 4 480 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 481 #define BGE_RX_RINGS_MAX 16 482 483 /* Ethernet MAC control registers */ 484 #define BGE_MAC_MODE 0x0400 485 #define BGE_MAC_STS 0x0404 486 #define BGE_MAC_EVT_ENB 0x0408 487 #define BGE_MAC_LED_CTL 0x040C 488 #define BGE_MAC_ADDR1_LO 0x0410 489 #define BGE_MAC_ADDR1_HI 0x0414 490 #define BGE_MAC_ADDR2_LO 0x0418 491 #define BGE_MAC_ADDR2_HI 0x041C 492 #define BGE_MAC_ADDR3_LO 0x0420 493 #define BGE_MAC_ADDR3_HI 0x0424 494 #define BGE_MAC_ADDR4_LO 0x0428 495 #define BGE_MAC_ADDR4_HI 0x042C 496 #define BGE_WOL_PATPTR 0x0430 497 #define BGE_WOL_PATCFG 0x0434 498 #define BGE_TX_RANDOM_BACKOFF 0x0438 499 #define BGE_RX_MTU 0x043C 500 #define BGE_GBIT_PCS_TEST 0x0440 501 #define BGE_TX_TBI_AUTONEG 0x0444 502 #define BGE_RX_TBI_AUTONEG 0x0448 503 #define BGE_MI_COMM 0x044C 504 #define BGE_MI_STS 0x0450 505 #define BGE_MI_MODE 0x0454 506 #define BGE_AUTOPOLL_STS 0x0458 507 #define BGE_TX_MODE 0x045C 508 #define BGE_TX_STS 0x0460 509 #define BGE_TX_LENGTHS 0x0464 510 #define BGE_RX_MODE 0x0468 511 #define BGE_RX_STS 0x046C 512 #define BGE_MAR0 0x0470 513 #define BGE_MAR1 0x0474 514 #define BGE_MAR2 0x0478 515 #define BGE_MAR3 0x047C 516 #define BGE_RX_BD_RULES_CTL0 0x0480 517 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 518 #define BGE_RX_BD_RULES_CTL1 0x0488 519 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 520 #define BGE_RX_BD_RULES_CTL2 0x0490 521 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 522 #define BGE_RX_BD_RULES_CTL3 0x0498 523 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 524 #define BGE_RX_BD_RULES_CTL4 0x04A0 525 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 526 #define BGE_RX_BD_RULES_CTL5 0x04A8 527 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 528 #define BGE_RX_BD_RULES_CTL6 0x04B0 529 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 530 #define BGE_RX_BD_RULES_CTL7 0x04B8 531 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 532 #define BGE_RX_BD_RULES_CTL8 0x04C0 533 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 534 #define BGE_RX_BD_RULES_CTL9 0x04C8 535 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 536 #define BGE_RX_BD_RULES_CTL10 0x04D0 537 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 538 #define BGE_RX_BD_RULES_CTL11 0x04D8 539 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 540 #define BGE_RX_BD_RULES_CTL12 0x04E0 541 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 542 #define BGE_RX_BD_RULES_CTL13 0x04E8 543 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 544 #define BGE_RX_BD_RULES_CTL14 0x04F0 545 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 546 #define BGE_RX_BD_RULES_CTL15 0x04F8 547 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 548 #define BGE_RX_RULES_CFG 0x0500 549 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 550 #define BGE_RX_STATS 0x0800 551 #define BGE_TX_STATS 0x0880 552 553 /* Ethernet MAC Mode register */ 554 #define BGE_MACMODE_RESET 0x00000001 555 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 556 #define BGE_MACMODE_PORTMODE 0x0000000C 557 #define BGE_MACMODE_LOOPBACK 0x00000010 558 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 559 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 560 #define BGE_MACMODE_MAX_DEFER 0x00000200 561 #define BGE_MACMODE_LINK_POLARITY 0x00000400 562 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 563 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 564 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 565 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 566 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 567 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 568 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 569 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 570 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 571 #define BGE_MACMODE_MIP_ENB 0x00100000 572 #define BGE_MACMODE_TXDMA_ENB 0x00200000 573 #define BGE_MACMODE_RXDMA_ENB 0x00400000 574 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 575 576 #define BGE_PORTMODE_NONE 0x00000000 577 #define BGE_PORTMODE_MII 0x00000004 578 #define BGE_PORTMODE_GMII 0x00000008 579 #define BGE_PORTMODE_TBI 0x0000000C 580 581 /* MAC Status register */ 582 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 583 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 584 #define BGE_MACSTAT_RX_CFG 0x00000004 585 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 586 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 587 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 588 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 589 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 590 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 591 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 592 #define BGE_MACSTAT_ODI_ERROR 0x02000000 593 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 594 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 595 596 /* MAC Event Enable Register */ 597 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 598 #define BGE_EVTENB_LINK_CHANGED 0x00001000 599 #define BGE_EVTENB_MI_COMPLETE 0x00400000 600 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 601 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 602 #define BGE_EVTENB_ODI_ERROR 0x02000000 603 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 604 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 605 606 /* LED Control Register */ 607 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 608 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 609 #define BGE_LEDCTL_100MBPS_LED 0x00000004 610 #define BGE_LEDCTL_10MBPS_LED 0x00000008 611 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 612 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 613 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 614 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 615 #define BGE_LEDCTL_100MBPS_STS 0x00000100 616 #define BGE_LEDCTL_10MBPS_STS 0x00000200 617 #define BGE_LEDCTL_TRADLED_STS 0x00000400 618 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 619 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 620 621 /* TX backoff seed register */ 622 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 623 624 /* Autopoll status register */ 625 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 626 627 /* Transmit MAC mode register */ 628 #define BGE_TXMODE_RESET 0x00000001 629 #define BGE_TXMODE_ENABLE 0x00000002 630 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 631 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 632 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 633 634 /* Transmit MAC status register */ 635 #define BGE_TXSTAT_RX_XOFFED 0x00000001 636 #define BGE_TXSTAT_SENT_XOFF 0x00000002 637 #define BGE_TXSTAT_SENT_XON 0x00000004 638 #define BGE_TXSTAT_LINK_UP 0x00000008 639 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 640 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 641 642 /* Transmit MAC lengths register */ 643 #define BGE_TXLEN_SLOTTIME 0x000000FF 644 #define BGE_TXLEN_IPG 0x00000F00 645 #define BGE_TXLEN_CRS 0x00003000 646 647 /* Receive MAC mode register */ 648 #define BGE_RXMODE_RESET 0x00000001 649 #define BGE_RXMODE_ENABLE 0x00000002 650 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 651 #define BGE_RXMODE_RX_GIANTS 0x00000020 652 #define BGE_RXMODE_RX_RUNTS 0x00000040 653 #define BGE_RXMODE_8022_LENCHECK 0x00000080 654 #define BGE_RXMODE_RX_PROMISC 0x00000100 655 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 656 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 657 658 /* Receive MAC status register */ 659 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 660 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 661 #define BGE_RXSTAT_RCVD_XON 0x00000004 662 663 /* Receive Rules Control register */ 664 #define BGE_RXRULECTL_OFFSET 0x000000FF 665 #define BGE_RXRULECTL_CLASS 0x00001F00 666 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 667 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 668 #define BGE_RXRULECTL_MAP 0x01000000 669 #define BGE_RXRULECTL_DISCARD 0x02000000 670 #define BGE_RXRULECTL_MASK 0x04000000 671 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 672 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 673 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 674 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 675 676 /* Receive Rules Mask register */ 677 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 678 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 679 680 /* MI communication register */ 681 #define BGE_MICOMM_DATA 0x0000FFFF 682 #define BGE_MICOMM_REG 0x001F0000 683 #define BGE_MICOMM_PHY 0x03E00000 684 #define BGE_MICOMM_CMD 0x0C000000 685 #define BGE_MICOMM_READFAIL 0x10000000 686 #define BGE_MICOMM_BUSY 0x20000000 687 688 #define BGE_MIREG(x) ((x & 0x1F) << 16) 689 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 690 #define BGE_MICMD_WRITE 0x04000000 691 #define BGE_MICMD_READ 0x08000000 692 693 /* MI status register */ 694 #define BGE_MISTS_LINK 0x00000001 695 #define BGE_MISTS_10MBPS 0x00000002 696 697 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 698 #define BGE_MIMODE_AUTOPOLL 0x00000010 699 #define BGE_MIMODE_CLKCNT 0x001F0000 700 701 702 /* 703 * Send data initiator control registers. 704 */ 705 #define BGE_SDI_MODE 0x0C00 706 #define BGE_SDI_STATUS 0x0C04 707 #define BGE_SDI_STATS_CTL 0x0C08 708 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 709 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 710 #define BGE_LOCSTATS_COS0 0x0C80 711 #define BGE_LOCSTATS_COS1 0x0C84 712 #define BGE_LOCSTATS_COS2 0x0C88 713 #define BGE_LOCSTATS_COS3 0x0C8C 714 #define BGE_LOCSTATS_COS4 0x0C90 715 #define BGE_LOCSTATS_COS5 0x0C84 716 #define BGE_LOCSTATS_COS6 0x0C98 717 #define BGE_LOCSTATS_COS7 0x0C9C 718 #define BGE_LOCSTATS_COS8 0x0CA0 719 #define BGE_LOCSTATS_COS9 0x0CA4 720 #define BGE_LOCSTATS_COS10 0x0CA8 721 #define BGE_LOCSTATS_COS11 0x0CAC 722 #define BGE_LOCSTATS_COS12 0x0CB0 723 #define BGE_LOCSTATS_COS13 0x0CB4 724 #define BGE_LOCSTATS_COS14 0x0CB8 725 #define BGE_LOCSTATS_COS15 0x0CBC 726 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 727 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 728 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 729 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 730 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 731 #define BGE_LOCSTATS_IRQS 0x0CD4 732 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 733 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 734 735 /* Send Data Initiator mode register */ 736 #define BGE_SDIMODE_RESET 0x00000001 737 #define BGE_SDIMODE_ENABLE 0x00000002 738 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 739 740 /* Send Data Initiator stats register */ 741 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 742 743 /* Send Data Initiator stats control register */ 744 #define BGE_SDISTATSCTL_ENABLE 0x00000001 745 #define BGE_SDISTATSCTL_FASTER 0x00000002 746 #define BGE_SDISTATSCTL_CLEAR 0x00000004 747 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 748 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 749 750 /* 751 * Send Data Completion Control registers 752 */ 753 #define BGE_SDC_MODE 0x1000 754 #define BGE_SDC_STATUS 0x1004 755 756 /* Send Data completion mode register */ 757 #define BGE_SDCMODE_RESET 0x00000001 758 #define BGE_SDCMODE_ENABLE 0x00000002 759 #define BGE_SDCMODE_ATTN 0x00000004 760 761 /* Send Data completion status register */ 762 #define BGE_SDCSTAT_ATTN 0x00000004 763 764 /* 765 * Send BD Ring Selector Control registers 766 */ 767 #define BGE_SRS_MODE 0x1400 768 #define BGE_SRS_STATUS 0x1404 769 #define BGE_SRS_HWDIAG 0x1408 770 #define BGE_SRS_LOC_NIC_CONS0 0x1440 771 #define BGE_SRS_LOC_NIC_CONS1 0x1444 772 #define BGE_SRS_LOC_NIC_CONS2 0x1448 773 #define BGE_SRS_LOC_NIC_CONS3 0x144C 774 #define BGE_SRS_LOC_NIC_CONS4 0x1450 775 #define BGE_SRS_LOC_NIC_CONS5 0x1454 776 #define BGE_SRS_LOC_NIC_CONS6 0x1458 777 #define BGE_SRS_LOC_NIC_CONS7 0x145C 778 #define BGE_SRS_LOC_NIC_CONS8 0x1460 779 #define BGE_SRS_LOC_NIC_CONS9 0x1464 780 #define BGE_SRS_LOC_NIC_CONS10 0x1468 781 #define BGE_SRS_LOC_NIC_CONS11 0x146C 782 #define BGE_SRS_LOC_NIC_CONS12 0x1470 783 #define BGE_SRS_LOC_NIC_CONS13 0x1474 784 #define BGE_SRS_LOC_NIC_CONS14 0x1478 785 #define BGE_SRS_LOC_NIC_CONS15 0x147C 786 787 /* Send BD Ring Selector Mode register */ 788 #define BGE_SRSMODE_RESET 0x00000001 789 #define BGE_SRSMODE_ENABLE 0x00000002 790 #define BGE_SRSMODE_ATTN 0x00000004 791 792 /* Send BD Ring Selector Status register */ 793 #define BGE_SRSSTAT_ERROR 0x00000004 794 795 /* Send BD Ring Selector HW Diagnostics register */ 796 #define BGE_SRSHWDIAG_STATE 0x0000000F 797 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 798 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 799 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 800 801 /* 802 * Send BD Initiator Selector Control registers 803 */ 804 #define BGE_SBDI_MODE 0x1800 805 #define BGE_SBDI_STATUS 0x1804 806 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 807 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 808 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 809 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 810 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 811 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 812 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 813 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 814 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 815 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 816 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 817 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 818 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 819 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 820 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 821 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 822 823 /* Send BD Initiator Mode register */ 824 #define BGE_SBDIMODE_RESET 0x00000001 825 #define BGE_SBDIMODE_ENABLE 0x00000002 826 #define BGE_SBDIMODE_ATTN 0x00000004 827 828 /* Send BD Initiator Status register */ 829 #define BGE_SBDISTAT_ERROR 0x00000004 830 831 /* 832 * Send BD Completion Control registers 833 */ 834 #define BGE_SBDC_MODE 0x1C00 835 #define BGE_SBDC_STATUS 0x1C04 836 837 /* Send BD Completion Control Mode register */ 838 #define BGE_SBDCMODE_RESET 0x00000001 839 #define BGE_SBDCMODE_ENABLE 0x00000002 840 #define BGE_SBDCMODE_ATTN 0x00000004 841 842 /* Send BD Completion Control Status register */ 843 #define BGE_SBDCSTAT_ATTN 0x00000004 844 845 /* 846 * Receive List Placement Control registers 847 */ 848 #define BGE_RXLP_MODE 0x2000 849 #define BGE_RXLP_STATUS 0x2004 850 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 851 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 852 #define BGE_RXLP_CFG 0x2010 853 #define BGE_RXLP_STATS_CTL 0x2014 854 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 855 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 856 #define BGE_RXLP_HEAD0 0x2100 857 #define BGE_RXLP_TAIL0 0x2104 858 #define BGE_RXLP_COUNT0 0x2108 859 #define BGE_RXLP_HEAD1 0x2110 860 #define BGE_RXLP_TAIL1 0x2114 861 #define BGE_RXLP_COUNT1 0x2118 862 #define BGE_RXLP_HEAD2 0x2120 863 #define BGE_RXLP_TAIL2 0x2124 864 #define BGE_RXLP_COUNT2 0x2128 865 #define BGE_RXLP_HEAD3 0x2130 866 #define BGE_RXLP_TAIL3 0x2134 867 #define BGE_RXLP_COUNT3 0x2138 868 #define BGE_RXLP_HEAD4 0x2140 869 #define BGE_RXLP_TAIL4 0x2144 870 #define BGE_RXLP_COUNT4 0x2148 871 #define BGE_RXLP_HEAD5 0x2150 872 #define BGE_RXLP_TAIL5 0x2154 873 #define BGE_RXLP_COUNT5 0x2158 874 #define BGE_RXLP_HEAD6 0x2160 875 #define BGE_RXLP_TAIL6 0x2164 876 #define BGE_RXLP_COUNT6 0x2168 877 #define BGE_RXLP_HEAD7 0x2170 878 #define BGE_RXLP_TAIL7 0x2174 879 #define BGE_RXLP_COUNT7 0x2178 880 #define BGE_RXLP_HEAD8 0x2180 881 #define BGE_RXLP_TAIL8 0x2184 882 #define BGE_RXLP_COUNT8 0x2188 883 #define BGE_RXLP_HEAD9 0x2190 884 #define BGE_RXLP_TAIL9 0x2194 885 #define BGE_RXLP_COUNT9 0x2198 886 #define BGE_RXLP_HEAD10 0x21A0 887 #define BGE_RXLP_TAIL10 0x21A4 888 #define BGE_RXLP_COUNT10 0x21A8 889 #define BGE_RXLP_HEAD11 0x21B0 890 #define BGE_RXLP_TAIL11 0x21B4 891 #define BGE_RXLP_COUNT11 0x21B8 892 #define BGE_RXLP_HEAD12 0x21C0 893 #define BGE_RXLP_TAIL12 0x21C4 894 #define BGE_RXLP_COUNT12 0x21C8 895 #define BGE_RXLP_HEAD13 0x21D0 896 #define BGE_RXLP_TAIL13 0x21D4 897 #define BGE_RXLP_COUNT13 0x21D8 898 #define BGE_RXLP_HEAD14 0x21E0 899 #define BGE_RXLP_TAIL14 0x21E4 900 #define BGE_RXLP_COUNT14 0x21E8 901 #define BGE_RXLP_HEAD15 0x21F0 902 #define BGE_RXLP_TAIL15 0x21F4 903 #define BGE_RXLP_COUNT15 0x21F8 904 #define BGE_RXLP_LOCSTAT_COS0 0x2200 905 #define BGE_RXLP_LOCSTAT_COS1 0x2204 906 #define BGE_RXLP_LOCSTAT_COS2 0x2208 907 #define BGE_RXLP_LOCSTAT_COS3 0x220C 908 #define BGE_RXLP_LOCSTAT_COS4 0x2210 909 #define BGE_RXLP_LOCSTAT_COS5 0x2214 910 #define BGE_RXLP_LOCSTAT_COS6 0x2218 911 #define BGE_RXLP_LOCSTAT_COS7 0x221C 912 #define BGE_RXLP_LOCSTAT_COS8 0x2220 913 #define BGE_RXLP_LOCSTAT_COS9 0x2224 914 #define BGE_RXLP_LOCSTAT_COS10 0x2228 915 #define BGE_RXLP_LOCSTAT_COS11 0x222C 916 #define BGE_RXLP_LOCSTAT_COS12 0x2230 917 #define BGE_RXLP_LOCSTAT_COS13 0x2234 918 #define BGE_RXLP_LOCSTAT_COS14 0x2238 919 #define BGE_RXLP_LOCSTAT_COS15 0x223C 920 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 921 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 922 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 923 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 924 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 925 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 926 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 927 928 929 /* Receive List Placement mode register */ 930 #define BGE_RXLPMODE_RESET 0x00000001 931 #define BGE_RXLPMODE_ENABLE 0x00000002 932 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 933 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 934 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 935 936 /* Receive List Placement Status register */ 937 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 938 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 939 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 940 941 /* 942 * Receive Data and Receive BD Initiator Control Registers 943 */ 944 #define BGE_RDBDI_MODE 0x2400 945 #define BGE_RDBDI_STATUS 0x2404 946 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 947 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 948 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 949 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 950 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 951 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 952 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 953 #define BGE_RX_STD_RCB_NICADDR 0x245C 954 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 955 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 956 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 957 #define BGE_RX_MINI_RCB_NICADDR 0x246C 958 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 959 #define BGE_RDBDI_STD_RX_CONS 0x2474 960 #define BGE_RDBDI_MINI_RX_CONS 0x2478 961 #define BGE_RDBDI_RETURN_PROD0 0x2480 962 #define BGE_RDBDI_RETURN_PROD1 0x2484 963 #define BGE_RDBDI_RETURN_PROD2 0x2488 964 #define BGE_RDBDI_RETURN_PROD3 0x248C 965 #define BGE_RDBDI_RETURN_PROD4 0x2490 966 #define BGE_RDBDI_RETURN_PROD5 0x2494 967 #define BGE_RDBDI_RETURN_PROD6 0x2498 968 #define BGE_RDBDI_RETURN_PROD7 0x249C 969 #define BGE_RDBDI_RETURN_PROD8 0x24A0 970 #define BGE_RDBDI_RETURN_PROD9 0x24A4 971 #define BGE_RDBDI_RETURN_PROD10 0x24A8 972 #define BGE_RDBDI_RETURN_PROD11 0x24AC 973 #define BGE_RDBDI_RETURN_PROD12 0x24B0 974 #define BGE_RDBDI_RETURN_PROD13 0x24B4 975 #define BGE_RDBDI_RETURN_PROD14 0x24B8 976 #define BGE_RDBDI_RETURN_PROD15 0x24BC 977 #define BGE_RDBDI_HWDIAG 0x24C0 978 979 980 /* Receive Data and Receive BD Initiator Mode register */ 981 #define BGE_RDBDIMODE_RESET 0x00000001 982 #define BGE_RDBDIMODE_ENABLE 0x00000002 983 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 984 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 985 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 986 987 /* Receive Data and Receive BD Initiator Status register */ 988 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 989 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 990 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 991 992 993 /* 994 * Receive Data Completion Control registers 995 */ 996 #define BGE_RDC_MODE 0x2800 997 998 /* Receive Data Completion Mode register */ 999 #define BGE_RDCMODE_RESET 0x00000001 1000 #define BGE_RDCMODE_ENABLE 0x00000002 1001 #define BGE_RDCMODE_ATTN 0x00000004 1002 1003 /* 1004 * Receive BD Initiator Control registers 1005 */ 1006 #define BGE_RBDI_MODE 0x2C00 1007 #define BGE_RBDI_STATUS 0x2C04 1008 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1009 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1010 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1011 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1012 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1013 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1014 1015 /* Receive BD Initiator Mode register */ 1016 #define BGE_RBDIMODE_RESET 0x00000001 1017 #define BGE_RBDIMODE_ENABLE 0x00000002 1018 #define BGE_RBDIMODE_ATTN 0x00000004 1019 1020 /* Receive BD Initiator Status register */ 1021 #define BGE_RBDISTAT_ATTN 0x00000004 1022 1023 /* 1024 * Receive BD Completion Control registers 1025 */ 1026 #define BGE_RBDC_MODE 0x3000 1027 #define BGE_RBDC_STATUS 0x3004 1028 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1029 #define BGE_RBDC_STD_BD_PROD 0x300C 1030 #define BGE_RBDC_MINI_BD_PROD 0x3010 1031 1032 /* Receive BD completion mode register */ 1033 #define BGE_RBDCMODE_RESET 0x00000001 1034 #define BGE_RBDCMODE_ENABLE 0x00000002 1035 #define BGE_RBDCMODE_ATTN 0x00000004 1036 1037 /* Receive BD completion status register */ 1038 #define BGE_RBDCSTAT_ERROR 0x00000004 1039 1040 /* 1041 * Receive List Selector Control registers 1042 */ 1043 #define BGE_RXLS_MODE 0x3400 1044 #define BGE_RXLS_STATUS 0x3404 1045 1046 /* Receive List Selector Mode register */ 1047 #define BGE_RXLSMODE_RESET 0x00000001 1048 #define BGE_RXLSMODE_ENABLE 0x00000002 1049 #define BGE_RXLSMODE_ATTN 0x00000004 1050 1051 /* Receive List Selector Status register */ 1052 #define BGE_RXLSSTAT_ERROR 0x00000004 1053 1054 /* 1055 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1056 */ 1057 #define BGE_MBCF_MODE 0x3800 1058 #define BGE_MBCF_STATUS 0x3804 1059 1060 /* Mbuf Cluster Free mode register */ 1061 #define BGE_MBCFMODE_RESET 0x00000001 1062 #define BGE_MBCFMODE_ENABLE 0x00000002 1063 #define BGE_MBCFMODE_ATTN 0x00000004 1064 1065 /* Mbuf Cluster Free status register */ 1066 #define BGE_MBCFSTAT_ERROR 0x00000004 1067 1068 /* 1069 * Host Coalescing Control registers 1070 */ 1071 #define BGE_HCC_MODE 0x3C00 1072 #define BGE_HCC_STATUS 0x3C04 1073 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1074 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1075 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1076 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1077 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1078 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1079 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1080 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1081 #define BGE_HCC_STATS_TICKS 0x3C28 1082 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1083 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1084 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1085 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1086 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1087 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1088 #define BGE_FLOW_ATTN 0x3C48 1089 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1090 #define BGE_HCC_STD_BD_CONS 0x3C54 1091 #define BGE_HCC_MINI_BD_CONS 0x3C58 1092 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1093 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1094 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1095 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1096 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1097 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1098 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1099 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1100 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1101 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1102 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1103 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1104 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1105 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1106 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1107 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1108 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1109 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1110 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1111 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1112 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1113 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1114 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1115 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1116 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1117 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1118 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1119 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1120 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1121 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1122 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1123 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1124 1125 1126 /* Host coalescing mode register */ 1127 #define BGE_HCCMODE_RESET 0x00000001 1128 #define BGE_HCCMODE_ENABLE 0x00000002 1129 #define BGE_HCCMODE_ATTN 0x00000004 1130 #define BGE_HCCMODE_COAL_NOW 0x00000008 1131 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1132 #define BGE_HCCMODE_64BYTE 0x00000080 1133 #define BGE_HCCMODE_32BYTE 0x00000100 1134 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1135 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1136 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1137 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1138 1139 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1140 1141 #define BGE_STATBLKSZ_FULL 0x00000000 1142 #define BGE_STATBLKSZ_64BYTE 0x00000080 1143 #define BGE_STATBLKSZ_32BYTE 0x00000100 1144 1145 /* Host coalescing status register */ 1146 #define BGE_HCCSTAT_ERROR 0x00000004 1147 1148 /* Flow attention register */ 1149 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1150 #define BGE_FLOWATTN_MEMARB 0x00000080 1151 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1152 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1153 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1154 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1155 #define BGE_FLOWATTN_RDBDI 0x00080000 1156 #define BGE_FLOWATTN_RXLS 0x00100000 1157 #define BGE_FLOWATTN_RXLP 0x00200000 1158 #define BGE_FLOWATTN_RBDC 0x00400000 1159 #define BGE_FLOWATTN_RBDI 0x00800000 1160 #define BGE_FLOWATTN_SDC 0x08000000 1161 #define BGE_FLOWATTN_SDI 0x10000000 1162 #define BGE_FLOWATTN_SRS 0x20000000 1163 #define BGE_FLOWATTN_SBDC 0x40000000 1164 #define BGE_FLOWATTN_SBDI 0x80000000 1165 1166 /* 1167 * Memory arbiter registers 1168 */ 1169 #define BGE_MARB_MODE 0x4000 1170 #define BGE_MARB_STATUS 0x4004 1171 #define BGE_MARB_TRAPADDR_HI 0x4008 1172 #define BGE_MARB_TRAPADDR_LO 0x400C 1173 1174 /* Memory arbiter mode register */ 1175 #define BGE_MARBMODE_RESET 0x00000001 1176 #define BGE_MARBMODE_ENABLE 0x00000002 1177 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1178 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1179 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1180 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1181 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1182 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1183 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1184 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1185 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1186 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1187 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1188 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1189 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1190 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1191 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1192 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1193 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1194 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1195 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1196 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1197 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1198 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1199 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1200 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1201 1202 /* Memory arbiter status register */ 1203 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1204 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1205 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1206 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1207 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1208 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1209 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1210 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1211 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1212 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1213 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1214 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1215 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1216 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1217 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1218 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1219 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1220 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1221 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1222 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1223 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1224 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1225 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1226 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1227 1228 /* 1229 * Buffer manager control registers 1230 */ 1231 #define BGE_BMAN_MODE 0x4400 1232 #define BGE_BMAN_STATUS 0x4404 1233 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1234 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1235 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1236 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1237 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1238 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1239 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1240 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1241 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1242 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1243 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1244 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1245 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1246 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1247 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1248 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1249 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1250 #define BGE_BMAN_HWDIAG_1 0x444C 1251 #define BGE_BMAN_HWDIAG_2 0x4450 1252 #define BGE_BMAN_HWDIAG_3 0x4454 1253 1254 /* Buffer manager mode register */ 1255 #define BGE_BMANMODE_RESET 0x00000001 1256 #define BGE_BMANMODE_ENABLE 0x00000002 1257 #define BGE_BMANMODE_ATTN 0x00000004 1258 #define BGE_BMANMODE_TESTMODE 0x00000008 1259 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1260 1261 /* Buffer manager status register */ 1262 #define BGE_BMANSTAT_ERRO 0x00000004 1263 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1264 1265 1266 /* 1267 * Read DMA Control registers 1268 */ 1269 #define BGE_RDMA_MODE 0x4800 1270 #define BGE_RDMA_STATUS 0x4804 1271 1272 /* Read DMA mode register */ 1273 #define BGE_RDMAMODE_RESET 0x00000001 1274 #define BGE_RDMAMODE_ENABLE 0x00000002 1275 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1276 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1277 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1278 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1279 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1280 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1281 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1282 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1283 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1284 1285 /* Read DMA status register */ 1286 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1287 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1288 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1289 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1290 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1291 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1292 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1293 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1294 1295 /* 1296 * Write DMA control registers 1297 */ 1298 #define BGE_WDMA_MODE 0x4C00 1299 #define BGE_WDMA_STATUS 0x4C04 1300 1301 /* Write DMA mode register */ 1302 #define BGE_WDMAMODE_RESET 0x00000001 1303 #define BGE_WDMAMODE_ENABLE 0x00000002 1304 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1305 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1306 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1307 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1308 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1309 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1310 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1311 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1312 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1313 1314 /* Write DMA status register */ 1315 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1316 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1317 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1318 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1319 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1320 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1321 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1322 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1323 1324 1325 /* 1326 * RX CPU registers 1327 */ 1328 #define BGE_RXCPU_MODE 0x5000 1329 #define BGE_RXCPU_STATUS 0x5004 1330 #define BGE_RXCPU_PC 0x501C 1331 1332 /* RX CPU mode register */ 1333 #define BGE_RXCPUMODE_RESET 0x00000001 1334 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1335 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1336 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1337 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1338 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1339 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1340 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1341 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1342 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1343 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1344 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1345 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1346 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1347 1348 /* RX CPU status register */ 1349 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1350 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1351 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1352 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1353 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1354 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1355 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1356 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1357 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1358 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1359 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1360 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1361 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1362 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1363 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1364 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1365 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1366 1367 1368 /* 1369 * TX CPU registers 1370 */ 1371 #define BGE_TXCPU_MODE 0x5400 1372 #define BGE_TXCPU_STATUS 0x5404 1373 #define BGE_TXCPU_PC 0x541C 1374 1375 /* TX CPU mode register */ 1376 #define BGE_TXCPUMODE_RESET 0x00000001 1377 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1378 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1379 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1380 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1381 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1382 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1383 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1384 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1385 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1386 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1387 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1388 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1389 1390 /* TX CPU status register */ 1391 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1392 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1393 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1394 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1395 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1396 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1397 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1398 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1399 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1400 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1401 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1402 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1403 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1404 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1405 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1406 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1407 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1408 1409 1410 /* 1411 * Low priority mailbox registers 1412 */ 1413 #define BGE_LPMBX_IRQ0_HI 0x5800 1414 #define BGE_LPMBX_IRQ0_LO 0x5804 1415 #define BGE_LPMBX_IRQ1_HI 0x5808 1416 #define BGE_LPMBX_IRQ1_LO 0x580C 1417 #define BGE_LPMBX_IRQ2_HI 0x5810 1418 #define BGE_LPMBX_IRQ2_LO 0x5814 1419 #define BGE_LPMBX_IRQ3_HI 0x5818 1420 #define BGE_LPMBX_IRQ3_LO 0x581C 1421 #define BGE_LPMBX_GEN0_HI 0x5820 1422 #define BGE_LPMBX_GEN0_LO 0x5824 1423 #define BGE_LPMBX_GEN1_HI 0x5828 1424 #define BGE_LPMBX_GEN1_LO 0x582C 1425 #define BGE_LPMBX_GEN2_HI 0x5830 1426 #define BGE_LPMBX_GEN2_LO 0x5834 1427 #define BGE_LPMBX_GEN3_HI 0x5828 1428 #define BGE_LPMBX_GEN3_LO 0x582C 1429 #define BGE_LPMBX_GEN4_HI 0x5840 1430 #define BGE_LPMBX_GEN4_LO 0x5844 1431 #define BGE_LPMBX_GEN5_HI 0x5848 1432 #define BGE_LPMBX_GEN5_LO 0x584C 1433 #define BGE_LPMBX_GEN6_HI 0x5850 1434 #define BGE_LPMBX_GEN6_LO 0x5854 1435 #define BGE_LPMBX_GEN7_HI 0x5858 1436 #define BGE_LPMBX_GEN7_LO 0x585C 1437 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1438 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1439 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1440 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1441 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1442 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1443 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1444 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1445 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1446 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1447 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1448 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1449 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1450 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1451 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1452 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1453 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1454 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1455 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1456 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1457 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1458 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1459 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1460 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1461 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1462 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1463 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1464 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1465 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1466 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1467 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1468 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1469 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1470 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1471 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1472 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1473 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1474 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1475 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1476 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1477 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1478 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1479 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1480 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1481 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1482 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1483 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1484 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1485 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1486 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1487 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1488 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1489 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1490 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1491 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1492 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1493 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1494 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1495 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1496 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1497 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1498 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1499 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1500 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1501 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1502 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1503 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1504 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1505 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1506 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1507 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1508 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1509 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1510 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1511 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1512 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1513 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1514 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1515 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1516 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1517 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1518 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1519 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1520 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1521 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1522 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1523 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1524 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1525 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1526 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1527 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1528 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1529 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1530 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1531 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1532 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1533 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1534 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1535 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1536 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1537 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1538 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1539 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1540 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1541 1542 /* 1543 * Flow throw Queue reset register 1544 */ 1545 #define BGE_FTQ_RESET 0x5C00 1546 1547 #define BGE_FTQRESET_DMAREAD 0x00000002 1548 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1549 #define BGE_FTQRESET_DMADONE 0x00000010 1550 #define BGE_FTQRESET_SBDC 0x00000020 1551 #define BGE_FTQRESET_SDI 0x00000040 1552 #define BGE_FTQRESET_WDMA 0x00000080 1553 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1554 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1555 #define BGE_FTQRESET_SDC 0x00000400 1556 #define BGE_FTQRESET_HCC 0x00000800 1557 #define BGE_FTQRESET_TXFIFO 0x00001000 1558 #define BGE_FTQRESET_MBC 0x00002000 1559 #define BGE_FTQRESET_RBDC 0x00004000 1560 #define BGE_FTQRESET_RXLP 0x00008000 1561 #define BGE_FTQRESET_RDBDI 0x00010000 1562 #define BGE_FTQRESET_RDC 0x00020000 1563 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1564 1565 /* 1566 * Message Signaled Interrupt registers 1567 */ 1568 #define BGE_MSI_MODE 0x6000 1569 #define BGE_MSI_STATUS 0x6004 1570 #define BGE_MSI_FIFOACCESS 0x6008 1571 1572 /* MSI mode register */ 1573 #define BGE_MSIMODE_RESET 0x00000001 1574 #define BGE_MSIMODE_ENABLE 0x00000002 1575 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1576 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1577 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1578 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1579 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1580 1581 /* MSI status register */ 1582 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1583 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1584 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1585 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1586 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1587 1588 1589 /* 1590 * DMA Completion registers 1591 */ 1592 #define BGE_DMAC_MODE 0x6400 1593 1594 /* DMA Completion mode register */ 1595 #define BGE_DMACMODE_RESET 0x00000001 1596 #define BGE_DMACMODE_ENABLE 0x00000002 1597 1598 1599 /* 1600 * General control registers. 1601 */ 1602 #define BGE_MODE_CTL 0x6800 1603 #define BGE_MISC_CFG 0x6804 1604 #define BGE_MISC_LOCAL_CTL 0x6808 1605 #define BGE_MISC_TIMER 0x680c 1606 #define BGE_EE_ADDR 0x6838 1607 #define BGE_EE_DATA 0x683C 1608 #define BGE_EE_CTL 0x6840 1609 #define BGE_MDI_CTL 0x6844 1610 #define BGE_EE_DELAY 0x6848 1611 1612 /* Mode control register */ 1613 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1614 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1615 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1616 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1617 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1618 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1619 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1620 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1621 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1622 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1623 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1624 #define BGE_MODECTL_STACKUP 0x00010000 1625 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1626 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1627 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1628 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1629 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1630 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1631 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1632 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1633 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1634 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1635 1636 /* Misc. config register */ 1637 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1638 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1639 1640 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1641 1642 /* Misc. Local Control */ 1643 #define BGE_MLC_INTR_STATE 0x00000001 1644 #define BGE_MLC_INTR_CLR 0x00000002 1645 #define BGE_MLC_INTR_SET 0x00000004 1646 #define BGE_MLC_INTR_ONATTN 0x00000008 1647 #define BGE_MLC_MISCIO_IN0 0x00000100 1648 #define BGE_MLC_MISCIO_IN1 0x00000200 1649 #define BGE_MLC_MISCIO_IN2 0x00000400 1650 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1651 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1652 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1653 #define BGE_MLC_MISCIO_OUT0 0x00004000 1654 #define BGE_MLC_MISCIO_OUT1 0x00008000 1655 #define BGE_MLC_MISCIO_OUT2 0x00010000 1656 #define BGE_MLC_EXTRAM_ENB 0x00020000 1657 #define BGE_MLC_SRAM_SIZE 0x001C0000 1658 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1659 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1660 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1661 #define BGE_MLC_AUTO_EEPROM 0x01000000 1662 1663 #define BGE_SSRAMSIZE_256KB 0x00000000 1664 #define BGE_SSRAMSIZE_512KB 0x00040000 1665 #define BGE_SSRAMSIZE_1MB 0x00080000 1666 #define BGE_SSRAMSIZE_2MB 0x000C0000 1667 #define BGE_SSRAMSIZE_4MB 0x00100000 1668 #define BGE_SSRAMSIZE_8MB 0x00140000 1669 #define BGE_SSRAMSIZE_16M 0x00180000 1670 1671 /* EEPROM address register */ 1672 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1673 #define BGE_EEADDR_HALFCLK 0x01FF0000 1674 #define BGE_EEADDR_START 0x02000000 1675 #define BGE_EEADDR_DEVID 0x1C000000 1676 #define BGE_EEADDR_RESET 0x20000000 1677 #define BGE_EEADDR_DONE 0x40000000 1678 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1679 1680 #define BGE_EEDEVID(x) ((x & 7) << 26) 1681 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1682 #define BGE_HALFCLK_384SCL 0x60 1683 #define BGE_EE_READCMD \ 1684 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1685 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1686 #define BGE_EE_WRCMD \ 1687 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1688 BGE_EEADDR_START|BGE_EEADDR_DONE) 1689 1690 /* EEPROM Control register */ 1691 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1692 #define BGE_EECTL_CLKOUT 0x00000002 1693 #define BGE_EECTL_CLKIN 0x00000004 1694 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1695 #define BGE_EECTL_DATAOUT 0x00000010 1696 #define BGE_EECTL_DATAIN 0x00000020 1697 1698 /* MDI (MII/GMII) access register */ 1699 #define BGE_MDI_DATA 0x00000001 1700 #define BGE_MDI_DIR 0x00000002 1701 #define BGE_MDI_SEL 0x00000004 1702 #define BGE_MDI_CLK 0x00000008 1703 1704 #define BGE_MEMWIN_START 0x00008000 1705 #define BGE_MEMWIN_END 0x0000FFFF 1706 1707 1708 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1709 do { \ 1710 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1711 (0xFFFF0000 & x)); \ 1712 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1713 } while(0) 1714 1715 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1716 do { \ 1717 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1718 (0xFFFF0000 & x)); \ 1719 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1720 } while(0) 1721 1722 /* 1723 * This magic number is used to prevent PXE restart when we 1724 * issue a software reset. We write this magic number to the 1725 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1726 * code from running. 1727 */ 1728 #define BGE_MAGIC_NUMBER 0x4B657654 1729 1730 #if BYTE_ORDER == LITTLE_ENDIAN 1731 typedef struct { 1732 u_int32_t bge_addr_hi; 1733 u_int32_t bge_addr_lo; 1734 } bge_hostaddr; 1735 #else 1736 typedef struct { 1737 u_int32_t bge_addr_hi; 1738 u_int32_t bge_addr_lo; 1739 } bge_hostaddr; 1740 #endif 1741 1742 #define BGE_HOSTADDR(x) (x).bge_addr_lo 1743 1744 static __inline void 1745 bge_set_hostaddr(volatile bge_hostaddr *x, bus_addr_t y) 1746 { 1747 x->bge_addr_lo = y & 0xffffffff; 1748 if (sizeof (bus_addr_t) == 8) 1749 x->bge_addr_hi = (u_int64_t)y >> 32; 1750 else 1751 x->bge_addr_hi = 0; 1752 } 1753 1754 /* Ring control block structure */ 1755 struct bge_rcb { 1756 bge_hostaddr bge_hostaddr; 1757 u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 1758 u_int32_t bge_nicaddr; 1759 }; 1760 1761 #if BYTE_ORDER == BIG_ENDIAN 1762 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((flags) << 16 | (maxlen)) 1763 #else 1764 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1765 #endif 1766 1767 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1768 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1769 rcb + offsetof(struct bge_rcb, offset), val) 1770 1771 1772 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1773 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1774 1775 struct bge_tx_bd { 1776 bge_hostaddr bge_addr; 1777 #if BYTE_ORDER == BIG_ENDIAN 1778 u_int16_t bge_len; 1779 u_int16_t bge_flags; 1780 u_int16_t bge_rsvd; 1781 u_int16_t bge_vlan_tag; 1782 #else 1783 u_int16_t bge_flags; 1784 u_int16_t bge_len; 1785 u_int16_t bge_vlan_tag; 1786 u_int16_t bge_rsvd; 1787 #endif 1788 }; 1789 1790 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1791 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1792 #define BGE_TXBDFLAG_END 0x0004 1793 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1794 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1795 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1796 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1797 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1798 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1799 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1800 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1801 #define BGE_TXBDFLAG_NO_CRC 0x8000 1802 1803 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1804 BGE_SEND_RING_1_TO_4 + \ 1805 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1806 1807 struct bge_rx_bd { 1808 bge_hostaddr bge_addr; 1809 #if BYTE_ORDER == BIG_ENDIAN 1810 u_int16_t bge_idx; 1811 u_int16_t bge_len; 1812 u_int16_t bge_type; 1813 u_int16_t bge_flags; 1814 u_int16_t bge_ip_csum; 1815 u_int16_t bge_tcp_udp_csum; 1816 u_int16_t bge_error_flag; 1817 u_int16_t bge_vlan_tag; 1818 #else 1819 u_int16_t bge_len; 1820 u_int16_t bge_idx; 1821 u_int16_t bge_flags; 1822 u_int16_t bge_type; 1823 u_int16_t bge_tcp_udp_csum; 1824 u_int16_t bge_ip_csum; 1825 u_int16_t bge_vlan_tag; 1826 u_int16_t bge_error_flag; 1827 #endif 1828 u_int32_t bge_rsvd; 1829 u_int32_t bge_opaque; 1830 }; 1831 1832 #define BGE_RXBDFLAG_END 0x0004 1833 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1834 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1835 #define BGE_RXBDFLAG_ERROR 0x0400 1836 #define BGE_RXBDFLAG_MINI_RING 0x0800 1837 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1838 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1839 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1840 1841 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1842 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1843 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1844 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1845 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1846 #define BGE_RXERRFLAG_RUNT 0x0020 1847 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1848 #define BGE_RXERRFLAG_GIANT 0x0080 1849 1850 struct bge_sts_idx { 1851 #if BYTE_ORDER == BIG_ENDIAN 1852 u_int16_t bge_tx_cons_idx; 1853 u_int16_t bge_rx_prod_idx; 1854 #else 1855 u_int16_t bge_rx_prod_idx; 1856 u_int16_t bge_tx_cons_idx; 1857 #endif 1858 }; 1859 1860 struct bge_status_block { 1861 u_int32_t bge_status; 1862 u_int32_t bge_rsvd0; 1863 #if BYTE_ORDER == BIG_ENDIAN 1864 u_int16_t bge_rx_std_cons_idx; 1865 u_int16_t bge_rx_jumbo_cons_idx; 1866 u_int16_t bge_rsvd1; 1867 u_int16_t bge_rx_mini_cons_idx; 1868 #else 1869 u_int16_t bge_rx_jumbo_cons_idx; 1870 u_int16_t bge_rx_std_cons_idx; 1871 u_int16_t bge_rx_mini_cons_idx; 1872 u_int16_t bge_rsvd1; 1873 #endif 1874 struct bge_sts_idx bge_idx[16]; 1875 }; 1876 1877 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1878 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1879 1880 #define BGE_STATFLAG_UPDATED 0x00000001 1881 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1882 #define BGE_STATFLAG_ERROR 0x00000004 1883 1884 1885 /* 1886 * Broadcom Vendor ID 1887 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1888 * even though they're now manufactured by Broadcom) 1889 */ 1890 #define BCOM_VENDORID 0x14E4 1891 #define BCOM_DEVICEID_BCM5700 0x1644 1892 #define BCOM_DEVICEID_BCM5701 0x1645 1893 1894 /* 1895 * Alteon AceNIC PCI vendor/device ID. 1896 */ 1897 #define ALT_VENDORID 0x12AE 1898 #define ALT_DEVICEID_ACENIC 0x0001 1899 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 1900 #define ALT_DEVICEID_BCM5700 0x0003 1901 #define ALT_DEVICEID_BCM5701 0x0004 1902 1903 /* 1904 * 3Com 3c985 PCI vendor/device ID. 1905 */ 1906 #define TC_VENDORID 0x10B7 1907 #define TC_DEVICEID_3C985 0x0001 1908 #define TC_DEVICEID_3C996 0x0003 1909 1910 /* 1911 * SysKonnect PCI vendor ID 1912 */ 1913 #define SK_VENDORID 0x1148 1914 #define SK_DEVICEID_ALTIMA 0x4400 1915 #define SK_SUBSYSID_9D21 0x4421 1916 #define SK_SUBSYSID_9D41 0x4441 1917 1918 /* 1919 * Altima PCI vendor/device ID. 1920 */ 1921 #define ALTIMA_VENDORID 0x173b 1922 #define ALTIMA_DEVICE_AC1000 0x03e8 1923 1924 /* 1925 * Offset of MAC address inside EEPROM. 1926 */ 1927 #define BGE_EE_MAC_OFFSET 0x7C 1928 #define BGE_EE_HWCFG_OFFSET 0xC8 1929 1930 #define BGE_HWCFG_VOLTAGE 0x00000003 1931 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1932 #define BGE_HWCFG_MEDIA 0x00000030 1933 1934 #define BGE_VOLTAGE_1POINT3 0x00000000 1935 #define BGE_VOLTAGE_1POINT8 0x00000001 1936 1937 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 1938 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1939 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 1940 1941 #define BGE_MEDIA_UNSPEC 0x00000000 1942 #define BGE_MEDIA_COPPER 0x00000010 1943 #define BGE_MEDIA_FIBER 0x00000020 1944 1945 #define BGE_PCI_READ_CMD 0x06000000 1946 #define BGE_PCI_WRITE_CMD 0x70000000 1947 1948 #define BGE_TICKS_PER_SEC 1000000 1949 1950 /* 1951 * Ring size constants. 1952 */ 1953 #define BGE_EVENT_RING_CNT 256 1954 #define BGE_CMD_RING_CNT 64 1955 #define BGE_STD_RX_RING_CNT 512 1956 #define BGE_JUMBO_RX_RING_CNT 256 1957 #define BGE_MINI_RX_RING_CNT 1024 1958 #define BGE_RETURN_RING_CNT 1024 1959 #define BGE_RETURN_RING_CNT_5705 512 1960 1961 /* 1962 * Possible TX ring sizes. 1963 */ 1964 #define BGE_TX_RING_CNT_128 128 1965 #define BGE_TX_RING_BASE_128 0x3800 1966 1967 #define BGE_TX_RING_CNT_256 256 1968 #define BGE_TX_RING_BASE_256 0x3000 1969 1970 #define BGE_TX_RING_CNT_512 512 1971 #define BGE_TX_RING_BASE_512 0x2000 1972 1973 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1974 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1975 1976 /* 1977 * Tigon III statistics counters. 1978 */ 1979 1980 /* Stats counters access through registers */ 1981 struct bge_mac_stats_regs { 1982 u_int32_t ifHCOutOctets; 1983 u_int32_t Reserved0; 1984 u_int32_t etherStatsCollisions; 1985 u_int32_t outXonSent; 1986 u_int32_t outXoffSent; 1987 u_int32_t Reserved1; 1988 u_int32_t dot3StatsInternalMacTransmitErrors; 1989 u_int32_t dot3StatsSingleCollisionFrames; 1990 u_int32_t dot3StatsMultipleCollisionFrames; 1991 u_int32_t dot3StatsDeferredTransmissions; 1992 u_int32_t Reserved2; 1993 u_int32_t dot3StatsExcessiveCollisions; 1994 u_int32_t dot3StatsLateCollisions; 1995 u_int32_t Reserved3[14]; 1996 u_int32_t ifHCOutUcastPkts; 1997 u_int32_t ifHCOutMulticastPkts; 1998 u_int32_t ifHCOutBroadcastPkts; 1999 u_int32_t Reserved4[2]; 2000 u_int32_t ifHCInOctets; 2001 u_int32_t Reserved5; 2002 u_int32_t etherStatsFragments; 2003 u_int32_t ifHCInUcastPkts; 2004 u_int32_t ifHCInMulticastPkts; 2005 u_int32_t ifHCInBroadcastPkts; 2006 u_int32_t dot3StatsFCSErrors; 2007 u_int32_t dot3StatsAlignmentErrors; 2008 u_int32_t xonPauseFramesReceived; 2009 u_int32_t xoffPauseFramesReceived; 2010 u_int32_t macControlFramesReceived; 2011 u_int32_t xoffStateEntered; 2012 u_int32_t dot3StatsFramesTooLong; 2013 u_int32_t etherStatsJabbers; 2014 u_int32_t etherStatsUndersizePkts; 2015 }; 2016 2017 struct bge_stats { 2018 u_int8_t Reserved0[256]; 2019 2020 /* Statistics maintained by Receive MAC. */ 2021 bge_hostaddr ifHCInOctets; 2022 bge_hostaddr Reserved1; 2023 bge_hostaddr etherStatsFragments; 2024 bge_hostaddr ifHCInUcastPkts; 2025 bge_hostaddr ifHCInMulticastPkts; 2026 bge_hostaddr ifHCInBroadcastPkts; 2027 bge_hostaddr dot3StatsFCSErrors; 2028 bge_hostaddr dot3StatsAlignmentErrors; 2029 bge_hostaddr xonPauseFramesReceived; 2030 bge_hostaddr xoffPauseFramesReceived; 2031 bge_hostaddr macControlFramesReceived; 2032 bge_hostaddr xoffStateEntered; 2033 bge_hostaddr dot3StatsFramesTooLong; 2034 bge_hostaddr etherStatsJabbers; 2035 bge_hostaddr etherStatsUndersizePkts; 2036 bge_hostaddr inRangeLengthError; 2037 bge_hostaddr outRangeLengthError; 2038 bge_hostaddr etherStatsPkts64Octets; 2039 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2040 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2041 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2042 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2043 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2044 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2045 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2046 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2047 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2048 2049 bge_hostaddr Unused1[37]; 2050 2051 /* Statistics maintained by Transmit MAC. */ 2052 bge_hostaddr ifHCOutOctets; 2053 bge_hostaddr Reserved2; 2054 bge_hostaddr etherStatsCollisions; 2055 bge_hostaddr outXonSent; 2056 bge_hostaddr outXoffSent; 2057 bge_hostaddr flowControlDone; 2058 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2059 bge_hostaddr dot3StatsSingleCollisionFrames; 2060 bge_hostaddr dot3StatsMultipleCollisionFrames; 2061 bge_hostaddr dot3StatsDeferredTransmissions; 2062 bge_hostaddr Reserved3; 2063 bge_hostaddr dot3StatsExcessiveCollisions; 2064 bge_hostaddr dot3StatsLateCollisions; 2065 bge_hostaddr dot3Collided2Times; 2066 bge_hostaddr dot3Collided3Times; 2067 bge_hostaddr dot3Collided4Times; 2068 bge_hostaddr dot3Collided5Times; 2069 bge_hostaddr dot3Collided6Times; 2070 bge_hostaddr dot3Collided7Times; 2071 bge_hostaddr dot3Collided8Times; 2072 bge_hostaddr dot3Collided9Times; 2073 bge_hostaddr dot3Collided10Times; 2074 bge_hostaddr dot3Collided11Times; 2075 bge_hostaddr dot3Collided12Times; 2076 bge_hostaddr dot3Collided13Times; 2077 bge_hostaddr dot3Collided14Times; 2078 bge_hostaddr dot3Collided15Times; 2079 bge_hostaddr ifHCOutUcastPkts; 2080 bge_hostaddr ifHCOutMulticastPkts; 2081 bge_hostaddr ifHCOutBroadcastPkts; 2082 bge_hostaddr dot3StatsCarrierSenseErrors; 2083 bge_hostaddr ifOutDiscards; 2084 bge_hostaddr ifOutErrors; 2085 2086 bge_hostaddr Unused2[31]; 2087 2088 /* Statistics maintained by Receive List Placement. */ 2089 bge_hostaddr COSIfHCInPkts[16]; 2090 bge_hostaddr COSFramesDroppedDueToFilters; 2091 bge_hostaddr nicDmaWriteQueueFull; 2092 bge_hostaddr nicDmaWriteHighPriQueueFull; 2093 bge_hostaddr nicNoMoreRxBDs; 2094 bge_hostaddr ifInDiscards; 2095 bge_hostaddr ifInErrors; 2096 bge_hostaddr nicRecvThresholdHit; 2097 2098 bge_hostaddr Unused3[9]; 2099 2100 /* Statistics maintained by Send Data Initiator. */ 2101 bge_hostaddr COSIfHCOutPkts[16]; 2102 bge_hostaddr nicDmaReadQueueFull; 2103 bge_hostaddr nicDmaReadHighPriQueueFull; 2104 bge_hostaddr nicSendDataCompQueueFull; 2105 2106 /* Statistics maintained by Host Coalescing. */ 2107 bge_hostaddr nicRingSetSendProdIndex; 2108 bge_hostaddr nicRingStatusUpdate; 2109 bge_hostaddr nicInterrupts; 2110 bge_hostaddr nicAvoidedInterrupts; 2111 bge_hostaddr nicSendThresholdHit; 2112 2113 u_int8_t Reserved4[320]; 2114 }; 2115 2116 /* 2117 * Tigon general information block. This resides in host memory 2118 * and contains the status counters, ring control blocks and 2119 * producer pointers. 2120 */ 2121 2122 struct bge_gib { 2123 struct bge_stats bge_stats; 2124 struct bge_rcb bge_tx_rcb[16]; 2125 struct bge_rcb bge_std_rx_rcb; 2126 struct bge_rcb bge_jumbo_rx_rcb; 2127 struct bge_rcb bge_mini_rx_rcb; 2128 struct bge_rcb bge_return_rcb; 2129 }; 2130 2131 /* 2132 * NOTE! On the Alpha, we have an alignment constraint. 2133 * The first thing in the packet is a 14-byte Ethernet header. 2134 * This means that the packet is misaligned. To compensate, 2135 * we actually offset the data 2 bytes into the cluster. This 2136 * alignes the packet after the Ethernet header at a 32-bit 2137 * boundary. 2138 */ 2139 2140 #define ETHER_ALIGN 2 2141 2142 #define BGE_FRAMELEN ETHER_MAX_LEN 2143 #define BGE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_CRC_LEN) 2144 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2145 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2146 #define BGE_PAGE_SIZE PAGE_SIZE 2147 #define BGE_MIN_FRAMELEN 60 2148 2149 /* 2150 * Other utility macros. 2151 */ 2152 #define BGE_INC(x, y) (x) = (x + 1) % y 2153 2154 /* 2155 * Vital product data and structures. 2156 */ 2157 #define BGE_VPD_FLAG 0x8000 2158 2159 /* VPD structures */ 2160 struct vpd_res { 2161 u_int8_t vr_id; 2162 u_int8_t vr_len; 2163 u_int8_t vr_pad; 2164 }; 2165 2166 struct vpd_key { 2167 char vk_key[2]; 2168 u_int8_t vk_len; 2169 }; 2170 2171 #define VPD_RES_ID 0x82 /* ID string */ 2172 #define VPD_RES_READ 0x90 /* start of read only area */ 2173 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2174 #define VPD_RES_END 0x78 /* end tag */ 2175 2176 2177 /* 2178 * Register access macros. The Tigon always uses memory mapped register 2179 * accesses and all registers must be accessed with 32 bit operations. 2180 */ 2181 2182 #define CSR_WRITE_4(sc, reg, val) \ 2183 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2184 2185 #define CSR_READ_4(sc, reg) \ 2186 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2187 2188 #define BGE_SETBIT(sc, reg, x) \ 2189 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2190 #define BGE_CLRBIT(sc, reg, x) \ 2191 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2192 2193 #define PCI_SETBIT(pc, tag, reg, x) \ 2194 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 2195 #define PCI_CLRBIT(pc, tag, reg, x) \ 2196 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 2197 2198 /* 2199 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2200 * values are tuneable. They control the actual amount of buffers 2201 * allocated for the standard, mini and jumbo receive rings. 2202 */ 2203 2204 #define BGE_SSLOTS 256 2205 #define BGE_MSLOTS 256 2206 #define BGE_JSLOTS 384 2207 #define BGE_RSLOTS 256 2208 2209 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2210 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2211 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2212 #define BGE_JPAGESZ PAGE_SIZE 2213 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2214 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2215 2216 /* 2217 * Ring structures. Most of these reside in host memory and we tell 2218 * the NIC where they are via the ring control blocks. The exceptions 2219 * are the tx and command rings, which live in NIC memory and which 2220 * we access via the shared memory window. 2221 */ 2222 struct bge_ring_data { 2223 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2224 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2225 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2226 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2227 struct bge_status_block bge_status_block; 2228 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2229 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2230 struct bge_gib bge_info; 2231 }; 2232 2233 #define BGE_RING_DMA_ADDR(sc, offset) \ 2234 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2235 offsetof(struct bge_ring_data, offset)) 2236 2237 /* 2238 * Number of DMA segments in a TxCB. Note that this is carefully 2239 * chosen to make the total struct size an even power of two. It's 2240 * critical that no TxCB be split across a page boundary since 2241 * no attempt is made to allocate physically contiguous memory. 2242 * 2243 */ 2244 #ifdef _LP64 2245 #define BGE_NTXSEG 30 2246 #else 2247 #define BGE_NTXSEG 31 2248 #endif 2249 2250 /* 2251 * Mbuf pointers. We need these to keep track of the virtual addresses 2252 * of our mbuf chains since we can only convert from physical to virtual, 2253 * not the other way around. 2254 */ 2255 struct bge_chain_data { 2256 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2257 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2258 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2259 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2260 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2261 bus_dmamap_t bge_rx_jumbo_map; 2262 /* Stick the jumbo mem management stuff here too. */ 2263 caddr_t bge_jslots[BGE_JSLOTS]; 2264 void *bge_jumbo_buf; 2265 }; 2266 2267 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 2268 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2269 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2270 2271 struct bge_type { 2272 u_int16_t bge_vid; 2273 u_int16_t bge_did; 2274 char *bge_name; 2275 }; 2276 2277 #define BGE_HWREV_TIGON 0x01 2278 #define BGE_HWREV_TIGON_II 0x02 2279 #define BGE_TIMEOUT 1000 2280 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2281 2282 struct bge_jpool_entry { 2283 int slot; 2284 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2285 }; 2286 2287 struct bge_bcom_hack { 2288 int reg; 2289 int val; 2290 }; 2291 2292 struct txdmamap_pool_entry { 2293 bus_dmamap_t dmamap; 2294 SLIST_ENTRY(txdmamap_pool_entry) link; 2295 }; 2296 2297 /* 2298 * Flags for bge_flags. 2299 */ 2300 #define BGE_TXRING_VALID 0x0001 2301 #define BGE_RXRING_VALID 0x0002 2302 #define BGE_JUMBO_RXRING_VALID 0x0004 2303 2304 struct bge_softc { 2305 struct device bge_dev; 2306 struct ethercom ethercom; /* interface info */ 2307 bus_space_handle_t bge_bhandle; 2308 bus_space_tag_t bge_btag; 2309 void *bge_intrhand; 2310 struct pci_attach_args bge_pa; 2311 struct mii_data bge_mii; 2312 struct ifmedia bge_ifmedia; /* media info */ 2313 u_int8_t bge_extram; /* has external SSRAM */ 2314 u_int8_t bge_tbi; 2315 u_int8_t bge_rx_alignment_bug; 2316 u_int32_t bge_return_ring_cnt; 2317 bus_dma_tag_t bge_dmatag; 2318 u_int32_t bge_chipid; 2319 u_int32_t bge_quirks; 2320 u_int32_t bge_local_ctrl_reg; 2321 struct bge_ring_data *bge_rdata; /* rings */ 2322 struct bge_chain_data bge_cdata; /* mbufs */ 2323 bus_dmamap_t bge_ring_map; 2324 u_int16_t bge_tx_saved_considx; 2325 u_int16_t bge_rx_saved_considx; 2326 u_int16_t bge_ev_saved_considx; 2327 u_int16_t bge_std; /* current std ring head */ 2328 u_int16_t bge_jumbo; /* current jumo ring head */ 2329 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2330 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2331 u_int32_t bge_stat_ticks; 2332 u_int32_t bge_rx_coal_ticks; 2333 u_int32_t bge_tx_coal_ticks; 2334 u_int32_t bge_rx_max_coal_bds; 2335 u_int32_t bge_tx_max_coal_bds; 2336 u_int32_t bge_tx_buf_ratio; 2337 int bge_if_flags; 2338 int bge_flags; 2339 int bge_flowflags; 2340 #ifdef BGE_EVENT_COUNTERS 2341 /* 2342 * Event counters. 2343 */ 2344 struct evcnt bge_ev_intr; /* interrupts */ 2345 struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ 2346 struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ 2347 struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ 2348 struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ 2349 struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ 2350 struct evcnt bge_ev_xoffentered;/* XOFF state entered */ 2351 #endif /* BGE_EVENT_COUNTERS */ 2352 int bge_txcnt; 2353 int bge_link; 2354 struct callout bge_timeout; 2355 char *bge_vpd_prodname; 2356 char *bge_vpd_readonly; 2357 int bge_pending_rxintr_change; 2358 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2359 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2360 }; 2361
Indexes created Sat Sep 27 22:09:54 GMT 2025