if_bgereg.h revision 1.27
1 /* $NetBSD: if_bgereg.h,v 1.27 2005/11/15 06:05:44 jonathan Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79 #define BGE_UNMAPPED 0x00001000 80 #define BGE_UNMAPPED_END 0x00001FFF 81 #define BGE_DMA_DESCRIPTORS 0x00002000 82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83 #define BGE_SEND_RING_1_TO_4 0x00004000 84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86 /* Mappings for internal memory configuration */ 87 #define BGE_STD_RX_RINGS 0x00006000 88 #define BGE_STD_RX_RINGS_END 0x00006FFF 89 #define BGE_JUMBO_RX_RINGS 0x00007000 90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91 #define BGE_BUFFPOOL_1 0x00008000 92 #define BGE_BUFFPOOL_1_END 0x0000FFFF 93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_2_END 0x00017FFF 95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96 #define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98 /* Mappings for external SSRAM configurations */ 99 #define BGE_SEND_RING_5_TO_6 0x00006000 100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101 #define BGE_SEND_RING_7_TO_8 0x00007000 102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103 #define BGE_SEND_RING_9_TO_16 0x00008000 104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105 #define BGE_EXT_STD_RX_RINGS 0x0000C000 106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109 #define BGE_MINI_RX_RINGS 0x0000E000 110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION1_END 0x00017FFF 113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114 #define BGE_AVAIL_REGION2_END 0x0001FFFF 115 #define BGE_EXT_SSRAM 0x00020000 116 #define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119 /* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129 /* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132 #define BGE_PCI_VID 0x00 133 #define BGE_PCI_DID 0x02 134 #define BGE_PCI_CMD 0x04 135 #define BGE_PCI_STS 0x06 136 #define BGE_PCI_REV 0x08 137 #define BGE_PCI_CLASS 0x09 138 #define BGE_PCI_CACHESZ 0x0C 139 #define BGE_PCI_LATTIMER 0x0D 140 #define BGE_PCI_HDRTYPE 0x0E 141 #define BGE_PCI_BIST 0x0F 142 #define BGE_PCI_BAR0 0x10 143 #define BGE_PCI_BAR1 0x14 144 #define BGE_PCI_SUBSYS 0x2C 145 #define BGE_PCI_SUBVID 0x2E 146 #define BGE_PCI_ROMBASE 0x30 147 #define BGE_PCI_CAPPTR 0x34 148 #define BGE_PCI_INTLINE 0x3C 149 #define BGE_PCI_INTPIN 0x3D 150 #define BGE_PCI_MINGNT 0x3E 151 #define BGE_PCI_MAXLAT 0x3F 152 #define BGE_PCI_PCIXCAP 0x40 153 #define BGE_PCI_NEXTPTR_PM 0x41 154 #define BGE_PCI_PCIX_CMD 0x42 155 #define BGE_PCI_PCIX_STS 0x44 156 #define BGE_PCI_PWRMGMT_CAPID 0x48 157 #define BGE_PCI_NEXTPTR_VPD 0x49 158 #define BGE_PCI_PWRMGMT_CAPS 0x4A 159 #define BGE_PCI_PWRMGMT_CMD 0x4C 160 #define BGE_PCI_PWRMGMT_STS 0x4D 161 #define BGE_PCI_PWRMGMT_DATA 0x4F 162 #define BGE_PCI_VPD_CAPID 0x50 163 #define BGE_PCI_NEXTPTR_MSI 0x51 164 #define BGE_PCI_VPD_ADDR 0x52 165 #define BGE_PCI_VPD_DATA 0x54 166 #define BGE_PCI_MSI_CAPID 0x58 167 #define BGE_PCI_NEXTPTR_NONE 0x59 168 #define BGE_PCI_MSI_CTL 0x5A 169 #define BGE_PCI_MSI_ADDR_HI 0x5C 170 #define BGE_PCI_MSI_ADDR_LO 0x60 171 #define BGE_PCI_MSI_DATA 0x64 172 173 /* 174 * PCI registers specific to the BCM570x family. 175 */ 176 #define BGE_PCI_MISC_CTL 0x68 177 #define BGE_PCI_DMA_RW_CTL 0x6C 178 #define BGE_PCI_PCISTATE 0x70 179 #define BGE_PCI_CLKCTL 0x74 180 #define BGE_PCI_REG_BASEADDR 0x78 181 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 182 #define BGE_PCI_REG_DATA 0x80 183 #define BGE_PCI_MEMWIN_DATA 0x84 184 #define BGE_PCI_MODECTL 0x88 185 #define BGE_PCI_MISC_CFG 0x8C 186 #define BGE_PCI_MISC_LOCALCTL 0x90 187 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 188 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 189 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 190 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 191 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 192 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 193 #define BGE_PCI_ISR_MBX_HI 0xB0 194 #define BGE_PCI_ISR_MBX_LO 0xB4 195 /* XXX: used in PCI-Express code for 575x chips */ 196 #define BGE_PCI_UNKNOWN0 0xC4 197 #define BGE_PCI_UNKNOWN1 0xD8 198 199 /* PCI Misc. Host control register */ 200 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 201 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 202 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 203 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 204 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 205 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 206 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 207 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 208 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 209 210 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 211 #if BYTE_ORDER == LITTLE_ENDIAN 212 #define BGE_DMA_SWAP_OPTIONS \ 213 BGE_MODECTL_WORDSWAP_NONFRAME| \ 214 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 215 #else 216 #define BGE_DMA_SWAP_OPTIONS \ 217 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 218 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 219 #endif 220 221 #define BGE_INIT \ 222 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 223 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 224 225 #define BGE_CHIPID_TIGON_I 0x40000000 226 #define BGE_CHIPID_TIGON_II 0x60000000 227 #define BGE_CHIPID_BCM5700_A0 0x70000000 228 #define BGE_CHIPID_BCM5700_A1 0x70010000 229 #define BGE_CHIPID_BCM5700_B0 0x71000000 230 #define BGE_CHIPID_BCM5700_B1 0x71020000 231 #define BGE_CHIPID_BCM5700_B2 0x71030000 232 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 233 #define BGE_CHIPID_BCM5700_C0 0x72000000 234 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 235 #define BGE_CHIPID_BCM5701_B0 0x01000000 236 #define BGE_CHIPID_BCM5701_B2 0x01020000 237 #define BGE_CHIPID_BCM5701_B5 0x01050000 238 #define BGE_CHIPID_BCM5703_A0 0x10000000 239 #define BGE_CHIPID_BCM5703_A1 0x10010000 240 #define BGE_CHIPID_BCM5703_A2 0x10020000 241 #define BGE_CHIPID_BCM5703_A3 0x11000000 242 #define BGE_CHIPID_BCM5704_A0 0x20000000 243 #define BGE_CHIPID_BCM5704_A1 0x20010000 244 #define BGE_CHIPID_BCM5704_A2 0x20020000 245 #define BGE_CHIPID_BCM5704_A3 0x20030000 246 #define BGE_CHIPID_BCM5705_A0 0x30000000 247 #define BGE_CHIPID_BCM5705_A1 0x30010000 248 #define BGE_CHIPID_BCM5705_A2 0x30020000 249 #define BGE_CHIPID_BCM5705_A3 0x30030000 250 #define BGE_CHIPID_BCM5750_A0 0x40000000 251 #define BGE_CHIPID_BCM5750_A1 0x40010000 252 #define BGE_CHIPID_BCM5751_A1 0x41010000 253 254 /* shorthand one */ 255 #define BGE_ASICREV(x) ((x) >> 28) 256 #define BGE_ASICREV_BCM5700 0x07 257 #define BGE_ASICREV_BCM5701 0x00 258 #define BGE_ASICREV_BCM5703 0x01 259 #define BGE_ASICREV_BCM5704 0x02 260 #define BGE_ASICREV_BCM5705 0x03 261 #define BGE_ASICREV_BCM5750 0x04 262 263 /* chip revisions */ 264 #define BGE_CHIPREV(x) ((x) >> 24) 265 #define BGE_CHIPREV_5700_AX 0x70 266 #define BGE_CHIPREV_5700_BX 0x71 267 #define BGE_CHIPREV_5700_CX 0x72 268 #define BGE_CHIPREV_5701_AX 0x00 269 270 /* PCI DMA Read/Write Control register */ 271 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 272 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 273 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 274 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 275 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 276 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 277 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 278 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 279 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 280 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 281 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 282 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 283 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 284 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 285 286 287 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 288 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 289 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 290 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 291 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 292 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 293 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 294 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 295 296 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 297 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 298 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 299 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 300 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 301 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 302 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 303 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 304 305 /* 306 * PCI state register -- note, this register is read only 307 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 308 * register is set. 309 */ 310 #define BGE_PCISTATE_FORCE_RESET 0x00000001 311 #define BGE_PCISTATE_INTR_STATE 0x00000002 312 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 313 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 314 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 315 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 316 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 317 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 318 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 319 320 /* 321 * The following bits in PCI state register are reserved. 322 * If we check that the register values reverts on reset, 323 * do not check these bits. On some 5704C (rev A3) and some 324 * Altima chips, these bits do not revert until much later 325 * in the bge driver's bge_reset() chip-reset state machine. 326 */ 327 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 328 329 /* 330 * PCI Clock Control register -- note, this register is read only 331 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 332 * register is set. 333 */ 334 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 335 #define BGE_PCICLOCKCTL_M66EN 0x00000080 336 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 337 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 338 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 339 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 340 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 341 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 342 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 343 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 344 345 346 #ifndef PCIM_CMD_MWIEN 347 #define PCIM_CMD_MWIEN 0x0010 348 #endif 349 350 /* 351 * High priority mailbox registers 352 * Each mailbox is 64-bits wide, though we only use the 353 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 354 * first. The NIC will load the mailbox after the lower 32 bit word 355 * has been updated. 356 */ 357 #define BGE_MBX_IRQ0_HI 0x0200 358 #define BGE_MBX_IRQ0_LO 0x0204 359 #define BGE_MBX_IRQ1_HI 0x0208 360 #define BGE_MBX_IRQ1_LO 0x020C 361 #define BGE_MBX_IRQ2_HI 0x0210 362 #define BGE_MBX_IRQ2_LO 0x0214 363 #define BGE_MBX_IRQ3_HI 0x0218 364 #define BGE_MBX_IRQ3_LO 0x021C 365 #define BGE_MBX_GEN0_HI 0x0220 366 #define BGE_MBX_GEN0_LO 0x0224 367 #define BGE_MBX_GEN1_HI 0x0228 368 #define BGE_MBX_GEN1_LO 0x022C 369 #define BGE_MBX_GEN2_HI 0x0230 370 #define BGE_MBX_GEN2_LO 0x0234 371 #define BGE_MBX_GEN3_HI 0x0228 372 #define BGE_MBX_GEN3_LO 0x022C 373 #define BGE_MBX_GEN4_HI 0x0240 374 #define BGE_MBX_GEN4_LO 0x0244 375 #define BGE_MBX_GEN5_HI 0x0248 376 #define BGE_MBX_GEN5_LO 0x024C 377 #define BGE_MBX_GEN6_HI 0x0250 378 #define BGE_MBX_GEN6_LO 0x0254 379 #define BGE_MBX_GEN7_HI 0x0258 380 #define BGE_MBX_GEN7_LO 0x025C 381 #define BGE_MBX_RELOAD_STATS_HI 0x0260 382 #define BGE_MBX_RELOAD_STATS_LO 0x0264 383 #define BGE_MBX_RX_STD_PROD_HI 0x0268 384 #define BGE_MBX_RX_STD_PROD_LO 0x026C 385 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 386 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 387 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 388 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 389 #define BGE_MBX_RX_CONS0_HI 0x0280 390 #define BGE_MBX_RX_CONS0_LO 0x0284 391 #define BGE_MBX_RX_CONS1_HI 0x0288 392 #define BGE_MBX_RX_CONS1_LO 0x028C 393 #define BGE_MBX_RX_CONS2_HI 0x0290 394 #define BGE_MBX_RX_CONS2_LO 0x0294 395 #define BGE_MBX_RX_CONS3_HI 0x0298 396 #define BGE_MBX_RX_CONS3_LO 0x029C 397 #define BGE_MBX_RX_CONS4_HI 0x02A0 398 #define BGE_MBX_RX_CONS4_LO 0x02A4 399 #define BGE_MBX_RX_CONS5_HI 0x02A8 400 #define BGE_MBX_RX_CONS5_LO 0x02AC 401 #define BGE_MBX_RX_CONS6_HI 0x02B0 402 #define BGE_MBX_RX_CONS6_LO 0x02B4 403 #define BGE_MBX_RX_CONS7_HI 0x02B8 404 #define BGE_MBX_RX_CONS7_LO 0x02BC 405 #define BGE_MBX_RX_CONS8_HI 0x02C0 406 #define BGE_MBX_RX_CONS8_LO 0x02C4 407 #define BGE_MBX_RX_CONS9_HI 0x02C8 408 #define BGE_MBX_RX_CONS9_LO 0x02CC 409 #define BGE_MBX_RX_CONS10_HI 0x02D0 410 #define BGE_MBX_RX_CONS10_LO 0x02D4 411 #define BGE_MBX_RX_CONS11_HI 0x02D8 412 #define BGE_MBX_RX_CONS11_LO 0x02DC 413 #define BGE_MBX_RX_CONS12_HI 0x02E0 414 #define BGE_MBX_RX_CONS12_LO 0x02E4 415 #define BGE_MBX_RX_CONS13_HI 0x02E8 416 #define BGE_MBX_RX_CONS13_LO 0x02EC 417 #define BGE_MBX_RX_CONS14_HI 0x02F0 418 #define BGE_MBX_RX_CONS14_LO 0x02F4 419 #define BGE_MBX_RX_CONS15_HI 0x02F8 420 #define BGE_MBX_RX_CONS15_LO 0x02FC 421 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 422 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 423 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 424 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 425 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 426 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 427 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 428 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 429 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 430 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 431 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 432 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 433 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 434 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 435 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 436 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 437 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 438 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 439 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 440 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 441 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 442 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 443 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 444 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 445 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 446 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 447 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 448 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 449 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 450 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 451 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 452 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 453 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 454 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 455 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 456 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 457 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 458 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 459 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 460 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 461 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 462 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 463 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 464 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 465 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 466 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 467 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 468 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 469 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 470 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 471 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 472 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 473 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 474 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 475 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 476 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 477 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 478 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 479 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 480 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 481 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 482 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 483 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 484 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 485 486 #define BGE_TX_RINGS_MAX 4 487 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 488 #define BGE_RX_RINGS_MAX 16 489 490 /* Ethernet MAC control registers */ 491 #define BGE_MAC_MODE 0x0400 492 #define BGE_MAC_STS 0x0404 493 #define BGE_MAC_EVT_ENB 0x0408 494 #define BGE_MAC_LED_CTL 0x040C 495 #define BGE_MAC_ADDR1_LO 0x0410 496 #define BGE_MAC_ADDR1_HI 0x0414 497 #define BGE_MAC_ADDR2_LO 0x0418 498 #define BGE_MAC_ADDR2_HI 0x041C 499 #define BGE_MAC_ADDR3_LO 0x0420 500 #define BGE_MAC_ADDR3_HI 0x0424 501 #define BGE_MAC_ADDR4_LO 0x0428 502 #define BGE_MAC_ADDR4_HI 0x042C 503 #define BGE_WOL_PATPTR 0x0430 504 #define BGE_WOL_PATCFG 0x0434 505 #define BGE_TX_RANDOM_BACKOFF 0x0438 506 #define BGE_RX_MTU 0x043C 507 #define BGE_GBIT_PCS_TEST 0x0440 508 #define BGE_TX_TBI_AUTONEG 0x0444 509 #define BGE_RX_TBI_AUTONEG 0x0448 510 #define BGE_MI_COMM 0x044C 511 #define BGE_MI_STS 0x0450 512 #define BGE_MI_MODE 0x0454 513 #define BGE_AUTOPOLL_STS 0x0458 514 #define BGE_TX_MODE 0x045C 515 #define BGE_TX_STS 0x0460 516 #define BGE_TX_LENGTHS 0x0464 517 #define BGE_RX_MODE 0x0468 518 #define BGE_RX_STS 0x046C 519 #define BGE_MAR0 0x0470 520 #define BGE_MAR1 0x0474 521 #define BGE_MAR2 0x0478 522 #define BGE_MAR3 0x047C 523 #define BGE_RX_BD_RULES_CTL0 0x0480 524 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 525 #define BGE_RX_BD_RULES_CTL1 0x0488 526 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 527 #define BGE_RX_BD_RULES_CTL2 0x0490 528 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 529 #define BGE_RX_BD_RULES_CTL3 0x0498 530 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 531 #define BGE_RX_BD_RULES_CTL4 0x04A0 532 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 533 #define BGE_RX_BD_RULES_CTL5 0x04A8 534 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 535 #define BGE_RX_BD_RULES_CTL6 0x04B0 536 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 537 #define BGE_RX_BD_RULES_CTL7 0x04B8 538 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 539 #define BGE_RX_BD_RULES_CTL8 0x04C0 540 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 541 #define BGE_RX_BD_RULES_CTL9 0x04C8 542 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 543 #define BGE_RX_BD_RULES_CTL10 0x04D0 544 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 545 #define BGE_RX_BD_RULES_CTL11 0x04D8 546 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 547 #define BGE_RX_BD_RULES_CTL12 0x04E0 548 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 549 #define BGE_RX_BD_RULES_CTL13 0x04E8 550 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 551 #define BGE_RX_BD_RULES_CTL14 0x04F0 552 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 553 #define BGE_RX_BD_RULES_CTL15 0x04F8 554 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 555 #define BGE_RX_RULES_CFG 0x0500 556 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 557 #define BGE_RX_STATS 0x0800 558 #define BGE_TX_STATS 0x0880 559 560 /* Ethernet MAC Mode register */ 561 #define BGE_MACMODE_RESET 0x00000001 562 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 563 #define BGE_MACMODE_PORTMODE 0x0000000C 564 #define BGE_MACMODE_LOOPBACK 0x00000010 565 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 566 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 567 #define BGE_MACMODE_MAX_DEFER 0x00000200 568 #define BGE_MACMODE_LINK_POLARITY 0x00000400 569 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 570 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 571 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 572 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 573 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 574 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 575 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 576 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 577 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 578 #define BGE_MACMODE_MIP_ENB 0x00100000 579 #define BGE_MACMODE_TXDMA_ENB 0x00200000 580 #define BGE_MACMODE_RXDMA_ENB 0x00400000 581 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 582 583 #define BGE_PORTMODE_NONE 0x00000000 584 #define BGE_PORTMODE_MII 0x00000004 585 #define BGE_PORTMODE_GMII 0x00000008 586 #define BGE_PORTMODE_TBI 0x0000000C 587 588 /* MAC Status register */ 589 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 590 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 591 #define BGE_MACSTAT_RX_CFG 0x00000004 592 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 593 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 594 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 595 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 596 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 597 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 598 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 599 #define BGE_MACSTAT_ODI_ERROR 0x02000000 600 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 601 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 602 603 /* MAC Event Enable Register */ 604 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 605 #define BGE_EVTENB_LINK_CHANGED 0x00001000 606 #define BGE_EVTENB_MI_COMPLETE 0x00400000 607 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 608 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 609 #define BGE_EVTENB_ODI_ERROR 0x02000000 610 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 611 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 612 613 /* LED Control Register */ 614 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 615 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 616 #define BGE_LEDCTL_100MBPS_LED 0x00000004 617 #define BGE_LEDCTL_10MBPS_LED 0x00000008 618 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 619 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 620 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 621 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 622 #define BGE_LEDCTL_100MBPS_STS 0x00000100 623 #define BGE_LEDCTL_10MBPS_STS 0x00000200 624 #define BGE_LEDCTL_TRADLED_STS 0x00000400 625 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 626 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 627 628 /* TX backoff seed register */ 629 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 630 631 /* Autopoll status register */ 632 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 633 634 /* Transmit MAC mode register */ 635 #define BGE_TXMODE_RESET 0x00000001 636 #define BGE_TXMODE_ENABLE 0x00000002 637 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 638 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 639 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 640 641 /* Transmit MAC status register */ 642 #define BGE_TXSTAT_RX_XOFFED 0x00000001 643 #define BGE_TXSTAT_SENT_XOFF 0x00000002 644 #define BGE_TXSTAT_SENT_XON 0x00000004 645 #define BGE_TXSTAT_LINK_UP 0x00000008 646 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 647 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 648 649 /* Transmit MAC lengths register */ 650 #define BGE_TXLEN_SLOTTIME 0x000000FF 651 #define BGE_TXLEN_IPG 0x00000F00 652 #define BGE_TXLEN_CRS 0x00003000 653 654 /* Receive MAC mode register */ 655 #define BGE_RXMODE_RESET 0x00000001 656 #define BGE_RXMODE_ENABLE 0x00000002 657 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 658 #define BGE_RXMODE_RX_GIANTS 0x00000020 659 #define BGE_RXMODE_RX_RUNTS 0x00000040 660 #define BGE_RXMODE_8022_LENCHECK 0x00000080 661 #define BGE_RXMODE_RX_PROMISC 0x00000100 662 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 663 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 664 665 /* Receive MAC status register */ 666 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 667 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 668 #define BGE_RXSTAT_RCVD_XON 0x00000004 669 670 /* Receive Rules Control register */ 671 #define BGE_RXRULECTL_OFFSET 0x000000FF 672 #define BGE_RXRULECTL_CLASS 0x00001F00 673 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 674 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 675 #define BGE_RXRULECTL_MAP 0x01000000 676 #define BGE_RXRULECTL_DISCARD 0x02000000 677 #define BGE_RXRULECTL_MASK 0x04000000 678 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 679 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 680 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 681 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 682 683 /* Receive Rules Mask register */ 684 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 685 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 686 687 /* MI communication register */ 688 #define BGE_MICOMM_DATA 0x0000FFFF 689 #define BGE_MICOMM_REG 0x001F0000 690 #define BGE_MICOMM_PHY 0x03E00000 691 #define BGE_MICOMM_CMD 0x0C000000 692 #define BGE_MICOMM_READFAIL 0x10000000 693 #define BGE_MICOMM_BUSY 0x20000000 694 695 #define BGE_MIREG(x) ((x & 0x1F) << 16) 696 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 697 #define BGE_MICMD_WRITE 0x04000000 698 #define BGE_MICMD_READ 0x08000000 699 700 /* MI status register */ 701 #define BGE_MISTS_LINK 0x00000001 702 #define BGE_MISTS_10MBPS 0x00000002 703 704 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 705 #define BGE_MIMODE_AUTOPOLL 0x00000010 706 #define BGE_MIMODE_CLKCNT 0x001F0000 707 708 709 /* 710 * Send data initiator control registers. 711 */ 712 #define BGE_SDI_MODE 0x0C00 713 #define BGE_SDI_STATUS 0x0C04 714 #define BGE_SDI_STATS_CTL 0x0C08 715 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 716 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 717 #define BGE_LOCSTATS_COS0 0x0C80 718 #define BGE_LOCSTATS_COS1 0x0C84 719 #define BGE_LOCSTATS_COS2 0x0C88 720 #define BGE_LOCSTATS_COS3 0x0C8C 721 #define BGE_LOCSTATS_COS4 0x0C90 722 #define BGE_LOCSTATS_COS5 0x0C84 723 #define BGE_LOCSTATS_COS6 0x0C98 724 #define BGE_LOCSTATS_COS7 0x0C9C 725 #define BGE_LOCSTATS_COS8 0x0CA0 726 #define BGE_LOCSTATS_COS9 0x0CA4 727 #define BGE_LOCSTATS_COS10 0x0CA8 728 #define BGE_LOCSTATS_COS11 0x0CAC 729 #define BGE_LOCSTATS_COS12 0x0CB0 730 #define BGE_LOCSTATS_COS13 0x0CB4 731 #define BGE_LOCSTATS_COS14 0x0CB8 732 #define BGE_LOCSTATS_COS15 0x0CBC 733 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 734 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 735 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 736 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 737 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 738 #define BGE_LOCSTATS_IRQS 0x0CD4 739 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 740 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 741 742 /* Send Data Initiator mode register */ 743 #define BGE_SDIMODE_RESET 0x00000001 744 #define BGE_SDIMODE_ENABLE 0x00000002 745 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 746 747 /* Send Data Initiator stats register */ 748 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 749 750 /* Send Data Initiator stats control register */ 751 #define BGE_SDISTATSCTL_ENABLE 0x00000001 752 #define BGE_SDISTATSCTL_FASTER 0x00000002 753 #define BGE_SDISTATSCTL_CLEAR 0x00000004 754 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 755 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 756 757 /* 758 * Send Data Completion Control registers 759 */ 760 #define BGE_SDC_MODE 0x1000 761 #define BGE_SDC_STATUS 0x1004 762 763 /* Send Data completion mode register */ 764 #define BGE_SDCMODE_RESET 0x00000001 765 #define BGE_SDCMODE_ENABLE 0x00000002 766 #define BGE_SDCMODE_ATTN 0x00000004 767 768 /* Send Data completion status register */ 769 #define BGE_SDCSTAT_ATTN 0x00000004 770 771 /* 772 * Send BD Ring Selector Control registers 773 */ 774 #define BGE_SRS_MODE 0x1400 775 #define BGE_SRS_STATUS 0x1404 776 #define BGE_SRS_HWDIAG 0x1408 777 #define BGE_SRS_LOC_NIC_CONS0 0x1440 778 #define BGE_SRS_LOC_NIC_CONS1 0x1444 779 #define BGE_SRS_LOC_NIC_CONS2 0x1448 780 #define BGE_SRS_LOC_NIC_CONS3 0x144C 781 #define BGE_SRS_LOC_NIC_CONS4 0x1450 782 #define BGE_SRS_LOC_NIC_CONS5 0x1454 783 #define BGE_SRS_LOC_NIC_CONS6 0x1458 784 #define BGE_SRS_LOC_NIC_CONS7 0x145C 785 #define BGE_SRS_LOC_NIC_CONS8 0x1460 786 #define BGE_SRS_LOC_NIC_CONS9 0x1464 787 #define BGE_SRS_LOC_NIC_CONS10 0x1468 788 #define BGE_SRS_LOC_NIC_CONS11 0x146C 789 #define BGE_SRS_LOC_NIC_CONS12 0x1470 790 #define BGE_SRS_LOC_NIC_CONS13 0x1474 791 #define BGE_SRS_LOC_NIC_CONS14 0x1478 792 #define BGE_SRS_LOC_NIC_CONS15 0x147C 793 794 /* Send BD Ring Selector Mode register */ 795 #define BGE_SRSMODE_RESET 0x00000001 796 #define BGE_SRSMODE_ENABLE 0x00000002 797 #define BGE_SRSMODE_ATTN 0x00000004 798 799 /* Send BD Ring Selector Status register */ 800 #define BGE_SRSSTAT_ERROR 0x00000004 801 802 /* Send BD Ring Selector HW Diagnostics register */ 803 #define BGE_SRSHWDIAG_STATE 0x0000000F 804 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 805 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 806 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 807 808 /* 809 * Send BD Initiator Selector Control registers 810 */ 811 #define BGE_SBDI_MODE 0x1800 812 #define BGE_SBDI_STATUS 0x1804 813 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 814 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 815 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 816 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 817 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 818 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 819 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 820 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 821 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 822 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 823 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 824 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 825 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 826 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 827 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 828 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 829 830 /* Send BD Initiator Mode register */ 831 #define BGE_SBDIMODE_RESET 0x00000001 832 #define BGE_SBDIMODE_ENABLE 0x00000002 833 #define BGE_SBDIMODE_ATTN 0x00000004 834 835 /* Send BD Initiator Status register */ 836 #define BGE_SBDISTAT_ERROR 0x00000004 837 838 /* 839 * Send BD Completion Control registers 840 */ 841 #define BGE_SBDC_MODE 0x1C00 842 #define BGE_SBDC_STATUS 0x1C04 843 844 /* Send BD Completion Control Mode register */ 845 #define BGE_SBDCMODE_RESET 0x00000001 846 #define BGE_SBDCMODE_ENABLE 0x00000002 847 #define BGE_SBDCMODE_ATTN 0x00000004 848 849 /* Send BD Completion Control Status register */ 850 #define BGE_SBDCSTAT_ATTN 0x00000004 851 852 /* 853 * Receive List Placement Control registers 854 */ 855 #define BGE_RXLP_MODE 0x2000 856 #define BGE_RXLP_STATUS 0x2004 857 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 858 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 859 #define BGE_RXLP_CFG 0x2010 860 #define BGE_RXLP_STATS_CTL 0x2014 861 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 862 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 863 #define BGE_RXLP_HEAD0 0x2100 864 #define BGE_RXLP_TAIL0 0x2104 865 #define BGE_RXLP_COUNT0 0x2108 866 #define BGE_RXLP_HEAD1 0x2110 867 #define BGE_RXLP_TAIL1 0x2114 868 #define BGE_RXLP_COUNT1 0x2118 869 #define BGE_RXLP_HEAD2 0x2120 870 #define BGE_RXLP_TAIL2 0x2124 871 #define BGE_RXLP_COUNT2 0x2128 872 #define BGE_RXLP_HEAD3 0x2130 873 #define BGE_RXLP_TAIL3 0x2134 874 #define BGE_RXLP_COUNT3 0x2138 875 #define BGE_RXLP_HEAD4 0x2140 876 #define BGE_RXLP_TAIL4 0x2144 877 #define BGE_RXLP_COUNT4 0x2148 878 #define BGE_RXLP_HEAD5 0x2150 879 #define BGE_RXLP_TAIL5 0x2154 880 #define BGE_RXLP_COUNT5 0x2158 881 #define BGE_RXLP_HEAD6 0x2160 882 #define BGE_RXLP_TAIL6 0x2164 883 #define BGE_RXLP_COUNT6 0x2168 884 #define BGE_RXLP_HEAD7 0x2170 885 #define BGE_RXLP_TAIL7 0x2174 886 #define BGE_RXLP_COUNT7 0x2178 887 #define BGE_RXLP_HEAD8 0x2180 888 #define BGE_RXLP_TAIL8 0x2184 889 #define BGE_RXLP_COUNT8 0x2188 890 #define BGE_RXLP_HEAD9 0x2190 891 #define BGE_RXLP_TAIL9 0x2194 892 #define BGE_RXLP_COUNT9 0x2198 893 #define BGE_RXLP_HEAD10 0x21A0 894 #define BGE_RXLP_TAIL10 0x21A4 895 #define BGE_RXLP_COUNT10 0x21A8 896 #define BGE_RXLP_HEAD11 0x21B0 897 #define BGE_RXLP_TAIL11 0x21B4 898 #define BGE_RXLP_COUNT11 0x21B8 899 #define BGE_RXLP_HEAD12 0x21C0 900 #define BGE_RXLP_TAIL12 0x21C4 901 #define BGE_RXLP_COUNT12 0x21C8 902 #define BGE_RXLP_HEAD13 0x21D0 903 #define BGE_RXLP_TAIL13 0x21D4 904 #define BGE_RXLP_COUNT13 0x21D8 905 #define BGE_RXLP_HEAD14 0x21E0 906 #define BGE_RXLP_TAIL14 0x21E4 907 #define BGE_RXLP_COUNT14 0x21E8 908 #define BGE_RXLP_HEAD15 0x21F0 909 #define BGE_RXLP_TAIL15 0x21F4 910 #define BGE_RXLP_COUNT15 0x21F8 911 #define BGE_RXLP_LOCSTAT_COS0 0x2200 912 #define BGE_RXLP_LOCSTAT_COS1 0x2204 913 #define BGE_RXLP_LOCSTAT_COS2 0x2208 914 #define BGE_RXLP_LOCSTAT_COS3 0x220C 915 #define BGE_RXLP_LOCSTAT_COS4 0x2210 916 #define BGE_RXLP_LOCSTAT_COS5 0x2214 917 #define BGE_RXLP_LOCSTAT_COS6 0x2218 918 #define BGE_RXLP_LOCSTAT_COS7 0x221C 919 #define BGE_RXLP_LOCSTAT_COS8 0x2220 920 #define BGE_RXLP_LOCSTAT_COS9 0x2224 921 #define BGE_RXLP_LOCSTAT_COS10 0x2228 922 #define BGE_RXLP_LOCSTAT_COS11 0x222C 923 #define BGE_RXLP_LOCSTAT_COS12 0x2230 924 #define BGE_RXLP_LOCSTAT_COS13 0x2234 925 #define BGE_RXLP_LOCSTAT_COS14 0x2238 926 #define BGE_RXLP_LOCSTAT_COS15 0x223C 927 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 928 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 929 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 930 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 931 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 932 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 933 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 934 935 936 /* Receive List Placement mode register */ 937 #define BGE_RXLPMODE_RESET 0x00000001 938 #define BGE_RXLPMODE_ENABLE 0x00000002 939 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 940 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 941 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 942 943 /* Receive List Placement Status register */ 944 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 945 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 946 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 947 948 /* 949 * Receive Data and Receive BD Initiator Control Registers 950 */ 951 #define BGE_RDBDI_MODE 0x2400 952 #define BGE_RDBDI_STATUS 0x2404 953 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 954 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 955 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 956 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 957 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 958 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 959 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 960 #define BGE_RX_STD_RCB_NICADDR 0x245C 961 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 962 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 963 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 964 #define BGE_RX_MINI_RCB_NICADDR 0x246C 965 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 966 #define BGE_RDBDI_STD_RX_CONS 0x2474 967 #define BGE_RDBDI_MINI_RX_CONS 0x2478 968 #define BGE_RDBDI_RETURN_PROD0 0x2480 969 #define BGE_RDBDI_RETURN_PROD1 0x2484 970 #define BGE_RDBDI_RETURN_PROD2 0x2488 971 #define BGE_RDBDI_RETURN_PROD3 0x248C 972 #define BGE_RDBDI_RETURN_PROD4 0x2490 973 #define BGE_RDBDI_RETURN_PROD5 0x2494 974 #define BGE_RDBDI_RETURN_PROD6 0x2498 975 #define BGE_RDBDI_RETURN_PROD7 0x249C 976 #define BGE_RDBDI_RETURN_PROD8 0x24A0 977 #define BGE_RDBDI_RETURN_PROD9 0x24A4 978 #define BGE_RDBDI_RETURN_PROD10 0x24A8 979 #define BGE_RDBDI_RETURN_PROD11 0x24AC 980 #define BGE_RDBDI_RETURN_PROD12 0x24B0 981 #define BGE_RDBDI_RETURN_PROD13 0x24B4 982 #define BGE_RDBDI_RETURN_PROD14 0x24B8 983 #define BGE_RDBDI_RETURN_PROD15 0x24BC 984 #define BGE_RDBDI_HWDIAG 0x24C0 985 986 987 /* Receive Data and Receive BD Initiator Mode register */ 988 #define BGE_RDBDIMODE_RESET 0x00000001 989 #define BGE_RDBDIMODE_ENABLE 0x00000002 990 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 991 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 992 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 993 994 /* Receive Data and Receive BD Initiator Status register */ 995 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 996 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 997 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 998 999 1000 /* 1001 * Receive Data Completion Control registers 1002 */ 1003 #define BGE_RDC_MODE 0x2800 1004 1005 /* Receive Data Completion Mode register */ 1006 #define BGE_RDCMODE_RESET 0x00000001 1007 #define BGE_RDCMODE_ENABLE 0x00000002 1008 #define BGE_RDCMODE_ATTN 0x00000004 1009 1010 /* 1011 * Receive BD Initiator Control registers 1012 */ 1013 #define BGE_RBDI_MODE 0x2C00 1014 #define BGE_RBDI_STATUS 0x2C04 1015 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1016 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1017 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1018 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1019 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1020 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1021 1022 /* Receive BD Initiator Mode register */ 1023 #define BGE_RBDIMODE_RESET 0x00000001 1024 #define BGE_RBDIMODE_ENABLE 0x00000002 1025 #define BGE_RBDIMODE_ATTN 0x00000004 1026 1027 /* Receive BD Initiator Status register */ 1028 #define BGE_RBDISTAT_ATTN 0x00000004 1029 1030 /* 1031 * Receive BD Completion Control registers 1032 */ 1033 #define BGE_RBDC_MODE 0x3000 1034 #define BGE_RBDC_STATUS 0x3004 1035 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1036 #define BGE_RBDC_STD_BD_PROD 0x300C 1037 #define BGE_RBDC_MINI_BD_PROD 0x3010 1038 1039 /* Receive BD completion mode register */ 1040 #define BGE_RBDCMODE_RESET 0x00000001 1041 #define BGE_RBDCMODE_ENABLE 0x00000002 1042 #define BGE_RBDCMODE_ATTN 0x00000004 1043 1044 /* Receive BD completion status register */ 1045 #define BGE_RBDCSTAT_ERROR 0x00000004 1046 1047 /* 1048 * Receive List Selector Control registers 1049 */ 1050 #define BGE_RXLS_MODE 0x3400 1051 #define BGE_RXLS_STATUS 0x3404 1052 1053 /* Receive List Selector Mode register */ 1054 #define BGE_RXLSMODE_RESET 0x00000001 1055 #define BGE_RXLSMODE_ENABLE 0x00000002 1056 #define BGE_RXLSMODE_ATTN 0x00000004 1057 1058 /* Receive List Selector Status register */ 1059 #define BGE_RXLSSTAT_ERROR 0x00000004 1060 1061 /* 1062 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1063 */ 1064 #define BGE_MBCF_MODE 0x3800 1065 #define BGE_MBCF_STATUS 0x3804 1066 1067 /* Mbuf Cluster Free mode register */ 1068 #define BGE_MBCFMODE_RESET 0x00000001 1069 #define BGE_MBCFMODE_ENABLE 0x00000002 1070 #define BGE_MBCFMODE_ATTN 0x00000004 1071 1072 /* Mbuf Cluster Free status register */ 1073 #define BGE_MBCFSTAT_ERROR 0x00000004 1074 1075 /* 1076 * Host Coalescing Control registers 1077 */ 1078 #define BGE_HCC_MODE 0x3C00 1079 #define BGE_HCC_STATUS 0x3C04 1080 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1081 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1082 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1083 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1084 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1085 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1086 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1087 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1088 #define BGE_HCC_STATS_TICKS 0x3C28 1089 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1090 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1091 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1092 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1093 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1094 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1095 #define BGE_FLOW_ATTN 0x3C48 1096 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1097 #define BGE_HCC_STD_BD_CONS 0x3C54 1098 #define BGE_HCC_MINI_BD_CONS 0x3C58 1099 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1100 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1101 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1102 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1103 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1104 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1105 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1106 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1107 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1108 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1109 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1110 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1111 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1112 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1113 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1114 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1115 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1116 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1117 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1118 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1119 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1120 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1121 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1122 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1123 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1124 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1125 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1126 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1127 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1128 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1129 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1130 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1131 1132 1133 /* Host coalescing mode register */ 1134 #define BGE_HCCMODE_RESET 0x00000001 1135 #define BGE_HCCMODE_ENABLE 0x00000002 1136 #define BGE_HCCMODE_ATTN 0x00000004 1137 #define BGE_HCCMODE_COAL_NOW 0x00000008 1138 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1139 #define BGE_HCCMODE_64BYTE 0x00000080 1140 #define BGE_HCCMODE_32BYTE 0x00000100 1141 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1142 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1143 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1144 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1145 1146 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1147 1148 #define BGE_STATBLKSZ_FULL 0x00000000 1149 #define BGE_STATBLKSZ_64BYTE 0x00000080 1150 #define BGE_STATBLKSZ_32BYTE 0x00000100 1151 1152 /* Host coalescing status register */ 1153 #define BGE_HCCSTAT_ERROR 0x00000004 1154 1155 /* Flow attention register */ 1156 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1157 #define BGE_FLOWATTN_MEMARB 0x00000080 1158 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1159 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1160 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1161 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1162 #define BGE_FLOWATTN_RDBDI 0x00080000 1163 #define BGE_FLOWATTN_RXLS 0x00100000 1164 #define BGE_FLOWATTN_RXLP 0x00200000 1165 #define BGE_FLOWATTN_RBDC 0x00400000 1166 #define BGE_FLOWATTN_RBDI 0x00800000 1167 #define BGE_FLOWATTN_SDC 0x08000000 1168 #define BGE_FLOWATTN_SDI 0x10000000 1169 #define BGE_FLOWATTN_SRS 0x20000000 1170 #define BGE_FLOWATTN_SBDC 0x40000000 1171 #define BGE_FLOWATTN_SBDI 0x80000000 1172 1173 /* 1174 * Memory arbiter registers 1175 */ 1176 #define BGE_MARB_MODE 0x4000 1177 #define BGE_MARB_STATUS 0x4004 1178 #define BGE_MARB_TRAPADDR_HI 0x4008 1179 #define BGE_MARB_TRAPADDR_LO 0x400C 1180 1181 /* Memory arbiter mode register */ 1182 #define BGE_MARBMODE_RESET 0x00000001 1183 #define BGE_MARBMODE_ENABLE 0x00000002 1184 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1185 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1186 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1187 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1188 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1189 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1190 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1191 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1192 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1193 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1194 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1195 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1196 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1197 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1198 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1199 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1200 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1201 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1202 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1203 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1204 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1205 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1206 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1207 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1208 1209 /* Memory arbiter status register */ 1210 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1211 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1212 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1213 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1214 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1215 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1216 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1217 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1218 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1219 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1220 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1221 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1222 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1223 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1224 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1225 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1226 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1227 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1228 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1229 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1230 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1231 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1232 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1233 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1234 1235 /* 1236 * Buffer manager control registers 1237 */ 1238 #define BGE_BMAN_MODE 0x4400 1239 #define BGE_BMAN_STATUS 0x4404 1240 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1241 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1242 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1243 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1244 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1245 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1246 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1247 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1248 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1249 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1250 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1251 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1252 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1253 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1254 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1255 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1256 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1257 #define BGE_BMAN_HWDIAG_1 0x444C 1258 #define BGE_BMAN_HWDIAG_2 0x4450 1259 #define BGE_BMAN_HWDIAG_3 0x4454 1260 1261 /* Buffer manager mode register */ 1262 #define BGE_BMANMODE_RESET 0x00000001 1263 #define BGE_BMANMODE_ENABLE 0x00000002 1264 #define BGE_BMANMODE_ATTN 0x00000004 1265 #define BGE_BMANMODE_TESTMODE 0x00000008 1266 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1267 1268 /* Buffer manager status register */ 1269 #define BGE_BMANSTAT_ERRO 0x00000004 1270 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1271 1272 1273 /* 1274 * Read DMA Control registers 1275 */ 1276 #define BGE_RDMA_MODE 0x4800 1277 #define BGE_RDMA_STATUS 0x4804 1278 1279 /* Read DMA mode register */ 1280 #define BGE_RDMAMODE_RESET 0x00000001 1281 #define BGE_RDMAMODE_ENABLE 0x00000002 1282 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1283 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1284 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1285 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1286 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1287 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1288 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1289 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1290 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1291 1292 /* Read DMA status register */ 1293 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1294 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1295 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1296 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1297 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1298 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1299 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1300 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1301 1302 /* 1303 * Write DMA control registers 1304 */ 1305 #define BGE_WDMA_MODE 0x4C00 1306 #define BGE_WDMA_STATUS 0x4C04 1307 1308 /* Write DMA mode register */ 1309 #define BGE_WDMAMODE_RESET 0x00000001 1310 #define BGE_WDMAMODE_ENABLE 0x00000002 1311 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1312 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1313 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1314 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1315 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1316 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1317 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1318 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1319 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1320 1321 /* Write DMA status register */ 1322 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1323 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1324 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1325 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1326 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1327 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1328 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1329 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1330 1331 1332 /* 1333 * RX CPU registers 1334 */ 1335 #define BGE_RXCPU_MODE 0x5000 1336 #define BGE_RXCPU_STATUS 0x5004 1337 #define BGE_RXCPU_PC 0x501C 1338 1339 /* RX CPU mode register */ 1340 #define BGE_RXCPUMODE_RESET 0x00000001 1341 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1342 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1343 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1344 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1345 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1346 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1347 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1348 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1349 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1350 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1351 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1352 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1353 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1354 1355 /* RX CPU status register */ 1356 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1357 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1358 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1359 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1360 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1361 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1362 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1363 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1364 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1365 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1366 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1367 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1368 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1369 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1370 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1371 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1372 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1373 1374 1375 /* 1376 * TX CPU registers 1377 */ 1378 #define BGE_TXCPU_MODE 0x5400 1379 #define BGE_TXCPU_STATUS 0x5404 1380 #define BGE_TXCPU_PC 0x541C 1381 1382 /* TX CPU mode register */ 1383 #define BGE_TXCPUMODE_RESET 0x00000001 1384 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1385 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1386 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1387 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1388 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1389 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1390 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1391 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1392 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1393 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1394 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1395 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1396 1397 /* TX CPU status register */ 1398 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1399 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1400 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1401 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1402 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1403 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1404 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1405 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1406 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1407 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1408 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1409 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1410 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1411 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1412 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1413 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1414 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1415 1416 1417 /* 1418 * Low priority mailbox registers 1419 */ 1420 #define BGE_LPMBX_IRQ0_HI 0x5800 1421 #define BGE_LPMBX_IRQ0_LO 0x5804 1422 #define BGE_LPMBX_IRQ1_HI 0x5808 1423 #define BGE_LPMBX_IRQ1_LO 0x580C 1424 #define BGE_LPMBX_IRQ2_HI 0x5810 1425 #define BGE_LPMBX_IRQ2_LO 0x5814 1426 #define BGE_LPMBX_IRQ3_HI 0x5818 1427 #define BGE_LPMBX_IRQ3_LO 0x581C 1428 #define BGE_LPMBX_GEN0_HI 0x5820 1429 #define BGE_LPMBX_GEN0_LO 0x5824 1430 #define BGE_LPMBX_GEN1_HI 0x5828 1431 #define BGE_LPMBX_GEN1_LO 0x582C 1432 #define BGE_LPMBX_GEN2_HI 0x5830 1433 #define BGE_LPMBX_GEN2_LO 0x5834 1434 #define BGE_LPMBX_GEN3_HI 0x5828 1435 #define BGE_LPMBX_GEN3_LO 0x582C 1436 #define BGE_LPMBX_GEN4_HI 0x5840 1437 #define BGE_LPMBX_GEN4_LO 0x5844 1438 #define BGE_LPMBX_GEN5_HI 0x5848 1439 #define BGE_LPMBX_GEN5_LO 0x584C 1440 #define BGE_LPMBX_GEN6_HI 0x5850 1441 #define BGE_LPMBX_GEN6_LO 0x5854 1442 #define BGE_LPMBX_GEN7_HI 0x5858 1443 #define BGE_LPMBX_GEN7_LO 0x585C 1444 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1445 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1446 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1447 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1448 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1449 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1450 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1451 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1452 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1453 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1454 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1455 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1456 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1457 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1458 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1459 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1460 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1461 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1462 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1463 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1464 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1465 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1466 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1467 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1468 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1469 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1470 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1471 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1472 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1473 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1474 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1475 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1476 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1477 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1478 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1479 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1480 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1481 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1482 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1483 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1484 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1485 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1486 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1487 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1488 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1489 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1490 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1491 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1492 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1493 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1494 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1495 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1496 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1497 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1498 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1499 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1500 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1501 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1502 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1503 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1504 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1505 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1506 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1507 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1508 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1509 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1510 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1511 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1512 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1513 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1514 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1515 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1516 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1517 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1518 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1519 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1520 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1521 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1522 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1523 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1524 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1525 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1526 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1527 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1528 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1529 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1530 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1531 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1532 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1533 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1534 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1535 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1536 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1537 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1538 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1539 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1540 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1541 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1542 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1543 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1544 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1545 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1546 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1547 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1548 1549 /* 1550 * Flow throw Queue reset register 1551 */ 1552 #define BGE_FTQ_RESET 0x5C00 1553 1554 #define BGE_FTQRESET_DMAREAD 0x00000002 1555 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1556 #define BGE_FTQRESET_DMADONE 0x00000010 1557 #define BGE_FTQRESET_SBDC 0x00000020 1558 #define BGE_FTQRESET_SDI 0x00000040 1559 #define BGE_FTQRESET_WDMA 0x00000080 1560 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1561 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1562 #define BGE_FTQRESET_SDC 0x00000400 1563 #define BGE_FTQRESET_HCC 0x00000800 1564 #define BGE_FTQRESET_TXFIFO 0x00001000 1565 #define BGE_FTQRESET_MBC 0x00002000 1566 #define BGE_FTQRESET_RBDC 0x00004000 1567 #define BGE_FTQRESET_RXLP 0x00008000 1568 #define BGE_FTQRESET_RDBDI 0x00010000 1569 #define BGE_FTQRESET_RDC 0x00020000 1570 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1571 1572 /* 1573 * Message Signaled Interrupt registers 1574 */ 1575 #define BGE_MSI_MODE 0x6000 1576 #define BGE_MSI_STATUS 0x6004 1577 #define BGE_MSI_FIFOACCESS 0x6008 1578 1579 /* MSI mode register */ 1580 #define BGE_MSIMODE_RESET 0x00000001 1581 #define BGE_MSIMODE_ENABLE 0x00000002 1582 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1583 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1584 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1585 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1586 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1587 1588 /* MSI status register */ 1589 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1590 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1591 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1592 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1593 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1594 1595 1596 /* 1597 * DMA Completion registers 1598 */ 1599 #define BGE_DMAC_MODE 0x6400 1600 1601 /* DMA Completion mode register */ 1602 #define BGE_DMACMODE_RESET 0x00000001 1603 #define BGE_DMACMODE_ENABLE 0x00000002 1604 1605 1606 /* 1607 * General control registers. 1608 */ 1609 #define BGE_MODE_CTL 0x6800 1610 #define BGE_MISC_CFG 0x6804 1611 #define BGE_MISC_LOCAL_CTL 0x6808 1612 #define BGE_MISC_TIMER 0x680c 1613 #define BGE_EE_ADDR 0x6838 1614 #define BGE_EE_DATA 0x683C 1615 #define BGE_EE_CTL 0x6840 1616 #define BGE_MDI_CTL 0x6844 1617 #define BGE_EE_DELAY 0x6848 1618 /* 1619 * XXX: Those names are made up as I have no documentation about it; 1620 * I only know it is only used in the PCI-Express case. 1621 */ 1622 #define BGE_PCIE_CTL0 0x7c00 1623 #define BGE_PCIE_CTL1 0x7e2c 1624 1625 /* Mode control register */ 1626 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1627 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1628 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1629 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1630 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1631 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1632 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1633 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1634 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1635 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1636 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1637 #define BGE_MODECTL_STACKUP 0x00010000 1638 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1639 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1640 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1641 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1642 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1643 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1644 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1645 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1646 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1647 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1648 1649 /* Misc. config register */ 1650 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1651 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1652 1653 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1654 1655 /* Misc. Local Control */ 1656 #define BGE_MLC_INTR_STATE 0x00000001 1657 #define BGE_MLC_INTR_CLR 0x00000002 1658 #define BGE_MLC_INTR_SET 0x00000004 1659 #define BGE_MLC_INTR_ONATTN 0x00000008 1660 #define BGE_MLC_MISCIO_IN0 0x00000100 1661 #define BGE_MLC_MISCIO_IN1 0x00000200 1662 #define BGE_MLC_MISCIO_IN2 0x00000400 1663 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1664 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1665 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1666 #define BGE_MLC_MISCIO_OUT0 0x00004000 1667 #define BGE_MLC_MISCIO_OUT1 0x00008000 1668 #define BGE_MLC_MISCIO_OUT2 0x00010000 1669 #define BGE_MLC_EXTRAM_ENB 0x00020000 1670 #define BGE_MLC_SRAM_SIZE 0x001C0000 1671 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1672 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1673 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1674 #define BGE_MLC_AUTO_EEPROM 0x01000000 1675 1676 #define BGE_SSRAMSIZE_256KB 0x00000000 1677 #define BGE_SSRAMSIZE_512KB 0x00040000 1678 #define BGE_SSRAMSIZE_1MB 0x00080000 1679 #define BGE_SSRAMSIZE_2MB 0x000C0000 1680 #define BGE_SSRAMSIZE_4MB 0x00100000 1681 #define BGE_SSRAMSIZE_8MB 0x00140000 1682 #define BGE_SSRAMSIZE_16M 0x00180000 1683 1684 /* EEPROM address register */ 1685 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1686 #define BGE_EEADDR_HALFCLK 0x01FF0000 1687 #define BGE_EEADDR_START 0x02000000 1688 #define BGE_EEADDR_DEVID 0x1C000000 1689 #define BGE_EEADDR_RESET 0x20000000 1690 #define BGE_EEADDR_DONE 0x40000000 1691 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1692 1693 #define BGE_EEDEVID(x) ((x & 7) << 26) 1694 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1695 #define BGE_HALFCLK_384SCL 0x60 1696 #define BGE_EE_READCMD \ 1697 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1698 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1699 #define BGE_EE_WRCMD \ 1700 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1701 BGE_EEADDR_START|BGE_EEADDR_DONE) 1702 1703 /* EEPROM Control register */ 1704 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1705 #define BGE_EECTL_CLKOUT 0x00000002 1706 #define BGE_EECTL_CLKIN 0x00000004 1707 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1708 #define BGE_EECTL_DATAOUT 0x00000010 1709 #define BGE_EECTL_DATAIN 0x00000020 1710 1711 /* MDI (MII/GMII) access register */ 1712 #define BGE_MDI_DATA 0x00000001 1713 #define BGE_MDI_DIR 0x00000002 1714 #define BGE_MDI_SEL 0x00000004 1715 #define BGE_MDI_CLK 0x00000008 1716 1717 #define BGE_MEMWIN_START 0x00008000 1718 #define BGE_MEMWIN_END 0x0000FFFF 1719 1720 1721 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1722 do { \ 1723 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1724 (0xFFFF0000 & x)); \ 1725 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1726 } while(0) 1727 1728 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1729 do { \ 1730 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1731 (0xFFFF0000 & x)); \ 1732 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1733 } while(0) 1734 1735 /* 1736 * This magic number is used to prevent PXE restart when we 1737 * issue a software reset. We write this magic number to the 1738 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1739 * code from running. 1740 */ 1741 #define BGE_MAGIC_NUMBER 0x4B657654 1742 1743 #if BYTE_ORDER == LITTLE_ENDIAN 1744 typedef struct { 1745 u_int32_t bge_addr_hi; 1746 u_int32_t bge_addr_lo; 1747 } bge_hostaddr; 1748 #else 1749 typedef struct { 1750 u_int32_t bge_addr_hi; 1751 u_int32_t bge_addr_lo; 1752 } bge_hostaddr; 1753 #endif 1754 1755 static __inline void 1756 bge_set_hostaddr(volatile bge_hostaddr *x, bus_addr_t y) 1757 { 1758 x->bge_addr_lo = y & 0xffffffff; 1759 if (sizeof (bus_addr_t) == 8) 1760 x->bge_addr_hi = (u_int64_t)y >> 32; 1761 else 1762 x->bge_addr_hi = 0; 1763 } 1764 1765 /* Ring control block structure */ 1766 struct bge_rcb { 1767 bge_hostaddr bge_hostaddr; 1768 u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 1769 u_int32_t bge_nicaddr; 1770 }; 1771 1772 #if BYTE_ORDER == BIG_ENDIAN 1773 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((flags) << 16 | (maxlen)) 1774 #else 1775 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1776 #endif 1777 1778 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1779 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1780 rcb + offsetof(struct bge_rcb, offset), val) 1781 1782 1783 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1784 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1785 1786 struct bge_tx_bd { 1787 bge_hostaddr bge_addr; 1788 #if BYTE_ORDER == BIG_ENDIAN 1789 u_int16_t bge_len; 1790 u_int16_t bge_flags; 1791 u_int16_t bge_rsvd; 1792 u_int16_t bge_vlan_tag; 1793 #else 1794 u_int16_t bge_flags; 1795 u_int16_t bge_len; 1796 u_int16_t bge_vlan_tag; 1797 u_int16_t bge_rsvd; 1798 #endif 1799 }; 1800 1801 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1802 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1803 #define BGE_TXBDFLAG_END 0x0004 1804 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1805 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1806 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1807 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1808 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1809 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1810 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1811 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1812 #define BGE_TXBDFLAG_NO_CRC 0x8000 1813 1814 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1815 BGE_SEND_RING_1_TO_4 + \ 1816 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1817 1818 struct bge_rx_bd { 1819 bge_hostaddr bge_addr; 1820 #if BYTE_ORDER == BIG_ENDIAN 1821 u_int16_t bge_idx; 1822 u_int16_t bge_len; 1823 u_int16_t bge_type; 1824 u_int16_t bge_flags; 1825 u_int16_t bge_ip_csum; 1826 u_int16_t bge_tcp_udp_csum; 1827 u_int16_t bge_error_flag; 1828 u_int16_t bge_vlan_tag; 1829 #else 1830 u_int16_t bge_len; 1831 u_int16_t bge_idx; 1832 u_int16_t bge_flags; 1833 u_int16_t bge_type; 1834 u_int16_t bge_tcp_udp_csum; 1835 u_int16_t bge_ip_csum; 1836 u_int16_t bge_vlan_tag; 1837 u_int16_t bge_error_flag; 1838 #endif 1839 u_int32_t bge_rsvd; 1840 u_int32_t bge_opaque; 1841 }; 1842 1843 #define BGE_RXBDFLAG_END 0x0004 1844 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1845 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1846 #define BGE_RXBDFLAG_ERROR 0x0400 1847 #define BGE_RXBDFLAG_MINI_RING 0x0800 1848 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1849 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1850 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1851 1852 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1853 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1854 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1855 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1856 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1857 #define BGE_RXERRFLAG_RUNT 0x0020 1858 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1859 #define BGE_RXERRFLAG_GIANT 0x0080 1860 1861 struct bge_sts_idx { 1862 #if BYTE_ORDER == BIG_ENDIAN 1863 u_int16_t bge_tx_cons_idx; 1864 u_int16_t bge_rx_prod_idx; 1865 #else 1866 u_int16_t bge_rx_prod_idx; 1867 u_int16_t bge_tx_cons_idx; 1868 #endif 1869 }; 1870 1871 struct bge_status_block { 1872 u_int32_t bge_status; 1873 u_int32_t bge_rsvd0; 1874 #if BYTE_ORDER == BIG_ENDIAN 1875 u_int16_t bge_rx_std_cons_idx; 1876 u_int16_t bge_rx_jumbo_cons_idx; 1877 u_int16_t bge_rsvd1; 1878 u_int16_t bge_rx_mini_cons_idx; 1879 #else 1880 u_int16_t bge_rx_jumbo_cons_idx; 1881 u_int16_t bge_rx_std_cons_idx; 1882 u_int16_t bge_rx_mini_cons_idx; 1883 u_int16_t bge_rsvd1; 1884 #endif 1885 struct bge_sts_idx bge_idx[16]; 1886 }; 1887 1888 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1889 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1890 1891 #define BGE_STATFLAG_UPDATED 0x00000001 1892 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1893 #define BGE_STATFLAG_ERROR 0x00000004 1894 1895 1896 /* 1897 * Broadcom Vendor ID 1898 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1899 * even though they're now manufactured by Broadcom) 1900 */ 1901 #define BCOM_VENDORID 0x14E4 1902 #define BCOM_DEVICEID_BCM5700 0x1644 1903 #define BCOM_DEVICEID_BCM5701 0x1645 1904 1905 /* 1906 * Alteon AceNIC PCI vendor/device ID. 1907 */ 1908 #define ALT_VENDORID 0x12AE 1909 #define ALT_DEVICEID_ACENIC 0x0001 1910 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 1911 #define ALT_DEVICEID_BCM5700 0x0003 1912 #define ALT_DEVICEID_BCM5701 0x0004 1913 1914 /* 1915 * 3Com 3c985 PCI vendor/device ID. 1916 */ 1917 #define TC_VENDORID 0x10B7 1918 #define TC_DEVICEID_3C985 0x0001 1919 #define TC_DEVICEID_3C996 0x0003 1920 1921 /* 1922 * SysKonnect PCI vendor ID 1923 */ 1924 #define SK_VENDORID 0x1148 1925 #define SK_DEVICEID_ALTIMA 0x4400 1926 #define SK_SUBSYSID_9D21 0x4421 1927 #define SK_SUBSYSID_9D41 0x4441 1928 1929 /* 1930 * Altima PCI vendor/device ID. 1931 */ 1932 #define ALTIMA_VENDORID 0x173b 1933 #define ALTIMA_DEVICE_AC1000 0x03e8 1934 1935 /* 1936 * Offset of MAC address inside EEPROM. 1937 */ 1938 #define BGE_EE_MAC_OFFSET 0x7C 1939 #define BGE_EE_HWCFG_OFFSET 0xC8 1940 1941 #define BGE_HWCFG_VOLTAGE 0x00000003 1942 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1943 #define BGE_HWCFG_MEDIA 0x00000030 1944 1945 #define BGE_VOLTAGE_1POINT3 0x00000000 1946 #define BGE_VOLTAGE_1POINT8 0x00000001 1947 1948 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 1949 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1950 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 1951 1952 #define BGE_MEDIA_UNSPEC 0x00000000 1953 #define BGE_MEDIA_COPPER 0x00000010 1954 #define BGE_MEDIA_FIBER 0x00000020 1955 1956 #define BGE_PCI_READ_CMD 0x06000000 1957 #define BGE_PCI_WRITE_CMD 0x70000000 1958 1959 #define BGE_TICKS_PER_SEC 1000000 1960 1961 /* 1962 * Ring size constants. 1963 */ 1964 #define BGE_EVENT_RING_CNT 256 1965 #define BGE_CMD_RING_CNT 64 1966 #define BGE_STD_RX_RING_CNT 512 1967 #define BGE_JUMBO_RX_RING_CNT 256 1968 #define BGE_MINI_RX_RING_CNT 1024 1969 #define BGE_RETURN_RING_CNT 1024 1970 #define BGE_RETURN_RING_CNT_5705 512 1971 1972 /* 1973 * Possible TX ring sizes. 1974 */ 1975 #define BGE_TX_RING_CNT_128 128 1976 #define BGE_TX_RING_BASE_128 0x3800 1977 1978 #define BGE_TX_RING_CNT_256 256 1979 #define BGE_TX_RING_BASE_256 0x3000 1980 1981 #define BGE_TX_RING_CNT_512 512 1982 #define BGE_TX_RING_BASE_512 0x2000 1983 1984 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1985 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1986 1987 /* 1988 * Tigon III statistics counters. 1989 */ 1990 1991 /* Stats counters access through registers */ 1992 struct bge_mac_stats_regs { 1993 u_int32_t ifHCOutOctets; 1994 u_int32_t Reserved0; 1995 u_int32_t etherStatsCollisions; 1996 u_int32_t outXonSent; 1997 u_int32_t outXoffSent; 1998 u_int32_t Reserved1; 1999 u_int32_t dot3StatsInternalMacTransmitErrors; 2000 u_int32_t dot3StatsSingleCollisionFrames; 2001 u_int32_t dot3StatsMultipleCollisionFrames; 2002 u_int32_t dot3StatsDeferredTransmissions; 2003 u_int32_t Reserved2; 2004 u_int32_t dot3StatsExcessiveCollisions; 2005 u_int32_t dot3StatsLateCollisions; 2006 u_int32_t Reserved3[14]; 2007 u_int32_t ifHCOutUcastPkts; 2008 u_int32_t ifHCOutMulticastPkts; 2009 u_int32_t ifHCOutBroadcastPkts; 2010 u_int32_t Reserved4[2]; 2011 u_int32_t ifHCInOctets; 2012 u_int32_t Reserved5; 2013 u_int32_t etherStatsFragments; 2014 u_int32_t ifHCInUcastPkts; 2015 u_int32_t ifHCInMulticastPkts; 2016 u_int32_t ifHCInBroadcastPkts; 2017 u_int32_t dot3StatsFCSErrors; 2018 u_int32_t dot3StatsAlignmentErrors; 2019 u_int32_t xonPauseFramesReceived; 2020 u_int32_t xoffPauseFramesReceived; 2021 u_int32_t macControlFramesReceived; 2022 u_int32_t xoffStateEntered; 2023 u_int32_t dot3StatsFramesTooLong; 2024 u_int32_t etherStatsJabbers; 2025 u_int32_t etherStatsUndersizePkts; 2026 }; 2027 2028 struct bge_stats { 2029 u_int8_t Reserved0[256]; 2030 2031 /* Statistics maintained by Receive MAC. */ 2032 bge_hostaddr ifHCInOctets; 2033 bge_hostaddr Reserved1; 2034 bge_hostaddr etherStatsFragments; 2035 bge_hostaddr ifHCInUcastPkts; 2036 bge_hostaddr ifHCInMulticastPkts; 2037 bge_hostaddr ifHCInBroadcastPkts; 2038 bge_hostaddr dot3StatsFCSErrors; 2039 bge_hostaddr dot3StatsAlignmentErrors; 2040 bge_hostaddr xonPauseFramesReceived; 2041 bge_hostaddr xoffPauseFramesReceived; 2042 bge_hostaddr macControlFramesReceived; 2043 bge_hostaddr xoffStateEntered; 2044 bge_hostaddr dot3StatsFramesTooLong; 2045 bge_hostaddr etherStatsJabbers; 2046 bge_hostaddr etherStatsUndersizePkts; 2047 bge_hostaddr inRangeLengthError; 2048 bge_hostaddr outRangeLengthError; 2049 bge_hostaddr etherStatsPkts64Octets; 2050 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2051 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2052 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2053 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2054 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2055 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2056 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2057 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2058 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2059 2060 bge_hostaddr Unused1[37]; 2061 2062 /* Statistics maintained by Transmit MAC. */ 2063 bge_hostaddr ifHCOutOctets; 2064 bge_hostaddr Reserved2; 2065 bge_hostaddr etherStatsCollisions; 2066 bge_hostaddr outXonSent; 2067 bge_hostaddr outXoffSent; 2068 bge_hostaddr flowControlDone; 2069 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2070 bge_hostaddr dot3StatsSingleCollisionFrames; 2071 bge_hostaddr dot3StatsMultipleCollisionFrames; 2072 bge_hostaddr dot3StatsDeferredTransmissions; 2073 bge_hostaddr Reserved3; 2074 bge_hostaddr dot3StatsExcessiveCollisions; 2075 bge_hostaddr dot3StatsLateCollisions; 2076 bge_hostaddr dot3Collided2Times; 2077 bge_hostaddr dot3Collided3Times; 2078 bge_hostaddr dot3Collided4Times; 2079 bge_hostaddr dot3Collided5Times; 2080 bge_hostaddr dot3Collided6Times; 2081 bge_hostaddr dot3Collided7Times; 2082 bge_hostaddr dot3Collided8Times; 2083 bge_hostaddr dot3Collided9Times; 2084 bge_hostaddr dot3Collided10Times; 2085 bge_hostaddr dot3Collided11Times; 2086 bge_hostaddr dot3Collided12Times; 2087 bge_hostaddr dot3Collided13Times; 2088 bge_hostaddr dot3Collided14Times; 2089 bge_hostaddr dot3Collided15Times; 2090 bge_hostaddr ifHCOutUcastPkts; 2091 bge_hostaddr ifHCOutMulticastPkts; 2092 bge_hostaddr ifHCOutBroadcastPkts; 2093 bge_hostaddr dot3StatsCarrierSenseErrors; 2094 bge_hostaddr ifOutDiscards; 2095 bge_hostaddr ifOutErrors; 2096 2097 bge_hostaddr Unused2[31]; 2098 2099 /* Statistics maintained by Receive List Placement. */ 2100 bge_hostaddr COSIfHCInPkts[16]; 2101 bge_hostaddr COSFramesDroppedDueToFilters; 2102 bge_hostaddr nicDmaWriteQueueFull; 2103 bge_hostaddr nicDmaWriteHighPriQueueFull; 2104 bge_hostaddr nicNoMoreRxBDs; 2105 bge_hostaddr ifInDiscards; 2106 bge_hostaddr ifInErrors; 2107 bge_hostaddr nicRecvThresholdHit; 2108 2109 bge_hostaddr Unused3[9]; 2110 2111 /* Statistics maintained by Send Data Initiator. */ 2112 bge_hostaddr COSIfHCOutPkts[16]; 2113 bge_hostaddr nicDmaReadQueueFull; 2114 bge_hostaddr nicDmaReadHighPriQueueFull; 2115 bge_hostaddr nicSendDataCompQueueFull; 2116 2117 /* Statistics maintained by Host Coalescing. */ 2118 bge_hostaddr nicRingSetSendProdIndex; 2119 bge_hostaddr nicRingStatusUpdate; 2120 bge_hostaddr nicInterrupts; 2121 bge_hostaddr nicAvoidedInterrupts; 2122 bge_hostaddr nicSendThresholdHit; 2123 2124 u_int8_t Reserved4[320]; 2125 }; 2126 2127 /* 2128 * Tigon general information block. This resides in host memory 2129 * and contains the status counters, ring control blocks and 2130 * producer pointers. 2131 */ 2132 2133 struct bge_gib { 2134 struct bge_stats bge_stats; 2135 struct bge_rcb bge_tx_rcb[16]; 2136 struct bge_rcb bge_std_rx_rcb; 2137 struct bge_rcb bge_jumbo_rx_rcb; 2138 struct bge_rcb bge_mini_rx_rcb; 2139 struct bge_rcb bge_return_rcb; 2140 }; 2141 2142 /* 2143 * NOTE! On the Alpha, we have an alignment constraint. 2144 * The first thing in the packet is a 14-byte Ethernet header. 2145 * This means that the packet is misaligned. To compensate, 2146 * we actually offset the data 2 bytes into the cluster. This 2147 * alignes the packet after the Ethernet header at a 32-bit 2148 * boundary. 2149 */ 2150 2151 #define ETHER_ALIGN 2 2152 2153 #define BGE_FRAMELEN ETHER_MAX_LEN 2154 #define BGE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_CRC_LEN) 2155 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2156 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2157 #define BGE_PAGE_SIZE PAGE_SIZE 2158 #define BGE_MIN_FRAMELEN 60 2159 2160 /* 2161 * Other utility macros. 2162 */ 2163 #define BGE_INC(x, y) (x) = (x + 1) % y 2164 2165 /* 2166 * Vital product data and structures. 2167 */ 2168 #define BGE_VPD_FLAG 0x8000 2169 2170 /* VPD structures */ 2171 struct vpd_res { 2172 u_int8_t vr_id; 2173 u_int8_t vr_len; 2174 u_int8_t vr_pad; 2175 }; 2176 2177 struct vpd_key { 2178 char vk_key[2]; 2179 u_int8_t vk_len; 2180 }; 2181 2182 #define VPD_RES_ID 0x82 /* ID string */ 2183 #define VPD_RES_READ 0x90 /* start of read only area */ 2184 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2185 #define VPD_RES_END 0x78 /* end tag */ 2186 2187 2188 /* 2189 * Register access macros. The Tigon always uses memory mapped register 2190 * accesses and all registers must be accessed with 32 bit operations. 2191 */ 2192 2193 #define CSR_WRITE_4(sc, reg, val) \ 2194 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2195 2196 #define CSR_READ_4(sc, reg) \ 2197 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2198 2199 #define BGE_SETBIT(sc, reg, x) \ 2200 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2201 #define BGE_CLRBIT(sc, reg, x) \ 2202 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2203 2204 #define PCI_SETBIT(pc, tag, reg, x) \ 2205 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 2206 #define PCI_CLRBIT(pc, tag, reg, x) \ 2207 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 2208 2209 /* 2210 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2211 * values are tuneable. They control the actual amount of buffers 2212 * allocated for the standard, mini and jumbo receive rings. 2213 */ 2214 2215 #define BGE_SSLOTS 256 2216 #define BGE_MSLOTS 256 2217 #define BGE_JSLOTS 384 2218 #define BGE_RSLOTS 256 2219 2220 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2221 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2222 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2223 #define BGE_JPAGESZ PAGE_SIZE 2224 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2225 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2226 2227 /* 2228 * Ring structures. Most of these reside in host memory and we tell 2229 * the NIC where they are via the ring control blocks. The exceptions 2230 * are the tx and command rings, which live in NIC memory and which 2231 * we access via the shared memory window. 2232 */ 2233 struct bge_ring_data { 2234 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2235 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2236 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2237 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2238 struct bge_status_block bge_status_block; 2239 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2240 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2241 struct bge_gib bge_info; 2242 }; 2243 2244 #define BGE_RING_DMA_ADDR(sc, offset) \ 2245 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2246 offsetof(struct bge_ring_data, offset)) 2247 2248 /* 2249 * Number of DMA segments in a TxCB. Note that this is carefully 2250 * chosen to make the total struct size an even power of two. It's 2251 * critical that no TxCB be split across a page boundary since 2252 * no attempt is made to allocate physically contiguous memory. 2253 * 2254 */ 2255 #ifdef _LP64 2256 #define BGE_NTXSEG 30 2257 #else 2258 #define BGE_NTXSEG 31 2259 #endif 2260 2261 /* 2262 * Mbuf pointers. We need these to keep track of the virtual addresses 2263 * of our mbuf chains since we can only convert from physical to virtual, 2264 * not the other way around. 2265 */ 2266 struct bge_chain_data { 2267 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2268 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2269 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2270 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2271 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2272 bus_dmamap_t bge_rx_jumbo_map; 2273 /* Stick the jumbo mem management stuff here too. */ 2274 caddr_t bge_jslots[BGE_JSLOTS]; 2275 void *bge_jumbo_buf; 2276 }; 2277 2278 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 2279 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2280 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2281 2282 struct bge_type { 2283 u_int16_t bge_vid; 2284 u_int16_t bge_did; 2285 char *bge_name; 2286 }; 2287 2288 #define BGE_HWREV_TIGON 0x01 2289 #define BGE_HWREV_TIGON_II 0x02 2290 #define BGE_TIMEOUT 1000 2291 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2292 2293 struct bge_jpool_entry { 2294 int slot; 2295 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2296 }; 2297 2298 struct bge_bcom_hack { 2299 int reg; 2300 int val; 2301 }; 2302 2303 struct txdmamap_pool_entry { 2304 bus_dmamap_t dmamap; 2305 SLIST_ENTRY(txdmamap_pool_entry) link; 2306 }; 2307 2308 /* 2309 * Flags for bge_flags. 2310 */ 2311 #define BGE_TXRING_VALID 0x0001 2312 #define BGE_RXRING_VALID 0x0002 2313 #define BGE_JUMBO_RXRING_VALID 0x0004 2314 2315 struct bge_softc { 2316 struct device bge_dev; 2317 struct ethercom ethercom; /* interface info */ 2318 bus_space_handle_t bge_bhandle; 2319 bus_space_tag_t bge_btag; 2320 void *bge_intrhand; 2321 struct pci_attach_args bge_pa; 2322 struct mii_data bge_mii; 2323 struct ifmedia bge_ifmedia; /* media info */ 2324 u_int8_t bge_extram; /* has external SSRAM */ 2325 u_int8_t bge_tbi; 2326 u_int8_t bge_rx_alignment_bug; 2327 u_int8_t bge_pcie; /* on a PCI Express port */ 2328 u_int32_t bge_return_ring_cnt; 2329 u_int32_t bge_tx_prodidx; 2330 bus_dma_tag_t bge_dmatag; 2331 u_int32_t bge_chipid; 2332 u_int32_t bge_quirks; 2333 u_int32_t bge_local_ctrl_reg; 2334 struct bge_ring_data *bge_rdata; /* rings */ 2335 struct bge_chain_data bge_cdata; /* mbufs */ 2336 bus_dmamap_t bge_ring_map; 2337 u_int16_t bge_tx_saved_considx; 2338 u_int16_t bge_rx_saved_considx; 2339 u_int16_t bge_ev_saved_considx; 2340 u_int16_t bge_std; /* current std ring head */ 2341 u_int16_t bge_jumbo; /* current jumo ring head */ 2342 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2343 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2344 u_int32_t bge_stat_ticks; 2345 u_int32_t bge_rx_coal_ticks; 2346 u_int32_t bge_tx_coal_ticks; 2347 u_int32_t bge_rx_max_coal_bds; 2348 u_int32_t bge_tx_max_coal_bds; 2349 u_int32_t bge_tx_buf_ratio; 2350 int bge_if_flags; 2351 int bge_flags; 2352 int bge_flowflags; 2353 #ifdef BGE_EVENT_COUNTERS 2354 /* 2355 * Event counters. 2356 */ 2357 struct evcnt bge_ev_intr; /* interrupts */ 2358 struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ 2359 struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ 2360 struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ 2361 struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ 2362 struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ 2363 struct evcnt bge_ev_xoffentered;/* XOFF state entered */ 2364 #endif /* BGE_EVENT_COUNTERS */ 2365 int bge_txcnt; 2366 int bge_link; 2367 struct callout bge_timeout; 2368 char *bge_vpd_prodname; 2369 char *bge_vpd_readonly; 2370 int bge_pending_rxintr_change; 2371 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2372 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2373 void *bge_powerhook; 2374 struct pci_conf_state bge_pciconf; 2375 }; 2376
Indexes created Sun Sep 28 07:09:56 GMT 2025