if_bgereg.h revision 1.33
1 /* $NetBSD: if_bgereg.h,v 1.33 2006/02/16 20:17:19 perry Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79 #define BGE_UNMAPPED 0x00001000 80 #define BGE_UNMAPPED_END 0x00001FFF 81 #define BGE_DMA_DESCRIPTORS 0x00002000 82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83 #define BGE_SEND_RING_1_TO_4 0x00004000 84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86 /* Mappings for internal memory configuration */ 87 #define BGE_STD_RX_RINGS 0x00006000 88 #define BGE_STD_RX_RINGS_END 0x00006FFF 89 #define BGE_JUMBO_RX_RINGS 0x00007000 90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91 #define BGE_BUFFPOOL_1 0x00008000 92 #define BGE_BUFFPOOL_1_END 0x0000FFFF 93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_2_END 0x00017FFF 95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96 #define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98 /* Mappings for external SSRAM configurations */ 99 #define BGE_SEND_RING_5_TO_6 0x00006000 100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101 #define BGE_SEND_RING_7_TO_8 0x00007000 102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103 #define BGE_SEND_RING_9_TO_16 0x00008000 104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105 #define BGE_EXT_STD_RX_RINGS 0x0000C000 106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109 #define BGE_MINI_RX_RINGS 0x0000E000 110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION1_END 0x00017FFF 113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114 #define BGE_AVAIL_REGION2_END 0x0001FFFF 115 #define BGE_EXT_SSRAM 0x00020000 116 #define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119 /* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129 /* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132 #define BGE_PCI_VID 0x00 133 #define BGE_PCI_DID 0x02 134 #define BGE_PCI_CMD 0x04 135 #define BGE_PCI_STS 0x06 136 #define BGE_PCI_REV 0x08 137 #define BGE_PCI_CLASS 0x09 138 #define BGE_PCI_CACHESZ 0x0C 139 #define BGE_PCI_LATTIMER 0x0D 140 #define BGE_PCI_HDRTYPE 0x0E 141 #define BGE_PCI_BIST 0x0F 142 #define BGE_PCI_BAR0 0x10 143 #define BGE_PCI_BAR1 0x14 144 #define BGE_PCI_SUBSYS 0x2C 145 #define BGE_PCI_SUBVID 0x2E 146 #define BGE_PCI_ROMBASE 0x30 147 #define BGE_PCI_CAPPTR 0x34 148 #define BGE_PCI_INTLINE 0x3C 149 #define BGE_PCI_INTPIN 0x3D 150 #define BGE_PCI_MINGNT 0x3E 151 #define BGE_PCI_MAXLAT 0x3F 152 #define BGE_PCI_PCIXCAP 0x40 153 #define BGE_PCI_NEXTPTR_PM 0x41 154 #define BGE_PCI_PCIX_CMD 0x42 155 #define BGE_PCI_PCIX_STS 0x44 156 #define BGE_PCI_PWRMGMT_CAPID 0x48 157 #define BGE_PCI_NEXTPTR_VPD 0x49 158 #define BGE_PCI_PWRMGMT_CAPS 0x4A 159 #define BGE_PCI_PWRMGMT_CMD 0x4C 160 #define BGE_PCI_PWRMGMT_STS 0x4D 161 #define BGE_PCI_PWRMGMT_DATA 0x4F 162 #define BGE_PCI_VPD_CAPID 0x50 163 #define BGE_PCI_NEXTPTR_MSI 0x51 164 #define BGE_PCI_VPD_ADDR 0x52 165 #define BGE_PCI_VPD_DATA 0x54 166 #define BGE_PCI_MSI_CAPID 0x58 167 #define BGE_PCI_NEXTPTR_NONE 0x59 168 #define BGE_PCI_MSI_CTL 0x5A 169 #define BGE_PCI_MSI_ADDR_HI 0x5C 170 #define BGE_PCI_MSI_ADDR_LO 0x60 171 #define BGE_PCI_MSI_DATA 0x64 172 173 /* 174 * PCI registers specific to the BCM570x family. 175 */ 176 #define BGE_PCI_MISC_CTL 0x68 177 #define BGE_PCI_DMA_RW_CTL 0x6C 178 #define BGE_PCI_PCISTATE 0x70 179 #define BGE_PCI_CLKCTL 0x74 180 #define BGE_PCI_REG_BASEADDR 0x78 181 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 182 #define BGE_PCI_REG_DATA 0x80 183 #define BGE_PCI_MEMWIN_DATA 0x84 184 #define BGE_PCI_MODECTL 0x88 185 #define BGE_PCI_MISC_CFG 0x8C 186 #define BGE_PCI_MISC_LOCALCTL 0x90 187 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 188 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 189 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 190 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 191 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 192 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 193 #define BGE_PCI_ISR_MBX_HI 0xB0 194 #define BGE_PCI_ISR_MBX_LO 0xB4 195 196 #define BGE_PCI_UNKNOWN0 0xC4 197 /* XXX: 198 * Used in PCI-Express code for 575x chips. 199 * Should be replaced with checking for a PCI config-space 200 * capability for PCI-Express, and PCI-Express standard 201 * offsets into that capability block. 202 */ 203 #define BGE_PCI_CONF_DEV_CTRL 0xD8 204 #define BGE_PCI_CONF_DEV_STUS 0xDA 205 206 207 /* PCI Misc. Host control register */ 208 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 209 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 210 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 211 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 212 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 213 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 214 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 215 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 216 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 217 218 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 219 #if BYTE_ORDER == LITTLE_ENDIAN 220 #define BGE_DMA_SWAP_OPTIONS \ 221 BGE_MODECTL_WORDSWAP_NONFRAME| \ 222 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 223 #else 224 #define BGE_DMA_SWAP_OPTIONS \ 225 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 226 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 227 #endif 228 229 #define BGE_INIT \ 230 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 231 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 232 233 #define BGE_CHIPID_TIGON_I 0x40000000 234 #define BGE_CHIPID_TIGON_II 0x60000000 235 #define BGE_CHIPID_BCM5700_A0 0x70000000 236 #define BGE_CHIPID_BCM5700_A1 0x70010000 237 #define BGE_CHIPID_BCM5700_B0 0x71000000 238 #define BGE_CHIPID_BCM5700_B1 0x71020000 239 #define BGE_CHIPID_BCM5700_B2 0x71030000 240 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 241 #define BGE_CHIPID_BCM5700_C0 0x72000000 242 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 243 #define BGE_CHIPID_BCM5701_B0 0x01000000 244 #define BGE_CHIPID_BCM5701_B2 0x01020000 245 #define BGE_CHIPID_BCM5701_B5 0x01050000 246 #define BGE_CHIPID_BCM5703_A0 0x10000000 247 #define BGE_CHIPID_BCM5703_A1 0x10010000 248 #define BGE_CHIPID_BCM5703_A2 0x10020000 249 #define BGE_CHIPID_BCM5703_A3 0x11000000 250 #define BGE_CHIPID_BCM5704_A0 0x20000000 251 #define BGE_CHIPID_BCM5704_A1 0x20010000 252 #define BGE_CHIPID_BCM5704_A2 0x20020000 253 #define BGE_CHIPID_BCM5704_A3 0x20030000 254 #define BGE_CHIPID_BCM5705_A0 0x30000000 255 #define BGE_CHIPID_BCM5705_A1 0x30010000 256 #define BGE_CHIPID_BCM5705_A2 0x30020000 257 #define BGE_CHIPID_BCM5705_A3 0x30030000 258 #define BGE_CHIPID_BCM5750_A0 0x40000000 259 #define BGE_CHIPID_BCM5750_A1 0x40010000 260 #define BGE_CHIPID_BCM5751_A1 0x41010000 261 #define BGE_CHIPID_BCM5714_A0 0x50000000 262 #define BGE_CHIPID_BCM5715_xx 0x90010000 263 264 /* shorthand one */ 265 #define BGE_ASICREV(x) ((x) >> 28) 266 #define BGE_ASICREV_BCM5700 0x07 267 #define BGE_ASICREV_BCM5701 0x00 268 #define BGE_ASICREV_BCM5703 0x01 269 #define BGE_ASICREV_BCM5704 0x02 270 #define BGE_ASICREV_BCM5705 0x03 271 #define BGE_ASICREV_BCM5750 0x04 272 #define BGE_ASICREV_BCM5714 0x05 273 #define BGE_ASICREV_BCM5752 0x06 274 /* ASIC revision 0x07 is the original bcm5700 */ 275 #define BGE_ASICREV_BCM5780 0x08 276 #define BGE_ASICREV_BCM5715 0x09 /* XXX ??? */ 277 278 /* chip revisions */ 279 #define BGE_CHIPREV(x) ((x) >> 24) 280 #define BGE_CHIPREV_5700_AX 0x70 281 #define BGE_CHIPREV_5700_BX 0x71 282 #define BGE_CHIPREV_5700_CX 0x72 283 #define BGE_CHIPREV_5701_AX 0x00 284 285 /* PCI DMA Read/Write Control register */ 286 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 287 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 288 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 289 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 290 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 291 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 292 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 293 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 294 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 295 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 296 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 297 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 298 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 299 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 300 301 /* PCI DMA Read/Write Control register, alternate usage for PCI-Express */ 302 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128 0x00180000 303 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256 0x00380000 304 305 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 306 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 307 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 308 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 309 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 310 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 311 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 312 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 313 314 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 315 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 316 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 317 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 318 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 319 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 320 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 321 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 322 323 /* 324 * PCI state register -- note, this register is read only 325 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 326 * register is set. 327 */ 328 #define BGE_PCISTATE_FORCE_RESET 0x00000001 329 #define BGE_PCISTATE_INTR_STATE 0x00000002 330 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 331 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 332 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 333 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 334 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 335 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 336 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 337 338 /* 339 * The following bits in PCI state register are reserved. 340 * If we check that the register values reverts on reset, 341 * do not check these bits. On some 5704C (rev A3) and some 342 * Altima chips, these bits do not revert until much later 343 * in the bge driver's bge_reset() chip-reset state machine. 344 */ 345 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 346 347 /* 348 * PCI Clock Control register -- note, this register is read only 349 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 350 * register is set. 351 */ 352 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 353 #define BGE_PCICLOCKCTL_M66EN 0x00000080 354 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 355 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 356 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 357 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 358 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 359 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 360 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 361 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 362 363 364 #ifndef PCIM_CMD_MWIEN 365 #define PCIM_CMD_MWIEN 0x0010 366 #endif 367 368 /* 369 * High priority mailbox registers 370 * Each mailbox is 64-bits wide, though we only use the 371 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 372 * first. The NIC will load the mailbox after the lower 32 bit word 373 * has been updated. 374 */ 375 #define BGE_MBX_IRQ0_HI 0x0200 376 #define BGE_MBX_IRQ0_LO 0x0204 377 #define BGE_MBX_IRQ1_HI 0x0208 378 #define BGE_MBX_IRQ1_LO 0x020C 379 #define BGE_MBX_IRQ2_HI 0x0210 380 #define BGE_MBX_IRQ2_LO 0x0214 381 #define BGE_MBX_IRQ3_HI 0x0218 382 #define BGE_MBX_IRQ3_LO 0x021C 383 #define BGE_MBX_GEN0_HI 0x0220 384 #define BGE_MBX_GEN0_LO 0x0224 385 #define BGE_MBX_GEN1_HI 0x0228 386 #define BGE_MBX_GEN1_LO 0x022C 387 #define BGE_MBX_GEN2_HI 0x0230 388 #define BGE_MBX_GEN2_LO 0x0234 389 #define BGE_MBX_GEN3_HI 0x0228 390 #define BGE_MBX_GEN3_LO 0x022C 391 #define BGE_MBX_GEN4_HI 0x0240 392 #define BGE_MBX_GEN4_LO 0x0244 393 #define BGE_MBX_GEN5_HI 0x0248 394 #define BGE_MBX_GEN5_LO 0x024C 395 #define BGE_MBX_GEN6_HI 0x0250 396 #define BGE_MBX_GEN6_LO 0x0254 397 #define BGE_MBX_GEN7_HI 0x0258 398 #define BGE_MBX_GEN7_LO 0x025C 399 #define BGE_MBX_RELOAD_STATS_HI 0x0260 400 #define BGE_MBX_RELOAD_STATS_LO 0x0264 401 #define BGE_MBX_RX_STD_PROD_HI 0x0268 402 #define BGE_MBX_RX_STD_PROD_LO 0x026C 403 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 404 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 405 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 406 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 407 #define BGE_MBX_RX_CONS0_HI 0x0280 408 #define BGE_MBX_RX_CONS0_LO 0x0284 409 #define BGE_MBX_RX_CONS1_HI 0x0288 410 #define BGE_MBX_RX_CONS1_LO 0x028C 411 #define BGE_MBX_RX_CONS2_HI 0x0290 412 #define BGE_MBX_RX_CONS2_LO 0x0294 413 #define BGE_MBX_RX_CONS3_HI 0x0298 414 #define BGE_MBX_RX_CONS3_LO 0x029C 415 #define BGE_MBX_RX_CONS4_HI 0x02A0 416 #define BGE_MBX_RX_CONS4_LO 0x02A4 417 #define BGE_MBX_RX_CONS5_HI 0x02A8 418 #define BGE_MBX_RX_CONS5_LO 0x02AC 419 #define BGE_MBX_RX_CONS6_HI 0x02B0 420 #define BGE_MBX_RX_CONS6_LO 0x02B4 421 #define BGE_MBX_RX_CONS7_HI 0x02B8 422 #define BGE_MBX_RX_CONS7_LO 0x02BC 423 #define BGE_MBX_RX_CONS8_HI 0x02C0 424 #define BGE_MBX_RX_CONS8_LO 0x02C4 425 #define BGE_MBX_RX_CONS9_HI 0x02C8 426 #define BGE_MBX_RX_CONS9_LO 0x02CC 427 #define BGE_MBX_RX_CONS10_HI 0x02D0 428 #define BGE_MBX_RX_CONS10_LO 0x02D4 429 #define BGE_MBX_RX_CONS11_HI 0x02D8 430 #define BGE_MBX_RX_CONS11_LO 0x02DC 431 #define BGE_MBX_RX_CONS12_HI 0x02E0 432 #define BGE_MBX_RX_CONS12_LO 0x02E4 433 #define BGE_MBX_RX_CONS13_HI 0x02E8 434 #define BGE_MBX_RX_CONS13_LO 0x02EC 435 #define BGE_MBX_RX_CONS14_HI 0x02F0 436 #define BGE_MBX_RX_CONS14_LO 0x02F4 437 #define BGE_MBX_RX_CONS15_HI 0x02F8 438 #define BGE_MBX_RX_CONS15_LO 0x02FC 439 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 440 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 441 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 442 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 443 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 444 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 445 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 446 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 447 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 448 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 449 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 450 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 451 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 452 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 453 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 454 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 455 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 456 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 457 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 458 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 459 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 460 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 461 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 462 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 463 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 464 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 465 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 466 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 467 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 468 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 469 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 470 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 471 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 472 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 473 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 474 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 475 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 476 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 477 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 478 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 479 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 480 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 481 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 482 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 483 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 484 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 485 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 486 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 487 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 488 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 489 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 490 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 491 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 492 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 493 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 494 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 495 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 496 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 497 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 498 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 499 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 500 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 501 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 502 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 503 504 #define BGE_TX_RINGS_MAX 4 505 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 506 #define BGE_RX_RINGS_MAX 16 507 508 /* Ethernet MAC control registers */ 509 #define BGE_MAC_MODE 0x0400 510 #define BGE_MAC_STS 0x0404 511 #define BGE_MAC_EVT_ENB 0x0408 512 #define BGE_MAC_LED_CTL 0x040C 513 #define BGE_MAC_ADDR1_LO 0x0410 514 #define BGE_MAC_ADDR1_HI 0x0414 515 #define BGE_MAC_ADDR2_LO 0x0418 516 #define BGE_MAC_ADDR2_HI 0x041C 517 #define BGE_MAC_ADDR3_LO 0x0420 518 #define BGE_MAC_ADDR3_HI 0x0424 519 #define BGE_MAC_ADDR4_LO 0x0428 520 #define BGE_MAC_ADDR4_HI 0x042C 521 #define BGE_WOL_PATPTR 0x0430 522 #define BGE_WOL_PATCFG 0x0434 523 #define BGE_TX_RANDOM_BACKOFF 0x0438 524 #define BGE_RX_MTU 0x043C 525 #define BGE_GBIT_PCS_TEST 0x0440 526 #define BGE_TX_TBI_AUTONEG 0x0444 527 #define BGE_RX_TBI_AUTONEG 0x0448 528 #define BGE_MI_COMM 0x044C 529 #define BGE_MI_STS 0x0450 530 #define BGE_MI_MODE 0x0454 531 #define BGE_AUTOPOLL_STS 0x0458 532 #define BGE_TX_MODE 0x045C 533 #define BGE_TX_STS 0x0460 534 #define BGE_TX_LENGTHS 0x0464 535 #define BGE_RX_MODE 0x0468 536 #define BGE_RX_STS 0x046C 537 #define BGE_MAR0 0x0470 538 #define BGE_MAR1 0x0474 539 #define BGE_MAR2 0x0478 540 #define BGE_MAR3 0x047C 541 #define BGE_RX_BD_RULES_CTL0 0x0480 542 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 543 #define BGE_RX_BD_RULES_CTL1 0x0488 544 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 545 #define BGE_RX_BD_RULES_CTL2 0x0490 546 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 547 #define BGE_RX_BD_RULES_CTL3 0x0498 548 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 549 #define BGE_RX_BD_RULES_CTL4 0x04A0 550 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 551 #define BGE_RX_BD_RULES_CTL5 0x04A8 552 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 553 #define BGE_RX_BD_RULES_CTL6 0x04B0 554 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 555 #define BGE_RX_BD_RULES_CTL7 0x04B8 556 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 557 #define BGE_RX_BD_RULES_CTL8 0x04C0 558 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 559 #define BGE_RX_BD_RULES_CTL9 0x04C8 560 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 561 #define BGE_RX_BD_RULES_CTL10 0x04D0 562 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 563 #define BGE_RX_BD_RULES_CTL11 0x04D8 564 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 565 #define BGE_RX_BD_RULES_CTL12 0x04E0 566 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 567 #define BGE_RX_BD_RULES_CTL13 0x04E8 568 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 569 #define BGE_RX_BD_RULES_CTL14 0x04F0 570 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 571 #define BGE_RX_BD_RULES_CTL15 0x04F8 572 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 573 #define BGE_RX_RULES_CFG 0x0500 574 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 575 #define BGE_RX_STATS 0x0800 576 #define BGE_TX_STATS 0x0880 577 578 /* Ethernet MAC Mode register */ 579 #define BGE_MACMODE_RESET 0x00000001 580 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 581 #define BGE_MACMODE_PORTMODE 0x0000000C 582 #define BGE_MACMODE_LOOPBACK 0x00000010 583 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 584 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 585 #define BGE_MACMODE_MAX_DEFER 0x00000200 586 #define BGE_MACMODE_LINK_POLARITY 0x00000400 587 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 588 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 589 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 590 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 591 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 592 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 593 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 594 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 595 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 596 #define BGE_MACMODE_MIP_ENB 0x00100000 597 #define BGE_MACMODE_TXDMA_ENB 0x00200000 598 #define BGE_MACMODE_RXDMA_ENB 0x00400000 599 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 600 601 #define BGE_PORTMODE_NONE 0x00000000 602 #define BGE_PORTMODE_MII 0x00000004 603 #define BGE_PORTMODE_GMII 0x00000008 604 #define BGE_PORTMODE_TBI 0x0000000C 605 606 /* MAC Status register */ 607 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 608 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 609 #define BGE_MACSTAT_RX_CFG 0x00000004 610 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 611 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 612 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 613 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 614 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 615 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 616 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 617 #define BGE_MACSTAT_ODI_ERROR 0x02000000 618 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 619 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 620 621 /* MAC Event Enable Register */ 622 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 623 #define BGE_EVTENB_LINK_CHANGED 0x00001000 624 #define BGE_EVTENB_MI_COMPLETE 0x00400000 625 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 626 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 627 #define BGE_EVTENB_ODI_ERROR 0x02000000 628 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 629 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 630 631 /* LED Control Register */ 632 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 633 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 634 #define BGE_LEDCTL_100MBPS_LED 0x00000004 635 #define BGE_LEDCTL_10MBPS_LED 0x00000008 636 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 637 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 638 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 639 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 640 #define BGE_LEDCTL_100MBPS_STS 0x00000100 641 #define BGE_LEDCTL_10MBPS_STS 0x00000200 642 #define BGE_LEDCTL_TRADLED_STS 0x00000400 643 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 644 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 645 646 /* TX backoff seed register */ 647 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 648 649 /* Autopoll status register */ 650 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 651 652 /* Transmit MAC mode register */ 653 #define BGE_TXMODE_RESET 0x00000001 654 #define BGE_TXMODE_ENABLE 0x00000002 655 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 656 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 657 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 658 659 /* Transmit MAC status register */ 660 #define BGE_TXSTAT_RX_XOFFED 0x00000001 661 #define BGE_TXSTAT_SENT_XOFF 0x00000002 662 #define BGE_TXSTAT_SENT_XON 0x00000004 663 #define BGE_TXSTAT_LINK_UP 0x00000008 664 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 665 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 666 667 /* Transmit MAC lengths register */ 668 #define BGE_TXLEN_SLOTTIME 0x000000FF 669 #define BGE_TXLEN_IPG 0x00000F00 670 #define BGE_TXLEN_CRS 0x00003000 671 672 /* Receive MAC mode register */ 673 #define BGE_RXMODE_RESET 0x00000001 674 #define BGE_RXMODE_ENABLE 0x00000002 675 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 676 #define BGE_RXMODE_RX_GIANTS 0x00000020 677 #define BGE_RXMODE_RX_RUNTS 0x00000040 678 #define BGE_RXMODE_8022_LENCHECK 0x00000080 679 #define BGE_RXMODE_RX_PROMISC 0x00000100 680 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 681 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 682 683 /* Receive MAC status register */ 684 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 685 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 686 #define BGE_RXSTAT_RCVD_XON 0x00000004 687 688 /* Receive Rules Control register */ 689 #define BGE_RXRULECTL_OFFSET 0x000000FF 690 #define BGE_RXRULECTL_CLASS 0x00001F00 691 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 692 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 693 #define BGE_RXRULECTL_MAP 0x01000000 694 #define BGE_RXRULECTL_DISCARD 0x02000000 695 #define BGE_RXRULECTL_MASK 0x04000000 696 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 697 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 698 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 699 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 700 701 /* Receive Rules Mask register */ 702 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 703 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 704 705 /* MI communication register */ 706 #define BGE_MICOMM_DATA 0x0000FFFF 707 #define BGE_MICOMM_REG 0x001F0000 708 #define BGE_MICOMM_PHY 0x03E00000 709 #define BGE_MICOMM_CMD 0x0C000000 710 #define BGE_MICOMM_READFAIL 0x10000000 711 #define BGE_MICOMM_BUSY 0x20000000 712 713 #define BGE_MIREG(x) ((x & 0x1F) << 16) 714 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 715 #define BGE_MICMD_WRITE 0x04000000 716 #define BGE_MICMD_READ 0x08000000 717 718 /* MI status register */ 719 #define BGE_MISTS_LINK 0x00000001 720 #define BGE_MISTS_10MBPS 0x00000002 721 722 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 723 #define BGE_MIMODE_AUTOPOLL 0x00000010 724 #define BGE_MIMODE_CLKCNT 0x001F0000 725 726 727 /* 728 * Send data initiator control registers. 729 */ 730 #define BGE_SDI_MODE 0x0C00 731 #define BGE_SDI_STATUS 0x0C04 732 #define BGE_SDI_STATS_CTL 0x0C08 733 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 734 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 735 #define BGE_LOCSTATS_COS0 0x0C80 736 #define BGE_LOCSTATS_COS1 0x0C84 737 #define BGE_LOCSTATS_COS2 0x0C88 738 #define BGE_LOCSTATS_COS3 0x0C8C 739 #define BGE_LOCSTATS_COS4 0x0C90 740 #define BGE_LOCSTATS_COS5 0x0C84 741 #define BGE_LOCSTATS_COS6 0x0C98 742 #define BGE_LOCSTATS_COS7 0x0C9C 743 #define BGE_LOCSTATS_COS8 0x0CA0 744 #define BGE_LOCSTATS_COS9 0x0CA4 745 #define BGE_LOCSTATS_COS10 0x0CA8 746 #define BGE_LOCSTATS_COS11 0x0CAC 747 #define BGE_LOCSTATS_COS12 0x0CB0 748 #define BGE_LOCSTATS_COS13 0x0CB4 749 #define BGE_LOCSTATS_COS14 0x0CB8 750 #define BGE_LOCSTATS_COS15 0x0CBC 751 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 752 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 753 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 754 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 755 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 756 #define BGE_LOCSTATS_IRQS 0x0CD4 757 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 758 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 759 760 /* Send Data Initiator mode register */ 761 #define BGE_SDIMODE_RESET 0x00000001 762 #define BGE_SDIMODE_ENABLE 0x00000002 763 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 764 765 /* Send Data Initiator stats register */ 766 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 767 768 /* Send Data Initiator stats control register */ 769 #define BGE_SDISTATSCTL_ENABLE 0x00000001 770 #define BGE_SDISTATSCTL_FASTER 0x00000002 771 #define BGE_SDISTATSCTL_CLEAR 0x00000004 772 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 773 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 774 775 /* 776 * Send Data Completion Control registers 777 */ 778 #define BGE_SDC_MODE 0x1000 779 #define BGE_SDC_STATUS 0x1004 780 781 /* Send Data completion mode register */ 782 #define BGE_SDCMODE_RESET 0x00000001 783 #define BGE_SDCMODE_ENABLE 0x00000002 784 #define BGE_SDCMODE_ATTN 0x00000004 785 786 /* Send Data completion status register */ 787 #define BGE_SDCSTAT_ATTN 0x00000004 788 789 /* 790 * Send BD Ring Selector Control registers 791 */ 792 #define BGE_SRS_MODE 0x1400 793 #define BGE_SRS_STATUS 0x1404 794 #define BGE_SRS_HWDIAG 0x1408 795 #define BGE_SRS_LOC_NIC_CONS0 0x1440 796 #define BGE_SRS_LOC_NIC_CONS1 0x1444 797 #define BGE_SRS_LOC_NIC_CONS2 0x1448 798 #define BGE_SRS_LOC_NIC_CONS3 0x144C 799 #define BGE_SRS_LOC_NIC_CONS4 0x1450 800 #define BGE_SRS_LOC_NIC_CONS5 0x1454 801 #define BGE_SRS_LOC_NIC_CONS6 0x1458 802 #define BGE_SRS_LOC_NIC_CONS7 0x145C 803 #define BGE_SRS_LOC_NIC_CONS8 0x1460 804 #define BGE_SRS_LOC_NIC_CONS9 0x1464 805 #define BGE_SRS_LOC_NIC_CONS10 0x1468 806 #define BGE_SRS_LOC_NIC_CONS11 0x146C 807 #define BGE_SRS_LOC_NIC_CONS12 0x1470 808 #define BGE_SRS_LOC_NIC_CONS13 0x1474 809 #define BGE_SRS_LOC_NIC_CONS14 0x1478 810 #define BGE_SRS_LOC_NIC_CONS15 0x147C 811 812 /* Send BD Ring Selector Mode register */ 813 #define BGE_SRSMODE_RESET 0x00000001 814 #define BGE_SRSMODE_ENABLE 0x00000002 815 #define BGE_SRSMODE_ATTN 0x00000004 816 817 /* Send BD Ring Selector Status register */ 818 #define BGE_SRSSTAT_ERROR 0x00000004 819 820 /* Send BD Ring Selector HW Diagnostics register */ 821 #define BGE_SRSHWDIAG_STATE 0x0000000F 822 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 823 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 824 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 825 826 /* 827 * Send BD Initiator Selector Control registers 828 */ 829 #define BGE_SBDI_MODE 0x1800 830 #define BGE_SBDI_STATUS 0x1804 831 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 832 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 833 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 834 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 835 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 836 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 837 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 838 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 839 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 840 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 841 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 842 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 843 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 844 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 845 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 846 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 847 848 /* Send BD Initiator Mode register */ 849 #define BGE_SBDIMODE_RESET 0x00000001 850 #define BGE_SBDIMODE_ENABLE 0x00000002 851 #define BGE_SBDIMODE_ATTN 0x00000004 852 853 /* Send BD Initiator Status register */ 854 #define BGE_SBDISTAT_ERROR 0x00000004 855 856 /* 857 * Send BD Completion Control registers 858 */ 859 #define BGE_SBDC_MODE 0x1C00 860 #define BGE_SBDC_STATUS 0x1C04 861 862 /* Send BD Completion Control Mode register */ 863 #define BGE_SBDCMODE_RESET 0x00000001 864 #define BGE_SBDCMODE_ENABLE 0x00000002 865 #define BGE_SBDCMODE_ATTN 0x00000004 866 867 /* Send BD Completion Control Status register */ 868 #define BGE_SBDCSTAT_ATTN 0x00000004 869 870 /* 871 * Receive List Placement Control registers 872 */ 873 #define BGE_RXLP_MODE 0x2000 874 #define BGE_RXLP_STATUS 0x2004 875 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 876 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 877 #define BGE_RXLP_CFG 0x2010 878 #define BGE_RXLP_STATS_CTL 0x2014 879 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 880 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 881 #define BGE_RXLP_HEAD0 0x2100 882 #define BGE_RXLP_TAIL0 0x2104 883 #define BGE_RXLP_COUNT0 0x2108 884 #define BGE_RXLP_HEAD1 0x2110 885 #define BGE_RXLP_TAIL1 0x2114 886 #define BGE_RXLP_COUNT1 0x2118 887 #define BGE_RXLP_HEAD2 0x2120 888 #define BGE_RXLP_TAIL2 0x2124 889 #define BGE_RXLP_COUNT2 0x2128 890 #define BGE_RXLP_HEAD3 0x2130 891 #define BGE_RXLP_TAIL3 0x2134 892 #define BGE_RXLP_COUNT3 0x2138 893 #define BGE_RXLP_HEAD4 0x2140 894 #define BGE_RXLP_TAIL4 0x2144 895 #define BGE_RXLP_COUNT4 0x2148 896 #define BGE_RXLP_HEAD5 0x2150 897 #define BGE_RXLP_TAIL5 0x2154 898 #define BGE_RXLP_COUNT5 0x2158 899 #define BGE_RXLP_HEAD6 0x2160 900 #define BGE_RXLP_TAIL6 0x2164 901 #define BGE_RXLP_COUNT6 0x2168 902 #define BGE_RXLP_HEAD7 0x2170 903 #define BGE_RXLP_TAIL7 0x2174 904 #define BGE_RXLP_COUNT7 0x2178 905 #define BGE_RXLP_HEAD8 0x2180 906 #define BGE_RXLP_TAIL8 0x2184 907 #define BGE_RXLP_COUNT8 0x2188 908 #define BGE_RXLP_HEAD9 0x2190 909 #define BGE_RXLP_TAIL9 0x2194 910 #define BGE_RXLP_COUNT9 0x2198 911 #define BGE_RXLP_HEAD10 0x21A0 912 #define BGE_RXLP_TAIL10 0x21A4 913 #define BGE_RXLP_COUNT10 0x21A8 914 #define BGE_RXLP_HEAD11 0x21B0 915 #define BGE_RXLP_TAIL11 0x21B4 916 #define BGE_RXLP_COUNT11 0x21B8 917 #define BGE_RXLP_HEAD12 0x21C0 918 #define BGE_RXLP_TAIL12 0x21C4 919 #define BGE_RXLP_COUNT12 0x21C8 920 #define BGE_RXLP_HEAD13 0x21D0 921 #define BGE_RXLP_TAIL13 0x21D4 922 #define BGE_RXLP_COUNT13 0x21D8 923 #define BGE_RXLP_HEAD14 0x21E0 924 #define BGE_RXLP_TAIL14 0x21E4 925 #define BGE_RXLP_COUNT14 0x21E8 926 #define BGE_RXLP_HEAD15 0x21F0 927 #define BGE_RXLP_TAIL15 0x21F4 928 #define BGE_RXLP_COUNT15 0x21F8 929 #define BGE_RXLP_LOCSTAT_COS0 0x2200 930 #define BGE_RXLP_LOCSTAT_COS1 0x2204 931 #define BGE_RXLP_LOCSTAT_COS2 0x2208 932 #define BGE_RXLP_LOCSTAT_COS3 0x220C 933 #define BGE_RXLP_LOCSTAT_COS4 0x2210 934 #define BGE_RXLP_LOCSTAT_COS5 0x2214 935 #define BGE_RXLP_LOCSTAT_COS6 0x2218 936 #define BGE_RXLP_LOCSTAT_COS7 0x221C 937 #define BGE_RXLP_LOCSTAT_COS8 0x2220 938 #define BGE_RXLP_LOCSTAT_COS9 0x2224 939 #define BGE_RXLP_LOCSTAT_COS10 0x2228 940 #define BGE_RXLP_LOCSTAT_COS11 0x222C 941 #define BGE_RXLP_LOCSTAT_COS12 0x2230 942 #define BGE_RXLP_LOCSTAT_COS13 0x2234 943 #define BGE_RXLP_LOCSTAT_COS14 0x2238 944 #define BGE_RXLP_LOCSTAT_COS15 0x223C 945 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 946 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 947 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 948 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 949 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 950 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 951 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 952 953 954 /* Receive List Placement mode register */ 955 #define BGE_RXLPMODE_RESET 0x00000001 956 #define BGE_RXLPMODE_ENABLE 0x00000002 957 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 958 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 959 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 960 961 /* Receive List Placement Status register */ 962 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 963 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 964 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 965 966 /* 967 * Receive Data and Receive BD Initiator Control Registers 968 */ 969 #define BGE_RDBDI_MODE 0x2400 970 #define BGE_RDBDI_STATUS 0x2404 971 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 972 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 973 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 974 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 975 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 976 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 977 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 978 #define BGE_RX_STD_RCB_NICADDR 0x245C 979 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 980 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 981 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 982 #define BGE_RX_MINI_RCB_NICADDR 0x246C 983 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 984 #define BGE_RDBDI_STD_RX_CONS 0x2474 985 #define BGE_RDBDI_MINI_RX_CONS 0x2478 986 #define BGE_RDBDI_RETURN_PROD0 0x2480 987 #define BGE_RDBDI_RETURN_PROD1 0x2484 988 #define BGE_RDBDI_RETURN_PROD2 0x2488 989 #define BGE_RDBDI_RETURN_PROD3 0x248C 990 #define BGE_RDBDI_RETURN_PROD4 0x2490 991 #define BGE_RDBDI_RETURN_PROD5 0x2494 992 #define BGE_RDBDI_RETURN_PROD6 0x2498 993 #define BGE_RDBDI_RETURN_PROD7 0x249C 994 #define BGE_RDBDI_RETURN_PROD8 0x24A0 995 #define BGE_RDBDI_RETURN_PROD9 0x24A4 996 #define BGE_RDBDI_RETURN_PROD10 0x24A8 997 #define BGE_RDBDI_RETURN_PROD11 0x24AC 998 #define BGE_RDBDI_RETURN_PROD12 0x24B0 999 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1000 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1001 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1002 #define BGE_RDBDI_HWDIAG 0x24C0 1003 1004 1005 /* Receive Data and Receive BD Initiator Mode register */ 1006 #define BGE_RDBDIMODE_RESET 0x00000001 1007 #define BGE_RDBDIMODE_ENABLE 0x00000002 1008 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1009 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1010 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1011 1012 /* Receive Data and Receive BD Initiator Status register */ 1013 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1014 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1015 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1016 1017 1018 /* 1019 * Receive Data Completion Control registers 1020 */ 1021 #define BGE_RDC_MODE 0x2800 1022 1023 /* Receive Data Completion Mode register */ 1024 #define BGE_RDCMODE_RESET 0x00000001 1025 #define BGE_RDCMODE_ENABLE 0x00000002 1026 #define BGE_RDCMODE_ATTN 0x00000004 1027 1028 /* 1029 * Receive BD Initiator Control registers 1030 */ 1031 #define BGE_RBDI_MODE 0x2C00 1032 #define BGE_RBDI_STATUS 0x2C04 1033 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1034 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1035 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1036 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1037 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1038 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1039 1040 /* Receive BD Initiator Mode register */ 1041 #define BGE_RBDIMODE_RESET 0x00000001 1042 #define BGE_RBDIMODE_ENABLE 0x00000002 1043 #define BGE_RBDIMODE_ATTN 0x00000004 1044 1045 /* Receive BD Initiator Status register */ 1046 #define BGE_RBDISTAT_ATTN 0x00000004 1047 1048 /* 1049 * Receive BD Completion Control registers 1050 */ 1051 #define BGE_RBDC_MODE 0x3000 1052 #define BGE_RBDC_STATUS 0x3004 1053 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1054 #define BGE_RBDC_STD_BD_PROD 0x300C 1055 #define BGE_RBDC_MINI_BD_PROD 0x3010 1056 1057 /* Receive BD completion mode register */ 1058 #define BGE_RBDCMODE_RESET 0x00000001 1059 #define BGE_RBDCMODE_ENABLE 0x00000002 1060 #define BGE_RBDCMODE_ATTN 0x00000004 1061 1062 /* Receive BD completion status register */ 1063 #define BGE_RBDCSTAT_ERROR 0x00000004 1064 1065 /* 1066 * Receive List Selector Control registers 1067 */ 1068 #define BGE_RXLS_MODE 0x3400 1069 #define BGE_RXLS_STATUS 0x3404 1070 1071 /* Receive List Selector Mode register */ 1072 #define BGE_RXLSMODE_RESET 0x00000001 1073 #define BGE_RXLSMODE_ENABLE 0x00000002 1074 #define BGE_RXLSMODE_ATTN 0x00000004 1075 1076 /* Receive List Selector Status register */ 1077 #define BGE_RXLSSTAT_ERROR 0x00000004 1078 1079 /* 1080 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1081 */ 1082 #define BGE_MBCF_MODE 0x3800 1083 #define BGE_MBCF_STATUS 0x3804 1084 1085 /* Mbuf Cluster Free mode register */ 1086 #define BGE_MBCFMODE_RESET 0x00000001 1087 #define BGE_MBCFMODE_ENABLE 0x00000002 1088 #define BGE_MBCFMODE_ATTN 0x00000004 1089 1090 /* Mbuf Cluster Free status register */ 1091 #define BGE_MBCFSTAT_ERROR 0x00000004 1092 1093 /* 1094 * Host Coalescing Control registers 1095 */ 1096 #define BGE_HCC_MODE 0x3C00 1097 #define BGE_HCC_STATUS 0x3C04 1098 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1099 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1100 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1101 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1102 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1103 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1104 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1105 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1106 #define BGE_HCC_STATS_TICKS 0x3C28 1107 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1108 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1109 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1110 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1111 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1112 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1113 #define BGE_FLOW_ATTN 0x3C48 1114 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1115 #define BGE_HCC_STD_BD_CONS 0x3C54 1116 #define BGE_HCC_MINI_BD_CONS 0x3C58 1117 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1118 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1119 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1120 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1121 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1122 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1123 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1124 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1125 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1126 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1127 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1128 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1129 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1130 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1131 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1132 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1133 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1134 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1135 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1136 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1137 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1138 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1139 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1140 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1141 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1142 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1143 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1144 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1145 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1146 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1147 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1148 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1149 1150 1151 /* Host coalescing mode register */ 1152 #define BGE_HCCMODE_RESET 0x00000001 1153 #define BGE_HCCMODE_ENABLE 0x00000002 1154 #define BGE_HCCMODE_ATTN 0x00000004 1155 #define BGE_HCCMODE_COAL_NOW 0x00000008 1156 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1157 #define BGE_HCCMODE_64BYTE 0x00000080 1158 #define BGE_HCCMODE_32BYTE 0x00000100 1159 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1160 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1161 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1162 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1163 1164 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1165 1166 #define BGE_STATBLKSZ_FULL 0x00000000 1167 #define BGE_STATBLKSZ_64BYTE 0x00000080 1168 #define BGE_STATBLKSZ_32BYTE 0x00000100 1169 1170 /* Host coalescing status register */ 1171 #define BGE_HCCSTAT_ERROR 0x00000004 1172 1173 /* Flow attention register */ 1174 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1175 #define BGE_FLOWATTN_MEMARB 0x00000080 1176 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1177 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1178 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1179 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1180 #define BGE_FLOWATTN_RDBDI 0x00080000 1181 #define BGE_FLOWATTN_RXLS 0x00100000 1182 #define BGE_FLOWATTN_RXLP 0x00200000 1183 #define BGE_FLOWATTN_RBDC 0x00400000 1184 #define BGE_FLOWATTN_RBDI 0x00800000 1185 #define BGE_FLOWATTN_SDC 0x08000000 1186 #define BGE_FLOWATTN_SDI 0x10000000 1187 #define BGE_FLOWATTN_SRS 0x20000000 1188 #define BGE_FLOWATTN_SBDC 0x40000000 1189 #define BGE_FLOWATTN_SBDI 0x80000000 1190 1191 /* 1192 * Memory arbiter registers 1193 */ 1194 #define BGE_MARB_MODE 0x4000 1195 #define BGE_MARB_STATUS 0x4004 1196 #define BGE_MARB_TRAPADDR_HI 0x4008 1197 #define BGE_MARB_TRAPADDR_LO 0x400C 1198 1199 /* Memory arbiter mode register */ 1200 #define BGE_MARBMODE_RESET 0x00000001 1201 #define BGE_MARBMODE_ENABLE 0x00000002 1202 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1203 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1204 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1205 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1206 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1207 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1208 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1209 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1210 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1211 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1212 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1213 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1214 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1215 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1216 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1217 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1218 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1219 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1220 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1221 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1222 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1223 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1224 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1225 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1226 1227 /* Memory arbiter status register */ 1228 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1229 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1230 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1231 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1232 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1233 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1234 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1235 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1236 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1237 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1238 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1239 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1240 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1241 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1242 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1243 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1244 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1245 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1246 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1247 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1248 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1249 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1250 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1251 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1252 1253 /* 1254 * Buffer manager control registers 1255 */ 1256 #define BGE_BMAN_MODE 0x4400 1257 #define BGE_BMAN_STATUS 0x4404 1258 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1259 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1260 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1261 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1262 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1263 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1264 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1265 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1266 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1267 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1268 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1269 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1270 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1271 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1272 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1273 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1274 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1275 #define BGE_BMAN_HWDIAG_1 0x444C 1276 #define BGE_BMAN_HWDIAG_2 0x4450 1277 #define BGE_BMAN_HWDIAG_3 0x4454 1278 1279 /* Buffer manager mode register */ 1280 #define BGE_BMANMODE_RESET 0x00000001 1281 #define BGE_BMANMODE_ENABLE 0x00000002 1282 #define BGE_BMANMODE_ATTN 0x00000004 1283 #define BGE_BMANMODE_TESTMODE 0x00000008 1284 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1285 1286 /* Buffer manager status register */ 1287 #define BGE_BMANSTAT_ERRO 0x00000004 1288 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1289 1290 1291 /* 1292 * Read DMA Control registers 1293 */ 1294 #define BGE_RDMA_MODE 0x4800 1295 #define BGE_RDMA_STATUS 0x4804 1296 1297 /* Read DMA mode register */ 1298 #define BGE_RDMAMODE_RESET 0x00000001 1299 #define BGE_RDMAMODE_ENABLE 0x00000002 1300 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1301 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1302 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1303 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1304 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1305 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1306 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1307 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1308 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1309 1310 /* Alternate encodings for PCI-Express, from Broadcom-supplied Linux driver */ 1311 #define BGE_RDMA_MODE_FIFO_LONG_BURST ((1<<17) || (1 << 16)) 1312 #define BGE_RDMA_MODE_FIFO_SIZE_128 (1 << 17) 1313 1314 /* Read DMA status register */ 1315 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1316 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1317 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1318 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1319 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1320 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1321 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1322 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1323 1324 /* 1325 * Write DMA control registers 1326 */ 1327 #define BGE_WDMA_MODE 0x4C00 1328 #define BGE_WDMA_STATUS 0x4C04 1329 1330 /* Write DMA mode register */ 1331 #define BGE_WDMAMODE_RESET 0x00000001 1332 #define BGE_WDMAMODE_ENABLE 0x00000002 1333 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1334 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1335 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1336 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1337 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1338 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1339 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1340 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1341 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1342 1343 /* Write DMA status register */ 1344 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1345 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1346 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1347 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1348 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1349 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1350 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1351 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1352 1353 1354 /* 1355 * RX CPU registers 1356 */ 1357 #define BGE_RXCPU_MODE 0x5000 1358 #define BGE_RXCPU_STATUS 0x5004 1359 #define BGE_RXCPU_PC 0x501C 1360 1361 /* RX CPU mode register */ 1362 #define BGE_RXCPUMODE_RESET 0x00000001 1363 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1364 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1365 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1366 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1367 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1368 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1369 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1370 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1371 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1372 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1373 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1374 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1375 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1376 1377 /* RX CPU status register */ 1378 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1379 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1380 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1381 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1382 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1383 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1384 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1385 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1386 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1387 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1388 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1389 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1390 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1391 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1392 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1393 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1394 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1395 1396 1397 /* 1398 * TX CPU registers 1399 */ 1400 #define BGE_TXCPU_MODE 0x5400 1401 #define BGE_TXCPU_STATUS 0x5404 1402 #define BGE_TXCPU_PC 0x541C 1403 1404 /* TX CPU mode register */ 1405 #define BGE_TXCPUMODE_RESET 0x00000001 1406 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1407 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1408 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1409 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1410 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1411 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1412 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1413 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1414 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1415 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1416 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1417 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1418 1419 /* TX CPU status register */ 1420 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1421 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1422 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1423 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1424 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1425 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1426 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1427 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1428 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1429 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1430 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1431 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1432 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1433 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1434 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1435 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1436 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1437 1438 1439 /* 1440 * Low priority mailbox registers 1441 */ 1442 #define BGE_LPMBX_IRQ0_HI 0x5800 1443 #define BGE_LPMBX_IRQ0_LO 0x5804 1444 #define BGE_LPMBX_IRQ1_HI 0x5808 1445 #define BGE_LPMBX_IRQ1_LO 0x580C 1446 #define BGE_LPMBX_IRQ2_HI 0x5810 1447 #define BGE_LPMBX_IRQ2_LO 0x5814 1448 #define BGE_LPMBX_IRQ3_HI 0x5818 1449 #define BGE_LPMBX_IRQ3_LO 0x581C 1450 #define BGE_LPMBX_GEN0_HI 0x5820 1451 #define BGE_LPMBX_GEN0_LO 0x5824 1452 #define BGE_LPMBX_GEN1_HI 0x5828 1453 #define BGE_LPMBX_GEN1_LO 0x582C 1454 #define BGE_LPMBX_GEN2_HI 0x5830 1455 #define BGE_LPMBX_GEN2_LO 0x5834 1456 #define BGE_LPMBX_GEN3_HI 0x5828 1457 #define BGE_LPMBX_GEN3_LO 0x582C 1458 #define BGE_LPMBX_GEN4_HI 0x5840 1459 #define BGE_LPMBX_GEN4_LO 0x5844 1460 #define BGE_LPMBX_GEN5_HI 0x5848 1461 #define BGE_LPMBX_GEN5_LO 0x584C 1462 #define BGE_LPMBX_GEN6_HI 0x5850 1463 #define BGE_LPMBX_GEN6_LO 0x5854 1464 #define BGE_LPMBX_GEN7_HI 0x5858 1465 #define BGE_LPMBX_GEN7_LO 0x585C 1466 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1467 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1468 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1469 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1470 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1471 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1472 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1473 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1474 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1475 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1476 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1477 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1478 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1479 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1480 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1481 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1482 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1483 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1484 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1485 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1486 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1487 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1488 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1489 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1490 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1491 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1492 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1493 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1494 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1495 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1496 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1497 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1498 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1499 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1500 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1501 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1502 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1503 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1504 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1505 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1506 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1507 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1508 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1509 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1510 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1511 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1512 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1513 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1514 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1515 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1516 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1517 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1518 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1519 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1520 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1521 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1522 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1523 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1524 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1525 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1526 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1527 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1528 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1529 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1530 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1531 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1532 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1533 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1534 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1535 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1536 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1537 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1538 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1539 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1540 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1541 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1542 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1543 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1544 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1545 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1546 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1547 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1548 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1549 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1550 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1551 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1552 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1553 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1554 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1555 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1556 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1557 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1558 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1559 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1560 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1561 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1562 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1563 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1564 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1565 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1566 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1567 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1568 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1569 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1570 1571 /* 1572 * Flow throw Queue reset register 1573 */ 1574 #define BGE_FTQ_RESET 0x5C00 1575 1576 #define BGE_FTQRESET_DMAREAD 0x00000002 1577 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1578 #define BGE_FTQRESET_DMADONE 0x00000010 1579 #define BGE_FTQRESET_SBDC 0x00000020 1580 #define BGE_FTQRESET_SDI 0x00000040 1581 #define BGE_FTQRESET_WDMA 0x00000080 1582 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1583 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1584 #define BGE_FTQRESET_SDC 0x00000400 1585 #define BGE_FTQRESET_HCC 0x00000800 1586 #define BGE_FTQRESET_TXFIFO 0x00001000 1587 #define BGE_FTQRESET_MBC 0x00002000 1588 #define BGE_FTQRESET_RBDC 0x00004000 1589 #define BGE_FTQRESET_RXLP 0x00008000 1590 #define BGE_FTQRESET_RDBDI 0x00010000 1591 #define BGE_FTQRESET_RDC 0x00020000 1592 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1593 1594 /* 1595 * Message Signaled Interrupt registers 1596 */ 1597 #define BGE_MSI_MODE 0x6000 1598 #define BGE_MSI_STATUS 0x6004 1599 #define BGE_MSI_FIFOACCESS 0x6008 1600 1601 /* MSI mode register */ 1602 #define BGE_MSIMODE_RESET 0x00000001 1603 #define BGE_MSIMODE_ENABLE 0x00000002 1604 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1605 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1606 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1607 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1608 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1609 1610 /* MSI status register */ 1611 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1612 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1613 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1614 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1615 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1616 1617 1618 /* 1619 * DMA Completion registers 1620 */ 1621 #define BGE_DMAC_MODE 0x6400 1622 1623 /* DMA Completion mode register */ 1624 #define BGE_DMACMODE_RESET 0x00000001 1625 #define BGE_DMACMODE_ENABLE 0x00000002 1626 1627 1628 /* 1629 * General control registers. 1630 */ 1631 #define BGE_MODE_CTL 0x6800 1632 #define BGE_MISC_CFG 0x6804 1633 #define BGE_MISC_LOCAL_CTL 0x6808 1634 #define BGE_MISC_TIMER 0x680c 1635 #define BGE_EE_ADDR 0x6838 1636 #define BGE_EE_DATA 0x683C 1637 #define BGE_EE_CTL 0x6840 1638 #define BGE_MDI_CTL 0x6844 1639 #define BGE_EE_DELAY 0x6848 1640 /* 1641 * XXX: Those names are made up as I have no documentation about it; 1642 * I only know it is only used in the PCI-Express case. 1643 */ 1644 #define BGE_PCIE_CTL0 0x7c00 1645 #define BGE_PCIE_CTL1 0x7e2c 1646 /* 1647 * TLP Control Register 1648 * Applicable to BCM5721 and BCM5751 only 1649 */ 1650 #define BGE_TLP_CONTROL_REG 0x7c00 1651 #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1652 1653 /* 1654 * PHY Test Control Register 1655 * Applicable to BCM5721 and BCM5751 only 1656 */ 1657 #define BGE_PHY_TEST_CTRL_REG 0x7e2c 1658 #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1659 #define BGE_PHY_PCIE_LTASS_MODE 0x0040 1660 1661 1662 1663 /* Mode control register */ 1664 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1665 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1666 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1667 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1668 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1669 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1670 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1671 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1672 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1673 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1674 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1675 #define BGE_MODECTL_STACKUP 0x00010000 1676 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1677 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1678 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1679 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1680 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1681 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1682 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1683 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1684 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1685 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1686 1687 /* Misc. config register */ 1688 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1689 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1690 1691 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1692 1693 /* Misc. Local Control */ 1694 #define BGE_MLC_INTR_STATE 0x00000001 1695 #define BGE_MLC_INTR_CLR 0x00000002 1696 #define BGE_MLC_INTR_SET 0x00000004 1697 #define BGE_MLC_INTR_ONATTN 0x00000008 1698 #define BGE_MLC_MISCIO_IN0 0x00000100 1699 #define BGE_MLC_MISCIO_IN1 0x00000200 1700 #define BGE_MLC_MISCIO_IN2 0x00000400 1701 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1702 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1703 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1704 #define BGE_MLC_MISCIO_OUT0 0x00004000 1705 #define BGE_MLC_MISCIO_OUT1 0x00008000 1706 #define BGE_MLC_MISCIO_OUT2 0x00010000 1707 #define BGE_MLC_EXTRAM_ENB 0x00020000 1708 #define BGE_MLC_SRAM_SIZE 0x001C0000 1709 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1710 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1711 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1712 #define BGE_MLC_AUTO_EEPROM 0x01000000 1713 1714 #define BGE_SSRAMSIZE_256KB 0x00000000 1715 #define BGE_SSRAMSIZE_512KB 0x00040000 1716 #define BGE_SSRAMSIZE_1MB 0x00080000 1717 #define BGE_SSRAMSIZE_2MB 0x000C0000 1718 #define BGE_SSRAMSIZE_4MB 0x00100000 1719 #define BGE_SSRAMSIZE_8MB 0x00140000 1720 #define BGE_SSRAMSIZE_16M 0x00180000 1721 1722 /* EEPROM address register */ 1723 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1724 #define BGE_EEADDR_HALFCLK 0x01FF0000 1725 #define BGE_EEADDR_START 0x02000000 1726 #define BGE_EEADDR_DEVID 0x1C000000 1727 #define BGE_EEADDR_RESET 0x20000000 1728 #define BGE_EEADDR_DONE 0x40000000 1729 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1730 1731 #define BGE_EEDEVID(x) ((x & 7) << 26) 1732 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1733 #define BGE_HALFCLK_384SCL 0x60 1734 #define BGE_EE_READCMD \ 1735 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1736 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1737 #define BGE_EE_WRCMD \ 1738 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1739 BGE_EEADDR_START|BGE_EEADDR_DONE) 1740 1741 /* EEPROM Control register */ 1742 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1743 #define BGE_EECTL_CLKOUT 0x00000002 1744 #define BGE_EECTL_CLKIN 0x00000004 1745 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1746 #define BGE_EECTL_DATAOUT 0x00000010 1747 #define BGE_EECTL_DATAIN 0x00000020 1748 1749 /* MDI (MII/GMII) access register */ 1750 #define BGE_MDI_DATA 0x00000001 1751 #define BGE_MDI_DIR 0x00000002 1752 #define BGE_MDI_SEL 0x00000004 1753 #define BGE_MDI_CLK 0x00000008 1754 1755 #define BGE_MEMWIN_START 0x00008000 1756 #define BGE_MEMWIN_END 0x0000FFFF 1757 1758 1759 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1760 do { \ 1761 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1762 (0xFFFF0000 & x)); \ 1763 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1764 } while(0) 1765 1766 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1767 do { \ 1768 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1769 (0xFFFF0000 & x)); \ 1770 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1771 } while(0) 1772 1773 /* 1774 * This magic number is used to prevent PXE restart when we 1775 * issue a software reset. We write this magic number to the 1776 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1777 * code from running. 1778 */ 1779 #define BGE_MAGIC_NUMBER 0x4B657654 1780 1781 typedef struct { 1782 u_int32_t bge_addr_hi; 1783 u_int32_t bge_addr_lo; 1784 } bge_hostaddr; 1785 1786 static __inline void 1787 bge_set_hostaddr(volatile bge_hostaddr *x, bus_addr_t y) 1788 { 1789 x->bge_addr_lo = y & 0xffffffff; 1790 if (sizeof (bus_addr_t) == 8) 1791 x->bge_addr_hi = (u_int64_t)y >> 32; 1792 else 1793 x->bge_addr_hi = 0; 1794 } 1795 1796 /* Ring control block structure */ 1797 struct bge_rcb { 1798 bge_hostaddr bge_hostaddr; 1799 u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 1800 u_int32_t bge_nicaddr; 1801 }; 1802 1803 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1804 1805 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1806 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1807 rcb + offsetof(struct bge_rcb, offset), val) 1808 1809 1810 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1811 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1812 1813 struct bge_tx_bd { 1814 bge_hostaddr bge_addr; 1815 #if BYTE_ORDER == BIG_ENDIAN 1816 u_int16_t bge_len; 1817 u_int16_t bge_flags; 1818 u_int16_t bge_rsvd; 1819 u_int16_t bge_vlan_tag; 1820 #else 1821 u_int16_t bge_flags; 1822 u_int16_t bge_len; 1823 u_int16_t bge_vlan_tag; 1824 u_int16_t bge_rsvd; 1825 #endif 1826 }; 1827 1828 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1829 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1830 #define BGE_TXBDFLAG_END 0x0004 1831 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1832 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1833 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1834 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1835 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1836 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1837 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1838 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1839 #define BGE_TXBDFLAG_NO_CRC 0x8000 1840 1841 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1842 BGE_SEND_RING_1_TO_4 + \ 1843 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1844 1845 struct bge_rx_bd { 1846 bge_hostaddr bge_addr; 1847 #if BYTE_ORDER == BIG_ENDIAN 1848 u_int16_t bge_idx; 1849 u_int16_t bge_len; 1850 u_int16_t bge_type; 1851 u_int16_t bge_flags; 1852 u_int16_t bge_ip_csum; 1853 u_int16_t bge_tcp_udp_csum; 1854 u_int16_t bge_error_flag; 1855 u_int16_t bge_vlan_tag; 1856 #else 1857 u_int16_t bge_len; 1858 u_int16_t bge_idx; 1859 u_int16_t bge_flags; 1860 u_int16_t bge_type; 1861 u_int16_t bge_tcp_udp_csum; 1862 u_int16_t bge_ip_csum; 1863 u_int16_t bge_vlan_tag; 1864 u_int16_t bge_error_flag; 1865 #endif 1866 u_int32_t bge_rsvd; 1867 u_int32_t bge_opaque; 1868 }; 1869 1870 #define BGE_RXBDFLAG_END 0x0004 1871 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1872 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1873 #define BGE_RXBDFLAG_ERROR 0x0400 1874 #define BGE_RXBDFLAG_MINI_RING 0x0800 1875 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1876 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1877 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1878 1879 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1880 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1881 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1882 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1883 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1884 #define BGE_RXERRFLAG_RUNT 0x0020 1885 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1886 #define BGE_RXERRFLAG_GIANT 0x0080 1887 1888 struct bge_sts_idx { 1889 #if BYTE_ORDER == BIG_ENDIAN 1890 u_int16_t bge_tx_cons_idx; 1891 u_int16_t bge_rx_prod_idx; 1892 #else 1893 u_int16_t bge_rx_prod_idx; 1894 u_int16_t bge_tx_cons_idx; 1895 #endif 1896 }; 1897 1898 struct bge_status_block { 1899 u_int32_t bge_status; 1900 u_int32_t bge_rsvd0; 1901 #if BYTE_ORDER == BIG_ENDIAN 1902 u_int16_t bge_rx_std_cons_idx; 1903 u_int16_t bge_rx_jumbo_cons_idx; 1904 u_int16_t bge_rsvd1; 1905 u_int16_t bge_rx_mini_cons_idx; 1906 #else 1907 u_int16_t bge_rx_jumbo_cons_idx; 1908 u_int16_t bge_rx_std_cons_idx; 1909 u_int16_t bge_rx_mini_cons_idx; 1910 u_int16_t bge_rsvd1; 1911 #endif 1912 struct bge_sts_idx bge_idx[16]; 1913 }; 1914 1915 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1916 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1917 1918 #define BGE_STATFLAG_UPDATED 0x00000001 1919 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1920 #define BGE_STATFLAG_ERROR 0x00000004 1921 1922 1923 /* 1924 * Broadcom Vendor ID 1925 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1926 * even though they're now manufactured by Broadcom) 1927 */ 1928 #define BCOM_VENDORID 0x14E4 1929 #define BCOM_DEVICEID_BCM5700 0x1644 1930 #define BCOM_DEVICEID_BCM5701 0x1645 1931 1932 /* 1933 * Alteon AceNIC PCI vendor/device ID. 1934 */ 1935 #define ALT_VENDORID 0x12AE 1936 #define ALT_DEVICEID_ACENIC 0x0001 1937 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 1938 #define ALT_DEVICEID_BCM5700 0x0003 1939 #define ALT_DEVICEID_BCM5701 0x0004 1940 1941 /* 1942 * 3Com 3c985 PCI vendor/device ID. 1943 */ 1944 #define TC_VENDORID 0x10B7 1945 #define TC_DEVICEID_3C985 0x0001 1946 #define TC_DEVICEID_3C996 0x0003 1947 1948 /* 1949 * SysKonnect PCI vendor ID 1950 */ 1951 #define SK_VENDORID 0x1148 1952 #define SK_DEVICEID_ALTIMA 0x4400 1953 #define SK_SUBSYSID_9D21 0x4421 1954 #define SK_SUBSYSID_9D41 0x4441 1955 1956 /* 1957 * Altima PCI vendor/device ID. 1958 */ 1959 #define ALTIMA_VENDORID 0x173b 1960 #define ALTIMA_DEVICE_AC1000 0x03e8 1961 1962 /* 1963 * Offset of MAC address inside EEPROM. 1964 */ 1965 #define BGE_EE_MAC_OFFSET 0x7C 1966 #define BGE_EE_HWCFG_OFFSET 0xC8 1967 1968 #define BGE_HWCFG_VOLTAGE 0x00000003 1969 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1970 #define BGE_HWCFG_MEDIA 0x00000030 1971 1972 #define BGE_VOLTAGE_1POINT3 0x00000000 1973 #define BGE_VOLTAGE_1POINT8 0x00000001 1974 1975 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 1976 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1977 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 1978 1979 #define BGE_MEDIA_UNSPEC 0x00000000 1980 #define BGE_MEDIA_COPPER 0x00000010 1981 #define BGE_MEDIA_FIBER 0x00000020 1982 1983 #define BGE_PCI_READ_CMD 0x06000000 1984 #define BGE_PCI_WRITE_CMD 0x70000000 1985 1986 #define BGE_TICKS_PER_SEC 1000000 1987 1988 /* 1989 * Ring size constants. 1990 */ 1991 #define BGE_EVENT_RING_CNT 256 1992 #define BGE_CMD_RING_CNT 64 1993 #define BGE_STD_RX_RING_CNT 512 1994 #define BGE_JUMBO_RX_RING_CNT 256 1995 #define BGE_MINI_RX_RING_CNT 1024 1996 #define BGE_RETURN_RING_CNT 1024 1997 #define BGE_RETURN_RING_CNT_5705 512 1998 1999 /* 2000 * Possible TX ring sizes. 2001 */ 2002 #define BGE_TX_RING_CNT_128 128 2003 #define BGE_TX_RING_BASE_128 0x3800 2004 2005 #define BGE_TX_RING_CNT_256 256 2006 #define BGE_TX_RING_BASE_256 0x3000 2007 2008 #define BGE_TX_RING_CNT_512 512 2009 #define BGE_TX_RING_BASE_512 0x2000 2010 2011 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2012 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2013 2014 /* 2015 * Tigon III statistics counters. 2016 */ 2017 2018 /* Stats counters access through registers */ 2019 struct bge_mac_stats_regs { 2020 u_int32_t ifHCOutOctets; 2021 u_int32_t Reserved0; 2022 u_int32_t etherStatsCollisions; 2023 u_int32_t outXonSent; 2024 u_int32_t outXoffSent; 2025 u_int32_t Reserved1; 2026 u_int32_t dot3StatsInternalMacTransmitErrors; 2027 u_int32_t dot3StatsSingleCollisionFrames; 2028 u_int32_t dot3StatsMultipleCollisionFrames; 2029 u_int32_t dot3StatsDeferredTransmissions; 2030 u_int32_t Reserved2; 2031 u_int32_t dot3StatsExcessiveCollisions; 2032 u_int32_t dot3StatsLateCollisions; 2033 u_int32_t Reserved3[14]; 2034 u_int32_t ifHCOutUcastPkts; 2035 u_int32_t ifHCOutMulticastPkts; 2036 u_int32_t ifHCOutBroadcastPkts; 2037 u_int32_t Reserved4[2]; 2038 u_int32_t ifHCInOctets; 2039 u_int32_t Reserved5; 2040 u_int32_t etherStatsFragments; 2041 u_int32_t ifHCInUcastPkts; 2042 u_int32_t ifHCInMulticastPkts; 2043 u_int32_t ifHCInBroadcastPkts; 2044 u_int32_t dot3StatsFCSErrors; 2045 u_int32_t dot3StatsAlignmentErrors; 2046 u_int32_t xonPauseFramesReceived; 2047 u_int32_t xoffPauseFramesReceived; 2048 u_int32_t macControlFramesReceived; 2049 u_int32_t xoffStateEntered; 2050 u_int32_t dot3StatsFramesTooLong; 2051 u_int32_t etherStatsJabbers; 2052 u_int32_t etherStatsUndersizePkts; 2053 }; 2054 2055 struct bge_stats { 2056 u_int8_t Reserved0[256]; 2057 2058 /* Statistics maintained by Receive MAC. */ 2059 bge_hostaddr ifHCInOctets; 2060 bge_hostaddr Reserved1; 2061 bge_hostaddr etherStatsFragments; 2062 bge_hostaddr ifHCInUcastPkts; 2063 bge_hostaddr ifHCInMulticastPkts; 2064 bge_hostaddr ifHCInBroadcastPkts; 2065 bge_hostaddr dot3StatsFCSErrors; 2066 bge_hostaddr dot3StatsAlignmentErrors; 2067 bge_hostaddr xonPauseFramesReceived; 2068 bge_hostaddr xoffPauseFramesReceived; 2069 bge_hostaddr macControlFramesReceived; 2070 bge_hostaddr xoffStateEntered; 2071 bge_hostaddr dot3StatsFramesTooLong; 2072 bge_hostaddr etherStatsJabbers; 2073 bge_hostaddr etherStatsUndersizePkts; 2074 bge_hostaddr inRangeLengthError; 2075 bge_hostaddr outRangeLengthError; 2076 bge_hostaddr etherStatsPkts64Octets; 2077 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2078 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2079 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2080 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2081 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2082 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2083 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2084 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2085 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2086 2087 bge_hostaddr Unused1[37]; 2088 2089 /* Statistics maintained by Transmit MAC. */ 2090 bge_hostaddr ifHCOutOctets; 2091 bge_hostaddr Reserved2; 2092 bge_hostaddr etherStatsCollisions; 2093 bge_hostaddr outXonSent; 2094 bge_hostaddr outXoffSent; 2095 bge_hostaddr flowControlDone; 2096 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2097 bge_hostaddr dot3StatsSingleCollisionFrames; 2098 bge_hostaddr dot3StatsMultipleCollisionFrames; 2099 bge_hostaddr dot3StatsDeferredTransmissions; 2100 bge_hostaddr Reserved3; 2101 bge_hostaddr dot3StatsExcessiveCollisions; 2102 bge_hostaddr dot3StatsLateCollisions; 2103 bge_hostaddr dot3Collided2Times; 2104 bge_hostaddr dot3Collided3Times; 2105 bge_hostaddr dot3Collided4Times; 2106 bge_hostaddr dot3Collided5Times; 2107 bge_hostaddr dot3Collided6Times; 2108 bge_hostaddr dot3Collided7Times; 2109 bge_hostaddr dot3Collided8Times; 2110 bge_hostaddr dot3Collided9Times; 2111 bge_hostaddr dot3Collided10Times; 2112 bge_hostaddr dot3Collided11Times; 2113 bge_hostaddr dot3Collided12Times; 2114 bge_hostaddr dot3Collided13Times; 2115 bge_hostaddr dot3Collided14Times; 2116 bge_hostaddr dot3Collided15Times; 2117 bge_hostaddr ifHCOutUcastPkts; 2118 bge_hostaddr ifHCOutMulticastPkts; 2119 bge_hostaddr ifHCOutBroadcastPkts; 2120 bge_hostaddr dot3StatsCarrierSenseErrors; 2121 bge_hostaddr ifOutDiscards; 2122 bge_hostaddr ifOutErrors; 2123 2124 bge_hostaddr Unused2[31]; 2125 2126 /* Statistics maintained by Receive List Placement. */ 2127 bge_hostaddr COSIfHCInPkts[16]; 2128 bge_hostaddr COSFramesDroppedDueToFilters; 2129 bge_hostaddr nicDmaWriteQueueFull; 2130 bge_hostaddr nicDmaWriteHighPriQueueFull; 2131 bge_hostaddr nicNoMoreRxBDs; 2132 bge_hostaddr ifInDiscards; 2133 bge_hostaddr ifInErrors; 2134 bge_hostaddr nicRecvThresholdHit; 2135 2136 bge_hostaddr Unused3[9]; 2137 2138 /* Statistics maintained by Send Data Initiator. */ 2139 bge_hostaddr COSIfHCOutPkts[16]; 2140 bge_hostaddr nicDmaReadQueueFull; 2141 bge_hostaddr nicDmaReadHighPriQueueFull; 2142 bge_hostaddr nicSendDataCompQueueFull; 2143 2144 /* Statistics maintained by Host Coalescing. */ 2145 bge_hostaddr nicRingSetSendProdIndex; 2146 bge_hostaddr nicRingStatusUpdate; 2147 bge_hostaddr nicInterrupts; 2148 bge_hostaddr nicAvoidedInterrupts; 2149 bge_hostaddr nicSendThresholdHit; 2150 2151 u_int8_t Reserved4[320]; 2152 }; 2153 2154 /* 2155 * Tigon general information block. This resides in host memory 2156 * and contains the status counters, ring control blocks and 2157 * producer pointers. 2158 */ 2159 2160 struct bge_gib { 2161 struct bge_stats bge_stats; 2162 struct bge_rcb bge_tx_rcb[16]; 2163 struct bge_rcb bge_std_rx_rcb; 2164 struct bge_rcb bge_jumbo_rx_rcb; 2165 struct bge_rcb bge_mini_rx_rcb; 2166 struct bge_rcb bge_return_rcb; 2167 }; 2168 2169 /* 2170 * NOTE! On the Alpha, we have an alignment constraint. 2171 * The first thing in the packet is a 14-byte Ethernet header. 2172 * This means that the packet is misaligned. To compensate, 2173 * we actually offset the data 2 bytes into the cluster. This 2174 * alignes the packet after the Ethernet header at a 32-bit 2175 * boundary. 2176 */ 2177 2178 #define ETHER_ALIGN 2 2179 2180 #define BGE_FRAMELEN ETHER_MAX_LEN 2181 #define BGE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_CRC_LEN) 2182 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2183 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2184 #define BGE_PAGE_SIZE PAGE_SIZE 2185 #define BGE_MIN_FRAMELEN 60 2186 2187 /* 2188 * Other utility macros. 2189 */ 2190 #define BGE_INC(x, y) (x) = (x + 1) % y 2191 2192 /* 2193 * Vital product data and structures. 2194 */ 2195 #define BGE_VPD_FLAG 0x8000 2196 2197 /* VPD structures */ 2198 struct vpd_res { 2199 u_int8_t vr_id; 2200 u_int8_t vr_len; 2201 u_int8_t vr_pad; 2202 }; 2203 2204 struct vpd_key { 2205 char vk_key[2]; 2206 u_int8_t vk_len; 2207 }; 2208 2209 #define VPD_RES_ID 0x82 /* ID string */ 2210 #define VPD_RES_READ 0x90 /* start of read only area */ 2211 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2212 #define VPD_RES_END 0x78 /* end tag */ 2213 2214 2215 /* 2216 * Register access macros. The Tigon always uses memory mapped register 2217 * accesses and all registers must be accessed with 32 bit operations. 2218 */ 2219 2220 #define CSR_WRITE_4(sc, reg, val) \ 2221 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2222 2223 #define CSR_READ_4(sc, reg) \ 2224 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2225 2226 #define BGE_SETBIT(sc, reg, x) \ 2227 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2228 #define BGE_CLRBIT(sc, reg, x) \ 2229 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2230 2231 #define PCI_SETBIT(pc, tag, reg, x) \ 2232 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 2233 #define PCI_CLRBIT(pc, tag, reg, x) \ 2234 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 2235 2236 /* 2237 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2238 * values are tuneable. They control the actual amount of buffers 2239 * allocated for the standard, mini and jumbo receive rings. 2240 */ 2241 2242 #define BGE_SSLOTS 256 2243 #define BGE_MSLOTS 256 2244 #define BGE_JSLOTS 384 2245 #define BGE_RSLOTS 256 2246 2247 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2248 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2249 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2250 #define BGE_JPAGESZ PAGE_SIZE 2251 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2252 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2253 2254 /* 2255 * Ring structures. Most of these reside in host memory and we tell 2256 * the NIC where they are via the ring control blocks. The exceptions 2257 * are the tx and command rings, which live in NIC memory and which 2258 * we access via the shared memory window. 2259 */ 2260 struct bge_ring_data { 2261 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2262 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2263 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2264 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2265 struct bge_status_block bge_status_block; 2266 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2267 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2268 struct bge_gib bge_info; 2269 }; 2270 2271 #define BGE_RING_DMA_ADDR(sc, offset) \ 2272 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2273 offsetof(struct bge_ring_data, offset)) 2274 2275 /* 2276 * Number of DMA segments in a TxCB. Note that this is carefully 2277 * chosen to make the total struct size an even power of two. It's 2278 * critical that no TxCB be split across a page boundary since 2279 * no attempt is made to allocate physically contiguous memory. 2280 * 2281 */ 2282 #if 0 /* pre-TSO values */ 2283 #define BGE_TXDMA_MAX ETHER_MAX_LEN_JUMBO 2284 #ifdef _LP64 2285 #define BGE_NTXSEG 30 2286 #else 2287 #define BGE_NTXSEG 31 2288 #endif 2289 #else /* TSO values */ 2290 #define BGE_TXDMA_MAX (round_page(IP_MAXPACKET)) /* for TSO */ 2291 #ifdef _LP64 2292 #define BGE_NTXSEG 120 /* XXX just a guess */ 2293 #else 2294 #define BGE_NTXSEG 124 /* XXX just a guess */ 2295 #endif 2296 #endif /* TSO values */ 2297 2298 2299 /* 2300 * Mbuf pointers. We need these to keep track of the virtual addresses 2301 * of our mbuf chains since we can only convert from physical to virtual, 2302 * not the other way around. 2303 */ 2304 struct bge_chain_data { 2305 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2306 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2307 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2308 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2309 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2310 bus_dmamap_t bge_rx_jumbo_map; 2311 /* Stick the jumbo mem management stuff here too. */ 2312 caddr_t bge_jslots[BGE_JSLOTS]; 2313 void *bge_jumbo_buf; 2314 }; 2315 2316 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 2317 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2318 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2319 2320 struct bge_type { 2321 u_int16_t bge_vid; 2322 u_int16_t bge_did; 2323 char *bge_name; 2324 }; 2325 2326 #define BGE_HWREV_TIGON 0x01 2327 #define BGE_HWREV_TIGON_II 0x02 2328 #define BGE_TIMEOUT 1000 2329 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2330 2331 struct bge_jpool_entry { 2332 int slot; 2333 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2334 }; 2335 2336 struct bge_bcom_hack { 2337 int reg; 2338 int val; 2339 }; 2340 2341 struct txdmamap_pool_entry { 2342 bus_dmamap_t dmamap; 2343 SLIST_ENTRY(txdmamap_pool_entry) link; 2344 }; 2345 2346 /* 2347 * Flags for bge_flags. 2348 */ 2349 #define BGE_TXRING_VALID 0x0001 2350 #define BGE_RXRING_VALID 0x0002 2351 #define BGE_JUMBO_RXRING_VALID 0x0004 2352 2353 struct bge_softc { 2354 struct device bge_dev; 2355 struct ethercom ethercom; /* interface info */ 2356 bus_space_handle_t bge_bhandle; 2357 bus_space_tag_t bge_btag; 2358 void *bge_intrhand; 2359 struct pci_attach_args bge_pa; 2360 struct mii_data bge_mii; 2361 struct ifmedia bge_ifmedia; /* media info */ 2362 u_int8_t bge_extram; /* has external SSRAM */ 2363 u_int8_t bge_tbi; 2364 u_int8_t bge_rx_alignment_bug; 2365 u_int8_t bge_pcie; /* on a PCI Express port */ 2366 u_int32_t bge_return_ring_cnt; 2367 u_int32_t bge_tx_prodidx; 2368 bus_dma_tag_t bge_dmatag; 2369 u_int32_t bge_chipid; 2370 u_int32_t bge_quirks; 2371 u_int32_t bge_local_ctrl_reg; 2372 struct bge_ring_data *bge_rdata; /* rings */ 2373 struct bge_chain_data bge_cdata; /* mbufs */ 2374 bus_dmamap_t bge_ring_map; 2375 u_int16_t bge_tx_saved_considx; 2376 u_int16_t bge_rx_saved_considx; 2377 u_int16_t bge_ev_saved_considx; 2378 u_int16_t bge_std; /* current std ring head */ 2379 u_int16_t bge_jumbo; /* current jumo ring head */ 2380 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2381 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2382 u_int32_t bge_stat_ticks; 2383 u_int32_t bge_rx_coal_ticks; 2384 u_int32_t bge_tx_coal_ticks; 2385 u_int32_t bge_rx_max_coal_bds; 2386 u_int32_t bge_tx_max_coal_bds; 2387 u_int32_t bge_tx_buf_ratio; 2388 int bge_if_flags; 2389 int bge_flags; 2390 int bge_flowflags; 2391 #ifdef BGE_EVENT_COUNTERS 2392 /* 2393 * Event counters. 2394 */ 2395 struct evcnt bge_ev_intr; /* interrupts */ 2396 struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ 2397 struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ 2398 struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ 2399 struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ 2400 struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ 2401 struct evcnt bge_ev_xoffentered;/* XOFF state entered */ 2402 #endif /* BGE_EVENT_COUNTERS */ 2403 int bge_txcnt; 2404 int bge_link; 2405 struct callout bge_timeout; 2406 char *bge_vpd_prodname; 2407 char *bge_vpd_readonly; 2408 int bge_pending_rxintr_change; 2409 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2410 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2411 void *bge_powerhook; 2412 struct pci_conf_state bge_pciconf; 2413 }; 2414
Indexes created Mon Sep 29 21:09:56 GMT 2025