if_bgereg.h revision 1.4
1 /* $NetBSD: if_bgereg.h,v 1.4 2002/07/13 22:31:18 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.4 2002/04/04 06:01:31 wpaul Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 77 #define BGE_UNMAPPED 0x00001000 78 #define BGE_UNMAPPED_END 0x00001FFF 79 #define BGE_DMA_DESCRIPTORS 0x00002000 80 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 81 #define BGE_SEND_RING_1_TO_4 0x00004000 82 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 83 84 /* Mappings for internal memory configuration */ 85 #define BGE_STD_RX_RINGS 0x00006000 86 #define BGE_STD_RX_RINGS_END 0x00006FFF 87 #define BGE_JUMBO_RX_RINGS 0x00007000 88 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 89 #define BGE_BUFFPOOL_1 0x00008000 90 #define BGE_BUFFPOOL_1_END 0x0000FFFF 91 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 92 #define BGE_BUFFPOOL_2_END 0x00017FFF 93 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_3_END 0x0001FFFF 95 96 /* Mappings for external SSRAM configurations */ 97 #define BGE_SEND_RING_5_TO_6 0x00006000 98 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 99 #define BGE_SEND_RING_7_TO_8 0x00007000 100 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 101 #define BGE_SEND_RING_9_TO_16 0x00008000 102 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 103 #define BGE_EXT_STD_RX_RINGS 0x0000C000 104 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 105 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 106 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 107 #define BGE_MINI_RX_RINGS 0x0000E000 108 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 109 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 110 #define BGE_AVAIL_REGION1_END 0x00017FFF 111 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION2_END 0x0001FFFF 113 #define BGE_EXT_SSRAM 0x00020000 114 #define BGE_EXT_SSRAM_END 0x000FFFFF 115 116 117 /* 118 * BCM570x register offsets. These are memory mapped registers 119 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 120 * Each register must be accessed using 32 bit operations. 121 * 122 * All registers are accessed through a 32K shared memory block. 123 * The first group of registers are actually copies of the PCI 124 * configuration space registers. 125 */ 126 127 /* 128 * PCI registers defined in the PCI 2.2 spec. 129 */ 130 #define BGE_PCI_VID 0x00 131 #define BGE_PCI_DID 0x02 132 #define BGE_PCI_CMD 0x04 133 #define BGE_PCI_STS 0x06 134 #define BGE_PCI_REV 0x08 135 #define BGE_PCI_CLASS 0x09 136 #define BGE_PCI_CACHESZ 0x0C 137 #define BGE_PCI_LATTIMER 0x0D 138 #define BGE_PCI_HDRTYPE 0x0E 139 #define BGE_PCI_BIST 0x0F 140 #define BGE_PCI_BAR0 0x10 141 #define BGE_PCI_BAR1 0x14 142 #define BGE_PCI_SUBSYS 0x2C 143 #define BGE_PCI_SUBVID 0x2E 144 #define BGE_PCI_ROMBASE 0x30 145 #define BGE_PCI_CAPPTR 0x34 146 #define BGE_PCI_INTLINE 0x3C 147 #define BGE_PCI_INTPIN 0x3D 148 #define BGE_PCI_MINGNT 0x3E 149 #define BGE_PCI_MAXLAT 0x3F 150 #define BGE_PCI_PCIXCAP 0x40 151 #define BGE_PCI_NEXTPTR_PM 0x41 152 #define BGE_PCI_PCIX_CMD 0x42 153 #define BGE_PCI_PCIX_STS 0x44 154 #define BGE_PCI_PWRMGMT_CAPID 0x48 155 #define BGE_PCI_NEXTPTR_VPD 0x49 156 #define BGE_PCI_PWRMGMT_CAPS 0x4A 157 #define BGE_PCI_PWRMGMT_CMD 0x4C 158 #define BGE_PCI_PWRMGMT_STS 0x4D 159 #define BGE_PCI_PWRMGMT_DATA 0x4F 160 #define BGE_PCI_VPD_CAPID 0x50 161 #define BGE_PCI_NEXTPTR_MSI 0x51 162 #define BGE_PCI_VPD_ADDR 0x52 163 #define BGE_PCI_VPD_DATA 0x54 164 #define BGE_PCI_MSI_CAPID 0x58 165 #define BGE_PCI_NEXTPTR_NONE 0x59 166 #define BGE_PCI_MSI_CTL 0x5A 167 #define BGE_PCI_MSI_ADDR_HI 0x5C 168 #define BGE_PCI_MSI_ADDR_LO 0x60 169 #define BGE_PCI_MSI_DATA 0x64 170 171 /* 172 * PCI registers specific to the BCM570x family. 173 */ 174 #define BGE_PCI_MISC_CTL 0x68 175 #define BGE_PCI_DMA_RW_CTL 0x6C 176 #define BGE_PCI_PCISTATE 0x70 177 #define BGE_PCI_CLKCTL 0x74 178 #define BGE_PCI_REG_BASEADDR 0x78 179 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 180 #define BGE_PCI_REG_DATA 0x80 181 #define BGE_PCI_MEMWIN_DATA 0x84 182 #define BGE_PCI_MODECTL 0x88 183 #define BGE_PCI_MISC_CFG 0x8C 184 #define BGE_PCI_MISC_LOCALCTL 0x90 185 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 186 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 187 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 188 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 189 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 190 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 191 #define BGE_PCI_ISR_MBX_HI 0xB0 192 #define BGE_PCI_ISR_MBX_LO 0xB4 193 194 /* PCI Misc. Host control register */ 195 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 196 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 197 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 198 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 199 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 200 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 201 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 202 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 203 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 204 205 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 206 #if BYTE_ORDER == LITTLE_ENDIAN 207 #define BGE_DMA_SWAP_OPTIONS \ 208 BGE_MODECTL_WORDSWAP_NONFRAME| \ 209 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 210 #else 211 #define BGE_DMA_SWAP_OPTIONS \ 212 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 213 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 214 #endif 215 216 #define BGE_INIT \ 217 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 218 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 219 220 #define BGE_ASICREV_TIGON_I 0x40000000 221 #define BGE_ASICREV_TIGON_II 0x60000000 222 #define BGE_ASICREV_BCM5700_A0 0x70000000 223 #define BGE_ASICREV_BCM5700_A1 0x70010000 224 #define BGE_ASICREV_BCM5700_B0 0x71000000 225 #define BGE_ASICREV_BCM5700_B1 0x71020000 226 #define BGE_ASICREV_BCM5700_B2 0x71030000 227 #define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 228 #define BGE_ASICREV_BCM5700_C0 0x72000000 229 #define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 230 #define BGE_ASICREV_BCM5701_B0 0x01000000 231 #define BGE_ASICREV_BCM5701_B2 0x01020000 232 #define BGE_ASICREV_BCM5701_B5 0x01050000 233 #define BGE_ASICREV_BCM5703_A0 0x10000000 234 #define BGE_ASICREV_BCM5703_A1 0x10010000 235 #define BGE_ASICREV_BCM5703_A2 0x10020000 236 237 /* PCI DMA Read/Write Control register */ 238 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 239 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 240 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 241 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 242 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 243 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 244 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 245 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 246 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 247 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 248 249 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 250 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 251 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 252 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 253 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 254 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 255 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 256 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 257 258 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 259 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 260 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 261 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 262 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 263 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 264 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 265 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 266 267 /* 268 * PCI state register -- note, this register is read only 269 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 270 * register is set. 271 */ 272 #define BGE_PCISTATE_FORCE_RESET 0x00000001 273 #define BGE_PCISTATE_INTR_STATE 0x00000002 274 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 275 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 276 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 277 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 278 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 279 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 280 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 281 282 /* 283 * PCI Clock Control register -- note, this register is read only 284 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 285 * register is set. 286 */ 287 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 288 #define BGE_PCICLOCKCTL_M66EN 0x00000080 289 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 290 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 291 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 292 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 293 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 294 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 295 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 296 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 297 298 299 #ifndef PCIM_CMD_MWIEN 300 #define PCIM_CMD_MWIEN 0x0010 301 #endif 302 303 /* 304 * High priority mailbox registers 305 * Each mailbox is 64-bits wide, though we only use the 306 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 307 * first. The NIC will load the mailbox after the lower 32 bit word 308 * has been updated. 309 */ 310 #define BGE_MBX_IRQ0_HI 0x0200 311 #define BGE_MBX_IRQ0_LO 0x0204 312 #define BGE_MBX_IRQ1_HI 0x0208 313 #define BGE_MBX_IRQ1_LO 0x020C 314 #define BGE_MBX_IRQ2_HI 0x0210 315 #define BGE_MBX_IRQ2_LO 0x0214 316 #define BGE_MBX_IRQ3_HI 0x0218 317 #define BGE_MBX_IRQ3_LO 0x021C 318 #define BGE_MBX_GEN0_HI 0x0220 319 #define BGE_MBX_GEN0_LO 0x0224 320 #define BGE_MBX_GEN1_HI 0x0228 321 #define BGE_MBX_GEN1_LO 0x022C 322 #define BGE_MBX_GEN2_HI 0x0230 323 #define BGE_MBX_GEN2_LO 0x0234 324 #define BGE_MBX_GEN3_HI 0x0228 325 #define BGE_MBX_GEN3_LO 0x022C 326 #define BGE_MBX_GEN4_HI 0x0240 327 #define BGE_MBX_GEN4_LO 0x0244 328 #define BGE_MBX_GEN5_HI 0x0248 329 #define BGE_MBX_GEN5_LO 0x024C 330 #define BGE_MBX_GEN6_HI 0x0250 331 #define BGE_MBX_GEN6_LO 0x0254 332 #define BGE_MBX_GEN7_HI 0x0258 333 #define BGE_MBX_GEN7_LO 0x025C 334 #define BGE_MBX_RELOAD_STATS_HI 0x0260 335 #define BGE_MBX_RELOAD_STATS_LO 0x0264 336 #define BGE_MBX_RX_STD_PROD_HI 0x0268 337 #define BGE_MBX_RX_STD_PROD_LO 0x026C 338 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 339 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 340 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 341 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 342 #define BGE_MBX_RX_CONS0_HI 0x0280 343 #define BGE_MBX_RX_CONS0_LO 0x0284 344 #define BGE_MBX_RX_CONS1_HI 0x0288 345 #define BGE_MBX_RX_CONS1_LO 0x028C 346 #define BGE_MBX_RX_CONS2_HI 0x0290 347 #define BGE_MBX_RX_CONS2_LO 0x0294 348 #define BGE_MBX_RX_CONS3_HI 0x0298 349 #define BGE_MBX_RX_CONS3_LO 0x029C 350 #define BGE_MBX_RX_CONS4_HI 0x02A0 351 #define BGE_MBX_RX_CONS4_LO 0x02A4 352 #define BGE_MBX_RX_CONS5_HI 0x02A8 353 #define BGE_MBX_RX_CONS5_LO 0x02AC 354 #define BGE_MBX_RX_CONS6_HI 0x02B0 355 #define BGE_MBX_RX_CONS6_LO 0x02B4 356 #define BGE_MBX_RX_CONS7_HI 0x02B8 357 #define BGE_MBX_RX_CONS7_LO 0x02BC 358 #define BGE_MBX_RX_CONS8_HI 0x02C0 359 #define BGE_MBX_RX_CONS8_LO 0x02C4 360 #define BGE_MBX_RX_CONS9_HI 0x02C8 361 #define BGE_MBX_RX_CONS9_LO 0x02CC 362 #define BGE_MBX_RX_CONS10_HI 0x02D0 363 #define BGE_MBX_RX_CONS10_LO 0x02D4 364 #define BGE_MBX_RX_CONS11_HI 0x02D8 365 #define BGE_MBX_RX_CONS11_LO 0x02DC 366 #define BGE_MBX_RX_CONS12_HI 0x02E0 367 #define BGE_MBX_RX_CONS12_LO 0x02E4 368 #define BGE_MBX_RX_CONS13_HI 0x02E8 369 #define BGE_MBX_RX_CONS13_LO 0x02EC 370 #define BGE_MBX_RX_CONS14_HI 0x02F0 371 #define BGE_MBX_RX_CONS14_LO 0x02F4 372 #define BGE_MBX_RX_CONS15_HI 0x02F8 373 #define BGE_MBX_RX_CONS15_LO 0x02FC 374 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 375 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 376 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 377 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 378 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 379 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 380 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 381 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 382 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 383 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 384 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 385 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 386 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 387 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 388 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 389 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 390 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 391 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 392 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 393 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 394 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 395 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 396 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 397 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 398 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 399 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 400 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 401 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 402 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 403 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 404 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 405 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 406 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 407 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 408 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 409 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 410 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 411 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 412 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 413 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 414 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 415 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 416 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 417 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 418 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 419 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 420 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 421 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 422 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 423 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 424 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 425 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 426 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 427 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 428 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 429 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 430 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 431 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 432 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 433 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 434 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 435 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 436 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 437 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 438 439 #define BGE_TX_RINGS_MAX 4 440 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 441 #define BGE_RX_RINGS_MAX 16 442 443 /* Ethernet MAC control registers */ 444 #define BGE_MAC_MODE 0x0400 445 #define BGE_MAC_STS 0x0404 446 #define BGE_MAC_EVT_ENB 0x0408 447 #define BGE_MAC_LED_CTL 0x040C 448 #define BGE_MAC_ADDR1_LO 0x0410 449 #define BGE_MAC_ADDR1_HI 0x0414 450 #define BGE_MAC_ADDR2_LO 0x0418 451 #define BGE_MAC_ADDR2_HI 0x041C 452 #define BGE_MAC_ADDR3_LO 0x0420 453 #define BGE_MAC_ADDR3_HI 0x0424 454 #define BGE_MAC_ADDR4_LO 0x0428 455 #define BGE_MAC_ADDR4_HI 0x042C 456 #define BGE_WOL_PATPTR 0x0430 457 #define BGE_WOL_PATCFG 0x0434 458 #define BGE_TX_RANDOM_BACKOFF 0x0438 459 #define BGE_RX_MTU 0x043C 460 #define BGE_GBIT_PCS_TEST 0x0440 461 #define BGE_TX_TBI_AUTONEG 0x0444 462 #define BGE_RX_TBI_AUTONEG 0x0448 463 #define BGE_MI_COMM 0x044C 464 #define BGE_MI_STS 0x0450 465 #define BGE_MI_MODE 0x0454 466 #define BGE_AUTOPOLL_STS 0x0458 467 #define BGE_TX_MODE 0x045C 468 #define BGE_TX_STS 0x0460 469 #define BGE_TX_LENGTHS 0x0464 470 #define BGE_RX_MODE 0x0468 471 #define BGE_RX_STS 0x046C 472 #define BGE_MAR0 0x0470 473 #define BGE_MAR1 0x0474 474 #define BGE_MAR2 0x0478 475 #define BGE_MAR3 0x047C 476 #define BGE_RX_BD_RULES_CTL0 0x0480 477 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 478 #define BGE_RX_BD_RULES_CTL1 0x0488 479 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 480 #define BGE_RX_BD_RULES_CTL2 0x0490 481 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 482 #define BGE_RX_BD_RULES_CTL3 0x0498 483 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 484 #define BGE_RX_BD_RULES_CTL4 0x04A0 485 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 486 #define BGE_RX_BD_RULES_CTL5 0x04A8 487 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 488 #define BGE_RX_BD_RULES_CTL6 0x04B0 489 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 490 #define BGE_RX_BD_RULES_CTL7 0x04B8 491 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 492 #define BGE_RX_BD_RULES_CTL8 0x04C0 493 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 494 #define BGE_RX_BD_RULES_CTL9 0x04C8 495 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 496 #define BGE_RX_BD_RULES_CTL10 0x04D0 497 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 498 #define BGE_RX_BD_RULES_CTL11 0x04D8 499 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 500 #define BGE_RX_BD_RULES_CTL12 0x04E0 501 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 502 #define BGE_RX_BD_RULES_CTL13 0x04E8 503 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 504 #define BGE_RX_BD_RULES_CTL14 0x04F0 505 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 506 #define BGE_RX_BD_RULES_CTL15 0x04F8 507 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 508 #define BGE_RX_RULES_CFG 0x0500 509 #define BGE_RX_STATS 0x0800 510 #define BGE_TX_STATS 0x0880 511 512 /* Ethernet MAC Mode register */ 513 #define BGE_MACMODE_RESET 0x00000001 514 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 515 #define BGE_MACMODE_PORTMODE 0x0000000C 516 #define BGE_MACMODE_LOOPBACK 0x00000010 517 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 518 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 519 #define BGE_MACMODE_MAX_DEFER 0x00000200 520 #define BGE_MACMODE_LINK_POLARITY 0x00000400 521 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 522 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 523 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 524 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 525 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 526 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 527 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 528 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 529 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 530 #define BGE_MACMODE_MIP_ENB 0x00100000 531 #define BGE_MACMODE_TXDMA_ENB 0x00200000 532 #define BGE_MACMODE_RXDMA_ENB 0x00400000 533 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 534 535 #define BGE_PORTMODE_NONE 0x00000000 536 #define BGE_PORTMODE_MII 0x00000004 537 #define BGE_PORTMODE_GMII 0x00000008 538 #define BGE_PORTMODE_TBI 0x0000000C 539 540 /* MAC Status register */ 541 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 542 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 543 #define BGE_MACSTAT_RX_CFG 0x00000004 544 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 545 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 546 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 547 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 548 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 549 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 550 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 551 #define BGE_MACSTAT_ODI_ERROR 0x02000000 552 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 553 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 554 555 /* MAC Event Enable Register */ 556 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 557 #define BGE_EVTENB_LINK_CHANGED 0x00001000 558 #define BGE_EVTENB_MI_COMPLETE 0x00400000 559 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 560 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 561 #define BGE_EVTENB_ODI_ERROR 0x02000000 562 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 563 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 564 565 /* LED Control Register */ 566 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 567 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 568 #define BGE_LEDCTL_100MBPS_LED 0x00000004 569 #define BGE_LEDCTL_10MBPS_LED 0x00000008 570 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 571 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 572 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 573 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 574 #define BGE_LEDCTL_100MBPS_STS 0x00000100 575 #define BGE_LEDCTL_10MBPS_STS 0x00000200 576 #define BGE_LEDCTL_TRADLED_STS 0x00000400 577 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 578 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 579 580 /* TX backoff seed register */ 581 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 582 583 /* Autopoll status register */ 584 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 585 586 /* Transmit MAC mode register */ 587 #define BGE_TXMODE_RESET 0x00000001 588 #define BGE_TXMODE_ENABLE 0x00000002 589 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 590 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 591 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 592 593 /* Transmit MAC status register */ 594 #define BGE_TXSTAT_RX_XOFFED 0x00000001 595 #define BGE_TXSTAT_SENT_XOFF 0x00000002 596 #define BGE_TXSTAT_SENT_XON 0x00000004 597 #define BGE_TXSTAT_LINK_UP 0x00000008 598 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 599 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 600 601 /* Transmit MAC lengths register */ 602 #define BGE_TXLEN_SLOTTIME 0x000000FF 603 #define BGE_TXLEN_IPG 0x00000F00 604 #define BGE_TXLEN_CRS 0x00003000 605 606 /* Receive MAC mode register */ 607 #define BGE_RXMODE_RESET 0x00000001 608 #define BGE_RXMODE_ENABLE 0x00000002 609 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 610 #define BGE_RXMODE_RX_GIANTS 0x00000020 611 #define BGE_RXMODE_RX_RUNTS 0x00000040 612 #define BGE_RXMODE_8022_LENCHECK 0x00000080 613 #define BGE_RXMODE_RX_PROMISC 0x00000100 614 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 615 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 616 617 /* Receive MAC status register */ 618 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 619 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 620 #define BGE_RXSTAT_RCVD_XON 0x00000004 621 622 /* Receive Rules Control register */ 623 #define BGE_RXRULECTL_OFFSET 0x000000FF 624 #define BGE_RXRULECTL_CLASS 0x00001F00 625 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 626 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 627 #define BGE_RXRULECTL_MAP 0x01000000 628 #define BGE_RXRULECTL_DISCARD 0x02000000 629 #define BGE_RXRULECTL_MASK 0x04000000 630 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 631 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 632 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 633 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 634 635 /* Receive Rules Mask register */ 636 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 637 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 638 639 /* MI communication register */ 640 #define BGE_MICOMM_DATA 0x0000FFFF 641 #define BGE_MICOMM_REG 0x001F0000 642 #define BGE_MICOMM_PHY 0x03E00000 643 #define BGE_MICOMM_CMD 0x0C000000 644 #define BGE_MICOMM_READFAIL 0x10000000 645 #define BGE_MICOMM_BUSY 0x20000000 646 647 #define BGE_MIREG(x) ((x & 0x1F) << 16) 648 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 649 #define BGE_MICMD_WRITE 0x04000000 650 #define BGE_MICMD_READ 0x08000000 651 652 /* MI status register */ 653 #define BGE_MISTS_LINK 0x00000001 654 #define BGE_MISTS_10MBPS 0x00000002 655 656 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 657 #define BGE_MIMODE_AUTOPOLL 0x00000010 658 #define BGE_MIMODE_CLKCNT 0x001F0000 659 660 661 /* 662 * Send data initiator control registers. 663 */ 664 #define BGE_SDI_MODE 0x0C00 665 #define BGE_SDI_STATUS 0x0C04 666 #define BGE_SDI_STATS_CTL 0x0C08 667 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 668 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 669 #define BGE_LOCSTATS_COS0 0x0C80 670 #define BGE_LOCSTATS_COS1 0x0C84 671 #define BGE_LOCSTATS_COS2 0x0C88 672 #define BGE_LOCSTATS_COS3 0x0C8C 673 #define BGE_LOCSTATS_COS4 0x0C90 674 #define BGE_LOCSTATS_COS5 0x0C84 675 #define BGE_LOCSTATS_COS6 0x0C98 676 #define BGE_LOCSTATS_COS7 0x0C9C 677 #define BGE_LOCSTATS_COS8 0x0CA0 678 #define BGE_LOCSTATS_COS9 0x0CA4 679 #define BGE_LOCSTATS_COS10 0x0CA8 680 #define BGE_LOCSTATS_COS11 0x0CAC 681 #define BGE_LOCSTATS_COS12 0x0CB0 682 #define BGE_LOCSTATS_COS13 0x0CB4 683 #define BGE_LOCSTATS_COS14 0x0CB8 684 #define BGE_LOCSTATS_COS15 0x0CBC 685 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 686 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 687 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 688 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 689 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 690 #define BGE_LOCSTATS_IRQS 0x0CD4 691 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 692 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 693 694 /* Send Data Initiator mode register */ 695 #define BGE_SDIMODE_RESET 0x00000001 696 #define BGE_SDIMODE_ENABLE 0x00000002 697 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 698 699 /* Send Data Initiator stats register */ 700 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 701 702 /* Send Data Initiator stats control register */ 703 #define BGE_SDISTATSCTL_ENABLE 0x00000001 704 #define BGE_SDISTATSCTL_FASTER 0x00000002 705 #define BGE_SDISTATSCTL_CLEAR 0x00000004 706 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 707 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 708 709 /* 710 * Send Data Completion Control registers 711 */ 712 #define BGE_SDC_MODE 0x1000 713 #define BGE_SDC_STATUS 0x1004 714 715 /* Send Data completion mode register */ 716 #define BGE_SDCMODE_RESET 0x00000001 717 #define BGE_SDCMODE_ENABLE 0x00000002 718 #define BGE_SDCMODE_ATTN 0x00000004 719 720 /* Send Data completion status register */ 721 #define BGE_SDCSTAT_ATTN 0x00000004 722 723 /* 724 * Send BD Ring Selector Control registers 725 */ 726 #define BGE_SRS_MODE 0x1400 727 #define BGE_SRS_STATUS 0x1404 728 #define BGE_SRS_HWDIAG 0x1408 729 #define BGE_SRS_LOC_NIC_CONS0 0x1440 730 #define BGE_SRS_LOC_NIC_CONS1 0x1444 731 #define BGE_SRS_LOC_NIC_CONS2 0x1448 732 #define BGE_SRS_LOC_NIC_CONS3 0x144C 733 #define BGE_SRS_LOC_NIC_CONS4 0x1450 734 #define BGE_SRS_LOC_NIC_CONS5 0x1454 735 #define BGE_SRS_LOC_NIC_CONS6 0x1458 736 #define BGE_SRS_LOC_NIC_CONS7 0x145C 737 #define BGE_SRS_LOC_NIC_CONS8 0x1460 738 #define BGE_SRS_LOC_NIC_CONS9 0x1464 739 #define BGE_SRS_LOC_NIC_CONS10 0x1468 740 #define BGE_SRS_LOC_NIC_CONS11 0x146C 741 #define BGE_SRS_LOC_NIC_CONS12 0x1470 742 #define BGE_SRS_LOC_NIC_CONS13 0x1474 743 #define BGE_SRS_LOC_NIC_CONS14 0x1478 744 #define BGE_SRS_LOC_NIC_CONS15 0x147C 745 746 /* Send BD Ring Selector Mode register */ 747 #define BGE_SRSMODE_RESET 0x00000001 748 #define BGE_SRSMODE_ENABLE 0x00000002 749 #define BGE_SRSMODE_ATTN 0x00000004 750 751 /* Send BD Ring Selector Status register */ 752 #define BGE_SRSSTAT_ERROR 0x00000004 753 754 /* Send BD Ring Selector HW Diagnostics register */ 755 #define BGE_SRSHWDIAG_STATE 0x0000000F 756 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 757 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 758 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 759 760 /* 761 * Send BD Initiator Selector Control registers 762 */ 763 #define BGE_SBDI_MODE 0x1800 764 #define BGE_SBDI_STATUS 0x1804 765 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 766 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 767 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 768 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 769 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 770 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 771 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 772 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 773 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 774 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 775 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 776 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 777 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 778 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 779 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 780 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 781 782 /* Send BD Initiator Mode register */ 783 #define BGE_SBDIMODE_RESET 0x00000001 784 #define BGE_SBDIMODE_ENABLE 0x00000002 785 #define BGE_SBDIMODE_ATTN 0x00000004 786 787 /* Send BD Initiator Status register */ 788 #define BGE_SBDISTAT_ERROR 0x00000004 789 790 /* 791 * Send BD Completion Control registers 792 */ 793 #define BGE_SBDC_MODE 0x1C00 794 #define BGE_SBDC_STATUS 0x1C04 795 796 /* Send BD Completion Control Mode register */ 797 #define BGE_SBDCMODE_RESET 0x00000001 798 #define BGE_SBDCMODE_ENABLE 0x00000002 799 #define BGE_SBDCMODE_ATTN 0x00000004 800 801 /* Send BD Completion Control Status register */ 802 #define BGE_SBDCSTAT_ATTN 0x00000004 803 804 /* 805 * Receive List Placement Control registers 806 */ 807 #define BGE_RXLP_MODE 0x2000 808 #define BGE_RXLP_STATUS 0x2004 809 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 810 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 811 #define BGE_RXLP_CFG 0x2010 812 #define BGE_RXLP_STATS_CTL 0x2014 813 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 814 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 815 #define BGE_RXLP_HEAD0 0x2100 816 #define BGE_RXLP_TAIL0 0x2104 817 #define BGE_RXLP_COUNT0 0x2108 818 #define BGE_RXLP_HEAD1 0x2110 819 #define BGE_RXLP_TAIL1 0x2114 820 #define BGE_RXLP_COUNT1 0x2118 821 #define BGE_RXLP_HEAD2 0x2120 822 #define BGE_RXLP_TAIL2 0x2124 823 #define BGE_RXLP_COUNT2 0x2128 824 #define BGE_RXLP_HEAD3 0x2130 825 #define BGE_RXLP_TAIL3 0x2134 826 #define BGE_RXLP_COUNT3 0x2138 827 #define BGE_RXLP_HEAD4 0x2140 828 #define BGE_RXLP_TAIL4 0x2144 829 #define BGE_RXLP_COUNT4 0x2148 830 #define BGE_RXLP_HEAD5 0x2150 831 #define BGE_RXLP_TAIL5 0x2154 832 #define BGE_RXLP_COUNT5 0x2158 833 #define BGE_RXLP_HEAD6 0x2160 834 #define BGE_RXLP_TAIL6 0x2164 835 #define BGE_RXLP_COUNT6 0x2168 836 #define BGE_RXLP_HEAD7 0x2170 837 #define BGE_RXLP_TAIL7 0x2174 838 #define BGE_RXLP_COUNT7 0x2178 839 #define BGE_RXLP_HEAD8 0x2180 840 #define BGE_RXLP_TAIL8 0x2184 841 #define BGE_RXLP_COUNT8 0x2188 842 #define BGE_RXLP_HEAD9 0x2190 843 #define BGE_RXLP_TAIL9 0x2194 844 #define BGE_RXLP_COUNT9 0x2198 845 #define BGE_RXLP_HEAD10 0x21A0 846 #define BGE_RXLP_TAIL10 0x21A4 847 #define BGE_RXLP_COUNT10 0x21A8 848 #define BGE_RXLP_HEAD11 0x21B0 849 #define BGE_RXLP_TAIL11 0x21B4 850 #define BGE_RXLP_COUNT11 0x21B8 851 #define BGE_RXLP_HEAD12 0x21C0 852 #define BGE_RXLP_TAIL12 0x21C4 853 #define BGE_RXLP_COUNT12 0x21C8 854 #define BGE_RXLP_HEAD13 0x21D0 855 #define BGE_RXLP_TAIL13 0x21D4 856 #define BGE_RXLP_COUNT13 0x21D8 857 #define BGE_RXLP_HEAD14 0x21E0 858 #define BGE_RXLP_TAIL14 0x21E4 859 #define BGE_RXLP_COUNT14 0x21E8 860 #define BGE_RXLP_HEAD15 0x21F0 861 #define BGE_RXLP_TAIL15 0x21F4 862 #define BGE_RXLP_COUNT15 0x21F8 863 #define BGE_RXLP_LOCSTAT_COS0 0x2200 864 #define BGE_RXLP_LOCSTAT_COS1 0x2204 865 #define BGE_RXLP_LOCSTAT_COS2 0x2208 866 #define BGE_RXLP_LOCSTAT_COS3 0x220C 867 #define BGE_RXLP_LOCSTAT_COS4 0x2210 868 #define BGE_RXLP_LOCSTAT_COS5 0x2214 869 #define BGE_RXLP_LOCSTAT_COS6 0x2218 870 #define BGE_RXLP_LOCSTAT_COS7 0x221C 871 #define BGE_RXLP_LOCSTAT_COS8 0x2220 872 #define BGE_RXLP_LOCSTAT_COS9 0x2224 873 #define BGE_RXLP_LOCSTAT_COS10 0x2228 874 #define BGE_RXLP_LOCSTAT_COS11 0x222C 875 #define BGE_RXLP_LOCSTAT_COS12 0x2230 876 #define BGE_RXLP_LOCSTAT_COS13 0x2234 877 #define BGE_RXLP_LOCSTAT_COS14 0x2238 878 #define BGE_RXLP_LOCSTAT_COS15 0x223C 879 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 880 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 881 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 882 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 883 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 884 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 885 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 886 887 888 /* Receive List Placement mode register */ 889 #define BGE_RXLPMODE_RESET 0x00000001 890 #define BGE_RXLPMODE_ENABLE 0x00000002 891 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 892 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 893 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 894 895 /* Receive List Placement Status register */ 896 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 897 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 898 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 899 900 /* 901 * Receive Data and Receive BD Initiator Control Registers 902 */ 903 #define BGE_RDBDI_MODE 0x2400 904 #define BGE_RDBDI_STATUS 0x2404 905 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 906 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 907 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 908 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 909 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 910 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 911 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 912 #define BGE_RX_STD_RCB_NICADDR 0x245C 913 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 914 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 915 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 916 #define BGE_RX_MINI_RCB_NICADDR 0x246C 917 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 918 #define BGE_RDBDI_STD_RX_CONS 0x2474 919 #define BGE_RDBDI_MINI_RX_CONS 0x2478 920 #define BGE_RDBDI_RETURN_PROD0 0x2480 921 #define BGE_RDBDI_RETURN_PROD1 0x2484 922 #define BGE_RDBDI_RETURN_PROD2 0x2488 923 #define BGE_RDBDI_RETURN_PROD3 0x248C 924 #define BGE_RDBDI_RETURN_PROD4 0x2490 925 #define BGE_RDBDI_RETURN_PROD5 0x2494 926 #define BGE_RDBDI_RETURN_PROD6 0x2498 927 #define BGE_RDBDI_RETURN_PROD7 0x249C 928 #define BGE_RDBDI_RETURN_PROD8 0x24A0 929 #define BGE_RDBDI_RETURN_PROD9 0x24A4 930 #define BGE_RDBDI_RETURN_PROD10 0x24A8 931 #define BGE_RDBDI_RETURN_PROD11 0x24AC 932 #define BGE_RDBDI_RETURN_PROD12 0x24B0 933 #define BGE_RDBDI_RETURN_PROD13 0x24B4 934 #define BGE_RDBDI_RETURN_PROD14 0x24B8 935 #define BGE_RDBDI_RETURN_PROD15 0x24BC 936 #define BGE_RDBDI_HWDIAG 0x24C0 937 938 939 /* Receive Data and Receive BD Initiator Mode register */ 940 #define BGE_RDBDIMODE_RESET 0x00000001 941 #define BGE_RDBDIMODE_ENABLE 0x00000002 942 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 943 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 944 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 945 946 /* Receive Data and Receive BD Initiator Status register */ 947 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 948 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 949 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 950 951 952 /* 953 * Receive Data Completion Control registers 954 */ 955 #define BGE_RDC_MODE 0x2800 956 957 /* Receive Data Completion Mode register */ 958 #define BGE_RDCMODE_RESET 0x00000001 959 #define BGE_RDCMODE_ENABLE 0x00000002 960 #define BGE_RDCMODE_ATTN 0x00000004 961 962 /* 963 * Receive BD Initiator Control registers 964 */ 965 #define BGE_RBDI_MODE 0x2C00 966 #define BGE_RBDI_STATUS 0x2C04 967 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 968 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 969 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 970 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 971 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 972 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 973 974 /* Receive BD Initiator Mode register */ 975 #define BGE_RBDIMODE_RESET 0x00000001 976 #define BGE_RBDIMODE_ENABLE 0x00000002 977 #define BGE_RBDIMODE_ATTN 0x00000004 978 979 /* Receive BD Initiator Status register */ 980 #define BGE_RBDISTAT_ATTN 0x00000004 981 982 /* 983 * Receive BD Completion Control registers 984 */ 985 #define BGE_RBDC_MODE 0x3000 986 #define BGE_RBDC_STATUS 0x3004 987 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 988 #define BGE_RBDC_STD_BD_PROD 0x300C 989 #define BGE_RBDC_MINI_BD_PROD 0x3010 990 991 /* Receive BD completion mode register */ 992 #define BGE_RBDCMODE_RESET 0x00000001 993 #define BGE_RBDCMODE_ENABLE 0x00000002 994 #define BGE_RBDCMODE_ATTN 0x00000004 995 996 /* Receive BD completion status register */ 997 #define BGE_RBDCSTAT_ERROR 0x00000004 998 999 /* 1000 * Receive List Selector Control registers 1001 */ 1002 #define BGE_RXLS_MODE 0x3400 1003 #define BGE_RXLS_STATUS 0x3404 1004 1005 /* Receive List Selector Mode register */ 1006 #define BGE_RXLSMODE_RESET 0x00000001 1007 #define BGE_RXLSMODE_ENABLE 0x00000002 1008 #define BGE_RXLSMODE_ATTN 0x00000004 1009 1010 /* Receive List Selector Status register */ 1011 #define BGE_RXLSSTAT_ERROR 0x00000004 1012 1013 /* 1014 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1015 */ 1016 #define BGE_MBCF_MODE 0x3800 1017 #define BGE_MBCF_STATUS 0x3804 1018 1019 /* Mbuf Cluster Free mode register */ 1020 #define BGE_MBCFMODE_RESET 0x00000001 1021 #define BGE_MBCFMODE_ENABLE 0x00000002 1022 #define BGE_MBCFMODE_ATTN 0x00000004 1023 1024 /* Mbuf Cluster Free status register */ 1025 #define BGE_MBCFSTAT_ERROR 0x00000004 1026 1027 /* 1028 * Host Coalescing Control registers 1029 */ 1030 #define BGE_HCC_MODE 0x3C00 1031 #define BGE_HCC_STATUS 0x3C04 1032 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1033 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1034 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1035 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1036 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1037 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1038 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1039 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1040 #define BGE_HCC_STATS_TICKS 0x3C28 1041 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1042 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1043 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1044 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1045 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1046 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1047 #define BGE_FLOW_ATTN 0x3C48 1048 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1049 #define BGE_HCC_STD_BD_CONS 0x3C54 1050 #define BGE_HCC_MINI_BD_CONS 0x3C58 1051 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1052 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1053 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1054 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1055 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1056 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1057 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1058 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1059 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1060 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1061 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1062 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1063 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1064 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1065 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1066 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1067 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1068 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1069 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1070 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1071 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1072 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1073 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1074 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1075 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1076 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1077 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1078 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1079 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1080 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1081 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1082 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1083 1084 1085 /* Host coalescing mode register */ 1086 #define BGE_HCCMODE_RESET 0x00000001 1087 #define BGE_HCCMODE_ENABLE 0x00000002 1088 #define BGE_HCCMODE_ATTN 0x00000004 1089 #define BGE_HCCMODE_COAL_NOW 0x00000008 1090 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1091 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1092 1093 #define BGE_STATBLKSZ_FULL 0x00000000 1094 #define BGE_STATBLKSZ_64BYTE 0x00000080 1095 #define BGE_STATBLKSZ_32BYTE 0x00000100 1096 1097 /* Host coalescing status register */ 1098 #define BGE_HCCSTAT_ERROR 0x00000004 1099 1100 /* Flow attention register */ 1101 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1102 #define BGE_FLOWATTN_MEMARB 0x00000080 1103 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1104 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1105 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1106 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1107 #define BGE_FLOWATTN_RDBDI 0x00080000 1108 #define BGE_FLOWATTN_RXLS 0x00100000 1109 #define BGE_FLOWATTN_RXLP 0x00200000 1110 #define BGE_FLOWATTN_RBDC 0x00400000 1111 #define BGE_FLOWATTN_RBDI 0x00800000 1112 #define BGE_FLOWATTN_SDC 0x08000000 1113 #define BGE_FLOWATTN_SDI 0x10000000 1114 #define BGE_FLOWATTN_SRS 0x20000000 1115 #define BGE_FLOWATTN_SBDC 0x40000000 1116 #define BGE_FLOWATTN_SBDI 0x80000000 1117 1118 /* 1119 * Memory arbiter registers 1120 */ 1121 #define BGE_MARB_MODE 0x4000 1122 #define BGE_MARB_STATUS 0x4004 1123 #define BGE_MARB_TRAPADDR_HI 0x4008 1124 #define BGE_MARB_TRAPADDR_LO 0x400C 1125 1126 /* Memory arbiter mode register */ 1127 #define BGE_MARBMODE_RESET 0x00000001 1128 #define BGE_MARBMODE_ENABLE 0x00000002 1129 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1130 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1131 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1132 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1133 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1134 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1135 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1136 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1137 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1138 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1139 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1140 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1141 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1142 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1143 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1144 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1145 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1146 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1147 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1148 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1149 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1150 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1151 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1152 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1153 1154 /* Memory arbiter status register */ 1155 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1156 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1157 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1158 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1159 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1160 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1161 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1162 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1163 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1164 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1165 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1166 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1167 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1168 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1169 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1170 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1171 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1172 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1173 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1174 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1175 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1176 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1177 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1178 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1179 1180 /* 1181 * Buffer manager control registers 1182 */ 1183 #define BGE_BMAN_MODE 0x4400 1184 #define BGE_BMAN_STATUS 0x4404 1185 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1186 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1187 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1188 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1189 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1190 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1191 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1192 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1193 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1194 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1195 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1196 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1197 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1198 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1199 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1200 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1201 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1202 #define BGE_BMAN_HWDIAG_1 0x444C 1203 #define BGE_BMAN_HWDIAG_2 0x4450 1204 #define BGE_BMAN_HWDIAG_3 0x4454 1205 1206 /* Buffer manager mode register */ 1207 #define BGE_BMANMODE_RESET 0x00000001 1208 #define BGE_BMANMODE_ENABLE 0x00000002 1209 #define BGE_BMANMODE_ATTN 0x00000004 1210 #define BGE_BMANMODE_TESTMODE 0x00000008 1211 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1212 1213 /* Buffer manager status register */ 1214 #define BGE_BMANSTAT_ERRO 0x00000004 1215 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1216 1217 1218 /* 1219 * Read DMA Control registers 1220 */ 1221 #define BGE_RDMA_MODE 0x4800 1222 #define BGE_RDMA_STATUS 0x4804 1223 1224 /* Read DMA mode register */ 1225 #define BGE_RDMAMODE_RESET 0x00000001 1226 #define BGE_RDMAMODE_ENABLE 0x00000002 1227 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1228 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1229 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1230 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1231 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1232 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1233 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1234 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1235 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1236 1237 /* Read DMA status register */ 1238 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1239 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1240 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1241 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1242 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1243 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1244 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1245 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1246 1247 /* 1248 * Write DMA control registers 1249 */ 1250 #define BGE_WDMA_MODE 0x4C00 1251 #define BGE_WDMA_STATUS 0x4C04 1252 1253 /* Write DMA mode register */ 1254 #define BGE_WDMAMODE_RESET 0x00000001 1255 #define BGE_WDMAMODE_ENABLE 0x00000002 1256 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1257 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1258 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1259 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1260 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1261 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1262 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1263 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1264 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1265 1266 /* Write DMA status register */ 1267 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1268 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1269 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1270 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1271 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1272 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1273 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1274 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1275 1276 1277 /* 1278 * RX CPU registers 1279 */ 1280 #define BGE_RXCPU_MODE 0x5000 1281 #define BGE_RXCPU_STATUS 0x5004 1282 #define BGE_RXCPU_PC 0x501C 1283 1284 /* RX CPU mode register */ 1285 #define BGE_RXCPUMODE_RESET 0x00000001 1286 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1287 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1288 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1289 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1290 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1291 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1292 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1293 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1294 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1295 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1296 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1297 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1298 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1299 1300 /* RX CPU status register */ 1301 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1302 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1303 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1304 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1305 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1306 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1307 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1308 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1309 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1310 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1311 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1312 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1313 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1314 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1315 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1316 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1317 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1318 1319 1320 /* 1321 * TX CPU registers 1322 */ 1323 #define BGE_TXCPU_MODE 0x5400 1324 #define BGE_TXCPU_STATUS 0x5404 1325 #define BGE_TXCPU_PC 0x541C 1326 1327 /* TX CPU mode register */ 1328 #define BGE_TXCPUMODE_RESET 0x00000001 1329 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1330 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1331 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1332 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1333 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1334 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1335 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1336 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1337 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1338 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1339 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1340 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1341 1342 /* TX CPU status register */ 1343 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1344 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1345 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1346 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1347 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1348 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1349 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1350 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1351 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1352 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1353 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1354 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1355 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1356 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1357 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1358 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1359 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1360 1361 1362 /* 1363 * Low priority mailbox registers 1364 */ 1365 #define BGE_LPMBX_IRQ0_HI 0x5800 1366 #define BGE_LPMBX_IRQ0_LO 0x5804 1367 #define BGE_LPMBX_IRQ1_HI 0x5808 1368 #define BGE_LPMBX_IRQ1_LO 0x580C 1369 #define BGE_LPMBX_IRQ2_HI 0x5810 1370 #define BGE_LPMBX_IRQ2_LO 0x5814 1371 #define BGE_LPMBX_IRQ3_HI 0x5818 1372 #define BGE_LPMBX_IRQ3_LO 0x581C 1373 #define BGE_LPMBX_GEN0_HI 0x5820 1374 #define BGE_LPMBX_GEN0_LO 0x5824 1375 #define BGE_LPMBX_GEN1_HI 0x5828 1376 #define BGE_LPMBX_GEN1_LO 0x582C 1377 #define BGE_LPMBX_GEN2_HI 0x5830 1378 #define BGE_LPMBX_GEN2_LO 0x5834 1379 #define BGE_LPMBX_GEN3_HI 0x5828 1380 #define BGE_LPMBX_GEN3_LO 0x582C 1381 #define BGE_LPMBX_GEN4_HI 0x5840 1382 #define BGE_LPMBX_GEN4_LO 0x5844 1383 #define BGE_LPMBX_GEN5_HI 0x5848 1384 #define BGE_LPMBX_GEN5_LO 0x584C 1385 #define BGE_LPMBX_GEN6_HI 0x5850 1386 #define BGE_LPMBX_GEN6_LO 0x5854 1387 #define BGE_LPMBX_GEN7_HI 0x5858 1388 #define BGE_LPMBX_GEN7_LO 0x585C 1389 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1390 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1391 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1392 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1393 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1394 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1395 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1396 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1397 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1398 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1399 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1400 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1401 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1402 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1403 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1404 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1405 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1406 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1407 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1408 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1409 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1410 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1411 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1412 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1413 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1414 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1415 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1416 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1417 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1418 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1419 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1420 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1421 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1422 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1423 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1424 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1425 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1426 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1427 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1428 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1429 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1430 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1431 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1432 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1433 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1434 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1435 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1436 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1437 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1438 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1439 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1440 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1441 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1442 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1443 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1444 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1445 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1446 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1447 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1448 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1449 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1450 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1451 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1452 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1453 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1454 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1455 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1456 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1457 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1458 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1459 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1460 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1461 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1462 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1463 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1464 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1465 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1466 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1467 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1468 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1469 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1470 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1471 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1472 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1473 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1474 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1475 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1476 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1477 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1478 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1479 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1480 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1481 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1482 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1483 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1484 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1485 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1486 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1487 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1488 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1489 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1490 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1491 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1492 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1493 1494 /* 1495 * Flow throw Queue reset register 1496 */ 1497 #define BGE_FTQ_RESET 0x5C00 1498 1499 #define BGE_FTQRESET_DMAREAD 0x00000002 1500 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1501 #define BGE_FTQRESET_DMADONE 0x00000010 1502 #define BGE_FTQRESET_SBDC 0x00000020 1503 #define BGE_FTQRESET_SDI 0x00000040 1504 #define BGE_FTQRESET_WDMA 0x00000080 1505 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1506 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1507 #define BGE_FTQRESET_SDC 0x00000400 1508 #define BGE_FTQRESET_HCC 0x00000800 1509 #define BGE_FTQRESET_TXFIFO 0x00001000 1510 #define BGE_FTQRESET_MBC 0x00002000 1511 #define BGE_FTQRESET_RBDC 0x00004000 1512 #define BGE_FTQRESET_RXLP 0x00008000 1513 #define BGE_FTQRESET_RDBDI 0x00010000 1514 #define BGE_FTQRESET_RDC 0x00020000 1515 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1516 1517 /* 1518 * Message Signaled Interrupt registers 1519 */ 1520 #define BGE_MSI_MODE 0x6000 1521 #define BGE_MSI_STATUS 0x6004 1522 #define BGE_MSI_FIFOACCESS 0x6008 1523 1524 /* MSI mode register */ 1525 #define BGE_MSIMODE_RESET 0x00000001 1526 #define BGE_MSIMODE_ENABLE 0x00000002 1527 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1528 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1529 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1530 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1531 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1532 1533 /* MSI status register */ 1534 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1535 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1536 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1537 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1538 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1539 1540 1541 /* 1542 * DMA Completion registers 1543 */ 1544 #define BGE_DMAC_MODE 0x6400 1545 1546 /* DMA Completion mode register */ 1547 #define BGE_DMACMODE_RESET 0x00000001 1548 #define BGE_DMACMODE_ENABLE 0x00000002 1549 1550 1551 /* 1552 * General control registers. 1553 */ 1554 #define BGE_MODE_CTL 0x6800 1555 #define BGE_MISC_CFG 0x6804 1556 #define BGE_MISC_LOCAL_CTL 0x6808 1557 #define BGE_EE_ADDR 0x6838 1558 #define BGE_EE_DATA 0x683C 1559 #define BGE_EE_CTL 0x6840 1560 #define BGE_MDI_CTL 0x6844 1561 #define BGE_EE_DELAY 0x6848 1562 1563 /* Mode control register */ 1564 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1565 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1566 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1567 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1568 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1569 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1570 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1571 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1572 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1573 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1574 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1575 #define BGE_MODECTL_STACKUP 0x00010000 1576 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1577 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1578 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1579 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1580 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1581 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1582 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1583 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1584 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1585 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1586 1587 /* Misc. config register */ 1588 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1589 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1590 1591 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1592 1593 /* Misc. Local Control */ 1594 #define BGE_MLC_INTR_STATE 0x00000001 1595 #define BGE_MLC_INTR_CLR 0x00000002 1596 #define BGE_MLC_INTR_SET 0x00000004 1597 #define BGE_MLC_INTR_ONATTN 0x00000008 1598 #define BGE_MLC_MISCIO_IN0 0x00000100 1599 #define BGE_MLC_MISCIO_IN1 0x00000200 1600 #define BGE_MLC_MISCIO_IN2 0x00000400 1601 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1602 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1603 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1604 #define BGE_MLC_MISCIO_OUT0 0x00004000 1605 #define BGE_MLC_MISCIO_OUT1 0x00008000 1606 #define BGE_MLC_MISCIO_OUT2 0x00010000 1607 #define BGE_MLC_EXTRAM_ENB 0x00020000 1608 #define BGE_MLC_SRAM_SIZE 0x001C0000 1609 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1610 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1611 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1612 #define BGE_MLC_AUTO_EEPROM 0x01000000 1613 1614 #define BGE_SSRAMSIZE_256KB 0x00000000 1615 #define BGE_SSRAMSIZE_512KB 0x00040000 1616 #define BGE_SSRAMSIZE_1MB 0x00080000 1617 #define BGE_SSRAMSIZE_2MB 0x000C0000 1618 #define BGE_SSRAMSIZE_4MB 0x00100000 1619 #define BGE_SSRAMSIZE_8MB 0x00140000 1620 #define BGE_SSRAMSIZE_16M 0x00180000 1621 1622 /* EEPROM address register */ 1623 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1624 #define BGE_EEADDR_HALFCLK 0x01FF0000 1625 #define BGE_EEADDR_START 0x02000000 1626 #define BGE_EEADDR_DEVID 0x1C000000 1627 #define BGE_EEADDR_RESET 0x20000000 1628 #define BGE_EEADDR_DONE 0x40000000 1629 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1630 1631 #define BGE_EEDEVID(x) ((x & 7) << 26) 1632 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1633 #define BGE_HALFCLK_384SCL 0x60 1634 #define BGE_EE_READCMD \ 1635 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1636 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1637 #define BGE_EE_WRCMD \ 1638 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1639 BGE_EEADDR_START|BGE_EEADDR_DONE) 1640 1641 /* EEPROM Control register */ 1642 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1643 #define BGE_EECTL_CLKOUT 0x00000002 1644 #define BGE_EECTL_CLKIN 0x00000004 1645 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1646 #define BGE_EECTL_DATAOUT 0x00000010 1647 #define BGE_EECTL_DATAIN 0x00000020 1648 1649 /* MDI (MII/GMII) access register */ 1650 #define BGE_MDI_DATA 0x00000001 1651 #define BGE_MDI_DIR 0x00000002 1652 #define BGE_MDI_SEL 0x00000004 1653 #define BGE_MDI_CLK 0x00000008 1654 1655 #define BGE_MEMWIN_START 0x00008000 1656 #define BGE_MEMWIN_END 0x0000FFFF 1657 1658 1659 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1660 do { \ 1661 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1662 (0xFFFF0000 & x)); \ 1663 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1664 } while(0) 1665 1666 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1667 do { \ 1668 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1669 (0xFFFF0000 & x)); \ 1670 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1671 } while(0) 1672 1673 /* 1674 * This magic number is used to prevent PXE restart when we 1675 * issue a software reset. We write this magic number to the 1676 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1677 * code from running. 1678 */ 1679 #define BGE_MAGIC_NUMBER 0x4B657654 1680 1681 #if BYTE_ORDER == LITTLE_ENDIAN 1682 typedef struct { 1683 u_int32_t bge_addr_hi; 1684 u_int32_t bge_addr_lo; 1685 } bge_hostaddr; 1686 #else 1687 typedef struct { 1688 u_int32_t bge_addr_hi; 1689 u_int32_t bge_addr_lo; 1690 } bge_hostaddr; 1691 #endif 1692 1693 #define BGE_HOSTADDR(x) (x).bge_addr_lo 1694 1695 static __inline void 1696 bge_set_hostaddr(bge_hostaddr *x, bus_addr_t y) 1697 { 1698 x->bge_addr_lo = y & 0xffffffff; 1699 if (sizeof (bus_addr_t) == 8) 1700 x->bge_addr_hi = (u_int64_t)y >> 32; 1701 else 1702 x->bge_addr_hi = 0; 1703 } 1704 1705 /* Ring control block structure */ 1706 struct bge_rcb { 1707 bge_hostaddr bge_hostaddr; 1708 #if BYTE_ORDER == BIG_ENDIAN 1709 u_int16_t bge_max_len; 1710 u_int16_t bge_flags; 1711 #else 1712 u_int16_t bge_flags; 1713 u_int16_t bge_max_len; 1714 #endif 1715 u_int32_t bge_nicaddr; 1716 }; 1717 1718 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1719 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1720 rcb + offsetof(struct bge_rcb, offset), val) 1721 1722 #define RCB_WRITE_2(sc, rcb, offset, val) \ 1723 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 1724 rcb + offsetof(struct bge_rcb, offset), val) 1725 1726 struct bge_rcb_opaque { 1727 u_int32_t bge_reg0; 1728 u_int32_t bge_reg1; 1729 u_int32_t bge_reg2; 1730 u_int32_t bge_reg3; 1731 }; 1732 1733 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1734 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1735 1736 struct bge_tx_bd { 1737 bge_hostaddr bge_addr; 1738 #if BYTE_ORDER == BIG_ENDIAN 1739 u_int16_t bge_len; 1740 u_int16_t bge_flags; 1741 u_int16_t bge_rsvd; 1742 u_int16_t bge_vlan_tag; 1743 #else 1744 u_int16_t bge_flags; 1745 u_int16_t bge_len; 1746 u_int16_t bge_vlan_tag; 1747 u_int16_t bge_rsvd; 1748 #endif 1749 }; 1750 1751 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1752 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1753 #define BGE_TXBDFLAG_END 0x0004 1754 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1755 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1756 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1757 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1758 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1759 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1760 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1761 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1762 #define BGE_TXBDFLAG_NO_CRC 0x8000 1763 1764 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1765 BGE_SEND_RING_1_TO_4 + \ 1766 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1767 1768 struct bge_rx_bd { 1769 bge_hostaddr bge_addr; 1770 #if BYTE_ORDER == BIG_ENDIAN 1771 u_int16_t bge_idx; 1772 u_int16_t bge_len; 1773 u_int16_t bge_type; 1774 u_int16_t bge_flags; 1775 u_int16_t bge_ip_csum; 1776 u_int16_t bge_tcp_udp_csum; 1777 u_int16_t bge_error_flag; 1778 u_int16_t bge_vlan_tag; 1779 #else 1780 u_int16_t bge_len; 1781 u_int16_t bge_idx; 1782 u_int16_t bge_flags; 1783 u_int16_t bge_type; 1784 u_int16_t bge_tcp_udp_csum; 1785 u_int16_t bge_ip_csum; 1786 u_int16_t bge_vlan_tag; 1787 u_int16_t bge_error_flag; 1788 #endif 1789 u_int32_t bge_rsvd; 1790 u_int32_t bge_opaque; 1791 }; 1792 1793 #define BGE_RXBDFLAG_END 0x0004 1794 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1795 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1796 #define BGE_RXBDFLAG_ERROR 0x0400 1797 #define BGE_RXBDFLAG_MINI_RING 0x0800 1798 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1799 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1800 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1801 1802 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1803 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1804 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1805 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1806 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1807 #define BGE_RXERRFLAG_RUNT 0x0020 1808 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1809 #define BGE_RXERRFLAG_GIANT 0x0080 1810 1811 struct bge_sts_idx { 1812 #if BYTE_ORDER == BIG_ENDIAN 1813 u_int16_t bge_tx_cons_idx; 1814 u_int16_t bge_rx_prod_idx; 1815 #else 1816 u_int16_t bge_rx_prod_idx; 1817 u_int16_t bge_tx_cons_idx; 1818 #endif 1819 }; 1820 1821 struct bge_status_block { 1822 u_int32_t bge_status; 1823 u_int32_t bge_rsvd0; 1824 #if BYTE_ORDER == BIG_ENDIAN 1825 u_int16_t bge_rx_std_cons_idx; 1826 u_int16_t bge_rx_jumbo_cons_idx; 1827 u_int16_t bge_rsvd1; 1828 u_int16_t bge_rx_mini_cons_idx; 1829 #else 1830 u_int16_t bge_rx_jumbo_cons_idx; 1831 u_int16_t bge_rx_std_cons_idx; 1832 u_int16_t bge_rx_mini_cons_idx; 1833 u_int16_t bge_rsvd1; 1834 #endif 1835 struct bge_sts_idx bge_idx[16]; 1836 }; 1837 1838 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1839 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1840 1841 #define BGE_STATFLAG_UPDATED 0x00000001 1842 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1843 #define BGE_STATFLAG_ERROR 0x00000004 1844 1845 1846 /* 1847 * Broadcom Vendor ID 1848 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1849 * even though they're now manufactured by Broadcom) 1850 */ 1851 #define BCOM_VENDORID 0x14E4 1852 #define BCOM_DEVICEID_BCM5700 0x1644 1853 #define BCOM_DEVICEID_BCM5701 0x1645 1854 1855 /* 1856 * Alteon AceNIC PCI vendor/device ID. 1857 */ 1858 #define ALT_VENDORID 0x12AE 1859 #define ALT_DEVICEID_ACENIC 0x0001 1860 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 1861 #define ALT_DEVICEID_BCM5700 0x0003 1862 #define ALT_DEVICEID_BCM5701 0x0004 1863 1864 /* 1865 * 3Com 3c985 PCI vendor/device ID. 1866 */ 1867 #define TC_VENDORID 0x10B7 1868 #define TC_DEVICEID_3C985 0x0001 1869 #define TC_DEVICEID_3C996 0x0003 1870 1871 /* 1872 * SysKonnect PCI vendor ID 1873 */ 1874 #define SK_VENDORID 0x1148 1875 #define SK_DEVICEID_ALTIMA 0x4400 1876 #define SK_SUBSYSID_9D21 0x4421 1877 #define SK_SUBSYSID_9D41 0x4441 1878 1879 /* 1880 * Altima PCI vendor/device ID. 1881 */ 1882 #define ALTIMA_VENDORID 0x173b 1883 #define ALTIMA_DEVICE_AC1000 0x03e8 1884 1885 /* 1886 * Offset of MAC address inside EEPROM. 1887 */ 1888 #define BGE_EE_MAC_OFFSET 0x7C 1889 #define BGE_EE_HWCFG_OFFSET 0xC8 1890 1891 #define BGE_HWCFG_VOLTAGE 0x00000003 1892 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1893 #define BGE_HWCFG_MEDIA 0x00000030 1894 1895 #define BGE_VOLTAGE_1POINT3 0x00000000 1896 #define BGE_VOLTAGE_1POINT8 0x00000001 1897 1898 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 1899 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1900 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 1901 1902 #define BGE_MEDIA_UNSPEC 0x00000000 1903 #define BGE_MEDIA_COPPER 0x00000010 1904 #define BGE_MEDIA_FIBER 0x00000020 1905 1906 #define BGE_PCI_READ_CMD 0x06000000 1907 #define BGE_PCI_WRITE_CMD 0x70000000 1908 1909 #define BGE_TICKS_PER_SEC 1000000 1910 1911 /* 1912 * Ring size constants. 1913 */ 1914 #define BGE_EVENT_RING_CNT 256 1915 #define BGE_CMD_RING_CNT 64 1916 #define BGE_STD_RX_RING_CNT 512 1917 #define BGE_JUMBO_RX_RING_CNT 256 1918 #define BGE_MINI_RX_RING_CNT 1024 1919 #define BGE_RETURN_RING_CNT 1024 1920 1921 /* 1922 * Possible TX ring sizes. 1923 */ 1924 #define BGE_TX_RING_CNT_128 128 1925 #define BGE_TX_RING_BASE_128 0x3800 1926 1927 #define BGE_TX_RING_CNT_256 256 1928 #define BGE_TX_RING_BASE_256 0x3000 1929 1930 #define BGE_TX_RING_CNT_512 512 1931 #define BGE_TX_RING_BASE_512 0x2000 1932 1933 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1934 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1935 1936 /* 1937 * Tigon III statistics counters. 1938 */ 1939 struct bge_stats { 1940 u_int8_t Reserved0[256]; 1941 1942 /* Statistics maintained by Receive MAC. */ 1943 bge_hostaddr ifHCInOctets; 1944 bge_hostaddr Reserved1; 1945 bge_hostaddr etherStatsFragments; 1946 bge_hostaddr ifHCInUcastPkts; 1947 bge_hostaddr ifHCInMulticastPkts; 1948 bge_hostaddr ifHCInBroadcastPkts; 1949 bge_hostaddr dot3StatsFCSErrors; 1950 bge_hostaddr dot3StatsAlignmentErrors; 1951 bge_hostaddr xonPauseFramesReceived; 1952 bge_hostaddr xoffPauseFramesReceived; 1953 bge_hostaddr macControlFramesReceived; 1954 bge_hostaddr xoffStateEntered; 1955 bge_hostaddr dot3StatsFramesTooLong; 1956 bge_hostaddr etherStatsJabbers; 1957 bge_hostaddr etherStatsUndersizePkts; 1958 bge_hostaddr inRangeLengthError; 1959 bge_hostaddr outRangeLengthError; 1960 bge_hostaddr etherStatsPkts64Octets; 1961 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1962 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1963 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1964 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1965 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1966 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1967 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1968 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1969 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1970 1971 bge_hostaddr Unused1[37]; 1972 1973 /* Statistics maintained by Transmit MAC. */ 1974 bge_hostaddr ifHCOutOctets; 1975 bge_hostaddr Reserved2; 1976 bge_hostaddr etherStatsCollisions; 1977 bge_hostaddr outXonSent; 1978 bge_hostaddr outXoffSent; 1979 bge_hostaddr flowControlDone; 1980 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1981 bge_hostaddr dot3StatsSingleCollisionFrames; 1982 bge_hostaddr dot3StatsMultipleCollisionFrames; 1983 bge_hostaddr dot3StatsDeferredTransmissions; 1984 bge_hostaddr Reserved3; 1985 bge_hostaddr dot3StatsExcessiveCollisions; 1986 bge_hostaddr dot3StatsLateCollisions; 1987 bge_hostaddr dot3Collided2Times; 1988 bge_hostaddr dot3Collided3Times; 1989 bge_hostaddr dot3Collided4Times; 1990 bge_hostaddr dot3Collided5Times; 1991 bge_hostaddr dot3Collided6Times; 1992 bge_hostaddr dot3Collided7Times; 1993 bge_hostaddr dot3Collided8Times; 1994 bge_hostaddr dot3Collided9Times; 1995 bge_hostaddr dot3Collided10Times; 1996 bge_hostaddr dot3Collided11Times; 1997 bge_hostaddr dot3Collided12Times; 1998 bge_hostaddr dot3Collided13Times; 1999 bge_hostaddr dot3Collided14Times; 2000 bge_hostaddr dot3Collided15Times; 2001 bge_hostaddr ifHCOutUcastPkts; 2002 bge_hostaddr ifHCOutMulticastPkts; 2003 bge_hostaddr ifHCOutBroadcastPkts; 2004 bge_hostaddr dot3StatsCarrierSenseErrors; 2005 bge_hostaddr ifOutDiscards; 2006 bge_hostaddr ifOutErrors; 2007 2008 bge_hostaddr Unused2[31]; 2009 2010 /* Statistics maintained by Receive List Placement. */ 2011 bge_hostaddr COSIfHCInPkts[16]; 2012 bge_hostaddr COSFramesDroppedDueToFilters; 2013 bge_hostaddr nicDmaWriteQueueFull; 2014 bge_hostaddr nicDmaWriteHighPriQueueFull; 2015 bge_hostaddr nicNoMoreRxBDs; 2016 bge_hostaddr ifInDiscards; 2017 bge_hostaddr ifInErrors; 2018 bge_hostaddr nicRecvThresholdHit; 2019 2020 bge_hostaddr Unused3[9]; 2021 2022 /* Statistics maintained by Send Data Initiator. */ 2023 bge_hostaddr COSIfHCOutPkts[16]; 2024 bge_hostaddr nicDmaReadQueueFull; 2025 bge_hostaddr nicDmaReadHighPriQueueFull; 2026 bge_hostaddr nicSendDataCompQueueFull; 2027 2028 /* Statistics maintained by Host Coalescing. */ 2029 bge_hostaddr nicRingSetSendProdIndex; 2030 bge_hostaddr nicRingStatusUpdate; 2031 bge_hostaddr nicInterrupts; 2032 bge_hostaddr nicAvoidedInterrupts; 2033 bge_hostaddr nicSendThresholdHit; 2034 2035 u_int8_t Reserved4[320]; 2036 }; 2037 2038 /* 2039 * Tigon general information block. This resides in host memory 2040 * and contains the status counters, ring control blocks and 2041 * producer pointers. 2042 */ 2043 2044 struct bge_gib { 2045 struct bge_stats bge_stats; 2046 struct bge_rcb bge_tx_rcb[16]; 2047 struct bge_rcb bge_std_rx_rcb; 2048 struct bge_rcb bge_jumbo_rx_rcb; 2049 struct bge_rcb bge_mini_rx_rcb; 2050 struct bge_rcb bge_return_rcb; 2051 }; 2052 2053 /* 2054 * NOTE! On the Alpha, we have an alignment constraint. 2055 * The first thing in the packet is a 14-byte Ethernet header. 2056 * This means that the packet is misaligned. To compensate, 2057 * we actually offset the data 2 bytes into the cluster. This 2058 * alignes the packet after the Ethernet header at a 32-bit 2059 * boundary. 2060 */ 2061 2062 #define ETHER_ALIGN 2 2063 2064 #define BGE_FRAMELEN ETHER_MAX_LEN 2065 #define BGE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_CRC_LEN) 2066 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2067 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2068 #define BGE_PAGE_SIZE PAGE_SIZE 2069 #define BGE_MIN_FRAMELEN 60 2070 2071 /* 2072 * Other utility macros. 2073 */ 2074 #define BGE_INC(x, y) (x) = (x + 1) % y 2075 2076 /* 2077 * Vital product data and structures. 2078 */ 2079 #define BGE_VPD_FLAG 0x8000 2080 2081 /* VPD structures */ 2082 struct vpd_res { 2083 u_int8_t vr_id; 2084 u_int8_t vr_len; 2085 u_int8_t vr_pad; 2086 }; 2087 2088 struct vpd_key { 2089 char vk_key[2]; 2090 u_int8_t vk_len; 2091 }; 2092 2093 #define VPD_RES_ID 0x82 /* ID string */ 2094 #define VPD_RES_READ 0x90 /* start of read only area */ 2095 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2096 #define VPD_RES_END 0x78 /* end tag */ 2097 2098 2099 /* 2100 * Register access macros. The Tigon always uses memory mapped register 2101 * accesses and all registers must be accessed with 32 bit operations. 2102 */ 2103 2104 #define CSR_WRITE_4(sc, reg, val) \ 2105 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2106 2107 #define CSR_READ_4(sc, reg) \ 2108 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2109 2110 #define BGE_SETBIT(sc, reg, x) \ 2111 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2112 #define BGE_CLRBIT(sc, reg, x) \ 2113 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2114 2115 #define PCI_SETBIT(pc, tag, reg, x) \ 2116 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 2117 #define PCI_CLRBIT(pc, tag, reg, x) \ 2118 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 2119 2120 /* 2121 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2122 * values are tuneable. They control the actual amount of buffers 2123 * allocated for the standard, mini and jumbo receive rings. 2124 */ 2125 2126 #define BGE_SSLOTS 256 2127 #define BGE_MSLOTS 256 2128 #define BGE_JSLOTS 384 2129 #define BGE_RSLOTS 256 2130 2131 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2132 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2133 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2134 #define BGE_JPAGESZ PAGE_SIZE 2135 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2136 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2137 2138 /* 2139 * Ring structures. Most of these reside in host memory and we tell 2140 * the NIC where they are via the ring control blocks. The exceptions 2141 * are the tx and command rings, which live in NIC memory and which 2142 * we access via the shared memory window. 2143 */ 2144 struct bge_ring_data { 2145 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2146 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2147 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2148 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2149 struct bge_status_block bge_status_block; 2150 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2151 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2152 struct bge_gib bge_info; 2153 }; 2154 2155 #define BGE_RING_DMA_ADDR(sc, offset) \ 2156 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2157 offsetof(struct bge_ring_data, offset)) 2158 2159 /* 2160 * Number of DMA segments in a TxCB. Note that this is carefully 2161 * chosen to make the total struct size an even power of two. It's 2162 * critical that no TxCB be split across a page boundry since 2163 * no attempt is made to allocate physically contiguous memory. 2164 * 2165 */ 2166 #ifdef _LP64 2167 #define BGE_NTXSEG 30 2168 #else 2169 #define BGE_NTXSEG 31 2170 #endif 2171 2172 /* 2173 * Mbuf pointers. We need these to keep track of the virtual addresses 2174 * of our mbuf chains since we can only convert from physical to virtual, 2175 * not the other way around. 2176 */ 2177 struct bge_chain_data { 2178 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2179 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2180 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2181 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2182 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2183 bus_dmamap_t bge_rx_jumbo_map; 2184 /* Stick the jumbo mem management stuff here too. */ 2185 caddr_t bge_jslots[BGE_JSLOTS]; 2186 void *bge_jumbo_buf; 2187 }; 2188 2189 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 2190 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2191 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2192 2193 struct bge_type { 2194 u_int16_t bge_vid; 2195 u_int16_t bge_did; 2196 char *bge_name; 2197 }; 2198 2199 #define BGE_HWREV_TIGON 0x01 2200 #define BGE_HWREV_TIGON_II 0x02 2201 #define BGE_TIMEOUT 1000 2202 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2203 2204 struct bge_jpool_entry { 2205 int slot; 2206 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2207 }; 2208 2209 struct bge_bcom_hack { 2210 int reg; 2211 int val; 2212 }; 2213 2214 struct txdmamap_pool_entry { 2215 bus_dmamap_t dmamap; 2216 SLIST_ENTRY(txdmamap_pool_entry) link; 2217 }; 2218 2219 /* 2220 * Flags for bge_flags. 2221 */ 2222 #define BGE_TXRING_VALID 0x0001 2223 #define BGE_RXRING_VALID 0x0002 2224 #define BGE_JUMBO_RXRING_VALID 0x0004 2225 2226 struct bge_softc { 2227 struct device bge_dev; 2228 struct ethercom ethercom; /* interface info */ 2229 bus_space_handle_t bge_bhandle; 2230 bus_space_tag_t bge_btag; 2231 void *bge_intrhand; 2232 struct pci_attach_args bge_pa; 2233 struct mii_data bge_mii; 2234 struct ifmedia bge_ifmedia; /* media info */ 2235 u_int8_t bge_extram; /* has external SSRAM */ 2236 u_int8_t bge_tbi; 2237 bus_dma_tag_t bge_dmatag; 2238 u_int32_t bge_asicrev; 2239 u_int32_t bge_quirks; 2240 struct bge_ring_data *bge_rdata; /* rings */ 2241 struct bge_chain_data bge_cdata; /* mbufs */ 2242 bus_dmamap_t bge_ring_map; 2243 u_int16_t bge_tx_saved_considx; 2244 u_int16_t bge_rx_saved_considx; 2245 u_int16_t bge_ev_saved_considx; 2246 u_int16_t bge_std; /* current std ring head */ 2247 u_int16_t bge_jumbo; /* current jumo ring head */ 2248 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2249 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2250 u_int32_t bge_stat_ticks; 2251 u_int32_t bge_rx_coal_ticks; 2252 u_int32_t bge_tx_coal_ticks; 2253 u_int32_t bge_rx_max_coal_bds; 2254 u_int32_t bge_tx_max_coal_bds; 2255 u_int32_t bge_tx_buf_ratio; 2256 int bge_if_flags; 2257 int bge_flags; 2258 int bge_txcnt; 2259 int bge_link; 2260 struct callout bge_timeout; 2261 char *bge_vpd_prodname; 2262 char *bge_vpd_readonly; 2263 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2264 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2265 }; 2266
Indexes created Thu Oct 16 14:10:15 GMT 2025