if_bgereg.h revision 1.45
1 /* $NetBSD: if_bgereg.h,v 1.45 2007/12/09 20:28:08 jmcneill Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79 #define BGE_UNMAPPED 0x00001000 80 #define BGE_UNMAPPED_END 0x00001FFF 81 #define BGE_DMA_DESCRIPTORS 0x00002000 82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83 #define BGE_SEND_RING_1_TO_4 0x00004000 84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86 /* Mappings for internal memory configuration */ 87 #define BGE_STD_RX_RINGS 0x00006000 88 #define BGE_STD_RX_RINGS_END 0x00006FFF 89 #define BGE_JUMBO_RX_RINGS 0x00007000 90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91 #define BGE_BUFFPOOL_1 0x00008000 92 #define BGE_BUFFPOOL_1_END 0x0000FFFF 93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_2_END 0x00017FFF 95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96 #define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98 /* Mappings for external SSRAM configurations */ 99 #define BGE_SEND_RING_5_TO_6 0x00006000 100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101 #define BGE_SEND_RING_7_TO_8 0x00007000 102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103 #define BGE_SEND_RING_9_TO_16 0x00008000 104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105 #define BGE_EXT_STD_RX_RINGS 0x0000C000 106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109 #define BGE_MINI_RX_RINGS 0x0000E000 110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION1_END 0x00017FFF 113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114 #define BGE_AVAIL_REGION2_END 0x0001FFFF 115 #define BGE_EXT_SSRAM 0x00020000 116 #define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119 /* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129 /* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132 #define BGE_PCI_VID 0x00 133 #define BGE_PCI_DID 0x02 134 #define BGE_PCI_CMD 0x04 135 #define BGE_PCI_STS 0x06 136 #define BGE_PCI_REV 0x08 137 #define BGE_PCI_CLASS 0x09 138 #define BGE_PCI_CACHESZ 0x0C 139 #define BGE_PCI_LATTIMER 0x0D 140 #define BGE_PCI_HDRTYPE 0x0E 141 #define BGE_PCI_BIST 0x0F 142 #define BGE_PCI_BAR0 0x10 143 #define BGE_PCI_BAR1 0x14 144 #define BGE_PCI_SUBSYS 0x2C 145 #define BGE_PCI_SUBVID 0x2E 146 #define BGE_PCI_ROMBASE 0x30 147 #define BGE_PCI_CAPPTR 0x34 148 #define BGE_PCI_INTLINE 0x3C 149 #define BGE_PCI_INTPIN 0x3D 150 #define BGE_PCI_MINGNT 0x3E 151 #define BGE_PCI_MAXLAT 0x3F 152 #define BGE_PCI_PCIXCAP 0x40 153 #define BGE_PCI_NEXTPTR_PM 0x41 154 #define BGE_PCI_PCIX_CMD 0x42 155 #define BGE_PCI_PCIX_STS 0x44 156 #define BGE_PCI_PWRMGMT_CAPID 0x48 157 #define BGE_PCI_NEXTPTR_VPD 0x49 158 #define BGE_PCI_PWRMGMT_CAPS 0x4A 159 #define BGE_PCI_PWRMGMT_CMD 0x4C 160 #define BGE_PCI_PWRMGMT_STS 0x4D 161 #define BGE_PCI_PWRMGMT_DATA 0x4F 162 #define BGE_PCI_VPD_CAPID 0x50 163 #define BGE_PCI_NEXTPTR_MSI 0x51 164 #define BGE_PCI_VPD_ADDR 0x52 165 #define BGE_PCI_VPD_DATA 0x54 166 #define BGE_PCI_MSI_CAPID 0x58 167 #define BGE_PCI_NEXTPTR_NONE 0x59 168 #define BGE_PCI_MSI_CTL 0x5A 169 #define BGE_PCI_MSI_ADDR_HI 0x5C 170 #define BGE_PCI_MSI_ADDR_LO 0x60 171 #define BGE_PCI_MSI_DATA 0x64 172 173 /* 174 * PCI registers specific to the BCM570x family. 175 */ 176 #define BGE_PCI_MISC_CTL 0x68 177 #define BGE_PCI_DMA_RW_CTL 0x6C 178 #define BGE_PCI_PCISTATE 0x70 179 #define BGE_PCI_CLKCTL 0x74 180 #define BGE_PCI_REG_BASEADDR 0x78 181 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 182 #define BGE_PCI_REG_DATA 0x80 183 #define BGE_PCI_MEMWIN_DATA 0x84 184 #define BGE_PCI_MODECTL 0x88 185 #define BGE_PCI_MISC_CFG 0x8C 186 #define BGE_PCI_MISC_LOCALCTL 0x90 187 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 188 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 189 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 190 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 191 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 192 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 193 #define BGE_PCI_ISR_MBX_HI 0xB0 194 #define BGE_PCI_ISR_MBX_LO 0xB4 195 196 #define BGE_PCI_UNKNOWN0 0xC4 197 /* XXX: 198 * Used in PCI-Express code for 575x chips. 199 * Should be replaced with checking for a PCI config-space 200 * capability for PCI-Express, and PCI-Express standard 201 * offsets into that capability block. 202 */ 203 #define BGE_PCI_CONF_DEV_CTRL 0xD8 204 #define BGE_PCI_CONF_DEV_STUS 0xDA 205 206 207 /* PCI Misc. Host control register */ 208 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 209 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 210 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 211 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 212 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 213 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 214 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 215 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 216 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 217 218 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 219 #if BYTE_ORDER == LITTLE_ENDIAN 220 #define BGE_DMA_SWAP_OPTIONS \ 221 BGE_MODECTL_WORDSWAP_NONFRAME| \ 222 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 223 #else 224 #define BGE_DMA_SWAP_OPTIONS \ 225 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 226 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 227 #endif 228 229 #define BGE_INIT \ 230 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 231 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 232 233 #define BGE_CHIPID_TIGON_I 0x40000000 234 #define BGE_CHIPID_TIGON_II 0x60000000 235 #define BGE_CHIPID_BCM5700_A0 0x70000000 236 #define BGE_CHIPID_BCM5700_A1 0x70010000 237 #define BGE_CHIPID_BCM5700_B0 0x71000000 238 #define BGE_CHIPID_BCM5700_B1 0x71010000 239 #define BGE_CHIPID_BCM5700_B2 0x71020000 240 #define BGE_CHIPID_BCM5700_B3 0x71030000 241 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 242 #define BGE_CHIPID_BCM5700_C0 0x72000000 243 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 244 #define BGE_CHIPID_BCM5701_B0 0x01000000 245 #define BGE_CHIPID_BCM5701_B2 0x01020000 246 #define BGE_CHIPID_BCM5701_B5 0x01050000 247 #define BGE_CHIPID_BCM5703_A0 0x10000000 248 #define BGE_CHIPID_BCM5703_A1 0x10010000 249 #define BGE_CHIPID_BCM5703_A2 0x10020000 250 #define BGE_CHIPID_BCM5703_A3 0x10030000 251 #define BGE_CHIPID_BCM5703_B0 0x11000000 252 #define BGE_CHIPID_BCM5704_A0 0x20000000 253 #define BGE_CHIPID_BCM5704_A1 0x20010000 254 #define BGE_CHIPID_BCM5704_A2 0x20020000 255 #define BGE_CHIPID_BCM5704_A3 0x20030000 256 #define BGE_CHIPID_BCM5704_B0 0x21000000 257 #define BGE_CHIPID_BCM5705_A0 0x30000000 258 #define BGE_CHIPID_BCM5705_A1 0x30010000 259 #define BGE_CHIPID_BCM5705_A2 0x30020000 260 #define BGE_CHIPID_BCM5705_A3 0x30030000 261 #define BGE_CHIPID_BCM5750_A0 0x40000000 262 #define BGE_CHIPID_BCM5750_A1 0x40010000 263 #define BGE_CHIPID_BCM5750_A3 0x40030000 264 #define BGE_CHIPID_BCM5750_B0 0x40100000 265 #define BGE_CHIPID_BCM5751_A1 0x41010000 266 #define BGE_CHIPID_BCM5750_C0 0x42000000 267 #define BGE_CHIPID_BCM5750_C1 0x42010000 268 #define BGE_CHIPID_BCM5750_C2 0x42020000 269 #define BGE_CHIPID_BCM5714_A0 0x50000000 270 #define BGE_CHIPID_BCM5752_A0 0x60000000 271 #define BGE_CHIPID_BCM5752_A1 0x60010000 272 #define BGE_CHIPID_BCM5752_A2 0x60020000 273 #define BGE_CHIPID_BCM5714_B0 0x80000000 274 #define BGE_CHIPID_BCM5714_B3 0x80030000 275 #define BGE_CHIPID_BCM5715_A0 0x90000000 276 #define BGE_CHIPID_BCM5715_A1 0x90010000 277 #define BGE_CHIPID_BCM5715_A3 0x90030000 278 #define BGE_CHIPID_BCM5787_A0 0xb0000000 279 #define BGE_CHIPID_BCM5787_A1 0xb0010000 280 #define BGE_CHIPID_BCM5787_A2 0xb0020000 281 #define BGE_CHIPID_BCM5906_A1 0xc0010000 282 283 /* shorthand one */ 284 #define BGE_ASICREV(x) ((x) >> 28) 285 #define BGE_ASICREV_BCM5700 0x07 286 #define BGE_ASICREV_BCM5701 0x00 287 #define BGE_ASICREV_BCM5703 0x01 288 #define BGE_ASICREV_BCM5704 0x02 289 #define BGE_ASICREV_BCM5705 0x03 290 #define BGE_ASICREV_BCM5750 0x04 291 #define BGE_ASICREV_BCM5714_A0 0x05 292 #define BGE_ASICREV_BCM5752 0x06 293 /* ASIC revision 0x07 is the original bcm5700 */ 294 #define BGE_ASICREV_BCM5780 0x08 295 #define BGE_ASICREV_BCM5714 0x09 296 #define BGE_ASICREV_BCM5755 0x0a 297 #define BGE_ASICREV_BCM5787 0x0b 298 #define BGE_ASICREV_BCM5706 0x0c 299 300 /* chip revisions */ 301 #define BGE_CHIPREV(x) ((x) >> 24) 302 #define BGE_CHIPREV_5700_AX 0x70 303 #define BGE_CHIPREV_5700_BX 0x71 304 #define BGE_CHIPREV_5700_CX 0x72 305 #define BGE_CHIPREV_5701_AX 0x00 306 #define BGE_CHIPREV_5703_AX 0x10 307 #define BGE_CHIPREV_5704_AX 0x20 308 #define BGE_CHIPREV_5704_BX 0x21 309 #define BGE_CHIPREV_5750_AX 0x40 310 #define BGE_CHIPREV_5750_BX 0x41 311 312 /* PCI DMA Read/Write Control register */ 313 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 314 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 315 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 316 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 317 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 318 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 319 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 320 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 321 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 322 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 323 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 324 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 325 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 326 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 327 328 /* PCI DMA Read/Write Control register, alternate usage for PCI-Express */ 329 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128 0x00180000 330 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256 0x00380000 331 332 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 333 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 334 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 335 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 336 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 337 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 338 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 339 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 340 341 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 342 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 343 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 344 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 345 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 346 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 347 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 348 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 349 350 /* 351 * PCI state register -- note, this register is read only 352 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 353 * register is set. 354 */ 355 #define BGE_PCISTATE_FORCE_RESET 0x00000001 356 #define BGE_PCISTATE_INTR_STATE 0x00000002 357 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 358 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 359 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 360 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 361 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 362 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 363 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 364 365 /* 366 * The following bits in PCI state register are reserved. 367 * If we check that the register values reverts on reset, 368 * do not check these bits. On some 5704C (rev A3) and some 369 * Altima chips, these bits do not revert until much later 370 * in the bge driver's bge_reset() chip-reset state machine. 371 */ 372 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 373 374 /* 375 * PCI Clock Control register -- note, this register is read only 376 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 377 * register is set. 378 */ 379 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 380 #define BGE_PCICLOCKCTL_M66EN 0x00000080 381 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 382 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 383 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 384 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 385 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 386 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 387 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 388 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 389 390 391 #ifndef PCIM_CMD_MWIEN 392 #define PCIM_CMD_MWIEN 0x0010 393 #endif 394 395 /* 396 * High priority mailbox registers 397 * Each mailbox is 64-bits wide, though we only use the 398 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 399 * first. The NIC will load the mailbox after the lower 32 bit word 400 * has been updated. 401 */ 402 #define BGE_MBX_IRQ0_HI 0x0200 403 #define BGE_MBX_IRQ0_LO 0x0204 404 #define BGE_MBX_IRQ1_HI 0x0208 405 #define BGE_MBX_IRQ1_LO 0x020C 406 #define BGE_MBX_IRQ2_HI 0x0210 407 #define BGE_MBX_IRQ2_LO 0x0214 408 #define BGE_MBX_IRQ3_HI 0x0218 409 #define BGE_MBX_IRQ3_LO 0x021C 410 #define BGE_MBX_GEN0_HI 0x0220 411 #define BGE_MBX_GEN0_LO 0x0224 412 #define BGE_MBX_GEN1_HI 0x0228 413 #define BGE_MBX_GEN1_LO 0x022C 414 #define BGE_MBX_GEN2_HI 0x0230 415 #define BGE_MBX_GEN2_LO 0x0234 416 #define BGE_MBX_GEN3_HI 0x0228 417 #define BGE_MBX_GEN3_LO 0x022C 418 #define BGE_MBX_GEN4_HI 0x0240 419 #define BGE_MBX_GEN4_LO 0x0244 420 #define BGE_MBX_GEN5_HI 0x0248 421 #define BGE_MBX_GEN5_LO 0x024C 422 #define BGE_MBX_GEN6_HI 0x0250 423 #define BGE_MBX_GEN6_LO 0x0254 424 #define BGE_MBX_GEN7_HI 0x0258 425 #define BGE_MBX_GEN7_LO 0x025C 426 #define BGE_MBX_RELOAD_STATS_HI 0x0260 427 #define BGE_MBX_RELOAD_STATS_LO 0x0264 428 #define BGE_MBX_RX_STD_PROD_HI 0x0268 429 #define BGE_MBX_RX_STD_PROD_LO 0x026C 430 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 431 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 432 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 433 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 434 #define BGE_MBX_RX_CONS0_HI 0x0280 435 #define BGE_MBX_RX_CONS0_LO 0x0284 436 #define BGE_MBX_RX_CONS1_HI 0x0288 437 #define BGE_MBX_RX_CONS1_LO 0x028C 438 #define BGE_MBX_RX_CONS2_HI 0x0290 439 #define BGE_MBX_RX_CONS2_LO 0x0294 440 #define BGE_MBX_RX_CONS3_HI 0x0298 441 #define BGE_MBX_RX_CONS3_LO 0x029C 442 #define BGE_MBX_RX_CONS4_HI 0x02A0 443 #define BGE_MBX_RX_CONS4_LO 0x02A4 444 #define BGE_MBX_RX_CONS5_HI 0x02A8 445 #define BGE_MBX_RX_CONS5_LO 0x02AC 446 #define BGE_MBX_RX_CONS6_HI 0x02B0 447 #define BGE_MBX_RX_CONS6_LO 0x02B4 448 #define BGE_MBX_RX_CONS7_HI 0x02B8 449 #define BGE_MBX_RX_CONS7_LO 0x02BC 450 #define BGE_MBX_RX_CONS8_HI 0x02C0 451 #define BGE_MBX_RX_CONS8_LO 0x02C4 452 #define BGE_MBX_RX_CONS9_HI 0x02C8 453 #define BGE_MBX_RX_CONS9_LO 0x02CC 454 #define BGE_MBX_RX_CONS10_HI 0x02D0 455 #define BGE_MBX_RX_CONS10_LO 0x02D4 456 #define BGE_MBX_RX_CONS11_HI 0x02D8 457 #define BGE_MBX_RX_CONS11_LO 0x02DC 458 #define BGE_MBX_RX_CONS12_HI 0x02E0 459 #define BGE_MBX_RX_CONS12_LO 0x02E4 460 #define BGE_MBX_RX_CONS13_HI 0x02E8 461 #define BGE_MBX_RX_CONS13_LO 0x02EC 462 #define BGE_MBX_RX_CONS14_HI 0x02F0 463 #define BGE_MBX_RX_CONS14_LO 0x02F4 464 #define BGE_MBX_RX_CONS15_HI 0x02F8 465 #define BGE_MBX_RX_CONS15_LO 0x02FC 466 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 467 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 468 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 469 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 470 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 471 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 472 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 473 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 474 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 475 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 476 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 477 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 478 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 479 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 480 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 481 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 482 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 483 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 484 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 485 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 486 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 487 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 488 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 489 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 490 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 491 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 492 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 493 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 494 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 495 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 496 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 497 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 498 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 499 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 500 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 501 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 502 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 503 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 504 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 505 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 506 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 507 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 508 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 509 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 510 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 511 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 512 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 513 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 514 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 515 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 516 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 517 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 518 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 519 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 520 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 521 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 522 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 523 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 524 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 525 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 526 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 527 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 528 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 529 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 530 531 #define BGE_TX_RINGS_MAX 4 532 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 533 #define BGE_RX_RINGS_MAX 16 534 535 /* Ethernet MAC control registers */ 536 #define BGE_MAC_MODE 0x0400 537 #define BGE_MAC_STS 0x0404 538 #define BGE_MAC_EVT_ENB 0x0408 539 #define BGE_MAC_LED_CTL 0x040C 540 #define BGE_MAC_ADDR1_LO 0x0410 541 #define BGE_MAC_ADDR1_HI 0x0414 542 #define BGE_MAC_ADDR2_LO 0x0418 543 #define BGE_MAC_ADDR2_HI 0x041C 544 #define BGE_MAC_ADDR3_LO 0x0420 545 #define BGE_MAC_ADDR3_HI 0x0424 546 #define BGE_MAC_ADDR4_LO 0x0428 547 #define BGE_MAC_ADDR4_HI 0x042C 548 #define BGE_WOL_PATPTR 0x0430 549 #define BGE_WOL_PATCFG 0x0434 550 #define BGE_TX_RANDOM_BACKOFF 0x0438 551 #define BGE_RX_MTU 0x043C 552 #define BGE_GBIT_PCS_TEST 0x0440 553 #define BGE_TX_TBI_AUTONEG 0x0444 554 #define BGE_RX_TBI_AUTONEG 0x0448 555 #define BGE_MI_COMM 0x044C 556 #define BGE_MI_STS 0x0450 557 #define BGE_MI_MODE 0x0454 558 #define BGE_AUTOPOLL_STS 0x0458 559 #define BGE_TX_MODE 0x045C 560 #define BGE_TX_STS 0x0460 561 #define BGE_TX_LENGTHS 0x0464 562 #define BGE_RX_MODE 0x0468 563 #define BGE_RX_STS 0x046C 564 #define BGE_MAR0 0x0470 565 #define BGE_MAR1 0x0474 566 #define BGE_MAR2 0x0478 567 #define BGE_MAR3 0x047C 568 #define BGE_RX_BD_RULES_CTL0 0x0480 569 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 570 #define BGE_RX_BD_RULES_CTL1 0x0488 571 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 572 #define BGE_RX_BD_RULES_CTL2 0x0490 573 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 574 #define BGE_RX_BD_RULES_CTL3 0x0498 575 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 576 #define BGE_RX_BD_RULES_CTL4 0x04A0 577 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 578 #define BGE_RX_BD_RULES_CTL5 0x04A8 579 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 580 #define BGE_RX_BD_RULES_CTL6 0x04B0 581 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 582 #define BGE_RX_BD_RULES_CTL7 0x04B8 583 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 584 #define BGE_RX_BD_RULES_CTL8 0x04C0 585 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 586 #define BGE_RX_BD_RULES_CTL9 0x04C8 587 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 588 #define BGE_RX_BD_RULES_CTL10 0x04D0 589 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 590 #define BGE_RX_BD_RULES_CTL11 0x04D8 591 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 592 #define BGE_RX_BD_RULES_CTL12 0x04E0 593 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 594 #define BGE_RX_BD_RULES_CTL13 0x04E8 595 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 596 #define BGE_RX_BD_RULES_CTL14 0x04F0 597 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 598 #define BGE_RX_BD_RULES_CTL15 0x04F8 599 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 600 #define BGE_RX_RULES_CFG 0x0500 601 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 602 #define BGE_RX_STATS 0x0800 603 #define BGE_TX_STATS 0x0880 604 605 /* Ethernet MAC Mode register */ 606 #define BGE_MACMODE_RESET 0x00000001 607 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 608 #define BGE_MACMODE_PORTMODE 0x0000000C 609 #define BGE_MACMODE_LOOPBACK 0x00000010 610 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 611 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 612 #define BGE_MACMODE_MAX_DEFER 0x00000200 613 #define BGE_MACMODE_LINK_POLARITY 0x00000400 614 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 615 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 616 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 617 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 618 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 619 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 620 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 621 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 622 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 623 #define BGE_MACMODE_MIP_ENB 0x00100000 624 #define BGE_MACMODE_TXDMA_ENB 0x00200000 625 #define BGE_MACMODE_RXDMA_ENB 0x00400000 626 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 627 628 #define BGE_PORTMODE_NONE 0x00000000 629 #define BGE_PORTMODE_MII 0x00000004 630 #define BGE_PORTMODE_GMII 0x00000008 631 #define BGE_PORTMODE_TBI 0x0000000C 632 633 /* MAC Status register */ 634 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 635 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 636 #define BGE_MACSTAT_RX_CFG 0x00000004 637 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 638 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 639 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 640 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 641 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 642 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 643 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 644 #define BGE_MACSTAT_ODI_ERROR 0x02000000 645 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 646 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 647 648 /* MAC Event Enable Register */ 649 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 650 #define BGE_EVTENB_LINK_CHANGED 0x00001000 651 #define BGE_EVTENB_MI_COMPLETE 0x00400000 652 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 653 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 654 #define BGE_EVTENB_ODI_ERROR 0x02000000 655 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 656 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 657 658 /* LED Control Register */ 659 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 660 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 661 #define BGE_LEDCTL_100MBPS_LED 0x00000004 662 #define BGE_LEDCTL_10MBPS_LED 0x00000008 663 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 664 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 665 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 666 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 667 #define BGE_LEDCTL_100MBPS_STS 0x00000100 668 #define BGE_LEDCTL_10MBPS_STS 0x00000200 669 #define BGE_LEDCTL_TRADLED_STS 0x00000400 670 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 671 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 672 673 /* TX backoff seed register */ 674 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 675 676 /* Autopoll status register */ 677 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 678 679 /* Transmit MAC mode register */ 680 #define BGE_TXMODE_RESET 0x00000001 681 #define BGE_TXMODE_ENABLE 0x00000002 682 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 683 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 684 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 685 686 /* Transmit MAC status register */ 687 #define BGE_TXSTAT_RX_XOFFED 0x00000001 688 #define BGE_TXSTAT_SENT_XOFF 0x00000002 689 #define BGE_TXSTAT_SENT_XON 0x00000004 690 #define BGE_TXSTAT_LINK_UP 0x00000008 691 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 692 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 693 694 /* Transmit MAC lengths register */ 695 #define BGE_TXLEN_SLOTTIME 0x000000FF 696 #define BGE_TXLEN_IPG 0x00000F00 697 #define BGE_TXLEN_CRS 0x00003000 698 699 /* Receive MAC mode register */ 700 #define BGE_RXMODE_RESET 0x00000001 701 #define BGE_RXMODE_ENABLE 0x00000002 702 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 703 #define BGE_RXMODE_RX_GIANTS 0x00000020 704 #define BGE_RXMODE_RX_RUNTS 0x00000040 705 #define BGE_RXMODE_8022_LENCHECK 0x00000080 706 #define BGE_RXMODE_RX_PROMISC 0x00000100 707 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 708 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 709 710 /* Receive MAC status register */ 711 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 712 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 713 #define BGE_RXSTAT_RCVD_XON 0x00000004 714 715 /* Receive Rules Control register */ 716 #define BGE_RXRULECTL_OFFSET 0x000000FF 717 #define BGE_RXRULECTL_CLASS 0x00001F00 718 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 719 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 720 #define BGE_RXRULECTL_MAP 0x01000000 721 #define BGE_RXRULECTL_DISCARD 0x02000000 722 #define BGE_RXRULECTL_MASK 0x04000000 723 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 724 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 725 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 726 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 727 728 /* Receive Rules Mask register */ 729 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 730 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 731 732 /* MI communication register */ 733 #define BGE_MICOMM_DATA 0x0000FFFF 734 #define BGE_MICOMM_REG 0x001F0000 735 #define BGE_MICOMM_PHY 0x03E00000 736 #define BGE_MICOMM_CMD 0x0C000000 737 #define BGE_MICOMM_READFAIL 0x10000000 738 #define BGE_MICOMM_BUSY 0x20000000 739 740 #define BGE_MIREG(x) ((x & 0x1F) << 16) 741 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 742 #define BGE_MICMD_WRITE 0x04000000 743 #define BGE_MICMD_READ 0x08000000 744 745 /* MI status register */ 746 #define BGE_MISTS_LINK 0x00000001 747 #define BGE_MISTS_10MBPS 0x00000002 748 749 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 750 #define BGE_MIMODE_AUTOPOLL 0x00000010 751 #define BGE_MIMODE_CLKCNT 0x001F0000 752 753 754 /* 755 * Send data initiator control registers. 756 */ 757 #define BGE_SDI_MODE 0x0C00 758 #define BGE_SDI_STATUS 0x0C04 759 #define BGE_SDI_STATS_CTL 0x0C08 760 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 761 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 762 #define BGE_LOCSTATS_COS0 0x0C80 763 #define BGE_LOCSTATS_COS1 0x0C84 764 #define BGE_LOCSTATS_COS2 0x0C88 765 #define BGE_LOCSTATS_COS3 0x0C8C 766 #define BGE_LOCSTATS_COS4 0x0C90 767 #define BGE_LOCSTATS_COS5 0x0C84 768 #define BGE_LOCSTATS_COS6 0x0C98 769 #define BGE_LOCSTATS_COS7 0x0C9C 770 #define BGE_LOCSTATS_COS8 0x0CA0 771 #define BGE_LOCSTATS_COS9 0x0CA4 772 #define BGE_LOCSTATS_COS10 0x0CA8 773 #define BGE_LOCSTATS_COS11 0x0CAC 774 #define BGE_LOCSTATS_COS12 0x0CB0 775 #define BGE_LOCSTATS_COS13 0x0CB4 776 #define BGE_LOCSTATS_COS14 0x0CB8 777 #define BGE_LOCSTATS_COS15 0x0CBC 778 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 779 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 780 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 781 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 782 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 783 #define BGE_LOCSTATS_IRQS 0x0CD4 784 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 785 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 786 787 /* Send Data Initiator mode register */ 788 #define BGE_SDIMODE_RESET 0x00000001 789 #define BGE_SDIMODE_ENABLE 0x00000002 790 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 791 792 /* Send Data Initiator stats register */ 793 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 794 795 /* Send Data Initiator stats control register */ 796 #define BGE_SDISTATSCTL_ENABLE 0x00000001 797 #define BGE_SDISTATSCTL_FASTER 0x00000002 798 #define BGE_SDISTATSCTL_CLEAR 0x00000004 799 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 800 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 801 802 /* 803 * Send Data Completion Control registers 804 */ 805 #define BGE_SDC_MODE 0x1000 806 #define BGE_SDC_STATUS 0x1004 807 808 /* Send Data completion mode register */ 809 #define BGE_SDCMODE_RESET 0x00000001 810 #define BGE_SDCMODE_ENABLE 0x00000002 811 #define BGE_SDCMODE_ATTN 0x00000004 812 813 /* Send Data completion status register */ 814 #define BGE_SDCSTAT_ATTN 0x00000004 815 816 /* 817 * Send BD Ring Selector Control registers 818 */ 819 #define BGE_SRS_MODE 0x1400 820 #define BGE_SRS_STATUS 0x1404 821 #define BGE_SRS_HWDIAG 0x1408 822 #define BGE_SRS_LOC_NIC_CONS0 0x1440 823 #define BGE_SRS_LOC_NIC_CONS1 0x1444 824 #define BGE_SRS_LOC_NIC_CONS2 0x1448 825 #define BGE_SRS_LOC_NIC_CONS3 0x144C 826 #define BGE_SRS_LOC_NIC_CONS4 0x1450 827 #define BGE_SRS_LOC_NIC_CONS5 0x1454 828 #define BGE_SRS_LOC_NIC_CONS6 0x1458 829 #define BGE_SRS_LOC_NIC_CONS7 0x145C 830 #define BGE_SRS_LOC_NIC_CONS8 0x1460 831 #define BGE_SRS_LOC_NIC_CONS9 0x1464 832 #define BGE_SRS_LOC_NIC_CONS10 0x1468 833 #define BGE_SRS_LOC_NIC_CONS11 0x146C 834 #define BGE_SRS_LOC_NIC_CONS12 0x1470 835 #define BGE_SRS_LOC_NIC_CONS13 0x1474 836 #define BGE_SRS_LOC_NIC_CONS14 0x1478 837 #define BGE_SRS_LOC_NIC_CONS15 0x147C 838 839 /* Send BD Ring Selector Mode register */ 840 #define BGE_SRSMODE_RESET 0x00000001 841 #define BGE_SRSMODE_ENABLE 0x00000002 842 #define BGE_SRSMODE_ATTN 0x00000004 843 844 /* Send BD Ring Selector Status register */ 845 #define BGE_SRSSTAT_ERROR 0x00000004 846 847 /* Send BD Ring Selector HW Diagnostics register */ 848 #define BGE_SRSHWDIAG_STATE 0x0000000F 849 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 850 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 851 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 852 853 /* 854 * Send BD Initiator Selector Control registers 855 */ 856 #define BGE_SBDI_MODE 0x1800 857 #define BGE_SBDI_STATUS 0x1804 858 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 859 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 860 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 861 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 862 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 863 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 864 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 865 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 866 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 867 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 868 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 869 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 870 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 871 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 872 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 873 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 874 875 /* Send BD Initiator Mode register */ 876 #define BGE_SBDIMODE_RESET 0x00000001 877 #define BGE_SBDIMODE_ENABLE 0x00000002 878 #define BGE_SBDIMODE_ATTN 0x00000004 879 880 /* Send BD Initiator Status register */ 881 #define BGE_SBDISTAT_ERROR 0x00000004 882 883 /* 884 * Send BD Completion Control registers 885 */ 886 #define BGE_SBDC_MODE 0x1C00 887 #define BGE_SBDC_STATUS 0x1C04 888 889 /* Send BD Completion Control Mode register */ 890 #define BGE_SBDCMODE_RESET 0x00000001 891 #define BGE_SBDCMODE_ENABLE 0x00000002 892 #define BGE_SBDCMODE_ATTN 0x00000004 893 894 /* Send BD Completion Control Status register */ 895 #define BGE_SBDCSTAT_ATTN 0x00000004 896 897 /* 898 * Receive List Placement Control registers 899 */ 900 #define BGE_RXLP_MODE 0x2000 901 #define BGE_RXLP_STATUS 0x2004 902 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 903 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 904 #define BGE_RXLP_CFG 0x2010 905 #define BGE_RXLP_STATS_CTL 0x2014 906 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 907 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 908 #define BGE_RXLP_HEAD0 0x2100 909 #define BGE_RXLP_TAIL0 0x2104 910 #define BGE_RXLP_COUNT0 0x2108 911 #define BGE_RXLP_HEAD1 0x2110 912 #define BGE_RXLP_TAIL1 0x2114 913 #define BGE_RXLP_COUNT1 0x2118 914 #define BGE_RXLP_HEAD2 0x2120 915 #define BGE_RXLP_TAIL2 0x2124 916 #define BGE_RXLP_COUNT2 0x2128 917 #define BGE_RXLP_HEAD3 0x2130 918 #define BGE_RXLP_TAIL3 0x2134 919 #define BGE_RXLP_COUNT3 0x2138 920 #define BGE_RXLP_HEAD4 0x2140 921 #define BGE_RXLP_TAIL4 0x2144 922 #define BGE_RXLP_COUNT4 0x2148 923 #define BGE_RXLP_HEAD5 0x2150 924 #define BGE_RXLP_TAIL5 0x2154 925 #define BGE_RXLP_COUNT5 0x2158 926 #define BGE_RXLP_HEAD6 0x2160 927 #define BGE_RXLP_TAIL6 0x2164 928 #define BGE_RXLP_COUNT6 0x2168 929 #define BGE_RXLP_HEAD7 0x2170 930 #define BGE_RXLP_TAIL7 0x2174 931 #define BGE_RXLP_COUNT7 0x2178 932 #define BGE_RXLP_HEAD8 0x2180 933 #define BGE_RXLP_TAIL8 0x2184 934 #define BGE_RXLP_COUNT8 0x2188 935 #define BGE_RXLP_HEAD9 0x2190 936 #define BGE_RXLP_TAIL9 0x2194 937 #define BGE_RXLP_COUNT9 0x2198 938 #define BGE_RXLP_HEAD10 0x21A0 939 #define BGE_RXLP_TAIL10 0x21A4 940 #define BGE_RXLP_COUNT10 0x21A8 941 #define BGE_RXLP_HEAD11 0x21B0 942 #define BGE_RXLP_TAIL11 0x21B4 943 #define BGE_RXLP_COUNT11 0x21B8 944 #define BGE_RXLP_HEAD12 0x21C0 945 #define BGE_RXLP_TAIL12 0x21C4 946 #define BGE_RXLP_COUNT12 0x21C8 947 #define BGE_RXLP_HEAD13 0x21D0 948 #define BGE_RXLP_TAIL13 0x21D4 949 #define BGE_RXLP_COUNT13 0x21D8 950 #define BGE_RXLP_HEAD14 0x21E0 951 #define BGE_RXLP_TAIL14 0x21E4 952 #define BGE_RXLP_COUNT14 0x21E8 953 #define BGE_RXLP_HEAD15 0x21F0 954 #define BGE_RXLP_TAIL15 0x21F4 955 #define BGE_RXLP_COUNT15 0x21F8 956 #define BGE_RXLP_LOCSTAT_COS0 0x2200 957 #define BGE_RXLP_LOCSTAT_COS1 0x2204 958 #define BGE_RXLP_LOCSTAT_COS2 0x2208 959 #define BGE_RXLP_LOCSTAT_COS3 0x220C 960 #define BGE_RXLP_LOCSTAT_COS4 0x2210 961 #define BGE_RXLP_LOCSTAT_COS5 0x2214 962 #define BGE_RXLP_LOCSTAT_COS6 0x2218 963 #define BGE_RXLP_LOCSTAT_COS7 0x221C 964 #define BGE_RXLP_LOCSTAT_COS8 0x2220 965 #define BGE_RXLP_LOCSTAT_COS9 0x2224 966 #define BGE_RXLP_LOCSTAT_COS10 0x2228 967 #define BGE_RXLP_LOCSTAT_COS11 0x222C 968 #define BGE_RXLP_LOCSTAT_COS12 0x2230 969 #define BGE_RXLP_LOCSTAT_COS13 0x2234 970 #define BGE_RXLP_LOCSTAT_COS14 0x2238 971 #define BGE_RXLP_LOCSTAT_COS15 0x223C 972 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 973 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 974 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 975 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 976 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 977 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 978 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 979 980 981 /* Receive List Placement mode register */ 982 #define BGE_RXLPMODE_RESET 0x00000001 983 #define BGE_RXLPMODE_ENABLE 0x00000002 984 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 985 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 986 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 987 988 /* Receive List Placement Status register */ 989 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 990 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 991 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 992 993 /* 994 * Receive Data and Receive BD Initiator Control Registers 995 */ 996 #define BGE_RDBDI_MODE 0x2400 997 #define BGE_RDBDI_STATUS 0x2404 998 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 999 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1000 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1001 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1002 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1003 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1004 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1005 #define BGE_RX_STD_RCB_NICADDR 0x245C 1006 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1007 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1008 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1009 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1010 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1011 #define BGE_RDBDI_STD_RX_CONS 0x2474 1012 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1013 #define BGE_RDBDI_RETURN_PROD0 0x2480 1014 #define BGE_RDBDI_RETURN_PROD1 0x2484 1015 #define BGE_RDBDI_RETURN_PROD2 0x2488 1016 #define BGE_RDBDI_RETURN_PROD3 0x248C 1017 #define BGE_RDBDI_RETURN_PROD4 0x2490 1018 #define BGE_RDBDI_RETURN_PROD5 0x2494 1019 #define BGE_RDBDI_RETURN_PROD6 0x2498 1020 #define BGE_RDBDI_RETURN_PROD7 0x249C 1021 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1022 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1023 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1024 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1025 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1026 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1027 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1028 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1029 #define BGE_RDBDI_HWDIAG 0x24C0 1030 1031 1032 /* Receive Data and Receive BD Initiator Mode register */ 1033 #define BGE_RDBDIMODE_RESET 0x00000001 1034 #define BGE_RDBDIMODE_ENABLE 0x00000002 1035 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1036 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1037 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1038 1039 /* Receive Data and Receive BD Initiator Status register */ 1040 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1041 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1042 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1043 1044 1045 /* 1046 * Receive Data Completion Control registers 1047 */ 1048 #define BGE_RDC_MODE 0x2800 1049 1050 /* Receive Data Completion Mode register */ 1051 #define BGE_RDCMODE_RESET 0x00000001 1052 #define BGE_RDCMODE_ENABLE 0x00000002 1053 #define BGE_RDCMODE_ATTN 0x00000004 1054 1055 /* 1056 * Receive BD Initiator Control registers 1057 */ 1058 #define BGE_RBDI_MODE 0x2C00 1059 #define BGE_RBDI_STATUS 0x2C04 1060 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1061 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1062 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1063 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1064 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1065 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1066 1067 /* Receive BD Initiator Mode register */ 1068 #define BGE_RBDIMODE_RESET 0x00000001 1069 #define BGE_RBDIMODE_ENABLE 0x00000002 1070 #define BGE_RBDIMODE_ATTN 0x00000004 1071 1072 /* Receive BD Initiator Status register */ 1073 #define BGE_RBDISTAT_ATTN 0x00000004 1074 1075 /* 1076 * Receive BD Completion Control registers 1077 */ 1078 #define BGE_RBDC_MODE 0x3000 1079 #define BGE_RBDC_STATUS 0x3004 1080 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1081 #define BGE_RBDC_STD_BD_PROD 0x300C 1082 #define BGE_RBDC_MINI_BD_PROD 0x3010 1083 1084 /* Receive BD completion mode register */ 1085 #define BGE_RBDCMODE_RESET 0x00000001 1086 #define BGE_RBDCMODE_ENABLE 0x00000002 1087 #define BGE_RBDCMODE_ATTN 0x00000004 1088 1089 /* Receive BD completion status register */ 1090 #define BGE_RBDCSTAT_ERROR 0x00000004 1091 1092 /* 1093 * Receive List Selector Control registers 1094 */ 1095 #define BGE_RXLS_MODE 0x3400 1096 #define BGE_RXLS_STATUS 0x3404 1097 1098 /* Receive List Selector Mode register */ 1099 #define BGE_RXLSMODE_RESET 0x00000001 1100 #define BGE_RXLSMODE_ENABLE 0x00000002 1101 #define BGE_RXLSMODE_ATTN 0x00000004 1102 1103 /* Receive List Selector Status register */ 1104 #define BGE_RXLSSTAT_ERROR 0x00000004 1105 1106 /* 1107 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1108 */ 1109 #define BGE_MBCF_MODE 0x3800 1110 #define BGE_MBCF_STATUS 0x3804 1111 1112 /* Mbuf Cluster Free mode register */ 1113 #define BGE_MBCFMODE_RESET 0x00000001 1114 #define BGE_MBCFMODE_ENABLE 0x00000002 1115 #define BGE_MBCFMODE_ATTN 0x00000004 1116 1117 /* Mbuf Cluster Free status register */ 1118 #define BGE_MBCFSTAT_ERROR 0x00000004 1119 1120 /* 1121 * Host Coalescing Control registers 1122 */ 1123 #define BGE_HCC_MODE 0x3C00 1124 #define BGE_HCC_STATUS 0x3C04 1125 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1126 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1127 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1128 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1129 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1130 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1131 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1132 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1133 #define BGE_HCC_STATS_TICKS 0x3C28 1134 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1135 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1136 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1137 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1138 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1139 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1140 #define BGE_FLOW_ATTN 0x3C48 1141 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1142 #define BGE_HCC_STD_BD_CONS 0x3C54 1143 #define BGE_HCC_MINI_BD_CONS 0x3C58 1144 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1145 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1146 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1147 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1148 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1149 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1150 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1151 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1152 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1153 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1154 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1155 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1156 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1157 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1158 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1159 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1160 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1161 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1162 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1163 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1164 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1165 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1166 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1167 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1168 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1169 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1170 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1171 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1172 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1173 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1174 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1175 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1176 1177 1178 /* Host coalescing mode register */ 1179 #define BGE_HCCMODE_RESET 0x00000001 1180 #define BGE_HCCMODE_ENABLE 0x00000002 1181 #define BGE_HCCMODE_ATTN 0x00000004 1182 #define BGE_HCCMODE_COAL_NOW 0x00000008 1183 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1184 #define BGE_HCCMODE_64BYTE 0x00000080 1185 #define BGE_HCCMODE_32BYTE 0x00000100 1186 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1187 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1188 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1189 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1190 1191 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1192 1193 #define BGE_STATBLKSZ_FULL 0x00000000 1194 #define BGE_STATBLKSZ_64BYTE 0x00000080 1195 #define BGE_STATBLKSZ_32BYTE 0x00000100 1196 1197 /* Host coalescing status register */ 1198 #define BGE_HCCSTAT_ERROR 0x00000004 1199 1200 /* Flow attention register */ 1201 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1202 #define BGE_FLOWATTN_MEMARB 0x00000080 1203 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1204 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1205 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1206 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1207 #define BGE_FLOWATTN_RDBDI 0x00080000 1208 #define BGE_FLOWATTN_RXLS 0x00100000 1209 #define BGE_FLOWATTN_RXLP 0x00200000 1210 #define BGE_FLOWATTN_RBDC 0x00400000 1211 #define BGE_FLOWATTN_RBDI 0x00800000 1212 #define BGE_FLOWATTN_SDC 0x08000000 1213 #define BGE_FLOWATTN_SDI 0x10000000 1214 #define BGE_FLOWATTN_SRS 0x20000000 1215 #define BGE_FLOWATTN_SBDC 0x40000000 1216 #define BGE_FLOWATTN_SBDI 0x80000000 1217 1218 /* 1219 * Memory arbiter registers 1220 */ 1221 #define BGE_MARB_MODE 0x4000 1222 #define BGE_MARB_STATUS 0x4004 1223 #define BGE_MARB_TRAPADDR_HI 0x4008 1224 #define BGE_MARB_TRAPADDR_LO 0x400C 1225 1226 /* Memory arbiter mode register */ 1227 #define BGE_MARBMODE_RESET 0x00000001 1228 #define BGE_MARBMODE_ENABLE 0x00000002 1229 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1230 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1231 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1232 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1233 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1234 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1235 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1236 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1237 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1238 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1239 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1240 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1241 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1242 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1243 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1244 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1245 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1246 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1247 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1248 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1249 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1250 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1251 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1252 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1253 1254 /* Memory arbiter status register */ 1255 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1256 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1257 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1258 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1259 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1260 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1261 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1262 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1263 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1264 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1265 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1266 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1267 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1268 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1269 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1270 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1271 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1272 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1273 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1274 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1275 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1276 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1277 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1278 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1279 1280 /* 1281 * Buffer manager control registers 1282 */ 1283 #define BGE_BMAN_MODE 0x4400 1284 #define BGE_BMAN_STATUS 0x4404 1285 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1286 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1287 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1288 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1289 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1290 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1291 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1292 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1293 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1294 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1295 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1296 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1297 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1298 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1299 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1300 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1301 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1302 #define BGE_BMAN_HWDIAG_1 0x444C 1303 #define BGE_BMAN_HWDIAG_2 0x4450 1304 #define BGE_BMAN_HWDIAG_3 0x4454 1305 1306 /* Buffer manager mode register */ 1307 #define BGE_BMANMODE_RESET 0x00000001 1308 #define BGE_BMANMODE_ENABLE 0x00000002 1309 #define BGE_BMANMODE_ATTN 0x00000004 1310 #define BGE_BMANMODE_TESTMODE 0x00000008 1311 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1312 1313 /* Buffer manager status register */ 1314 #define BGE_BMANSTAT_ERRO 0x00000004 1315 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1316 1317 1318 /* 1319 * Read DMA Control registers 1320 */ 1321 #define BGE_RDMA_MODE 0x4800 1322 #define BGE_RDMA_STATUS 0x4804 1323 1324 /* Read DMA mode register */ 1325 #define BGE_RDMAMODE_RESET 0x00000001 1326 #define BGE_RDMAMODE_ENABLE 0x00000002 1327 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1328 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1329 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1330 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1331 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1332 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1333 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1334 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1335 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1336 1337 /* Alternate encodings for PCI-Express, from Broadcom-supplied Linux driver */ 1338 #define BGE_RDMA_MODE_FIFO_LONG_BURST ((1<<17) || (1 << 16)) 1339 #define BGE_RDMA_MODE_FIFO_SIZE_128 (1 << 17) 1340 1341 /* Read DMA status register */ 1342 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1343 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1344 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1345 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1346 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1347 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1348 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1349 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1350 1351 /* 1352 * Write DMA control registers 1353 */ 1354 #define BGE_WDMA_MODE 0x4C00 1355 #define BGE_WDMA_STATUS 0x4C04 1356 1357 /* Write DMA mode register */ 1358 #define BGE_WDMAMODE_RESET 0x00000001 1359 #define BGE_WDMAMODE_ENABLE 0x00000002 1360 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1361 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1362 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1363 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1364 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1365 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1366 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1367 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1368 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1369 1370 /* Write DMA status register */ 1371 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1372 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1373 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1374 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1375 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1376 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1377 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1378 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1379 1380 1381 /* 1382 * RX CPU registers 1383 */ 1384 #define BGE_RXCPU_MODE 0x5000 1385 #define BGE_RXCPU_STATUS 0x5004 1386 #define BGE_RXCPU_PC 0x501C 1387 1388 /* RX CPU mode register */ 1389 #define BGE_RXCPUMODE_RESET 0x00000001 1390 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1391 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1392 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1393 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1394 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1395 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1396 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1397 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1398 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1399 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1400 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1401 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1402 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1403 1404 /* RX CPU status register */ 1405 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1406 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1407 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1408 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1409 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1410 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1411 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1412 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1413 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1414 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1415 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1416 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1417 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1418 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1419 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1420 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1421 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1422 1423 1424 /* 1425 * TX CPU registers 1426 */ 1427 #define BGE_TXCPU_MODE 0x5400 1428 #define BGE_TXCPU_STATUS 0x5404 1429 #define BGE_TXCPU_PC 0x541C 1430 1431 /* TX CPU mode register */ 1432 #define BGE_TXCPUMODE_RESET 0x00000001 1433 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1434 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1435 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1436 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1437 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1438 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1439 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1440 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1441 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1442 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1443 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1444 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1445 1446 /* TX CPU status register */ 1447 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1448 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1449 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1450 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1451 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1452 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1453 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1454 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1455 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1456 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1457 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1458 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1459 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1460 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1461 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1462 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1463 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1464 1465 1466 /* 1467 * Low priority mailbox registers 1468 */ 1469 #define BGE_LPMBX_IRQ0_HI 0x5800 1470 #define BGE_LPMBX_IRQ0_LO 0x5804 1471 #define BGE_LPMBX_IRQ1_HI 0x5808 1472 #define BGE_LPMBX_IRQ1_LO 0x580C 1473 #define BGE_LPMBX_IRQ2_HI 0x5810 1474 #define BGE_LPMBX_IRQ2_LO 0x5814 1475 #define BGE_LPMBX_IRQ3_HI 0x5818 1476 #define BGE_LPMBX_IRQ3_LO 0x581C 1477 #define BGE_LPMBX_GEN0_HI 0x5820 1478 #define BGE_LPMBX_GEN0_LO 0x5824 1479 #define BGE_LPMBX_GEN1_HI 0x5828 1480 #define BGE_LPMBX_GEN1_LO 0x582C 1481 #define BGE_LPMBX_GEN2_HI 0x5830 1482 #define BGE_LPMBX_GEN2_LO 0x5834 1483 #define BGE_LPMBX_GEN3_HI 0x5828 1484 #define BGE_LPMBX_GEN3_LO 0x582C 1485 #define BGE_LPMBX_GEN4_HI 0x5840 1486 #define BGE_LPMBX_GEN4_LO 0x5844 1487 #define BGE_LPMBX_GEN5_HI 0x5848 1488 #define BGE_LPMBX_GEN5_LO 0x584C 1489 #define BGE_LPMBX_GEN6_HI 0x5850 1490 #define BGE_LPMBX_GEN6_LO 0x5854 1491 #define BGE_LPMBX_GEN7_HI 0x5858 1492 #define BGE_LPMBX_GEN7_LO 0x585C 1493 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1494 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1495 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1496 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1497 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1498 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1499 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1500 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1501 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1502 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1503 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1504 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1505 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1506 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1507 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1508 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1509 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1510 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1511 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1512 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1513 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1514 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1515 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1516 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1517 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1518 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1519 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1520 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1521 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1522 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1523 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1524 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1525 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1526 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1527 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1528 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1529 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1530 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1531 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1532 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1533 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1534 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1535 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1536 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1537 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1538 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1539 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1540 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1541 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1542 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1543 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1544 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1545 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1546 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1547 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1548 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1549 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1550 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1551 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1552 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1553 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1554 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1555 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1556 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1557 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1558 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1559 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1560 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1561 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1562 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1563 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1564 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1565 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1566 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1567 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1568 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1569 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1570 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1571 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1572 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1573 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1574 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1575 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1576 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1577 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1578 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1579 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1580 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1581 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1582 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1583 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1584 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1585 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1586 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1587 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1588 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1589 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1590 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1591 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1592 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1593 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1594 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1595 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1596 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1597 1598 /* 1599 * Flow throw Queue reset register 1600 */ 1601 #define BGE_FTQ_RESET 0x5C00 1602 1603 #define BGE_FTQRESET_DMAREAD 0x00000002 1604 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1605 #define BGE_FTQRESET_DMADONE 0x00000010 1606 #define BGE_FTQRESET_SBDC 0x00000020 1607 #define BGE_FTQRESET_SDI 0x00000040 1608 #define BGE_FTQRESET_WDMA 0x00000080 1609 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1610 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1611 #define BGE_FTQRESET_SDC 0x00000400 1612 #define BGE_FTQRESET_HCC 0x00000800 1613 #define BGE_FTQRESET_TXFIFO 0x00001000 1614 #define BGE_FTQRESET_MBC 0x00002000 1615 #define BGE_FTQRESET_RBDC 0x00004000 1616 #define BGE_FTQRESET_RXLP 0x00008000 1617 #define BGE_FTQRESET_RDBDI 0x00010000 1618 #define BGE_FTQRESET_RDC 0x00020000 1619 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1620 1621 /* 1622 * Message Signaled Interrupt registers 1623 */ 1624 #define BGE_MSI_MODE 0x6000 1625 #define BGE_MSI_STATUS 0x6004 1626 #define BGE_MSI_FIFOACCESS 0x6008 1627 1628 /* MSI mode register */ 1629 #define BGE_MSIMODE_RESET 0x00000001 1630 #define BGE_MSIMODE_ENABLE 0x00000002 1631 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1632 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1633 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1634 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1635 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1636 1637 /* MSI status register */ 1638 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1639 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1640 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1641 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1642 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1643 1644 1645 /* 1646 * DMA Completion registers 1647 */ 1648 #define BGE_DMAC_MODE 0x6400 1649 1650 /* DMA Completion mode register */ 1651 #define BGE_DMACMODE_RESET 0x00000001 1652 #define BGE_DMACMODE_ENABLE 0x00000002 1653 1654 1655 /* 1656 * General control registers. 1657 */ 1658 #define BGE_MODE_CTL 0x6800 1659 #define BGE_MISC_CFG 0x6804 1660 #define BGE_MISC_LOCAL_CTL 0x6808 1661 #define BGE_MISC_TIMER 0x680c 1662 #define BGE_EE_ADDR 0x6838 1663 #define BGE_EE_DATA 0x683C 1664 #define BGE_EE_CTL 0x6840 1665 #define BGE_MDI_CTL 0x6844 1666 #define BGE_EE_DELAY 0x6848 1667 #define BGE_FASTBOOT_PC 0x6894 1668 /* 1669 * XXX: Those names are made up as I have no documentation about it; 1670 * I only know it is only used in the PCI-Express case. 1671 */ 1672 #define BGE_PCIE_CTL0 0x7c00 1673 #define BGE_PCIE_CTL1 0x7e2c 1674 /* 1675 * TLP Control Register 1676 * Applicable to BCM5721 and BCM5751 only 1677 */ 1678 #define BGE_TLP_CONTROL_REG 0x7c00 1679 #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1680 1681 /* 1682 * PHY Test Control Register 1683 * Applicable to BCM5721 and BCM5751 only 1684 */ 1685 #define BGE_PHY_TEST_CTRL_REG 0x7e2c 1686 #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1687 #define BGE_PHY_PCIE_LTASS_MODE 0x0040 1688 1689 1690 1691 /* Mode control register */ 1692 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1693 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1694 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1695 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1696 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1697 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1698 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1699 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1700 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1701 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1702 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1703 #define BGE_MODECTL_STACKUP 0x00010000 1704 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1705 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1706 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1707 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1708 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1709 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1710 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1711 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1712 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1713 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1714 1715 /* Misc. config register */ 1716 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1717 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1718 1719 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1720 1721 /* Misc. Local Control */ 1722 #define BGE_MLC_INTR_STATE 0x00000001 1723 #define BGE_MLC_INTR_CLR 0x00000002 1724 #define BGE_MLC_INTR_SET 0x00000004 1725 #define BGE_MLC_INTR_ONATTN 0x00000008 1726 #define BGE_MLC_MISCIO_IN0 0x00000100 1727 #define BGE_MLC_MISCIO_IN1 0x00000200 1728 #define BGE_MLC_MISCIO_IN2 0x00000400 1729 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1730 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1731 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1732 #define BGE_MLC_MISCIO_OUT0 0x00004000 1733 #define BGE_MLC_MISCIO_OUT1 0x00008000 1734 #define BGE_MLC_MISCIO_OUT2 0x00010000 1735 #define BGE_MLC_EXTRAM_ENB 0x00020000 1736 #define BGE_MLC_SRAM_SIZE 0x001C0000 1737 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1738 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1739 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1740 #define BGE_MLC_AUTO_EEPROM 0x01000000 1741 1742 #define BGE_SSRAMSIZE_256KB 0x00000000 1743 #define BGE_SSRAMSIZE_512KB 0x00040000 1744 #define BGE_SSRAMSIZE_1MB 0x00080000 1745 #define BGE_SSRAMSIZE_2MB 0x000C0000 1746 #define BGE_SSRAMSIZE_4MB 0x00100000 1747 #define BGE_SSRAMSIZE_8MB 0x00140000 1748 #define BGE_SSRAMSIZE_16M 0x00180000 1749 1750 /* EEPROM address register */ 1751 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1752 #define BGE_EEADDR_HALFCLK 0x01FF0000 1753 #define BGE_EEADDR_START 0x02000000 1754 #define BGE_EEADDR_DEVID 0x1C000000 1755 #define BGE_EEADDR_RESET 0x20000000 1756 #define BGE_EEADDR_DONE 0x40000000 1757 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1758 1759 #define BGE_EEDEVID(x) ((x & 7) << 26) 1760 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1761 #define BGE_HALFCLK_384SCL 0x60 1762 #define BGE_EE_READCMD \ 1763 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1764 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1765 #define BGE_EE_WRCMD \ 1766 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1767 BGE_EEADDR_START|BGE_EEADDR_DONE) 1768 1769 /* EEPROM Control register */ 1770 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1771 #define BGE_EECTL_CLKOUT 0x00000002 1772 #define BGE_EECTL_CLKIN 0x00000004 1773 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1774 #define BGE_EECTL_DATAOUT 0x00000010 1775 #define BGE_EECTL_DATAIN 0x00000020 1776 1777 /* MDI (MII/GMII) access register */ 1778 #define BGE_MDI_DATA 0x00000001 1779 #define BGE_MDI_DIR 0x00000002 1780 #define BGE_MDI_SEL 0x00000004 1781 #define BGE_MDI_CLK 0x00000008 1782 1783 #define BGE_MEMWIN_START 0x00008000 1784 #define BGE_MEMWIN_END 0x0000FFFF 1785 1786 1787 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1788 do { \ 1789 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1790 (0xFFFF0000 & x)); \ 1791 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1792 } while(0) 1793 1794 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1795 do { \ 1796 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1797 (0xFFFF0000 & x)); \ 1798 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1799 } while(0) 1800 1801 /* 1802 * This magic number is used to prevent PXE restart when we 1803 * issue a software reset. We write this magic number to the 1804 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1805 * code from running. 1806 */ 1807 #define BGE_MAGIC_NUMBER 0x4B657654 1808 1809 typedef struct { 1810 volatile u_int32_t bge_addr_hi; 1811 volatile u_int32_t bge_addr_lo; 1812 } bge_hostaddr; 1813 1814 static __inline void 1815 bge_set_hostaddr(volatile bge_hostaddr *x, bus_addr_t y) 1816 { 1817 x->bge_addr_lo = y & 0xffffffff; 1818 if (sizeof (bus_addr_t) == 8) 1819 x->bge_addr_hi = (u_int64_t)y >> 32; 1820 else 1821 x->bge_addr_hi = 0; 1822 } 1823 1824 /* Ring control block structure */ 1825 struct bge_rcb { 1826 bge_hostaddr bge_hostaddr; 1827 volatile u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 1828 volatile u_int32_t bge_nicaddr; 1829 }; 1830 1831 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1832 1833 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1834 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1835 rcb + offsetof(struct bge_rcb, offset), val) 1836 1837 1838 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1839 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1840 1841 struct bge_tx_bd { 1842 bge_hostaddr bge_addr; 1843 #if BYTE_ORDER == BIG_ENDIAN 1844 volatile u_int16_t bge_len; 1845 volatile u_int16_t bge_flags; 1846 volatile u_int16_t bge_rsvd; 1847 volatile u_int16_t bge_vlan_tag; 1848 #else 1849 volatile u_int16_t bge_flags; 1850 volatile u_int16_t bge_len; 1851 volatile u_int16_t bge_vlan_tag; 1852 volatile u_int16_t bge_rsvd; 1853 #endif 1854 }; 1855 1856 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1857 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1858 #define BGE_TXBDFLAG_END 0x0004 1859 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1860 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1861 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1862 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1863 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1864 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1865 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1866 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1867 #define BGE_TXBDFLAG_NO_CRC 0x8000 1868 1869 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1870 BGE_SEND_RING_1_TO_4 + \ 1871 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1872 1873 struct bge_rx_bd { 1874 bge_hostaddr bge_addr; 1875 #if BYTE_ORDER == BIG_ENDIAN 1876 volatile u_int16_t bge_idx; 1877 volatile u_int16_t bge_len; 1878 volatile u_int16_t bge_type; 1879 volatile u_int16_t bge_flags; 1880 volatile u_int16_t bge_ip_csum; 1881 volatile u_int16_t bge_tcp_udp_csum; 1882 volatile u_int16_t bge_error_flag; 1883 volatile u_int16_t bge_vlan_tag; 1884 #else 1885 volatile u_int16_t bge_len; 1886 volatile u_int16_t bge_idx; 1887 volatile u_int16_t bge_flags; 1888 volatile u_int16_t bge_type; 1889 volatile u_int16_t bge_tcp_udp_csum; 1890 volatile u_int16_t bge_ip_csum; 1891 volatile u_int16_t bge_vlan_tag; 1892 volatile u_int16_t bge_error_flag; 1893 #endif 1894 volatile u_int32_t bge_rsvd; 1895 volatile u_int32_t bge_opaque; 1896 }; 1897 1898 #define BGE_RXBDFLAG_END 0x0004 1899 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1900 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1901 #define BGE_RXBDFLAG_ERROR 0x0400 1902 #define BGE_RXBDFLAG_MINI_RING 0x0800 1903 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1904 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1905 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1906 1907 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1908 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1909 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1910 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1911 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1912 #define BGE_RXERRFLAG_RUNT 0x0020 1913 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1914 #define BGE_RXERRFLAG_GIANT 0x0080 1915 1916 struct bge_sts_idx { 1917 #if BYTE_ORDER == BIG_ENDIAN 1918 volatile u_int16_t bge_tx_cons_idx; 1919 volatile u_int16_t bge_rx_prod_idx; 1920 #else 1921 volatile u_int16_t bge_rx_prod_idx; 1922 volatile u_int16_t bge_tx_cons_idx; 1923 #endif 1924 }; 1925 1926 struct bge_status_block { 1927 volatile u_int32_t bge_status; 1928 volatile u_int32_t bge_rsvd0; 1929 #if BYTE_ORDER == BIG_ENDIAN 1930 volatile u_int16_t bge_rx_std_cons_idx; 1931 volatile u_int16_t bge_rx_jumbo_cons_idx; 1932 volatile u_int16_t bge_rsvd1; 1933 volatile u_int16_t bge_rx_mini_cons_idx; 1934 #else 1935 volatile u_int16_t bge_rx_jumbo_cons_idx; 1936 volatile u_int16_t bge_rx_std_cons_idx; 1937 volatile u_int16_t bge_rx_mini_cons_idx; 1938 volatile u_int16_t bge_rsvd1; 1939 #endif 1940 struct bge_sts_idx bge_idx[16]; 1941 }; 1942 1943 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1944 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1945 1946 #define BGE_STATFLAG_UPDATED 0x00000001 1947 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1948 #define BGE_STATFLAG_ERROR 0x00000004 1949 1950 1951 /* 1952 * Broadcom Vendor ID 1953 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1954 * even though they're now manufactured by Broadcom) 1955 */ 1956 #define BCOM_VENDORID 0x14E4 1957 #define BCOM_DEVICEID_BCM5700 0x1644 1958 #define BCOM_DEVICEID_BCM5701 0x1645 1959 #define BCOM_DEVICEID_BCM5789 0x169d 1960 1961 /* 1962 * Alteon AceNIC PCI vendor/device ID. 1963 */ 1964 #define ALT_VENDORID 0x12AE 1965 #define ALT_DEVICEID_ACENIC 0x0001 1966 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 1967 #define ALT_DEVICEID_BCM5700 0x0003 1968 #define ALT_DEVICEID_BCM5701 0x0004 1969 1970 /* 1971 * 3Com 3c985 PCI vendor/device ID. 1972 */ 1973 #define TC_VENDORID 0x10B7 1974 #define TC_DEVICEID_3C985 0x0001 1975 #define TC_DEVICEID_3C996 0x0003 1976 1977 /* 1978 * SysKonnect PCI vendor ID 1979 */ 1980 #define SK_VENDORID 0x1148 1981 #define SK_DEVICEID_ALTIMA 0x4400 1982 #define SK_SUBSYSID_9D21 0x4421 1983 #define SK_SUBSYSID_9D41 0x4441 1984 1985 /* 1986 * Altima PCI vendor/device ID. 1987 */ 1988 #define ALTIMA_VENDORID 0x173b 1989 #define ALTIMA_DEVICE_AC1000 0x03e8 1990 1991 /* 1992 * Offset of MAC address inside EEPROM. 1993 */ 1994 #define BGE_EE_MAC_OFFSET 0x7C 1995 #define BGE_EE_HWCFG_OFFSET 0xC8 1996 1997 #define BGE_HWCFG_VOLTAGE 0x00000003 1998 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1999 #define BGE_HWCFG_MEDIA 0x00000030 2000 2001 #define BGE_VOLTAGE_1POINT3 0x00000000 2002 #define BGE_VOLTAGE_1POINT8 0x00000001 2003 2004 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2005 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2006 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2007 2008 #define BGE_MEDIA_UNSPEC 0x00000000 2009 #define BGE_MEDIA_COPPER 0x00000010 2010 #define BGE_MEDIA_FIBER 0x00000020 2011 2012 #define BGE_PCI_READ_CMD 0x06000000 2013 #define BGE_PCI_WRITE_CMD 0x70000000 2014 2015 #define BGE_TICKS_PER_SEC 1000000 2016 2017 /* 2018 * Ring size constants. 2019 */ 2020 #define BGE_EVENT_RING_CNT 256 2021 #define BGE_CMD_RING_CNT 64 2022 #define BGE_STD_RX_RING_CNT 512 2023 #define BGE_JUMBO_RX_RING_CNT 256 2024 #define BGE_MINI_RX_RING_CNT 1024 2025 #define BGE_RETURN_RING_CNT 1024 2026 #define BGE_RETURN_RING_CNT_5705 512 2027 2028 /* 2029 * Possible TX ring sizes. 2030 */ 2031 #define BGE_TX_RING_CNT_128 128 2032 #define BGE_TX_RING_BASE_128 0x3800 2033 2034 #define BGE_TX_RING_CNT_256 256 2035 #define BGE_TX_RING_BASE_256 0x3000 2036 2037 #define BGE_TX_RING_CNT_512 512 2038 #define BGE_TX_RING_BASE_512 0x2000 2039 2040 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2041 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2042 2043 /* 2044 * Tigon III statistics counters. 2045 */ 2046 2047 /* Stats counters access through registers */ 2048 struct bge_mac_stats_regs { 2049 u_int32_t ifHCOutOctets; 2050 u_int32_t Reserved0; 2051 u_int32_t etherStatsCollisions; 2052 u_int32_t outXonSent; 2053 u_int32_t outXoffSent; 2054 u_int32_t Reserved1; 2055 u_int32_t dot3StatsInternalMacTransmitErrors; 2056 u_int32_t dot3StatsSingleCollisionFrames; 2057 u_int32_t dot3StatsMultipleCollisionFrames; 2058 u_int32_t dot3StatsDeferredTransmissions; 2059 u_int32_t Reserved2; 2060 u_int32_t dot3StatsExcessiveCollisions; 2061 u_int32_t dot3StatsLateCollisions; 2062 u_int32_t Reserved3[14]; 2063 u_int32_t ifHCOutUcastPkts; 2064 u_int32_t ifHCOutMulticastPkts; 2065 u_int32_t ifHCOutBroadcastPkts; 2066 u_int32_t Reserved4[2]; 2067 u_int32_t ifHCInOctets; 2068 u_int32_t Reserved5; 2069 u_int32_t etherStatsFragments; 2070 u_int32_t ifHCInUcastPkts; 2071 u_int32_t ifHCInMulticastPkts; 2072 u_int32_t ifHCInBroadcastPkts; 2073 u_int32_t dot3StatsFCSErrors; 2074 u_int32_t dot3StatsAlignmentErrors; 2075 u_int32_t xonPauseFramesReceived; 2076 u_int32_t xoffPauseFramesReceived; 2077 u_int32_t macControlFramesReceived; 2078 u_int32_t xoffStateEntered; 2079 u_int32_t dot3StatsFramesTooLong; 2080 u_int32_t etherStatsJabbers; 2081 u_int32_t etherStatsUndersizePkts; 2082 }; 2083 2084 struct bge_stats { 2085 u_int8_t Reserved0[256]; 2086 2087 /* Statistics maintained by Receive MAC. */ 2088 bge_hostaddr ifHCInOctets; 2089 bge_hostaddr Reserved1; 2090 bge_hostaddr etherStatsFragments; 2091 bge_hostaddr ifHCInUcastPkts; 2092 bge_hostaddr ifHCInMulticastPkts; 2093 bge_hostaddr ifHCInBroadcastPkts; 2094 bge_hostaddr dot3StatsFCSErrors; 2095 bge_hostaddr dot3StatsAlignmentErrors; 2096 bge_hostaddr xonPauseFramesReceived; 2097 bge_hostaddr xoffPauseFramesReceived; 2098 bge_hostaddr macControlFramesReceived; 2099 bge_hostaddr xoffStateEntered; 2100 bge_hostaddr dot3StatsFramesTooLong; 2101 bge_hostaddr etherStatsJabbers; 2102 bge_hostaddr etherStatsUndersizePkts; 2103 bge_hostaddr inRangeLengthError; 2104 bge_hostaddr outRangeLengthError; 2105 bge_hostaddr etherStatsPkts64Octets; 2106 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2107 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2108 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2109 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2110 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2111 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2112 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2113 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2114 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2115 2116 bge_hostaddr Unused1[37]; 2117 2118 /* Statistics maintained by Transmit MAC. */ 2119 bge_hostaddr ifHCOutOctets; 2120 bge_hostaddr Reserved2; 2121 bge_hostaddr etherStatsCollisions; 2122 bge_hostaddr outXonSent; 2123 bge_hostaddr outXoffSent; 2124 bge_hostaddr flowControlDone; 2125 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2126 bge_hostaddr dot3StatsSingleCollisionFrames; 2127 bge_hostaddr dot3StatsMultipleCollisionFrames; 2128 bge_hostaddr dot3StatsDeferredTransmissions; 2129 bge_hostaddr Reserved3; 2130 bge_hostaddr dot3StatsExcessiveCollisions; 2131 bge_hostaddr dot3StatsLateCollisions; 2132 bge_hostaddr dot3Collided2Times; 2133 bge_hostaddr dot3Collided3Times; 2134 bge_hostaddr dot3Collided4Times; 2135 bge_hostaddr dot3Collided5Times; 2136 bge_hostaddr dot3Collided6Times; 2137 bge_hostaddr dot3Collided7Times; 2138 bge_hostaddr dot3Collided8Times; 2139 bge_hostaddr dot3Collided9Times; 2140 bge_hostaddr dot3Collided10Times; 2141 bge_hostaddr dot3Collided11Times; 2142 bge_hostaddr dot3Collided12Times; 2143 bge_hostaddr dot3Collided13Times; 2144 bge_hostaddr dot3Collided14Times; 2145 bge_hostaddr dot3Collided15Times; 2146 bge_hostaddr ifHCOutUcastPkts; 2147 bge_hostaddr ifHCOutMulticastPkts; 2148 bge_hostaddr ifHCOutBroadcastPkts; 2149 bge_hostaddr dot3StatsCarrierSenseErrors; 2150 bge_hostaddr ifOutDiscards; 2151 bge_hostaddr ifOutErrors; 2152 2153 bge_hostaddr Unused2[31]; 2154 2155 /* Statistics maintained by Receive List Placement. */ 2156 bge_hostaddr COSIfHCInPkts[16]; 2157 bge_hostaddr COSFramesDroppedDueToFilters; 2158 bge_hostaddr nicDmaWriteQueueFull; 2159 bge_hostaddr nicDmaWriteHighPriQueueFull; 2160 bge_hostaddr nicNoMoreRxBDs; 2161 bge_hostaddr ifInDiscards; 2162 bge_hostaddr ifInErrors; 2163 bge_hostaddr nicRecvThresholdHit; 2164 2165 bge_hostaddr Unused3[9]; 2166 2167 /* Statistics maintained by Send Data Initiator. */ 2168 bge_hostaddr COSIfHCOutPkts[16]; 2169 bge_hostaddr nicDmaReadQueueFull; 2170 bge_hostaddr nicDmaReadHighPriQueueFull; 2171 bge_hostaddr nicSendDataCompQueueFull; 2172 2173 /* Statistics maintained by Host Coalescing. */ 2174 bge_hostaddr nicRingSetSendProdIndex; 2175 bge_hostaddr nicRingStatusUpdate; 2176 bge_hostaddr nicInterrupts; 2177 bge_hostaddr nicAvoidedInterrupts; 2178 bge_hostaddr nicSendThresholdHit; 2179 2180 u_int8_t Reserved4[320]; 2181 }; 2182 2183 /* 2184 * Tigon general information block. This resides in host memory 2185 * and contains the status counters, ring control blocks and 2186 * producer pointers. 2187 */ 2188 2189 struct bge_gib { 2190 struct bge_stats bge_stats; 2191 struct bge_rcb bge_tx_rcb[16]; 2192 struct bge_rcb bge_std_rx_rcb; 2193 struct bge_rcb bge_jumbo_rx_rcb; 2194 struct bge_rcb bge_mini_rx_rcb; 2195 struct bge_rcb bge_return_rcb; 2196 }; 2197 2198 /* 2199 * NOTE! On the Alpha, we have an alignment constraint. 2200 * The first thing in the packet is a 14-byte Ethernet header. 2201 * This means that the packet is misaligned. To compensate, 2202 * we actually offset the data 2 bytes into the cluster. This 2203 * alignes the packet after the Ethernet header at a 32-bit 2204 * boundary. 2205 */ 2206 2207 #define ETHER_ALIGN 2 2208 2209 #define BGE_FRAMELEN ETHER_MAX_LEN 2210 #define BGE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_CRC_LEN) 2211 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2212 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2213 #define BGE_PAGE_SIZE PAGE_SIZE 2214 #define BGE_MIN_FRAMELEN 60 2215 2216 /* 2217 * Other utility macros. 2218 */ 2219 #define BGE_INC(x, y) (x) = (x + 1) % y 2220 2221 /* 2222 * Vital product data and structures. 2223 */ 2224 #define BGE_VPD_FLAG 0x8000 2225 2226 /* VPD structures */ 2227 struct vpd_res { 2228 u_int8_t vr_id; 2229 u_int8_t vr_len; 2230 u_int8_t vr_pad; 2231 }; 2232 2233 struct vpd_key { 2234 char vk_key[2]; 2235 u_int8_t vk_len; 2236 }; 2237 2238 #define VPD_RES_ID 0x82 /* ID string */ 2239 #define VPD_RES_READ 0x90 /* start of read only area */ 2240 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2241 #define VPD_RES_END 0x78 /* end tag */ 2242 2243 2244 /* 2245 * Register access macros. The Tigon always uses memory mapped register 2246 * accesses and all registers must be accessed with 32 bit operations. 2247 */ 2248 2249 #define CSR_WRITE_4(sc, reg, val) \ 2250 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2251 2252 #define CSR_READ_4(sc, reg) \ 2253 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2254 2255 #define BGE_SETBIT(sc, reg, x) \ 2256 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2257 #define BGE_CLRBIT(sc, reg, x) \ 2258 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2259 2260 #define PCI_SETBIT(pc, tag, reg, x) \ 2261 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 2262 #define PCI_CLRBIT(pc, tag, reg, x) \ 2263 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 2264 2265 /* 2266 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2267 * values are tuneable. They control the actual amount of buffers 2268 * allocated for the standard, mini and jumbo receive rings. 2269 */ 2270 2271 #define BGE_SSLOTS 256 2272 #define BGE_MSLOTS 256 2273 #define BGE_JSLOTS 384 2274 #define BGE_RSLOTS 256 2275 2276 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2277 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2278 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2279 #define BGE_JPAGESZ PAGE_SIZE 2280 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2281 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2282 2283 /* 2284 * Ring structures. Most of these reside in host memory and we tell 2285 * the NIC where they are via the ring control blocks. The exceptions 2286 * are the tx and command rings, which live in NIC memory and which 2287 * we access via the shared memory window. 2288 */ 2289 struct bge_ring_data { 2290 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2291 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2292 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2293 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2294 struct bge_status_block bge_status_block; 2295 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2296 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2297 struct bge_gib bge_info; 2298 }; 2299 2300 #define BGE_RING_DMA_ADDR(sc, offset) \ 2301 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2302 offsetof(struct bge_ring_data, offset)) 2303 2304 /* 2305 * Number of DMA segments in a TxCB. Note that this is carefully 2306 * chosen to make the total struct size an even power of two. It's 2307 * critical that no TxCB be split across a page boundary since 2308 * no attempt is made to allocate physically contiguous memory. 2309 * 2310 */ 2311 #if 0 /* pre-TSO values */ 2312 #define BGE_TXDMA_MAX ETHER_MAX_LEN_JUMBO 2313 #ifdef _LP64 2314 #define BGE_NTXSEG 30 2315 #else 2316 #define BGE_NTXSEG 31 2317 #endif 2318 #else /* TSO values */ 2319 #define BGE_TXDMA_MAX (round_page(IP_MAXPACKET)) /* for TSO */ 2320 #ifdef _LP64 2321 #define BGE_NTXSEG 120 /* XXX just a guess */ 2322 #else 2323 #define BGE_NTXSEG 124 /* XXX just a guess */ 2324 #endif 2325 #endif /* TSO values */ 2326 2327 2328 /* 2329 * Mbuf pointers. We need these to keep track of the virtual addresses 2330 * of our mbuf chains since we can only convert from physical to virtual, 2331 * not the other way around. 2332 */ 2333 struct bge_chain_data { 2334 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2335 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2336 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2337 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2338 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2339 bus_dmamap_t bge_rx_jumbo_map; 2340 /* Stick the jumbo mem management stuff here too. */ 2341 void * bge_jslots[BGE_JSLOTS]; 2342 void * bge_jumbo_buf; 2343 }; 2344 2345 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 2346 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2347 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2348 2349 struct bge_type { 2350 u_int16_t bge_vid; 2351 u_int16_t bge_did; 2352 char *bge_name; 2353 }; 2354 2355 #define BGE_HWREV_TIGON 0x01 2356 #define BGE_HWREV_TIGON_II 0x02 2357 #define BGE_TIMEOUT 1000 2358 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2359 2360 struct bge_jpool_entry { 2361 int slot; 2362 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2363 }; 2364 2365 struct bge_bcom_hack { 2366 int reg; 2367 int val; 2368 }; 2369 2370 struct txdmamap_pool_entry { 2371 bus_dmamap_t dmamap; 2372 SLIST_ENTRY(txdmamap_pool_entry) link; 2373 }; 2374 2375 /* 2376 * Flags for bge_flags. 2377 */ 2378 #define BGE_TXRING_VALID 0x0001 2379 #define BGE_RXRING_VALID 0x0002 2380 #define BGE_JUMBO_RXRING_VALID 0x0004 2381 2382 struct bge_softc { 2383 device_t bge_dev; 2384 struct ethercom ethercom; /* interface info */ 2385 bus_space_handle_t bge_bhandle; 2386 bus_space_tag_t bge_btag; 2387 void *bge_intrhand; 2388 pci_chipset_tag_t sc_pc; 2389 pcitag_t sc_pcitag; 2390 2391 struct mii_data bge_mii; 2392 struct ifmedia bge_ifmedia; /* media info */ 2393 u_int8_t bge_extram; /* has external SSRAM */ 2394 u_int8_t bge_tbi; 2395 u_int8_t bge_rx_alignment_bug; 2396 u_int8_t bge_pcie; /* on a PCI Express port */ 2397 u_int32_t bge_return_ring_cnt; 2398 u_int32_t bge_tx_prodidx; 2399 bus_dma_tag_t bge_dmatag; 2400 u_int32_t bge_chipid; 2401 u_int32_t bge_quirks; 2402 u_int32_t bge_local_ctrl_reg; 2403 struct bge_ring_data *bge_rdata; /* rings */ 2404 struct bge_chain_data bge_cdata; /* mbufs */ 2405 bus_dmamap_t bge_ring_map; 2406 u_int16_t bge_tx_saved_considx; 2407 u_int16_t bge_rx_saved_considx; 2408 u_int16_t bge_ev_saved_considx; 2409 u_int16_t bge_std; /* current std ring head */ 2410 u_int16_t bge_jumbo; /* current jumo ring head */ 2411 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2412 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2413 u_int32_t bge_stat_ticks; 2414 u_int32_t bge_rx_coal_ticks; 2415 u_int32_t bge_tx_coal_ticks; 2416 u_int32_t bge_rx_max_coal_bds; 2417 u_int32_t bge_tx_max_coal_bds; 2418 u_int32_t bge_tx_buf_ratio; 2419 int bge_if_flags; 2420 int bge_flags; 2421 int bge_flowflags; 2422 #ifdef BGE_EVENT_COUNTERS 2423 /* 2424 * Event counters. 2425 */ 2426 struct evcnt bge_ev_intr; /* interrupts */ 2427 struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ 2428 struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ 2429 struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ 2430 struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ 2431 struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ 2432 struct evcnt bge_ev_xoffentered;/* XOFF state entered */ 2433 #endif /* BGE_EVENT_COUNTERS */ 2434 int bge_txcnt; 2435 int bge_link; 2436 struct callout bge_timeout; 2437 char *bge_vpd_prodname; 2438 char *bge_vpd_readonly; 2439 int bge_pending_rxintr_change; 2440 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2441 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2442 }; 2443
Indexes created Sat Sep 27 14:09:57 GMT 2025