if_bgereg.h revision 1.49
1 /* $NetBSD: if_bgereg.h,v 1.49 2009/03/22 16:20:06 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 79 #define BGE_UNMAPPED 0x00001000 80 #define BGE_UNMAPPED_END 0x00001FFF 81 #define BGE_DMA_DESCRIPTORS 0x00002000 82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 83 #define BGE_SEND_RING_1_TO_4 0x00004000 84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 85 86 /* Mappings for internal memory configuration */ 87 #define BGE_STD_RX_RINGS 0x00006000 88 #define BGE_STD_RX_RINGS_END 0x00006FFF 89 #define BGE_JUMBO_RX_RINGS 0x00007000 90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 91 #define BGE_BUFFPOOL_1 0x00008000 92 #define BGE_BUFFPOOL_1_END 0x0000FFFF 93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 94 #define BGE_BUFFPOOL_2_END 0x00017FFF 95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 96 #define BGE_BUFFPOOL_3_END 0x0001FFFF 97 98 /* Mappings for external SSRAM configurations */ 99 #define BGE_SEND_RING_5_TO_6 0x00006000 100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 101 #define BGE_SEND_RING_7_TO_8 0x00007000 102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 103 #define BGE_SEND_RING_9_TO_16 0x00008000 104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 105 #define BGE_EXT_STD_RX_RINGS 0x0000C000 106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 109 #define BGE_MINI_RX_RINGS 0x0000E000 110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 112 #define BGE_AVAIL_REGION1_END 0x00017FFF 113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 114 #define BGE_AVAIL_REGION2_END 0x0001FFFF 115 #define BGE_EXT_SSRAM 0x00020000 116 #define BGE_EXT_SSRAM_END 0x000FFFFF 117 118 119 /* 120 * BCM570x register offsets. These are memory mapped registers 121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 122 * Each register must be accessed using 32 bit operations. 123 * 124 * All registers are accessed through a 32K shared memory block. 125 * The first group of registers are actually copies of the PCI 126 * configuration space registers. 127 */ 128 129 /* 130 * PCI registers defined in the PCI 2.2 spec. 131 */ 132 #define BGE_PCI_VID 0x00 133 #define BGE_PCI_DID 0x02 134 #define BGE_PCI_CMD 0x04 135 #define BGE_PCI_STS 0x06 136 #define BGE_PCI_REV 0x08 137 #define BGE_PCI_CLASS 0x09 138 #define BGE_PCI_CACHESZ 0x0C 139 #define BGE_PCI_LATTIMER 0x0D 140 #define BGE_PCI_HDRTYPE 0x0E 141 #define BGE_PCI_BIST 0x0F 142 #define BGE_PCI_BAR0 0x10 143 #define BGE_PCI_BAR1 0x14 144 #define BGE_PCI_SUBSYS 0x2C 145 #define BGE_PCI_SUBVID 0x2E 146 #define BGE_PCI_ROMBASE 0x30 147 #define BGE_PCI_CAPPTR 0x34 148 #define BGE_PCI_INTLINE 0x3C 149 #define BGE_PCI_INTPIN 0x3D 150 #define BGE_PCI_MINGNT 0x3E 151 #define BGE_PCI_MAXLAT 0x3F 152 #define BGE_PCI_PCIXCAP 0x40 153 #define BGE_PCI_NEXTPTR_PM 0x41 154 #define BGE_PCI_PCIX_CMD 0x42 155 #define BGE_PCI_PCIX_STS 0x44 156 #define BGE_PCI_PWRMGMT_CAPID 0x48 157 #define BGE_PCI_NEXTPTR_VPD 0x49 158 #define BGE_PCI_PWRMGMT_CAPS 0x4A 159 #define BGE_PCI_PWRMGMT_CMD 0x4C 160 #define BGE_PCI_PWRMGMT_STS 0x4D 161 #define BGE_PCI_PWRMGMT_DATA 0x4F 162 #define BGE_PCI_VPD_CAPID 0x50 163 #define BGE_PCI_NEXTPTR_MSI 0x51 164 #define BGE_PCI_VPD_ADDR 0x52 165 #define BGE_PCI_VPD_DATA 0x54 166 #define BGE_PCI_MSI_CAPID 0x58 167 #define BGE_PCI_NEXTPTR_NONE 0x59 168 #define BGE_PCI_MSI_CTL 0x5A 169 #define BGE_PCI_MSI_ADDR_HI 0x5C 170 #define BGE_PCI_MSI_ADDR_LO 0x60 171 #define BGE_PCI_MSI_DATA 0x64 172 173 /* 174 * PCI registers specific to the BCM570x family. 175 */ 176 #define BGE_PCI_MISC_CTL 0x68 177 #define BGE_PCI_DMA_RW_CTL 0x6C 178 #define BGE_PCI_PCISTATE 0x70 179 #define BGE_PCI_CLKCTL 0x74 180 #define BGE_PCI_REG_BASEADDR 0x78 181 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 182 #define BGE_PCI_REG_DATA 0x80 183 #define BGE_PCI_MEMWIN_DATA 0x84 184 #define BGE_PCI_MODECTL 0x88 185 #define BGE_PCI_MISC_CFG 0x8C 186 #define BGE_PCI_MISC_LOCALCTL 0x90 187 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 188 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 189 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 190 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 191 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 192 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 193 #define BGE_PCI_ISR_MBX_HI 0xB0 194 #define BGE_PCI_ISR_MBX_LO 0xB4 195 196 #define BGE_PCI_UNKNOWN0 0xC4 197 /* XXX: 198 * Used in PCI-Express code for 575x chips. 199 * Should be replaced with checking for a PCI config-space 200 * capability for PCI-Express, and PCI-Express standard 201 * offsets into that capability block. 202 */ 203 #define BGE_PCI_CONF_DEV_CTRL 0xD8 204 #define BGE_PCI_CONF_DEV_STUS 0xDA 205 206 207 /* PCI Misc. Host control register */ 208 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 209 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 210 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 211 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 212 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 213 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 214 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 215 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 216 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 217 218 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 219 #if BYTE_ORDER == LITTLE_ENDIAN 220 #define BGE_DMA_SWAP_OPTIONS \ 221 BGE_MODECTL_WORDSWAP_NONFRAME| \ 222 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 223 #else 224 #define BGE_DMA_SWAP_OPTIONS \ 225 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 226 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 227 #endif 228 229 #define BGE_INIT \ 230 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 231 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 232 233 #define BGE_CHIPID_TIGON_I 0x40000000 234 #define BGE_CHIPID_TIGON_II 0x60000000 235 #define BGE_CHIPID_BCM5700_A0 0x70000000 236 #define BGE_CHIPID_BCM5700_A1 0x70010000 237 #define BGE_CHIPID_BCM5700_B0 0x71000000 238 #define BGE_CHIPID_BCM5700_B1 0x71010000 239 #define BGE_CHIPID_BCM5700_B2 0x71020000 240 #define BGE_CHIPID_BCM5700_B3 0x71030000 241 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 242 #define BGE_CHIPID_BCM5700_C0 0x72000000 243 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 244 #define BGE_CHIPID_BCM5701_B0 0x01000000 245 #define BGE_CHIPID_BCM5701_B2 0x01020000 246 #define BGE_CHIPID_BCM5701_B5 0x01050000 247 #define BGE_CHIPID_BCM5703_A0 0x10000000 248 #define BGE_CHIPID_BCM5703_A1 0x10010000 249 #define BGE_CHIPID_BCM5703_A2 0x10020000 250 #define BGE_CHIPID_BCM5703_A3 0x10030000 251 #define BGE_CHIPID_BCM5703_B0 0x11000000 252 #define BGE_CHIPID_BCM5704_A0 0x20000000 253 #define BGE_CHIPID_BCM5704_A1 0x20010000 254 #define BGE_CHIPID_BCM5704_A2 0x20020000 255 #define BGE_CHIPID_BCM5704_A3 0x20030000 256 #define BGE_CHIPID_BCM5704_B0 0x21000000 257 #define BGE_CHIPID_BCM5705_A0 0x30000000 258 #define BGE_CHIPID_BCM5705_A1 0x30010000 259 #define BGE_CHIPID_BCM5705_A2 0x30020000 260 #define BGE_CHIPID_BCM5705_A3 0x30030000 261 #define BGE_CHIPID_BCM5750_A0 0x40000000 262 #define BGE_CHIPID_BCM5750_A1 0x40010000 263 #define BGE_CHIPID_BCM5750_A3 0x40030000 264 #define BGE_CHIPID_BCM5750_B0 0x40100000 265 #define BGE_CHIPID_BCM5751_A1 0x41010000 266 #define BGE_CHIPID_BCM5750_C0 0x42000000 267 #define BGE_CHIPID_BCM5750_C1 0x42010000 268 #define BGE_CHIPID_BCM5750_C2 0x42020000 269 #define BGE_CHIPID_BCM5714_A0 0x50000000 270 #define BGE_CHIPID_BCM5752_A0 0x60000000 271 #define BGE_CHIPID_BCM5752_A1 0x60010000 272 #define BGE_CHIPID_BCM5752_A2 0x60020000 273 #define BGE_CHIPID_BCM5714_B0 0x80000000 274 #define BGE_CHIPID_BCM5714_B3 0x80030000 275 #define BGE_CHIPID_BCM5715_A0 0x90000000 276 #define BGE_CHIPID_BCM5715_A1 0x90010000 277 #define BGE_CHIPID_BCM5715_A3 0x90030000 278 #define BGE_CHIPID_BCM5755_A0 0xa0000000 279 #define BGE_CHIPID_BCM5755_A1 0xa0010000 280 #define BGE_CHIPID_BCM5755_A2 0xa0020000 281 #define BGE_CHIPID_BCM5755_C0 0xa2000000 282 #define BGE_CHIPID_BCM5787_A0 0xb0000000 283 #define BGE_CHIPID_BCM5787_A1 0xb0010000 284 #define BGE_CHIPID_BCM5787_A2 0xb0020000 285 #define BGE_CHIPID_BCM5906_A1 0xc0010000 286 #define BGE_CHIPID_BCM5906_A2 0xc0020000 287 288 /* shorthand one */ 289 #define BGE_ASICREV(x) ((x) >> 28) 290 #define BGE_ASICREV_BCM5700 0x07 291 #define BGE_ASICREV_BCM5701 0x00 292 #define BGE_ASICREV_BCM5703 0x01 293 #define BGE_ASICREV_BCM5704 0x02 294 #define BGE_ASICREV_BCM5705 0x03 295 #define BGE_ASICREV_BCM5750 0x04 296 #define BGE_ASICREV_BCM5714_A0 0x05 297 #define BGE_ASICREV_BCM5752 0x06 298 /* ASIC revision 0x07 is the original bcm5700 */ 299 #define BGE_ASICREV_BCM5780 0x08 300 #define BGE_ASICREV_BCM5714 0x09 301 #define BGE_ASICREV_BCM5755 0x0a 302 #define BGE_ASICREV_BCM5787 0x0b 303 /* is this one mistyped ??? */ 304 #define BGE_ASICREV_BCM5706 0x0c 305 306 #define BGE_ASICREV_BCM5906 0x0c 307 308 /* chip revisions */ 309 #define BGE_CHIPREV(x) ((x) >> 24) 310 #define BGE_CHIPREV_5700_AX 0x70 311 #define BGE_CHIPREV_5700_BX 0x71 312 #define BGE_CHIPREV_5700_CX 0x72 313 #define BGE_CHIPREV_5701_AX 0x00 314 #define BGE_CHIPREV_5703_AX 0x10 315 #define BGE_CHIPREV_5704_AX 0x20 316 #define BGE_CHIPREV_5704_BX 0x21 317 #define BGE_CHIPREV_5750_AX 0x40 318 #define BGE_CHIPREV_5750_BX 0x41 319 320 /* PCI DMA Read/Write Control register */ 321 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 322 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 323 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 324 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 325 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 326 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 327 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 328 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 329 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 330 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 331 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 332 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 333 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 334 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 335 336 /* PCI DMA Read/Write Control register, alternate usage for PCI-Express */ 337 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128 0x00180000 338 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256 0x00380000 339 340 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 341 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 342 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 343 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 344 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 345 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 346 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 347 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 348 349 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 350 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 351 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 352 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 353 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 354 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 355 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 356 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 357 358 /* 359 * PCI state register -- note, this register is read only 360 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 361 * register is set. 362 */ 363 #define BGE_PCISTATE_FORCE_RESET 0x00000001 364 #define BGE_PCISTATE_INTR_STATE 0x00000002 365 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 366 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 367 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 368 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 369 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 370 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 371 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 372 373 /* 374 * The following bits in PCI state register are reserved. 375 * If we check that the register values reverts on reset, 376 * do not check these bits. On some 5704C (rev A3) and some 377 * Altima chips, these bits do not revert until much later 378 * in the bge driver's bge_reset() chip-reset state machine. 379 */ 380 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 381 382 /* 383 * PCI Clock Control register -- note, this register is read only 384 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 385 * register is set. 386 */ 387 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 388 #define BGE_PCICLOCKCTL_M66EN 0x00000080 389 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 390 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 391 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 392 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 393 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 394 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 395 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 396 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 397 398 399 #ifndef PCIM_CMD_MWIEN 400 #define PCIM_CMD_MWIEN 0x0010 401 #endif 402 403 /* 404 * High priority mailbox registers 405 * Each mailbox is 64-bits wide, though we only use the 406 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 407 * first. The NIC will load the mailbox after the lower 32 bit word 408 * has been updated. 409 */ 410 #define BGE_MBX_IRQ0_HI 0x0200 411 #define BGE_MBX_IRQ0_LO 0x0204 412 #define BGE_MBX_IRQ1_HI 0x0208 413 #define BGE_MBX_IRQ1_LO 0x020C 414 #define BGE_MBX_IRQ2_HI 0x0210 415 #define BGE_MBX_IRQ2_LO 0x0214 416 #define BGE_MBX_IRQ3_HI 0x0218 417 #define BGE_MBX_IRQ3_LO 0x021C 418 #define BGE_MBX_GEN0_HI 0x0220 419 #define BGE_MBX_GEN0_LO 0x0224 420 #define BGE_MBX_GEN1_HI 0x0228 421 #define BGE_MBX_GEN1_LO 0x022C 422 #define BGE_MBX_GEN2_HI 0x0230 423 #define BGE_MBX_GEN2_LO 0x0234 424 #define BGE_MBX_GEN3_HI 0x0228 425 #define BGE_MBX_GEN3_LO 0x022C 426 #define BGE_MBX_GEN4_HI 0x0240 427 #define BGE_MBX_GEN4_LO 0x0244 428 #define BGE_MBX_GEN5_HI 0x0248 429 #define BGE_MBX_GEN5_LO 0x024C 430 #define BGE_MBX_GEN6_HI 0x0250 431 #define BGE_MBX_GEN6_LO 0x0254 432 #define BGE_MBX_GEN7_HI 0x0258 433 #define BGE_MBX_GEN7_LO 0x025C 434 #define BGE_MBX_RELOAD_STATS_HI 0x0260 435 #define BGE_MBX_RELOAD_STATS_LO 0x0264 436 #define BGE_MBX_RX_STD_PROD_HI 0x0268 437 #define BGE_MBX_RX_STD_PROD_LO 0x026C 438 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 439 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 440 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 441 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 442 #define BGE_MBX_RX_CONS0_HI 0x0280 443 #define BGE_MBX_RX_CONS0_LO 0x0284 444 #define BGE_MBX_RX_CONS1_HI 0x0288 445 #define BGE_MBX_RX_CONS1_LO 0x028C 446 #define BGE_MBX_RX_CONS2_HI 0x0290 447 #define BGE_MBX_RX_CONS2_LO 0x0294 448 #define BGE_MBX_RX_CONS3_HI 0x0298 449 #define BGE_MBX_RX_CONS3_LO 0x029C 450 #define BGE_MBX_RX_CONS4_HI 0x02A0 451 #define BGE_MBX_RX_CONS4_LO 0x02A4 452 #define BGE_MBX_RX_CONS5_HI 0x02A8 453 #define BGE_MBX_RX_CONS5_LO 0x02AC 454 #define BGE_MBX_RX_CONS6_HI 0x02B0 455 #define BGE_MBX_RX_CONS6_LO 0x02B4 456 #define BGE_MBX_RX_CONS7_HI 0x02B8 457 #define BGE_MBX_RX_CONS7_LO 0x02BC 458 #define BGE_MBX_RX_CONS8_HI 0x02C0 459 #define BGE_MBX_RX_CONS8_LO 0x02C4 460 #define BGE_MBX_RX_CONS9_HI 0x02C8 461 #define BGE_MBX_RX_CONS9_LO 0x02CC 462 #define BGE_MBX_RX_CONS10_HI 0x02D0 463 #define BGE_MBX_RX_CONS10_LO 0x02D4 464 #define BGE_MBX_RX_CONS11_HI 0x02D8 465 #define BGE_MBX_RX_CONS11_LO 0x02DC 466 #define BGE_MBX_RX_CONS12_HI 0x02E0 467 #define BGE_MBX_RX_CONS12_LO 0x02E4 468 #define BGE_MBX_RX_CONS13_HI 0x02E8 469 #define BGE_MBX_RX_CONS13_LO 0x02EC 470 #define BGE_MBX_RX_CONS14_HI 0x02F0 471 #define BGE_MBX_RX_CONS14_LO 0x02F4 472 #define BGE_MBX_RX_CONS15_HI 0x02F8 473 #define BGE_MBX_RX_CONS15_LO 0x02FC 474 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 475 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 476 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 477 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 478 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 479 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 480 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 481 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 482 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 483 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 484 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 485 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 486 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 487 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 488 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 489 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 490 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 491 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 492 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 493 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 494 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 495 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 496 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 497 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 498 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 499 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 500 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 501 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 502 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 503 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 504 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 505 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 506 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 507 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 508 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 509 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 510 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 511 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 512 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 513 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 514 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 515 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 516 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 517 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 518 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 519 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 520 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 521 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 522 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 523 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 524 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 525 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 526 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 527 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 528 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 529 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 530 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 531 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 532 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 533 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 534 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 535 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 536 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 537 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 538 539 #define BGE_TX_RINGS_MAX 4 540 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 541 #define BGE_RX_RINGS_MAX 16 542 543 /* Ethernet MAC control registers */ 544 #define BGE_MAC_MODE 0x0400 545 #define BGE_MAC_STS 0x0404 546 #define BGE_MAC_EVT_ENB 0x0408 547 #define BGE_MAC_LED_CTL 0x040C 548 #define BGE_MAC_ADDR1_LO 0x0410 549 #define BGE_MAC_ADDR1_HI 0x0414 550 #define BGE_MAC_ADDR2_LO 0x0418 551 #define BGE_MAC_ADDR2_HI 0x041C 552 #define BGE_MAC_ADDR3_LO 0x0420 553 #define BGE_MAC_ADDR3_HI 0x0424 554 #define BGE_MAC_ADDR4_LO 0x0428 555 #define BGE_MAC_ADDR4_HI 0x042C 556 #define BGE_WOL_PATPTR 0x0430 557 #define BGE_WOL_PATCFG 0x0434 558 #define BGE_TX_RANDOM_BACKOFF 0x0438 559 #define BGE_RX_MTU 0x043C 560 #define BGE_GBIT_PCS_TEST 0x0440 561 #define BGE_TX_TBI_AUTONEG 0x0444 562 #define BGE_RX_TBI_AUTONEG 0x0448 563 #define BGE_MI_COMM 0x044C 564 #define BGE_MI_STS 0x0450 565 #define BGE_MI_MODE 0x0454 566 #define BGE_AUTOPOLL_STS 0x0458 567 #define BGE_TX_MODE 0x045C 568 #define BGE_TX_STS 0x0460 569 #define BGE_TX_LENGTHS 0x0464 570 #define BGE_RX_MODE 0x0468 571 #define BGE_RX_STS 0x046C 572 #define BGE_MAR0 0x0470 573 #define BGE_MAR1 0x0474 574 #define BGE_MAR2 0x0478 575 #define BGE_MAR3 0x047C 576 #define BGE_RX_BD_RULES_CTL0 0x0480 577 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 578 #define BGE_RX_BD_RULES_CTL1 0x0488 579 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 580 #define BGE_RX_BD_RULES_CTL2 0x0490 581 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 582 #define BGE_RX_BD_RULES_CTL3 0x0498 583 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 584 #define BGE_RX_BD_RULES_CTL4 0x04A0 585 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 586 #define BGE_RX_BD_RULES_CTL5 0x04A8 587 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 588 #define BGE_RX_BD_RULES_CTL6 0x04B0 589 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 590 #define BGE_RX_BD_RULES_CTL7 0x04B8 591 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 592 #define BGE_RX_BD_RULES_CTL8 0x04C0 593 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 594 #define BGE_RX_BD_RULES_CTL9 0x04C8 595 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 596 #define BGE_RX_BD_RULES_CTL10 0x04D0 597 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 598 #define BGE_RX_BD_RULES_CTL11 0x04D8 599 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 600 #define BGE_RX_BD_RULES_CTL12 0x04E0 601 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 602 #define BGE_RX_BD_RULES_CTL13 0x04E8 603 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 604 #define BGE_RX_BD_RULES_CTL14 0x04F0 605 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 606 #define BGE_RX_BD_RULES_CTL15 0x04F8 607 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 608 #define BGE_RX_RULES_CFG 0x0500 609 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 610 #define BGE_RX_STATS 0x0800 611 #define BGE_TX_STATS 0x0880 612 613 /* Ethernet MAC Mode register */ 614 #define BGE_MACMODE_RESET 0x00000001 615 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 616 #define BGE_MACMODE_PORTMODE 0x0000000C 617 #define BGE_MACMODE_LOOPBACK 0x00000010 618 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 619 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 620 #define BGE_MACMODE_MAX_DEFER 0x00000200 621 #define BGE_MACMODE_LINK_POLARITY 0x00000400 622 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 623 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 624 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 625 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 626 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 627 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 628 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 629 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 630 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 631 #define BGE_MACMODE_MIP_ENB 0x00100000 632 #define BGE_MACMODE_TXDMA_ENB 0x00200000 633 #define BGE_MACMODE_RXDMA_ENB 0x00400000 634 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 635 636 #define BGE_PORTMODE_NONE 0x00000000 637 #define BGE_PORTMODE_MII 0x00000004 638 #define BGE_PORTMODE_GMII 0x00000008 639 #define BGE_PORTMODE_TBI 0x0000000C 640 641 /* MAC Status register */ 642 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 643 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 644 #define BGE_MACSTAT_RX_CFG 0x00000004 645 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 646 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 647 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 648 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 649 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 650 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 651 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 652 #define BGE_MACSTAT_ODI_ERROR 0x02000000 653 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 654 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 655 656 /* MAC Event Enable Register */ 657 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 658 #define BGE_EVTENB_LINK_CHANGED 0x00001000 659 #define BGE_EVTENB_MI_COMPLETE 0x00400000 660 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 661 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 662 #define BGE_EVTENB_ODI_ERROR 0x02000000 663 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 664 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 665 666 /* LED Control Register */ 667 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 668 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 669 #define BGE_LEDCTL_100MBPS_LED 0x00000004 670 #define BGE_LEDCTL_10MBPS_LED 0x00000008 671 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 672 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 673 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 674 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 675 #define BGE_LEDCTL_100MBPS_STS 0x00000100 676 #define BGE_LEDCTL_10MBPS_STS 0x00000200 677 #define BGE_LEDCTL_TRADLED_STS 0x00000400 678 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 679 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 680 681 /* TX backoff seed register */ 682 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 683 684 /* Autopoll status register */ 685 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 686 687 /* Transmit MAC mode register */ 688 #define BGE_TXMODE_RESET 0x00000001 689 #define BGE_TXMODE_ENABLE 0x00000002 690 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 691 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 692 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 693 694 /* Transmit MAC status register */ 695 #define BGE_TXSTAT_RX_XOFFED 0x00000001 696 #define BGE_TXSTAT_SENT_XOFF 0x00000002 697 #define BGE_TXSTAT_SENT_XON 0x00000004 698 #define BGE_TXSTAT_LINK_UP 0x00000008 699 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 700 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 701 702 /* Transmit MAC lengths register */ 703 #define BGE_TXLEN_SLOTTIME 0x000000FF 704 #define BGE_TXLEN_IPG 0x00000F00 705 #define BGE_TXLEN_CRS 0x00003000 706 707 /* Receive MAC mode register */ 708 #define BGE_RXMODE_RESET 0x00000001 709 #define BGE_RXMODE_ENABLE 0x00000002 710 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 711 #define BGE_RXMODE_RX_GIANTS 0x00000020 712 #define BGE_RXMODE_RX_RUNTS 0x00000040 713 #define BGE_RXMODE_8022_LENCHECK 0x00000080 714 #define BGE_RXMODE_RX_PROMISC 0x00000100 715 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 716 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 717 718 /* Receive MAC status register */ 719 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 720 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 721 #define BGE_RXSTAT_RCVD_XON 0x00000004 722 723 /* Receive Rules Control register */ 724 #define BGE_RXRULECTL_OFFSET 0x000000FF 725 #define BGE_RXRULECTL_CLASS 0x00001F00 726 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 727 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 728 #define BGE_RXRULECTL_MAP 0x01000000 729 #define BGE_RXRULECTL_DISCARD 0x02000000 730 #define BGE_RXRULECTL_MASK 0x04000000 731 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 732 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 733 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 734 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 735 736 /* Receive Rules Mask register */ 737 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 738 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 739 740 /* MI communication register */ 741 #define BGE_MICOMM_DATA 0x0000FFFF 742 #define BGE_MICOMM_REG 0x001F0000 743 #define BGE_MICOMM_PHY 0x03E00000 744 #define BGE_MICOMM_CMD 0x0C000000 745 #define BGE_MICOMM_READFAIL 0x10000000 746 #define BGE_MICOMM_BUSY 0x20000000 747 748 #define BGE_MIREG(x) ((x & 0x1F) << 16) 749 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 750 #define BGE_MICMD_WRITE 0x04000000 751 #define BGE_MICMD_READ 0x08000000 752 753 /* MI status register */ 754 #define BGE_MISTS_LINK 0x00000001 755 #define BGE_MISTS_10MBPS 0x00000002 756 757 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 758 #define BGE_MIMODE_AUTOPOLL 0x00000010 759 #define BGE_MIMODE_CLKCNT 0x001F0000 760 761 762 /* 763 * Send data initiator control registers. 764 */ 765 #define BGE_SDI_MODE 0x0C00 766 #define BGE_SDI_STATUS 0x0C04 767 #define BGE_SDI_STATS_CTL 0x0C08 768 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 769 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 770 #define BGE_LOCSTATS_COS0 0x0C80 771 #define BGE_LOCSTATS_COS1 0x0C84 772 #define BGE_LOCSTATS_COS2 0x0C88 773 #define BGE_LOCSTATS_COS3 0x0C8C 774 #define BGE_LOCSTATS_COS4 0x0C90 775 #define BGE_LOCSTATS_COS5 0x0C84 776 #define BGE_LOCSTATS_COS6 0x0C98 777 #define BGE_LOCSTATS_COS7 0x0C9C 778 #define BGE_LOCSTATS_COS8 0x0CA0 779 #define BGE_LOCSTATS_COS9 0x0CA4 780 #define BGE_LOCSTATS_COS10 0x0CA8 781 #define BGE_LOCSTATS_COS11 0x0CAC 782 #define BGE_LOCSTATS_COS12 0x0CB0 783 #define BGE_LOCSTATS_COS13 0x0CB4 784 #define BGE_LOCSTATS_COS14 0x0CB8 785 #define BGE_LOCSTATS_COS15 0x0CBC 786 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 787 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 788 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 789 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 790 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 791 #define BGE_LOCSTATS_IRQS 0x0CD4 792 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 793 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 794 795 /* Send Data Initiator mode register */ 796 #define BGE_SDIMODE_RESET 0x00000001 797 #define BGE_SDIMODE_ENABLE 0x00000002 798 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 799 800 /* Send Data Initiator stats register */ 801 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 802 803 /* Send Data Initiator stats control register */ 804 #define BGE_SDISTATSCTL_ENABLE 0x00000001 805 #define BGE_SDISTATSCTL_FASTER 0x00000002 806 #define BGE_SDISTATSCTL_CLEAR 0x00000004 807 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 808 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 809 810 /* 811 * Send Data Completion Control registers 812 */ 813 #define BGE_SDC_MODE 0x1000 814 #define BGE_SDC_STATUS 0x1004 815 816 /* Send Data completion mode register */ 817 #define BGE_SDCMODE_RESET 0x00000001 818 #define BGE_SDCMODE_ENABLE 0x00000002 819 #define BGE_SDCMODE_ATTN 0x00000004 820 821 /* Send Data completion status register */ 822 #define BGE_SDCSTAT_ATTN 0x00000004 823 824 /* 825 * Send BD Ring Selector Control registers 826 */ 827 #define BGE_SRS_MODE 0x1400 828 #define BGE_SRS_STATUS 0x1404 829 #define BGE_SRS_HWDIAG 0x1408 830 #define BGE_SRS_LOC_NIC_CONS0 0x1440 831 #define BGE_SRS_LOC_NIC_CONS1 0x1444 832 #define BGE_SRS_LOC_NIC_CONS2 0x1448 833 #define BGE_SRS_LOC_NIC_CONS3 0x144C 834 #define BGE_SRS_LOC_NIC_CONS4 0x1450 835 #define BGE_SRS_LOC_NIC_CONS5 0x1454 836 #define BGE_SRS_LOC_NIC_CONS6 0x1458 837 #define BGE_SRS_LOC_NIC_CONS7 0x145C 838 #define BGE_SRS_LOC_NIC_CONS8 0x1460 839 #define BGE_SRS_LOC_NIC_CONS9 0x1464 840 #define BGE_SRS_LOC_NIC_CONS10 0x1468 841 #define BGE_SRS_LOC_NIC_CONS11 0x146C 842 #define BGE_SRS_LOC_NIC_CONS12 0x1470 843 #define BGE_SRS_LOC_NIC_CONS13 0x1474 844 #define BGE_SRS_LOC_NIC_CONS14 0x1478 845 #define BGE_SRS_LOC_NIC_CONS15 0x147C 846 847 /* Send BD Ring Selector Mode register */ 848 #define BGE_SRSMODE_RESET 0x00000001 849 #define BGE_SRSMODE_ENABLE 0x00000002 850 #define BGE_SRSMODE_ATTN 0x00000004 851 852 /* Send BD Ring Selector Status register */ 853 #define BGE_SRSSTAT_ERROR 0x00000004 854 855 /* Send BD Ring Selector HW Diagnostics register */ 856 #define BGE_SRSHWDIAG_STATE 0x0000000F 857 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 858 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 859 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 860 861 /* 862 * Send BD Initiator Selector Control registers 863 */ 864 #define BGE_SBDI_MODE 0x1800 865 #define BGE_SBDI_STATUS 0x1804 866 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 867 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 868 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 869 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 870 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 871 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 872 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 873 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 874 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 875 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 876 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 877 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 878 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 879 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 880 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 881 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 882 883 /* Send BD Initiator Mode register */ 884 #define BGE_SBDIMODE_RESET 0x00000001 885 #define BGE_SBDIMODE_ENABLE 0x00000002 886 #define BGE_SBDIMODE_ATTN 0x00000004 887 888 /* Send BD Initiator Status register */ 889 #define BGE_SBDISTAT_ERROR 0x00000004 890 891 /* 892 * Send BD Completion Control registers 893 */ 894 #define BGE_SBDC_MODE 0x1C00 895 #define BGE_SBDC_STATUS 0x1C04 896 897 /* Send BD Completion Control Mode register */ 898 #define BGE_SBDCMODE_RESET 0x00000001 899 #define BGE_SBDCMODE_ENABLE 0x00000002 900 #define BGE_SBDCMODE_ATTN 0x00000004 901 902 /* Send BD Completion Control Status register */ 903 #define BGE_SBDCSTAT_ATTN 0x00000004 904 905 /* 906 * Receive List Placement Control registers 907 */ 908 #define BGE_RXLP_MODE 0x2000 909 #define BGE_RXLP_STATUS 0x2004 910 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 911 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 912 #define BGE_RXLP_CFG 0x2010 913 #define BGE_RXLP_STATS_CTL 0x2014 914 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 915 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 916 #define BGE_RXLP_HEAD0 0x2100 917 #define BGE_RXLP_TAIL0 0x2104 918 #define BGE_RXLP_COUNT0 0x2108 919 #define BGE_RXLP_HEAD1 0x2110 920 #define BGE_RXLP_TAIL1 0x2114 921 #define BGE_RXLP_COUNT1 0x2118 922 #define BGE_RXLP_HEAD2 0x2120 923 #define BGE_RXLP_TAIL2 0x2124 924 #define BGE_RXLP_COUNT2 0x2128 925 #define BGE_RXLP_HEAD3 0x2130 926 #define BGE_RXLP_TAIL3 0x2134 927 #define BGE_RXLP_COUNT3 0x2138 928 #define BGE_RXLP_HEAD4 0x2140 929 #define BGE_RXLP_TAIL4 0x2144 930 #define BGE_RXLP_COUNT4 0x2148 931 #define BGE_RXLP_HEAD5 0x2150 932 #define BGE_RXLP_TAIL5 0x2154 933 #define BGE_RXLP_COUNT5 0x2158 934 #define BGE_RXLP_HEAD6 0x2160 935 #define BGE_RXLP_TAIL6 0x2164 936 #define BGE_RXLP_COUNT6 0x2168 937 #define BGE_RXLP_HEAD7 0x2170 938 #define BGE_RXLP_TAIL7 0x2174 939 #define BGE_RXLP_COUNT7 0x2178 940 #define BGE_RXLP_HEAD8 0x2180 941 #define BGE_RXLP_TAIL8 0x2184 942 #define BGE_RXLP_COUNT8 0x2188 943 #define BGE_RXLP_HEAD9 0x2190 944 #define BGE_RXLP_TAIL9 0x2194 945 #define BGE_RXLP_COUNT9 0x2198 946 #define BGE_RXLP_HEAD10 0x21A0 947 #define BGE_RXLP_TAIL10 0x21A4 948 #define BGE_RXLP_COUNT10 0x21A8 949 #define BGE_RXLP_HEAD11 0x21B0 950 #define BGE_RXLP_TAIL11 0x21B4 951 #define BGE_RXLP_COUNT11 0x21B8 952 #define BGE_RXLP_HEAD12 0x21C0 953 #define BGE_RXLP_TAIL12 0x21C4 954 #define BGE_RXLP_COUNT12 0x21C8 955 #define BGE_RXLP_HEAD13 0x21D0 956 #define BGE_RXLP_TAIL13 0x21D4 957 #define BGE_RXLP_COUNT13 0x21D8 958 #define BGE_RXLP_HEAD14 0x21E0 959 #define BGE_RXLP_TAIL14 0x21E4 960 #define BGE_RXLP_COUNT14 0x21E8 961 #define BGE_RXLP_HEAD15 0x21F0 962 #define BGE_RXLP_TAIL15 0x21F4 963 #define BGE_RXLP_COUNT15 0x21F8 964 #define BGE_RXLP_LOCSTAT_COS0 0x2200 965 #define BGE_RXLP_LOCSTAT_COS1 0x2204 966 #define BGE_RXLP_LOCSTAT_COS2 0x2208 967 #define BGE_RXLP_LOCSTAT_COS3 0x220C 968 #define BGE_RXLP_LOCSTAT_COS4 0x2210 969 #define BGE_RXLP_LOCSTAT_COS5 0x2214 970 #define BGE_RXLP_LOCSTAT_COS6 0x2218 971 #define BGE_RXLP_LOCSTAT_COS7 0x221C 972 #define BGE_RXLP_LOCSTAT_COS8 0x2220 973 #define BGE_RXLP_LOCSTAT_COS9 0x2224 974 #define BGE_RXLP_LOCSTAT_COS10 0x2228 975 #define BGE_RXLP_LOCSTAT_COS11 0x222C 976 #define BGE_RXLP_LOCSTAT_COS12 0x2230 977 #define BGE_RXLP_LOCSTAT_COS13 0x2234 978 #define BGE_RXLP_LOCSTAT_COS14 0x2238 979 #define BGE_RXLP_LOCSTAT_COS15 0x223C 980 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 981 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 982 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 983 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 984 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 985 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 986 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 987 988 989 /* Receive List Placement mode register */ 990 #define BGE_RXLPMODE_RESET 0x00000001 991 #define BGE_RXLPMODE_ENABLE 0x00000002 992 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 993 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 994 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 995 996 /* Receive List Placement Status register */ 997 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 998 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 999 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1000 1001 /* 1002 * Receive Data and Receive BD Initiator Control Registers 1003 */ 1004 #define BGE_RDBDI_MODE 0x2400 1005 #define BGE_RDBDI_STATUS 0x2404 1006 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1007 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1008 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1009 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1010 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1011 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1012 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1013 #define BGE_RX_STD_RCB_NICADDR 0x245C 1014 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1015 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1016 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1017 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1018 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1019 #define BGE_RDBDI_STD_RX_CONS 0x2474 1020 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1021 #define BGE_RDBDI_RETURN_PROD0 0x2480 1022 #define BGE_RDBDI_RETURN_PROD1 0x2484 1023 #define BGE_RDBDI_RETURN_PROD2 0x2488 1024 #define BGE_RDBDI_RETURN_PROD3 0x248C 1025 #define BGE_RDBDI_RETURN_PROD4 0x2490 1026 #define BGE_RDBDI_RETURN_PROD5 0x2494 1027 #define BGE_RDBDI_RETURN_PROD6 0x2498 1028 #define BGE_RDBDI_RETURN_PROD7 0x249C 1029 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1030 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1031 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1032 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1033 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1034 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1035 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1036 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1037 #define BGE_RDBDI_HWDIAG 0x24C0 1038 1039 1040 /* Receive Data and Receive BD Initiator Mode register */ 1041 #define BGE_RDBDIMODE_RESET 0x00000001 1042 #define BGE_RDBDIMODE_ENABLE 0x00000002 1043 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1044 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1045 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1046 1047 /* Receive Data and Receive BD Initiator Status register */ 1048 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1049 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1050 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1051 1052 1053 /* 1054 * Receive Data Completion Control registers 1055 */ 1056 #define BGE_RDC_MODE 0x2800 1057 1058 /* Receive Data Completion Mode register */ 1059 #define BGE_RDCMODE_RESET 0x00000001 1060 #define BGE_RDCMODE_ENABLE 0x00000002 1061 #define BGE_RDCMODE_ATTN 0x00000004 1062 1063 /* 1064 * Receive BD Initiator Control registers 1065 */ 1066 #define BGE_RBDI_MODE 0x2C00 1067 #define BGE_RBDI_STATUS 0x2C04 1068 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1069 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1070 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1071 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1072 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1073 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1074 1075 /* Receive BD Initiator Mode register */ 1076 #define BGE_RBDIMODE_RESET 0x00000001 1077 #define BGE_RBDIMODE_ENABLE 0x00000002 1078 #define BGE_RBDIMODE_ATTN 0x00000004 1079 1080 /* Receive BD Initiator Status register */ 1081 #define BGE_RBDISTAT_ATTN 0x00000004 1082 1083 /* 1084 * Receive BD Completion Control registers 1085 */ 1086 #define BGE_RBDC_MODE 0x3000 1087 #define BGE_RBDC_STATUS 0x3004 1088 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1089 #define BGE_RBDC_STD_BD_PROD 0x300C 1090 #define BGE_RBDC_MINI_BD_PROD 0x3010 1091 1092 /* Receive BD completion mode register */ 1093 #define BGE_RBDCMODE_RESET 0x00000001 1094 #define BGE_RBDCMODE_ENABLE 0x00000002 1095 #define BGE_RBDCMODE_ATTN 0x00000004 1096 1097 /* Receive BD completion status register */ 1098 #define BGE_RBDCSTAT_ERROR 0x00000004 1099 1100 /* 1101 * Receive List Selector Control registers 1102 */ 1103 #define BGE_RXLS_MODE 0x3400 1104 #define BGE_RXLS_STATUS 0x3404 1105 1106 /* Receive List Selector Mode register */ 1107 #define BGE_RXLSMODE_RESET 0x00000001 1108 #define BGE_RXLSMODE_ENABLE 0x00000002 1109 #define BGE_RXLSMODE_ATTN 0x00000004 1110 1111 /* Receive List Selector Status register */ 1112 #define BGE_RXLSSTAT_ERROR 0x00000004 1113 1114 /* 1115 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1116 */ 1117 #define BGE_MBCF_MODE 0x3800 1118 #define BGE_MBCF_STATUS 0x3804 1119 1120 /* Mbuf Cluster Free mode register */ 1121 #define BGE_MBCFMODE_RESET 0x00000001 1122 #define BGE_MBCFMODE_ENABLE 0x00000002 1123 #define BGE_MBCFMODE_ATTN 0x00000004 1124 1125 /* Mbuf Cluster Free status register */ 1126 #define BGE_MBCFSTAT_ERROR 0x00000004 1127 1128 /* 1129 * Host Coalescing Control registers 1130 */ 1131 #define BGE_HCC_MODE 0x3C00 1132 #define BGE_HCC_STATUS 0x3C04 1133 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1134 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1135 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1136 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1137 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1138 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1139 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1140 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1141 #define BGE_HCC_STATS_TICKS 0x3C28 1142 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1143 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1144 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1145 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1146 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1147 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1148 #define BGE_FLOW_ATTN 0x3C48 1149 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1150 #define BGE_HCC_STD_BD_CONS 0x3C54 1151 #define BGE_HCC_MINI_BD_CONS 0x3C58 1152 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1153 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1154 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1155 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1156 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1157 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1158 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1159 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1160 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1161 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1162 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1163 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1164 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1165 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1166 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1167 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1168 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1169 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1170 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1171 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1172 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1173 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1174 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1175 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1176 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1177 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1178 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1179 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1180 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1181 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1182 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1183 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1184 1185 1186 /* Host coalescing mode register */ 1187 #define BGE_HCCMODE_RESET 0x00000001 1188 #define BGE_HCCMODE_ENABLE 0x00000002 1189 #define BGE_HCCMODE_ATTN 0x00000004 1190 #define BGE_HCCMODE_COAL_NOW 0x00000008 1191 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1192 #define BGE_HCCMODE_64BYTE 0x00000080 1193 #define BGE_HCCMODE_32BYTE 0x00000100 1194 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1195 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1196 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1197 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1198 1199 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1200 1201 #define BGE_STATBLKSZ_FULL 0x00000000 1202 #define BGE_STATBLKSZ_64BYTE 0x00000080 1203 #define BGE_STATBLKSZ_32BYTE 0x00000100 1204 1205 /* Host coalescing status register */ 1206 #define BGE_HCCSTAT_ERROR 0x00000004 1207 1208 /* Flow attention register */ 1209 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1210 #define BGE_FLOWATTN_MEMARB 0x00000080 1211 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1212 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1213 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1214 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1215 #define BGE_FLOWATTN_RDBDI 0x00080000 1216 #define BGE_FLOWATTN_RXLS 0x00100000 1217 #define BGE_FLOWATTN_RXLP 0x00200000 1218 #define BGE_FLOWATTN_RBDC 0x00400000 1219 #define BGE_FLOWATTN_RBDI 0x00800000 1220 #define BGE_FLOWATTN_SDC 0x08000000 1221 #define BGE_FLOWATTN_SDI 0x10000000 1222 #define BGE_FLOWATTN_SRS 0x20000000 1223 #define BGE_FLOWATTN_SBDC 0x40000000 1224 #define BGE_FLOWATTN_SBDI 0x80000000 1225 1226 /* 1227 * Memory arbiter registers 1228 */ 1229 #define BGE_MARB_MODE 0x4000 1230 #define BGE_MARB_STATUS 0x4004 1231 #define BGE_MARB_TRAPADDR_HI 0x4008 1232 #define BGE_MARB_TRAPADDR_LO 0x400C 1233 1234 /* Memory arbiter mode register */ 1235 #define BGE_MARBMODE_RESET 0x00000001 1236 #define BGE_MARBMODE_ENABLE 0x00000002 1237 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1238 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1239 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1240 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1241 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1242 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1243 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1244 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1245 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1246 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1247 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1248 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1249 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1250 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1251 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1252 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1253 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1254 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1255 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1256 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1257 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1258 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1259 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1260 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1261 1262 /* Memory arbiter status register */ 1263 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1264 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1265 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1266 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1267 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1268 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1269 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1270 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1271 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1272 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1273 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1274 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1275 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1276 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1277 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1278 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1279 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1280 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1281 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1282 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1283 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1284 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1285 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1286 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1287 1288 /* 1289 * Buffer manager control registers 1290 */ 1291 #define BGE_BMAN_MODE 0x4400 1292 #define BGE_BMAN_STATUS 0x4404 1293 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1294 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1295 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1296 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1297 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1298 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1299 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1300 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1301 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1302 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1303 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1304 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1305 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1306 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1307 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1308 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1309 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1310 #define BGE_BMAN_HWDIAG_1 0x444C 1311 #define BGE_BMAN_HWDIAG_2 0x4450 1312 #define BGE_BMAN_HWDIAG_3 0x4454 1313 1314 /* Buffer manager mode register */ 1315 #define BGE_BMANMODE_RESET 0x00000001 1316 #define BGE_BMANMODE_ENABLE 0x00000002 1317 #define BGE_BMANMODE_ATTN 0x00000004 1318 #define BGE_BMANMODE_TESTMODE 0x00000008 1319 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1320 1321 /* Buffer manager status register */ 1322 #define BGE_BMANSTAT_ERRO 0x00000004 1323 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1324 1325 1326 /* 1327 * Read DMA Control registers 1328 */ 1329 #define BGE_RDMA_MODE 0x4800 1330 #define BGE_RDMA_STATUS 0x4804 1331 1332 /* Read DMA mode register */ 1333 #define BGE_RDMAMODE_RESET 0x00000001 1334 #define BGE_RDMAMODE_ENABLE 0x00000002 1335 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1336 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1337 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1338 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1339 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1340 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1341 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1342 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1343 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1344 1345 /* Alternate encodings for PCI-Express, from Broadcom-supplied Linux driver */ 1346 #define BGE_RDMA_MODE_FIFO_LONG_BURST ((1<<17) || (1 << 16)) 1347 #define BGE_RDMA_MODE_FIFO_SIZE_128 (1 << 17) 1348 1349 /* Read DMA status register */ 1350 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1351 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1352 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1353 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1354 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1355 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1356 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1357 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1358 1359 /* 1360 * Write DMA control registers 1361 */ 1362 #define BGE_WDMA_MODE 0x4C00 1363 #define BGE_WDMA_STATUS 0x4C04 1364 1365 /* Write DMA mode register */ 1366 #define BGE_WDMAMODE_RESET 0x00000001 1367 #define BGE_WDMAMODE_ENABLE 0x00000002 1368 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1369 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1370 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1371 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1372 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1373 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1374 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1375 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1376 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1377 1378 /* Write DMA status register */ 1379 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1380 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1381 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1382 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1383 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1384 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1385 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1386 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1387 1388 1389 /* 1390 * RX CPU registers 1391 */ 1392 #define BGE_RXCPU_MODE 0x5000 1393 #define BGE_RXCPU_STATUS 0x5004 1394 #define BGE_RXCPU_PC 0x501C 1395 1396 /* RX CPU mode register */ 1397 #define BGE_RXCPUMODE_RESET 0x00000001 1398 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1399 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1400 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1401 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1402 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1403 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1404 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1405 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1406 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1407 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1408 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1409 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1410 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1411 1412 /* RX CPU status register */ 1413 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1414 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1415 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1416 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1417 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1418 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1419 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1420 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1421 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1422 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1423 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1424 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1425 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1426 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1427 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1428 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1429 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1430 1431 /* 1432 * V? CPU registers 1433 */ 1434 #define BGE_VCPU_STATUS 0x5100 1435 #define BGE_VCPU_EXT_CTRL 0x6890 1436 1437 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1438 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1439 1440 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1441 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1442 1443 /* 1444 * TX CPU registers 1445 */ 1446 #define BGE_TXCPU_MODE 0x5400 1447 #define BGE_TXCPU_STATUS 0x5404 1448 #define BGE_TXCPU_PC 0x541C 1449 1450 /* TX CPU mode register */ 1451 #define BGE_TXCPUMODE_RESET 0x00000001 1452 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1453 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1454 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1455 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1456 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1457 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1458 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1459 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1460 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1461 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1462 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1463 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1464 1465 /* TX CPU status register */ 1466 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1467 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1468 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1469 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1470 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1471 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1472 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1473 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1474 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1475 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1476 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1477 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1478 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1479 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1480 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1481 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1482 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1483 1484 1485 /* 1486 * Low priority mailbox registers 1487 */ 1488 #define BGE_LPMBX_IRQ0_HI 0x5800 1489 #define BGE_LPMBX_IRQ0_LO 0x5804 1490 #define BGE_LPMBX_IRQ1_HI 0x5808 1491 #define BGE_LPMBX_IRQ1_LO 0x580C 1492 #define BGE_LPMBX_IRQ2_HI 0x5810 1493 #define BGE_LPMBX_IRQ2_LO 0x5814 1494 #define BGE_LPMBX_IRQ3_HI 0x5818 1495 #define BGE_LPMBX_IRQ3_LO 0x581C 1496 #define BGE_LPMBX_GEN0_HI 0x5820 1497 #define BGE_LPMBX_GEN0_LO 0x5824 1498 #define BGE_LPMBX_GEN1_HI 0x5828 1499 #define BGE_LPMBX_GEN1_LO 0x582C 1500 #define BGE_LPMBX_GEN2_HI 0x5830 1501 #define BGE_LPMBX_GEN2_LO 0x5834 1502 #define BGE_LPMBX_GEN3_HI 0x5828 1503 #define BGE_LPMBX_GEN3_LO 0x582C 1504 #define BGE_LPMBX_GEN4_HI 0x5840 1505 #define BGE_LPMBX_GEN4_LO 0x5844 1506 #define BGE_LPMBX_GEN5_HI 0x5848 1507 #define BGE_LPMBX_GEN5_LO 0x584C 1508 #define BGE_LPMBX_GEN6_HI 0x5850 1509 #define BGE_LPMBX_GEN6_LO 0x5854 1510 #define BGE_LPMBX_GEN7_HI 0x5858 1511 #define BGE_LPMBX_GEN7_LO 0x585C 1512 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1513 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1514 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1515 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1516 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1517 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1518 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1519 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1520 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1521 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1522 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1523 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1524 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1525 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1526 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1527 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1528 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1529 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1530 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1531 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1532 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1533 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1534 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1535 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1536 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1537 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1538 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1539 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1540 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1541 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1542 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1543 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1544 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1545 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1546 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1547 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1548 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1549 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1550 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1551 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1552 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1553 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1554 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1555 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1556 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1557 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1558 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1559 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1560 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1561 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1562 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1563 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1564 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1565 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1566 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1567 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1568 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1569 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1570 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1571 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1572 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1573 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1574 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1575 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1576 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1577 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1578 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1579 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1580 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1581 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1582 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1583 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1584 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1585 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1586 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1587 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1588 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1589 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1590 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1591 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1592 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1593 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1594 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1595 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1596 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1597 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1598 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1599 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1600 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1601 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1602 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1603 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1604 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1605 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1606 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1607 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1608 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1609 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1610 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1611 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1612 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1613 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1614 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1615 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1616 1617 /* 1618 * Flow throw Queue reset register 1619 */ 1620 #define BGE_FTQ_RESET 0x5C00 1621 1622 #define BGE_FTQRESET_DMAREAD 0x00000002 1623 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1624 #define BGE_FTQRESET_DMADONE 0x00000010 1625 #define BGE_FTQRESET_SBDC 0x00000020 1626 #define BGE_FTQRESET_SDI 0x00000040 1627 #define BGE_FTQRESET_WDMA 0x00000080 1628 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1629 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1630 #define BGE_FTQRESET_SDC 0x00000400 1631 #define BGE_FTQRESET_HCC 0x00000800 1632 #define BGE_FTQRESET_TXFIFO 0x00001000 1633 #define BGE_FTQRESET_MBC 0x00002000 1634 #define BGE_FTQRESET_RBDC 0x00004000 1635 #define BGE_FTQRESET_RXLP 0x00008000 1636 #define BGE_FTQRESET_RDBDI 0x00010000 1637 #define BGE_FTQRESET_RDC 0x00020000 1638 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1639 1640 /* 1641 * Message Signaled Interrupt registers 1642 */ 1643 #define BGE_MSI_MODE 0x6000 1644 #define BGE_MSI_STATUS 0x6004 1645 #define BGE_MSI_FIFOACCESS 0x6008 1646 1647 /* MSI mode register */ 1648 #define BGE_MSIMODE_RESET 0x00000001 1649 #define BGE_MSIMODE_ENABLE 0x00000002 1650 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1651 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1652 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1653 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1654 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1655 1656 /* MSI status register */ 1657 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1658 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1659 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1660 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1661 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1662 1663 1664 /* 1665 * DMA Completion registers 1666 */ 1667 #define BGE_DMAC_MODE 0x6400 1668 1669 /* DMA Completion mode register */ 1670 #define BGE_DMACMODE_RESET 0x00000001 1671 #define BGE_DMACMODE_ENABLE 0x00000002 1672 1673 1674 /* 1675 * General control registers. 1676 */ 1677 #define BGE_MODE_CTL 0x6800 1678 #define BGE_MISC_CFG 0x6804 1679 #define BGE_MISC_LOCAL_CTL 0x6808 1680 #define BGE_MISC_TIMER 0x680c 1681 #define BGE_EE_ADDR 0x6838 1682 #define BGE_EE_DATA 0x683C 1683 #define BGE_EE_CTL 0x6840 1684 #define BGE_MDI_CTL 0x6844 1685 #define BGE_EE_DELAY 0x6848 1686 #define BGE_FASTBOOT_PC 0x6894 1687 /* 1688 * XXX: Those names are made up as I have no documentation about it; 1689 * I only know it is only used in the PCI-Express case. 1690 */ 1691 #define BGE_PCIE_CTL0 0x7c00 1692 #define BGE_PCIE_CTL1 0x7e2c 1693 1694 /* 1695 * NVRAM Control registers 1696 */ 1697 #define BGE_NVRAM_CMD 0x7000 1698 #define BGE_NVRAM_STAT 0x7004 1699 #define BGE_NVRAM_WRDATA 0x7008 1700 #define BGE_NVRAM_ADDR 0x700c 1701 #define BGE_NVRAM_RDDATA 0x7010 1702 #define BGE_NVRAM_CFG1 0x7014 1703 #define BGE_NVRAM_CFG2 0x7018 1704 #define BGE_NVRAM_CFG3 0x701c 1705 #define BGE_NVRAM_SWARB 0x7020 1706 #define BGE_NVRAM_ACCESS 0x7024 1707 #define BGE_NVRAM_WRITE1 0x7028 1708 1709 #define BGE_NVRAMCMD_RESET 0x00000001 1710 #define BGE_NVRAMCMD_DONE 0x00000008 1711 #define BGE_NVRAMCMD_START 0x00000010 1712 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1713 #define BGE_NVRAMCMD_ERASE 0x00000040 1714 #define BGE_NVRAMCMD_FIRST 0x00000080 1715 #define BGE_NVRAMCMD_LAST 0x00000100 1716 1717 #define BGE_NVRAM_READCMD \ 1718 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1719 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1720 #define BGE_NVRAM_WRITECMD \ 1721 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1722 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1723 1724 #define BGE_NVRAMSWARB_SET0 0x00000001 1725 #define BGE_NVRAMSWARB_SET1 0x00000002 1726 #define BGE_NVRAMSWARB_SET2 0x00000003 1727 #define BGE_NVRAMSWARB_SET3 0x00000004 1728 #define BGE_NVRAMSWARB_CLR0 0x00000010 1729 #define BGE_NVRAMSWARB_CLR1 0x00000020 1730 #define BGE_NVRAMSWARB_CLR2 0x00000040 1731 #define BGE_NVRAMSWARB_CLR3 0x00000080 1732 #define BGE_NVRAMSWARB_GNT0 0x00000100 1733 #define BGE_NVRAMSWARB_GNT1 0x00000200 1734 #define BGE_NVRAMSWARB_GNT2 0x00000400 1735 #define BGE_NVRAMSWARB_GNT3 0x00000800 1736 #define BGE_NVRAMSWARB_REQ0 0x00001000 1737 #define BGE_NVRAMSWARB_REQ1 0x00002000 1738 #define BGE_NVRAMSWARB_REQ2 0x00004000 1739 #define BGE_NVRAMSWARB_REQ3 0x00008000 1740 1741 #define BGE_NVRAMACC_ENABLE 0x00000001 1742 #define BGE_NVRAMACC_WRENABLE 0x00000002 1743 1744 /* 1745 * TLP Control Register 1746 * Applicable to BCM5721 and BCM5751 only 1747 */ 1748 #define BGE_TLP_CONTROL_REG 0x7c00 1749 #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1750 1751 /* 1752 * PHY Test Control Register 1753 * Applicable to BCM5721 and BCM5751 only 1754 */ 1755 #define BGE_PHY_TEST_CTRL_REG 0x7e2c 1756 #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1757 #define BGE_PHY_PCIE_LTASS_MODE 0x0040 1758 1759 1760 1761 /* Mode control register */ 1762 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1763 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1764 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1765 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1766 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1767 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1768 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1769 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1770 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1771 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1772 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1773 #define BGE_MODECTL_STACKUP 0x00010000 1774 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1775 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1776 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1777 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1778 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1779 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1780 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1781 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1782 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1783 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1784 1785 /* Misc. config register */ 1786 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1787 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1788 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1789 1790 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1791 1792 /* Misc. Local Control */ 1793 #define BGE_MLC_INTR_STATE 0x00000001 1794 #define BGE_MLC_INTR_CLR 0x00000002 1795 #define BGE_MLC_INTR_SET 0x00000004 1796 #define BGE_MLC_INTR_ONATTN 0x00000008 1797 #define BGE_MLC_MISCIO_IN0 0x00000100 1798 #define BGE_MLC_MISCIO_IN1 0x00000200 1799 #define BGE_MLC_MISCIO_IN2 0x00000400 1800 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1801 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1802 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1803 #define BGE_MLC_MISCIO_OUT0 0x00004000 1804 #define BGE_MLC_MISCIO_OUT1 0x00008000 1805 #define BGE_MLC_MISCIO_OUT2 0x00010000 1806 #define BGE_MLC_EXTRAM_ENB 0x00020000 1807 #define BGE_MLC_SRAM_SIZE 0x001C0000 1808 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1809 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1810 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1811 #define BGE_MLC_AUTO_EEPROM 0x01000000 1812 1813 #define BGE_SSRAMSIZE_256KB 0x00000000 1814 #define BGE_SSRAMSIZE_512KB 0x00040000 1815 #define BGE_SSRAMSIZE_1MB 0x00080000 1816 #define BGE_SSRAMSIZE_2MB 0x000C0000 1817 #define BGE_SSRAMSIZE_4MB 0x00100000 1818 #define BGE_SSRAMSIZE_8MB 0x00140000 1819 #define BGE_SSRAMSIZE_16M 0x00180000 1820 1821 /* EEPROM address register */ 1822 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1823 #define BGE_EEADDR_HALFCLK 0x01FF0000 1824 #define BGE_EEADDR_START 0x02000000 1825 #define BGE_EEADDR_DEVID 0x1C000000 1826 #define BGE_EEADDR_RESET 0x20000000 1827 #define BGE_EEADDR_DONE 0x40000000 1828 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1829 1830 #define BGE_EEDEVID(x) ((x & 7) << 26) 1831 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1832 #define BGE_HALFCLK_384SCL 0x60 1833 #define BGE_EE_READCMD \ 1834 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1835 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1836 #define BGE_EE_WRCMD \ 1837 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1838 BGE_EEADDR_START|BGE_EEADDR_DONE) 1839 1840 /* EEPROM Control register */ 1841 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1842 #define BGE_EECTL_CLKOUT 0x00000002 1843 #define BGE_EECTL_CLKIN 0x00000004 1844 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1845 #define BGE_EECTL_DATAOUT 0x00000010 1846 #define BGE_EECTL_DATAIN 0x00000020 1847 1848 /* MDI (MII/GMII) access register */ 1849 #define BGE_MDI_DATA 0x00000001 1850 #define BGE_MDI_DIR 0x00000002 1851 #define BGE_MDI_SEL 0x00000004 1852 #define BGE_MDI_CLK 0x00000008 1853 1854 #define BGE_MEMWIN_START 0x00008000 1855 #define BGE_MEMWIN_END 0x0000FFFF 1856 1857 1858 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1859 do { \ 1860 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1861 (0xFFFF0000 & x)); \ 1862 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1863 } while(0) 1864 1865 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1866 do { \ 1867 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1868 (0xFFFF0000 & x)); \ 1869 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1870 } while(0) 1871 1872 /* 1873 * This magic number is used to prevent PXE restart when we 1874 * issue a software reset. We write this magic number to the 1875 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1876 * code from running. 1877 */ 1878 #define BGE_MAGIC_NUMBER 0x4B657654 1879 1880 typedef struct { 1881 volatile u_int32_t bge_addr_hi; 1882 volatile u_int32_t bge_addr_lo; 1883 } bge_hostaddr; 1884 1885 static __inline void 1886 bge_set_hostaddr(volatile bge_hostaddr *x, bus_addr_t y) 1887 { 1888 x->bge_addr_lo = y & 0xffffffff; 1889 if (sizeof (bus_addr_t) == 8) 1890 x->bge_addr_hi = (u_int64_t)y >> 32; 1891 else 1892 x->bge_addr_hi = 0; 1893 } 1894 1895 /* Ring control block structure */ 1896 struct bge_rcb { 1897 bge_hostaddr bge_hostaddr; 1898 volatile u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 1899 volatile u_int32_t bge_nicaddr; 1900 }; 1901 1902 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1903 1904 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1905 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1906 rcb + offsetof(struct bge_rcb, offset), val) 1907 1908 1909 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1910 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1911 1912 struct bge_tx_bd { 1913 bge_hostaddr bge_addr; 1914 #if BYTE_ORDER == BIG_ENDIAN 1915 volatile u_int16_t bge_len; 1916 volatile u_int16_t bge_flags; 1917 volatile u_int16_t bge_rsvd; 1918 volatile u_int16_t bge_vlan_tag; 1919 #else 1920 volatile u_int16_t bge_flags; 1921 volatile u_int16_t bge_len; 1922 volatile u_int16_t bge_vlan_tag; 1923 volatile u_int16_t bge_rsvd; 1924 #endif 1925 }; 1926 1927 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1928 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1929 #define BGE_TXBDFLAG_END 0x0004 1930 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1931 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1932 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1933 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1934 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1935 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1936 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1937 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1938 #define BGE_TXBDFLAG_NO_CRC 0x8000 1939 1940 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1941 BGE_SEND_RING_1_TO_4 + \ 1942 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1943 1944 struct bge_rx_bd { 1945 bge_hostaddr bge_addr; 1946 #if BYTE_ORDER == BIG_ENDIAN 1947 volatile u_int16_t bge_idx; 1948 volatile u_int16_t bge_len; 1949 volatile u_int16_t bge_type; 1950 volatile u_int16_t bge_flags; 1951 volatile u_int16_t bge_ip_csum; 1952 volatile u_int16_t bge_tcp_udp_csum; 1953 volatile u_int16_t bge_error_flag; 1954 volatile u_int16_t bge_vlan_tag; 1955 #else 1956 volatile u_int16_t bge_len; 1957 volatile u_int16_t bge_idx; 1958 volatile u_int16_t bge_flags; 1959 volatile u_int16_t bge_type; 1960 volatile u_int16_t bge_tcp_udp_csum; 1961 volatile u_int16_t bge_ip_csum; 1962 volatile u_int16_t bge_vlan_tag; 1963 volatile u_int16_t bge_error_flag; 1964 #endif 1965 volatile u_int32_t bge_rsvd; 1966 volatile u_int32_t bge_opaque; 1967 }; 1968 1969 #define BGE_RXBDFLAG_END 0x0004 1970 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1971 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1972 #define BGE_RXBDFLAG_ERROR 0x0400 1973 #define BGE_RXBDFLAG_MINI_RING 0x0800 1974 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1975 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1976 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1977 1978 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1979 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1980 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1981 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1982 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1983 #define BGE_RXERRFLAG_RUNT 0x0020 1984 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1985 #define BGE_RXERRFLAG_GIANT 0x0080 1986 1987 struct bge_sts_idx { 1988 #if BYTE_ORDER == BIG_ENDIAN 1989 volatile u_int16_t bge_tx_cons_idx; 1990 volatile u_int16_t bge_rx_prod_idx; 1991 #else 1992 volatile u_int16_t bge_rx_prod_idx; 1993 volatile u_int16_t bge_tx_cons_idx; 1994 #endif 1995 }; 1996 1997 struct bge_status_block { 1998 volatile u_int32_t bge_status; 1999 volatile u_int32_t bge_rsvd0; 2000 #if BYTE_ORDER == BIG_ENDIAN 2001 volatile u_int16_t bge_rx_std_cons_idx; 2002 volatile u_int16_t bge_rx_jumbo_cons_idx; 2003 volatile u_int16_t bge_rsvd1; 2004 volatile u_int16_t bge_rx_mini_cons_idx; 2005 #else 2006 volatile u_int16_t bge_rx_jumbo_cons_idx; 2007 volatile u_int16_t bge_rx_std_cons_idx; 2008 volatile u_int16_t bge_rx_mini_cons_idx; 2009 volatile u_int16_t bge_rsvd1; 2010 #endif 2011 struct bge_sts_idx bge_idx[16]; 2012 }; 2013 2014 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2015 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2016 2017 #define BGE_STATFLAG_UPDATED 0x00000001 2018 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2019 #define BGE_STATFLAG_ERROR 0x00000004 2020 2021 2022 /* 2023 * Broadcom Vendor ID 2024 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2025 * even though they're now manufactured by Broadcom) 2026 */ 2027 #define BCOM_VENDORID 0x14E4 2028 #define BCOM_DEVICEID_BCM5700 0x1644 2029 #define BCOM_DEVICEID_BCM5701 0x1645 2030 #define BCOM_DEVICEID_BCM5789 0x169d 2031 2032 /* 2033 * Alteon AceNIC PCI vendor/device ID. 2034 */ 2035 #define ALT_VENDORID 0x12AE 2036 #define ALT_DEVICEID_ACENIC 0x0001 2037 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 2038 #define ALT_DEVICEID_BCM5700 0x0003 2039 #define ALT_DEVICEID_BCM5701 0x0004 2040 2041 /* 2042 * 3Com 3c985 PCI vendor/device ID. 2043 */ 2044 #define TC_VENDORID 0x10B7 2045 #define TC_DEVICEID_3C985 0x0001 2046 #define TC_DEVICEID_3C996 0x0003 2047 2048 /* 2049 * SysKonnect PCI vendor ID 2050 */ 2051 #define SK_VENDORID 0x1148 2052 #define SK_DEVICEID_ALTIMA 0x4400 2053 #define SK_SUBSYSID_9D21 0x4421 2054 #define SK_SUBSYSID_9D41 0x4441 2055 2056 /* 2057 * Altima PCI vendor/device ID. 2058 */ 2059 #define ALTIMA_VENDORID 0x173b 2060 #define ALTIMA_DEVICE_AC1000 0x03e8 2061 2062 /* 2063 * Offset of MAC address inside EEPROM. 2064 */ 2065 #define BGE_EE_MAC_OFFSET 0x7C 2066 #define BGE_EE_MAC_OFFSET_5906 0x10 2067 #define BGE_EE_HWCFG_OFFSET 0xC8 2068 2069 #define BGE_HWCFG_VOLTAGE 0x00000003 2070 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2071 #define BGE_HWCFG_MEDIA 0x00000030 2072 2073 #define BGE_VOLTAGE_1POINT3 0x00000000 2074 #define BGE_VOLTAGE_1POINT8 0x00000001 2075 2076 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2077 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2078 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2079 2080 #define BGE_MEDIA_UNSPEC 0x00000000 2081 #define BGE_MEDIA_COPPER 0x00000010 2082 #define BGE_MEDIA_FIBER 0x00000020 2083 2084 #define BGE_PCI_READ_CMD 0x06000000 2085 #define BGE_PCI_WRITE_CMD 0x70000000 2086 2087 #define BGE_TICKS_PER_SEC 1000000 2088 2089 /* 2090 * Ring size constants. 2091 */ 2092 #define BGE_EVENT_RING_CNT 256 2093 #define BGE_CMD_RING_CNT 64 2094 #define BGE_STD_RX_RING_CNT 512 2095 #define BGE_JUMBO_RX_RING_CNT 256 2096 #define BGE_MINI_RX_RING_CNT 1024 2097 #define BGE_RETURN_RING_CNT 1024 2098 #define BGE_RETURN_RING_CNT_5705 512 2099 2100 /* 2101 * Possible TX ring sizes. 2102 */ 2103 #define BGE_TX_RING_CNT_128 128 2104 #define BGE_TX_RING_BASE_128 0x3800 2105 2106 #define BGE_TX_RING_CNT_256 256 2107 #define BGE_TX_RING_BASE_256 0x3000 2108 2109 #define BGE_TX_RING_CNT_512 512 2110 #define BGE_TX_RING_BASE_512 0x2000 2111 2112 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2113 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2114 2115 /* 2116 * Tigon III statistics counters. 2117 */ 2118 2119 /* Stats counters access through registers */ 2120 struct bge_mac_stats_regs { 2121 u_int32_t ifHCOutOctets; 2122 u_int32_t Reserved0; 2123 u_int32_t etherStatsCollisions; 2124 u_int32_t outXonSent; 2125 u_int32_t outXoffSent; 2126 u_int32_t Reserved1; 2127 u_int32_t dot3StatsInternalMacTransmitErrors; 2128 u_int32_t dot3StatsSingleCollisionFrames; 2129 u_int32_t dot3StatsMultipleCollisionFrames; 2130 u_int32_t dot3StatsDeferredTransmissions; 2131 u_int32_t Reserved2; 2132 u_int32_t dot3StatsExcessiveCollisions; 2133 u_int32_t dot3StatsLateCollisions; 2134 u_int32_t Reserved3[14]; 2135 u_int32_t ifHCOutUcastPkts; 2136 u_int32_t ifHCOutMulticastPkts; 2137 u_int32_t ifHCOutBroadcastPkts; 2138 u_int32_t Reserved4[2]; 2139 u_int32_t ifHCInOctets; 2140 u_int32_t Reserved5; 2141 u_int32_t etherStatsFragments; 2142 u_int32_t ifHCInUcastPkts; 2143 u_int32_t ifHCInMulticastPkts; 2144 u_int32_t ifHCInBroadcastPkts; 2145 u_int32_t dot3StatsFCSErrors; 2146 u_int32_t dot3StatsAlignmentErrors; 2147 u_int32_t xonPauseFramesReceived; 2148 u_int32_t xoffPauseFramesReceived; 2149 u_int32_t macControlFramesReceived; 2150 u_int32_t xoffStateEntered; 2151 u_int32_t dot3StatsFramesTooLong; 2152 u_int32_t etherStatsJabbers; 2153 u_int32_t etherStatsUndersizePkts; 2154 }; 2155 2156 struct bge_stats { 2157 u_int8_t Reserved0[256]; 2158 2159 /* Statistics maintained by Receive MAC. */ 2160 bge_hostaddr ifHCInOctets; 2161 bge_hostaddr Reserved1; 2162 bge_hostaddr etherStatsFragments; 2163 bge_hostaddr ifHCInUcastPkts; 2164 bge_hostaddr ifHCInMulticastPkts; 2165 bge_hostaddr ifHCInBroadcastPkts; 2166 bge_hostaddr dot3StatsFCSErrors; 2167 bge_hostaddr dot3StatsAlignmentErrors; 2168 bge_hostaddr xonPauseFramesReceived; 2169 bge_hostaddr xoffPauseFramesReceived; 2170 bge_hostaddr macControlFramesReceived; 2171 bge_hostaddr xoffStateEntered; 2172 bge_hostaddr dot3StatsFramesTooLong; 2173 bge_hostaddr etherStatsJabbers; 2174 bge_hostaddr etherStatsUndersizePkts; 2175 bge_hostaddr inRangeLengthError; 2176 bge_hostaddr outRangeLengthError; 2177 bge_hostaddr etherStatsPkts64Octets; 2178 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2179 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2180 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2181 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2182 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2183 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2184 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2185 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2186 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2187 2188 bge_hostaddr Unused1[37]; 2189 2190 /* Statistics maintained by Transmit MAC. */ 2191 bge_hostaddr ifHCOutOctets; 2192 bge_hostaddr Reserved2; 2193 bge_hostaddr etherStatsCollisions; 2194 bge_hostaddr outXonSent; 2195 bge_hostaddr outXoffSent; 2196 bge_hostaddr flowControlDone; 2197 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2198 bge_hostaddr dot3StatsSingleCollisionFrames; 2199 bge_hostaddr dot3StatsMultipleCollisionFrames; 2200 bge_hostaddr dot3StatsDeferredTransmissions; 2201 bge_hostaddr Reserved3; 2202 bge_hostaddr dot3StatsExcessiveCollisions; 2203 bge_hostaddr dot3StatsLateCollisions; 2204 bge_hostaddr dot3Collided2Times; 2205 bge_hostaddr dot3Collided3Times; 2206 bge_hostaddr dot3Collided4Times; 2207 bge_hostaddr dot3Collided5Times; 2208 bge_hostaddr dot3Collided6Times; 2209 bge_hostaddr dot3Collided7Times; 2210 bge_hostaddr dot3Collided8Times; 2211 bge_hostaddr dot3Collided9Times; 2212 bge_hostaddr dot3Collided10Times; 2213 bge_hostaddr dot3Collided11Times; 2214 bge_hostaddr dot3Collided12Times; 2215 bge_hostaddr dot3Collided13Times; 2216 bge_hostaddr dot3Collided14Times; 2217 bge_hostaddr dot3Collided15Times; 2218 bge_hostaddr ifHCOutUcastPkts; 2219 bge_hostaddr ifHCOutMulticastPkts; 2220 bge_hostaddr ifHCOutBroadcastPkts; 2221 bge_hostaddr dot3StatsCarrierSenseErrors; 2222 bge_hostaddr ifOutDiscards; 2223 bge_hostaddr ifOutErrors; 2224 2225 bge_hostaddr Unused2[31]; 2226 2227 /* Statistics maintained by Receive List Placement. */ 2228 bge_hostaddr COSIfHCInPkts[16]; 2229 bge_hostaddr COSFramesDroppedDueToFilters; 2230 bge_hostaddr nicDmaWriteQueueFull; 2231 bge_hostaddr nicDmaWriteHighPriQueueFull; 2232 bge_hostaddr nicNoMoreRxBDs; 2233 bge_hostaddr ifInDiscards; 2234 bge_hostaddr ifInErrors; 2235 bge_hostaddr nicRecvThresholdHit; 2236 2237 bge_hostaddr Unused3[9]; 2238 2239 /* Statistics maintained by Send Data Initiator. */ 2240 bge_hostaddr COSIfHCOutPkts[16]; 2241 bge_hostaddr nicDmaReadQueueFull; 2242 bge_hostaddr nicDmaReadHighPriQueueFull; 2243 bge_hostaddr nicSendDataCompQueueFull; 2244 2245 /* Statistics maintained by Host Coalescing. */ 2246 bge_hostaddr nicRingSetSendProdIndex; 2247 bge_hostaddr nicRingStatusUpdate; 2248 bge_hostaddr nicInterrupts; 2249 bge_hostaddr nicAvoidedInterrupts; 2250 bge_hostaddr nicSendThresholdHit; 2251 2252 u_int8_t Reserved4[320]; 2253 }; 2254 2255 /* 2256 * Tigon general information block. This resides in host memory 2257 * and contains the status counters, ring control blocks and 2258 * producer pointers. 2259 */ 2260 2261 struct bge_gib { 2262 struct bge_stats bge_stats; 2263 struct bge_rcb bge_tx_rcb[16]; 2264 struct bge_rcb bge_std_rx_rcb; 2265 struct bge_rcb bge_jumbo_rx_rcb; 2266 struct bge_rcb bge_mini_rx_rcb; 2267 struct bge_rcb bge_return_rcb; 2268 }; 2269 2270 /* 2271 * NOTE! On the Alpha, we have an alignment constraint. 2272 * The first thing in the packet is a 14-byte Ethernet header. 2273 * This means that the packet is misaligned. To compensate, 2274 * we actually offset the data 2 bytes into the cluster. This 2275 * alignes the packet after the Ethernet header at a 32-bit 2276 * boundary. 2277 */ 2278 2279 #define ETHER_ALIGN 2 2280 2281 #define BGE_FRAMELEN ETHER_MAX_LEN 2282 #define BGE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_CRC_LEN) 2283 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2284 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2285 #define BGE_PAGE_SIZE PAGE_SIZE 2286 #define BGE_MIN_FRAMELEN 60 2287 2288 /* 2289 * Other utility macros. 2290 */ 2291 #define BGE_INC(x, y) (x) = (x + 1) % y 2292 2293 /* 2294 * Vital product data and structures. 2295 */ 2296 #define BGE_VPD_FLAG 0x8000 2297 2298 /* VPD structures */ 2299 struct vpd_res { 2300 u_int8_t vr_id; 2301 u_int8_t vr_len; 2302 u_int8_t vr_pad; 2303 }; 2304 2305 struct vpd_key { 2306 char vk_key[2]; 2307 u_int8_t vk_len; 2308 }; 2309 2310 #define VPD_RES_ID 0x82 /* ID string */ 2311 #define VPD_RES_READ 0x90 /* start of read only area */ 2312 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2313 #define VPD_RES_END 0x78 /* end tag */ 2314 2315 2316 /* 2317 * Register access macros. The Tigon always uses memory mapped register 2318 * accesses and all registers must be accessed with 32 bit operations. 2319 */ 2320 2321 #define CSR_WRITE_4(sc, reg, val) \ 2322 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2323 2324 #define CSR_READ_4(sc, reg) \ 2325 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2326 2327 #define BGE_SETBIT(sc, reg, x) \ 2328 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 2329 #define BGE_CLRBIT(sc, reg, x) \ 2330 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 2331 2332 #define PCI_SETBIT(pc, tag, reg, x) \ 2333 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x)) 2334 #define PCI_CLRBIT(pc, tag, reg, x) \ 2335 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x)) 2336 2337 /* 2338 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2339 * values are tuneable. They control the actual amount of buffers 2340 * allocated for the standard, mini and jumbo receive rings. 2341 */ 2342 2343 #define BGE_SSLOTS 256 2344 #define BGE_MSLOTS 256 2345 #define BGE_JSLOTS 384 2346 #define BGE_RSLOTS 256 2347 2348 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2349 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2350 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2351 #define BGE_JPAGESZ PAGE_SIZE 2352 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2353 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2354 2355 /* 2356 * Ring structures. Most of these reside in host memory and we tell 2357 * the NIC where they are via the ring control blocks. The exceptions 2358 * are the tx and command rings, which live in NIC memory and which 2359 * we access via the shared memory window. 2360 */ 2361 struct bge_ring_data { 2362 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2363 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2364 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2365 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2366 struct bge_status_block bge_status_block; 2367 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2368 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2369 struct bge_gib bge_info; 2370 }; 2371 2372 #define BGE_RING_DMA_ADDR(sc, offset) \ 2373 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2374 offsetof(struct bge_ring_data, offset)) 2375 2376 /* 2377 * Number of DMA segments in a TxCB. Note that this is carefully 2378 * chosen to make the total struct size an even power of two. It's 2379 * critical that no TxCB be split across a page boundary since 2380 * no attempt is made to allocate physically contiguous memory. 2381 * 2382 */ 2383 #if 0 /* pre-TSO values */ 2384 #define BGE_TXDMA_MAX ETHER_MAX_LEN_JUMBO 2385 #ifdef _LP64 2386 #define BGE_NTXSEG 30 2387 #else 2388 #define BGE_NTXSEG 31 2389 #endif 2390 #else /* TSO values */ 2391 #define BGE_TXDMA_MAX (round_page(IP_MAXPACKET)) /* for TSO */ 2392 #ifdef _LP64 2393 #define BGE_NTXSEG 120 /* XXX just a guess */ 2394 #else 2395 #define BGE_NTXSEG 124 /* XXX just a guess */ 2396 #endif 2397 #endif /* TSO values */ 2398 2399 2400 /* 2401 * Mbuf pointers. We need these to keep track of the virtual addresses 2402 * of our mbuf chains since we can only convert from physical to virtual, 2403 * not the other way around. 2404 */ 2405 struct bge_chain_data { 2406 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2407 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2408 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2409 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2410 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2411 bus_dmamap_t bge_rx_jumbo_map; 2412 /* Stick the jumbo mem management stuff here too. */ 2413 void * bge_jslots[BGE_JSLOTS]; 2414 void * bge_jumbo_buf; 2415 }; 2416 2417 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 2418 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 2419 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 2420 2421 struct bge_type { 2422 u_int16_t bge_vid; 2423 u_int16_t bge_did; 2424 char *bge_name; 2425 }; 2426 2427 #define BGE_HWREV_TIGON 0x01 2428 #define BGE_HWREV_TIGON_II 0x02 2429 #define BGE_TIMEOUT 1000 2430 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2431 2432 struct bge_jpool_entry { 2433 int slot; 2434 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2435 }; 2436 2437 struct bge_bcom_hack { 2438 int reg; 2439 int val; 2440 }; 2441 2442 struct txdmamap_pool_entry { 2443 bus_dmamap_t dmamap; 2444 SLIST_ENTRY(txdmamap_pool_entry) link; 2445 }; 2446 2447 /* 2448 * Flags for bge_flags. 2449 */ 2450 #define BGE_TXRING_VALID 0x00000001 2451 #define BGE_RXRING_VALID 0x00000002 2452 #define BGE_JUMBO_RXRING_VALID 0x00000004 2453 #define BGE_RX_ALIGNBUG 0x00000008 2454 #define BGE_PCIX 0x00000020 2455 #define BGE_PCIE 0x00000040 2456 #define BGE_PHY_FIBER_TBI 0x00000800 2457 2458 struct bge_softc { 2459 device_t bge_dev; 2460 struct ethercom ethercom; /* interface info */ 2461 bus_space_handle_t bge_bhandle; 2462 bus_space_tag_t bge_btag; 2463 void *bge_intrhand; 2464 pci_chipset_tag_t sc_pc; 2465 pcitag_t sc_pcitag; 2466 2467 struct mii_data bge_mii; 2468 struct ifmedia bge_ifmedia; /* media info */ 2469 u_int8_t bge_extram; /* has external SSRAM */ 2470 u_int32_t bge_return_ring_cnt; 2471 u_int32_t bge_tx_prodidx; 2472 bus_dma_tag_t bge_dmatag; 2473 u_int32_t bge_chipid; 2474 u_int32_t bge_local_ctrl_reg; 2475 struct bge_ring_data *bge_rdata; /* rings */ 2476 struct bge_chain_data bge_cdata; /* mbufs */ 2477 bus_dmamap_t bge_ring_map; 2478 u_int16_t bge_tx_saved_considx; 2479 u_int16_t bge_rx_saved_considx; 2480 u_int16_t bge_ev_saved_considx; 2481 u_int16_t bge_std; /* current std ring head */ 2482 u_int16_t bge_jumbo; /* current jumo ring head */ 2483 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2484 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2485 u_int32_t bge_stat_ticks; 2486 u_int32_t bge_rx_coal_ticks; 2487 u_int32_t bge_tx_coal_ticks; 2488 u_int32_t bge_rx_max_coal_bds; 2489 u_int32_t bge_tx_max_coal_bds; 2490 u_int32_t bge_tx_buf_ratio; 2491 int bge_if_flags; 2492 int bge_flags; 2493 int bge_flowflags; 2494 #ifdef BGE_EVENT_COUNTERS 2495 /* 2496 * Event counters. 2497 */ 2498 struct evcnt bge_ev_intr; /* interrupts */ 2499 struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ 2500 struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ 2501 struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ 2502 struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ 2503 struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ 2504 struct evcnt bge_ev_xoffentered;/* XOFF state entered */ 2505 #endif /* BGE_EVENT_COUNTERS */ 2506 int bge_txcnt; 2507 int bge_link; 2508 struct callout bge_timeout; 2509 char *bge_vpd_prodname; 2510 char *bge_vpd_readonly; 2511 int bge_pending_rxintr_change; 2512 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2513 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2514 2515 #if NRND > 0 2516 rndsource_element_t rnd_source; /* random source */ 2517 #endif 2518 }; 2519
Indexes created Fri Sep 26 20:09:58 GMT 2025