if_bgereg.h revision 1.54
1 /* $NetBSD: if_bgereg.h,v 1.54 2010/01/24 16:21:09 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 66 #define BGE_PAGE_ZERO 0x00000000 67 #define BGE_PAGE_ZERO_END 0x000000FF 68 #define BGE_SEND_RING_RCB 0x00000100 69 #define BGE_SEND_RING_RCB_END 0x000001FF 70 #define BGE_RX_RETURN_RING_RCB 0x00000200 71 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72 #define BGE_STATS_BLOCK 0x00000300 73 #define BGE_STATS_BLOCK_END 0x00000AFF 74 #define BGE_STATUS_BLOCK 0x00000B00 75 #define BGE_STATUS_BLOCK_END 0x00000B4F 76 #define BGE_SOFTWARE_GENCOMM 0x00000B50 77 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 80 #define BGE_UNMAPPED 0x00001000 81 #define BGE_UNMAPPED_END 0x00001FFF 82 #define BGE_DMA_DESCRIPTORS 0x00002000 83 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 84 #define BGE_SEND_RING_1_TO_4 0x00004000 85 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 86 87 /* Mappings for internal memory configuration */ 88 #define BGE_STD_RX_RINGS 0x00006000 89 #define BGE_STD_RX_RINGS_END 0x00006FFF 90 #define BGE_JUMBO_RX_RINGS 0x00007000 91 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 92 #define BGE_BUFFPOOL_1 0x00008000 93 #define BGE_BUFFPOOL_1_END 0x0000FFFF 94 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 95 #define BGE_BUFFPOOL_2_END 0x00017FFF 96 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 97 #define BGE_BUFFPOOL_3_END 0x0001FFFF 98 99 /* Mappings for external SSRAM configurations */ 100 #define BGE_SEND_RING_5_TO_6 0x00006000 101 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 102 #define BGE_SEND_RING_7_TO_8 0x00007000 103 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 104 #define BGE_SEND_RING_9_TO_16 0x00008000 105 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 106 #define BGE_EXT_STD_RX_RINGS 0x0000C000 107 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 108 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 109 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 110 #define BGE_MINI_RX_RINGS 0x0000E000 111 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 112 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 113 #define BGE_AVAIL_REGION1_END 0x00017FFF 114 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 115 #define BGE_AVAIL_REGION2_END 0x0001FFFF 116 #define BGE_EXT_SSRAM 0x00020000 117 #define BGE_EXT_SSRAM_END 0x000FFFFF 118 119 120 /* 121 * BCM570x register offsets. These are memory mapped registers 122 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 123 * Each register must be accessed using 32 bit operations. 124 * 125 * All registers are accessed through a 32K shared memory block. 126 * The first group of registers are actually copies of the PCI 127 * configuration space registers. 128 */ 129 130 /* 131 * PCI registers defined in the PCI 2.2 spec. 132 */ 133 #define BGE_PCI_VID 0x00 134 #define BGE_PCI_DID 0x02 135 #define BGE_PCI_CMD 0x04 136 #define BGE_PCI_STS 0x06 137 #define BGE_PCI_REV 0x08 138 #define BGE_PCI_CLASS 0x09 139 #define BGE_PCI_CACHESZ 0x0C 140 #define BGE_PCI_LATTIMER 0x0D 141 #define BGE_PCI_HDRTYPE 0x0E 142 #define BGE_PCI_BIST 0x0F 143 #define BGE_PCI_BAR0 0x10 144 #define BGE_PCI_BAR1 0x14 145 #define BGE_PCI_SUBSYS 0x2C 146 #define BGE_PCI_SUBVID 0x2E 147 #define BGE_PCI_ROMBASE 0x30 148 #define BGE_PCI_CAPPTR 0x34 149 #define BGE_PCI_INTLINE 0x3C 150 #define BGE_PCI_INTPIN 0x3D 151 #define BGE_PCI_MINGNT 0x3E 152 #define BGE_PCI_MAXLAT 0x3F 153 #define BGE_PCI_PCIXCAP 0x40 154 #define BGE_PCI_NEXTPTR_PM 0x41 155 #define BGE_PCI_PCIX_CMD 0x42 156 #define BGE_PCI_PCIX_STS 0x44 157 #define BGE_PCI_PWRMGMT_CAPID 0x48 158 #define BGE_PCI_NEXTPTR_VPD 0x49 159 #define BGE_PCI_PWRMGMT_CAPS 0x4A 160 #define BGE_PCI_PWRMGMT_CMD 0x4C 161 #define BGE_PCI_PWRMGMT_STS 0x4D 162 #define BGE_PCI_PWRMGMT_DATA 0x4F 163 #define BGE_PCI_VPD_CAPID 0x50 164 #define BGE_PCI_NEXTPTR_MSI 0x51 165 #define BGE_PCI_VPD_ADDR 0x52 166 #define BGE_PCI_VPD_DATA 0x54 167 #define BGE_PCI_MSI_CAPID 0x58 168 #define BGE_PCI_NEXTPTR_NONE 0x59 169 #define BGE_PCI_MSI_CTL 0x5A 170 #define BGE_PCI_MSI_ADDR_HI 0x5C 171 #define BGE_PCI_MSI_ADDR_LO 0x60 172 #define BGE_PCI_MSI_DATA 0x64 173 174 /* 175 * PCI registers specific to the BCM570x family. 176 */ 177 #define BGE_PCI_MISC_CTL 0x68 178 #define BGE_PCI_DMA_RW_CTL 0x6C 179 #define BGE_PCI_PCISTATE 0x70 180 #define BGE_PCI_CLKCTL 0x74 181 #define BGE_PCI_REG_BASEADDR 0x78 182 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 183 #define BGE_PCI_REG_DATA 0x80 184 #define BGE_PCI_MEMWIN_DATA 0x84 185 #define BGE_PCI_MODECTL 0x88 186 #define BGE_PCI_MISC_CFG 0x8C 187 #define BGE_PCI_MISC_LOCALCTL 0x90 188 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 189 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 190 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 191 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 192 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 193 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 194 #define BGE_PCI_ISR_MBX_HI 0xB0 195 #define BGE_PCI_ISR_MBX_LO 0xB4 196 #define BGE_PCI_PRODID_ASICREV 0xBC 197 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 198 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 199 200 #define BGE_PCI_UNKNOWN0 0xC4 201 /* XXX: 202 * Used in PCI-Express code for 575x chips. 203 * Should be replaced with checking for a PCI config-space 204 * capability for PCI-Express, and PCI-Express standard 205 * offsets into that capability block. 206 */ 207 #define BGE_PCI_CONF_DEV_CTRL 0xD8 208 #define BGE_PCI_CONF_DEV_STUS 0xDA 209 210 211 /* PCI Misc. Host control register */ 212 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 213 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 214 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 215 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 216 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 217 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 218 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 219 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 220 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 221 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 222 223 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 224 #if BYTE_ORDER == LITTLE_ENDIAN 225 #define BGE_DMA_SWAP_OPTIONS \ 226 BGE_MODECTL_WORDSWAP_NONFRAME| \ 227 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 228 #else 229 #define BGE_DMA_SWAP_OPTIONS \ 230 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 231 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 232 #endif 233 234 #define BGE_INIT \ 235 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 236 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 237 238 #define BGE_CHIPID_TIGON_I 0x4000 239 #define BGE_CHIPID_TIGON_II 0x6000 240 #define BGE_CHIPID_BCM5700_A0 0x7000 241 #define BGE_CHIPID_BCM5700_A1 0x7001 242 #define BGE_CHIPID_BCM5700_B0 0x7100 243 #define BGE_CHIPID_BCM5700_B1 0x7101 244 #define BGE_CHIPID_BCM5700_B2 0x7102 245 #define BGE_CHIPID_BCM5700_B3 0x7103 246 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 247 #define BGE_CHIPID_BCM5700_C0 0x7200 248 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 249 #define BGE_CHIPID_BCM5701_B0 0x0100 250 #define BGE_CHIPID_BCM5701_B2 0x0102 251 #define BGE_CHIPID_BCM5701_B5 0x0105 252 #define BGE_CHIPID_BCM5703_A0 0x1000 253 #define BGE_CHIPID_BCM5703_A1 0x1001 254 #define BGE_CHIPID_BCM5703_A2 0x1002 255 #define BGE_CHIPID_BCM5703_A3 0x1003 256 #define BGE_CHIPID_BCM5703_B0 0x1100 257 #define BGE_CHIPID_BCM5704_A0 0x2000 258 #define BGE_CHIPID_BCM5704_A1 0x2001 259 #define BGE_CHIPID_BCM5704_A2 0x2002 260 #define BGE_CHIPID_BCM5704_A3 0x2003 261 #define BGE_CHIPID_BCM5704_B0 0x2100 262 #define BGE_CHIPID_BCM5705_A0 0x3000 263 #define BGE_CHIPID_BCM5705_A1 0x3001 264 #define BGE_CHIPID_BCM5705_A2 0x3002 265 #define BGE_CHIPID_BCM5705_A3 0x3003 266 #define BGE_CHIPID_BCM5750_A0 0x4000 267 #define BGE_CHIPID_BCM5750_A1 0x4001 268 #define BGE_CHIPID_BCM5750_A3 0x4003 269 #define BGE_CHIPID_BCM5750_B0 0x4010 270 #define BGE_CHIPID_BCM5750_B1 0x4101 271 #define BGE_CHIPID_BCM5750_C0 0x4200 272 #define BGE_CHIPID_BCM5750_C1 0x4201 273 #define BGE_CHIPID_BCM5750_C2 0x4202 274 #define BGE_CHIPID_BCM5714_A0 0x5000 275 #define BGE_CHIPID_BCM5761_A0 0x5761000 276 #define BGE_CHIPID_BCM5761_A1 0x5761100 277 #define BGE_CHIPID_BCM5784_A0 0x5784000 278 #define BGE_CHIPID_BCM5784_A1 0x5784100 279 #define BGE_CHIPID_BCM5752_A0 0x6000 280 #define BGE_CHIPID_BCM5752_A1 0x6001 281 #define BGE_CHIPID_BCM5752_A2 0x6002 282 #define BGE_CHIPID_BCM5714_B0 0x8000 283 #define BGE_CHIPID_BCM5714_B3 0x8003 284 #define BGE_CHIPID_BCM5715_A0 0x9000 285 #define BGE_CHIPID_BCM5715_A1 0x9001 286 #define BGE_CHIPID_BCM5715_A3 0x9003 287 #define BGE_CHIPID_BCM5755_A0 0xa000 288 #define BGE_CHIPID_BCM5755_A1 0xa001 289 #define BGE_CHIPID_BCM5755_A2 0xa002 290 #define BGE_CHIPID_BCM5755_C0 0xa200 291 #define BGE_CHIPID_BCM5787_A0 0xb000 292 #define BGE_CHIPID_BCM5787_A1 0xb001 293 #define BGE_CHIPID_BCM5787_A2 0xb002 294 #define BGE_CHIPID_BCM5906_A1 0xc001 295 #define BGE_CHIPID_BCM5906_A2 0xc002 296 #define BGE_CHIPID_BCM57780_A0 0x57780000 297 #define BGE_CHIPID_BCM57780_A1 0x57780001 298 299 /* shorthand one */ 300 #define BGE_ASICREV(x) ((x) >> 12) 301 #define BGE_ASICREV_BCM5700 0x07 302 #define BGE_ASICREV_BCM5701 0x00 303 #define BGE_ASICREV_BCM5703 0x01 304 #define BGE_ASICREV_BCM5704 0x02 305 #define BGE_ASICREV_BCM5705 0x03 306 #define BGE_ASICREV_BCM5750 0x04 307 #define BGE_ASICREV_BCM5714_A0 0x05 308 #define BGE_ASICREV_BCM5752 0x06 309 /* ASIC revision 0x07 is the original bcm5700 */ 310 #define BGE_ASICREV_BCM5780 0x08 311 #define BGE_ASICREV_BCM5714 0x09 312 #define BGE_ASICREV_BCM5755 0x0a 313 #define BGE_ASICREV_BCM5787 0x0b 314 #define BGE_ASICREV_BCM5906 0x0c 315 #define BGE_ASICREV_USE_PRODID_REG 0x0f 316 #define BGE_ASICREV_BCM5761 0x5761 317 #define BGE_ASICREV_BCM5784 0x5784 318 #define BGE_ASICREV_BCM5785 0x5785 319 #define BGE_ASICREV_BCM57780 0x57780 320 #define BGE_ASICREV_BCM5717 0x5717 321 #define BGE_ASICREV_BCM57765 0x57785 322 323 /* chip revisions */ 324 #define BGE_CHIPREV(x) ((x) >> 8) 325 #define BGE_CHIPREV_5700_AX 0x70 326 #define BGE_CHIPREV_5700_BX 0x71 327 #define BGE_CHIPREV_5700_CX 0x72 328 #define BGE_CHIPREV_5701_AX 0x00 329 #define BGE_CHIPREV_5703_AX 0x10 330 #define BGE_CHIPREV_5704_AX 0x20 331 #define BGE_CHIPREV_5704_BX 0x21 332 #define BGE_CHIPREV_5750_AX 0x40 333 #define BGE_CHIPREV_5750_BX 0x41 334 335 /* PCI DMA Read/Write Control register */ 336 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 337 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 338 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 339 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 340 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 341 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 342 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 343 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 344 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 345 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 346 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 347 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 348 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 349 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 350 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 351 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 352 353 /* PCI DMA Read/Write Control register, alternate usage for PCI-Express */ 354 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128 0x00180000 355 #define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256 0x00380000 356 357 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 358 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 359 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 360 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 361 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 362 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 363 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 364 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 365 366 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 367 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 368 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 369 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 370 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 371 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 372 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 373 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 374 375 /* 376 * PCI state register -- note, this register is read only 377 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 378 * register is set. 379 */ 380 #define BGE_PCISTATE_FORCE_RESET 0x00000001 381 #define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 382 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 383 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 384 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 385 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 386 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 387 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 388 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 389 390 /* 391 * The following bits in PCI state register are reserved. 392 * If we check that the register values reverts on reset, 393 * do not check these bits. On some 5704C (rev A3) and some 394 * Altima chips, these bits do not revert until much later 395 * in the bge driver's bge_reset() chip-reset state machine. 396 */ 397 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 398 399 /* 400 * PCI Clock Control register -- note, this register is read only 401 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 402 * register is set. 403 */ 404 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 405 #define BGE_PCICLOCKCTL_M66EN 0x00000080 406 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 407 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 408 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 409 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 410 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 411 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 412 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 413 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 414 415 416 #ifndef PCIM_CMD_MWIEN 417 #define PCIM_CMD_MWIEN 0x0010 418 #endif 419 420 /* 421 * High priority mailbox registers 422 * Each mailbox is 64-bits wide, though we only use the 423 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 424 * first. The NIC will load the mailbox after the lower 32 bit word 425 * has been updated. 426 */ 427 #define BGE_MBX_IRQ0_HI 0x0200 428 #define BGE_MBX_IRQ0_LO 0x0204 429 #define BGE_MBX_IRQ1_HI 0x0208 430 #define BGE_MBX_IRQ1_LO 0x020C 431 #define BGE_MBX_IRQ2_HI 0x0210 432 #define BGE_MBX_IRQ2_LO 0x0214 433 #define BGE_MBX_IRQ3_HI 0x0218 434 #define BGE_MBX_IRQ3_LO 0x021C 435 #define BGE_MBX_GEN0_HI 0x0220 436 #define BGE_MBX_GEN0_LO 0x0224 437 #define BGE_MBX_GEN1_HI 0x0228 438 #define BGE_MBX_GEN1_LO 0x022C 439 #define BGE_MBX_GEN2_HI 0x0230 440 #define BGE_MBX_GEN2_LO 0x0234 441 #define BGE_MBX_GEN3_HI 0x0228 442 #define BGE_MBX_GEN3_LO 0x022C 443 #define BGE_MBX_GEN4_HI 0x0240 444 #define BGE_MBX_GEN4_LO 0x0244 445 #define BGE_MBX_GEN5_HI 0x0248 446 #define BGE_MBX_GEN5_LO 0x024C 447 #define BGE_MBX_GEN6_HI 0x0250 448 #define BGE_MBX_GEN6_LO 0x0254 449 #define BGE_MBX_GEN7_HI 0x0258 450 #define BGE_MBX_GEN7_LO 0x025C 451 #define BGE_MBX_RELOAD_STATS_HI 0x0260 452 #define BGE_MBX_RELOAD_STATS_LO 0x0264 453 #define BGE_MBX_RX_STD_PROD_HI 0x0268 454 #define BGE_MBX_RX_STD_PROD_LO 0x026C 455 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 456 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 457 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 458 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 459 #define BGE_MBX_RX_CONS0_HI 0x0280 460 #define BGE_MBX_RX_CONS0_LO 0x0284 461 #define BGE_MBX_RX_CONS1_HI 0x0288 462 #define BGE_MBX_RX_CONS1_LO 0x028C 463 #define BGE_MBX_RX_CONS2_HI 0x0290 464 #define BGE_MBX_RX_CONS2_LO 0x0294 465 #define BGE_MBX_RX_CONS3_HI 0x0298 466 #define BGE_MBX_RX_CONS3_LO 0x029C 467 #define BGE_MBX_RX_CONS4_HI 0x02A0 468 #define BGE_MBX_RX_CONS4_LO 0x02A4 469 #define BGE_MBX_RX_CONS5_HI 0x02A8 470 #define BGE_MBX_RX_CONS5_LO 0x02AC 471 #define BGE_MBX_RX_CONS6_HI 0x02B0 472 #define BGE_MBX_RX_CONS6_LO 0x02B4 473 #define BGE_MBX_RX_CONS7_HI 0x02B8 474 #define BGE_MBX_RX_CONS7_LO 0x02BC 475 #define BGE_MBX_RX_CONS8_HI 0x02C0 476 #define BGE_MBX_RX_CONS8_LO 0x02C4 477 #define BGE_MBX_RX_CONS9_HI 0x02C8 478 #define BGE_MBX_RX_CONS9_LO 0x02CC 479 #define BGE_MBX_RX_CONS10_HI 0x02D0 480 #define BGE_MBX_RX_CONS10_LO 0x02D4 481 #define BGE_MBX_RX_CONS11_HI 0x02D8 482 #define BGE_MBX_RX_CONS11_LO 0x02DC 483 #define BGE_MBX_RX_CONS12_HI 0x02E0 484 #define BGE_MBX_RX_CONS12_LO 0x02E4 485 #define BGE_MBX_RX_CONS13_HI 0x02E8 486 #define BGE_MBX_RX_CONS13_LO 0x02EC 487 #define BGE_MBX_RX_CONS14_HI 0x02F0 488 #define BGE_MBX_RX_CONS14_LO 0x02F4 489 #define BGE_MBX_RX_CONS15_HI 0x02F8 490 #define BGE_MBX_RX_CONS15_LO 0x02FC 491 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 492 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 493 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 494 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 495 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 496 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 497 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 498 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 499 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 500 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 501 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 502 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 503 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 504 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 505 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 506 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 507 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 508 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 509 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 510 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 511 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 512 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 513 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 514 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 515 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 516 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 517 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 518 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 519 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 520 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 521 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 522 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 523 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 524 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 525 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 526 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 527 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 528 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 529 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 530 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 531 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 532 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 533 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 534 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 535 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 536 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 537 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 538 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 539 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 540 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 541 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 542 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 543 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 544 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 545 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 546 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 547 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 548 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 549 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 550 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 551 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 552 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 553 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 554 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 555 556 #define BGE_TX_RINGS_MAX 4 557 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 558 #define BGE_RX_RINGS_MAX 16 559 560 /* Ethernet MAC control registers */ 561 #define BGE_MAC_MODE 0x0400 562 #define BGE_MAC_STS 0x0404 563 #define BGE_MAC_EVT_ENB 0x0408 564 #define BGE_MAC_LED_CTL 0x040C 565 #define BGE_MAC_ADDR1_LO 0x0410 566 #define BGE_MAC_ADDR1_HI 0x0414 567 #define BGE_MAC_ADDR2_LO 0x0418 568 #define BGE_MAC_ADDR2_HI 0x041C 569 #define BGE_MAC_ADDR3_LO 0x0420 570 #define BGE_MAC_ADDR3_HI 0x0424 571 #define BGE_MAC_ADDR4_LO 0x0428 572 #define BGE_MAC_ADDR4_HI 0x042C 573 #define BGE_WOL_PATPTR 0x0430 574 #define BGE_WOL_PATCFG 0x0434 575 #define BGE_TX_RANDOM_BACKOFF 0x0438 576 #define BGE_RX_MTU 0x043C 577 #define BGE_GBIT_PCS_TEST 0x0440 578 #define BGE_TX_TBI_AUTONEG 0x0444 579 #define BGE_RX_TBI_AUTONEG 0x0448 580 #define BGE_MI_COMM 0x044C 581 #define BGE_MI_STS 0x0450 582 #define BGE_MI_MODE 0x0454 583 #define BGE_AUTOPOLL_STS 0x0458 584 #define BGE_TX_MODE 0x045C 585 #define BGE_TX_STS 0x0460 586 #define BGE_TX_LENGTHS 0x0464 587 #define BGE_RX_MODE 0x0468 588 #define BGE_RX_STS 0x046C 589 #define BGE_MAR0 0x0470 590 #define BGE_MAR1 0x0474 591 #define BGE_MAR2 0x0478 592 #define BGE_MAR3 0x047C 593 #define BGE_RX_BD_RULES_CTL0 0x0480 594 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 595 #define BGE_RX_BD_RULES_CTL1 0x0488 596 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 597 #define BGE_RX_BD_RULES_CTL2 0x0490 598 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 599 #define BGE_RX_BD_RULES_CTL3 0x0498 600 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 601 #define BGE_RX_BD_RULES_CTL4 0x04A0 602 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 603 #define BGE_RX_BD_RULES_CTL5 0x04A8 604 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 605 #define BGE_RX_BD_RULES_CTL6 0x04B0 606 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 607 #define BGE_RX_BD_RULES_CTL7 0x04B8 608 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 609 #define BGE_RX_BD_RULES_CTL8 0x04C0 610 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 611 #define BGE_RX_BD_RULES_CTL9 0x04C8 612 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 613 #define BGE_RX_BD_RULES_CTL10 0x04D0 614 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 615 #define BGE_RX_BD_RULES_CTL11 0x04D8 616 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 617 #define BGE_RX_BD_RULES_CTL12 0x04E0 618 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 619 #define BGE_RX_BD_RULES_CTL13 0x04E8 620 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 621 #define BGE_RX_BD_RULES_CTL14 0x04F0 622 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 623 #define BGE_RX_BD_RULES_CTL15 0x04F8 624 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 625 #define BGE_RX_RULES_CFG 0x0500 626 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 627 #define BGE_SERDES_CFG 0x0590 628 #define BGE_SGDIG_CFG 0x05B0 629 #define BGE_SGDIG_STS 0x05B4 630 #define BGE_MAC_STATS 0x0800 631 #define BGE_TX_STATS 0x0880 632 633 /* Ethernet MAC Mode register */ 634 #define BGE_MACMODE_RESET 0x00000001 635 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 636 #define BGE_MACMODE_PORTMODE 0x0000000C 637 #define BGE_MACMODE_LOOPBACK 0x00000010 638 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 639 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 640 #define BGE_MACMODE_MAX_DEFER 0x00000200 641 #define BGE_MACMODE_LINK_POLARITY 0x00000400 642 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 643 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 644 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 645 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 646 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 647 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 648 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 649 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 650 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 651 #define BGE_MACMODE_MIP_ENB 0x00100000 652 #define BGE_MACMODE_TXDMA_ENB 0x00200000 653 #define BGE_MACMODE_RXDMA_ENB 0x00400000 654 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 655 656 #define BGE_PORTMODE_NONE 0x00000000 657 #define BGE_PORTMODE_MII 0x00000004 658 #define BGE_PORTMODE_GMII 0x00000008 659 #define BGE_PORTMODE_TBI 0x0000000C 660 661 /* MAC Status register */ 662 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 663 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 664 #define BGE_MACSTAT_RX_CFG 0x00000004 665 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 666 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 667 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 668 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 669 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 670 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 671 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 672 #define BGE_MACSTAT_ODI_ERROR 0x02000000 673 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 674 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 675 676 /* MAC Event Enable Register */ 677 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 678 #define BGE_EVTENB_LINK_CHANGED 0x00001000 679 #define BGE_EVTENB_MI_COMPLETE 0x00400000 680 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 681 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 682 #define BGE_EVTENB_ODI_ERROR 0x02000000 683 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 684 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 685 686 /* LED Control Register */ 687 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 688 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 689 #define BGE_LEDCTL_100MBPS_LED 0x00000004 690 #define BGE_LEDCTL_10MBPS_LED 0x00000008 691 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 692 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 693 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 694 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 695 #define BGE_LEDCTL_100MBPS_STS 0x00000100 696 #define BGE_LEDCTL_10MBPS_STS 0x00000200 697 #define BGE_LEDCTL_TRADLED_STS 0x00000400 698 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 699 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 700 701 /* TX backoff seed register */ 702 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 703 704 /* Autopoll status register */ 705 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 706 707 /* Transmit MAC mode register */ 708 #define BGE_TXMODE_RESET 0x00000001 709 #define BGE_TXMODE_ENABLE 0x00000002 710 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 711 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 712 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 713 714 /* Transmit MAC status register */ 715 #define BGE_TXSTAT_RX_XOFFED 0x00000001 716 #define BGE_TXSTAT_SENT_XOFF 0x00000002 717 #define BGE_TXSTAT_SENT_XON 0x00000004 718 #define BGE_TXSTAT_LINK_UP 0x00000008 719 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 720 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 721 722 /* Transmit MAC lengths register */ 723 #define BGE_TXLEN_SLOTTIME 0x000000FF 724 #define BGE_TXLEN_IPG 0x00000F00 725 #define BGE_TXLEN_CRS 0x00003000 726 727 /* Receive MAC mode register */ 728 #define BGE_RXMODE_RESET 0x00000001 729 #define BGE_RXMODE_ENABLE 0x00000002 730 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 731 #define BGE_RXMODE_RX_GIANTS 0x00000020 732 #define BGE_RXMODE_RX_RUNTS 0x00000040 733 #define BGE_RXMODE_8022_LENCHECK 0x00000080 734 #define BGE_RXMODE_RX_PROMISC 0x00000100 735 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 736 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 737 738 /* Receive MAC status register */ 739 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 740 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 741 #define BGE_RXSTAT_RCVD_XON 0x00000004 742 743 /* Receive Rules Control register */ 744 #define BGE_RXRULECTL_OFFSET 0x000000FF 745 #define BGE_RXRULECTL_CLASS 0x00001F00 746 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 747 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 748 #define BGE_RXRULECTL_MAP 0x01000000 749 #define BGE_RXRULECTL_DISCARD 0x02000000 750 #define BGE_RXRULECTL_MASK 0x04000000 751 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 752 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 753 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 754 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 755 756 /* Receive Rules Mask register */ 757 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 758 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 759 760 /* SGDIG config (not documented) */ 761 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 762 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 763 #define BGE_SGDIGCFG_SEND 0x40000000 764 #define BGE_SGDIGCFG_AUTO 0x80000000 765 766 /* SGDIG status (not documented) */ 767 #define BGE_SGDIGSTS_DONE 0x00000002 768 769 /* MI communication register */ 770 #define BGE_MICOMM_DATA 0x0000FFFF 771 #define BGE_MICOMM_REG 0x001F0000 772 #define BGE_MICOMM_PHY 0x03E00000 773 #define BGE_MICOMM_CMD 0x0C000000 774 #define BGE_MICOMM_READFAIL 0x10000000 775 #define BGE_MICOMM_BUSY 0x20000000 776 777 #define BGE_MIREG(x) ((x & 0x1F) << 16) 778 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 779 #define BGE_MICMD_WRITE 0x04000000 780 #define BGE_MICMD_READ 0x08000000 781 782 /* MI status register */ 783 #define BGE_MISTS_LINK 0x00000001 784 #define BGE_MISTS_10MBPS 0x00000002 785 786 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 787 #define BGE_MIMODE_AUTOPOLL 0x00000010 788 #define BGE_MIMODE_CLKCNT 0x001F0000 789 790 791 /* 792 * Send data initiator control registers. 793 */ 794 #define BGE_SDI_MODE 0x0C00 795 #define BGE_SDI_STATUS 0x0C04 796 #define BGE_SDI_STATS_CTL 0x0C08 797 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 798 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 799 #define BGE_LOCSTATS_COS0 0x0C80 800 #define BGE_LOCSTATS_COS1 0x0C84 801 #define BGE_LOCSTATS_COS2 0x0C88 802 #define BGE_LOCSTATS_COS3 0x0C8C 803 #define BGE_LOCSTATS_COS4 0x0C90 804 #define BGE_LOCSTATS_COS5 0x0C84 805 #define BGE_LOCSTATS_COS6 0x0C98 806 #define BGE_LOCSTATS_COS7 0x0C9C 807 #define BGE_LOCSTATS_COS8 0x0CA0 808 #define BGE_LOCSTATS_COS9 0x0CA4 809 #define BGE_LOCSTATS_COS10 0x0CA8 810 #define BGE_LOCSTATS_COS11 0x0CAC 811 #define BGE_LOCSTATS_COS12 0x0CB0 812 #define BGE_LOCSTATS_COS13 0x0CB4 813 #define BGE_LOCSTATS_COS14 0x0CB8 814 #define BGE_LOCSTATS_COS15 0x0CBC 815 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 816 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 817 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 818 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 819 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 820 #define BGE_LOCSTATS_IRQS 0x0CD4 821 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 822 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 823 824 /* Send Data Initiator mode register */ 825 #define BGE_SDIMODE_RESET 0x00000001 826 #define BGE_SDIMODE_ENABLE 0x00000002 827 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 828 829 /* Send Data Initiator stats register */ 830 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 831 832 /* Send Data Initiator stats control register */ 833 #define BGE_SDISTATSCTL_ENABLE 0x00000001 834 #define BGE_SDISTATSCTL_FASTER 0x00000002 835 #define BGE_SDISTATSCTL_CLEAR 0x00000004 836 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 837 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 838 839 /* 840 * Send Data Completion Control registers 841 */ 842 #define BGE_SDC_MODE 0x1000 843 #define BGE_SDC_STATUS 0x1004 844 845 /* Send Data completion mode register */ 846 #define BGE_SDCMODE_RESET 0x00000001 847 #define BGE_SDCMODE_ENABLE 0x00000002 848 #define BGE_SDCMODE_ATTN 0x00000004 849 #define BGE_SDCMODE_CDELAY 0x00000010 850 851 /* Send Data completion status register */ 852 #define BGE_SDCSTAT_ATTN 0x00000004 853 854 /* 855 * Send BD Ring Selector Control registers 856 */ 857 #define BGE_SRS_MODE 0x1400 858 #define BGE_SRS_STATUS 0x1404 859 #define BGE_SRS_HWDIAG 0x1408 860 #define BGE_SRS_LOC_NIC_CONS0 0x1440 861 #define BGE_SRS_LOC_NIC_CONS1 0x1444 862 #define BGE_SRS_LOC_NIC_CONS2 0x1448 863 #define BGE_SRS_LOC_NIC_CONS3 0x144C 864 #define BGE_SRS_LOC_NIC_CONS4 0x1450 865 #define BGE_SRS_LOC_NIC_CONS5 0x1454 866 #define BGE_SRS_LOC_NIC_CONS6 0x1458 867 #define BGE_SRS_LOC_NIC_CONS7 0x145C 868 #define BGE_SRS_LOC_NIC_CONS8 0x1460 869 #define BGE_SRS_LOC_NIC_CONS9 0x1464 870 #define BGE_SRS_LOC_NIC_CONS10 0x1468 871 #define BGE_SRS_LOC_NIC_CONS11 0x146C 872 #define BGE_SRS_LOC_NIC_CONS12 0x1470 873 #define BGE_SRS_LOC_NIC_CONS13 0x1474 874 #define BGE_SRS_LOC_NIC_CONS14 0x1478 875 #define BGE_SRS_LOC_NIC_CONS15 0x147C 876 877 /* Send BD Ring Selector Mode register */ 878 #define BGE_SRSMODE_RESET 0x00000001 879 #define BGE_SRSMODE_ENABLE 0x00000002 880 #define BGE_SRSMODE_ATTN 0x00000004 881 882 /* Send BD Ring Selector Status register */ 883 #define BGE_SRSSTAT_ERROR 0x00000004 884 885 /* Send BD Ring Selector HW Diagnostics register */ 886 #define BGE_SRSHWDIAG_STATE 0x0000000F 887 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 888 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 889 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 890 891 /* 892 * Send BD Initiator Selector Control registers 893 */ 894 #define BGE_SBDI_MODE 0x1800 895 #define BGE_SBDI_STATUS 0x1804 896 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 897 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 898 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 899 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 900 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 901 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 902 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 903 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 904 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 905 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 906 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 907 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 908 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 909 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 910 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 911 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 912 913 /* Send BD Initiator Mode register */ 914 #define BGE_SBDIMODE_RESET 0x00000001 915 #define BGE_SBDIMODE_ENABLE 0x00000002 916 #define BGE_SBDIMODE_ATTN 0x00000004 917 918 /* Send BD Initiator Status register */ 919 #define BGE_SBDISTAT_ERROR 0x00000004 920 921 /* 922 * Send BD Completion Control registers 923 */ 924 #define BGE_SBDC_MODE 0x1C00 925 #define BGE_SBDC_STATUS 0x1C04 926 927 /* Send BD Completion Control Mode register */ 928 #define BGE_SBDCMODE_RESET 0x00000001 929 #define BGE_SBDCMODE_ENABLE 0x00000002 930 #define BGE_SBDCMODE_ATTN 0x00000004 931 932 /* Send BD Completion Control Status register */ 933 #define BGE_SBDCSTAT_ATTN 0x00000004 934 935 /* 936 * Receive List Placement Control registers 937 */ 938 #define BGE_RXLP_MODE 0x2000 939 #define BGE_RXLP_STATUS 0x2004 940 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 941 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 942 #define BGE_RXLP_CFG 0x2010 943 #define BGE_RXLP_STATS_CTL 0x2014 944 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 945 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 946 #define BGE_RXLP_HEAD0 0x2100 947 #define BGE_RXLP_TAIL0 0x2104 948 #define BGE_RXLP_COUNT0 0x2108 949 #define BGE_RXLP_HEAD1 0x2110 950 #define BGE_RXLP_TAIL1 0x2114 951 #define BGE_RXLP_COUNT1 0x2118 952 #define BGE_RXLP_HEAD2 0x2120 953 #define BGE_RXLP_TAIL2 0x2124 954 #define BGE_RXLP_COUNT2 0x2128 955 #define BGE_RXLP_HEAD3 0x2130 956 #define BGE_RXLP_TAIL3 0x2134 957 #define BGE_RXLP_COUNT3 0x2138 958 #define BGE_RXLP_HEAD4 0x2140 959 #define BGE_RXLP_TAIL4 0x2144 960 #define BGE_RXLP_COUNT4 0x2148 961 #define BGE_RXLP_HEAD5 0x2150 962 #define BGE_RXLP_TAIL5 0x2154 963 #define BGE_RXLP_COUNT5 0x2158 964 #define BGE_RXLP_HEAD6 0x2160 965 #define BGE_RXLP_TAIL6 0x2164 966 #define BGE_RXLP_COUNT6 0x2168 967 #define BGE_RXLP_HEAD7 0x2170 968 #define BGE_RXLP_TAIL7 0x2174 969 #define BGE_RXLP_COUNT7 0x2178 970 #define BGE_RXLP_HEAD8 0x2180 971 #define BGE_RXLP_TAIL8 0x2184 972 #define BGE_RXLP_COUNT8 0x2188 973 #define BGE_RXLP_HEAD9 0x2190 974 #define BGE_RXLP_TAIL9 0x2194 975 #define BGE_RXLP_COUNT9 0x2198 976 #define BGE_RXLP_HEAD10 0x21A0 977 #define BGE_RXLP_TAIL10 0x21A4 978 #define BGE_RXLP_COUNT10 0x21A8 979 #define BGE_RXLP_HEAD11 0x21B0 980 #define BGE_RXLP_TAIL11 0x21B4 981 #define BGE_RXLP_COUNT11 0x21B8 982 #define BGE_RXLP_HEAD12 0x21C0 983 #define BGE_RXLP_TAIL12 0x21C4 984 #define BGE_RXLP_COUNT12 0x21C8 985 #define BGE_RXLP_HEAD13 0x21D0 986 #define BGE_RXLP_TAIL13 0x21D4 987 #define BGE_RXLP_COUNT13 0x21D8 988 #define BGE_RXLP_HEAD14 0x21E0 989 #define BGE_RXLP_TAIL14 0x21E4 990 #define BGE_RXLP_COUNT14 0x21E8 991 #define BGE_RXLP_HEAD15 0x21F0 992 #define BGE_RXLP_TAIL15 0x21F4 993 #define BGE_RXLP_COUNT15 0x21F8 994 #define BGE_RXLP_LOCSTAT_COS0 0x2200 995 #define BGE_RXLP_LOCSTAT_COS1 0x2204 996 #define BGE_RXLP_LOCSTAT_COS2 0x2208 997 #define BGE_RXLP_LOCSTAT_COS3 0x220C 998 #define BGE_RXLP_LOCSTAT_COS4 0x2210 999 #define BGE_RXLP_LOCSTAT_COS5 0x2214 1000 #define BGE_RXLP_LOCSTAT_COS6 0x2218 1001 #define BGE_RXLP_LOCSTAT_COS7 0x221C 1002 #define BGE_RXLP_LOCSTAT_COS8 0x2220 1003 #define BGE_RXLP_LOCSTAT_COS9 0x2224 1004 #define BGE_RXLP_LOCSTAT_COS10 0x2228 1005 #define BGE_RXLP_LOCSTAT_COS11 0x222C 1006 #define BGE_RXLP_LOCSTAT_COS12 0x2230 1007 #define BGE_RXLP_LOCSTAT_COS13 0x2234 1008 #define BGE_RXLP_LOCSTAT_COS14 0x2238 1009 #define BGE_RXLP_LOCSTAT_COS15 0x223C 1010 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1011 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1012 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1013 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1014 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1015 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1016 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1017 1018 1019 /* Receive List Placement mode register */ 1020 #define BGE_RXLPMODE_RESET 0x00000001 1021 #define BGE_RXLPMODE_ENABLE 0x00000002 1022 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1023 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1024 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1025 1026 /* Receive List Placement Status register */ 1027 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1028 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1029 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1030 1031 /* 1032 * Receive Data and Receive BD Initiator Control Registers 1033 */ 1034 #define BGE_RDBDI_MODE 0x2400 1035 #define BGE_RDBDI_STATUS 0x2404 1036 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1037 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1038 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1039 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1040 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1041 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1042 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1043 #define BGE_RX_STD_RCB_NICADDR 0x245C 1044 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1045 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1046 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1047 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1048 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1049 #define BGE_RDBDI_STD_RX_CONS 0x2474 1050 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1051 #define BGE_RDBDI_RETURN_PROD0 0x2480 1052 #define BGE_RDBDI_RETURN_PROD1 0x2484 1053 #define BGE_RDBDI_RETURN_PROD2 0x2488 1054 #define BGE_RDBDI_RETURN_PROD3 0x248C 1055 #define BGE_RDBDI_RETURN_PROD4 0x2490 1056 #define BGE_RDBDI_RETURN_PROD5 0x2494 1057 #define BGE_RDBDI_RETURN_PROD6 0x2498 1058 #define BGE_RDBDI_RETURN_PROD7 0x249C 1059 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1060 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1061 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1062 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1063 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1064 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1065 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1066 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1067 #define BGE_RDBDI_HWDIAG 0x24C0 1068 1069 1070 /* Receive Data and Receive BD Initiator Mode register */ 1071 #define BGE_RDBDIMODE_RESET 0x00000001 1072 #define BGE_RDBDIMODE_ENABLE 0x00000002 1073 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1074 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1075 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1076 1077 /* Receive Data and Receive BD Initiator Status register */ 1078 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1079 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1080 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1081 1082 1083 /* 1084 * Receive Data Completion Control registers 1085 */ 1086 #define BGE_RDC_MODE 0x2800 1087 1088 /* Receive Data Completion Mode register */ 1089 #define BGE_RDCMODE_RESET 0x00000001 1090 #define BGE_RDCMODE_ENABLE 0x00000002 1091 #define BGE_RDCMODE_ATTN 0x00000004 1092 1093 /* 1094 * Receive BD Initiator Control registers 1095 */ 1096 #define BGE_RBDI_MODE 0x2C00 1097 #define BGE_RBDI_STATUS 0x2C04 1098 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1099 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1100 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1101 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1102 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1103 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1104 1105 #define BGE_STD_REPL_LWM 0x2D00 1106 #define BGE_JUMBO_REPL_LWM 0x2D04 1107 1108 /* Receive BD Initiator Mode register */ 1109 #define BGE_RBDIMODE_RESET 0x00000001 1110 #define BGE_RBDIMODE_ENABLE 0x00000002 1111 #define BGE_RBDIMODE_ATTN 0x00000004 1112 1113 /* Receive BD Initiator Status register */ 1114 #define BGE_RBDISTAT_ATTN 0x00000004 1115 1116 /* 1117 * Receive BD Completion Control registers 1118 */ 1119 #define BGE_RBDC_MODE 0x3000 1120 #define BGE_RBDC_STATUS 0x3004 1121 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1122 #define BGE_RBDC_STD_BD_PROD 0x300C 1123 #define BGE_RBDC_MINI_BD_PROD 0x3010 1124 1125 /* Receive BD completion mode register */ 1126 #define BGE_RBDCMODE_RESET 0x00000001 1127 #define BGE_RBDCMODE_ENABLE 0x00000002 1128 #define BGE_RBDCMODE_ATTN 0x00000004 1129 1130 /* Receive BD completion status register */ 1131 #define BGE_RBDCSTAT_ERROR 0x00000004 1132 1133 /* 1134 * Receive List Selector Control registers 1135 */ 1136 #define BGE_RXLS_MODE 0x3400 1137 #define BGE_RXLS_STATUS 0x3404 1138 1139 /* Receive List Selector Mode register */ 1140 #define BGE_RXLSMODE_RESET 0x00000001 1141 #define BGE_RXLSMODE_ENABLE 0x00000002 1142 #define BGE_RXLSMODE_ATTN 0x00000004 1143 1144 /* Receive List Selector Status register */ 1145 #define BGE_RXLSSTAT_ERROR 0x00000004 1146 1147 /* 1148 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1149 */ 1150 #define BGE_MBCF_MODE 0x3800 1151 #define BGE_MBCF_STATUS 0x3804 1152 1153 /* Mbuf Cluster Free mode register */ 1154 #define BGE_MBCFMODE_RESET 0x00000001 1155 #define BGE_MBCFMODE_ENABLE 0x00000002 1156 #define BGE_MBCFMODE_ATTN 0x00000004 1157 1158 /* Mbuf Cluster Free status register */ 1159 #define BGE_MBCFSTAT_ERROR 0x00000004 1160 1161 /* 1162 * Host Coalescing Control registers 1163 */ 1164 #define BGE_HCC_MODE 0x3C00 1165 #define BGE_HCC_STATUS 0x3C04 1166 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1167 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1168 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1169 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1170 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1171 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1172 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1173 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1174 #define BGE_HCC_STATS_TICKS 0x3C28 1175 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1176 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1177 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1178 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1179 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1180 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1181 #define BGE_FLOW_ATTN 0x3C48 1182 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1183 #define BGE_HCC_STD_BD_CONS 0x3C54 1184 #define BGE_HCC_MINI_BD_CONS 0x3C58 1185 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1186 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1187 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1188 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1189 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1190 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1191 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1192 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1193 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1194 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1195 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1196 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1197 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1198 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1199 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1200 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1201 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1202 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1203 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1204 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1205 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1206 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1207 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1208 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1209 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1210 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1211 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1212 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1213 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1214 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1215 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1216 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1217 1218 1219 /* Host coalescing mode register */ 1220 #define BGE_HCCMODE_RESET 0x00000001 1221 #define BGE_HCCMODE_ENABLE 0x00000002 1222 #define BGE_HCCMODE_ATTN 0x00000004 1223 #define BGE_HCCMODE_COAL_NOW 0x00000008 1224 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1225 #define BGE_HCCMODE_64BYTE 0x00000080 1226 #define BGE_HCCMODE_32BYTE 0x00000100 1227 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1228 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1229 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1230 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1231 1232 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1233 1234 #define BGE_STATBLKSZ_FULL 0x00000000 1235 #define BGE_STATBLKSZ_64BYTE 0x00000080 1236 #define BGE_STATBLKSZ_32BYTE 0x00000100 1237 1238 /* Host coalescing status register */ 1239 #define BGE_HCCSTAT_ERROR 0x00000004 1240 1241 /* Flow attention register */ 1242 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1243 #define BGE_FLOWATTN_MEMARB 0x00000080 1244 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1245 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1246 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1247 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1248 #define BGE_FLOWATTN_RDBDI 0x00080000 1249 #define BGE_FLOWATTN_RXLS 0x00100000 1250 #define BGE_FLOWATTN_RXLP 0x00200000 1251 #define BGE_FLOWATTN_RBDC 0x00400000 1252 #define BGE_FLOWATTN_RBDI 0x00800000 1253 #define BGE_FLOWATTN_SDC 0x08000000 1254 #define BGE_FLOWATTN_SDI 0x10000000 1255 #define BGE_FLOWATTN_SRS 0x20000000 1256 #define BGE_FLOWATTN_SBDC 0x40000000 1257 #define BGE_FLOWATTN_SBDI 0x80000000 1258 1259 /* 1260 * Memory arbiter registers 1261 */ 1262 #define BGE_MARB_MODE 0x4000 1263 #define BGE_MARB_STATUS 0x4004 1264 #define BGE_MARB_TRAPADDR_HI 0x4008 1265 #define BGE_MARB_TRAPADDR_LO 0x400C 1266 1267 /* Memory arbiter mode register */ 1268 #define BGE_MARBMODE_RESET 0x00000001 1269 #define BGE_MARBMODE_ENABLE 0x00000002 1270 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1271 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1272 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1273 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1274 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1275 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1276 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1277 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1278 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1279 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1280 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1281 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1282 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1283 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1284 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1285 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1286 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1287 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1288 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1289 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1290 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1291 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1292 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1293 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1294 1295 /* Memory arbiter status register */ 1296 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1297 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1298 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1299 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1300 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1301 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1302 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1303 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1304 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1305 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1306 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1307 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1308 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1309 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1310 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1311 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1312 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1313 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1314 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1315 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1316 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1317 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1318 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1319 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1320 1321 /* 1322 * Buffer manager control registers 1323 */ 1324 #define BGE_BMAN_MODE 0x4400 1325 #define BGE_BMAN_STATUS 0x4404 1326 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1327 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1328 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1329 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1330 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1331 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1332 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1333 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1334 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1335 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1336 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1337 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1338 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1339 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1340 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1341 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1342 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1343 #define BGE_BMAN_HWDIAG_1 0x444C 1344 #define BGE_BMAN_HWDIAG_2 0x4450 1345 #define BGE_BMAN_HWDIAG_3 0x4454 1346 1347 /* Buffer manager mode register */ 1348 #define BGE_BMANMODE_RESET 0x00000001 1349 #define BGE_BMANMODE_ENABLE 0x00000002 1350 #define BGE_BMANMODE_ATTN 0x00000004 1351 #define BGE_BMANMODE_TESTMODE 0x00000008 1352 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1353 1354 /* Buffer manager status register */ 1355 #define BGE_BMANSTAT_ERRO 0x00000004 1356 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1357 1358 1359 /* 1360 * Read DMA Control registers 1361 */ 1362 #define BGE_RDMA_MODE 0x4800 1363 #define BGE_RDMA_STATUS 0x4804 1364 1365 /* Read DMA mode register */ 1366 #define BGE_RDMAMODE_RESET 0x00000001 1367 #define BGE_RDMAMODE_ENABLE 0x00000002 1368 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1369 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1370 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1371 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1372 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1373 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1374 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1375 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1376 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1377 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1378 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1379 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1380 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1381 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1382 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1383 #define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1384 1385 /* Alternate encodings for PCI-Express, from Broadcom-supplied Linux driver */ 1386 #define BGE_RDMA_MODE_FIFO_LONG_BURST ((1<<17) | (1 << 16)) 1387 #define BGE_RDMA_MODE_FIFO_SIZE_128 (1 << 17) 1388 1389 /* Read DMA status register */ 1390 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1391 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1392 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1393 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1394 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1395 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1396 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1397 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1398 1399 /* 1400 * Write DMA control registers 1401 */ 1402 #define BGE_WDMA_MODE 0x4C00 1403 #define BGE_WDMA_STATUS 0x4C04 1404 1405 /* Write DMA mode register */ 1406 #define BGE_WDMAMODE_RESET 0x00000001 1407 #define BGE_WDMAMODE_ENABLE 0x00000002 1408 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1409 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1410 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1411 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1412 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1413 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1414 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1415 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1416 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1417 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1418 1419 /* Write DMA status register */ 1420 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1421 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1422 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1423 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1424 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1425 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1426 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1427 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1428 1429 1430 /* 1431 * RX CPU registers 1432 */ 1433 #define BGE_RXCPU_MODE 0x5000 1434 #define BGE_RXCPU_STATUS 0x5004 1435 #define BGE_RXCPU_PC 0x501C 1436 1437 /* RX CPU mode register */ 1438 #define BGE_RXCPUMODE_RESET 0x00000001 1439 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1440 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1441 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1442 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1443 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1444 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1445 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1446 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1447 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1448 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1449 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1450 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1451 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1452 1453 /* RX CPU status register */ 1454 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1455 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1456 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1457 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1458 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1459 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1460 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1461 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1462 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1463 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1464 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1465 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1466 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1467 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1468 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1469 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1470 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1471 1472 /* 1473 * V? CPU registers 1474 */ 1475 #define BGE_VCPU_STATUS 0x5100 1476 #define BGE_VCPU_EXT_CTRL 0x6890 1477 1478 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1479 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1480 1481 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1482 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1483 1484 /* 1485 * TX CPU registers 1486 */ 1487 #define BGE_TXCPU_MODE 0x5400 1488 #define BGE_TXCPU_STATUS 0x5404 1489 #define BGE_TXCPU_PC 0x541C 1490 1491 /* TX CPU mode register */ 1492 #define BGE_TXCPUMODE_RESET 0x00000001 1493 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1494 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1495 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1496 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1497 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1498 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1499 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1500 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1501 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1502 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1503 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1504 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1505 1506 /* TX CPU status register */ 1507 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1508 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1509 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1510 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1511 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1512 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1513 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1514 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1515 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1516 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1517 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1518 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1519 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1520 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1521 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1522 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1523 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1524 1525 1526 /* 1527 * Low priority mailbox registers 1528 */ 1529 #define BGE_LPMBX_IRQ0_HI 0x5800 1530 #define BGE_LPMBX_IRQ0_LO 0x5804 1531 #define BGE_LPMBX_IRQ1_HI 0x5808 1532 #define BGE_LPMBX_IRQ1_LO 0x580C 1533 #define BGE_LPMBX_IRQ2_HI 0x5810 1534 #define BGE_LPMBX_IRQ2_LO 0x5814 1535 #define BGE_LPMBX_IRQ3_HI 0x5818 1536 #define BGE_LPMBX_IRQ3_LO 0x581C 1537 #define BGE_LPMBX_GEN0_HI 0x5820 1538 #define BGE_LPMBX_GEN0_LO 0x5824 1539 #define BGE_LPMBX_GEN1_HI 0x5828 1540 #define BGE_LPMBX_GEN1_LO 0x582C 1541 #define BGE_LPMBX_GEN2_HI 0x5830 1542 #define BGE_LPMBX_GEN2_LO 0x5834 1543 #define BGE_LPMBX_GEN3_HI 0x5828 1544 #define BGE_LPMBX_GEN3_LO 0x582C 1545 #define BGE_LPMBX_GEN4_HI 0x5840 1546 #define BGE_LPMBX_GEN4_LO 0x5844 1547 #define BGE_LPMBX_GEN5_HI 0x5848 1548 #define BGE_LPMBX_GEN5_LO 0x584C 1549 #define BGE_LPMBX_GEN6_HI 0x5850 1550 #define BGE_LPMBX_GEN6_LO 0x5854 1551 #define BGE_LPMBX_GEN7_HI 0x5858 1552 #define BGE_LPMBX_GEN7_LO 0x585C 1553 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1554 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1555 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1556 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1557 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1558 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1559 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1560 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1561 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1562 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1563 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1564 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1565 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1566 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1567 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1568 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1569 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1570 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1571 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1572 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1573 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1574 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1575 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1576 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1577 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1578 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1579 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1580 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1581 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1582 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1583 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1584 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1585 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1586 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1587 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1588 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1589 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1590 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1591 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1592 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1593 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1594 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1595 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1596 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1597 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1598 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1599 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1600 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1601 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1602 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1603 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1604 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1605 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1606 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1607 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1608 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1609 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1610 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1611 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1612 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1613 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1614 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1615 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1616 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1617 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1618 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1619 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1620 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1621 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1622 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1623 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1624 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1625 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1626 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1627 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1628 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1629 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1630 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1631 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1632 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1633 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1634 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1635 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1636 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1637 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1638 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1639 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1640 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1641 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1642 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1643 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1644 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1645 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1646 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1647 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1648 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1649 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1650 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1651 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1652 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1653 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1654 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1655 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1656 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1657 1658 /* 1659 * Flow throw Queue reset register 1660 */ 1661 #define BGE_FTQ_RESET 0x5C00 1662 1663 #define BGE_FTQRESET_DMAREAD 0x00000002 1664 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1665 #define BGE_FTQRESET_DMADONE 0x00000010 1666 #define BGE_FTQRESET_SBDC 0x00000020 1667 #define BGE_FTQRESET_SDI 0x00000040 1668 #define BGE_FTQRESET_WDMA 0x00000080 1669 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1670 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1671 #define BGE_FTQRESET_SDC 0x00000400 1672 #define BGE_FTQRESET_HCC 0x00000800 1673 #define BGE_FTQRESET_TXFIFO 0x00001000 1674 #define BGE_FTQRESET_MBC 0x00002000 1675 #define BGE_FTQRESET_RBDC 0x00004000 1676 #define BGE_FTQRESET_RXLP 0x00008000 1677 #define BGE_FTQRESET_RDBDI 0x00010000 1678 #define BGE_FTQRESET_RDC 0x00020000 1679 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1680 1681 /* 1682 * Message Signaled Interrupt registers 1683 */ 1684 #define BGE_MSI_MODE 0x6000 1685 #define BGE_MSI_STATUS 0x6004 1686 #define BGE_MSI_FIFOACCESS 0x6008 1687 1688 /* MSI mode register */ 1689 #define BGE_MSIMODE_RESET 0x00000001 1690 #define BGE_MSIMODE_ENABLE 0x00000002 1691 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1692 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1693 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1694 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1695 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1696 1697 /* MSI status register */ 1698 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1699 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1700 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1701 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1702 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1703 1704 1705 /* 1706 * DMA Completion registers 1707 */ 1708 #define BGE_DMAC_MODE 0x6400 1709 1710 /* DMA Completion mode register */ 1711 #define BGE_DMACMODE_RESET 0x00000001 1712 #define BGE_DMACMODE_ENABLE 0x00000002 1713 1714 1715 /* 1716 * General control registers. 1717 */ 1718 #define BGE_MODE_CTL 0x6800 1719 #define BGE_MISC_CFG 0x6804 1720 #define BGE_MISC_LOCAL_CTL 0x6808 1721 #define BGE_MISC_TIMER 0x680c 1722 #define BGE_EE_ADDR 0x6838 1723 #define BGE_EE_DATA 0x683C 1724 #define BGE_EE_CTL 0x6840 1725 #define BGE_MDI_CTL 0x6844 1726 #define BGE_EE_DELAY 0x6848 1727 #define BGE_FASTBOOT_PC 0x6894 1728 /* 1729 * XXX: Those names are made up as I have no documentation about it; 1730 * I only know it is only used in the PCI-Express case. 1731 */ 1732 #define BGE_PCIE_CTL0 0x7c00 1733 #define BGE_PCIE_CTL1 0x7e2c 1734 1735 /* 1736 * NVRAM Control registers 1737 */ 1738 #define BGE_NVRAM_CMD 0x7000 1739 #define BGE_NVRAM_STAT 0x7004 1740 #define BGE_NVRAM_WRDATA 0x7008 1741 #define BGE_NVRAM_ADDR 0x700c 1742 #define BGE_NVRAM_RDDATA 0x7010 1743 #define BGE_NVRAM_CFG1 0x7014 1744 #define BGE_NVRAM_CFG2 0x7018 1745 #define BGE_NVRAM_CFG3 0x701c 1746 #define BGE_NVRAM_SWARB 0x7020 1747 #define BGE_NVRAM_ACCESS 0x7024 1748 #define BGE_NVRAM_WRITE1 0x7028 1749 1750 #define BGE_NVRAMCMD_RESET 0x00000001 1751 #define BGE_NVRAMCMD_DONE 0x00000008 1752 #define BGE_NVRAMCMD_START 0x00000010 1753 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1754 #define BGE_NVRAMCMD_ERASE 0x00000040 1755 #define BGE_NVRAMCMD_FIRST 0x00000080 1756 #define BGE_NVRAMCMD_LAST 0x00000100 1757 1758 #define BGE_NVRAM_READCMD \ 1759 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1760 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1761 #define BGE_NVRAM_WRITECMD \ 1762 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1763 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1764 1765 #define BGE_NVRAMSWARB_SET0 0x00000001 1766 #define BGE_NVRAMSWARB_SET1 0x00000002 1767 #define BGE_NVRAMSWARB_SET2 0x00000003 1768 #define BGE_NVRAMSWARB_SET3 0x00000004 1769 #define BGE_NVRAMSWARB_CLR0 0x00000010 1770 #define BGE_NVRAMSWARB_CLR1 0x00000020 1771 #define BGE_NVRAMSWARB_CLR2 0x00000040 1772 #define BGE_NVRAMSWARB_CLR3 0x00000080 1773 #define BGE_NVRAMSWARB_GNT0 0x00000100 1774 #define BGE_NVRAMSWARB_GNT1 0x00000200 1775 #define BGE_NVRAMSWARB_GNT2 0x00000400 1776 #define BGE_NVRAMSWARB_GNT3 0x00000800 1777 #define BGE_NVRAMSWARB_REQ0 0x00001000 1778 #define BGE_NVRAMSWARB_REQ1 0x00002000 1779 #define BGE_NVRAMSWARB_REQ2 0x00004000 1780 #define BGE_NVRAMSWARB_REQ3 0x00008000 1781 1782 #define BGE_NVRAMACC_ENABLE 0x00000001 1783 #define BGE_NVRAMACC_WRENABLE 0x00000002 1784 1785 /* 1786 * TLP Control Register 1787 * Applicable to BCM5721 and BCM5751 only 1788 */ 1789 #define BGE_TLP_CONTROL_REG 0x7c00 1790 #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1791 1792 /* 1793 * PHY Test Control Register 1794 * Applicable to BCM5721 and BCM5751 only 1795 */ 1796 #define BGE_PHY_TEST_CTRL_REG 0x7e2c 1797 #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1798 #define BGE_PHY_PCIE_LTASS_MODE 0x0040 1799 1800 1801 1802 /* Mode control register */ 1803 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1804 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1805 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1806 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1807 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1808 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1809 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1810 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1811 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1812 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1813 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1814 #define BGE_MODECTL_STACKUP 0x00010000 1815 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1816 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1817 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1818 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1819 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1820 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1821 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1822 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1823 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1824 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1825 1826 /* Misc. config register */ 1827 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1828 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1829 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1830 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1831 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 1832 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1833 #define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 1834 1835 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1836 1837 /* Misc. Local Control */ 1838 #define BGE_MLC_INTR_STATE 0x00000001 1839 #define BGE_MLC_INTR_CLR 0x00000002 1840 #define BGE_MLC_INTR_SET 0x00000004 1841 #define BGE_MLC_INTR_ONATTN 0x00000008 1842 #define BGE_MLC_MISCIO_IN0 0x00000100 1843 #define BGE_MLC_MISCIO_IN1 0x00000200 1844 #define BGE_MLC_MISCIO_IN2 0x00000400 1845 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1846 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1847 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1848 #define BGE_MLC_MISCIO_OUT0 0x00004000 1849 #define BGE_MLC_MISCIO_OUT1 0x00008000 1850 #define BGE_MLC_MISCIO_OUT2 0x00010000 1851 #define BGE_MLC_EXTRAM_ENB 0x00020000 1852 #define BGE_MLC_SRAM_SIZE 0x001C0000 1853 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1854 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1855 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1856 #define BGE_MLC_AUTO_EEPROM 0x01000000 1857 1858 #define BGE_SSRAMSIZE_256KB 0x00000000 1859 #define BGE_SSRAMSIZE_512KB 0x00040000 1860 #define BGE_SSRAMSIZE_1MB 0x00080000 1861 #define BGE_SSRAMSIZE_2MB 0x000C0000 1862 #define BGE_SSRAMSIZE_4MB 0x00100000 1863 #define BGE_SSRAMSIZE_8MB 0x00140000 1864 #define BGE_SSRAMSIZE_16M 0x00180000 1865 1866 /* EEPROM address register */ 1867 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1868 #define BGE_EEADDR_HALFCLK 0x01FF0000 1869 #define BGE_EEADDR_START 0x02000000 1870 #define BGE_EEADDR_DEVID 0x1C000000 1871 #define BGE_EEADDR_RESET 0x20000000 1872 #define BGE_EEADDR_DONE 0x40000000 1873 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1874 1875 #define BGE_EEDEVID(x) ((x & 7) << 26) 1876 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1877 #define BGE_HALFCLK_384SCL 0x60 1878 #define BGE_EE_READCMD \ 1879 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1880 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1881 #define BGE_EE_WRCMD \ 1882 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1883 BGE_EEADDR_START|BGE_EEADDR_DONE) 1884 1885 /* EEPROM Control register */ 1886 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1887 #define BGE_EECTL_CLKOUT 0x00000002 1888 #define BGE_EECTL_CLKIN 0x00000004 1889 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1890 #define BGE_EECTL_DATAOUT 0x00000010 1891 #define BGE_EECTL_DATAIN 0x00000020 1892 1893 /* MDI (MII/GMII) access register */ 1894 #define BGE_MDI_DATA 0x00000001 1895 #define BGE_MDI_DIR 0x00000002 1896 #define BGE_MDI_SEL 0x00000004 1897 #define BGE_MDI_CLK 0x00000008 1898 1899 #define BGE_MEMWIN_START 0x00008000 1900 #define BGE_MEMWIN_END 0x0000FFFF 1901 1902 1903 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1904 do { \ 1905 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1906 (0xFFFF0000 & x)); \ 1907 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1908 } while(0) 1909 1910 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 1911 do { \ 1912 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 1913 (0xFFFF0000 & x)); \ 1914 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1915 } while(0) 1916 1917 /* 1918 * This magic number is used to prevent PXE restart when we 1919 * issue a software reset. We write this magic number to the 1920 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1921 * code from running. 1922 */ 1923 #define BGE_MAGIC_NUMBER 0x4B657654 1924 1925 typedef struct { 1926 volatile u_int32_t bge_addr_hi; 1927 volatile u_int32_t bge_addr_lo; 1928 } bge_hostaddr; 1929 1930 /* Ring control block structure */ 1931 struct bge_rcb { 1932 bge_hostaddr bge_hostaddr; 1933 volatile u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 1934 volatile u_int32_t bge_nicaddr; 1935 }; 1936 1937 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1938 1939 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1940 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1941 1942 struct bge_tx_bd { 1943 bge_hostaddr bge_addr; 1944 #if BYTE_ORDER == BIG_ENDIAN 1945 volatile u_int16_t bge_len; 1946 volatile u_int16_t bge_flags; 1947 volatile u_int16_t bge_rsvd; 1948 volatile u_int16_t bge_vlan_tag; 1949 #else 1950 volatile u_int16_t bge_flags; 1951 volatile u_int16_t bge_len; 1952 volatile u_int16_t bge_vlan_tag; 1953 volatile u_int16_t bge_rsvd; 1954 #endif 1955 }; 1956 1957 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1958 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1959 #define BGE_TXBDFLAG_END 0x0004 1960 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1961 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1962 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1963 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1964 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1965 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1966 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1967 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1968 #define BGE_TXBDFLAG_NO_CRC 0x8000 1969 1970 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1971 BGE_SEND_RING_1_TO_4 + \ 1972 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1973 1974 struct bge_rx_bd { 1975 bge_hostaddr bge_addr; 1976 #if BYTE_ORDER == BIG_ENDIAN 1977 volatile u_int16_t bge_idx; 1978 volatile u_int16_t bge_len; 1979 volatile u_int16_t bge_type; 1980 volatile u_int16_t bge_flags; 1981 volatile u_int16_t bge_ip_csum; 1982 volatile u_int16_t bge_tcp_udp_csum; 1983 volatile u_int16_t bge_error_flag; 1984 volatile u_int16_t bge_vlan_tag; 1985 #else 1986 volatile u_int16_t bge_len; 1987 volatile u_int16_t bge_idx; 1988 volatile u_int16_t bge_flags; 1989 volatile u_int16_t bge_type; 1990 volatile u_int16_t bge_tcp_udp_csum; 1991 volatile u_int16_t bge_ip_csum; 1992 volatile u_int16_t bge_vlan_tag; 1993 volatile u_int16_t bge_error_flag; 1994 #endif 1995 volatile u_int32_t bge_rsvd; 1996 volatile u_int32_t bge_opaque; 1997 }; 1998 1999 #define BGE_RXBDFLAG_END 0x0004 2000 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 2001 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 2002 #define BGE_RXBDFLAG_ERROR 0x0400 2003 #define BGE_RXBDFLAG_MINI_RING 0x0800 2004 #define BGE_RXBDFLAG_IP_CSUM 0x1000 2005 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2006 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2007 2008 #define BGE_RXERRFLAG_BAD_CRC 0x0001 2009 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 2010 #define BGE_RXERRFLAG_LINK_LOST 0x0004 2011 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2012 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 2013 #define BGE_RXERRFLAG_RUNT 0x0020 2014 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2015 #define BGE_RXERRFLAG_GIANT 0x0080 2016 2017 struct bge_sts_idx { 2018 #if BYTE_ORDER == BIG_ENDIAN 2019 volatile u_int16_t bge_tx_cons_idx; 2020 volatile u_int16_t bge_rx_prod_idx; 2021 #else 2022 volatile u_int16_t bge_rx_prod_idx; 2023 volatile u_int16_t bge_tx_cons_idx; 2024 #endif 2025 }; 2026 2027 struct bge_status_block { 2028 volatile u_int32_t bge_status; 2029 volatile u_int32_t bge_rsvd0; 2030 #if BYTE_ORDER == BIG_ENDIAN 2031 volatile u_int16_t bge_rx_std_cons_idx; 2032 volatile u_int16_t bge_rx_jumbo_cons_idx; 2033 volatile u_int16_t bge_rsvd1; 2034 volatile u_int16_t bge_rx_mini_cons_idx; 2035 #else 2036 volatile u_int16_t bge_rx_jumbo_cons_idx; 2037 volatile u_int16_t bge_rx_std_cons_idx; 2038 volatile u_int16_t bge_rx_mini_cons_idx; 2039 volatile u_int16_t bge_rsvd1; 2040 #endif 2041 struct bge_sts_idx bge_idx[16]; 2042 }; 2043 2044 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2045 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2046 2047 #define BGE_STATFLAG_UPDATED 0x00000001 2048 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2049 #define BGE_STATFLAG_ERROR 0x00000004 2050 2051 2052 /* 2053 * Broadcom Vendor ID 2054 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2055 * even though they're now manufactured by Broadcom) 2056 */ 2057 #define BCOM_VENDORID 0x14E4 2058 #define BCOM_DEVICEID_BCM5700 0x1644 2059 #define BCOM_DEVICEID_BCM5701 0x1645 2060 #define BCOM_DEVICEID_BCM5789 0x169d 2061 2062 /* 2063 * Alteon AceNIC PCI vendor/device ID. 2064 */ 2065 #define ALT_VENDORID 0x12AE 2066 #define ALT_DEVICEID_ACENIC 0x0001 2067 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 2068 #define ALT_DEVICEID_BCM5700 0x0003 2069 #define ALT_DEVICEID_BCM5701 0x0004 2070 2071 /* 2072 * 3Com 3c985 PCI vendor/device ID. 2073 */ 2074 #define TC_VENDORID 0x10B7 2075 #define TC_DEVICEID_3C985 0x0001 2076 #define TC_DEVICEID_3C996 0x0003 2077 2078 /* 2079 * SysKonnect PCI vendor ID 2080 */ 2081 #define SK_VENDORID 0x1148 2082 #define SK_DEVICEID_ALTIMA 0x4400 2083 #define SK_SUBSYSID_9D21 0x4421 2084 #define SK_SUBSYSID_9D41 0x4441 2085 2086 /* 2087 * Altima PCI vendor/device ID. 2088 */ 2089 #define ALTIMA_VENDORID 0x173b 2090 #define ALTIMA_DEVICE_AC1000 0x03e8 2091 2092 /* 2093 * Offset of MAC address inside EEPROM. 2094 */ 2095 #define BGE_EE_MAC_OFFSET 0x7C 2096 #define BGE_EE_MAC_OFFSET_5906 0x10 2097 #define BGE_EE_HWCFG_OFFSET 0xC8 2098 2099 #define BGE_HWCFG_VOLTAGE 0x00000003 2100 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2101 #define BGE_HWCFG_MEDIA 0x00000030 2102 2103 #define BGE_VOLTAGE_1POINT3 0x00000000 2104 #define BGE_VOLTAGE_1POINT8 0x00000001 2105 2106 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2107 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2108 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2109 2110 #define BGE_MEDIA_UNSPEC 0x00000000 2111 #define BGE_MEDIA_COPPER 0x00000010 2112 #define BGE_MEDIA_FIBER 0x00000020 2113 2114 #define BGE_PCI_READ_CMD 0x06000000 2115 #define BGE_PCI_WRITE_CMD 0x70000000 2116 2117 #define BGE_TICKS_PER_SEC 1000000 2118 2119 /* 2120 * Ring size constants. 2121 */ 2122 #define BGE_EVENT_RING_CNT 256 2123 #define BGE_CMD_RING_CNT 64 2124 #define BGE_STD_RX_RING_CNT 512 2125 #define BGE_JUMBO_RX_RING_CNT 256 2126 #define BGE_MINI_RX_RING_CNT 1024 2127 #define BGE_RETURN_RING_CNT 1024 2128 #define BGE_RETURN_RING_CNT_5705 512 2129 2130 /* 2131 * Possible TX ring sizes. 2132 */ 2133 #define BGE_TX_RING_CNT_128 128 2134 #define BGE_TX_RING_BASE_128 0x3800 2135 2136 #define BGE_TX_RING_CNT_256 256 2137 #define BGE_TX_RING_BASE_256 0x3000 2138 2139 #define BGE_TX_RING_CNT_512 512 2140 #define BGE_TX_RING_BASE_512 0x2000 2141 2142 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2143 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2144 2145 /* 2146 * Tigon III statistics counters. 2147 */ 2148 2149 /* Stats counters access through registers */ 2150 struct bge_mac_stats_regs { 2151 u_int32_t ifHCOutOctets; 2152 u_int32_t Reserved0; 2153 u_int32_t etherStatsCollisions; 2154 u_int32_t outXonSent; 2155 u_int32_t outXoffSent; 2156 u_int32_t Reserved1; 2157 u_int32_t dot3StatsInternalMacTransmitErrors; 2158 u_int32_t dot3StatsSingleCollisionFrames; 2159 u_int32_t dot3StatsMultipleCollisionFrames; 2160 u_int32_t dot3StatsDeferredTransmissions; 2161 u_int32_t Reserved2; 2162 u_int32_t dot3StatsExcessiveCollisions; 2163 u_int32_t dot3StatsLateCollisions; 2164 u_int32_t Reserved3[14]; 2165 u_int32_t ifHCOutUcastPkts; 2166 u_int32_t ifHCOutMulticastPkts; 2167 u_int32_t ifHCOutBroadcastPkts; 2168 u_int32_t Reserved4[2]; 2169 u_int32_t ifHCInOctets; 2170 u_int32_t Reserved5; 2171 u_int32_t etherStatsFragments; 2172 u_int32_t ifHCInUcastPkts; 2173 u_int32_t ifHCInMulticastPkts; 2174 u_int32_t ifHCInBroadcastPkts; 2175 u_int32_t dot3StatsFCSErrors; 2176 u_int32_t dot3StatsAlignmentErrors; 2177 u_int32_t xonPauseFramesReceived; 2178 u_int32_t xoffPauseFramesReceived; 2179 u_int32_t macControlFramesReceived; 2180 u_int32_t xoffStateEntered; 2181 u_int32_t dot3StatsFramesTooLong; 2182 u_int32_t etherStatsJabbers; 2183 u_int32_t etherStatsUndersizePkts; 2184 }; 2185 2186 struct bge_stats { 2187 u_int8_t Reserved0[256]; 2188 2189 /* Statistics maintained by Receive MAC. */ 2190 bge_hostaddr ifHCInOctets; 2191 bge_hostaddr Reserved1; 2192 bge_hostaddr etherStatsFragments; 2193 bge_hostaddr ifHCInUcastPkts; 2194 bge_hostaddr ifHCInMulticastPkts; 2195 bge_hostaddr ifHCInBroadcastPkts; 2196 bge_hostaddr dot3StatsFCSErrors; 2197 bge_hostaddr dot3StatsAlignmentErrors; 2198 bge_hostaddr xonPauseFramesReceived; 2199 bge_hostaddr xoffPauseFramesReceived; 2200 bge_hostaddr macControlFramesReceived; 2201 bge_hostaddr xoffStateEntered; 2202 bge_hostaddr dot3StatsFramesTooLong; 2203 bge_hostaddr etherStatsJabbers; 2204 bge_hostaddr etherStatsUndersizePkts; 2205 bge_hostaddr inRangeLengthError; 2206 bge_hostaddr outRangeLengthError; 2207 bge_hostaddr etherStatsPkts64Octets; 2208 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2209 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2210 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2211 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2212 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2213 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2214 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2215 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2216 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2217 2218 bge_hostaddr Unused1[37]; 2219 2220 /* Statistics maintained by Transmit MAC. */ 2221 bge_hostaddr ifHCOutOctets; 2222 bge_hostaddr Reserved2; 2223 bge_hostaddr etherStatsCollisions; 2224 bge_hostaddr outXonSent; 2225 bge_hostaddr outXoffSent; 2226 bge_hostaddr flowControlDone; 2227 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2228 bge_hostaddr dot3StatsSingleCollisionFrames; 2229 bge_hostaddr dot3StatsMultipleCollisionFrames; 2230 bge_hostaddr dot3StatsDeferredTransmissions; 2231 bge_hostaddr Reserved3; 2232 bge_hostaddr dot3StatsExcessiveCollisions; 2233 bge_hostaddr dot3StatsLateCollisions; 2234 bge_hostaddr dot3Collided2Times; 2235 bge_hostaddr dot3Collided3Times; 2236 bge_hostaddr dot3Collided4Times; 2237 bge_hostaddr dot3Collided5Times; 2238 bge_hostaddr dot3Collided6Times; 2239 bge_hostaddr dot3Collided7Times; 2240 bge_hostaddr dot3Collided8Times; 2241 bge_hostaddr dot3Collided9Times; 2242 bge_hostaddr dot3Collided10Times; 2243 bge_hostaddr dot3Collided11Times; 2244 bge_hostaddr dot3Collided12Times; 2245 bge_hostaddr dot3Collided13Times; 2246 bge_hostaddr dot3Collided14Times; 2247 bge_hostaddr dot3Collided15Times; 2248 bge_hostaddr ifHCOutUcastPkts; 2249 bge_hostaddr ifHCOutMulticastPkts; 2250 bge_hostaddr ifHCOutBroadcastPkts; 2251 bge_hostaddr dot3StatsCarrierSenseErrors; 2252 bge_hostaddr ifOutDiscards; 2253 bge_hostaddr ifOutErrors; 2254 2255 bge_hostaddr Unused2[31]; 2256 2257 /* Statistics maintained by Receive List Placement. */ 2258 bge_hostaddr COSIfHCInPkts[16]; 2259 bge_hostaddr COSFramesDroppedDueToFilters; 2260 bge_hostaddr nicDmaWriteQueueFull; 2261 bge_hostaddr nicDmaWriteHighPriQueueFull; 2262 bge_hostaddr nicNoMoreRxBDs; 2263 bge_hostaddr ifInDiscards; 2264 bge_hostaddr ifInErrors; 2265 bge_hostaddr nicRecvThresholdHit; 2266 2267 bge_hostaddr Unused3[9]; 2268 2269 /* Statistics maintained by Send Data Initiator. */ 2270 bge_hostaddr COSIfHCOutPkts[16]; 2271 bge_hostaddr nicDmaReadQueueFull; 2272 bge_hostaddr nicDmaReadHighPriQueueFull; 2273 bge_hostaddr nicSendDataCompQueueFull; 2274 2275 /* Statistics maintained by Host Coalescing. */ 2276 bge_hostaddr nicRingSetSendProdIndex; 2277 bge_hostaddr nicRingStatusUpdate; 2278 bge_hostaddr nicInterrupts; 2279 bge_hostaddr nicAvoidedInterrupts; 2280 bge_hostaddr nicSendThresholdHit; 2281 2282 u_int8_t Reserved4[320]; 2283 }; 2284 2285 /* 2286 * Tigon general information block. This resides in host memory 2287 * and contains the status counters, ring control blocks and 2288 * producer pointers. 2289 */ 2290 2291 struct bge_gib { 2292 struct bge_stats bge_stats; 2293 struct bge_rcb bge_tx_rcb[16]; 2294 struct bge_rcb bge_std_rx_rcb; 2295 struct bge_rcb bge_jumbo_rx_rcb; 2296 struct bge_rcb bge_mini_rx_rcb; 2297 struct bge_rcb bge_return_rcb; 2298 }; 2299 2300 /* 2301 * NOTE! On the Alpha, we have an alignment constraint. 2302 * The first thing in the packet is a 14-byte Ethernet header. 2303 * This means that the packet is misaligned. To compensate, 2304 * we actually offset the data 2 bytes into the cluster. This 2305 * alignes the packet after the Ethernet header at a 32-bit 2306 * boundary. 2307 */ 2308 2309 #define ETHER_ALIGN 2 2310 2311 #define BGE_FRAMELEN ETHER_MAX_LEN 2312 #define BGE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_CRC_LEN) 2313 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2314 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2315 #define BGE_PAGE_SIZE PAGE_SIZE 2316 #define BGE_MIN_FRAMELEN 60 2317 2318 /* 2319 * Vital product data and structures. 2320 */ 2321 #define BGE_VPD_FLAG 0x8000 2322 2323 /* VPD structures */ 2324 struct vpd_res { 2325 u_int8_t vr_id; 2326 u_int8_t vr_len; 2327 u_int8_t vr_pad; 2328 }; 2329 2330 struct vpd_key { 2331 char vk_key[2]; 2332 u_int8_t vk_len; 2333 }; 2334 2335 #define VPD_RES_ID 0x82 /* ID string */ 2336 #define VPD_RES_READ 0x90 /* start of read only area */ 2337 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2338 #define VPD_RES_END 0x78 /* end tag */ 2339 2340 /* Flags for phyflags in proplib. */ 2341 #define BGE_TXRING_VALID 0x00000001 2342 #define BGE_RXRING_VALID 0x00000002 2343 #define BGE_JUMBO_RXRING_VALID 0x00000004 2344 #define BGE_RX_ALIGNBUG 0x00000008 2345 #define BGE_NO_3LED 0x00000010 2346 #define BGE_PCIX 0x00000020 2347 #define BGE_PCIE 0x00000040 2348 #define BGE_NO_EEPROM 0x00000100 2349 #define BGE_JUMBO_CAPABLE 0x00000200 2350 #define BGE_10_100_ONLY 0x00000400 2351 #define BGE_PHY_FIBER_TBI 0x00000800 2352 #define BGE_PHY_FIBER_MII 0x00001000 2353 #define BGE_PHY_CRC_BUG 0x00002000 2354 #define BGE_PHY_ADC_BUG 0x00004000 2355 #define BGE_PHY_5704_A0_BUG 0x00008000 2356 #define BGE_PHY_JITTER_BUG 0x00010000 2357 #define BGE_PHY_BER_BUG 0x00020000 2358 #define BGE_PHY_ADJUST_TRIM 0x00040000 2359 #define BGE_NO_ETH_WIRE_SPEED 0x00080000 2360 #define BGE_IS_5788 0x00100000 2361 #define BGE_5705_PLUS 0x00200000 2362 #define BGE_5750_PLUS 0x00400000 2363 #define BGE_5755_PLUS 0x00800000 2364 #define BGE_5714_FAMILY 0x01000000 2365 #define BGE_5700_FAMILY 0x02000000 2366 #define BGE_TSO 0x04000000 2367
Indexes created Mon Sep 29 21:09:56 GMT 2025