if_bgereg.h revision 1.62
1 /* $NetBSD: if_bgereg.h,v 1.62 2013/03/13 09:44:20 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 #define BGE_PAGE_ZERO 0x00000000 66 #define BGE_PAGE_ZERO_END 0x000000FF 67 #define BGE_SEND_RING_RCB 0x00000100 68 #define BGE_SEND_RING_RCB_END 0x000001FF 69 #define BGE_RX_RETURN_RING_RCB 0x00000200 70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 71 #define BGE_STATS_BLOCK 0x00000300 72 #define BGE_STATS_BLOCK_END 0x00000AFF 73 #define BGE_STATUS_BLOCK 0x00000B00 74 #define BGE_STATUS_BLOCK_END 0x00000B4F 75 #define BGE_SOFTWARE_GENCOMM 0x00000B50 76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 78 #define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 79 #define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 80 #define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 81 #define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 82 #define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 83 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 84 #define BGE_UNMAPPED 0x00001000 85 #define BGE_UNMAPPED_END 0x00001FFF 86 #define BGE_DMA_DESCRIPTORS 0x00002000 87 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 88 #define BGE_SEND_RING_1_TO_4 0x00004000 89 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 90 91 /* Firmware interface */ 92 #define BGE_FW_DRV_ALIVE 0x00000001 93 #define BGE_FW_PAUSE 0x00000002 94 95 /* Mappings for internal memory configuration */ 96 #define BGE_STD_RX_RINGS 0x00006000 97 #define BGE_STD_RX_RINGS_END 0x00006FFF 98 #define BGE_JUMBO_RX_RINGS 0x00007000 99 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 100 #define BGE_BUFFPOOL_1 0x00008000 101 #define BGE_BUFFPOOL_1_END 0x0000FFFF 102 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 103 #define BGE_BUFFPOOL_2_END 0x00017FFF 104 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 105 #define BGE_BUFFPOOL_3_END 0x0001FFFF 106 107 /* Mappings for external SSRAM configurations */ 108 #define BGE_SEND_RING_5_TO_6 0x00006000 109 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 110 #define BGE_SEND_RING_7_TO_8 0x00007000 111 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 112 #define BGE_SEND_RING_9_TO_16 0x00008000 113 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 114 #define BGE_EXT_STD_RX_RINGS 0x0000C000 115 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 116 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 117 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 118 #define BGE_MINI_RX_RINGS 0x0000E000 119 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 120 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 121 #define BGE_AVAIL_REGION1_END 0x00017FFF 122 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 123 #define BGE_AVAIL_REGION2_END 0x0001FFFF 124 #define BGE_EXT_SSRAM 0x00020000 125 #define BGE_EXT_SSRAM_END 0x000FFFFF 126 127 128 /* 129 * BCM570x register offsets. These are memory mapped registers 130 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 131 * Each register must be accessed using 32 bit operations. 132 * 133 * All registers are accessed through a 32K shared memory block. 134 * The first group of registers are actually copies of the PCI 135 * configuration space registers. 136 */ 137 138 /* 139 * PCI registers defined in the PCI 2.2 spec. 140 */ 141 #define BGE_PCI_VID 0x00 142 #define BGE_PCI_DID 0x02 143 #define BGE_PCI_CMD 0x04 144 #define BGE_PCI_STS 0x06 145 #define BGE_PCI_REV 0x08 146 #define BGE_PCI_CLASS 0x09 147 #define BGE_PCI_CACHESZ 0x0C 148 #define BGE_PCI_LATTIMER 0x0D 149 #define BGE_PCI_HDRTYPE 0x0E 150 #define BGE_PCI_BIST 0x0F 151 #define BGE_PCI_BAR0 0x10 152 #define BGE_PCI_BAR1 0x14 153 #define BGE_PCI_SUBSYS 0x2C 154 #define BGE_PCI_SUBVID 0x2E 155 #define BGE_PCI_ROMBASE 0x30 156 #define BGE_PCI_CAPPTR 0x34 157 #define BGE_PCI_INTLINE 0x3C 158 #define BGE_PCI_INTPIN 0x3D 159 #define BGE_PCI_MINGNT 0x3E 160 #define BGE_PCI_MAXLAT 0x3F 161 #define BGE_PCI_PCIXCAP 0x40 162 #define BGE_PCI_NEXTPTR_PM 0x41 163 #define BGE_PCI_PCIX_CMD 0x42 164 #define BGE_PCI_PCIX_STS 0x44 165 #define BGE_PCI_PWRMGMT_CAPID 0x48 166 #define BGE_PCI_NEXTPTR_VPD 0x49 167 #define BGE_PCI_PWRMGMT_CAPS 0x4A 168 #define BGE_PCI_PWRMGMT_CMD 0x4C 169 #define BGE_PCI_PWRMGMT_STS 0x4D 170 #define BGE_PCI_PWRMGMT_DATA 0x4F 171 #define BGE_PCI_VPD_CAPID 0x50 172 #define BGE_PCI_NEXTPTR_MSI 0x51 173 #define BGE_PCI_VPD_ADDR 0x52 174 #define BGE_PCI_VPD_DATA 0x54 175 #define BGE_PCI_MSI_CAPID 0x58 176 #define BGE_PCI_NEXTPTR_NONE 0x59 177 #define BGE_PCI_MSI_CTL 0x5A 178 #define BGE_PCI_MSI_ADDR_HI 0x5C 179 #define BGE_PCI_MSI_ADDR_LO 0x60 180 #define BGE_PCI_MSI_DATA 0x64 181 182 /* 183 * PCI Express definitions 184 * According to 185 * PCI Express base specification, REV. 1.0a 186 */ 187 188 /* PCI Express device control, 16bits */ 189 #define BGE_PCIE_DEVCTL 0x08 190 #define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 191 #define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 192 #define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 193 #define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 194 #define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 195 #define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 196 #define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 197 198 /* PCI MSI. ??? */ 199 #define BGE_PCIE_CAPID_REG 0xD0 200 #define BGE_PCIE_CAPID 0x10 201 202 /* 203 * PCI registers specific to the BCM570x family. 204 */ 205 #define BGE_PCI_MISC_CTL 0x68 206 #define BGE_PCI_DMA_RW_CTL 0x6C 207 #define BGE_PCI_PCISTATE 0x70 208 #define BGE_PCI_CLKCTL 0x74 209 #define BGE_PCI_REG_BASEADDR 0x78 210 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 211 #define BGE_PCI_REG_DATA 0x80 212 #define BGE_PCI_MEMWIN_DATA 0x84 213 #define BGE_PCI_MODECTL 0x88 214 #define BGE_PCI_MISC_CFG 0x8C 215 #define BGE_PCI_MISC_LOCALCTL 0x90 216 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 217 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 218 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 219 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 220 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 221 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 222 #define BGE_PCI_ISR_MBX_HI 0xB0 223 #define BGE_PCI_ISR_MBX_LO 0xB4 224 #define BGE_PCI_PRODID_ASICREV 0xBC 225 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 226 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 227 228 #define BGE_PCI_UNKNOWN0 0xC4 229 /* XXX: 230 * Used in PCI-Express code for 575x chips. 231 * Should be replaced with checking for a PCI config-space 232 * capability for PCI-Express, and PCI-Express standard 233 * offsets into that capability block. 234 */ 235 #define BGE_PCI_CONF_DEV_CTRL 0xD8 236 #define BGE_PCI_CONF_DEV_STUS 0xDA 237 238 /* PCI Misc. Host control register */ 239 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 240 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 241 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 242 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 243 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 244 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 245 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 246 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 247 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 248 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 249 250 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 251 #if BYTE_ORDER == LITTLE_ENDIAN 252 #define BGE_DMA_SWAP_OPTIONS \ 253 BGE_MODECTL_WORDSWAP_NONFRAME| \ 254 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 255 #else 256 #define BGE_DMA_SWAP_OPTIONS \ 257 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 258 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 259 #endif 260 261 #define BGE_INIT \ 262 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 263 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 264 265 #define BGE_CHIPID_TIGON_I 0x4000 266 #define BGE_CHIPID_TIGON_II 0x6000 267 #define BGE_CHIPID_BCM5700_A0 0x7000 268 #define BGE_CHIPID_BCM5700_A1 0x7001 269 #define BGE_CHIPID_BCM5700_B0 0x7100 270 #define BGE_CHIPID_BCM5700_B1 0x7101 271 #define BGE_CHIPID_BCM5700_B2 0x7102 272 #define BGE_CHIPID_BCM5700_B3 0x7103 273 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 274 #define BGE_CHIPID_BCM5700_C0 0x7200 275 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 276 #define BGE_CHIPID_BCM5701_B0 0x0100 277 #define BGE_CHIPID_BCM5701_B2 0x0102 278 #define BGE_CHIPID_BCM5701_B5 0x0105 279 #define BGE_CHIPID_BCM5703_A0 0x1000 280 #define BGE_CHIPID_BCM5703_A1 0x1001 281 #define BGE_CHIPID_BCM5703_A2 0x1002 282 #define BGE_CHIPID_BCM5703_A3 0x1003 283 #define BGE_CHIPID_BCM5703_B0 0x1100 284 #define BGE_CHIPID_BCM5704_A0 0x2000 285 #define BGE_CHIPID_BCM5704_A1 0x2001 286 #define BGE_CHIPID_BCM5704_A2 0x2002 287 #define BGE_CHIPID_BCM5704_A3 0x2003 288 #define BGE_CHIPID_BCM5704_B0 0x2100 289 #define BGE_CHIPID_BCM5705_A0 0x3000 290 #define BGE_CHIPID_BCM5705_A1 0x3001 291 #define BGE_CHIPID_BCM5705_A2 0x3002 292 #define BGE_CHIPID_BCM5705_A3 0x3003 293 #define BGE_CHIPID_BCM5750_A0 0x4000 294 #define BGE_CHIPID_BCM5750_A1 0x4001 295 #define BGE_CHIPID_BCM5750_A3 0x4003 296 #define BGE_CHIPID_BCM5750_B0 0x4010 297 #define BGE_CHIPID_BCM5750_B1 0x4101 298 #define BGE_CHIPID_BCM5750_C0 0x4200 299 #define BGE_CHIPID_BCM5750_C1 0x4201 300 #define BGE_CHIPID_BCM5750_C2 0x4202 301 #define BGE_CHIPID_BCM5714_A0 0x5000 302 #define BGE_CHIPID_BCM5761_A0 0x5761000 303 #define BGE_CHIPID_BCM5761_A1 0x5761100 304 #define BGE_CHIPID_BCM5784_A0 0x5784000 305 #define BGE_CHIPID_BCM5784_A1 0x5784100 306 #define BGE_CHIPID_BCM5752_A0 0x6000 307 #define BGE_CHIPID_BCM5752_A1 0x6001 308 #define BGE_CHIPID_BCM5752_A2 0x6002 309 #define BGE_CHIPID_BCM5714_B0 0x8000 310 #define BGE_CHIPID_BCM5714_B3 0x8003 311 #define BGE_CHIPID_BCM5715_A0 0x9000 312 #define BGE_CHIPID_BCM5715_A1 0x9001 313 #define BGE_CHIPID_BCM5715_A3 0x9003 314 #define BGE_CHIPID_BCM5755_A0 0xa000 315 #define BGE_CHIPID_BCM5755_A1 0xa001 316 #define BGE_CHIPID_BCM5755_A2 0xa002 317 #define BGE_CHIPID_BCM5755_C0 0xa200 318 #define BGE_CHIPID_BCM5787_A0 0xb000 319 #define BGE_CHIPID_BCM5787_A1 0xb001 320 #define BGE_CHIPID_BCM5787_A2 0xb002 321 #define BGE_CHIPID_BCM5906_A0 0xc000 322 #define BGE_CHIPID_BCM5906_A1 0xc001 323 #define BGE_CHIPID_BCM5906_A2 0xc002 324 #define BGE_CHIPID_BCM57762 0x57766000 325 #define BGE_CHIPID_BCM57780_A0 0x57780000 326 #define BGE_CHIPID_BCM57780_A1 0x57780001 327 #define BGE_CHIPID_BCM5717_A0 0x05717000 328 #define BGE_CHIPID_BCM57765_A0 0x57785000 329 #define BGE_CHIPID_BCM57765_B0 0x57785100 330 331 /* shorthand one */ 332 #define BGE_ASICREV(x) ((x) >> 12) 333 #define BGE_ASICREV_BCM5700 0x07 334 #define BGE_ASICREV_BCM5701 0x00 335 #define BGE_ASICREV_BCM5703 0x01 336 #define BGE_ASICREV_BCM5704 0x02 337 #define BGE_ASICREV_BCM5705 0x03 338 #define BGE_ASICREV_BCM5750 0x04 339 #define BGE_ASICREV_BCM5714_A0 0x05 340 #define BGE_ASICREV_BCM5752 0x06 341 /* ASIC revision 0x07 is the original bcm5700 */ 342 #define BGE_ASICREV_BCM5780 0x08 343 #define BGE_ASICREV_BCM5714 0x09 344 #define BGE_ASICREV_BCM5755 0x0a 345 #define BGE_ASICREV_BCM5787 0x0b 346 #define BGE_ASICREV_BCM5906 0x0c 347 #define BGE_ASICREV_USE_PRODID_REG 0x0f 348 #define BGE_ASICREV_BCM5761 0x5761 349 #define BGE_ASICREV_BCM5784 0x5784 350 #define BGE_ASICREV_BCM5785 0x5785 351 #define BGE_ASICREV_BCM57780 0x57780 352 #define BGE_ASICREV_BCM5717 0x5717 353 #define BGE_ASICREV_BCM57765 0x57785 354 #define BGE_ASICREV_BCM57766 0x57766 355 356 /* chip revisions */ 357 #define BGE_CHIPREV(x) ((x) >> 8) 358 #define BGE_CHIPREV_5700_AX 0x70 359 #define BGE_CHIPREV_5700_BX 0x71 360 #define BGE_CHIPREV_5700_CX 0x72 361 #define BGE_CHIPREV_5701_AX 0x00 362 #define BGE_CHIPREV_5703_AX 0x10 363 #define BGE_CHIPREV_5704_AX 0x20 364 #define BGE_CHIPREV_5704_BX 0x21 365 #define BGE_CHIPREV_5750_AX 0x40 366 #define BGE_CHIPREV_5750_BX 0x41 367 #define BGE_CHIPREV_57765_AX 0x577650 368 369 /* PCI DMA Read/Write Control register */ 370 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 371 #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 372 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 373 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 374 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 375 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 376 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 377 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 378 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 379 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 380 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 381 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 382 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 383 384 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 385 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 386 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 387 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 388 389 #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 390 #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 391 392 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 393 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 394 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 395 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 396 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 397 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 398 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 399 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 400 401 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 402 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 403 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 404 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 405 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 406 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 407 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 408 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 409 410 /* 411 * PCI state register -- note, this register is read only 412 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 413 * register is set. 414 */ 415 #define BGE_PCISTATE_FORCE_RESET 0x00000001 416 #define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 417 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 418 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 419 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 420 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 421 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 422 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 423 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 424 425 /* 426 * The following bits in PCI state register are reserved. 427 * If we check that the register values reverts on reset, 428 * do not check these bits. On some 5704C (rev A3) and some 429 * Altima chips, these bits do not revert until much later 430 * in the bge driver's bge_reset() chip-reset state machine. 431 */ 432 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 433 434 /* 435 * PCI Clock Control register -- note, this register is read only 436 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 437 * register is set. 438 */ 439 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 440 #define BGE_PCICLOCKCTL_M66EN 0x00000080 441 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 442 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 443 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 444 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 445 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 446 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 447 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 448 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 449 450 /* 451 * High priority mailbox registers 452 * Each mailbox is 64-bits wide, though we only use the 453 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 454 * first. The NIC will load the mailbox after the lower 32 bit word 455 * has been updated. 456 */ 457 #define BGE_MBX_IRQ0_HI 0x0200 458 #define BGE_MBX_IRQ0_LO 0x0204 459 #define BGE_MBX_IRQ1_HI 0x0208 460 #define BGE_MBX_IRQ1_LO 0x020C 461 #define BGE_MBX_IRQ2_HI 0x0210 462 #define BGE_MBX_IRQ2_LO 0x0214 463 #define BGE_MBX_IRQ3_HI 0x0218 464 #define BGE_MBX_IRQ3_LO 0x021C 465 #define BGE_MBX_GEN0_HI 0x0220 466 #define BGE_MBX_GEN0_LO 0x0224 467 #define BGE_MBX_GEN1_HI 0x0228 468 #define BGE_MBX_GEN1_LO 0x022C 469 #define BGE_MBX_GEN2_HI 0x0230 470 #define BGE_MBX_GEN2_LO 0x0234 471 #define BGE_MBX_GEN3_HI 0x0228 472 #define BGE_MBX_GEN3_LO 0x022C 473 #define BGE_MBX_GEN4_HI 0x0240 474 #define BGE_MBX_GEN4_LO 0x0244 475 #define BGE_MBX_GEN5_HI 0x0248 476 #define BGE_MBX_GEN5_LO 0x024C 477 #define BGE_MBX_GEN6_HI 0x0250 478 #define BGE_MBX_GEN6_LO 0x0254 479 #define BGE_MBX_GEN7_HI 0x0258 480 #define BGE_MBX_GEN7_LO 0x025C 481 #define BGE_MBX_RELOAD_STATS_HI 0x0260 482 #define BGE_MBX_RELOAD_STATS_LO 0x0264 483 #define BGE_MBX_RX_STD_PROD_HI 0x0268 484 #define BGE_MBX_RX_STD_PROD_LO 0x026C 485 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 486 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 487 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 488 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 489 #define BGE_MBX_RX_CONS0_HI 0x0280 490 #define BGE_MBX_RX_CONS0_LO 0x0284 491 #define BGE_MBX_RX_CONS1_HI 0x0288 492 #define BGE_MBX_RX_CONS1_LO 0x028C 493 #define BGE_MBX_RX_CONS2_HI 0x0290 494 #define BGE_MBX_RX_CONS2_LO 0x0294 495 #define BGE_MBX_RX_CONS3_HI 0x0298 496 #define BGE_MBX_RX_CONS3_LO 0x029C 497 #define BGE_MBX_RX_CONS4_HI 0x02A0 498 #define BGE_MBX_RX_CONS4_LO 0x02A4 499 #define BGE_MBX_RX_CONS5_HI 0x02A8 500 #define BGE_MBX_RX_CONS5_LO 0x02AC 501 #define BGE_MBX_RX_CONS6_HI 0x02B0 502 #define BGE_MBX_RX_CONS6_LO 0x02B4 503 #define BGE_MBX_RX_CONS7_HI 0x02B8 504 #define BGE_MBX_RX_CONS7_LO 0x02BC 505 #define BGE_MBX_RX_CONS8_HI 0x02C0 506 #define BGE_MBX_RX_CONS8_LO 0x02C4 507 #define BGE_MBX_RX_CONS9_HI 0x02C8 508 #define BGE_MBX_RX_CONS9_LO 0x02CC 509 #define BGE_MBX_RX_CONS10_HI 0x02D0 510 #define BGE_MBX_RX_CONS10_LO 0x02D4 511 #define BGE_MBX_RX_CONS11_HI 0x02D8 512 #define BGE_MBX_RX_CONS11_LO 0x02DC 513 #define BGE_MBX_RX_CONS12_HI 0x02E0 514 #define BGE_MBX_RX_CONS12_LO 0x02E4 515 #define BGE_MBX_RX_CONS13_HI 0x02E8 516 #define BGE_MBX_RX_CONS13_LO 0x02EC 517 #define BGE_MBX_RX_CONS14_HI 0x02F0 518 #define BGE_MBX_RX_CONS14_LO 0x02F4 519 #define BGE_MBX_RX_CONS15_HI 0x02F8 520 #define BGE_MBX_RX_CONS15_LO 0x02FC 521 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 522 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 523 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 524 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 525 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 526 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 527 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 528 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 529 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 530 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 531 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 532 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 533 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 534 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 535 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 536 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 537 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 538 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 539 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 540 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 541 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 542 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 543 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 544 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 545 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 546 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 547 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 548 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 549 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 550 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 551 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 552 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 553 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 554 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 555 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 556 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 557 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 558 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 559 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 560 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 561 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 562 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 563 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 564 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 565 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 566 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 567 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 568 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 569 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 570 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 571 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 572 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 573 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 574 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 575 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 576 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 577 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 578 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 579 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 580 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 581 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 582 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 583 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 584 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 585 586 #define BGE_TX_RINGS_MAX 4 587 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 588 #define BGE_RX_RINGS_MAX 16 589 590 /* Ethernet MAC control registers */ 591 #define BGE_MAC_MODE 0x0400 592 #define BGE_MAC_STS 0x0404 593 #define BGE_MAC_EVT_ENB 0x0408 594 #define BGE_MAC_LED_CTL 0x040C 595 #define BGE_MAC_ADDR1_LO 0x0410 596 #define BGE_MAC_ADDR1_HI 0x0414 597 #define BGE_MAC_ADDR2_LO 0x0418 598 #define BGE_MAC_ADDR2_HI 0x041C 599 #define BGE_MAC_ADDR3_LO 0x0420 600 #define BGE_MAC_ADDR3_HI 0x0424 601 #define BGE_MAC_ADDR4_LO 0x0428 602 #define BGE_MAC_ADDR4_HI 0x042C 603 #define BGE_WOL_PATPTR 0x0430 604 #define BGE_WOL_PATCFG 0x0434 605 #define BGE_TX_RANDOM_BACKOFF 0x0438 606 #define BGE_RX_MTU 0x043C 607 #define BGE_GBIT_PCS_TEST 0x0440 608 #define BGE_TX_TBI_AUTONEG 0x0444 609 #define BGE_RX_TBI_AUTONEG 0x0448 610 #define BGE_MI_COMM 0x044C 611 #define BGE_MI_STS 0x0450 612 #define BGE_MI_MODE 0x0454 613 #define BGE_AUTOPOLL_STS 0x0458 614 #define BGE_TX_MODE 0x045C 615 #define BGE_TX_STS 0x0460 616 #define BGE_TX_LENGTHS 0x0464 617 #define BGE_RX_MODE 0x0468 618 #define BGE_RX_STS 0x046C 619 #define BGE_MAR0 0x0470 620 #define BGE_MAR1 0x0474 621 #define BGE_MAR2 0x0478 622 #define BGE_MAR3 0x047C 623 #define BGE_RX_BD_RULES_CTL0 0x0480 624 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 625 #define BGE_RX_BD_RULES_CTL1 0x0488 626 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 627 #define BGE_RX_BD_RULES_CTL2 0x0490 628 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 629 #define BGE_RX_BD_RULES_CTL3 0x0498 630 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 631 #define BGE_RX_BD_RULES_CTL4 0x04A0 632 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 633 #define BGE_RX_BD_RULES_CTL5 0x04A8 634 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 635 #define BGE_RX_BD_RULES_CTL6 0x04B0 636 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 637 #define BGE_RX_BD_RULES_CTL7 0x04B8 638 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 639 #define BGE_RX_BD_RULES_CTL8 0x04C0 640 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 641 #define BGE_RX_BD_RULES_CTL9 0x04C8 642 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 643 #define BGE_RX_BD_RULES_CTL10 0x04D0 644 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 645 #define BGE_RX_BD_RULES_CTL11 0x04D8 646 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 647 #define BGE_RX_BD_RULES_CTL12 0x04E0 648 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 649 #define BGE_RX_BD_RULES_CTL13 0x04E8 650 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 651 #define BGE_RX_BD_RULES_CTL14 0x04F0 652 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 653 #define BGE_RX_BD_RULES_CTL15 0x04F8 654 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 655 #define BGE_RX_RULES_CFG 0x0500 656 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 657 #define BGE_SERDES_CFG 0x0590 658 #define BGE_SGDIG_CFG 0x05B0 659 #define BGE_SGDIG_STS 0x05B4 660 #define BGE_MAC_STATS 0x0800 661 662 /* Ethernet MAC Mode register */ 663 #define BGE_MACMODE_RESET 0x00000001 664 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 665 #define BGE_MACMODE_PORTMODE 0x0000000C 666 #define BGE_MACMODE_LOOPBACK 0x00000010 667 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 668 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 669 #define BGE_MACMODE_MAX_DEFER 0x00000200 670 #define BGE_MACMODE_LINK_POLARITY 0x00000400 671 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 672 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 673 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 674 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 675 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 676 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 677 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 678 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 679 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 680 #define BGE_MACMODE_MIP_ENB 0x00100000 681 #define BGE_MACMODE_TXDMA_ENB 0x00200000 682 #define BGE_MACMODE_RXDMA_ENB 0x00400000 683 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 684 685 #define BGE_PORTMODE_NONE 0x00000000 686 #define BGE_PORTMODE_MII 0x00000004 687 #define BGE_PORTMODE_GMII 0x00000008 688 #define BGE_PORTMODE_TBI 0x0000000C 689 690 /* MAC Status register */ 691 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 692 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 693 #define BGE_MACSTAT_RX_CFG 0x00000004 694 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 695 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 696 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 697 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 698 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 699 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 700 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 701 #define BGE_MACSTAT_ODI_ERROR 0x02000000 702 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 703 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 704 705 /* MAC Event Enable Register */ 706 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 707 #define BGE_EVTENB_LINK_CHANGED 0x00001000 708 #define BGE_EVTENB_MI_COMPLETE 0x00400000 709 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 710 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 711 #define BGE_EVTENB_ODI_ERROR 0x02000000 712 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 713 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 714 715 /* LED Control Register */ 716 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 717 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 718 #define BGE_LEDCTL_100MBPS_LED 0x00000004 719 #define BGE_LEDCTL_10MBPS_LED 0x00000008 720 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 721 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 722 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 723 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 724 #define BGE_LEDCTL_100MBPS_STS 0x00000100 725 #define BGE_LEDCTL_10MBPS_STS 0x00000200 726 #define BGE_LEDCTL_TRADLED_STS 0x00000400 727 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 728 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 729 730 /* TX backoff seed register */ 731 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 732 733 /* Autopoll status register */ 734 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 735 736 /* Transmit MAC mode register */ 737 #define BGE_TXMODE_RESET 0x00000001 738 #define BGE_TXMODE_ENABLE 0x00000002 739 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 740 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 741 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 742 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 743 744 /* Transmit MAC status register */ 745 #define BGE_TXSTAT_RX_XOFFED 0x00000001 746 #define BGE_TXSTAT_SENT_XOFF 0x00000002 747 #define BGE_TXSTAT_SENT_XON 0x00000004 748 #define BGE_TXSTAT_LINK_UP 0x00000008 749 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 750 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 751 752 /* Transmit MAC lengths register */ 753 #define BGE_TXLEN_SLOTTIME 0x000000FF 754 #define BGE_TXLEN_IPG 0x00000F00 755 #define BGE_TXLEN_CRS 0x00003000 756 757 /* Receive MAC mode register */ 758 #define BGE_RXMODE_RESET 0x00000001 759 #define BGE_RXMODE_ENABLE 0x00000002 760 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 761 #define BGE_RXMODE_RX_GIANTS 0x00000020 762 #define BGE_RXMODE_RX_RUNTS 0x00000040 763 #define BGE_RXMODE_8022_LENCHECK 0x00000080 764 #define BGE_RXMODE_RX_PROMISC 0x00000100 765 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 766 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 767 768 /* Receive MAC status register */ 769 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 770 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 771 #define BGE_RXSTAT_RCVD_XON 0x00000004 772 773 /* Receive Rules Control register */ 774 #define BGE_RXRULECTL_OFFSET 0x000000FF 775 #define BGE_RXRULECTL_CLASS 0x00001F00 776 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 777 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 778 #define BGE_RXRULECTL_MAP 0x01000000 779 #define BGE_RXRULECTL_DISCARD 0x02000000 780 #define BGE_RXRULECTL_MASK 0x04000000 781 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 782 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 783 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 784 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 785 786 /* Receive Rules Mask register */ 787 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 788 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 789 790 /* SGDIG config (not documented) */ 791 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 792 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 793 #define BGE_SGDIGCFG_SEND 0x40000000 794 #define BGE_SGDIGCFG_AUTO 0x80000000 795 796 /* SGDIG status (not documented) */ 797 #define BGE_SGDIGSTS_DONE 0x00000002 798 799 /* MI communication register */ 800 #define BGE_MICOMM_DATA 0x0000FFFF 801 #define BGE_MICOMM_REG 0x001F0000 802 #define BGE_MICOMM_PHY 0x03E00000 803 #define BGE_MICOMM_CMD 0x0C000000 804 #define BGE_MICOMM_READFAIL 0x10000000 805 #define BGE_MICOMM_BUSY 0x20000000 806 807 #define BGE_MIREG(x) ((x & 0x1F) << 16) 808 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 809 #define BGE_MICMD_WRITE 0x04000000 810 #define BGE_MICMD_READ 0x08000000 811 812 /* MI status register */ 813 #define BGE_MISTS_LINK 0x00000001 814 #define BGE_MISTS_10MBPS 0x00000002 815 816 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 817 #define BGE_MIMODE_AUTOPOLL 0x00000010 818 #define BGE_MIMODE_CLKCNT 0x001F0000 819 820 821 /* 822 * Send data initiator control registers. 823 */ 824 #define BGE_SDI_MODE 0x0C00 825 #define BGE_SDI_STATUS 0x0C04 826 #define BGE_SDI_STATS_CTL 0x0C08 827 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 828 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 829 #define BGE_ISO_PKT_TX 0x0C20 830 #define BGE_LOCSTATS_COS0 0x0C80 831 #define BGE_LOCSTATS_COS1 0x0C84 832 #define BGE_LOCSTATS_COS2 0x0C88 833 #define BGE_LOCSTATS_COS3 0x0C8C 834 #define BGE_LOCSTATS_COS4 0x0C90 835 #define BGE_LOCSTATS_COS5 0x0C84 836 #define BGE_LOCSTATS_COS6 0x0C98 837 #define BGE_LOCSTATS_COS7 0x0C9C 838 #define BGE_LOCSTATS_COS8 0x0CA0 839 #define BGE_LOCSTATS_COS9 0x0CA4 840 #define BGE_LOCSTATS_COS10 0x0CA8 841 #define BGE_LOCSTATS_COS11 0x0CAC 842 #define BGE_LOCSTATS_COS12 0x0CB0 843 #define BGE_LOCSTATS_COS13 0x0CB4 844 #define BGE_LOCSTATS_COS14 0x0CB8 845 #define BGE_LOCSTATS_COS15 0x0CBC 846 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 847 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 848 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 849 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 850 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 851 #define BGE_LOCSTATS_IRQS 0x0CD4 852 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 853 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 854 855 /* Send Data Initiator mode register */ 856 #define BGE_SDIMODE_RESET 0x00000001 857 #define BGE_SDIMODE_ENABLE 0x00000002 858 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 859 860 /* Send Data Initiator stats register */ 861 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 862 863 /* Send Data Initiator stats control register */ 864 #define BGE_SDISTATSCTL_ENABLE 0x00000001 865 #define BGE_SDISTATSCTL_FASTER 0x00000002 866 #define BGE_SDISTATSCTL_CLEAR 0x00000004 867 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 868 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 869 870 /* 871 * Send Data Completion Control registers 872 */ 873 #define BGE_SDC_MODE 0x1000 874 #define BGE_SDC_STATUS 0x1004 875 876 /* Send Data completion mode register */ 877 #define BGE_SDCMODE_RESET 0x00000001 878 #define BGE_SDCMODE_ENABLE 0x00000002 879 #define BGE_SDCMODE_ATTN 0x00000004 880 #define BGE_SDCMODE_CDELAY 0x00000010 881 882 /* Send Data completion status register */ 883 #define BGE_SDCSTAT_ATTN 0x00000004 884 885 /* 886 * Send BD Ring Selector Control registers 887 */ 888 #define BGE_SRS_MODE 0x1400 889 #define BGE_SRS_STATUS 0x1404 890 #define BGE_SRS_HWDIAG 0x1408 891 #define BGE_SRS_LOC_NIC_CONS0 0x1440 892 #define BGE_SRS_LOC_NIC_CONS1 0x1444 893 #define BGE_SRS_LOC_NIC_CONS2 0x1448 894 #define BGE_SRS_LOC_NIC_CONS3 0x144C 895 #define BGE_SRS_LOC_NIC_CONS4 0x1450 896 #define BGE_SRS_LOC_NIC_CONS5 0x1454 897 #define BGE_SRS_LOC_NIC_CONS6 0x1458 898 #define BGE_SRS_LOC_NIC_CONS7 0x145C 899 #define BGE_SRS_LOC_NIC_CONS8 0x1460 900 #define BGE_SRS_LOC_NIC_CONS9 0x1464 901 #define BGE_SRS_LOC_NIC_CONS10 0x1468 902 #define BGE_SRS_LOC_NIC_CONS11 0x146C 903 #define BGE_SRS_LOC_NIC_CONS12 0x1470 904 #define BGE_SRS_LOC_NIC_CONS13 0x1474 905 #define BGE_SRS_LOC_NIC_CONS14 0x1478 906 #define BGE_SRS_LOC_NIC_CONS15 0x147C 907 908 /* Send BD Ring Selector Mode register */ 909 #define BGE_SRSMODE_RESET 0x00000001 910 #define BGE_SRSMODE_ENABLE 0x00000002 911 #define BGE_SRSMODE_ATTN 0x00000004 912 913 /* Send BD Ring Selector Status register */ 914 #define BGE_SRSSTAT_ERROR 0x00000004 915 916 /* Send BD Ring Selector HW Diagnostics register */ 917 #define BGE_SRSHWDIAG_STATE 0x0000000F 918 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 919 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 920 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 921 922 /* 923 * Send BD Initiator Selector Control registers 924 */ 925 #define BGE_SBDI_MODE 0x1800 926 #define BGE_SBDI_STATUS 0x1804 927 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 928 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 929 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 930 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 931 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 932 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 933 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 934 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 935 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 936 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 937 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 938 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 939 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 940 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 941 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 942 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 943 944 /* Send BD Initiator Mode register */ 945 #define BGE_SBDIMODE_RESET 0x00000001 946 #define BGE_SBDIMODE_ENABLE 0x00000002 947 #define BGE_SBDIMODE_ATTN 0x00000004 948 949 /* Send BD Initiator Status register */ 950 #define BGE_SBDISTAT_ERROR 0x00000004 951 952 /* 953 * Send BD Completion Control registers 954 */ 955 #define BGE_SBDC_MODE 0x1C00 956 #define BGE_SBDC_STATUS 0x1C04 957 958 /* Send BD Completion Control Mode register */ 959 #define BGE_SBDCMODE_RESET 0x00000001 960 #define BGE_SBDCMODE_ENABLE 0x00000002 961 #define BGE_SBDCMODE_ATTN 0x00000004 962 963 /* Send BD Completion Control Status register */ 964 #define BGE_SBDCSTAT_ATTN 0x00000004 965 966 /* 967 * Receive List Placement Control registers 968 */ 969 #define BGE_RXLP_MODE 0x2000 970 #define BGE_RXLP_STATUS 0x2004 971 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 972 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 973 #define BGE_RXLP_CFG 0x2010 974 #define BGE_RXLP_STATS_CTL 0x2014 975 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 976 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 977 #define BGE_RXLP_HEAD0 0x2100 978 #define BGE_RXLP_TAIL0 0x2104 979 #define BGE_RXLP_COUNT0 0x2108 980 #define BGE_RXLP_HEAD1 0x2110 981 #define BGE_RXLP_TAIL1 0x2114 982 #define BGE_RXLP_COUNT1 0x2118 983 #define BGE_RXLP_HEAD2 0x2120 984 #define BGE_RXLP_TAIL2 0x2124 985 #define BGE_RXLP_COUNT2 0x2128 986 #define BGE_RXLP_HEAD3 0x2130 987 #define BGE_RXLP_TAIL3 0x2134 988 #define BGE_RXLP_COUNT3 0x2138 989 #define BGE_RXLP_HEAD4 0x2140 990 #define BGE_RXLP_TAIL4 0x2144 991 #define BGE_RXLP_COUNT4 0x2148 992 #define BGE_RXLP_HEAD5 0x2150 993 #define BGE_RXLP_TAIL5 0x2154 994 #define BGE_RXLP_COUNT5 0x2158 995 #define BGE_RXLP_HEAD6 0x2160 996 #define BGE_RXLP_TAIL6 0x2164 997 #define BGE_RXLP_COUNT6 0x2168 998 #define BGE_RXLP_HEAD7 0x2170 999 #define BGE_RXLP_TAIL7 0x2174 1000 #define BGE_RXLP_COUNT7 0x2178 1001 #define BGE_RXLP_HEAD8 0x2180 1002 #define BGE_RXLP_TAIL8 0x2184 1003 #define BGE_RXLP_COUNT8 0x2188 1004 #define BGE_RXLP_HEAD9 0x2190 1005 #define BGE_RXLP_TAIL9 0x2194 1006 #define BGE_RXLP_COUNT9 0x2198 1007 #define BGE_RXLP_HEAD10 0x21A0 1008 #define BGE_RXLP_TAIL10 0x21A4 1009 #define BGE_RXLP_COUNT10 0x21A8 1010 #define BGE_RXLP_HEAD11 0x21B0 1011 #define BGE_RXLP_TAIL11 0x21B4 1012 #define BGE_RXLP_COUNT11 0x21B8 1013 #define BGE_RXLP_HEAD12 0x21C0 1014 #define BGE_RXLP_TAIL12 0x21C4 1015 #define BGE_RXLP_COUNT12 0x21C8 1016 #define BGE_RXLP_HEAD13 0x21D0 1017 #define BGE_RXLP_TAIL13 0x21D4 1018 #define BGE_RXLP_COUNT13 0x21D8 1019 #define BGE_RXLP_HEAD14 0x21E0 1020 #define BGE_RXLP_TAIL14 0x21E4 1021 #define BGE_RXLP_COUNT14 0x21E8 1022 #define BGE_RXLP_HEAD15 0x21F0 1023 #define BGE_RXLP_TAIL15 0x21F4 1024 #define BGE_RXLP_COUNT15 0x21F8 1025 #define BGE_RXLP_LOCSTAT_COS0 0x2200 1026 #define BGE_RXLP_LOCSTAT_COS1 0x2204 1027 #define BGE_RXLP_LOCSTAT_COS2 0x2208 1028 #define BGE_RXLP_LOCSTAT_COS3 0x220C 1029 #define BGE_RXLP_LOCSTAT_COS4 0x2210 1030 #define BGE_RXLP_LOCSTAT_COS5 0x2214 1031 #define BGE_RXLP_LOCSTAT_COS6 0x2218 1032 #define BGE_RXLP_LOCSTAT_COS7 0x221C 1033 #define BGE_RXLP_LOCSTAT_COS8 0x2220 1034 #define BGE_RXLP_LOCSTAT_COS9 0x2224 1035 #define BGE_RXLP_LOCSTAT_COS10 0x2228 1036 #define BGE_RXLP_LOCSTAT_COS11 0x222C 1037 #define BGE_RXLP_LOCSTAT_COS12 0x2230 1038 #define BGE_RXLP_LOCSTAT_COS13 0x2234 1039 #define BGE_RXLP_LOCSTAT_COS14 0x2238 1040 #define BGE_RXLP_LOCSTAT_COS15 0x223C 1041 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1042 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1043 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1044 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1045 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1046 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1047 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1048 1049 1050 /* Receive List Placement mode register */ 1051 #define BGE_RXLPMODE_RESET 0x00000001 1052 #define BGE_RXLPMODE_ENABLE 0x00000002 1053 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1054 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1055 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1056 1057 /* Receive List Placement Status register */ 1058 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1059 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1060 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1061 1062 /* 1063 * Receive Data and Receive BD Initiator Control Registers 1064 */ 1065 #define BGE_RDBDI_MODE 0x2400 1066 #define BGE_RDBDI_STATUS 0x2404 1067 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1068 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1069 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1070 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1071 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1072 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1073 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1074 #define BGE_RX_STD_RCB_NICADDR 0x245C 1075 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1076 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1077 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1078 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1079 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1080 #define BGE_RDBDI_STD_RX_CONS 0x2474 1081 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1082 #define BGE_RDBDI_RETURN_PROD0 0x2480 1083 #define BGE_RDBDI_RETURN_PROD1 0x2484 1084 #define BGE_RDBDI_RETURN_PROD2 0x2488 1085 #define BGE_RDBDI_RETURN_PROD3 0x248C 1086 #define BGE_RDBDI_RETURN_PROD4 0x2490 1087 #define BGE_RDBDI_RETURN_PROD5 0x2494 1088 #define BGE_RDBDI_RETURN_PROD6 0x2498 1089 #define BGE_RDBDI_RETURN_PROD7 0x249C 1090 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1091 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1092 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1093 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1094 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1095 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1096 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1097 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1098 #define BGE_RDBDI_HWDIAG 0x24C0 1099 1100 1101 /* Receive Data and Receive BD Initiator Mode register */ 1102 #define BGE_RDBDIMODE_RESET 0x00000001 1103 #define BGE_RDBDIMODE_ENABLE 0x00000002 1104 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1105 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1106 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1107 1108 /* Receive Data and Receive BD Initiator Status register */ 1109 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1110 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1111 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1112 1113 1114 /* 1115 * Receive Data Completion Control registers 1116 */ 1117 #define BGE_RDC_MODE 0x2800 1118 1119 /* Receive Data Completion Mode register */ 1120 #define BGE_RDCMODE_RESET 0x00000001 1121 #define BGE_RDCMODE_ENABLE 0x00000002 1122 #define BGE_RDCMODE_ATTN 0x00000004 1123 1124 /* 1125 * Receive BD Initiator Control registers 1126 */ 1127 #define BGE_RBDI_MODE 0x2C00 1128 #define BGE_RBDI_STATUS 0x2C04 1129 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1130 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1131 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1132 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1133 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1134 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1135 1136 #define BGE_STD_REPL_LWM 0x2D00 1137 #define BGE_JUMBO_REPL_LWM 0x2D04 1138 1139 /* Receive BD Initiator Mode register */ 1140 #define BGE_RBDIMODE_RESET 0x00000001 1141 #define BGE_RBDIMODE_ENABLE 0x00000002 1142 #define BGE_RBDIMODE_ATTN 0x00000004 1143 1144 /* Receive BD Initiator Status register */ 1145 #define BGE_RBDISTAT_ATTN 0x00000004 1146 1147 /* 1148 * Receive BD Completion Control registers 1149 */ 1150 #define BGE_RBDC_MODE 0x3000 1151 #define BGE_RBDC_STATUS 0x3004 1152 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1153 #define BGE_RBDC_STD_BD_PROD 0x300C 1154 #define BGE_RBDC_MINI_BD_PROD 0x3010 1155 1156 /* Receive BD completion mode register */ 1157 #define BGE_RBDCMODE_RESET 0x00000001 1158 #define BGE_RBDCMODE_ENABLE 0x00000002 1159 #define BGE_RBDCMODE_ATTN 0x00000004 1160 1161 /* Receive BD completion status register */ 1162 #define BGE_RBDCSTAT_ERROR 0x00000004 1163 1164 /* 1165 * Receive List Selector Control registers 1166 */ 1167 #define BGE_RXLS_MODE 0x3400 1168 #define BGE_RXLS_STATUS 0x3404 1169 1170 /* Receive List Selector Mode register */ 1171 #define BGE_RXLSMODE_RESET 0x00000001 1172 #define BGE_RXLSMODE_ENABLE 0x00000002 1173 #define BGE_RXLSMODE_ATTN 0x00000004 1174 1175 /* Receive List Selector Status register */ 1176 #define BGE_RXLSSTAT_ERROR 0x00000004 1177 1178 /* Central Power Management Unit (CPMU) register */ 1179 #define BGE_CPMU_CTRL 0x3600 1180 #define BGE_CPMU_LSPD_10MB_CLK 0x3604 1181 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1182 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1183 #define BGE_CPMU_HST_ACC 0x361C 1184 #define BGE_CPMU_CLCK_ORIDE 0x3624 1185 #define BGE_CPMU_CLCK_STAT 0x3630 1186 #define BGE_CPMU_MUTEX_REQ 0x365C 1187 #define BGE_CPMU_MUTEX_GNT 0x3660 1188 #define BGE_CPMU_PHY_STRAP 0x3664 1189 #define BGE_CPMU_PADRNG_CTL 0x3668 1190 1191 /* CPMU Control register */ 1192 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1193 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1194 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1195 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1196 1197 /* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1198 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1199 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1200 1201 /* Link Speed 1000MB Power Mode Clock Policy register */ 1202 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1203 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1204 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1205 1206 /* Link Aware Power Mode Clock Policy register */ 1207 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1208 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1209 1210 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1211 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1212 1213 /* Clock Speed Override Policy register */ 1214 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1215 1216 /* CPMU Clock Status register */ 1217 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1218 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1219 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1220 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1221 1222 /* CPMU Mutex Request register */ 1223 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1224 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1225 1226 /* CPMU GPHY Strap register */ 1227 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1228 1229 /* CPMU Padring Control register */ 1230 #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1231 1232 /* 1233 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1234 */ 1235 #define BGE_MBCF_MODE 0x3800 1236 #define BGE_MBCF_STATUS 0x3804 1237 1238 /* Mbuf Cluster Free mode register */ 1239 #define BGE_MBCFMODE_RESET 0x00000001 1240 #define BGE_MBCFMODE_ENABLE 0x00000002 1241 #define BGE_MBCFMODE_ATTN 0x00000004 1242 1243 /* Mbuf Cluster Free status register */ 1244 #define BGE_MBCFSTAT_ERROR 0x00000004 1245 1246 /* 1247 * Host Coalescing Control registers 1248 */ 1249 #define BGE_HCC_MODE 0x3C00 1250 #define BGE_HCC_STATUS 0x3C04 1251 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1252 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1253 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1254 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1255 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1256 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1257 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1258 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1259 #define BGE_HCC_STATS_TICKS 0x3C28 1260 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1261 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1262 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1263 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1264 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1265 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1266 #define BGE_FLOW_ATTN 0x3C48 1267 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1268 #define BGE_HCC_STD_BD_CONS 0x3C54 1269 #define BGE_HCC_MINI_BD_CONS 0x3C58 1270 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1271 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1272 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1273 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1274 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1275 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1276 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1277 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1278 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1279 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1280 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1281 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1282 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1283 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1284 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1285 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1286 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1287 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1288 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1289 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1290 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1291 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1292 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1293 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1294 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1295 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1296 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1297 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1298 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1299 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1300 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1301 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1302 1303 1304 /* Host coalescing mode register */ 1305 #define BGE_HCCMODE_RESET 0x00000001 1306 #define BGE_HCCMODE_ENABLE 0x00000002 1307 #define BGE_HCCMODE_ATTN 0x00000004 1308 #define BGE_HCCMODE_COAL_NOW 0x00000008 1309 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1310 #define BGE_HCCMODE_64BYTE 0x00000080 1311 #define BGE_HCCMODE_32BYTE 0x00000100 1312 #define BGE_HCCMODE_CLRTICK_RXBD 0x00000200 1313 #define BGE_HCCMODE_CLRTICK_TXBD 0x00000400 1314 #define BGE_HCCMODE_NOINT_ON_NOW 0x00000800 1315 #define BGE_HCCMODE_NOINT_ON_FORCE 0x00001000 1316 1317 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1318 1319 #define BGE_STATBLKSZ_FULL 0x00000000 1320 #define BGE_STATBLKSZ_64BYTE 0x00000080 1321 #define BGE_STATBLKSZ_32BYTE 0x00000100 1322 1323 /* Host coalescing status register */ 1324 #define BGE_HCCSTAT_ERROR 0x00000004 1325 1326 /* Flow attention register */ 1327 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1328 #define BGE_FLOWATTN_MEMARB 0x00000080 1329 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1330 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1331 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1332 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1333 #define BGE_FLOWATTN_RDBDI 0x00080000 1334 #define BGE_FLOWATTN_RXLS 0x00100000 1335 #define BGE_FLOWATTN_RXLP 0x00200000 1336 #define BGE_FLOWATTN_RBDC 0x00400000 1337 #define BGE_FLOWATTN_RBDI 0x00800000 1338 #define BGE_FLOWATTN_SDC 0x08000000 1339 #define BGE_FLOWATTN_SDI 0x10000000 1340 #define BGE_FLOWATTN_SRS 0x20000000 1341 #define BGE_FLOWATTN_SBDC 0x40000000 1342 #define BGE_FLOWATTN_SBDI 0x80000000 1343 1344 /* 1345 * Memory arbiter registers 1346 */ 1347 #define BGE_MARB_MODE 0x4000 1348 #define BGE_MARB_STATUS 0x4004 1349 #define BGE_MARB_TRAPADDR_HI 0x4008 1350 #define BGE_MARB_TRAPADDR_LO 0x400C 1351 1352 /* Memory arbiter mode register */ 1353 #define BGE_MARBMODE_RESET 0x00000001 1354 #define BGE_MARBMODE_ENABLE 0x00000002 1355 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1356 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1357 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1358 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1359 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1360 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1361 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1362 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1363 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1364 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1365 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1366 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1367 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1368 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1369 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1370 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1371 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1372 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1373 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1374 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1375 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1376 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1377 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1378 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1379 1380 /* Memory arbiter status register */ 1381 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1382 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1383 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1384 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1385 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1386 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1387 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1388 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1389 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1390 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1391 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1392 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1393 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1394 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1395 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1396 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1397 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1398 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1399 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1400 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1401 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1402 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1403 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1404 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1405 1406 /* 1407 * Buffer manager control registers 1408 */ 1409 #define BGE_BMAN_MODE 0x4400 1410 #define BGE_BMAN_STATUS 0x4404 1411 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1412 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1413 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1414 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1415 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1416 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1417 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1418 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1419 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1420 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1421 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1422 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1423 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1424 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1425 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1426 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1427 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1428 #define BGE_BMAN_HWDIAG_1 0x444C 1429 #define BGE_BMAN_HWDIAG_2 0x4450 1430 #define BGE_BMAN_HWDIAG_3 0x4454 1431 1432 /* Buffer manager mode register */ 1433 #define BGE_BMANMODE_RESET 0x00000001 1434 #define BGE_BMANMODE_ENABLE 0x00000002 1435 #define BGE_BMANMODE_ATTN 0x00000004 1436 #define BGE_BMANMODE_TESTMODE 0x00000008 1437 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1438 1439 /* Buffer manager status register */ 1440 #define BGE_BMANSTAT_ERRO 0x00000004 1441 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1442 1443 1444 /* 1445 * Read DMA Control registers 1446 */ 1447 #define BGE_RDMA_MODE 0x4800 1448 #define BGE_RDMA_STATUS 0x4804 1449 1450 /* Read DMA mode register */ 1451 #define BGE_RDMAMODE_RESET 0x00000001 1452 #define BGE_RDMAMODE_ENABLE 0x00000002 1453 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1454 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1455 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1456 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1457 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1458 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1459 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1460 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1461 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1462 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1463 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1464 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1465 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1466 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1467 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1468 #define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1469 1470 /* Read DMA status register */ 1471 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1472 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1473 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1474 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1475 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1476 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1477 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1478 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1479 1480 /* 1481 * Write DMA control registers 1482 */ 1483 #define BGE_WDMA_MODE 0x4C00 1484 #define BGE_WDMA_STATUS 0x4C04 1485 1486 /* Write DMA mode register */ 1487 #define BGE_WDMAMODE_RESET 0x00000001 1488 #define BGE_WDMAMODE_ENABLE 0x00000002 1489 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1490 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1491 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1492 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1493 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1494 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1495 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1496 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1497 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1498 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1499 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1500 1501 /* Write DMA status register */ 1502 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1503 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1504 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1505 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1506 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1507 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1508 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1509 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1510 1511 1512 /* 1513 * RX CPU registers 1514 */ 1515 #define BGE_RXCPU_MODE 0x5000 1516 #define BGE_RXCPU_STATUS 0x5004 1517 #define BGE_RXCPU_PC 0x501C 1518 1519 /* RX CPU mode register */ 1520 #define BGE_RXCPUMODE_RESET 0x00000001 1521 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1522 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1523 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1524 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1525 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1526 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1527 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1528 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1529 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1530 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1531 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1532 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1533 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1534 1535 /* RX CPU status register */ 1536 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1537 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1538 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1539 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1540 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1541 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1542 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1543 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1544 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1545 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1546 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1547 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1548 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1549 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1550 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1551 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1552 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1553 1554 /* 1555 * V? CPU registers 1556 */ 1557 #define BGE_VCPU_STATUS 0x5100 1558 #define BGE_VCPU_EXT_CTRL 0x6890 1559 1560 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1561 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1562 1563 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1564 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1565 1566 /* 1567 * TX CPU registers 1568 */ 1569 #define BGE_TXCPU_MODE 0x5400 1570 #define BGE_TXCPU_STATUS 0x5404 1571 #define BGE_TXCPU_PC 0x541C 1572 1573 /* TX CPU mode register */ 1574 #define BGE_TXCPUMODE_RESET 0x00000001 1575 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1576 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1577 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1578 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1579 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1580 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1581 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1582 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1583 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1584 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1585 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1586 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1587 1588 /* TX CPU status register */ 1589 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1590 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1591 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1592 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1593 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1594 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1595 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1596 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1597 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1598 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1599 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1600 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1601 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1602 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1603 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1604 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1605 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1606 1607 1608 /* 1609 * Low priority mailbox registers 1610 */ 1611 #define BGE_LPMBX_IRQ0_HI 0x5800 1612 #define BGE_LPMBX_IRQ0_LO 0x5804 1613 #define BGE_LPMBX_IRQ1_HI 0x5808 1614 #define BGE_LPMBX_IRQ1_LO 0x580C 1615 #define BGE_LPMBX_IRQ2_HI 0x5810 1616 #define BGE_LPMBX_IRQ2_LO 0x5814 1617 #define BGE_LPMBX_IRQ3_HI 0x5818 1618 #define BGE_LPMBX_IRQ3_LO 0x581C 1619 #define BGE_LPMBX_GEN0_HI 0x5820 1620 #define BGE_LPMBX_GEN0_LO 0x5824 1621 #define BGE_LPMBX_GEN1_HI 0x5828 1622 #define BGE_LPMBX_GEN1_LO 0x582C 1623 #define BGE_LPMBX_GEN2_HI 0x5830 1624 #define BGE_LPMBX_GEN2_LO 0x5834 1625 #define BGE_LPMBX_GEN3_HI 0x5828 1626 #define BGE_LPMBX_GEN3_LO 0x582C 1627 #define BGE_LPMBX_GEN4_HI 0x5840 1628 #define BGE_LPMBX_GEN4_LO 0x5844 1629 #define BGE_LPMBX_GEN5_HI 0x5848 1630 #define BGE_LPMBX_GEN5_LO 0x584C 1631 #define BGE_LPMBX_GEN6_HI 0x5850 1632 #define BGE_LPMBX_GEN6_LO 0x5854 1633 #define BGE_LPMBX_GEN7_HI 0x5858 1634 #define BGE_LPMBX_GEN7_LO 0x585C 1635 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1636 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1637 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1638 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1639 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1640 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1641 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1642 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1643 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1644 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1645 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1646 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1647 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1648 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1649 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1650 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1651 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1652 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1653 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1654 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1655 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1656 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1657 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1658 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1659 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1660 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1661 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1662 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1663 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1664 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1665 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1666 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1667 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1668 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1669 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1670 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1671 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1672 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1673 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1674 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1675 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1676 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1677 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1678 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1679 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1680 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1681 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1682 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1683 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1684 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1685 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1686 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1687 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1688 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1689 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1690 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1691 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1692 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1693 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1694 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1695 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1696 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1697 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1698 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1699 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1700 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1701 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1702 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1703 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1704 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1705 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1706 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1707 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1708 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1709 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1710 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1711 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1712 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1713 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1714 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1715 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1716 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1717 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1718 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1719 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1720 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1721 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1722 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1723 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1724 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1725 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1726 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1727 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1728 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1729 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1730 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1731 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1732 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1733 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1734 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1735 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1736 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1737 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1738 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1739 1740 /* 1741 * Flow throw Queue reset register 1742 */ 1743 #define BGE_FTQ_RESET 0x5C00 1744 1745 #define BGE_FTQRESET_DMAREAD 0x00000002 1746 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1747 #define BGE_FTQRESET_DMADONE 0x00000010 1748 #define BGE_FTQRESET_SBDC 0x00000020 1749 #define BGE_FTQRESET_SDI 0x00000040 1750 #define BGE_FTQRESET_WDMA 0x00000080 1751 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1752 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1753 #define BGE_FTQRESET_SDC 0x00000400 1754 #define BGE_FTQRESET_HCC 0x00000800 1755 #define BGE_FTQRESET_TXFIFO 0x00001000 1756 #define BGE_FTQRESET_MBC 0x00002000 1757 #define BGE_FTQRESET_RBDC 0x00004000 1758 #define BGE_FTQRESET_RXLP 0x00008000 1759 #define BGE_FTQRESET_RDBDI 0x00010000 1760 #define BGE_FTQRESET_RDC 0x00020000 1761 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1762 1763 /* 1764 * Message Signaled Interrupt registers 1765 */ 1766 #define BGE_MSI_MODE 0x6000 1767 #define BGE_MSI_STATUS 0x6004 1768 #define BGE_MSI_FIFOACCESS 0x6008 1769 1770 /* MSI mode register */ 1771 #define BGE_MSIMODE_RESET 0x00000001 1772 #define BGE_MSIMODE_ENABLE 0x00000002 1773 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1774 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1775 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1776 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1777 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1778 1779 /* MSI status register */ 1780 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1781 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1782 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1783 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1784 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1785 1786 1787 /* 1788 * DMA Completion registers 1789 */ 1790 #define BGE_DMAC_MODE 0x6400 1791 1792 /* DMA Completion mode register */ 1793 #define BGE_DMACMODE_RESET 0x00000001 1794 #define BGE_DMACMODE_ENABLE 0x00000002 1795 1796 1797 /* 1798 * General control registers. 1799 */ 1800 #define BGE_MODE_CTL 0x6800 1801 #define BGE_MISC_CFG 0x6804 1802 #define BGE_MISC_LOCAL_CTL 0x6808 1803 #define BGE_CPU_EVENT 0x6810 1804 #define BGE_EE_ADDR 0x6838 1805 #define BGE_EE_DATA 0x683C 1806 #define BGE_EE_CTL 0x6840 1807 #define BGE_MDI_CTL 0x6844 1808 #define BGE_EE_DELAY 0x6848 1809 #define BGE_FASTBOOT_PC 0x6894 1810 /* 1811 * XXX: Those names are made up as I have no documentation about it; 1812 * I only know it is only used in the PCI-Express case. 1813 */ 1814 #define BGE_PCIE_CTL0 0x7c00 1815 #define BGE_PCIE_CTL1 0x7e2c 1816 1817 /* 1818 * NVRAM Control registers 1819 */ 1820 #define BGE_NVRAM_CMD 0x7000 1821 #define BGE_NVRAM_STAT 0x7004 1822 #define BGE_NVRAM_WRDATA 0x7008 1823 #define BGE_NVRAM_ADDR 0x700c 1824 #define BGE_NVRAM_RDDATA 0x7010 1825 #define BGE_NVRAM_CFG1 0x7014 1826 #define BGE_NVRAM_CFG2 0x7018 1827 #define BGE_NVRAM_CFG3 0x701c 1828 #define BGE_NVRAM_SWARB 0x7020 1829 #define BGE_NVRAM_ACCESS 0x7024 1830 #define BGE_NVRAM_WRITE1 0x7028 1831 1832 #define BGE_NVRAMCMD_RESET 0x00000001 1833 #define BGE_NVRAMCMD_DONE 0x00000008 1834 #define BGE_NVRAMCMD_START 0x00000010 1835 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1836 #define BGE_NVRAMCMD_ERASE 0x00000040 1837 #define BGE_NVRAMCMD_FIRST 0x00000080 1838 #define BGE_NVRAMCMD_LAST 0x00000100 1839 1840 #define BGE_NVRAM_READCMD \ 1841 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1842 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1843 #define BGE_NVRAM_WRITECMD \ 1844 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1845 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1846 1847 #define BGE_NVRAMSWARB_SET0 0x00000001 1848 #define BGE_NVRAMSWARB_SET1 0x00000002 1849 #define BGE_NVRAMSWARB_SET2 0x00000003 1850 #define BGE_NVRAMSWARB_SET3 0x00000004 1851 #define BGE_NVRAMSWARB_CLR0 0x00000010 1852 #define BGE_NVRAMSWARB_CLR1 0x00000020 1853 #define BGE_NVRAMSWARB_CLR2 0x00000040 1854 #define BGE_NVRAMSWARB_CLR3 0x00000080 1855 #define BGE_NVRAMSWARB_GNT0 0x00000100 1856 #define BGE_NVRAMSWARB_GNT1 0x00000200 1857 #define BGE_NVRAMSWARB_GNT2 0x00000400 1858 #define BGE_NVRAMSWARB_GNT3 0x00000800 1859 #define BGE_NVRAMSWARB_REQ0 0x00001000 1860 #define BGE_NVRAMSWARB_REQ1 0x00002000 1861 #define BGE_NVRAMSWARB_REQ2 0x00004000 1862 #define BGE_NVRAMSWARB_REQ3 0x00008000 1863 1864 #define BGE_NVRAMACC_ENABLE 0x00000001 1865 #define BGE_NVRAMACC_WRENABLE 0x00000002 1866 1867 /* 1868 * TLP Control Register 1869 * Applicable to BCM5721 and BCM5751 only 1870 */ 1871 #define BGE_TLP_CONTROL_REG 0x7c00 1872 #define BGE_TLP_FTSMAX 0x000c 1873 #define BGE_TLP_FTSMAX_MSK 0x000000ff 1874 #define BGE_TLP_FTSMAX_VAL 0x0000002c 1875 #define BGE_TLP_PHYCTL1 0x0004 1876 #define BGE_TLP_PHYCTL1_EN_L1PLLPD 0x00001000 1877 #define BGE_TLP_PHYCTL5 0x0014 1878 #define BGE_TLP_PHYCTL5_DIS_L2CLKREQ 0x80000000 1879 #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1880 1881 /* 1882 * PHY Test Control Register 1883 * Applicable to BCM5721 and BCM5751 only 1884 */ 1885 #define BGE_PHY_TEST_CTRL_REG 0x7e2c 1886 #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1887 #define BGE_PHY_PCIE_LTASS_MODE 0x0040 1888 1889 /* Mode control register */ 1890 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1891 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1892 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1893 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1894 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1895 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1896 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1897 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1898 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1899 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1900 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1901 #define BGE_MODECTL_STACKUP 0x00010000 1902 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1903 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1904 #define BGE_MODECTL_PCIE_TLPADDR1 0x00400000 1905 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1906 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1907 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1908 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1909 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1910 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1911 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1912 #define BGE_MODECTL_PCIE_TLPADDR0 0x20000000 1913 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1914 #define BGE_MODECTL_PCIE_TLPADDR2 0x80000000 1915 #define BGE_MODECTL_PCIE_TLPADDRMASK (BGE_MODECTL_PCIE_TLPADDR2 | \ 1916 BGE_MODECTL_PCIE_TLPADDR1 | \ 1917 BGE_MODECTL_PCIE_TLPADDR0) 1918 1919 /* Misc. config register */ 1920 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1921 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1922 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1923 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1924 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 1925 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1926 #define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 1927 #define BGE_MISCCFG_GRC_RESET_DISABLE 0x20000000 1928 1929 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1930 1931 /* Misc. Local Control */ 1932 #define BGE_MLC_INTR_STATE 0x00000001 1933 #define BGE_MLC_INTR_CLR 0x00000002 1934 #define BGE_MLC_INTR_SET 0x00000004 1935 #define BGE_MLC_INTR_ONATTN 0x00000008 1936 #define BGE_MLC_MISCIO_IN0 0x00000100 1937 #define BGE_MLC_MISCIO_IN1 0x00000200 1938 #define BGE_MLC_MISCIO_IN2 0x00000400 1939 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1940 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1941 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1942 #define BGE_MLC_MISCIO_OUT0 0x00004000 1943 #define BGE_MLC_MISCIO_OUT1 0x00008000 1944 #define BGE_MLC_MISCIO_OUT2 0x00010000 1945 #define BGE_MLC_EXTRAM_ENB 0x00020000 1946 #define BGE_MLC_SRAM_SIZE 0x001C0000 1947 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1948 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1949 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1950 #define BGE_MLC_AUTO_EEPROM 0x01000000 1951 1952 #define BGE_SSRAMSIZE_256KB 0x00000000 1953 #define BGE_SSRAMSIZE_512KB 0x00040000 1954 #define BGE_SSRAMSIZE_1MB 0x00080000 1955 #define BGE_SSRAMSIZE_2MB 0x000C0000 1956 #define BGE_SSRAMSIZE_4MB 0x00100000 1957 #define BGE_SSRAMSIZE_8MB 0x00140000 1958 #define BGE_SSRAMSIZE_16M 0x00180000 1959 1960 /* EEPROM address register */ 1961 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1962 #define BGE_EEADDR_HALFCLK 0x01FF0000 1963 #define BGE_EEADDR_START 0x02000000 1964 #define BGE_EEADDR_DEVID 0x1C000000 1965 #define BGE_EEADDR_RESET 0x20000000 1966 #define BGE_EEADDR_DONE 0x40000000 1967 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1968 1969 #define BGE_EEDEVID(x) ((x & 7) << 26) 1970 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1971 #define BGE_HALFCLK_384SCL 0x60 1972 #define BGE_EE_READCMD \ 1973 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1974 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1975 #define BGE_EE_WRCMD \ 1976 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1977 BGE_EEADDR_START|BGE_EEADDR_DONE) 1978 1979 /* EEPROM Control register */ 1980 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1981 #define BGE_EECTL_CLKOUT 0x00000002 1982 #define BGE_EECTL_CLKIN 0x00000004 1983 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1984 #define BGE_EECTL_DATAOUT 0x00000010 1985 #define BGE_EECTL_DATAIN 0x00000020 1986 1987 /* MDI (MII/GMII) access register */ 1988 #define BGE_MDI_DATA 0x00000001 1989 #define BGE_MDI_DIR 0x00000002 1990 #define BGE_MDI_SEL 0x00000004 1991 #define BGE_MDI_CLK 0x00000008 1992 1993 #define BGE_MEMWIN_START 0x00008000 1994 #define BGE_MEMWIN_END 0x0000FFFF 1995 1996 1997 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 1998 do { \ 1999 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2000 (0xFFFF0000 & x)); \ 2001 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2002 } while(0) 2003 2004 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 2005 do { \ 2006 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2007 (0xFFFF0000 & x)); \ 2008 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2009 } while(0) 2010 2011 /* 2012 * This magic number is used to prevent PXE restart when we 2013 * issue a software reset. We write this magic number to the 2014 * firmware mailbox at 0xB50 in order to prevent the PXE boot 2015 * code from running. 2016 */ 2017 #define BGE_MAGIC_NUMBER 0x4B657654 2018 2019 typedef struct { 2020 volatile u_int32_t bge_addr_hi; 2021 volatile u_int32_t bge_addr_lo; 2022 } bge_hostaddr; 2023 2024 /* Ring control block structure */ 2025 struct bge_rcb { 2026 bge_hostaddr bge_hostaddr; 2027 volatile u_int32_t bge_maxlen_flags; /* two 16-bit fields */ 2028 volatile u_int32_t bge_nicaddr; 2029 }; 2030 2031 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2032 2033 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2034 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 2035 2036 struct bge_tx_bd { 2037 bge_hostaddr bge_addr; 2038 #if BYTE_ORDER == BIG_ENDIAN 2039 volatile u_int16_t bge_len; 2040 volatile u_int16_t bge_flags; 2041 volatile u_int16_t bge_rsvd; 2042 volatile u_int16_t bge_vlan_tag; 2043 #else 2044 volatile u_int16_t bge_flags; 2045 volatile u_int16_t bge_len; 2046 volatile u_int16_t bge_vlan_tag; 2047 volatile u_int16_t bge_rsvd; 2048 #endif 2049 }; 2050 2051 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2052 #define BGE_TXBDFLAG_IP_CSUM 0x0002 2053 #define BGE_TXBDFLAG_END 0x0004 2054 #define BGE_TXBDFLAG_IP_FRAG 0x0008 2055 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2056 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 2057 #define BGE_TXBDFLAG_COAL_NOW 0x0080 2058 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2059 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2060 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2061 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2062 #define BGE_TXBDFLAG_NO_CRC 0x8000 2063 2064 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 2065 BGE_SEND_RING_1_TO_4 + \ 2066 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2067 2068 struct bge_rx_bd { 2069 bge_hostaddr bge_addr; 2070 #if BYTE_ORDER == BIG_ENDIAN 2071 volatile u_int16_t bge_idx; 2072 volatile u_int16_t bge_len; 2073 volatile u_int16_t bge_type; 2074 volatile u_int16_t bge_flags; 2075 volatile u_int16_t bge_ip_csum; 2076 volatile u_int16_t bge_tcp_udp_csum; 2077 volatile u_int16_t bge_error_flag; 2078 volatile u_int16_t bge_vlan_tag; 2079 #else 2080 volatile u_int16_t bge_len; 2081 volatile u_int16_t bge_idx; 2082 volatile u_int16_t bge_flags; 2083 volatile u_int16_t bge_type; 2084 volatile u_int16_t bge_tcp_udp_csum; 2085 volatile u_int16_t bge_ip_csum; 2086 volatile u_int16_t bge_vlan_tag; 2087 volatile u_int16_t bge_error_flag; 2088 #endif 2089 volatile u_int32_t bge_rsvd; 2090 volatile u_int32_t bge_opaque; 2091 }; 2092 2093 #define BGE_RXBDFLAG_END 0x0004 2094 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 2095 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 2096 #define BGE_RXBDFLAG_ERROR 0x0400 2097 #define BGE_RXBDFLAG_MINI_RING 0x0800 2098 #define BGE_RXBDFLAG_IP_CSUM 0x1000 2099 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2100 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2101 2102 #define BGE_RXERRFLAG_BAD_CRC 0x0001 2103 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 2104 #define BGE_RXERRFLAG_LINK_LOST 0x0004 2105 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2106 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 2107 #define BGE_RXERRFLAG_RUNT 0x0020 2108 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2109 #define BGE_RXERRFLAG_GIANT 0x0080 2110 2111 struct bge_sts_idx { 2112 #if BYTE_ORDER == BIG_ENDIAN 2113 volatile u_int16_t bge_tx_cons_idx; 2114 volatile u_int16_t bge_rx_prod_idx; 2115 #else 2116 volatile u_int16_t bge_rx_prod_idx; 2117 volatile u_int16_t bge_tx_cons_idx; 2118 #endif 2119 }; 2120 2121 struct bge_status_block { 2122 volatile u_int32_t bge_status; 2123 volatile u_int32_t bge_rsvd0; 2124 #if BYTE_ORDER == BIG_ENDIAN 2125 volatile u_int16_t bge_rx_std_cons_idx; 2126 volatile u_int16_t bge_rx_jumbo_cons_idx; 2127 volatile u_int16_t bge_rsvd1; 2128 volatile u_int16_t bge_rx_mini_cons_idx; 2129 #else 2130 volatile u_int16_t bge_rx_jumbo_cons_idx; 2131 volatile u_int16_t bge_rx_std_cons_idx; 2132 volatile u_int16_t bge_rx_mini_cons_idx; 2133 volatile u_int16_t bge_rsvd1; 2134 #endif 2135 struct bge_sts_idx bge_idx[16]; 2136 }; 2137 2138 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2139 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2140 2141 #define BGE_STATFLAG_UPDATED 0x00000001 2142 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2143 #define BGE_STATFLAG_ERROR 0x00000004 2144 2145 2146 /* 2147 * Broadcom Vendor ID 2148 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2149 * even though they're now manufactured by Broadcom) 2150 */ 2151 #define BCOM_VENDORID 0x14E4 2152 #define BCOM_DEVICEID_BCM5700 0x1644 2153 #define BCOM_DEVICEID_BCM5701 0x1645 2154 #define BCOM_DEVICEID_BCM5789 0x169d 2155 2156 /* 2157 * Alteon AceNIC PCI vendor/device ID. 2158 */ 2159 #define ALT_VENDORID 0x12AE 2160 #define ALT_DEVICEID_ACENIC 0x0001 2161 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 2162 #define ALT_DEVICEID_BCM5700 0x0003 2163 #define ALT_DEVICEID_BCM5701 0x0004 2164 2165 /* 2166 * 3Com 3c985 PCI vendor/device ID. 2167 */ 2168 #define TC_VENDORID 0x10B7 2169 #define TC_DEVICEID_3C985 0x0001 2170 #define TC_DEVICEID_3C996 0x0003 2171 2172 /* 2173 * SysKonnect PCI vendor ID 2174 */ 2175 #define SK_VENDORID 0x1148 2176 #define SK_DEVICEID_ALTIMA 0x4400 2177 #define SK_SUBSYSID_9D21 0x4421 2178 #define SK_SUBSYSID_9D41 0x4441 2179 2180 /* 2181 * Altima PCI vendor/device ID. 2182 */ 2183 #define ALTIMA_VENDORID 0x173b 2184 #define ALTIMA_DEVICE_AC1000 0x03e8 2185 2186 /* 2187 * Offset of MAC address inside EEPROM. 2188 */ 2189 #define BGE_EE_MAC_OFFSET 0x7C 2190 #define BGE_EE_MAC_OFFSET_5906 0x10 2191 #define BGE_EE_HWCFG_OFFSET 0xC8 2192 2193 #define BGE_HWCFG_VOLTAGE 0x00000003 2194 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2195 #define BGE_HWCFG_MEDIA 0x00000030 2196 #define BGE_HWCFG_ASF 0x00000080 2197 2198 #define BGE_VOLTAGE_1POINT3 0x00000000 2199 #define BGE_VOLTAGE_1POINT8 0x00000001 2200 2201 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2202 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2203 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2204 2205 #define BGE_MEDIA_UNSPEC 0x00000000 2206 #define BGE_MEDIA_COPPER 0x00000010 2207 #define BGE_MEDIA_FIBER 0x00000020 2208 2209 #define BGE_PCI_READ_CMD 0x06000000 2210 #define BGE_PCI_WRITE_CMD 0x70000000 2211 2212 #define BGE_TICKS_PER_SEC 1000000 2213 2214 /* 2215 * Ring size constants. 2216 */ 2217 #define BGE_EVENT_RING_CNT 256 2218 #define BGE_CMD_RING_CNT 64 2219 #define BGE_STD_RX_RING_CNT 512 2220 #define BGE_JUMBO_RX_RING_CNT 256 2221 #define BGE_MINI_RX_RING_CNT 1024 2222 #define BGE_RETURN_RING_CNT 1024 2223 #define BGE_RETURN_RING_CNT_5705 512 2224 2225 /* 2226 * Possible TX ring sizes. 2227 */ 2228 #define BGE_TX_RING_CNT_128 128 2229 #define BGE_TX_RING_BASE_128 0x3800 2230 2231 #define BGE_TX_RING_CNT_256 256 2232 #define BGE_TX_RING_BASE_256 0x3000 2233 2234 #define BGE_TX_RING_CNT_512 512 2235 #define BGE_TX_RING_BASE_512 0x2000 2236 2237 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2238 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2239 2240 /* 2241 * Tigon III statistics counters. 2242 */ 2243 2244 /* Stats counters access through registers */ 2245 struct bge_mac_stats_regs { 2246 u_int32_t ifHCOutOctets; 2247 u_int32_t Reserved0; 2248 u_int32_t etherStatsCollisions; 2249 u_int32_t outXonSent; 2250 u_int32_t outXoffSent; 2251 u_int32_t Reserved1; 2252 u_int32_t dot3StatsInternalMacTransmitErrors; 2253 u_int32_t dot3StatsSingleCollisionFrames; 2254 u_int32_t dot3StatsMultipleCollisionFrames; 2255 u_int32_t dot3StatsDeferredTransmissions; 2256 u_int32_t Reserved2; 2257 u_int32_t dot3StatsExcessiveCollisions; 2258 u_int32_t dot3StatsLateCollisions; 2259 u_int32_t Reserved3[14]; 2260 u_int32_t ifHCOutUcastPkts; 2261 u_int32_t ifHCOutMulticastPkts; 2262 u_int32_t ifHCOutBroadcastPkts; 2263 u_int32_t Reserved4[2]; 2264 u_int32_t ifHCInOctets; 2265 u_int32_t Reserved5; 2266 u_int32_t etherStatsFragments; 2267 u_int32_t ifHCInUcastPkts; 2268 u_int32_t ifHCInMulticastPkts; 2269 u_int32_t ifHCInBroadcastPkts; 2270 u_int32_t dot3StatsFCSErrors; 2271 u_int32_t dot3StatsAlignmentErrors; 2272 u_int32_t xonPauseFramesReceived; 2273 u_int32_t xoffPauseFramesReceived; 2274 u_int32_t macControlFramesReceived; 2275 u_int32_t xoffStateEntered; 2276 u_int32_t dot3StatsFramesTooLong; 2277 u_int32_t etherStatsJabbers; 2278 u_int32_t etherStatsUndersizePkts; 2279 }; 2280 2281 struct bge_stats { 2282 u_int8_t Reserved0[256]; 2283 2284 /* Statistics maintained by Receive MAC. */ 2285 bge_hostaddr ifHCInOctets; 2286 bge_hostaddr Reserved1; 2287 bge_hostaddr etherStatsFragments; 2288 bge_hostaddr ifHCInUcastPkts; 2289 bge_hostaddr ifHCInMulticastPkts; 2290 bge_hostaddr ifHCInBroadcastPkts; 2291 bge_hostaddr dot3StatsFCSErrors; 2292 bge_hostaddr dot3StatsAlignmentErrors; 2293 bge_hostaddr xonPauseFramesReceived; 2294 bge_hostaddr xoffPauseFramesReceived; 2295 bge_hostaddr macControlFramesReceived; 2296 bge_hostaddr xoffStateEntered; 2297 bge_hostaddr dot3StatsFramesTooLong; 2298 bge_hostaddr etherStatsJabbers; 2299 bge_hostaddr etherStatsUndersizePkts; 2300 bge_hostaddr inRangeLengthError; 2301 bge_hostaddr outRangeLengthError; 2302 bge_hostaddr etherStatsPkts64Octets; 2303 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2304 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2305 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2306 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2307 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2308 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2309 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2310 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2311 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2312 2313 bge_hostaddr Unused1[37]; 2314 2315 /* Statistics maintained by Transmit MAC. */ 2316 bge_hostaddr ifHCOutOctets; 2317 bge_hostaddr Reserved2; 2318 bge_hostaddr etherStatsCollisions; 2319 bge_hostaddr outXonSent; 2320 bge_hostaddr outXoffSent; 2321 bge_hostaddr flowControlDone; 2322 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2323 bge_hostaddr dot3StatsSingleCollisionFrames; 2324 bge_hostaddr dot3StatsMultipleCollisionFrames; 2325 bge_hostaddr dot3StatsDeferredTransmissions; 2326 bge_hostaddr Reserved3; 2327 bge_hostaddr dot3StatsExcessiveCollisions; 2328 bge_hostaddr dot3StatsLateCollisions; 2329 bge_hostaddr dot3Collided2Times; 2330 bge_hostaddr dot3Collided3Times; 2331 bge_hostaddr dot3Collided4Times; 2332 bge_hostaddr dot3Collided5Times; 2333 bge_hostaddr dot3Collided6Times; 2334 bge_hostaddr dot3Collided7Times; 2335 bge_hostaddr dot3Collided8Times; 2336 bge_hostaddr dot3Collided9Times; 2337 bge_hostaddr dot3Collided10Times; 2338 bge_hostaddr dot3Collided11Times; 2339 bge_hostaddr dot3Collided12Times; 2340 bge_hostaddr dot3Collided13Times; 2341 bge_hostaddr dot3Collided14Times; 2342 bge_hostaddr dot3Collided15Times; 2343 bge_hostaddr ifHCOutUcastPkts; 2344 bge_hostaddr ifHCOutMulticastPkts; 2345 bge_hostaddr ifHCOutBroadcastPkts; 2346 bge_hostaddr dot3StatsCarrierSenseErrors; 2347 bge_hostaddr ifOutDiscards; 2348 bge_hostaddr ifOutErrors; 2349 2350 bge_hostaddr Unused2[31]; 2351 2352 /* Statistics maintained by Receive List Placement. */ 2353 bge_hostaddr COSIfHCInPkts[16]; 2354 bge_hostaddr COSFramesDroppedDueToFilters; 2355 bge_hostaddr nicDmaWriteQueueFull; 2356 bge_hostaddr nicDmaWriteHighPriQueueFull; 2357 bge_hostaddr nicNoMoreRxBDs; 2358 bge_hostaddr ifInDiscards; 2359 bge_hostaddr ifInErrors; 2360 bge_hostaddr nicRecvThresholdHit; 2361 2362 bge_hostaddr Unused3[9]; 2363 2364 /* Statistics maintained by Send Data Initiator. */ 2365 bge_hostaddr COSIfHCOutPkts[16]; 2366 bge_hostaddr nicDmaReadQueueFull; 2367 bge_hostaddr nicDmaReadHighPriQueueFull; 2368 bge_hostaddr nicSendDataCompQueueFull; 2369 2370 /* Statistics maintained by Host Coalescing. */ 2371 bge_hostaddr nicRingSetSendProdIndex; 2372 bge_hostaddr nicRingStatusUpdate; 2373 bge_hostaddr nicInterrupts; 2374 bge_hostaddr nicAvoidedInterrupts; 2375 bge_hostaddr nicSendThresholdHit; 2376 2377 u_int8_t Reserved4[320]; 2378 }; 2379 2380 /* 2381 * Tigon general information block. This resides in host memory 2382 * and contains the status counters, ring control blocks and 2383 * producer pointers. 2384 */ 2385 2386 struct bge_gib { 2387 struct bge_stats bge_stats; 2388 struct bge_rcb bge_tx_rcb[16]; 2389 struct bge_rcb bge_std_rx_rcb; 2390 struct bge_rcb bge_jumbo_rx_rcb; 2391 struct bge_rcb bge_mini_rx_rcb; 2392 struct bge_rcb bge_return_rcb; 2393 }; 2394 2395 /* 2396 * NOTE! On the Alpha, we have an alignment constraint. 2397 * The first thing in the packet is a 14-byte Ethernet header. 2398 * This means that the packet is misaligned. To compensate, 2399 * we actually offset the data 2 bytes into the cluster. This 2400 * alignes the packet after the Ethernet header at a 32-bit 2401 * boundary. 2402 */ 2403 2404 #define ETHER_ALIGN 2 2405 2406 #define BGE_FRAMELEN ETHER_MAX_LEN 2407 #define BGE_MAX_FRAMELEN 1536 2408 #define BGE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO 2409 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2410 #define BGE_PAGE_SIZE PAGE_SIZE 2411 #define BGE_MIN_FRAMELEN 60 2412 2413 /* 2414 * Vital product data and structures. 2415 */ 2416 #define BGE_VPD_FLAG 0x8000 2417 2418 /* VPD structures */ 2419 struct vpd_res { 2420 u_int8_t vr_id; 2421 u_int8_t vr_len; 2422 u_int8_t vr_pad; 2423 }; 2424 2425 struct vpd_key { 2426 char vk_key[2]; 2427 u_int8_t vk_len; 2428 }; 2429 2430 #define VPD_RES_ID 0x82 /* ID string */ 2431 #define VPD_RES_READ 0x90 /* start of read only area */ 2432 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2433 #define VPD_RES_END 0x78 /* end tag */ 2434 2435 /* Flags for phyflags in proplib. */ 2436 #define BGE_TXRING_VALID 0x00000001 2437 #define BGE_RXRING_VALID 0x00000002 2438 #define BGE_JUMBO_RXRING_VALID 0x00000004 2439 #define BGE_RX_ALIGNBUG 0x00000008 2440 #define BGE_NO_3LED 0x00000010 2441 #define BGE_PCIX 0x00000020 2442 #define BGE_PCIE 0x00000040 2443 #define BGE_NO_EEPROM 0x00000100 2444 #define BGE_JUMBO_CAPABLE 0x00000200 2445 #define BGE_10_100_ONLY 0x00000400 2446 #define BGE_PHY_FIBER_TBI 0x00000800 2447 #define BGE_PHY_FIBER_MII 0x00001000 2448 #define BGE_PHY_CRC_BUG 0x00002000 2449 #define BGE_PHY_ADC_BUG 0x00004000 2450 #define BGE_PHY_5704_A0_BUG 0x00008000 2451 #define BGE_PHY_JITTER_BUG 0x00010000 2452 #define BGE_PHY_BER_BUG 0x00020000 2453 #define BGE_PHY_ADJUST_TRIM 0x00040000 2454 #define BGE_NO_ETH_WIRE_SPEED 0x00080000 2455 #define BGE_IS_5788 0x00100000 2456 #define BGE_5705_PLUS 0x00200000 2457 #define BGE_575X_PLUS 0x00400000 2458 #define BGE_5755_PLUS 0x00800000 2459 #define BGE_5714_FAMILY 0x01000000 2460 #define BGE_5700_FAMILY 0x02000000 2461 #define BGE_5717_PLUS 0x04000000 2462 #define BGE_57765_PLUS 0x08000000 2463 #define BGE_CPMU_PRESENT 0x20000000 2464 #define BGE_TSO 0x80000000 2465
Indexes created Sat Sep 27 14:09:57 GMT 2025